DOCSLIB.ORG

A Formal Approach to Memory Access Optimization: Data Layout, Reorganization, and Near-Data Processing

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text

Load more

A Formal Approach to Memory Access Optimization: Data Layout, Reorganization, and Near-Data Processing Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical and Computer Engineering BERKIN AKIN B.S., Electrical and Electronics Engineering, Middle East Technical University M.S., Electrical and Computer Engineering, Carnegie Mellon University Carnegie Mellon University Pittsburgh, PA, USA July 2015 Copyright © 2015 Berkin Akın Abstract The memory system is a major bottleneck in achieving high performance and energy efficiency for various processing platforms. This thesis aims to improve memory performance and energy ef- ficiency of data intensive applications through a two-pronged approach which combines a formal representation framework and a hardware substrate that can efficiently reorganize data in mem- ory. The proposed formal framework enables representing and systematically manipulating data layout formats, address mapping schemes, and memory access patterns through permutations to exploit the locality and parallelism in memory. Driven by the implications from the formal framework, this thesis presents the HAMLeT architecture for highly-concurrent, energy-efficient and low-overhead data reorganization performed completely in memory. Although data reorganization simply relo- cates data in memory, it is costly on conventional systems mainly due to inefficient access patterns, limited data reuse, and roundtrip data traversal throughout the memory hierarchy. HAMLeT pur- sues a near-data processing approach exploiting the 3D-stacked DRAM technology. Integrated in the logic layer, interfaced directly to the local controllers, it takes advantage of the internal fine-grain parallelism, high bandwidth and locality which are inaccessible otherwise. Its parallel streaming ar- chitecture can extract high throughput from stringent power, area, and thermal budgets. The thesis evaluates the efficient data reorganization capability provided by HAMLeT through sev- eral fundamental use cases. First, it demonstrates software-transparent data reorganization per- formed in memory to improve the memory access. A proposed hardware monitoring determines iii inefficient memory usage and issues a data reorganization to adapt an optimized data layout and address mapping for the observed memory access patterns. This mechanism is performed trans- parently and does not require any changes to the user software—HAMLeT handles the remapping and its side effects completely in hardware. Second, HAMLeT provides an efficient substrate to explicitly reorganize data in memory. This gives an ability to offload and accelerate common data reorganization routines observed in high-performance computing libraries (e.g., matrix transpose, scatter/gather, permutation, pack/unpack, etc.). Third, explicitly performed data reorganization en- ables considering the data layout and address mapping as a part of the algorithm design space. Exposing these memory characteristics to the algorithm design space creates opportunities for al- gorithm/architecture co-design. Co-optimized computation flow, memory accesses, and data layout lead to new algorithms that are conventionally avoided. iv Acknowledgement I owe all my success to my great advisors Professor James Hoe and Professor Franz Franchetti. Their support, advice and expertise made this work possible, I am very thankful for their time and effort. James has tremendous experience and expertise in addition to his great personality and sense of humor. Although this thesis was "done in his head" long before, it took me a while to "make it perfect". Franz is one of the smartest people that I have ever met. He always had brilliant ideas and creative solutions in every subject. Our long and productive discussions, which are made enjoyable thanks to his unique wit, contributed to a huge portion of this thesis. To me both James and Franz are both excellent advisors and good friends. I would like to thank my thesis committee members Professor Larry Pileggi and Professor Steve Keckler. Larry provided me great support and feedback throughout my PhD life including my thesis. I’m thankful to him for giving me the opportunity to access the state-of-the-art silicon technology and also teaching me how to use it. His collaboration and efforts were really valuable to me. Steve provided helpful feedback, constructive discussions and great architecture insights which made this thesis possible. I’m grateful for his time and effort. This work was partially sponsored by the Defense Advanced Research Projects Agency (DARPA) PERFECT program under agreement HR0011-13-2-0007. I’m thankful for their generous supports to fund this research. I’d like to also thank all the SPIRAL and CALCM team members in CMU. First, I’m thankful to Peter Milder for introducing me to his hardware infrastructure in SPIRAL, and for his help and col- v laboration during my first years in CMU. I’d like to also thank Michael Papamichael and Gabe Weisz for their company in the office and in various conferences, and also for their useful discussions on a lot of research or non-research topics. Special thanks to Michael for his suggestions on a lot of "how to fix a VW Golf" topics. I had the honor to work with great lab mates, researchers and post- docs in SPIRAL and CALCM including Nikos Alachiotis, Christos Angelopoulos, Kevin Chang, Eric Chung, Qi Guo, Yoongu Kim, Peter Klemperer, Bob Koutsoyannis, Tze Meng Low, Joe Mel- ber, Marie Nguyen, Eriko Nurvitadhi, Thom Popovici, Fazle Sadi, Lavanya Subramanian, Richard Veras, Yu Wang, Guanglin Xu, Jiyuan Zhang, Zhipeng Zhao, Qiuling Zhu, and many more. I would like to also thank excellent professors in CMU that I got a chance to meet and work together. Especially, I’d like to thank Professor Onur Mutlu for teaching me advanced computer architecture, Professor Jose Moura and Professor Markus Puschel for our collaborations in SPIRAL, special thanks to Markus for being a great host in Zurich. I thank all of the brilliant ECE staff, especially Claire Bauerle and Samantha Goldstein who made administrative tasks run smoothly. I feel lucky to be around great friends and fellow graduate students in Pittsburgh. There are too many to list but special thanks go to Ekin Sumbul and Cagla Cakir for their answers to my yet another circuits questions, and to Onur Albayrak, Melis Hazar, Meric Isgenc, Tugce Ozturk, Mert Terzi, Sercan Yildiz, and many more. Thank you all for making the life here so much fun. Trying to push processing "near" memory was a bit difficult, when I was "far away" from my family. I cannot express with words my gratefulness to my parents Adil Akin and Leyla Akin, and my sister Gizem Akin. Although they will not understand much of it, this thesis would be impossible without their love and support. Finally, I’d like to thank Sila Gulgec, my "home" here, for her continuous love and support. She was always with me both in the most stressful and the happiest times throughout this journey. This thesis would be meaningless without her. vi Contents 1 Introduction1 1.1 Motivation..........................................1 1.2 Thesis Approach and Contributions............................3 1.3 Thesis Organization....................................6 2 Background9 2.1 The Main Memory System................................9 2.1.1 DRAM Organization and Operation.......................9 2.1.2 3D-stacked DRAM Technology......................... 14 2.2 Hitting the Memory and Power Walls.......................... 18 2.3 Near Data Processing.................................... 20 2.3.1 3D Stacking Based Near Data Processing.................... 21 2.3.2 Hardware Specialization for NDP........................ 22 2.4 Data Layout and Reorganization............................. 23 3 A Formal Approach to Memory Access Optimization 29 3.1 Mathematical Framework................................. 29 3.1.1 Formula Representation of Permutations.................... 30 3.1.2 Formula Identities................................. 33 3.2 Permutation as a Data Reorganization Primitive..................... 34 3.3 Index Transformation.................................... 35 vii 3.4 A Formula Rewrite System for Permutations...................... 40 3.4.1 Permutation Rewriting.............................. 41 3.4.2 Labelled Formula................................. 42 3.4.3 Case Study..................................... 43 3.5 Practical Implications................................... 45 3.6 Spiral Based Toolchain................................... 47 4 HAMLeT Architecture for Data Reorganization 49 4.1 Data Reorganization Unit................................. 50 4.1.1 Reconfigurable Permutation Memory...................... 51 4.1.2 DMA Units..................................... 56 4.2 Address Remapping Unit................................. 58 4.2.1 Bit Shuffle Unit.................................. 59 4.2.2 Supporting Multiple Remappings........................ 59 4.3 Configuring HAMLeT................................... 61 5 Fundamental Use Cases 65 5.1 Automatic Mode...................................... 65 5.1.1 Changing Address Mapping........................... 67 5.1.2 Physical Data Reorganization.......................... 67 5.1.3 Memory Access Monitoring........................... 69 5.1.4 Host Application and Reorganization in Parallel................ 70 5.2 Explicit Mode........................................ 71 5.2.1 Spiral Based Toolchain.............................. 72 5.2.2 Explicit Memory Management.........................
Recommended publications
  • Memory Interference Characterization Between CPU Cores and Integrated Gpus in Mixed-Criticality Platforms

    Memory Interference Characterization Between CPU Cores and Integrated Gpus in Mixed-Criticality Platforms

    Memory Interference Characterization between CPU cores and integrated GPUs in Mixed-Criticality Platforms Roberto Cavicchioli, Nicola Capodieci and Marko Bertogna University of Modena And Reggio Emilia, Department of Physics, Informatics and Mathematics, Modena, Italy [email protected] Abstract—Most of today’s mixed criticality platforms feature be put on the memory traffic originated by the iGPU, as it Systems on Chip (SoC) where a multi-core CPU complex (the represents a very popular architectural paradigm for computing host) competes with an integrated Graphic Processor Unit (iGPU, massively parallel workloads at impressive performance per the device) for accessing central memory. The multi-core host Watt ratios [1]. This architectural choice (commonly referred and the iGPU share the same memory controller, which has to to as General Purpose GPU computing, GPGPU) is one of the arbitrate data access to both clients through often undisclosed reference architectures for future embedded mixed-criticality or non-priority driven mechanisms. Such aspect becomes crit- ical when the iGPU is a high performance massively parallel applications, such as autonomous driving and unmanned aerial computing complex potentially able to saturate the available vehicle control. DRAM bandwidth of the considered SoC. The contribution of this paper is to qualitatively analyze and characterize the conflicts In order to maximize the validity of the presented results, due to parallel accesses to main memory by both CPU cores we considered different platforms featuring different memory and iGPU, so to motivate the need of novel paradigms for controllers, instruction sets, data bus width, cache hierarchy memory centric scheduling mechanisms. We analyzed different configurations and programming models: well known and commercially available platforms in order to i NVIDIA Tegra K1 SoC (TK1), using CUDA 6.5 [2] for estimate variations in throughput and latencies within various memory access patterns, both at host and device side.
  • A Cache-Efficient Sorting Algorithm for Database and Data Mining

    A Cache-Efficient Sorting Algorithm for Database and Data Mining

    A Cache-Efficient Sorting Algorithm for Database and Data Mining Computations using Graphics Processors Naga K. Govindaraju, Nikunj Raghuvanshi, Michael Henson, David Tuft, Dinesh Manocha University of North Carolina at Chapel Hill {naga,nikunj,henson,tuft,dm}@cs.unc.edu http://gamma.cs.unc.edu/GPUSORT Abstract els [3]. These techniques have been extensively studied for CPU-based algorithms. We present a fast sorting algorithm using graphics pro- Recently, database researchers have been exploiting the cessors (GPUs) that adapts well to database and data min- computational capabilities of graphics processors to accel- ing applications. Our algorithm uses texture mapping and erate database queries and redesign the query processing en- blending functionalities of GPUs to implement an efficient gine [8, 18, 19, 39]. These include typical database opera- bitonic sorting network. We take into account the commu- tions such as conjunctive selections, aggregates and semi- nication bandwidth overhead to the video memory on the linear queries, stream-based frequency and quantile estima- GPUs and reduce the memory bandwidth requirements. We tion operations,and spatial database operations. These al- also present strategies to exploit the tile-based computa- gorithms utilize the high memory bandwidth, the inherent tional model of GPUs. Our new algorithm has a memory- parallelism and vector processing functionalities of GPUs efficient data access pattern and we describe an efficient to execute the queries efficiently. Furthermore, GPUs are instruction dispatch mechanism to improve the overall sort- becoming increasingly programmable and have also been ing performance. We have used our sorting algorithm to ac- used for sorting [19, 24, 35]. celerate join-based queries and stream mining algorithms.
  • How to Solve the Current Memory Access and Data Transfer Bottlenecks: at the Processor Architecture Or at the Compiler Level?

    How to Solve the Current Memory Access and Data Transfer Bottlenecks: at the Processor Architecture Or at the Compiler Level?

    Hot topic session: How to solve the current memory access and data transfer bottlenecks: at the processor architecture or at the compiler level? Francky Catthoor, Nikil D. Dutt, IMEC , Leuven, Belgium ([email protected]) U.C.Irvine, CA ([email protected]) Christoforos E. Kozyrakis, U.C.Berkeley, CA ([email protected]) Abstract bedded memories are correctly incorporated. What is more controversial still however is how to deal with dynamic ap- Current processor architectures, both in the pro- plication behaviour, with multithreading and with highly grammable and custom case, become more and more dom- concurrent architecture platforms. inated by the data access bottlenecks in the cache, system bus and main memory subsystems. In order to provide suf- 2. Explicitly parallel architectures for mem- ficiently high data throughput in the emerging era of highly ory performance enhancement (Christo- parallel processors where many arithmetic resources can work concurrently, novel solutions for the memory access foros E. Kozyrakis) and data transfer will have to be introduced. The crucial question we want to address in this hot topic While microprocessor architectures have significantly session is where one can expect these novel solutions to evolved over the last fifteen years, the memory system rely on: will they be mainly innovative processor archi- is still a major performance bottleneck. The increasingly tecture ideas, or novel approaches in the application com- complex structures used for speculation, reordering, and piler/synthesis technology, or a mix. caching have improved performance, but are quickly run- ning out of steam. These techniques are becoming ineffec- tive in terms of resource utilization and scaling potential.
  • Prefetching for Complex Memory Access Patterns

    Prefetching for Complex Memory Access Patterns

    UCAM-CL-TR-923 Technical Report ISSN 1476-2986 Number 923 Computer Laboratory Prefetching for complex memory access patterns Sam Ainsworth July 2018 15 JJ Thomson Avenue Cambridge CB3 0FD United Kingdom phone +44 1223 763500 http://www.cl.cam.ac.uk/ c 2018 Sam Ainsworth This technical report is based on a dissertation submitted February 2018 by the author for the degree of Doctor of Philosophy to the University of Cambridge, Churchill College. Technical reports published by the University of Cambridge Computer Laboratory are freely available via the Internet: http://www.cl.cam.ac.uk/techreports/ ISSN 1476-2986 Abstract Modern-day workloads, particularly those in big data, are heavily memory-latency bound. This is because of both irregular memory accesses, which have no discernible pattern in their memory addresses, and large data sets that cannot fit in any cache. However, this need not be a barrier to high performance. With some data structure knowledge it is typically possible to bring data into the fast on-chip memory caches early, so that it is already available by the time it needs to be accessed. This thesis makes three contributions. I first contribute an automated software prefetch- ing compiler technique to insert high-performance prefetches into program code to bring data into the cache early, achieving 1.3 geometric mean speedup on the most complex × processors, and 2.7 on the simplest. I also provide an analysis of when and why this × is likely to be successful, which data structures to target, and how to schedule software prefetches well. Then I introduce a hardware solution, the configurable graph prefetcher.
  • Eth-28647-02.Pdf

    Eth-28647-02.Pdf

    Research Collection Doctoral Thesis Adaptive main memory compression Author(s): Tuduce, Irina Publication Date: 2006 Permanent Link: https://doi.org/10.3929/ethz-a-005180607 Rights / License: In Copyright - Non-Commercial Use Permitted This page was generated automatically upon download from the ETH Zurich Research Collection. For more information please consult the Terms of use. ETH Library Doctoral Thesis ETH No. 16327 Adaptive Main Memory Compression A dissertation submitted to the Swiss Federal Institute of Technology Zurich (ETH ZÜRICH) for the degree of Doctor of Technical Sciences presented by Irina Tuduce Engineer, TU Cluj-Napoca born April 9, 1976 citizen of Romania accepted on the recommendation of Prof. Dr. Thomas Gross, examiner Prof. Dr. Lothar Thiele, co-examiner 2005 Seite Leer / Blank leaf Seite Leer / Blank leaf Seite Leer lank Abstract Computer pioneers correctly predicted that programmers would want unlimited amounts of fast memory. Since fast memory is expensive, an economical solution to that desire is a memory hierarchy organized into several levels. Each level has greater capacity than the preceding but it is less quickly accessible. The goal of the memory hierarchy is to provide a memory system with cost almost as low as the cheapest level of memory and speed almost as fast as the fastest level. In the last decades, the processor performance improved much faster than the performance of the memory levels. The memory hierarchy proved to be a scalable solution, i.e., the bigger the perfomance gap between processor and memory, the more levels are used in the memory hierarchy. For instance, in 1980 microprocessors were often designed without caches, while in 2005 most of them come with two levels of caches on the chip.
  • Detecting False Sharing Efficiently and Effectively

    Detecting False Sharing Efficiently and Effectively

    W&M ScholarWorks Arts & Sciences Articles Arts and Sciences 2016 Cheetah: Detecting False Sharing Efficiently andff E ectively Tongping Liu Univ Texas San Antonio, Dept Comp Sci, San Antonio, TX 78249 USA; Xu Liu Coll William & Mary, Dept Comp Sci, Williamsburg, VA 23185 USA Follow this and additional works at: https://scholarworks.wm.edu/aspubs Recommended Citation Liu, T., & Liu, X. (2016, March). Cheetah: Detecting false sharing efficiently and effectively. In 2016 IEEE/ ACM International Symposium on Code Generation and Optimization (CGO) (pp. 1-11). IEEE. This Article is brought to you for free and open access by the Arts and Sciences at W&M ScholarWorks. It has been accepted for inclusion in Arts & Sciences Articles by an authorized administrator of W&M ScholarWorks. For more information, please contact [email protected]. Cheetah: Detecting False Sharing Efficiently and Effectively Tongping Liu ∗ Xu Liu ∗ Department of Computer Science Department of Computer Science University of Texas at San Antonio College of William and Mary San Antonio, TX 78249 USA Williamsburg, VA 23185 USA [email protected] [email protected] Abstract 1. Introduction False sharing is a notorious performance problem that may Multicore processors are ubiquitous in the computing spec- occur in multithreaded programs when they are running on trum: from smart phones, personal desktops, to high-end ubiquitous multicore hardware. It can dramatically degrade servers. Multithreading is the de-facto programming model the performance by up to an order of magnitude, significantly to exploit the massive parallelism of modern multicore archi- hurting the scalability. Identifying false sharing in complex tectures.
  • A Hybrid Analytical DRAM Performance Model

    A Hybrid Analytical DRAM Performance Model

    A Hybrid Analytical DRAM Performance Model George L. Yuan Tor M. Aamodt Department of Electrical and Computer Engineering University of British Columbia, Vancouver, BC, CANADA fgyuan,[email protected] Abstract 2000 As process technology scales, the number of transistors that 1600 can ¯t in a unit area has increased exponentially. Proces- 1200 sor throughput, memory storage, and memory throughput 800 have all been increasing at an exponential pace. As such, 400 DRAM has become an ever-tightening bottleneck for appli- 0 Memory Access Latency cations with irregular memory access patterns. Computer BS FWT DG LPS LIB MMC MUM NN RAY RED SP SLA TRA WP architects in industry sometimes use ad hoc analytical mod- eling techniques in lieu of cycle-accurate performance sim- Figure 1: Average memory latency measured in perfor- ulation to identify critical design points. Moreover, ana- mance simulation lytical models can provide clear mathematical relationships for how system performance is a®ected by individual mi- croarchitectural parameters, something that may be di±cult cess behavior. In the massively multithreaded GPU Com- to obtain with a detailed performance simulator. Modern pute architecture that we simulate, threads are scheduled to DRAM controllers rely on Out-of-Order scheduling policies Single-Instruction Multiple-Data pipelines in groups of 32 to increase row access locality and decrease the overheads of called warps, each thread of which is capable of generating timing constraint delays. This paper proposes a hybrid ana- a memory request to any location in GPU main memory. lytical DRAM performance model that uses memory address (This can be done as long as the limit on the number of in- traces to predict the DRAM e±ciency of a DRAM system flight memory requests per GPU shader core has not been when using such a memory scheduling policy.
  • Performance Analysis of Cache Memory

    Performance Analysis of Cache Memory

    CORE Metadata, citation and similar papers at core.ac.uk Provided by Drexel Libraries E-Repository and Archives Cache Miss Analysis of Walsh-Hadamard Transform Algorithms A Thesis Submitted to the Faculty of Drexel University by Mihai Alexandru Furis in partial fulfillment of the requirements for the degree of Master of Science in Computer Science March 2003 ii Acknowledgements I would like to express my sincere gratitude to my graduate advisor, Professor Jeremy Johnson Ph.D., for his continuing support during the thesis preparation. Without his advice, guidance, understanding and patience everything would have been a lot more complicated. Finally, I am grateful to all the members of the Computer Science and Mathematics Departments: professors, TAs or friends, with who I collaborated over the years at Drexel University. iii Table of Contents Table of Contents ....................................................................................................... iii List of Tables................................................................................................................ v List of Figures ............................................................................................................. vi Abstract....................................................................................................................... vii Chapter 1 Introduction................................................................................................1 Chapter 2 Review of cache memory structure and organization .........................6
  • Classifying Memory Access Patterns for Prefetching

    Classifying Memory Access Patterns for Prefetching

    Classifying Memory Access Patterns for Prefetching Grant Ayers∗ Heiner Litz∗ Stanford University UC Santa Cruz Christos Kozyrakis Parthasarathy Ranganathan Stanford University, Google Google Abstract + Ideal Prefetching is a well-studied technique for addressing the Temporal memory access stall time of contemporary microprocessors. (large table) However, despite a large body of related work, the memory Run-ahead access behavior of applications is not well understood, and it Static compiler Correlation remains difficult to predict whether a particular application will benefit from a given prefetcher technique. In this work Stride we propose a novel methodology to classify the memory Next-line Performance • Generality access patterns of applications, enabling well-informed rea- + soning about the applicability of a certain prefetcher. Our Implementation burden (storage, hw/sw complexity) approach leverages instruction dataflow information to un- cover a wide range of access patterns, including arbitrary Figure 1. The landscape of prefetcher designs which weighs combinations of offsets and indirection. These combinations– heavily toward low performance or high cost or prefetch kernels–represent reuse, strides, reference locality, and complex address generation. By determining the com- plexity and frequency of these access patterns, we enable 1 Introduction reasoning about prefetcher timeliness and criticality, expos- Von-Neuman architectures suffer from the well-known ing the limitations of existing prefetchers today. Moreover, processor-memory performance gap: While processors have using these kernels, we are able to compute the next address enjoyed exponential increases in performance, memory has for the majority of top-missing instructions, and we propose scaled in terms of bandwidth and capacity but not in ac- a software prefetch injection methodology that is able to cess latency.
  • STEALTHMEM: System-Level Protection Against Cache-Based Side Channel Attacks in the Cloud

    STEALTHMEM: System-Level Protection Against Cache-Based Side Channel Attacks in the Cloud

    STEALTHMEM: System-Level Protection Against Cache-Based Side Channel Attacks in the Cloud Taesoo Kim Marcus Peinado Gloria Mainar-Ruiz MIT CSAIL Microsoft Research Microsoft Research Abstract number of users. However, security and privacy concerns over off-loading sensitive data make many end-users, en- Cloud services are rapidly gaining adoption due to the terprises and government organizations reluctant to adopt promises of cost efficiency, availability, and on-demand cloud services [18, 20, 25]. scaling. To achieve these promises, cloud providers share To offer cost reductions and efficiencies, cloud physical resources to support multi-tenancy of cloud plat- providers multiplex physical resources among multiple forms. However, the possibility of sharing the same hard- tenants of their cloud platforms. However, such sharing ware with potential attackers makes users reluctant to off- exposes multiple side channels that exist in commod- load sensitive data into the cloud. Worse yet, researchers ity hardware and that may enable attacks even in the have demonstrated side channel attacks via shared mem- absence of software vulnerabilities. By exploiting side ory caches to break full encryption keys of AES, DES, channels that arise from shared CPU caches, researchers and RSA. have demonstrated attacks extracting encryption keys of We present STEALTHMEM, a system-level protection popular cryptographic algorithms such as AES, DES, and mechanism against cache-based side channel attacks in RSA. Table 1 summarizes some of these attacks. the cloud. STEALTHMEM manages a set of locked cache Unfortunately, the problem is not limited to cryptog- lines per core, which are never evicted from the cache, raphy. Any algorithm whose memory access pattern de- and efficiently multiplexes them so that each VM can load pends on confidential information is at risk of leaking its own sensitive data into the locked cache lines.
  • Embedded Memory Architecture for Low-Power Application Processor

    Embedded Memory Architecture for Low-Power Application Processor

    Embedded Memories for Nano-Scale VLSIs Series on Integrated Circuits and Systems Series Editor: Anantha Chandrakasan Massachusetts Institute of Technology Cambridge, Massachusetts Embedded Memories for Nano-Scale VLSIs Kevin Zhang (Ed.) ISBN 978-0-387-88496-7 Carbon Nanotube Electronics Ali Javey and Jing Kong (Eds.) ISBN 978-0-387-36833-7 Wafer Level 3-D ICs Process Technology Chuan Seng Tan, Ronald J. Gutmann, and L. Rafael Reif (Eds.) ISBN 978-0-387-76532-7 Adaptive Techniques for Dynamic Processor Optimization: Theory and Practice Alice Wang and Samuel Naffziger (Eds.) ISBN 978-0-387-76471-9 mm-Wave Silicon Technology: 60 GHz and Beyond Ali M. Niknejad and Hossein Hashemi (Eds.) ISBN 978-0-387-76558-7 Ultra Wideband: Circuits, Transceivers, and Systems Ranjit Gharpurey and Peter Kinget (Eds.) ISBN 978-0-387-37238-9 Creating Assertion-Based IP Harry D. Foster and Adam C. Krolnik ISBN 978-0-387-36641-8 Design for Manufacturability and Statistical Design: A Constructive Approach Michael Orshansky, Sani R. Nassif, and Duane Boning ISBN 978-0-387-30928-6 Low Power Methodology Manual: For System-on-Chip Design Michael Keating, David Flynn, Rob Aitken, Alan Gibbons, and Kaijian Shi ISBN 978-0-387-71818-7 Modern Circuit Placement: Best Practices and Results Gi-Joon Nam and Jason Cong ISBN 978-0-387-36837-5 CMOS Biotechnology Hakho Lee, Donhee Ham and Robert M. Westervelt ISBN 978-0-387-36836-8 Continued after index Kevin Zhang Editor Embedded Memories for Nano-Scale VLSIs 123 Editor Kevin Zhang Intel Corporation 2501 NW. 229th Ave. Hillsboro, OR 97124 USA [email protected] ISBN 978-0-387-88496-7 e-ISBN 978-0-387-88497-4 DOI 10.1007/978-0-387-88497-4 Library of Congress Control Number: 2008936472 c Springer Science+Business Media, LLC 2009 All rights reserved.
  • A Visual Performance Analysis Tool for Memory Bound GPU Kernels

    A Visual Performance Analysis Tool for Memory Bound GPU Kernels

    View metadata, citation and similar papers at core.ac.uk brought to you by CORE provided by Computer Science Technical Reports @Virginia Tech CampProf: A Visual Performance Analysis Tool for Memory Bound GPU Kernels Ashwin M. Aji, Mayank Daga, Wu-chun Feng Dept. of Computer Science Virginia Tech Blacksburg, USA faaji, mdaga, [email protected] Abstract—Current GPU tools and performance models provide which may severely affect the performance of memory-bound some common architectural insights that guide the programmers CUDA kernels [6], [7]. Our studies show that the performance to write optimal code. We challenge these performance models, can degrade by up to seven-times because of partition camp- by modeling and analyzing a lesser known, but very severe performance pitfall, called ‘Partition Camping’, in NVIDIA ing (Figure 3). While common optimization techniques for GPUs. Partition Camping is caused by memory accesses that NVIDIA GPUs have been widely studied, and many tools are skewed towards a subset of the available memory partitions, and models guide programmers to perform common intra- which may degrade the performance of memory-bound CUDA block optimizations, neither the current performance models kernels by up to seven-times. No existing tool can detect the nor existing tools can discover the partition camping effect in partition camping effect in CUDA kernels. We complement the existing tools by developing ‘CampProf’, a CUDA kernels. spreadsheet based, visual analysis tool, that detects the degree to We develop CampProf, which is a new, easy-to-use, and a which any memory-bound kernel suffers from partition camping. spreadsheet based visual analysis tool for detecting partition In addition, CampProf also predicts the kernel’s performance camping effects in memory-bound CUDA kernels.