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Programming Intel® Quickassist Technology Hardware Accelerators for Optimal Performance White Paper Programming Intel® QuickAssist Technology Hardware Accelerators for Optimal Performance White Paper April 2015 Document Number: 332125-002 You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest Intel product specifications and roadmaps. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Copies of documents which have an order number and are referenced in this document may be obtained by calling 1-800-548-4725 or by visiting: http://www.intel.com/design/literature.htm. Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Learn more at http://www.intel.com/ or from the OEM or retailer. No computer system can be absolutely secure. Tests document performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit http://www.intel.com/performance. Intel, Intel Core, Xeon, and the Intel logo are trademarks of Intel Corporation in the U.S. and/or other countries. *Other names and brands may be claimed as the property of others. © 2015, Intel Corporation. Programming Intel® QuickAssist Technology Hardware Accelerators White Paper April 2015 2 Document Number: 332125-002 Contents 1.0 Introduction ................................................................................................................................................. 6 1.1 Intended Audience .......................................................................................................................................... 6 1.2 Overview of this Document ......................................................................................................................... 6 1.3 Terminology ....................................................................................................................................................... 7 1.4 Reference Documents ................................................................................................................................... 8 2.0 Intel® QuickAssist Technology Overview ............................................................................................ 10 2.1 Parallel Compression Benchmark .......................................................................................................... 11 3.0 Background ................................................................................................................................................ 13 4.0 Accelerator Overview .............................................................................................................................. 14 4.1 Asynchronous Hardware Interface ........................................................................................................ 14 4.2 Multiple Parallel Engines ............................................................................................................................16 4.3 Direct Memory Access ................................................................................................................................. 17 5.0 Parallelizability ......................................................................................................................................... 19 5.1 Symmetric Cryptography ........................................................................................................................... 19 5.2 Public Key Cryptography ........................................................................................................................... 20 5.3 Compression ...................................................................................................................................................20 6.0 Programming Model ................................................................................................................................ 22 6.1 Software, Multi-Core and Multi-Threading ........................................................................................22 6.2 Hardware, Synchronous, Single Threaded .........................................................................................25 6.3 Hardware, Synchronous, Multi-Threading .........................................................................................27 6.4 Hardware, Asynchronous ........................................................................................................................... 29 6.5 Multi-Core and Hyper Threading ............................................................................................................ 30 6.6 Multi-Socket and NUMA .............................................................................................................................30 6.7 Batch Submissions ........................................................................................................................................30 6.8 Polling vs. Interrupts .................................................................................................................................... 30 6.9 Programming Model Summary ...............................................................................................................32 7.0 Memory Model .......................................................................................................................................... 33 8.0 Methodology ............................................................................................................................................. 34 8.1 Benchmark Application .............................................................................................................................. 34 8.2 Compression Framework ........................................................................................................................... 34 8.2.1 Chunks ............................................................................................................................................. 36 8.2.2 Buffer Sizes .................................................................................................................................... 37 8.3 Providers ...........................................................................................................................................................37 8.3.1 zlib Provider ..................................................................................................................................38 Programming Intel® QuickAssist Technology Hardware Accelerators April 2015 White Paper Document Number: 332125-002 3 8.3.2 qat Provider ................................................................................................................................... 38 8.4 Inputs .................................................................................................................................................................. 40 8.5 Outputs ..............................................................................................................................................................42 8.5.1 Compression Ratio .....................................................................................................................42 8.5.2 Compression Elapsed Time ...................................................................................................42 8.5.3 Throughput ................................................................................................................................... 43 8.5.4 Compression CPU Time ...........................................................................................................43 8.6 Platform Description ....................................................................................................................................44 9.0 Related Work ............................................................................................................................................. 45 10.0 Future Work ............................................................................................................................................... 46 11.0 Summary of Recommendations ............................................................................................................ 47 Figures Figure 1. Parallel Compression Software Stack ....................................................................................................12 Figure 2. Multi-Socket and NUMA ............................................................................................................................... 18 Figure 3. Compression Ratio vs. Chunk Size ..........................................................................................................
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