Global Project Consultancy [email protected] Mobile: +91 9725021409 Journal Title Multi-operand Redundant Adders on FPGAs Scalable Digital CMOS Comparator Using a Parallel Prefix Tree 16-Bit Wave-Pipelined Sparse-Tree RSFQ The LUT-SR Family of Uniform Random Number Generators for FPGA Architectures MDC FFT/IFFT With Variable Length for MIMO-OFDM Systems Efficient RNS Implementation of Elliptic Curve Point Multiplication Over GF(p) Pipelined Radix- Feedforward FFT Architectures Error Detection in Majority Logic Decoding of euclidean Geometry Low Density Parity Design of Testable Reversible Sequential Circuits Design of Digit-Serial FIR Filters: Algorithms Architecture for Real-Time Nonparametric Probability Density Function Estimation Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation- Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix High-Throughput Multi standard Transform Core Supporting MPEG/H.264/VC-1 Using Comments on “Low-Energy CSMT Carry Generators and Binary Adders FFT Architectures for Real-Valued Signals Based on Radix- and Radix- Algorithms FPGA Architecture for OFDM Software Defined Radio with an optimized Direct Low-Cost FIR Filter Designs Based on Faithfully Rounded Truncated Multiple Constant A Built-In Repair Analyzer With Optimal Repair Rate for Word-Oriented Memories An Energy-Efficient L2 Cache Architecture Using Way Tag Low-Complexity Multiplier for GF(2^m) Based on All-One Polynomials CORDIC Designs for Fixed Angle of Rotation Pipelined Parallel FFT Architectures via Folding Transformation A Novel Modulo Adder for 2^n-2^k-1 Residue Number System

IEEE-2006 A VLSI architecture for a Run-time Multi-precision Reconfigurable Booth Multiplier IEEE-2006 Low-power and high-quality Cordic-based Loeffler DCT for signal processing IEEE-2006 Implementation of a Multi-channel UART Controller Based on FIFO Technique and IEEE-2006 A Low-Power Multiplier With the Spurious Power Suppression Technique IEEE-2006 FPGA Implementation(s) of a Scalable Encryption Algorithm IEEE-2006 VLSI Implementation of High Speed and High Resolution FFT Algorithm Based on IEEE-2006 Design of Delay-Insensitive Three Dimension Pipeline Array Multiplier for Image IEEE-2006 DCT-Based Image Watermarking Using Subsampling-2003 IEEE-2006 Shift Invert Coding (SINV) for Low Power VLSI-2004 IEEE-2006 Robust DWT-SVD Domain Image Watermarking: Embedding Data in All Frequencies- IEEE-2006 Digital Design of DS-CDMA Transmitter Using VHDL and FPGA-2005 IEEE-2006 Design of Edge Detection Systems

IEEE-2007 A VLSI Architecture for Visible Watermarking in a Secure Still (S2DC) IEEE-2007 A Lossless Data Compression and Decompression Algorithm and Its Hardware IEEE-2007 An FPGA-based Architecture for Real Time Image Feature Extraction-2004 IEEE-2007 Image Compression with Different Types of Wavelets-2006

IEEE-2008 Fuzzy based PID Controller using VHDL for Transportation Application [email protected] Mobile: +91 9725021409 IEEE-2008 Research on Fast Super-resolution Image Reconstruction Base on Image Sequence IEEE-2008 A Robust UART Architecture Based on Recursive Running Sum Filter for Better Noise IEEE-2008 FPGA Implementation Of Usb Transceiver Macrocell Interface With USB2.0 IEEE-2008 Multiplier design based on ancient Indian Vedic Mathematics IEEE-2008 A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM IEEE-2008 Design Exploration of a Spurious Power Suppression Technique (SPST) and Its IEEE-2008 Implementation of IEEE 802.11 a WLAN

IEEE-2009 The CSI Multimedia Architecture IEEE-2009 Design and Implementation of Boundary-Scan Circuit for FPGA IEEE-2009 Hardware Algorithm for Variable Precision Multiplication on FPGA IEEE-2009 VLSI Implementations of the Cryptographic Hash Functions MD6 and ïrRUPT IEEE-2009 VLSI Implementation of an Edge-Oriented Image Scaling Processor IEEE-2009 FPGA-Based Face Detection System Using Haar Classifiers IEEE-2009 An Effective Fast and Small-Area Parallel-Pipeline Architecture for OTM- IEEE-2009 Fast Scaling in the Residue Number System IEEE-2009 VLSI Architecture and Chip for Combined Invisible Robust Watermarking IEEE-2009 Implementing Gabor Filter for Fingerprint Recognition Using Verilog HDL IEEE-2009 An Area-Efficient Universal Cryptography Processor for Smart Cards IEEE-2009 FPGA Based Power Efficient Channelizer for Software Defined Radio IEEE-2009 Improvement of the Orthogonal Code Convolution Capabilities Using FPGA IEEE-2009 Lossless Compression using Efficient Encoding of Bitmasks IEEE-2009 3D Discrete Wavelet Transform VLSI Architecture for Image Processing IEEE-2009 A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm

IEEE-2010 Design of Low-Cost High-performance Floating-point Fused Multiply-Add with IEEE-2010 A High-speed 32-bit Signed/Unsigned Pipelined Multiplier IEEE-2010 A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 IEEE-2010 FPGA Implementations of the Hummingbird Cryptographic Algorithm IEEE-2010 FPGA Implementation(s) of a Scalable Encryption Algorithm IEEE-2010 A Memory-Efficient and Highly Parallel Architecture for Variable Block Size Integer IEEE-2010 Contrast Enhancement of Color Images using Tunable Sigmoid Function IEEE-2010 Image Compression with Different Types of Wavelets IEEE-2010 Performance Efficient FPGA Implementation of Parallel 2-D MRI Image Filtering IEEE-2010 Design and FPGA Implementation of Modular Multiplication methods using Cellular IEEE-2010 Image Edge Detection Based on FPGA IEEE-2010 VLSI Implementation of Autocorrelator and CORDIC algorithm for OFDM based IEEE-2010 Improvisation of Gabor Filter design using Verilog HDL IEEE-2010 Product Reed-Solomon Codes for Implementing NAND Flash Controller on FPGA chip IEEE-2010 A Pipeline VLSI Architecture for High-Speed Computation of the 1-D Discrete Wavelet IEEE-2010 VLSI Implementation of Fully Pipelined Multiplierless 2D DCT/IDCT Architecture for

IEEE-2011 An Efficient Implementation of Floating Point Multiplier IEEE-2011 High Speed and Low Space Complexity FPGA Based ECC Processor IEEE-2011 A blind digital watermarking algorithm based on wavelet transform IEEE-2011 A Distributed Canny Edge Detector And Its Implementation on FPGA IEEE-2011 Design and Simulation of UART Serial Communication Module Based on VHDL IEEE-2011 Design and VLSI implementation of high-performance face-detection engine for mobile IEEE-2011 Design and Implementation of Area-optimized AES based on FPGA IEEE-2011 Design of Low Power And High Speed Configurable Booth Multiplier [email protected] Mobile: +91 9725021409 IEEE-2011 Face detection and recognition method based on skin color and depth information IEEE-2011 High Speed ASIC Design of Complex Multiplier Using Vedic Mathematics IEEE-2011 A New Reversible Design of BCD Adder IEEE-2011 Authentication from JPEG Headers IEEE-2011 Design and Implementation of Low Power Digital FIR Filter based on low power IEEE-2011 Parallel Architecture for Hierarchical Optical Flow Estimation Based on FPGA IEEE-2011 A Very Fast and Low Power Carry Select Adder Circuit IEEE-2011 A_multichannel watermaking scheme based on DCT-DWT IEEE-2011 An Implementation of a 2D FIR Filter Using the Signed-Digit Number System IEEE-2011 Design and Characterization of Parallel Prefix Adders using FPGAs IEEE-2011 FPGA based FFT Algorithm Implementation in WiMAX Communications System IEEE-2011 FPGA Design of AES Core Architecture for Portable Hard Disk IEEE-2011 FPGA Implementation of RS232 to Universal serial bus converter IEEE-2011 Image Encryption Based On AES Key Expansion IEEE-2011 Feature Extraction of Digital Aerial Images by FPGA based implementation of edge IEEE-2011 An Efficient Architecture Design for VGA Monitor Controller IEEE-2011 Curve Fitting Algorithm FPGA implementation IEEE-2011 FPGA Implementation of AES Algorithm IEEE-2011 Design of Low Power Column Bypass Multiplier using FPGA IEEE-2011 Design of Serial Communication Interface Based on FPGA IEEE-2011 Design and Implementation of an FPGA-based Real-Time Face Recognition System IEEE-2011 VHDL Design and FPGA Implementation of Weighted Majority Logic Decoders IEEE-2011 Low Cost Binary128 Floating-Point FMA Unit Design with SIMD Support IEEE-2011 Design of Low Power And High Speed Configurable Booth Multiplier IEEE-2011 Design Enhancement Of combinational Neural Networks using HDL Based FPGA IEEE-2011 Efficient VLSI Architecture for Discrete Wavelet Transform

IEEE-2012 Design of 64-Bit Low Power Parallel Prefix VLSI Adder for High Speed Arithmetic IEEE-2012 Design of Low Power High Speed VLSI Adder Subsystem IEEE-2012 Synthesis and Implementation of UART using VHDL Codes IEEE-2012 HICPA: A Hybrid Low Power Adder for High-Performance Processors IEEE-2012 Low-Power and Area-Efficient Carry Select Adder IEEE-2012 Design and Implementation of Two Variable Multiplier Using KCM and Vedic IEEE-2012 Design and Implementation of a High Performance Multiplier using HDL IEEE-2012 Design of Low-Power and High Performance Radix-4 Multiplier IEEE-2012 Design of Plural-Multiplier Based on CORDIC Algorithm for FFT Application IEEE-2012 FPGA implementation of Binary Coded Decimal Digit Adders and Multipliers IEEE-2012 High Speed and Area Efficient Vedic Multiplier IEEE-2012 High speed Modified Booth Encoder multiplier for signed and unsigned numbers IEEE-2012 An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform IEEE-2012 High Speed Signed Multiplier for Digital Signal Processing Applications IEEE-2012 Accumulator Based 3-Weight Pattern Generation IEEE-2012 Design of Low Power TPG Using LP-LFSR IEEE-2012 Viterbi-Based Efficient Test Data Compression IEEE-2012 A Feature-Based Robust Digital Image Watermarking Scheme IEEE-2012 Digital Image Watermarking Based on Super Resolution Image Reconstruction IEEE-2012 Hardware Implementation of a Digital Watermarking System for Video Authentication IEEE-2012 Watermarking Mobile Phone Colour Images with Reed Solomon Error Correction Code IEEE-2012 Watermarking Scheme for Copyright Protection of 3d Animated Model IEEE-2012 Efficiency of BCH Codes in Digital Image Watermarking [email protected] Mobile: +91 9725021409 IEEE-2012 Image Magnification by Modifying DCT Coefficients IEEE-2012 A Real-time Face Detection And Recognition System IEEE-2012 VHDL Implementation of UART with Status Register IEEE-2012 Implementation of Hybrid Wave-pipelined 2D DWT Using ASIC IEEE-2012 FPGA Based Real Time Face Detection using Adaboost and Histogram Equalization IEEE-2012 Pipelined Parallel FFT Architectures via Folding Transformation IEEE-2012 VHDL Design for Image Segmentation using Gabor filter for Disease Detection. IEEE-2012 An Efficient Viterbi Decoder IEEE-2012 Improved Architectures for a Fused Floating-Point Add-Subtract Unit IEEE-2012 Very Low Resolution Face Recognition Problem IEEE-2012 Improved Architectures for a Fused Floating-Point Add-Subtract Unit IEEE-2012 Area-Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters of

IEEE-2013 16-Bit Wave-Pipelined Sparse-Tree RSFQ Adder IEEE-2013 Area-Delay Efficient Binary Adders in QCA IEEE-2013 Asynchronous Design of Energy Efficient Full Adder IEEE-2013 Comments on “Low-Energy CSMT Carry Generators and Binary Adders” IEEE-2013 FPGA Based Implementation of a Double Precision IEEE Floating-Point Adder IEEE-2013 Low-Power Digital Signal Processing Using Approximate Adders IEEE-2013 Design of High Speed Low Power Multiplier using Reversible logic-A Vedic IEEE-2013 FPGA Implementation of high speed 8-bit Vedic multiplier using IEEE-2013 Novel High Speed Vedic Mathematics Multiplier using Compressors IEEE-2013 Performance Evaluation of FFT Processor Using Conventional and Vedic Algorithm IEEE-2013 A Robust QR- Code Video Watermarking Scheme Based On SVD and DWT Composite IEEE-2013 A Wavelet based Image Watermarking Technique using Image Sharing Method IEEE-2013 An Adaptive Blind Video Watermarking Technique based on SD-BPSO and DWT-SVD IEEE-2013 Digital watermarking using DWT and DES IEEE-2013 Digital Watermarking with copyright authentication for image communication IEEE-2013 Hardware Implementation of a Digital Watermarking System for Video Authentication IEEE-2013 Image authentication and restoration by multiple watermarking techniques with advance IEEE-2013 Implementation and performance analysis of DCT-DWT-SVD based watermarking IEEE-2013 Robust Watermarking of AES Encrypted Images for DRM Systems IEEE-2013 A Fatigue Detection System with Eyeglasses Removal IEEE-2013 A Novel Approach for Face Detection using Artificial Neural Network IEEE-2013 Children Detection Algorithm Based on Statistical Models and LDA in Human Face IEEE-2013 Efficient algorithms for detection of face, eye and eye state IEEE-2013 A 2D Discrete Wavelet Transform Based 7-State Hidden Markov Model for Efficient IEEE-2013 Analysis of Multispectral Image Using Discrete Wavelet Transform IEEE-2013 Discrete Wavelet Transform and Data Expansion Reduction in Homomorphic Encrypted IEEE-2013 Image steganography in DWT domain using double-stegging with RSA encryption IEEE-2013 Study and Analysis of PCA, DCT & DWT based Image Fusion Techniques IEEE-2013 Texture classification using color local texture features IEEE-2013 VLSI architecture of multiplier-less DWT image processor IEEE-2013 VLSI Implementation of a Low-Cost High-Quality Image Scaling Processor IEEE-2013 Multiplier-less VLSI architecture of 1-D Hilbert transform pair using Biorthogonal IEEE-2013 VLSI implementation of low-power cost-efficient lossless ECG encoder design for IEEE-2013 An on-chip AHB bus tracer with real time compression and dynamic multi-resolution IEEE-2013 Radix-8 booth encoded modulo multipliers with adoptive delay for high dynamic range IEEE-2013 High throughput DA-based DCT with high accuracy error compensated adder tree IEEE-2013 Design of characterization of parallel pre-fix adders using FPGA [email protected] Mobile: +91 9725021409 IEEE-2013 Self immunity technique to improve integrity against soft errors IEEE-2013 Design and simulation of UART serial communication module based on VHDL IEEE-2013 Reducing the computation time in (short bit-width) two’s complement multipliers IEEE-2013 FPGA implementation of scalable encryption algorithm IEEE-2013 A new VLSI architecture of parallel multiplier accumulator based on radix-2 modified IEEE-2013 LUT optimization for memory-based computation IEEE-2013 Hardware implementation of RFID mutual authentication protocol IEEE-2013 FPGA implementation of the hummingbird cryptographic algorithm IEEE-2013 VHDL modeling of Wi-Fi MAC layer for transmitter IEEE-2013 FPGA implementation of USB transceiver macrocell interface with usb2.0 IEEE-2013 FPGA implementation of sha-1 algorithm IEEE-2013 VHDL implementation of lossless data compression IEEE-2013 A VLIW vector media compressor with cascaded SIMD ALU’s IEEE-2013 Design and implementation of blue tooth security using VHDL IEEE-2013 Optimized implementation of FFT processor for OFDM systems IEEE-2013 Finite state machine based vending machine controller with auto-billing features IEEE-2013 Cyclic redundancy check generation using multiple lookup table algorithms IEEE-2013 The design of high performance barrel integer adder IEEE-2013 Architectural level power optimization techniques for multipliers IEEE-2013 Design and minimization of reversible circuits for a data acquisition and storage system IEEE-2013 Arithmetic & logic unit (ALU) design using reversible IEEE-2013 A distinguish between reversible and conventional logic gates IEEE-2013 Design & implementation of MAC unit using reversible logic IEEE-2013 Modified toffoli gate and its applications in designing components of reversible IEEE-2013 A new reversible design of BCD adder IEEE-2013 An efficient implementation of floating point multiplier IEEE-2013 Fault tolerant variable block carry skip logic (VBCSL) using parity preserving reversible IEEE-2013 Design of a nanometric reversible 4-bit binary counter with parallel load IEEE-2013 Introduction to reversible logic gates & its application IEEE-2013 Design and implementation of APB bridge based on AMBA 4.0 IEEE-2013 A table-based algorithm for pipelined CRC calculation IEEE-2013 Applying CDMA technique to network-on-chip

IEEE-2014 Area-Delay-Power Efficient Carry-Select Adder IEEE-2014 Design of Efficient Binary Comparators in Quantum-Dot Cellular Automata IEEE-2014 Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation- IEEE-2014 Area-Delay Efficient Binary Adders in QCA IEEE-2014 Efficient Integer DCT Architectures for HEVC IEEE-2014 Recursive Approach to the Design of a Parallel Self-Timed Adder IEEE-2014 Improved 8-Point Approximate DCT for Image and Video Compression Requiring Only IEEE-2014 High-Throughput Multistandard Transform Core Supporting MPEG/H.264/VC-1 Using IEEE-2014 Comments on Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding IEEE-2014 Hardware Efficient VLSI Architecture for 3-D Discrete Wavelet Transform IEEE-2014 A Decimal Binary Multi-operand Adder using a Fast Binary to Decimal Converter IEEE-2014 ASIC Design of Reversible Multiplier Circuit IEEE-2014 A Novel MRI Brain Edge Detection Using PSOFCM Segmentation and Canny IEEE-2014 Power-Delay Optimized 32 Bit Radix-4, Sparse-4 Prefix Adder IEEE-2014 Real Time Human Face Detection and Tracking IEEE-2014 Key Dependent Image Steganography Using Edge Detection [email protected] Mobile: +91 9725021409 IEEE-2014 High-Throughput Programmable Systolic Array FFT Architecture and FPGA IEEE-2014 VLSI Implementation of an Adaptive Edge-Enhanced Color Interpolation Processor for IEEE-2014 Area–Delay–Power Efficient Carry-Select Adder IEEE-2014 Block Based Robust Blind Image Watermarking Using Discrete Wavelet Transform IEEE-2014 Gabor Filter Based Hand-Drawn Underline Removal in Printed Documents IEEE-2014 A novel approach to realize Built-in-self-test(BIST) enabled UART using VHDL IEEE-2014 Design of Low Power Split Path Data Driven Dynamic Ripple Carry Adders IEEE-2014 Pipelined Architecture for Vedic Multiplier IEEE-2014 Implementation of High Speed Low Power Combinational and Sequential Circuits using IEEE-2014 Area-delay-power-efficient architecture for folded two-dimensional discrete wavelet IEEE-2014 Transaction-based SoC Design Techniques for AMBA AXI4 Bus Interconnects using IEEE-2014 High Speed Convolution and Deconvolution Algorithm IEEE-2014 Improved 8-Point Approximate DCT for Image and Video Compression Requiring Only IEEE-2014 Design of Efficient Binary Comparators in Quantum-Dot Cellular Automata IEEE-2014 Recursive Approach to the Design of a Parallel Self-Timed Adder IEEE-2014 A Novel Architecture for QPSK Modulation based on Time-Mode Signal Processing IEEE-2014 A Positive Level Shifter for High Speed Symmetric Switching in Flash Memories IEEE-2014 An Efficient Hardware Architecture for Stereo Disparity Estimation IEEE-2014 An Approach for Efficient FIR Filter Design for Hearing Aid Application IEEE-2014 An Efficient Algorithm for Power and Delay Minimization in on-chip Bus

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