THÈSE Pour Obtenir Le Grade De DOCTEUR DE LA COMMUNAUTÉ UNIVERSITÉ GRENOBLE ALPES Spécialité : Nanoélectronique Et Nanotechnologies Arrêté Ministériel : 7 Août 2006

THÈSE Pour obtenir le grade de DOCTEUR DE LA COMMUNAUTÉ UNIVERSITÉ GRENOBLE ALPES Spécialité : Nanoélectronique et nanotechnologies Arrêté ministériel : 7 août 2006

Présentée par Marinela BARCI

Thèse dirigée par Dr. Barbara DE SALVO et codirigée par Dr. Gabriel MOLAS

préparée au sein du Laboratoire CEA- Leti, Grenoble et Altis Semiconductor, Corbeil -Essonnes dans l'École Doctorale d’Électronique, Électrotechnique, Automatique et Traitement du Signal

Caractérisation électrique et optimisation technologique des mémoires résistives Conductive Bridge Memory (CBRAM) afin d’optimiser la performance, la vitesse et la fiabilité

Thèse soutenue publiquement le 6 Avril 2016, devant le jury composé de : M Gérard GHIBAUDO Directeur de Recherche CNRS (IMEP-LAHC), Président M Abdelkader SOUIFI Professeur, Institut National des Sciences Appliquées (INSA) de Lyon, Rapporteur M Amara AMARA Professeur, Institut Supérieur d’Électronique de Paris (ISEP), Rapporteur M Damien DELERUYELLE Maître de Conférence, IM2NP, Université d'Aix-Marseille, Examinateur Mme Barbara DE SALVO Directeur de Recherche, Cea-Leti, Grenoble, Directrice de thèse M Pascal LOUIS Ingénieur, Altis Semiconductor, Corbeil-Essonnes, Responsable Industriel M Gabriel MOLAS Ingénieur chercheur, Cea-Leti, Grenoble, Co-encadrant de thèse, Membre invité M Daniel BERTRAND Ingénieur chercheur, Altis Semiconductor, Corbeil Essonnes, Membre invité

Abstract

Flash technology is approaching its scaling limits, so the demand for novel memory technologies is increasing. Promising replacing candidates are the emerging non volatile technologies such as Conductive Bridge Memory (CBRAM), Oxide based Resistive RAM (OXRAM), Magnetic Random Access Memory (MRAM) and Phase Change Memory (PCRAM). In particular, CBRAM is based on a simple Metal- Insulator-Metal (MIM) structure and presents several advantages compared to the other technologies. CBRAM is non volatile, i.e. it keeps the information when the power is off, it is scalable down to 10nm technology node, it can be easily integrated into the Back-End-of-Line (BEOL), finally, it has high operation speed at low voltages and low cost per bit. Nevertheless, demands for the industrialization of CBRAM are very stringent and issues related to device reliability are still to be faced. In this thesis we analyze two generations of CBRAM technology, each one addressing a specific application market. The first part of the PhD is dedicated to the electrical study of Cu-based/GdOx structures, which present the advantages of a very stable data retention and resistance to soldering reflow and also good endurance behavior. This CBRAM family addresses mainly the high temperature applications as automotive. To fulfill the specification requirements, doping of metal- oxide and bilayers are integrated to decrease the forming voltage and increase the programming window. Better endurance performance is also achieved. The second part is dedicated to a new CBRAM technology, with a simple MIM structure. In this case, the device shows fast operation speed of 20ns at low voltages of 2V, combined with satisfying endurance and data retention. This technology seems to be compatible with the growing Internet of Things (IOT) market. In summary, during the PhD research, the main objective was to study the reliability of the embedded CBRAM devices in terms of forming, endurance and data retention. Some methodologies were developed and the electrical set-up was modified and adapted to specific measurements. Physical models were developed to explain and better fit the experimental results. Based on the obtained results, we demonstrate that the CBRAM technology is highly promising for future NVM applications.

i Résumé

La technologie Flash arrive à ses limites de miniaturisation. Ainsi, la nécessité de nouvelles technologies mémoire augmente. Les candidats au remplacement des mé- moires Flash sont les technologies non volatiles émergentes comme les mémoires à pont conducteur (CBRAM), résistives à base d’oxyde (RRAM), mémoires magné- tiques (MRAM) et mémoires à changement de phase (PCRAM). En particulier, les mémoires CBRAM sont basées sur structure simple métal-isolant- métal (MIM) et présentent plusieurs avantages par rapport aux autres technologies. La CBRAM est non volatile, à savoir qu’elle garde l’information lorsque l’alimentation est coupée, ses dimensions peuvent être réduites jusqu’au nœud 10 nm, elle peut facilement être intégrée dans le Back-End d’une intégration CMOS, enfin, elle a une vitesse de fonctionnement élevée à basse tension et un faible coût de fabrication. Néanmoins, les spécifications pour l’industrialisation des CBRAM sont très strictes. Dans cette thèse, nous analysons deux générations de technologie CBRAM, chacune adressant un marché d’application spécifique. La premiére partie de la thèse est consacrée à l’étude électrique des structures à base de cuivre et de GdOx , qui présentent comme avantages une conservation des données trés stable et une bonne résistance lors de la soudure des puces, et un bon comportement de léndurance. Cette technologie adresse principalement les applications à haute température telle que l’automobile. Pour ré- pondre aux spécifications, un oxyde métallique dopé ainsi que des bicouches sont intégrés pour réduire la tension de formation de la mémoire et augmenter la fenêtre de programmation. Les performances en endurance sont améliorées. La deuxiéme partie est dédiée à une nouvelle technologie de CBRAM, avec un empilement de type MIM. Dans ce cas, nous avons démontré des temps de commutation trés ra- pides de 20 ns à basses tensions (2 V), combinés avec une endurance satisfaisante et une bonne rétention des données. Cette technologie semble être compatible avec les applications Internet des objets (IOT). En résumé, au cours de ce doctorat, lóbjectif principal était d’étudier la fiabilité des dispositifs embarqués CBRAM en termes d’écriture des données, endurance et la conservation de l’information. Une méthodologie de test spécifique a été développée, afin d’évaluer les performances des technologies étudiées. Des modèles physiques ont été mis au point pour expliquer et analyser les résultats expérimentaux. Sur la base des résultats obtenus, nous démontrons que la technologie de CBRAM est trés prometteuse pour les futures applications de mémoires non volatiles.

ii Contents

1 Introduction 3 1.1 Memory Market study and trends ...... 3 1.2 State-of-Art: Mature and Emerging NV memories ...... 5 1.2.1 FLASH technology ...... 5 1.2.2 RRAM technology ...... 8 1.2.3 Other emerging NV memories ...... 12 1.2.4 Summary of emerging NVM ...... 14 1.3 RRAM single device and demonstrators performances ...... 17 1.4 Motivation of this work ...... 20

2 Overview of the studied CBRAM technology 21 2.1 CBRAM conﬁguration ...... 22 2.2 Electrical characterization methodology ...... 22 2.2.1 Forming in QS and Pulsed Mode ...... 23 2.2.2 SET and RESET Operation ...... 24 2.2.3 Short pulse measurements ...... 25 2.2.4 High temperature data retention ...... 26 2.2.5 Cycling endurance ...... 27 2.2.6 Pre-forming ...... 28 2.3 Modeling ...... 29 2.3.1 2D numerical model ...... 29

3 CBRAM - Study of Data retention 31 3.1 State-of-Art: Data retention study of CBRAM technology ...... 31 3.2 Sample description ...... 33 3.3 Methodology ...... 34 3.4 Numerical model ...... 35 3.5 Results and discussion ...... 36 3.5.1 LRS ...... 36 3.5.2 HRS ...... 38 3.5.3 Temperature activation ...... 39 3.5.4 Trade-oﬀ "retention vs. consumption" ...... 40

iii 3.6 Conclusions ...... 41

4 Bilayer devices to improve memory performances 43 4.1 State of Art: Electrical performances of bilayer metal-oxide RRAM . 43 4.1.1 Gd2O3/(10%) Cu-MoOx, Yoon et al., Microelec. Eng. 2009 . . 43 4.1.2 HfOx/AlOx RRAM, Yu et al., VLSI-TSA 2011 ...... 44 4.1.3 Ni/ HfOx/ AlOy/p+-Si, Tran et al., EDL 2011 ...... 46 4.1.4 Pt/ZrOx /HfOx/TiN, Jung et al., APL 2010 ...... 48 4.1.5 Pt /CuxO/ SiO2/Pt, Yi et al., NVMTS 2008 ...... 50 4.1.6 TiN/TiOx/HfOx/TiN, Chen et al., IEDM 2009 ...... 52 4.1.7 Mono and Bilayer CBRAM technology studied in this work . . 54 4.2 Results and discussions ...... 54 4.2.1 Quasi - static measurements ...... 55 4.2.2 Pulsed - mode measurements ...... 55 4.2.3 Data retention ...... 57 4.2.4 Endurance ...... 59 4.2.5 Modeling and discussion ...... 62 4.3 Conclusions ...... 64

5 Generation 3 metal-oxide CBRAM technology compatible for low power applications 67 5.1 State of Art: Advantages of the new technology to be compatible with IOT applications ...... 67 5.2 Technological details, set-up and methodology ...... 68 5.3 Experimental Results ...... 68 5.3.1 Quasi - static measurements ...... 68 5.3.2 Short-pulse measurements ...... 70 5.3.3 Pulsed - mode measurements ...... 73 5.3.4 Endurance ...... 75 5.3.5 Data retention ...... 80 5.4 Conclusions ...... 81

6 General Conclusions and Perspectives 84

A Résumé en français 87 A.1 Mémoires non-volatiles émergentes ...... 87 A.1.1 Technologies de mémoire non volatile émergentes ...... 87 A.1.2 Démonstrateur et leurs performances ...... 90 A.1.3 Motivation ...... 90 A.2 CBRAM étude de la conservation des données ...... 92 A.2.1 Conclusion ...... 98

iv A.3 Dispositifs CBRAM bicouches pour améliorer les performances de la mémoire ...... 101 A.3.1 Conclusion ...... 110 A.4 Génération 3 CBRAM pour des applications a basse puissance . . . . 111 A.4.1 Conclusion ...... 119 A.5 Conclusions General ...... 121 A.5.1 Perspectives ...... 123

B Author’s publications 124

Bibliography 126

v Manuscript Outline

The manuscript is organized in 6 chapters. In Chapter 1, we introduce the context and motivation of the research done during these three years of the PhD. A description of the memory market and RRAM/CBRAM State-of-the-Art are given in details. In chapter 2, an overview of the studied CBRAM technology is given, the integration flow and the main applications are shown. The methodology to characterize the reliability of our structures is given for both 1T1R and miniarrays configuration, including in forming, SET/RESET operation, screening of the parameters during SET and RESET operations, endurance measurements, thermal stability and soldering-reflow. A new set-up was realized to measure cycling endurance for short- pulse measurements. A new idea was proposed to improve uniformity and facilitate "forming" process. Numerical models were developed to explain the experimental results. Chapter 3 focuses on the thermal stability of CBRAM technology. It is shown that the electrical measurements are in good agreements with the physical model, able to explain the retention behavior. "Smart" RESET operation was proposed to improve retention and Arrhenius plot was used to extract the temperature at 10 years retention is guaranteed. A region showing stable LRS and HRS retention behavior is demonstrated for different programming currents. Low power consumption is shown for 30 µA. Measurements were performed up to 300 °C. In Chapter 4, we propose a bilayer metal-oxide/Al2O3 CBRAM device that shows improvement in HRS and cycling endurance up to 1 × 105 cycles. The electrical results are shown for both mono and bilayer devices. A 2D numerical model is developed to explain endurance failure behavior. A "smart" endurance test was proposed to reach 1 × 106 cycles cycles increasing applied voltages during SET and RESET progressively until the initial target resistance is reached. In chapter 5, we introduce a new generation of CBRAM technology, with the advantage of using simple materials (easier to integrate) and low power consumption. Reliability tests were performed for our devices regarding forming, cycling endurance using pulses of minimum 20 ns up to 1 µs and data retention up to 200 °C. In chapter 6, a summary of the results we obtained during the thesis is presented. Finally, we also provide some prospects on the future work to be done in order to improve our technology and make it suitable for NV market demands.

1 Acknowledgements

This PhD thesis was prepared in collaboration between the Universite Grenoble Alpes, CEA LETI and Altis Semiconductor. First, I would like to express my special appreciation and thanks to my thesis director Dr. Barbara De Salvo. I would like to thank her for encouraging my research and for allowing me to grow as a research scientist. Then, I would like to thank my supervisors Dr. Gabriel Molas and Dr. Elisa Vianello for supporting and helping me during my thesis. I want to thank all the LCM team: Luca Perniola, Eric Jalaguier, Gabriele Navarro, Veronique Sousa, Alain Persico, Christelle Charpin, Sophie Bernasconi, Carine Ja- han, Remi Coquand, Etienne Nowak, Laurent Grenouillet, Catherine Carabasse, Jean-Francois Nodin. It was a pleasure to be part of your team and to work with you. I thank Anne Roule, Mathieu Bernard, Philippe Blaise, Stephane Becu, Alain Lopez, Jacques Cluzel, Denis Blachier, Carlo Cagli, Giovanni Romano and all the people from LCTE and LICL laboratories for their support. I thank my colleagues from Altis Semiconductor: my manager Pascal Louis, Daniel Bertrand, Michel Sar- langue, Brahim Belgacem, Mehdi Kanoun, Jacques Liebault, Pascal Verrier, Faiz Dahmani and Emilie Jansingh and all the others who I did not mention. Thank you for your fruitful discussions, lunches, coffee breaks and for more that you gave me the opportunity to have an experience in industry during my PhD. I thank all the PhD students, interns and postdocs who shared with me great moments during the last three years: Daniele, Thanasis, Manan, Boubacar, Quentin, Thomas, Gabriele, Giorgio, Therese, Jeremy, Florian, Yann, Sebastien, Amine, Julien, Issam, Sarra, Heimanu, Remi, Luca, Niccolo, Thilo, Julia, Mourad, Mouhamad, Giuseppe, Cecile, Adam, Daeseok, Luc, Martin, Aurore, Fabien, Loic, Romain, Vincent, Mathilde, Corentin, Anouar, Mathias, Patricia, Alexandre. I am sorry if I have forgotten someone. I would like to thank Sabine and Brigitte for their help and availability during these three years. I am grateful to Prof. Gerard Ghibaudo, Prof. Abdelkader Soufi, Prof. Amara Amara and Prof. Damien Deleruyelle for accepting to review this thesis and for their useful comments, remarks and questions during my PhD defense. I thank my family for being the greatest support in my life, for teaching me that you need to work hard, believe in yourself and never give up if you want to fulfill your dreams. Last, but not least I want to thank all my professors from the primary school to PhD, for their knowledge, help and support.

2 Chapter 1

Introduction

In this chapter we will give a general view of memories. In a ﬁrst part we will discuss about the memory market study and the trends for applications such as stand-alone, embedded and Storage Class Memory. Among the mature and emerging non volatile memories, we want to identify the role of CBRAM in the memory market study. Then a section on the State-of-the-Art of memories is given in details, starting from Flash and the evolution of other emerging memories such as CBRAM, OxRAM, PCRAM and MRAM. Some comparison between CBRAM and other memories is given, identifying both the advantages and issues related to each technology. The latest publications are mentioned, explaining each product and its speciﬁcations. The last part will be dedicated to the motivation of this work.

1.1 Memory Market study and trends

Memory can be either volatile and non-volatile memoriy (NVM).Depending on their applications, NVM are classiﬁed into stand-alone, embedded and storage class memory SCM. Classic volatile memories consist in SRAM and DRAM and they are the most common used in the nowadays applications dominating the market for stand- alone applications around 35.6 B$ as shown in Fig.A.1b and around 60 % for the mobile micro processors (MPU) and micro-controllers (MCU) applications as shown in Fig.A.1a. Somehow they do not keep the information after the power is turned oﬀ. For this reason novel NV memories are having more and more attention. The data in Fig.A.1a shows that they occupy 1.3 B$ of the stand-alone market and 27 % of automotive and micro-controllers market cost. NAND and DRAM stand-alone memories dominate the memory market, representing about 90 % of overall memory sales. Among the emerging NVM we can mention phase change memory PCM, magnetic random access memory MRAM, ferroelectric RAM FeRAM, resistive switch memory (also called ReRAM, CBRAM, OxRAM), polymeric-based memory, molec- ular memory etc as shown in Fig.1.4. These memories should overcome the scaling

3 1 – Introduction

(a)

(b)

Figure 1.1. (b)Memory market chart for stand-alone applications. (a) Memory market chart for embedded applications [1]. issues which effect Flash memory, the most mature NV technology with a presence in the market of 28.7 B$. Predictions show that by 2020, emerging NVM market will grow up to 7 B$ by 2020 with Enterprise Storgae as the largest market due to fast adoption of RRAM and STT-MRAM as represented in Fig.A.3. Wearable is the second growing market because of the strong demand for low power. SCM is evolving as a cathegory of memory targetting to fill the gap between RAM and SSD in terms of short latency and high density. It combines the benefits of solid-state memory, such as high performance and robustness, with the archival capabilities and low cost of conventional hard-disk magnetic storage. Such a device requires a nonvolatile memory (NVM) technology that could be manufactured at a very low cost per bit. The main parameters determing its evolution are: latency, endurance, volatility and cost [1]. In this section an overview of Emerging Resistive technologies will be given [2].

4 1 – Introduction

The schematics shown in Fig.A.2 highlights the applications in industry and trans- portation up to mass storage memory applications. IOT is catching more and more attention and the demand for smart and wearable electronics is increasing. With its advantages as low power and fast switching speed, CBRAM stands as one of the promising future memory. Many research centers and companies are investing in NVM memory ﬁeld in the level of start-up companies as Adesto, Crossbar, Cro- cus Technology; Integrated device manufacturers as Samsung, Toshiba or foundries as TSMC, GlobalFoundrais. Their business is encouraged by data centers, social network and ebusiness players as Facebook, Google and eBay.

Figure 1.2. Applications of new emerging RRAM technologies [1].

1.2 State-of-Art: Mature and Emerging NV memories

1.2.1 FLASH technology Flash is considered a mature NV memory technology and it is already available in the market in current memory applications. It is divided into 2 groups NAND and NOR Flash architectures. NOR are suitable for code storage, while NAND are more used for data storage. These memories are based in Si-CMOS technology, having an additional ﬂoating gate between the MOSFET channel and the controlling gate as shown in Fig.1.6. Since it is isolated by insulating oxide, electrons are trapped in this area and the transistor is set in the logical "0" state. So a higher voltage is needed to be applied in the controlling gate to make the channel conductive, which

5 1 – Introduction

Figure 1.3. Main contributors in NV Memories development [1].

Figure 1.4. Memory classiﬁcation including volatile and non volatile, both mature and emerging technologies [3].

increases the threshold voltage of the transistor(Vt1 higher than Vt2) and puts it in logical "1" state. In order to read, the voltage applied in the controlling gate (CG)

6 1 – Introduction

Figure 1.5. Emergin NVM market trend by applications from 2014-2020 [1]. should be in the intermediate state. If the transistor conducts, the floating gate is not charged, so a logical "1" is stored in the gate. Otherwise if the transistor does not conduct at this applied voltage, the floating gate is charged and a logical "0" is stored. Experimentally this is proved by measuring the current passing through the transistor at this intermediate voltage, which allows single bit or multibit cell device depending on the charge stored in the floating gate. NAND flash memory is also used in hard disks or optical media (e.g. CD, DVD). One example is the microSD card which has an area of about 1.5 cm2, with a thickness of less than 1 mm and offers presently up to 16 GB of storage capacity at the same time [3].

Figure 1.6. Schematic of a Flash cell. Single bit or multibit storage is possible depending on the charge stored in the ﬂoating gate.

NAND has become the cheapest and densiest device in the semiconductor industry. 64 Gb and 128 Gb monolithic MLC NAND are already in production at 16 and

7 1 – Introduction

(a) (b)

Figure 1.7. (a) Vertical NAND cell integration presented by Samsung. (b) Vertical NAND speciﬁcations [4].

15nm half-pitch [4]. But planar Flash is approaching its limits due to scaling. Now the focus has moved to the integration of vertical NAND (Fig. 1.7a and Fig. 1.7b). Its main advantages with compared to planar NAND are density, cost and threshold variability is reduced for vertical NAND related to program and RTN with a great advantage for multilevel storage, [5].

1.2.2 RRAM technology Conductive Bridge RAM CBRAM

In this chapter we will focus on the ReRAM. These memories consist in a MIM (Metal-Insulator-Metal) structure. The top electrode (the anode) is made of an electrochemically metal as Ag or Cu as shown in Fig.1.8. The solid electrolyte can be a chalcogenide as GeS2, GeSe or a metal oxide as HfOx, GdOx,Ta2O5 etc. The bottom electrode or the cathode is made of an inert metal such as W, Pt. When a positive bias is applied between top and bottom electrode, the state of the device is switched between HRS (High resistive state) and LRS (Low resistive state) and viceversa if the bias polarity is reversed. The schematic of CBRAM switching mechanism is shown in Fig.1.9. This behavior is called bipolar. To use the same terminology we will refer to LRS as the ON-state of the device and HRS to the OFF-state. The resistance change is due to electro-chemical formation and dissolution of conductive ﬁlaments. When a positive voltage is applied on the top electrode, metal atoms are oxidized and dissolve into the solid electrolyte. Under the electric ﬁeld these metal cations immigrate towards the bottom electrode where they are reduced and deposited. This process

8 1 – Introduction

Figure 1.8. Schematic behavior of a CBRAM cell integrated into 1T1R configuration. continues and a conductive filament (CF) is formed between the cathode and anode, shunting the resistance from HRS to LRS. When a negative voltage is applied, the CF dissolves and resistance is switched back to HRS. Current - induced Joule heating may also contribute to the filament rupture. The device can switch between HRS and LRS many times, since electro-chemical reaction does not cause big damage to the CBRAM device. For memories with metal sulfides as solid electrolyte, mobile ions as Ag+ already exist in the electrolyte. But for other metal oxides, the mobile ions are external and usually a "forming" process is performed to drive these ions into these materials, before stable resistive switching can be achieved. This forming value is higher than the other subsequent Write operations named SET. CBRAM technology is considered as a promising technology due to its many advantages, among them most interesting are: CBRAM is non volatile, it keeps the information when the power is off, it is scalable down to 10 nm technology node [6], [7]. It can be integrated into the BEOL. It has high operation speed at low voltages. Even if a lot of research has been conducted from different research laboratories and companies, some issues related to device reliability and controllability still have to be addressed [3]. Some demonstrators (Fig.1.10a) of 2 Mbit first generation CBRAM integrated in 90 nm technology are shown from Altis Semiconductor and 1 Mbit array second generation CBRAM integrated into 130 nm technology presented by Adesto are already available in the market [8]. In Fig. 1.10b a 4 Mb product is presented by Sony [9]. A 16 Gb Cu-ReRAM integrated in 27 nm technology node is shown in Fig. 1.11a and Fig. 1.11b by Sony-Micron [10], [11] and [12].

Oxide-based Resistive RAM

They are also named OxRAM or Valence Change Memory (VCM). RRAM are composed of a MIM structure, normally a thin insulator ﬁlm, more in general metal-oxide

9 1 – Introduction

Figure 1.9. Current-Voltage behavior of a CBRAM cell.

(a) (b)

Figure 1.10. (a) 1 Mbit array CBRAM presented by Adesto at IEDM 2013 [8]. (b) 4 Mb CBRAM array and its speciﬁcation are presenteed by Sony at ISSCC 2011 [9].

(TiO2,HfOx) is sandwiched between 2 metal electrodes made of Pt. Other metal- oxides as TiOx, AlOx, WOx and SrTiOx have also been exploited and show bipolar behavior. The basic operation lies in a redox mechanism. When a voltage is applied on the top electrode (Fig.1.12), oxygen vacancies and oxygen anions are generated into the insulating layer. The O2-ﬂows towards the positively biased electrode and oxidizes TiO2 into Ti2O5, which increases the barrier height, increasing the structure’s resistance. If the voltage polarity is inversed, oxygen vacancies ﬂow towards the negatively biased electrode, reducing the TiO2 insulating layer, so reducing its resistance. OxRAM is interesting for innovative applications such as neuromorphic

10 1 – Introduction

(a) (b)

Figure 1.11. (a) Cu-ReRAM cell integrated in 27 nm technology node. (b) 16 Gb die micrograph presented at ISSCC 2014 [12]. and convolutional neural network for pattern recognition applications. [13]–[15] OxRAM devices scale down to 8 nm with HfOx, they show 1 ns switching speed and energies of the order of pJ [16], [17]. Beside its excellent performances, one main issue with OxRAM devices remains variability and work is still needed to be done to fully understand its switching mechanisms in order to overcome this issue. Some demonstrators are shown in Fig 1.13a and its cell speciﬁcations (Fig. 1.13b) from Panasonic: 8 Mb TaOx ReRAM with write pulses of 8.2 ns [18] and [19] and Toshiba: 32 Gb ReRAM integrated in 24 nm CMOS technology.

Figure 1.12. Switching mechanism in binary metal-oxide RRAM.

A low power 2 Mb ReRAM was developed in 90 nm CMOS platform by Renesas

11 1 – Introduction

(a) (b)

Figure 1.13. (a) OxRAM memory array and its bipolar diode JV characteristic was presented by Panasonic [18]. (b) Macrograph of the test chip description is given for 512 kbit 1T1R array [19].

[20]. The integration ﬂow-chart of the cell composed of Ta2O5 and Ru bottom electrode is shown in Fig. 1.14.

Figure 1.14. Switching mechanism in binary metal-oxide RRAM was presented by Renesas [20].

1.2.3 Other emerging NV memories Transfer Torque STT-MRAM In order to overcome the scalabilty and high cell writing current issues, Spin Transfer Torque Magentic RAM (STT-MRAM) proposes a magnetic tunnel junction (MTJ) structure composed of 2 ferromagnetic layers and a very thin MgO– based tunneling barrier of less than 1nm. By applying a polarized electron current into the device, a change from parallel "1" to antiparallel "0" and viceversa occurs. The orentiation of the magnetization of the Free layer (FL) can be switched between two states and it is used to store information. The magnetization of the Reference layer (RL) is ﬁxed. If the orientation of RL and FL are the same, the device is in Parallel (P) state,

12 1 – Introduction

(a) (b)

Figure 1.15. (a) Schematic view of a STT-MRAM cell. The MTJ is composed of a reference layer (RL), a tunnel barrier and a free layer (FL), both layers magnetized perpenticular to the plane of the junction [23]. (b) STT-MRAM electrical characteristics. Resistance versus applied magnetic field, showing bistable resistance states near zero-field associated with parallel (P) and antiparallel (AP) magnetized bits. Resistance versus voltage, showing switching between AP and P states (positive bias) and vice versa (negative bias). otherwise it is in Antiparallel (AP) state. The working principle of a STTRAM is based on two phenomena such as Tunneling Magento-Resistance (TMR) effect and the Spin Transfer Torque (STT) effect. TMR effect [21] is the ratio of resistance between parallel and antiparallel R. The resistance of the cell can be sensed in order to determine the magentic state of the FL, so the stored information can be retrived. While STT effect [22] is the effect which allows to switch the orientation of the magnetization of the FL. When electrons flow through the MTJ, a torque is exerted on the magnetization of FL, and if it is large enough, the magentic state of the FL can be switched and the information is written. If a positive bias is applied to the device, electrons with same spin orientation as RL magnetization will be transmitted by tunneling through the MTJ and will transfer their spin to the FL by STT. The MTJ will be in Parallel state. If a negative voltage is applied, the electrons are injected from the FL to the RL. In Fig. 1.15b is shown STT-MRAM electrical characteristics. Resistance versus applied magnetic field, showing bistable resistance states near zero-field associated with parallel (P) and antiparallel (AP) magnetized bits. Resistance versus voltage, showing switching between AP and P states (positive bias) and vice versa (negative bias). At the interface between the tunneling barrier and RL, electrons with the same orientation as RL will be transmitted through MTJ, while electrons with oposite orientation will be reflected back in the FL and switch its magnetization to AP state. Multilayers configuration is possible with stacked MTJs. STT-RAM have high endurance due to the fact that no magentic degradation mechanism is associated to the switching of the magnetization orientation [23]. 2 Mb STT-RAM with a MgO tunneling barrier using 0.2 µm2 technology process was presented by Hitachi [24].

13 1 – Introduction

(a) (b)

Figure 1.16. (a) Schematic cross-section of a PCM cell. (b) IV characteristics of crystalline and amorphous phase of PCRAM materials [27].

Phase Change RAM PCRAM

The classical cell called "mushroom cell" Phase Change RAM (PCRAM) consists of memory storage or programmable region, most used is a chalcogenide GeSbTe material (Fig. 1.16a). When a voltage is applied in the top and bottom electrodes, it injects a heat pulse into the programming region of the chalcogenides phase change material [25], changing its state from amorphous high resistance state to polycrys- talline LRS. These high and low resistive states happen during "RESET" and "SET" operations. In PCRAM it is possible to switch the material between crystalline and amorphous many times. Crystallization is achieved by heating the material above its crystallization temperature (SET operation). Amorphization is achieved by melting the material in the liquid state and rapidly quenching it into disordered amorphous phase (RESET operation) as shown in Fig. 1.16b. One of the limita- tions to PCRAM technology is the relatively high RESET current [26]. PCRAM technology can enable Multi-Level-Cell MLC scaling. It is implemented in both stand-alone and embedded applications. Some pro- totypes and demonstrators are shown from Samsung: 512 MB SLC memory chip integrated in 90 nm process with an area of 0.047 um2 and Numonyx Inc: 128 MB integrated in 90 nm process [26].

1.2.4 Summary of emerging NVM

RRAM is interesting for eNVM applications compared to eFlash because it uses low power: 2-3 V instead of up to 20 V. It is low cost, about 20% less than eFlash and uses 3 extra masks layer instead of 10 used in eFlash. It is compatible with CMOS BEOL technology and it has 10-100 times faster write time. MCUs with eNVM tend

14 1 – Introduction to be the workhorse for IOT, increasing the interest of eRRAM commercialization. Thermal stability is still an issue in order to replace eFlash. For the moment it was demonstrated stable retention behavior of 85 °C/10yrs in products and in research work around 110 °C/10yrs but this remains still lower than eFlash. RRAM is also compatible with standalone applications, but 3D RRAM is not ready to replace 3D NAND. RRAM remains a good option for Storage Class Memories (SCM) in order to close the gap between DRAM and NAND. SCM can be divided into 2 types: memory or storage mapped SCMs [5]. In order to be compatible for Memory SCM, the technology should replace a part of DRAM for power applications. Nowadays MRAM seems ﬁtting better in terms of retention and cost but scalability below 20 nm is still an issue. To be compatible with storage SCM the main demands are low cost, NV and high density which emerging RRAM seems to compete. In order to reach low cost, cross-bar multilayer array of RRAM is exploited. Recent announcement was made by Intel-Micron with their 3D XPoint memory, which meets the requirements for storage SCM [28]. In addition to the device integration, a lot of research has been done regarding the selector device. Many options are used in the literature: as npn diodes, MSM (Mihnea et al., Sekar et al.), (Sandisk US patent), Metal-Insulator-Metal (MIM) structures (Panasonic), Ovonic Threshold Switch (OTS) presented by Kau et al., (Intel) and Mixed Ionic Electronic Conduction (MIEC) selector by G. Burr et al., (IBM). The main parameters evaluating a suitable selector are: selectivity (1 × 1010), endurance (1 × 108 ), switching slope (< 5 mV/div), max current density (> 5 × 106 A/cm2 and processing temperature (<300 °C) [29]. In Fig 1.17a the integration of FAST selector is shown and in Fig. 1.17b are shown its I-V characteristics at room temperature and 125 °C. Thereafter, we summerize the reliability performances of OxRAM and CBRAM, according to [30]:

Forming The stack considered for OxRAM is made of reactive Ti top electrode/amorphous ALD HfSIOx dielectric layer and TiN bottom electrode, while the stack for CBRAM consists in TE/Cu ion reservoir/electrolyte layer/TiN bottom electrode. Diﬀerent sources for the formation of the ﬁlament are considered: In OxRAM there is a "soft- breakdown" of the dielectric while in CBRAM, the CF is formed due to electro- chemical ionization of Cu which is provided by external reservoir (TE). In CBRAM, forming voltage thus is lower than the breakdown voltage.

Endurance Both technologies show feasible endurance up to 1 × 106 cycles as shown in Fig. 1.19 but with CBRAM a larger programming window of almost 1000 times is achieved,

15 1 – Introduction

(a)

(b)

Figure 1.17. (a) Passive crossbar array integration of FAST selectors (single cell to 4Mb array). Images of the fabricated selectors. (b) I-V characteristics of the integrated selectors (isolated single cell, cells in 100Kb and 4Mb arrays) at 25 °C and I-V at 125 °C. [29].

(a) (b)

Figure 1.18. (a) Cell description and TEM image for the CBRAM cell. (b) Cell description and TEM image for the OxRAM cell [30]. driven by higher HRS.

Data retention

Both technologies were tested at high temperature of 150 °C/1hr at low operating current of 40 µA. The results are shown in Fig. 1.20. Improved stability is demonstrated for CBRAM structures.

16 1 – Introduction

Figure 1.19. Cycling behavior up to 1 × 106 cycles for both CBRAM and OxRAM technologies [30].

Figure 1.20. Retention behavior of the memory cell for CBRAM and OxRAM at 150 °C/1hr for low operating current of 40 µA [30].

ReRAM challenges For both technologies there are some issues as variability and read/program noise as shown in Fig. 1.19, since ethe conducting ﬁlament is believed to approach a few atoms in size. High density applications require the cell to function with low programming noise, high variability and noise are signiﬁcant product-level concern. OxRAM cells show 2x higher noise compared to CBRAM. Beside the advantage of CBRAM, OxRAM uses simple materials (without the need of Cu integration) making it low cost and easier to be integrated in CMOS technology.

1.3 RRAM single device and demonstrators performances

Memory devices have stringent requirements in order to be industrialized. The criteria are ﬁxed from surveys of Emerging Research Device Work Group [3]. In terms of electrical performances the main characteristics consist in forming voltage and current, switching speed, power consumption, endurance cycling, data retention,

17 1 – Introduction

Figure 1.21. Normalized STD of single-cell LRS read current vs. median read current. OxRAM cells show 2x higher noise compared to CBRAM [30]. multibit capability, density, reproducibility and scaling. These parameters vary and one or another has priority depending in their applications: storage, memory, logic or neuromorphic as representing in Fig.1.22 as a demand to extend "CMOS Extension" and "Beyond CMOS" technologies. For memory applications the requirements and the data demostrated in the literature are promising and compatible [31]–[33]. In table A.1 are shown the performance parameters projected for scaled emerging research memory technologies STTRAM, CBRAM, PCM and OxRAM, the values are the one demonstrated in the literature and the one projected. These performances are positive and in the future they can replace Flash technology.

Figure 1.22. Device requirements corresponding to diﬀerent memory applications [31]–[33].

18 1 – Introduction

STT- PCRAM CBRAM OxRAM MRAM Feature Demonstrated 45 65 20 5 Size F (nm) Projected 8 16 5 <5 Demonstrated 4F2 20F2 4F2 4F2 Cell Area Projected 4F2 8F2 4F2 4F2 Programming Demonstrated 3 1.8 0.6 1 Voltage (V) Projected <3 <1 <0.5 <1 Programming Demonstrated 100 35 <1 <1 Time (ns) Projected <50 <1 <1 <1 Programming Demonstrated 6 · 10−12 2.5 · 10−12 8 · 10−12 1 · 10−12 Energy (J/bit) Projected 1 · 10−15 1.5 · 10−13 N.A. 1 · 10−16 Read Demonstrated 1.2 1.8 0.2 0.1 Voltage (V) Projected <1 <1 <0.2 0.1 Retention Demonstrated >10yr >10yr >10yr >10yr Time Projected >10yr >10yr >10yr >10yr Endurance Demonstrated 109 1012 1010 1012 (nb. cycles) Projected 109 1015 1011 1012

Table 1.1. Comparison of the performance of the diﬀerent emerging nonvolatile memory technologies according to the 2013 International Technology Roadmap for Semiconductor (ITRS), with projections for year 2026 [3].

19 1 – Introduction

1.4 Motivation of this work

Flash technology is approaching its scaling limits, so the demand for novel technologies is increasing. Promising candidates are NV RRAM due to their simple structure, CMOS compatibility, low power, fast switching speed and scalability, low cost per bit. Some issues related to the understanding of the operating mechanisms and variability still need to be addressed. In order to address these issues and increase RRAM performances, material engineering for metallic electrodes [34] and the insulating layer are currently proposed, including the implementing of new methods for better quality material deposition. Correction algorithms are proposed to limit current overshoot, variability and increase the window margin. Memory select devices also need to be improved. A lot of research is focused on 3D crossbar integration of emerging technologies [35] with the advantage of higher density and they occupy less space. Market experts believe that the NVM will double by 2020, increasing its presence in both standalone and embedded applications. Also smart devices such as tablets and phones have been a driving force for increasing the demand of storage capacity. The main focus of this thesis is the CBRAM technology. An introduction of its State - of - the Art, operation principle and future applications was given in this Chapter. Recently, many companies and research laboratories presented CBRAM with metal-oxides integrated as resistive layer. The devices show reliability improvements such as data retention, endurance and soldering reﬂow with respect to the previous technology which was based on chalcogenides as insulating layer [36], [8]. The main applications we targeted were high temperature and low power applications.

20 Chapter 2

Overview of the studied CBRAM technology

A CBRAM device consists of a MIM structure. In the frame of this PhD, 2 main technologies have been implemented, using metal oxides as resistive layer. In the ﬁrst case, we targeted high temperature embedded applications. The main issue for CBRAM to be compatible with these applications is thermal stability. In our devices, the top electrode is electro-chemically active, and is made of CuTeGe, the metal-oxide is composed of 5nm GdOx. The bottom electrode consists of an inert metal such as Ta or TaN plug of 200 nm of diameter. In order to have a lower forming voltage, GdOx has been doped with Hf up to 15% (measured by RBS). On the other hand in order to increase the memory window, thin layers (0.5 nm) of HfO2 and Al2O3 have been integrated together with GdOx. The evolution of Altis CBRAM technology is shown in Fig. 2.1. First generation CBRAM consists in chalcogenides materials [36]–[38] as resistive layer, they show fast programming conditions, high window ratio and good endurance but do not stand the soldering reﬂow. In order to overcome this issue, CBRAM using metal-oxides were implemented. Typical metal-oxide materials are HfO2, Ta2O5, GdOx, Al2O3, ZrOx etc. In our work we used Cu-alloy with GdOx oxide. In order to improve the CBRAM reliability, bottom interfaces as Hf, Ti were used. In GdOx layer doped with Hf and Al, the forming voltage was reduced to around 1V [39]. Better endurance and higher ROFF were shown for bilayer devices as GdOx/Al2O3 and GdOx/HfO2. Beside the good electrical performances with GdOx, in order to target low power applications, a new technology was integrated. The metal-oxide seems to be more robust than GdOx to Break-down, improving endurance cycling and keeping stable retention.

21 2 – Overview of the studied CBRAM technology

Figure 2.1. Schematic description of the CBRAM technologies developed in Altis. 2.1 CBRAM conﬁguration

In 1 transistor 1 resistor (1T1R) conﬁguration, the CBRAM cell is integrated into the BEOL of a 130 nm CMOS technology. By controlling the gate of the transistor, we can modulate the current passing through the device. In this work we also studied mini-arrays composed of 8 WL,8 BL and a common plate or anode is in common for all CBRAM devices. Each device itself is a 1T1R. So for the same area, we can integrate more devices. Starting from 1T1R structures, macros with densities of Mbit products are shown in literature as presented in Fig. 2.2 [8].

Figure 2.2. Integration of the CBRAM cell from 1T1R to Mbit products.

2.2 Electrical characterization methodology

The first type of measurement we performed to characterize the cell consists in reading the pristine resistance at low VAnode of 0.1V. This value indicates the initial state of the metal-oxide: insulator or conductive. Also there are some criteria to be satisfied in order to be compatible with our products. The test is performed for several mini-arrays located in different positions of the 200 mm wafer. Then, a test sequence is performed in a CBRAM sample in order to evaluate the performances of the memory (Fig. 2.3).

22 2 – Overview of the studied CBRAM technology

Figure 2.3. Description of the methodology used to electrically characterize CBRAM devices.

2.2.1 Forming in QS and Pulsed Mode

In order to study the operation principle of the CBRAM cell, measurements in Quasi-static mode are performed. Once we fix the operating current (Fig. 2.4a), we can study the characteristics of the CBRAM cell as shown in Fig. 2.4b. We apply a V in the anode of the device and we read the current passing through the cell through SMUs. As the V value is increased linearly there is a transition from HRS to LRS. This is due to the redox reaction of the Cu-anode and the diffusion of Cu- ions into the electrolyte. In presence of the high electric field, the ions are reduced in the inert electrode and they form a conductive filament. Normally the pristine R is high (> GΩ, so the current in the IV measurements before forming/switching are in the order of pA down to nA and the current signal cannot be distinguished from the background noise. VF orming corresponds to the first SET operation, and it corresponds to the voltage value when switching to LRS occurs. Normally it is of the order of 2V to 3V in quasi-static (QS) mode. "Forming-free" devices would be preferred, compatible with our CMOS integrated in embedded 130nm technology. Moreover, the CMOS transistor integrated in a 130 nm technology can mantain VF orming of 3.5V in pulsed mode. If the bias polarity wass reversed, the filament dissolves, creating a gap between the bottom electrode and the remaining CF. In this case a transition from LRS to HRS occurs. The ROFF of the HRS is generally lower than RP ristine; probabily due to the remaining part of the CF [6]. During pulsed mode switching, a "smart-forming" sequence was developed to

23 2 – Overview of the studied CBRAM technology

(a) (b)

Figure 2.4. (a) Current-Voltage behavior of the studied transistor. (b) IV characteristics of the CBRAM cell, for a given programming current. overcome the variability from cell to cell and limit the energy brought to the system. Schematics illustrating of the progressive increase of VAnode in order to reach the LRS target value, called "smart-forming" is given in Fig. 2.5.

Figure 2.5. Schematics illustrating the progressive increase of VAnode in order to reach the LRS target value. This procedure is called "smart forming".

2.2.2 SET and RESET Operation SET and RESET screening experiments aim at identifying the voltages to respectively SET and RESET the CBRAM, for a given pulse time. When SET operation is performed, the cell is switched back to LRS, currents of micro to mA are recorded. In fact the ﬁlament is recreated starting from the remaining CF. This operation can be repeated many times, making the device reliable for memory applications. As we increase the applied V during RESET, ROFF increases up to a certain value, then it starts to decrease for too elevated voltages. This is called "reverse SET", since the device should be in HRS, but in fact it comes back to the LRS, as represented in Fig. 2.6a. In the case of Generation 3 metal-oxide CBRAM, a more robust behavior was demonstrated and no breakdown is noticed up to VBL−RESET of 3V. As ROFF is higher, the cell needs more V to be SET back to the LRS. In Fig. 2.6b is shown the impact of the SET voltage as a function of the HRS. When

24 2 – Overview of the studied CBRAM technology

(a) (b) (c)

Figure 2.6. (a) HRS as a function of the RESET V. (b) SET V as a function of the HRS. (c) LRS as a function of the programming current. the cell is programmed in strong HRS, it needs more V to be put back to the LRS. The relation between the LRS and the programming current is shown in Fig. 2.6c during Forming and SET operation. Screening SET/RESET parameters are done by parametric test in pulsed mode. From the graphs we can choose a trade-off between the programming conditions (VBL−SET , VBL−RESET , VWL−SET , VWL−RESET , PW during SET/RESET) for cycling endurance and data retention depending on the targeted specifications. Typical pulse duration of 1 µs are used. First the cells are formed in Pulsed mode, using a "smart forming" sequence. There is variability in terms of VF orming from cell to cell, so a progressive set starting from 2V (monolayer) or 2.5V (bilayer) up to 4V is performed in order to form the cells without stressing too much the stack. As V increases during RESET, ROFF also increases starting from LRS to HRS. While no impact is noticed in LRS 2.7b. Starting from HRS, if we increase V during SET, RON decreases abruptly up to 10th of 1 kΩ as the filament is formed 2.7a. The last screening test is done to modulate pulse duration during SET and RESET operation as shown in Fig. 2.8. The R values are presented in median and percentiles (30%, 70%).

2.2.3 Short pulse measurements

The pulsed technique allows programming at different resistance values by applying pulses of different lengths or different pulse amplitudes. If we perform measurements in pulse mode, we need the cell to operate at pulse duration down to 20ns, which makes the instrumentation itself of high importance. In general short pulse measurements are performed by applying a time defined rectangular V pulse. This technique is used to SET/RESET and Read the CBRAM device. In order to target low power applications, we performed measurements in short pulses. The energy consumption is estimated by calculating the product of the applied voltage times programming current times the pulse duration.

25 2 – Overview of the studied CBRAM technology

(a) (b)

Figure 2.7. (a) Sequence and experimental results regarding screening parameters VA and VWL during SET operation. RESET conditions are ﬁxed. (b) Sequence and experimental results regarding screening parameters VBL and VWL during RESET operation. RESET conditions are ﬁxed.

Figure 2.8. Sequence and experimental results regarding screening pulse duration during SET and RESET operation.

2.2.4 High temperature data retention

Retention measurements are performed at high temperatures in the oven, but read operation is done at room temperature (RT) and low V. It is important for the technology to maintain the information for 10 years. In Fig. 2.9 it is shown the schematics in order to program and erase the cells which will be used for data retention measurements. A schematic description of the methodology used to characterize data retention is given in Fig. 2.10. Normal operating T is 85 °C for chips in industry; we targeted HT applications so we performed measurements in high

26 2 – Overview of the studied CBRAM technology

Figure 2.9. Forming and Program/Erase sequence in order to perform data retention measurements.

T of 130 °C up to 250 °C. The parameter Nu, which is the slope of R(T) (resistance decay) or data loss factor is used quantify the data loss. To ensure 10 years, this parameter should be around 0.12-0.15. As ICC is increased better LRS retention stability is ensured, thus we performed LRS and HRS retention characteristics starting from various initial resistance value. Soldering reﬂow measurements or SMT measurements are done at 260 °C for 15 to 20 min.

2.2.5 Cycling endurance

Depending on the application, endurance requirements vary; for DRAM replacement 1 × 1015 cycles are required, while for embedded applications, the specifications vary from 1 × 103 to 1 × 106 Also the window ratio is important from the technological point of view; a large window is preferred to have tolerance for designers. In Fig. 2.11 is shown the methodology used to characterize the cycling endurance of CBRAM. Some correction algorithms are used in order to control this ratio from cycle to cycle. It may be time consuming so implementations with 2 to 3 pulse generators, applied in the VAnode, VWL, VBL during SET/RESET with short pulses are used. During each operation, the resistance is checked and if it is not in the targeted range, programming voltage is increased during SET and RESET operation. In order to identify the failure mechanism during cycling, we have defined the following parameters HB: it shows the % of the cells blocked in HRS during SET operation; BD: the % of cells which remain in LRS during HRS, HRS drif: resistance drift towards LRS as number of cycles is increased. Different programming conditions (VBL−SET , VBL−RESET , VWL−SET , VWL−RESET ) are used in order to evaluate the endurance behavior and find the best operating conditions which offer the optimum cycling behavior. In fact, as we will discuss more in details in the next

27 2 – Overview of the studied CBRAM technology

Figure 2.10. Description of the methodology used to characterize electrically the retention performance at high temperature of CBRAM technology. chapters, the programming conditions are important and determine the cycling behavior and maximum number of cycles. Another parameter we used to quantify the endurance behavior is the yield, deﬁned as the ratio between the number of cells, whose R is lower than a target RON value over the total number of tested cells. This value is calculated for all the cycles and is expressed in percentage value.

2.2.6 Pre-forming

Beside the CBRAM traditional stack, we integrated a Ti thin layer in the bottom of the metal-oxide. We claim that if a "reverse" forming operation is applied prior to a normal forming operation, the electrical behavior of the CBRAM device is improved in terms of resistance and voltage distribution, which is very important in order to overcome the variability from cell to cell. In fact, "pre-forming" operation induces the creation of oxygen vacancies in the metal-oxide (Fig. 2.12). The presence of these defects make the R lowered compared to RP ristine, but still higher than the RF orming. If a normal forming is applied afterwards, the conductive ﬁlament (CF) is made of Cu-ions and the resistance values is of the order of the RF orming. After "RESET" operation, the cell is brought to HRS [40]. Starting from pristine state

28 2 – Overview of the studied CBRAM technology

Figure 2.11. Endurance behavior for monolayer and bilayer CBRAM devices up to 1 × 105 cycles

(which it is around some 1 GΩ), a reverse bias is applied in the anode (similar to a "RESET" operation), which we will call "pre-forming". It is shown that the pristine resistance value is modulated, being similar to ROFF (around some 100 kΩ). We suppose that the presence of Ti induces oxygen vacancies in the oxide (and creates a TiOx interface!). After, a "normal" forming is applied, the oxygen vacancies facilitate the creation of the CF made of Cu-ions. The behavior is illustrated in Figs. 2.12, where pristine R, forming V and R distribution are shown for both cases.

2.3 Modeling

In order to explain and better understand the electrical results, we have developed some physical models as brieﬂy explained above.

2.3.1 2D numerical model A 2D numerical model developed in [41] was used to study the data retention behavior of Cu/metal oxide CBRAM devices. We assume that the LRS resistance is controlled by the ﬁlament width, while the HRS resistance depends on the residual

29 2 – Overview of the studied CBRAM technology

Figure 2.12. Resistance and Voltage distribution schematics when a "pre- forming" operation is done [40].

filament width and height. The filament is composed of Cu atoms regularly distributed in the resistive layer, each atom being treated independently. During bake, Cu atoms migrate following a Ficks law with a diffusion coefficient D. The local Cu concentration is locally computed in order to extract the local resistivity in every point of the electrolyte based on a semiconductor law. The cell resistance is then computed with a percolation model through a resistance network. It is thus possible to correlate the time evolution of RON and ROFF to the initial RON and ROFF values (corresponding to different filament shapes) [42]. A TAT empirical model was used to calculate the amount of current and to explain the failure mechanisms during cycling for HRS CBRAM technology. The ROFF decreasing during cycling can be explained by two mechanisms: defect generation and accumulation of Cu residual atoms (residual filament) in the resistive layer. In the case of the mono-layer CBRAM, we assume that the defects created in the metal oxide are at the origin of the endurance degradation. This model will be used in Chapter 4 to analyze the electrical results.

30 Chapter 3

CBRAM - Study of Data retention

In this chapter, we investigate the high temperature behavior of oxide-based conductive bridge memories. A methodology to optimize both high and low resistance states stability is presented. A numerical model is developed able to simulate the filament dissolution over time. This allows us to establish a clear correlation between the filament morphology and the ON/OFF states stability. It is shown that the optimization of the memory programming conditions leads to a stable memory window up to 250 °C. The CBRAM technology is highly promising as future non-volatile memories in general purpose micro-controllers (MCU) due to its low operating voltages, fast switching behavior, low integration cost and good CMOS compatibility. Nevertheless, in order to enable the technology, the high temperature stability must be addressed (in particular, to demonstrate data integrity after the peak temperature of reflow soldering). In this chapter, the role of SET and RESET conditions on retention behavior (data loss rate and activation energy) is clarified. We show that optimization of the programming conditions can drastically enlarge the high temperature memory retention. The experimental data are explained by means of numerical simulations, demonstrating a clear correlation between the filament morphology/dissolution rate and the memory operating conditions.

3.1 State-of-Art: Data retention study of CBRAM technology

In this section, an overview of the retention study of RRAM will be given. Two main methods are usually adopted to accelerate data retention, either an accelera- tion by mean of an electric ﬁeld [43], or a temperature activation [44]. We mainly used for our studies the second method, where the device behavior is studied at diﬀerent temperatures and by the means of Arrhenius plot, the temperature which ensures 10 years data retention is extracted. A summary of the literature review regarding data retention measurements and methodology is shown in Fig. 3.1. The

31 3 – CBRAM - Study of Data retention

Figure 3.1. Summary of the literature review on data retention regarding RRAM technology [45], [43], [41], [46], [44]. device parameters extracted from each work are: forming, SET/RESET voltage and current, endurance, thermal stability, physical model description, applications and improvement that they propose to improve retention degradation. In Fig. A.5, the strong dependence of the programming window on the measuring

32 3 – CBRAM - Study of Data retention

Figure 3.2. Window ratio as a function of temperature for diﬀerent ReRAM technologies. As the temperature is increased, the window margin is de- creased. By integrating a thin interface layer, the window is increased of almost 1 decade [8], [37], [39], [47]–[64].

T appears, with neglecting the impact of the baking time (normally more than 24 hours) and program/erase conditions. Each point corresponds to a given technology, considering CBRAM and RRAM in general [8], [37], [39], [47]–[64]. The graph explains the trade-oﬀ between the endurance and the thermal stability. As we can notice, as the temperature is increased, the window margin starts to decrease from 6 decades to almost 1 decade. If strong conditions are used to cycle the device (to achieve high programming window), less stability in temperature is noticed. In our case, we have integrated a thin insulating layer on top of the metal-oxide, in order to improve this margin of 1 decade and thus achieving stable retention properties at 250 °C, result which we will discuss in next chapter.

3.2 Sample description

The CBRAM technology studied in this work is composed of a Ta/GdOx/CuTeGe/TiN stack as shown in Fig. A.6a [65]. The memory cell consists in a resistor plus a transistor used as selector (1T1R). Typical IV switching characteristics (Forming, SET and RESET) in quasi static modes are illustrated in Fig. A.6b. In the following, the experiments are performed in pulsed mode.

33 3 – CBRAM - Study of Data retention

(a) (b)

Figure 3.3. (a) CBRAM cell schematics for 1T1R structures. (b) Typical IV characteristics for CBRAM structure during Forming, SET and RESET operations. 3.3 Methodology

ON and OFF states retention characteristics were measured at various temperatures 130 °C-300 °C with several SET and RESET conditions, resulting in a large range of initial RON and ROFF values. The operating current provided by the selector transistor controls the Low Resistance State (LRS), while the RESET conditions (voltage and pulse time) modulate the High Resistance State (HRS). Results reported in this paper correspond to the average over 100 cells. In Fig. 3.4 it is shown the ﬂowchart in order to explain the "smart forming sequence" and the method to program the cell in LRS and HRS before the retention measurements. During "smart forming" we follow a read-write-read sequence, each time increasing progressively the voltage amplitude (from 2V to 3V) and compare with the target LRS (in our case this values is around 35 kW. Then 2.5 cycles are performed in cells which we want to program in LRS and 3 cycles in cells we want to program in HRS. After the devices are put in the oven at high temperature and we monitor the resistance value in logarithmic values of time up to 24 hours total measured time. The slopes of the LRS/HRS (time) retention characteristics (plotted in log-log scale) are extracted, leading to vON and vOFF parameters, respectively (Fig. A.8). The higher vON and |vOFF|, the worse is the retention time. From the graph in Fig. A.8 we have extrapolated the parameter vON. This parameter describes the drift coeﬃcient, it can qualitatively express the loss of data retention as a function of time [42]. This is given by a power law as follows:

v R = R0 · (t/t0) (3.1) If we suppose a factor 10 of R , the calculated drift coeﬃcient after 1 × 105 s R0 corresponds to a value around 0.15 - 0.2. Above this value, the retention behavior

34 3 – CBRAM - Study of Data retention

Figure 3.4. Diagram explaining the methodology in order to study data retention of HRS and LRS. The programming sequence for "smart forming" and SET/RESET is shown on the right.

Figure 3.5. Measured LRS and HRS retention characteristics at 200° corresponding to a compliance current ISET= 100 µA. The parameter vON and vOFF are extracted for each case. They follow a power law. is stable and below this value the retention behavior is unstable.

3.4 Numerical model

2D numerical simulations of the filament dissolution were performed to understand the experimental retention results. We assume that the LRS resistance is controlled by the filament width, while the HRS resistance depends on the residual filament width and height (Fig. A.7). The filament is composed of Cu atoms regularly distributed in the resistive layer, each atom being treated independently. The Cu

35 3 – CBRAM - Study of Data retention

Figure 3.6. LRS and HRS filament configuration used for retention simulations. Assuming a Ficks law for Cu diffusion during bake, local Cu concentration and cell resistance are computed with a percolation model. concentration in the filament is adjusted in the x-axis in order to take into account the cylindrical shape of the filament: indeed, Cu concentration is higher in the center of the filament than close to the edges. This correction factor allows us to use 2D simulations, emulating a 3D filamentary behavior. During bake, Cu atoms migrate following a Ficks law with a diffusion coefficient D. The local Cu concentration is locally computed in order to extract the local resistivity in every point of the electrolyte based on a semiconductor law. The cell resistance is then computed with a percolation model through a resistance network. It is thus possible to correlate the time evolution of RON and ROFF to the initial RON and ROFF values (corresponding to different filament shapes). The equations are reported above:

dx, y = sqrt(2 · D) · Rand(x, y) (3.2) where D = D0 · exp(−EA/k · T ) (3.3)

D is the diffusion coefficient, EA is the activation energy, D0 is the diffusivity pre-factor, T is the temperature and ρ is the local resistance calculation, which follows a semiconductor law as shown above:

ρ = 1/σ = 1/(q · n · µ) (3.4)

3.5 Results and discussion

3.5.1 LRS ON state retention curves are plotted in Fig. A.9 for various SET conditions, leading to an initial RON spread of more than 2 decades. The lower the initial resistance,

36 3 – CBRAM - Study of Data retention

Figure 3.7. Simulated and measured LRS characteristics at 130° for various initial RON corresponding to compliance currents ISET ranging from20 µA to 200 µA. High ISET corresponds to more stable LRS.

(a) (b)

Figure 3.8. (a) Simulated and measured LRS slopes (νON) extracted from retention at 130° as a function of initial RON.A νON of 0.15 is assumed to ensure sufficiently large memory window after 10 years at 130°. Stable LRS are thus observed up to 100 k W. (b) Slope (νON) of LRS retention at 130° as a function of ROFF (before SET). No clear correlation between νON and ROFF appears. the higher is the LRS stability. It can be noticed that the experimental curves are well reproduced by our numerical model. This result is confirmed by the decrease of νON as the initial RON decreases (Fig. A.10a). In particular, the experimental data 5 and the model indicate that when RON< 1 × 10 , the filament is sufficiently thick to be stable over time. For higher RON, the percolation becomes dominant and the filament is more sensible to the Cu diffusion in the electrolyte during bake, leading to LRS instability. Finally, it appears that νON is completely uncorrelated to the previous OFF state resistance (Fig. 3.8b).

37 3 – CBRAM - Study of Data retention

(a) (b)

Figure 3.9. (b) νOFF parameter corresponding to the HRS and its dependency on the ROFF. (b) Slope of HRS (νOFF) as a function of ROFF at 130°. In the inset the retention characteristics with diﬀerent initial ROFF are shown. Higher initial ROFF shows better retention behavior.

3.5.2 HRS

In Fig. A.11b, we plotted the measured and simulated HRS retention characteristics for various initial ROFF obtained by adjusting the RESET voltage (smart RESET). It appears that a higher ROFF leads to a more stable HRS and a lower νOFF. We claim that the height of the remaining filament in the electrolyte is reduced as the RESET conditions are strengthened. Thus, this leads to a larger gap between the remaining filament and the Cu-based top electrode, which prevents the reconstruction of a conductive path during bake. Then, we looked at the impact of RON value on the HRS stability (Fig. A.10b). We show that, for a given initial ROFF, the HRS stability is degraded when the memory has been previously SET to a low RON. To confirm this trend, Fig. A.11a reports νOFF as a function of RON. Both experiments and simulations exhibit a higher slope (corresponding for HRS to a stable behavior) as RON increases. This can be explained as follows: a lower RON leads to a thicker remaining filament, yielding to more Cu atoms in the filament able to reconnect to the top electrode.

The retention characteristics at 130° with ISET = 80 µA are shown in Fig. 3.11. Almost 3 decades are maintain stable in median ROFF /RON value for 24 hours retention time. In Fig. A.12a it is represented the soldering reflow profile. The measurement is done at T = 260 °C for 15 min. The resistance distribution before and after soldering reflow is shown for LRS and HRS in Fig. A.12b. Both states show stable SMT behavior.

38 3 – CBRAM - Study of Data retention

Figure 3.10. Retention characteristics for same initial ROFF but programmed with diﬀerent LRS conditions.

Figure 3.11. Retention characteristics for LRS and HRS at 130° for ICC=80 µA.

3.5.3 Temperature activation

ON and OFF states retention characteristics were measured at various temperatures (85°- 300°) with ISET equal to 30 µA ,80 µA and 100 µA (Fig. A.14). The failure time criterion was ﬁxed to a critical variation ROFF/RON of a factor 2 (Arrhenius graphs in Fig.A.15). Using a low programming current, LRS is controlling the lifetime while for high ISET HRS plays the critical role. Moreover, we can notice that the maximum operating temperature for 10 years retention has drastically increased for higher SET currents (250° for ISET =80 µA ).

39 3 – CBRAM - Study of Data retention

(a) (b)

Figure 3.12. (a)Soldering reﬂow proﬁle. The measurements were done at 260 °C for 15 min. (b) Cumulative distribution CDF of the LRS and HRS before and after soldering.

Figure 3.13. LRS and HRS retention characteristics at various temperatures (130° to 300°), with initial programming currents ISET equal to 80 µA or 100 µA.

3.5.4 Trade-oﬀ "retention vs. consumption"

Figure A.13 summarizes the νON and νOFF slopes extracted during retention measurements at 130° as a function of the programming current ISET. A |νmax| value of 0.15 is represented in the graph, and corresponds to an arbitrary maximum v to

40 3 – CBRAM - Study of Data retention

Figure 3.14. Slopes (νON) and (νOFF) of LRS (square) and HRS (circle) as a function of the ISET used to set the initial RON during retention at 130°.A νMAX of 0.15 is assumed to ensure sufficiently large memory window after 10 years data retention. A stable operating window during retention thus appears when ISET currents between 30 µA and 200 µA are used. ensure sufficiently large memory window after 10 years at 130°. This graph allows us to identify an optimum operating window for this technology between 30 µA and 100 µA, thus confirms the low-power potential of the CBRAM technology. It should also be noticed that this window can be further enlarged by increasing the RESET conditions (and thus the ROFF), allowing to reduce νOFF without degrading LRS stability. For a low programming current (Fig. A.15), LRS is controlling the lifetime while for high ISET HRS becomes the limiting point. Moreover, we can notice that the maximum operating temperature for 10 years retention is drastically increased for higher SET currents. Thus, one should keep in mind that in resistive memory technologies, activation energies and operating temperatures are strictly correlated to the SET and RESET programming conditions.

3.6 Conclusions

In this chapter an overview of the state-of-the-art of CBRAM data retention behavior at high temperatures was shown. Both experimental results and models were used to explain retention loss for different CBRAM technologies. Arrhenius plot was used to extract the temperature which ensures 10 years data retention. Program- ming algorithms were proposed in order to improve the retention characteristics. In temperature accelerated testing, retention time decreases with decreasing size of CFs, which is associated to the diffusion of vacancies/ions from CFs during high- temperature baking. These filaments can be weaker or even broken during the baking process, which leads to RON increase and retention failure, and the filaments can be

41 3 – CBRAM - Study of Data retention

Figure 3.15. Time-to-fail Arrhenius plot for three ISET equal to 30 µA, 80 µA and 100 µA. The retention capability of 10 years is extrapolated at 50° for 30 µA and 250° for 100 µA. For this figure, fail time criterion corresponds to a variation of ROFF/RON of a factor 2. ruptured easier as temperature is increased. The SET and RESET algorithms are a single voltage pulse (SVP) and a ramped pulse series (RPS: write-verify-write) mode. Also a trade-off between SET and RESET programming conditions is suggested. Some groups proposed two engineering techniques of Cu-alloy active electrode to improve bridge’s robustness, and anti-Cu diffusive inert electrode to suppress Cu diffusion from the bridge. Ru alloy is recognized as a candidate of future barrier metals for Cu interconnects because of low resistivity and good adhesive strength to the Cu. The trade-off between the endurance and the thermal stability was elucidated. If strong conditions are used to cycle the device (in order to achieve high programming window), less stability in temperature is noticed. We demonstrated that the programming conditions in oxide-based CBRAM can be optimized in order to achieve low power SET current (30 µA) and moderate temperature window operation, or stable 250° behavior and 100 µA SET current. Based on experimental data and simulations, the physical mechanism governing retention failure of oxide-based CBRAM was clarified. In particular, a clear correlation between the filament shape (depending from SET and RESET conditions) LRS and HRS thermal stability was established.

42 Chapter 4

Bilayer devices to improve memory performances

In this chapter, a detailed reliability analysis of metal-oxide CBRAM devices is presented. We demonstrate that the addition of a thin metal-oxide layer in the bottom of the memory stack signiﬁcantly increases the ROFF and the memory window (more than 1 decade), with improved endurance performance. At the same time, high thermal stability is also achieved (window margin constant during more than 24 hours at 250 °C). The origin of the window margin degradation during endurance is discussed and interpreted by means of a Trap Assisted Tunneling (TAT) Model, putting in evidence the role of defect generation and Cu residual atoms in the resistive layer.

4.1 State of Art: Electrical performances of bilayer metal-oxide RRAM

4.1.1 Gd2O3/(10%) Cu-MoOx, Yoon et al., Microelec. Eng. 2009 The device shows both unipolar and bipolar switching behavior. Based on the switching characteristics, they show that it is a ﬁlamentary conduction. In Fig. 4.1 it is illustrated the device behavior during forming and SET/RESET operation [66].

Data retention High temperature range of 200 °C - 250 °C was measured. In this work they read failure time that changes the state to HRS. In other word, the composed copper ﬁlament path is disconnected by copper ion movement at high temperature. Based on the Arrhenius plot, the activation energy is about 1.4 eV which is comparable to that of Cu electro-migration.

43 4 – Bilayer devices to improve memory performances

Figure 4.1. Device behavior during forming and SET/RESET operation in Gd2O3/(10%) Cu-doped MoOx.

Figure 4.2. Retention behavior of the RRAM device.

4 Endurance Endurance up to 1 × 10 cycles was demonstrated at VSET /VRESET of 2V/-2V, 1 µs programming conditions. Read operation was done at 0.1V.

Application It is claimed that the dual-layer oxide Gd2O3/(10%) Cu-doped MoOx RRAM is a promising technology for potential for future high density memory applications.

4.1.2 HfOx/AlOx RRAM, Yu et al., VLSI-TSA 2011 Yu et al., presented HfOx/AlOx bi-layer RRAM devices. TiN is regarded as an oxygen reservoir and can provide a source of oxygen migration. Thus, usually RRAM devices with TiN as electrode show the bipolar switching behavior. The ﬁrst SET

44 4 – Bilayer devices to improve memory performances

Figure 4.3. Retention behavior of the RRAM device. operation called forming corresponds to 8V. The mechanism of resistive switching (RS) in metal oxides has been widely attributed to the formation/rupture of conductive ﬁlaments (CFs) which may consist of oxygen vacancies. It was suggested that the diﬀusion of Al atoms into HfOx could stabilize the CFs to reduce the ran- domness of RS. Because the reset process usually can only rupture the upper part of the CFs, the so-called "virtual cathode" in the bottom AlOx layers tends to serve as the seeds the re-grow the CFs. [67]. In Fig. 4.4 it is shown the bilayer behavior during forming and SET/RESET operations.

Figure 4.4. Device behavior during forming and SET/RESET operation.

Endurance About 1 × 106 cycles have been obtained before the resistance window collapses as represented in Fig. 4.5. The failure at LRS indicates that there are

45 4 – Bilayer devices to improve memory performances eventually too many oxygen vacancies in the oxides that not suﬃcient oxygen ions can return from TiN.

Figure 4.5. Endurance behavior of HfOx/AlOx bi-layer RRAM devices.

Multi-level operation One method is to tune the LRS resistance by set compliance current and the other is to tune the HRS resistance by reset stop voltage with ﬁxed 50 ns pulse width but linearly increasing the pulse amplitudes from -2.3 V to -2.9 V, three distinguished HRS states were achieved as shown in Fig. 4.6a. Another method is, with ﬁxed -2.3 V pulse amplitude but exponentially increasing the pulse widths from 50 ns to 5 µs, similar three HRS states were achieved (Fig. 4.6b).

Voltage-time dilemma To obtain the same HRS resistance ( 50 kΩ) from a LRS resistance ( 10 kΩ), transient current response waveform suggests that a shorter and larger pulse (-2.3 V/50 ns) is preferred over a longer and smaller pulse (-2 V/500 ns) because of much a reduced energy consumption, although both methods were eﬀective to achieve the target resistance.

Application HfOx/AlOx bi-layer RRAM can exploit the multilevel capability of NV RRAM.

4.1.3 Ni/ HfOx/ AlOy/p+-Si, Tran et al., EDL 2011 Tran et al., reported a unipolar RRAM structure composed of Ni electrode/Ni electrode/ HfOx/ AlOy/p+-Si RRAM (depoistion of metal-oxide is done by ALD). It is

46 4 – Bilayer devices to improve memory performances

(a) (b)

Figure 4.6. (a) Method 1 consists in increasing linearly the pulse amplitude, ﬁxed pulse width. (b) Method 2 consists in increasing exponentially the pulse widths, ﬁxed pulse amplitude. feasible to employ a vertical Si diode as a selector for integration in a crossbar structure for low-cost 3-D integration and eliminate the usage of noble metals, e.g., Pt. It is worth to note that Ni has been widely used in the mainstream CMOS technology as source/drain contact material and also can be patterned using Cl2-based plasma, commonly available in foundries. As compared with RRAM with single-layer HfOx, the demonstrated HfOx/AlOy-based RRAM. [68]

Swiching properties RRAM shows VF orming of 3V, reduced set voltage (from 2.3 to 1.2 V) and reset voltage (from 1.6 to 0.4 V) as shown in Fig. 4.7, demonstrating great promise for low voltage application, a high on/oﬀ resistance ratio of 1 × 105

Figure 4.7. Switching behavior of Ni electrode/ HfOx/ AlOy/p+-Si RRAM devices.

47 4 – Bilayer devices to improve memory performances

Endurance Good uniformity of switching parameters (Vset/Vreset/HRS/LRS) was shown up to > 1 × 106 cycles in Fig.4.8.

Figure 4.8. Endurance behavior of Ni electrode/ HfOx/ AlOy/p+-Si RRAM devices.

Data retention High temperature retention (> 1 × 105 s at 120 °C), high- temperature operating stability (200 °C) without threshold resistive switching, and a fast set/reset speed of about 10/30 ns are presented in Fig.4.9.

Application Unipolar Ni electrode/ HfOx/ AlOy/p+-Si RRAM is promising for future high density crossbar NVM.

4.1.4 Pt/ZrOx /HfOx/TiN, Jung et al., APL 2010 Jung et al., demonstrated Pt/ZrOx 5 nm /HfOx 3nm/TiN bilayer devices with bipolar switching behavior.

Switching properties VF orming increases as HfOx thickness increases. While VF orming decreases for diﬀerent materials used as TE. When Zr is used as TE, VF orming is lower as shown in Fig.4.10. These results can be attributed to the different GibbâĂŹs free energy of the oxidation. By considering a Gibbs free energy balance in the interface between HfOx and top electrodes, it is acceptable that oxidation in Zr top electrode occurs more easily than in Ti and Pt top electrode. In the case of bi-layers, better R and VF orming distribution is noticed. In the case of the mono-layer structure, the active ﬁlament participating in the switching process

48 4 – Bilayer devices to improve memory performances

Figure 4.9. Endurance behavior of Ni electrode/ HfOx/ AlOy/p+-Si RRAM devices. is controlled by competition among parallel conductive ﬁlaments. However, the resistive switching of the bilayer structure is induced by a redox reaction at the tip of the local ﬁlament in the ZrOx/HfOx interface. [69]

Figure 4.10. Forming voltages as a function of electrode thickness.

49 4 – Bilayer devices to improve memory performances

Filament morphology When positive bias is applied to the uppermost Pt – electrode, O2 from HfOx moves upward and further oxidizes the upper ZrOx layer, and the oxygen vacancies simultaneously move downward. The strong local electrical field in the HfOx matrix triggers the formation of filaments that conduct oxygen vacancies and propagate in a treelike fashion from the TiN cathode to the ZrOx /HfOx interface; thus, the memory switches to the LRS. When a negative bias is applied to the uppermost Pt electrode, both the electrons injected from the uppermost electrode through the weak upper filament branches, which lead to local heating at the interface, and the repealed oxygen ions from the ZrOx layer together cause local oxidization of the branched dendrites of the filaments at the interface. Consequently, switching to the HRS is accomplished (Fig. 4.11).

Figure 4.11. Device behavior during Forming and SET/RESET operation.

Endurance Almost 1 decade is stable up to 1 × 105 cycles.

Data retention The retention characteristics are measured for the two resistance states at 85 °C. From extrapolation, we can guarantee two resistance states over ten years. As shown in the inset of Fig. 4.12 the instability in the HRS above 150 °C was observed. This implies that the reduction process occurring in the weak ﬁlaments at the tip of the local ﬁlament at the ZrOx /HfOx interface.

Application Bi-layer ZrOx /HfOx is promising for high-performance nonvolatile memory devices.

4.1.5 Pt /CuxO/ SiO2/Pt, Yi et al., NVMTS 2008 Yi. et al., presented double layered hybrid structure composed of a copper sulﬁde layer and a thin oxide CuxO and SiO2 devices.

50 4 – Bilayer devices to improve memory performances

Figure 4.12. Device behavior during Forming and SET/RESET operation.

Endurance 5nm CuxO and SiO2 shows poor endurance (Fig.4.13 and already at 200 cycles oﬀ resistance increased. This degradation seems to be occasioned by a large Cu ions bridge residue after incomplete reset process. Thicker stack of 10 nm seems to improve in endurance performance [70].

Figure 4.13. Device behavior during Forming and SET/RESET operation.

In the case of 15nm thick SiO2/copper sulfide bi-layered devices, inserting a silicon dioxide layer between top electrode and copper sulfide, increase VSET up to about - 1V. In addition, off-state resistance was increased up to 1 GΩ level even though top electrode size was about 20 µm. The device exhibits large on/off ratio 7 over 1 × 10 at - 0.2 VREAD and multi-level possibility through strong dependence of on-state resistance on programming current.

51 4 – Bilayer devices to improve memory performances

Application Double layer CuxO and SiO2 have the capability for multibit operation of NV RRAM as shown in Fig.4.14.

Figure 4.14. Device behavior during Forming and SET/RESET operation.

4.1.6 TiN/TiOx/HfOx/TiN, Chen et al., IEDM 2009 Chen et al., presented RRAM technology made of TiN/TiOx/ TiN/TiOx/HfOx/TiN RRAM array integrated into 0.18 µm CMOS technology. The devices are fabricated to study the stochastic resistance switching behavior, The addition of an AlOx buﬀer layer underneath the HfOx resistive layer enhances the read disturb immunity.

Switching properties VF orming <3V and (VSET and VRESET ) are lower than 1 V [71].

Read Disturb Since the SET process is a re-breakdown of the recovery oxide layer, the low Weibull slope is expected due to the very thin (2 3 nm) and defec- tive recovered oxide layer (Fig 4.15). An inserted AlOx buﬀer layer at the HfOx layer/TiN bottom electrode interface can improve the read disturb immunity of RHIGH . The AlOx layer can reduce the applied voltage across the HfOx layer to elevate the time-to-disturb voltage of the device to 0.5V.

Data retention Under retention test at 150 °C, the RHIGH and RLOW of this device are stable and 10-yr lifetime can be expected as shown in Fig. 4.16.

52 4 – Bilayer devices to improve memory performances

Figure 4.15. Read disturb behavior of TiN/TiOx/HfOx/TiN RRAM.

Figure 4.16. Data retention behavior at 150 °C.

Endurance These devices can exceed more than 1 × 106 times by a pulse width of 40 ns under fixed operation voltage and current. Two novel verification methods for RRAM are proposed to effectively narrow down the fluctuation of RHIGH and RLOW as plotted in Fig 4.17. By increasing progressively up the VRESET from 1.5 to 1.8 V, the RHIGH distribution becomes tight. The RHIGH value of all devices in the 1 Kb array are higher than 100 kΩ by using the VRESET of 1.8V. Regarding the LRS, the approach applies higher VSET to these devices after performing the RESET process. The maximum RLOW value of all devices is below SI10kW by this RLOW verification.

Application Bi-layer TiN/TiOx/HfOx/TiN RRAM are promising for future NV memories.

53 4 – Bilayer devices to improve memory performances

Figure 4.17. Device behavior during cycling endurance.

4.1.7 Mono and Bilayer CBRAM technology studied in this work

High temperature stability [8], [42], large window margin and good endurance [11], [10] are required for advanced non-volatile memory applications. However com- bining these critical features is challenging and requires improvements both at the technological [39], [72] and design levels [36]. In this work, we propose an optimized oxide-based CBRAM based on a bi-layer solid electrolyte [48], [70], [72]. The objective was to enlarge the insulating region when the memory is in the high resistive state, in order to improve the memory performances (memory window, thermal stability and endurance). The key features of the proposed stack will be addressed and the involved physical mechanism will be discussed. CBRAM devices studied in this paper are described in Fig. A.6a. The mono-layer CBRAM reference sample employs a metal-oxide deposited by PVD as resistive layer [42]. A metal plug acts as bottom electrode, while the top electrode consists in a CuTex-based ion sup- ply layer [11]. In bi-layer CBRAMs, 5A Al2O3 or HfO2 were deposited by ALD as bottom interface between the metal plug and the resistive layer resulting in a Ta/GdOx/Al2O3/CuTeGe/TiN and Ta/GdOx/HfO2/CuTeGe/TiN devices. Note that the memory cell consists in a selector transistor and the resistance change element (1T1R).

4.2 Results and discussions

In this section, a detailed description of the electrical results are given. All the results are obtained on 64 cells arrays. Resistance values are represented as the median, while 25%-75% percentiles are used as error bars. A speciﬁc focus is made on the MOx/Al2O3 sample which exhibit the most promising results.

54 4 – Bilayer devices to improve memory performances

Figure 4.18. Schematic of CBRAM resistors studied in this work (the CBRAM cell being a 1T1R structure) We have studied monolayer and bilayer devices.

4.2.1 Quasi - static measurements

In Fig. 4.19a and Fig. 4.19b the resistance in the pristine state (R0) measured at low VREAD=0.1V with forming voltage VF orming in quasi-static mode are respectively shown for the mono-layer and bi-layers CBRAM devices. It appears that the bilayer sample exhibits an increased R0 (> 1 GΩ) and VF orming with respect to the mono-layer reference. Moreover, higher R0 and VF orming are measured with Al2O3 bottom interface, due to the higher dielectric constant of Al2O3 compared to HfO2. One should also notice that a 48A mono-layer CBRAM still exhibits lower R0 and VF orming than the bi-layer, despite the same physical thickness of the total stack. Current- voltage characteristics during forming and SET/RESET operations are shown in Fig. A.16a for the monolayer device and in Fig. 4.20b and Fig. 4.20c for bilayer devices. We can notice that for three samples a higher voltage is required during Forming, around 2.5V for the bilayers and 1.2V for the monolayer GdOx. SET voltage also is around 1V. The current during SET and RESET are about 100 µA.

4.2.2 Pulsed - mode measurements Pulsed mode measurements were performed in order to evaluate the memory switching speed. In Fig. 4.21a and Fig. 4.21b we started from the Low Resistive State (LRS) and applied RESET pulses of 1µs, gradually increasing the RESET word line

55 4 – Bilayer devices to improve memory performances

(a) (b)

Figure 4.19. (a) Fresh resistance values for the CBRAM devices studied in this work. (b) Mean values and standard deviations of forming voltages for diﬀerent CBRAM samples.

(a) (b) (c)

Figure 4.20. (a) IV characteristics for monolayer GdOx devices formed and set at VWL = 1V and reset at VBL = 1.2V . (b) IV characteristics for bilayer GdOx/AlOx devices formed and set at VWL = 1V and reset at VBL = 1.2V . (c) IV characteristics for bilayer GdOx/HfO2 devices formed and set at VWL = 1V and reset at VBL = 1.2V .

(VWL) or bit line (VBL) voltages. Between each RESET operation, the CBRAM is set back to the ON state. Cells are reset for lower voltages (VBL 1.2V) on the mono-layer reference due to the thinner stack, but at higher voltages (VBL >1.6V) a larger window margin is reached on the bi-layer CBRAM (more than one decade of gain). In Fig. 4.22a and Fig. 4.22b we start from the High Resistive State (HRS) and gradually increase VWL or VBL−SET . Similar RON and VSET are obtained at the 1st order between mono and bi-layers CBRAM. Impact of the pulse width is represented in Fig. A.20a, A.20b for MOx/Al2O3 CBRAM, indicating typical voltages of 2.2V and -1.5V to SET and RESET 99.9% of the cells at 1µs, respectively.

56 4 – Bilayer devices to improve memory performances

(a) (b)

Figure 4.21. (a) RON as a function of SET VWL for the 3 studied samples (1 µs pulses). ROFF between each RESET cycle is also represented. (b) RON as a function of SET VBL−SET for the 3 studied samples (1 µs pulses). ROFF between each RESET cycle is also represented.

(a) (b)

Figure 4.22. (a) ROFF as a function of RESET VWL voltage (1 µs pulses) for the 3 studied samples. RON between each RESET cycle is also represented. (b) ROFF as a function of RESET |VBL−RESET | voltage (1 µs pulses) for the 3 studied samples. RON between each RESET cycle is also represented.

4.2.3 Data retention

Data retention characteristics are reported at 200 °C for the 3 samples in Fig. 4.24a and Fig. A.29b. Both HRS and LRS show a stable behavior. The programming conditions during SET are: VWL−SET =1V, VA=2V (monolayer) and 2.5V (bilayer) and pulse duration is 1 µs. While during RESET operation: VWL−RESET =2.5V, VBL=2V (monolayer) and 1.7V (bilayer) and pulse duration is 1 µs. It is important

57 4 – Bilayer devices to improve memory performances

(a) (b)

Figure 4.23. (a) Distribution in normal scale of RESET cells as a function of the pulse voltage for MOx/Al2O3 CBRAM. (b) Distribution in normal scale of SET cells as a function of the pulse voltage for MOx/Al2O3 CBRAM.

(a) (b)

Figure 4.24. (a) CDF distribution of LRS and HRS retention characteristics at 200 °C. (b) CDF of LRS and HRS for the initial and ﬁnal baking time for mono and bilayer devices. to note that the window margin gain obtained with bilayers remains stable over 5 time, even after 1 × 10 s bake time. No activation is measured on MOx/Al2O3 samples up to 250 °C (Fig. 4.25).

58 4 – Bilayer devices to improve memory performances

Figure 4.25. Retention behavior of metal-oxide CBRAM both in LRS and HRS for mono and bi-layer at 250 °C.

4.2.4 Endurance

CBRAM endurance requires careful optimization and analysis to reach high performance characteristics. In this work, three main mechanisms were identified as responsible for the decreasing of the window margin during cycling (Fig. A.21): HRS drift (decrease of ROFF mean value), breakdown (R stuck in the LRS after RESET), and unefficient SET (R stuck in HRS after SET). In order to optimize the endurance characteristics, SET and RESET voltages were adjusted to limit these phenomena. Fig. A.22a reports the impact of RESET VBL: increasing VBL−RESET improves the window margin (red curve) but increases the percentage of broken cells after 1 × 103 cycles (blue curve). Concerning SET ( Fig. A.22b), unsufficient VBL−SET results in a high percentage of cells stuck in HRS (red curve), while increasing VBL−SET too much results in larger number of broken cells (blue curve). Based on this preliminary study, we could determine the best SET/RESET conditions for each CBRAM sample. The programming conditions during SET are: VWL−SET =1V, VA=2V (monolayer) and 2.5V (bilayer) and pulse duration is 1 µs. While during RESET operation: VWL−RESET =2.5V, VBL=2V (monolayer) and 1.7V (bilayer) and pulse duration is 1 µs. Endurance characteristics are reported on Fig. A.23a for mono and bi-layer devices. A clear improvement of the endurance characteristics is obtained when bi-layers are integrated as resistive layers, with more than one decade between LRS and HRS after 1 × 105 cycles. Part of this improvement can be explained by the fact that for a fixed memory window, lower operating voltages are required to SET/RESET bi-layer CBRAM, reducing the gradual degradation of the memory stack during cycling. In all samples, a progressive drift of the HRS resistance appears during cycling. It can be noticed better in Fig. A.23b, as the

59 4 – Bilayer devices to improve memory performances

number of cycle increases, ROFF decreases and and also BD rate increases. This results in closing the memory window and degradation of the endurance.

Figure 4.26. HRS and LRS normal distributions illustrating the deﬁnition of breakdown rate (BD), cells stuck in HRS (BH) and HRS drift.

Given the endurance characteristics for both monolayer and bilayer devices, the switching yield is calculated for both LRS and HRS. The yield is deﬁne as the percentage of cells which switch given the SET and RESET RON and ROFF criteria respectively, over the total number of tested cells. These values are calculated for

(a) (b)

Figure 4.27. (a) Percentage of broken cells (BD) and window margin (Ratio) in function of VRESET after 1000 cycles for MOx/HfO2 CBRAM. (b) BD and HB rate versus VSET at ﬁxed |VBL−RESET | =1.75V after 1000 cycles for MOx/HfO2 CBRAM.

60 4 – Bilayer devices to improve memory performances

(a) (b)

Figure 4.28. (a) Endurance characteristics of mono and bi-layer are shown. Bi-layer devices exhibit up to 1 × 105 cycles with stable one decade OFF/ON. (b) CDF of R as the number of cycles increases from the 1st to 1 × 105 thcycle for both LRS and HRS.

(a) (b)

Figure 4.29. (a) Yield of LRS defined as the percentage of cells which switch given the SET RON criterion. (b) Yield of HRS defined as the percentage of cells which switch given the RESET ROFF criterion. each cycles. As seen in Fig. 4.29a, LRS yield is better for LRS in bilayers. This is due to a bit lower RON value, which satisfies better the criteria. Fig. 4.29b shows a good yield of above 80% for mono and bilayer devices up to 1000 cycles. After monolayer devices show worse yield due to a higher degradation of HRS during cycling.

61 4 – Bilayer devices to improve memory performances

4.2.5 Modeling and discussion In order to analyze the origin of the HRS resistance drift during cycling, we performed a âĂĲsmartâĂİ RESET sequence after cycling. In particular, RESET pulses of 1µs are applied, progressively raising the VBL amplitude from 1.5V to 2.5V, until a targeted resistance value is reached. The experiment was performed on both mono and bilayer CBRAM. Fig. A.24b shows the resistances after the 1st cycle, 1 × 104 cycles and after the smart RESET sequence. It appears that the smart RE- SET allows to completely recover the initial ROFF value in the case of MOx/Al2O3 bi-layer CBRAM. On the other case, the resistance drift is irreversible on the monolayer reference, regardless of the applied RESET voltage [73].

Figure 4.30. LRS and HRS resistances for mono and bilayer CBRAM after the ﬁrst reset and after 10 kcycles. Using a smart reset in the last cycle allows to recover initial ROFF in case of the bilayer.

Based on these data, we propose the following interpretation (Fig. A.25). The ROFF decreasing during cycling can be explained by two mechanisms: defect generation and accumulation of Cu residual atoms (residual ﬁlament) in the resistive layer. In the case of the mono-layer CBRAM (Fig. A.25a), we assume that the defects created in the metal oxide are at the origin of the endurance degradation. In the case of bi-layers (A.25b) we have in addition Cu accumulation in the bottom interface which reduces the ROFF value close to that of the mono-layer reference. Applying a smart RESET to the bi-layer, Cu can be removed, increasing the insulating gap in the resistive layer and the corresponding HRS resistance. Thus, ROFF can recover its initial value as shown previously (Fig. A.24b). Consequently, using a smart RESET procedure during cycling allows to maintain a constant memory 5 window of 2 decades for 1 × 10 cycles (Fig. A.26a) in MOx/Al2O3 CBRAM. The applied voltages during smart SET and RESET operation are shown in Fig. A.26b.

62 4 – Bilayer devices to improve memory performances

We can notice a progressive increase of RESET voltage from -1.5V to -2V in order to maintain a stable HRS over time. After 1000 cycles, a correction in VSET is also done to compensate the impact of RESET.

Figure 4.31. Schematic description of the defect generation and Cu accumulation in the resistive layer for the HRS degradation during endurance for mono (a) and bilayer (b) CBRAM. tox is the dielectric thickness, tb is the barrier thickness and NT is trap volume density. In the case of bilayers we assume a residual Cu ﬁlament in the bottom layer which can be removed by applying a smart erase as seen in Fig. A.24b.

To describe the endurance characteristics, we used an empirical model that cor- relates the resistance of the solid electrolyte to the volume trap density NT (see Fig. A.27a) as shown below: [74].

(a) (b)

Figure 4.32. (a) Smart endurance characteristics for MOx/Al2O3 CBRAM. (b) Applied smart SET and RESET voltages during cycling.

63 4 – Bilayer devices to improve memory performances

(a) (b)

Figure 4.33. (a) Fitting and experimental endurance characteristics. (b) Num- ber of traps as a function number of cycles for 3 samples using the formula a NT = A · [log(#cycles)] + B, a=3.

RHRS(NT , tb) = RLRS · (Π/2 · σT · NT · λ · exp(−(Erel/4KT ) + (tb/2λ))+ −1 + exp(−tb/λe)) (4.1)

Where σT is the trap cross section, λ and λe is the tunneling constants, Erel is the relaxation energy for charged traps and k,T are Boltzmann constant and temperature. Increasing NT gives rise to a higher leakage current after RESET, thus yielding to a lower ROFF . Based on this equation, we ﬁtted the ROFF evolution and drift during endurance without any smart correction scheme (see Fig. A.27a). The corresponding trap density NT is found to follow a power law in function of the a cycle number # cycle: NT = A · [log(#cycles)] + B, a=3. The A parameter (trap generation rate) is reduced by more than a factor 2 when a MOx/Al2O3 bi-layer is used with respect to the mono-layer reference (Fig. A.27b). Finally, based on the model, we estimated the trap and Cu contributions to the ROFF drift by comparing the ROFF values after cycling with and without ﬁnal smart RESET (Fig. A.28). MOx/Al2O3 bi-layer reduces the generated trap density of 50% compared to the mono-layer reference.

4.3 Conclusions

In this chapter, we proposed bilayer CBRAM devices able to improve the memory performances. As seen in the literature, bilayers oﬀer better read disturb immunity,

64 4 – Bilayer devices to improve memory performances

Figure 4.34. Number of traps calculated for each sample using the empirical TAT model, ﬁxed tb=1.5nm. Relation of R in function of Nt is calculated according to [74].

Traps after 1 × 104 cycles (× 1 × 1021 cm−3) Ndefects remaining NCu removed Sample NT = Ndefects+ NCu after smart Reset by smart Reset MOX 4.4 4.4 0 MOX /Al2O3 3.2 0.8 2.4 MOX /HfO2 3.3 3 0.3

Table 4.1. Number of traps calculated for each sample using the empirical TAT model, ﬁxed tb=1.5nm. Relation of R in function of NT is calculated according to [74].

higher ROFF and better endurance or data retention depending on the technology with respect to monolayer CBRAM devices. These improvements were explained by the formation mechanisms of CF in the resistive layer or bottom interface. Al- gorithms to improve programming window were proposed, either by fixing RESET amplitude and varying pulse duration, either by fixing RESET pulse duration and increasing voltage amplitude. A trade- off between these parameters can give the best performance. In our work we integrated thin layer of HfO2 or Al2O3 with GdOx. The window margin is increased of more than one decade and shows stability up to 1 × 105 s at 250 °C for the bilayer devices. An endurance of 1 × 105 cycles is achieved. An empirical model is proposed to compute the OFF state resistance (HRS) drift

65 4 – Bilayer devices to improve memory performances during cycling. The gradual defect generation and Cu accumulation in the electrolyte are taken into account and decorrelated. In conclusion, the integration of a bottom interface in a CBRAM device allows to reduce the defect concentration of 50%, thus improving the memory window and endurance characteristics.

66 Chapter 5

Generation 3 metal-oxide CBRAM technology compatible for low power applications

In this chapter we will focus on a new CBRAM technology which has the advantage of short pulse programming and low power consumption. The details will not be revealed due to the conﬁdential policies of the company. We will be mostly focused on the methodology in order to characterize the technological performances and the electrical properties of the tested devices. The structure remains a MIM stack, but both IBL and RL has been changed compared to the second Cu/metal-oxide CBRAM generation. The devices are integrated in the BEOL of the CMOS transistor. Miniarrays macros are composed of 64 bits each. Within a wafer, more than 100 arrays are measurable, providing satisfying statistical data.

5.1 State of Art: Advantages of the new technology to be compatible with IOT applications

CBRAM is more and more near to the commercialization. Some issues are the trade- oﬀ between programming current and data retention. Jameson and Kamalanathan reported a ZrTe/AlOx/Ta structure, where ZrTe is thought to be suitable for making subquantum CBRAM cells [75]. RRAM are suitable for low power applications due to low programming voltages (less than 3V) and short programming pulses (of the order of ns) [5], [20]. The energy of the Te-based CBRAM (of the order of 0.1 to 10 pJ/cell) is 10 times lower compared to the 2nd generation metal-based CBRAM (1- 100 pJ/cell). Already some products regarding the new generation CBRAM called Maveriq are presented by Adesto [76] in the market. A motivation for material engineering can be the diﬃculty to integrate Cu into the device and the need to be

67 5 – Generation 3 metal-oxide CBRAM technology compatible for low power applications compatible with the stringent demands for low power applications as IOT.

5.2 Technological details, set-up and methodology

Measurements are performed both in quasi-static and pulsed mode for 1T1R devices and miniarrays. One miniarray contains 64 bits of 1T1R each. The detailed methodology to characterize the device is given in chapter 2 and is based on forming, endurance and data retention measurements. Diﬀerent programming conditions during SET and RESET are used and their impact on device performance and reliability are studied. As mentioned before, this technology is suitable for low-power applications. 1T1R devices were measured at 20 ns pulse widths. In order to characterize miniarrays, the signal has to pass through the switching matrixes, which limits the correct measurements up to 100 ns. The schematic of the set- up is shown in Fig. 5.1 for 1T1R and in Fig. 5.2 for miniarrays.

Figure 5.1. Set-up in order to measure 1T1R structures with 4 terminals, SMUs are connected respectively to the Anode and BL, during Pulse mode measurement the output of the pulse generator is connected to WL and the signal GND is common to all other signals.

5.3 Experimental Results

5.3.1 Quasi - static measurements In Fig. 5.3a the pristine resistance is shown for all the dies within a 200 nm wafer. The read measurements are done at low read voltages of 0.1V. In Fig. A.30a is shown the CDF of pristine resistance for 6 miniarrays. The median value is around 200 MΩ and is comparable between 1T1R and miniarrays. Typical current-voltage characteristics are shown in Fig. 5.4 for VWL−SET =1V (corresponding to 100 µA). We can extract the forming, SET and RESET currents

68 5 – Generation 3 metal-oxide CBRAM technology compatible for low power applications

Figure 5.2. Set-up in order to measure mini-arrays structures with 17 terminals (8 BL, 8 WL, 1 common plate).

(a) (b)

Figure 5.3. (a) Pristine resistance distributed in 200 nm wafer to evidence the uniformity from die to die in 1T1R conﬁguration. (a) CDF distribution for pristine resistance of Gen. 3 CBRAM measured in mini-arrays. Pristine resistance is of the order of few GΩ and is comparable between 1T1R and mini-arrays devices.

and voltages. VF orming is almost 2.5V and VSET is around 1.5V. Reset voltage is less than 1V. Impact of compliance current on LRS starting from pristine state and gradually increasing the current up to LRS saturation values is shown in Fig. A.31a. Typical LRS are around 10 kΩ. Impact of RESET voltage on the HRS and LRS is shown in Fig. A.31b. First a progressive reset is done, starting fro low V and increasing VBL−RESET up to 3V (deﬁned as bottom-up), while the top-down method consists in starting from high VBL and decreasing progressively its value up to 0.5V. No break-down or parasitic reverse SET are noticed for HRS up to 3V, conﬁrming the

69 5 – Generation 3 metal-oxide CBRAM technology compatible for low power applications

Figure 5.4. Typical IV characteristis of Gen.3 CBRAM evidencing Forming and SET/ RESET voltage and current.

(a) (b)

Figure 5.5. (a) Impact of compliance current on LRS starting from pristine state and gradually increasing the current up to LRS saturation values. (b) Impact of RESET voltage on the HRS and LRS. No break-down is noticed for HRS up to 3V. robustness of the metal-oxide. Typical HRS are of the order of 1 MΩ. LRS also increases for V higher than 1V. In fact as higher reset voltage are used, it is more diﬃcult to set back the device in its LRS.

5.3.2 Short-pulse measurements Signals measured with an oscilloscope during SET and RESET are shown in Fig. A.32a and Fig. A.32b. Measurements using pulses of 20 ns are feasible with this set-up. The endurance characteristics and the resistance distribution up to 500 cycles are shown in Fig. A.33. The devices are programmed at 20ns. Almost 1 decade is

70 5 – Generation 3 metal-oxide CBRAM technology compatible for low power applications

(a) (b)

Figure 5.6. (a) Signals on WL, BL and Anode during SET operation are measured with an oscilloscope. (b) Signals on WL, BL and Anode during RESET operation measured with an oscilloscope. Pulses of 20 ns are possible during SET and RESET. stable after 1000 cycles.

Figure 5.7. Endurance behavior of 1T1R device programmed at 20 ns for SET/RESET conditions. CDF distribution of LRS and HRS, 2% of BD is noticed and at 50% almost 1 decade of memory window is shown.

Measurents varying pulse duration are done to study the impact on LRS and HRS and the programming window. In Fig. A.34a, the resistance CDF is plotted for both LRS and HRS. The distribution indicates the resistance values for endurance measurements up to 1000 cycles. As we increase pulses from 20 ns to 1000 ns, LRS drifts towards lower values. The device shows more "conductive" behavior. No

71 5 – Generation 3 metal-oxide CBRAM technology compatible for low power applications

(a) (b)

Figure 5.8. (a) Distribution of LRS and HRS during SET and RESET for pulses varying from 20ns to 1 µs. (b) CDF of LRS for pulses varying from 20 ns to 1 µs. A factor 5 of R modulation is noticed. Median LRS and the standard deviation calculated for each pulse width. obvious modulation is noticed for HRS, independent from pulse widths. Almost 1 decade is stable for 20ns/1000 cycles. In Fig. A.34a and Fig. A.34b is shown the endurance behavior, plotted in CDF distributions for LRS. Varying pulse duration has an impact on LRS of almost a factor 5. As pulse width increases, LRS decreases. In order to quantify the percentage of cells which did not switch properly from cycle to cycle, we calculated the failure probability using a failure criteria: RON > 20 kΩ (which corresponds more or less to the mean RON value) and ROFF <100 kΩ (which corresponds more or less to the mean ROFF value). An illustration of failure criteria for RON and ROFF was shown in Fig A.35a. The calculated probability for each condition is plotted in the graph of Fig. A.35b. As pulse duration is increased, LRS failure probability progressively decreases from 20% to 0%. The same trend is shown for HRS. We want to quantify the percentage of written cells given the programming voltage and current, to do so, we use a criterion deﬁned as the probability to write cells to a certain LRS value: P(RON < 20 kΩ). As shown in Fig. A.36, around 95% of the cells switched correctly at 20ns during 1000 cycles. If we calculate the energy consumption at 20ns:

−4 −9 E = Vprogram · Iprogram · PW = 2.8 · 10 × 10 · 20 × 10 = 5.6 picoJ (5.1)

Thanks to the fast SET behavior, this technology is suitable for low power consumption applications.

72 5 – Generation 3 metal-oxide CBRAM technology compatible for low power applications

(a) (b)

Figure 5.9. (a) Illustration of the deﬁnition of the failure probability for LRS and HRS, measurements are done at 50 ns. (b) Failure probability extracted for each pulse duration for LRS and HRS.

Figure 5.10. Impact of successful Write (SET) operations on diﬀerent pulse widths. Also the measurements are done varying VBL during RESET and the impact on LRS is studied.

5.3.3 Pulsed - mode measurements

The forming voltage varies from cell to cell with a mean value around 3V measured on miniarrays (see Fig. A.30b). In Fig. A.37a and in Fig. A.37b are given the median and percentile resistance values during SET screening ranging VA and VWL−SET respectively. RESET parameters are ﬁxed: VWL−RESET =2.7V, VBL−RESET =2.2V and pulse width of 1 µs. Between each SET operation, a RESET operation is performed. To reach a LRS lower than 100 kΩ, VA should be higher than 1.8V and VWL−SET higher than 0.65V. The saturation LRS value is around 1 kΩ.

73 5 – Generation 3 metal-oxide CBRAM technology compatible for low power applications

Figure 5.11. Distribution of forming voltage within 6 devices, each consists of 64 bits. A "smart" forming method is applied as explained in Chapter 2.

(a) (b)

Figure 5.12. (a) Screening of the anode voltage during SET operation. Start- ing from HRS, the voltage is increased progressively until the transition to LRS occurs (saturation of R independent of the applied voltage). Between each operation, a RESET operation is done. (b) Screening of the gate voltage during SET operation. Pulses of 1 µs are applied.

In Fig. A.38a and in Fig. A.38b are presented the resistance values during RE- SET screening ranging VBL−RESET and VWL−RESET respectively. SET parameters are ﬁxed: VWL−SET =1V, VBL−SET =2.6V and pulse width of 1 µs. Between each RE- SEToperation, a SET operation is performed. The values are represented in median and percentiles. To have a HRS higher than 100 kΩ, VBL−RESET should be higher than 1.6V and VWL−RESET higher than 2.2V. The saturation HRS value is around 1 MΩ.

74 5 – Generation 3 metal-oxide CBRAM technology compatible for low power applications

(a) (b)

Figure 5.13. (a) Screening of the bitline voltage during RESET operation. Start- ing from LRS, the voltage is increased progressively until the transition to HRS occurs (saturation of R independent of the applied voltage). Between each operation, a SET operation is done. (b) Screening of the gate voltage during RESET operation. Starting from LRS, the voltage is increased progressively until the transition to HRS occurs. Pules of 1 µs are applied.

5.3.4 Endurance In this subsection, the cycling endurance behavior of CBRAM technology is shown. The first part is dedicated to 1T1R devices and the second part to miniarrays. Different set-up were required to measure the endurance behavior. As already discussed, when testing miniarrays,pulse width is limited to 100ns due to our set-up. A staticstics of 64 cells were tested and different SET and RESET conditions were used.

Endurance behavior of mini-arrays

In this paragraph, the cycling endurance behavior for miniarrays is shown.

Impact of programming current and pulse duration: In Fig. A.40 cells were programmed at different VWL−SET (0.65, 0.8V, 1V and 1.25V) and variable pulse widths of 100ns, 200ns, 500ns and 1 µs during SET and RESET were used. First the devices are cycled up to 10 times and best parameters are identified in terms of window margin and BD rate. In fact as we decrease the pulse width worse endurance behavior is noticed, with higher BD rate and worse window margin. Also better endurance is shown for VWL−SET > 0.8V. This can be correlated to the filament size, higher current means a thicker filament and more robust. Stable endurance behavior is shown up to 200ns, with almost 2 decades in mean value.

75 5 – Generation 3 metal-oxide CBRAM technology compatible for low power applications

Figure 5.14. Distribution characteristics for endurance measurements in miniarrays are shown. Both PW and VWL−SET are varied during SET operation.

Impact of RESET voltage VBL−RESET : In Fig. A.41 cells were programmed at different VBL−RESET (2, 2.2V, 2.4V and 2.6V) at fixed pulse width of 500ns and VWL−SET of 1V. First the devices are cycled up to 10 times and best parameters are identified in terms of window margin and BD rate. HRS seems more well distributed as VBL−RESET is increased, but no degradation is noticed for both LRS and HRS after 10 cycles. Higher VBL−RESET , induces more stress in the oxide and more oxygen vacancies, which degrade the HRS.

Impact of pule width: In Fig. A.39 cells were programmed at different pulse widths of 100ns, 200ns, 500ns and 1 µs during SET and RESET operations. VWL−SET is fixed at 1.2V. First the devices are cycled up to 100 cycles and best parameters are identified in terms of window margin and BD rate. In fact as we decrease the pulse width worse retention behavior is noticed. More time is needed to stabilize the filament creation. Stable endurance behavior is shown up to 200ns, with almost 2 decades in mean value and HRS BD rate of 10

Optimization of P/E conditions: In Fig. 5.17a and in Fig. 5.17b is shown the endurance behavior and CDFs of CBRAM cells up to 1 × 103 cycles. Different VWL−SET (0.8V, 1V and 1.25V) and fixed pulse widths of 500ns during SET and RESET were used to program the structures. LRS is more conductive as VWL−SET is increased, due to a thicker filament. Stable behavior is shown for all conditions with a memory window (resistance values are presented in median value and percentiles) around 2 decades. In Fig. 5.18a and in Fig. 5.18b is shown the endurance behavior and CDFs of

76 5 – Generation 3 metal-oxide CBRAM technology compatible for low power applications

Figure 5.15. Endurance measurements, median values (and percentiles) and CDFs are shown for diﬀerent VBL−RESET up to 2.6V. The measurements are done in miniarray devices.

5 CBRAM cells cycled up to 1 × 10 cycles. VWL−SET of 1V, pulse width of 500ns and VA=2.5V are used during SET, while VWL−RESET of 2.5V, pulse width of 500ns and VBL−RESET =2.4V are used to program the structures during RESET. HRS is responsible for endurance degradation. Almost 1 decade of loss is noticed after 1 × 105 cycles, while LRS is stable. Higher reset voltages induce defects in the oxide and the device becomes less "isolant". HRS drifts towards LRS. Almost 1 decade of memory window remains after 1 × 105 cycles.

Short pulse endurance in 1T1R devices We tested 1T1R structures to perform short pulse measurements and endurance up to 1 × 105 cycles. Fixed the programming current we vary pulse duration and reset conditions and we study the impact on endurance, HRS, LRS, resistance drift and BD. In Fig. 5.19 is shown the endurance behavior of 1T1R devices programmed at 0.65V for pulse widths of 100ns, 500ns and 1 µs. The devices were cycled up to 5 1 × 10 cycles using two diﬀerent VBL−RESET of 2V and 2.2V. LRS is very high for 0.65V and tends towards HRS during cycling. We also notice a lot of variability from cycle to cycle. The window ratio is less than 1 decade.

77 5 – Generation 3 metal-oxide CBRAM technology compatible for low power applications

Figure 5.16. Endurance measurements, median values (and percentiles) and CDFs are shown for diﬀerent PW during SET/RESET. Pulses vary from 100 ns to 1 µs. The measurements are done in miniarray devices.

A summary of the tested parameters (VBL−SET , VBL−RESET ) to study endurance are given in Fig. 5.20. VWL−SET is fixed at 1V and pulse duration of 1 µs. We want to extract the best parameters to have the best endurance up to 105. By increasing VBL−RESET , HRS is higher but it degrades during cycling, closing the memory window. Also increasing VBL−SET seems to effect HRS endurance behavior. So a moderate VBL−RESET of 2.2V and VBL−SET of 2.8V or high VBL−RESET of 2.4V and moderate VBL−SET of 2.5V seems the best trade-off. A summary of the tested parameters (VBL−SET , VBL−RESET ) to study endurance are given in Fig. 5.21. VWL−SET is fixed at 1.2V and pulse duration of 1 µs. We want to extract the best parameters to have the best endurance up to 105 cycles. By increasing VBL−RESET , HRS is higher but it still degrades during cycling, closing the memory window. It seems that 1.2V (strong SET condition) shows stable LRS, but degraded HRS during endurance. In Fig. 5.22 is shown a summary of all conditions used to test our sample 5 endurance behavior. The best behavior for 10 cycles is shown for VWL−SET =1V for both LRS and HRS. We can also notice that pulse duration plays a critical role and as we decrease its value, HRS degrades faster, increasing BD rate and closing the memory window. Also best combination for (VBL−SET , VBL−RESET ) seems to be either (2.8V, 2.2V) or (2.5V, 2.4V). Once we have an overview of the combination of our SET/RESET parameters,

78 5 – Generation 3 metal-oxide CBRAM technology compatible for low power applications

(a)

(b)

Figure 5.17. (a) Best programming conditions are used to cycle the miniarray devices up to 103 cycles. The endurance and CDF characteristis are shown for 500 ns.

we managed to maintain almost 1 decade up to 1 × 106 cycles forthe optimized conditions for 100 ns (Fig. A.42a) and 500 ns (Fig. A.42b). Our devices show good behavior up to 105 cycles, after that the memory window is completely closed. For pulse duration of 100ns it seems that HRS completely drifts to LRS, while for 500ns both LRS and HRS are responsible for endurance degradation. Also variability and erratic points from cycle to cycle are noticed. The main contribution can be due to filamentary nature of the filament. As shown in the literature [75], [77], the filament can be composed of few atoms, and each atom can have a crucial point in the behavior of the device. Oxygen vacancies are generated when increasing the cycle number, and different filament morphology can be created, degrading or not the device performance during each cycle.

79 5 – Generation 3 metal-oxide CBRAM technology compatible for low power applications

(a) (b)

Figure 5.18. (a) Best programming conditions are used to cycle the miniarray devices up to 105 cycles. The endurance and CDF characteristis are shown for 500 ns.

Figure 5.19. Endurance characteristics and CDF distributions for VWL−SET =0.65V are presented for 1T1R structures. Fixed VBL−RESET , measurements at diﬀerent pulse widths are done up to 105 cycles.

5.3.5 Data retention

Fig. 5.24a represents the behavior of the devices stressed at a high temperature of 115 °C for 24 hours. In a first order approximation we can say that LRS is stable for VWL−SET >0.8V. This can be correlated with filament morphology. As more current passes through the device, a larger filament (in diameter) is created, more robust and more difficult to be dissolved. The device is more conductive and LRS is lower. Regarding HRS, retention characteristics show a stable behavior for VWL−SET < 1.3V. In fact, a large resistive filament (resulting from the RESET operation after high SET current) is more likely to reconnect with the electrodes during bake, degrading its stability. We can conclude that the optimum operating

80 5 – Generation 3 metal-oxide CBRAM technology compatible for low power applications

5 Figure 5.20. Endurance characteristics up to 10 cycles, ﬁxed VWL−SET =1V and varying P/E conditions are shown for 1T1R devices.

5 Figure 5.21. Endurance characteristics up to 10 cycles, fixed VWL−SET =1.2V and varying P/E conditions are shown for 1T1R devices. point to maintain information is around 1V. As we increase the temperature (Fig. 5.24b), faster evolution of LRS and HRS appears. LRS tends to higher R values for all VWL−SET . In Fig. A.43a retention measurements were done up to 200 °C. It seems that both LRS and HRS degrade after 24 hours. LRS tends towards HRS. While HRS is more complex and is af- fected by the programming current. Higher programming current tend to drift HRS towards LRS, while for lower values, HRS tends to even higher resistance values. Data retention characteristics are shown for fixed VWL−SET of 0.8V at three different temperatures for a total accumulated baked time of 24 hours is shown in Fig. A.43b. LRS drift is noticed for LRS. In fact, if low programming current is used, a thin filament is created, which is not very robust and it can easily dissolve during baking at high temperatures. As temperature is increased from 115 °C to 200 °C, HRS also tends to drift to higher values. It can be explained by the filament morphology: vertical diffusion of the filament can happen, recreating the filament and reducing the ROFF value.

5.4 Conclusions

In this chapter, third generation CBRAM technology was studied in terms of reliability and memory performance. Material engineering was done for the whole MIM

81 5 – Generation 3 metal-oxide CBRAM technology compatible for low power applications

Figure 5.22. Summary of endurance measurements up to 105 cycles for diﬀerent P/E conditions.

(a) (b)

Figure 5.23. (a) Endurance measurements for 1T1R devices up to 106 cycles for 100 ns are shown. After 105 cycles , HRS drift towards LRS seems to be the main factor closing the memory window. (b) Endurance measurements for 1T1R devices up to 106 cycles for 500 ns. After 105 cycles, both HRS drift towards LRS and LRS towards HRS are responsible for endurance degradation. structure. The idea was to improve endurance behavior, combined with good thermal stability. Forming values seem to be around 3V and are relatively higher than devices with GdOx (2.5V), but shorter programming pulses are used (up to 20ns), which means less power consumption is used to program our devices. Typical pulses of 1 µs were used to switch GdOx CBRAM cells. Also MOx seems to withstand better voltage breakdown compared to GdOx. Endurance behavior was studied

82 5 – Generation 3 metal-oxide CBRAM technology compatible for low power applications

(a) (b)

Figure 5.24. (a) Data retention characteristics are shown for diﬀerent VWL−SET at 115 °C for 24 hours. (b) Data retention characteristics are shown for diﬀerent VWL−SET at 130 °C for 24 hours.

(a) (b)

Figure 5.25. (a) Data retention characteristics are shown for different VWL−SET at 200 °C for 24 hours. (b) Data retention characteristics are shown for fixed VWL−SET of 0.8V at three different temperatures for a total accumulated baked time of 24 hours. for both 1T1R and miniarray devices. Different P/E conditions were used during SET/RESET operations. Their impact on the endurance behavior was studied and analyzed and best parameters were identified to reach 1 × 105 cycles for 100ns. En- durance were performed and LRS or HRS seem to be responsible for endurance degradation depending on the programming conditions. Variability is noticed from cell to cell and from cycle to cycle in our structures, and we tried to find our best conditions to overcome this issue. Almost 2 decades of memory window were shown for 100ns/1 × 105 cycles. Data retention was performed for temperatures up to 200 °C for 24 hours baking time. We noticed that both LRS and HRS tend to degrade, but following different failure mechanisms depending on the programming conditions.

83 Chapter 6

General Conclusions and Perspectives

In this thesis, we addressed CBRAM data retention behavior at high temperatures, starting by an overview of the State-of-the Art. Both experimental results and models were presented to explain the retention loss for different CBRAM technologies. Arrhenius plot was used to extract the temperature which ensures 10 years data retention. Programming algorithms were proposed in order to improve the retention characteristics. In temperature accelerated testing, it appeared that retention time decreases with decreasing size of CFs, which is associated to the diffusion of vacancies/ions from CFs during high-temperature baking. The trade-off between the endurance and the thermal stability was elucidated. If strong conditions are used to cycle the device (in order to achieve high programming window), less stability in temperature is obtained. We demonstrated that the programming conditions in oxide-based CBRAM can be optimized in order to achieve low power SET current (30 µA) and moderate temperature window operation, or stable 250 °C behavior and 100 µA SET current. Based on experimental data and simulations, the physical mechanism governing retention failure of oxide-based CBRAM was clarified. In particular, a clear correlation between the filament shape (depending from SET and RESET conditions) and LRS and HRS thermal stability was established: higher compliance currents result in a thicker filament, more robust and difficult to RESET. On the other hand, low programming currents result in a weaker filament, easier to dissolve during baking time. We also proposed bilayer CBRAM devices able to improve the memory performances. As seen in the literature, bilayers offer better read disturb immunity, higher ROFF and better endurance or data retention (depending on the technology) with respect to monolayer CBRAM devices. These improvements were explained by the formation mechanisms of CF in the resistive layer or bottom interface. Algorithms to improve programming window were proposed, either by fixing RESET amplitude

84 6 – General Conclusions and Perspectives and varying pulse duration, either by fixing RESET pulse duration and increasing voltage amplitude. A trade- off between these parameters can give the best performance. In our work we integrated thin layer of HfO2 or Al2O3 with GdOx . The window margin is increased of more than one decade and shows stability up to 1 × 105 cycles at 250 °C for the bilayer devices. An endurance of 1 × 105 cycles is achieved. An empirical model is proposed to compute the OFF state resistance (HRS) drift during cycling. The gradual defect generation and Cu accumulation in the electrolyte are taken into account and de-correlated. In conclusion, the integration of a bottom interface in a CBRAM device allows to reduce the defect concentration of 50%, thus improving the memory window and endurance characteristics. Larger window results to a larger gap between the remaining filament and the bottom electrode. Finally, we discussed the third generation CBRAM technology. Material engineering was done for the whole MIM structure. The objective was to improve endurance behavior, combined with good thermal stability while keeping the use of simple materials, easily integrated in CMOS technology. Forming values around 3V (i.e. relatively higher than devices with GdOx (2.5V)) were shown, but shorter programming pulses were used (up to 20 ns), thus indicating that less power consumption is used to program our devices. Typical pulses of 1 µs were used to switch GdOx CBRAM cells. Also MOx seems to withstand better voltage breakdown compared to GdOx . Endurance behavior was studied for both 1T1R and miniarray devices. Different P/E conditions were used during SET/RESET operations. Their impact on the endurance behavior was studied and analyzed and best parameters were identified to reach 1 × 105 cycles for 100 ns. Endurance were performed and both LRS and HRS are responsible for endurance degradation depending on the programming conditions. As the pulse width decreases, the HRS decreases. The filament needs a larger pulse to form and stabilize. Variability was noticed from cell to cell and from cycle to cycle in our structures, and optimized conditions were identified to overcome this issue. Almost 2 decades of memory window were shown for 100 ns/ 1 × 105 cycles. Data retention was performed for temperatures up to 200 °C for 24 hours baking time. We noticed that both LRS and HRS tend to degrade, but following different failure mechanisms depending on the programming conditions. This can be correlated also with the filament morphology. Thicker filaments, formed by large programming current are more robust and stable to data retention. Future work can be done to further optimize CBRAM device performances. Reliability in terms of retention and endurance should be optimized in order to al- low CBRAM industrialization and be compatible with the NVM market demands. Material engineering is needed in order to find the best materials, which are low cost and easy to integrate into current CMOS technology. In particular, resistive layer quality to reduce defect concentration and generation during SET and RESET operations should be improved, in order to limit the CBRAM degradation during

85 6 – General Conclusions and Perspectives endurance. Variability remains one of the key problem especially for HRS, and should be addressed in more details, to improve the uniformity of the device behavior. Indeed, the wide resistance distribution prevent from large density RRAM integration. Programming algorithms can also be envisaged in order to correct the endurance behavior. So correction algorithms need to be developed to maintain a stable window. "Smart endurance" for example can help to constantly control and maintain stable HRS. Smart forming for improved reliability (limiting the energy provided to the system during the forming operation) should be also implemented.

86 Appendix A

Résumé en français

Introduction

A.1 Mémoires non-volatiles émergentes

A.1.1 Technologies de mémoire non volatile émergentes La mémoire peut être soit volatile soit une mémoire non volatile (NVM). En fonction de leur applications, NVM sont classés en stand-alone, intégré et la mémoire de classe de stockage (SCM). Mémoires volatiles classiques consistent en SRAM et DRAM et ils sont le plus couramment utilisés dans les applications de nos jours qui dominent le marché pour les applications autonomes autour de 35.6 B $ comme indiqué dans Fig. A.1a et environ 60% pour les micro-processeurs mobiles (MPU) et microcontrôleurs (MCU) applications comme indiqué dans Fig.A.1b. Quelque part, ils ne gardent

87 A – Résumé en français

(a) (b)

Figure A.1. (b)Graphique du marché de la mémoire pour les applications embarquées. (a) Graphique du marché de mémoire pour les applications autonomes [1]. pas l’information aprés la mise sous tension d’arrêt. Pour cette raison, de nouveaux souvenirs non-volatiles ont de plus en plus d’attention. Les données en Fig.A.1b montrent qu’ils occupent 1.3 B $ du marché autonome et 27% du coût du marché de l’automobile et des microcontrôleurs. NAND et DRAM dominent le marché de la mémoire, ce qui représente environ 90% des ventes totales de mémoire. Parmi les NVM émergents, nous pouvons mentionner la phase changement de mémoire PCM, les mémoires magnétique MRAM, ferroélectrique RAM FRAM, mémoire de commutateur résistif (également appelé ReRAM, CBRAM, OxRAM), la mémoire à base de polymére, moléculaire. Ces mémoires doivent surmonter les problémes de mise à l’échelle qui eﬀet mémoire ﬂash, la technologie NV le plus mature avec une présence sur le marché de 28.7 B $. Les prévisions montrent que d’ici 2020, les marchés émergents NVM vont croître jusqu’à 7 B $ en 2020 avec Enterprise Storage comme le plus grand marché en raison de l’adoption rapide de MRAM et STT-MRAM comme représenté sur la Fig. A.2 et Fig. A.3. Wearable est le deuxiéme marché en pleine croissance en raison de la forte demande de faible puissance. SCM évolue en tant que catégorie de mémoire visant à combler l’écart entre la RAM et SSD en termes de latence courte et haute densité. Il combine les avantages de la mémoire à semi-conducteurs, tels que la haute performance et robustesse, avec les capacités d’archivage et de faible coût du stockage conventionnel magnétique dur. Un tel dispositif nécessite une technologie non volatile (NVM) qui pourrait être fabriqué à un trés faible coût par bit. Les schémas présentés dans Fig. A.3 mettent en évidence les applications dans l’industrie et le transport jusqu’à la masse des applications de mémoire de stockage. IOT suscite de plus en plus d’attention et de la demande pour des produits électroniques intelligents et portables augmente. Avec ses avantages comme faible puissance et de la vitesse de commutation rapide, CBRAM se présente comme l’un

88 A – Résumé en français

Figure A.2. Applications des nouvelles technologies émergentes RRAM [1]. des la mémoire avenir prometteur. De nombreux centres de recherche et les entreprises investissent dans le domaine de la mémoire NVM du niveau des sociétés start-up comme Adesto, Crossbar, Crocus La technologie ; fabricants d’appareils in- tégrés comme Samsung, Toshiba ou fonderies comme TSMC, GlobalFoundries. Leur entreprise est encouragée par les centres de données, sociale joueurs comme Face- book, Google et eBay réseau et ebusiness (Fig. A.4).

Figure A.3. Tendance du marché des émergions NVM par applications pour la période 2014-2020 [1].

89 A – Résumé en français

Figure A.4. Principaux contributeurs de développement de NVM [1].

A.1.2 Démonstrateur et leurs performances

Les dispositifs de mémoire ont des exigences strictes aﬁn d’être industrialisés. Les critéres sont ﬁxés à partir des enquêtes des Emerging Device Research Work Group [3]. En termes de performances électriques les principales caractéristiques consistent à former la tension et le courant, la vitesse, la consommation d’énergie, l’endurance, la conservation des données de commutation, une capacité de plusieurs bits, la den- sité, la reproductibilité et la mise à l’échelle. Ces paramétres varient et un ou l’autre a la priorité en fonction de leurs applications : stockage, la mémoire, la logique ou neuromorphique comme une demande d’étendre "CMOS Extension" et les technologies "Beyond CMOS". Pour les applications de mémoire les exigences et les données démontrées dans la littérature sont prometteurs et compatibles [31]–[33]. Dans le tableau A.1 sont indiqués les paramétres de performance prévus pour écaillé émer- gents technologies de mémoire de recherche STTRAM, CBRAM, PCM et OxRAM, les valeurs sont une preuve dans la littérature et celui projeté. Ces performances sont positives et dans l’avenir, ils peuvent remplacer la technologie Flash.

A.1.3 Motivation

La technologie Flash est proche de ses limites de mise à l’échelle, de sorte que la demande de nouvelles technologies augmente. Les candidats prometteurs sont NV MRAM en raison de leur structure simple, la compatibilité CMOS, de faible puissance, la vitesse de commutation rapide et l’évolutivité, à faible coût par bit. Certaines questions liées à la compréhension des mécanismes de fonctionnement et

90 A – Résumé en français

Table A.1. La comparaison des performances des diﬀérentes émergentes non volatiles technologies de mémoire selon 2014 pour la technologie Semi-conducteurs (ITRS), avec des projections pour l’année 2026 [3].

91 A – Résumé en français la variabilité doivent encore être pris en compte. Aﬁn de répondre à ces questions et d’augmenter les performances de la RAM, l’ingénierie des matériaux pour élec- trodes métalliques [34] et la couche isolante sont actuellement proposées, y compris la mise en œuvre de nouvelles méthodes pour mieux le dépôt de matériel de qualité. Algorithmes de correction sont proposés pour limiter le courant de dépassement, la variabilité et augmenter la marge de fenêtre. Dispositifs de sélection de mémoire doivent également être améliorés. Beaucoup de recherches se concentre sur l’intégra- tion de la barre transversale 3D des nouvelles technologies [35] avec l’avantage d’une densité plus élevée et ils occupent moins d’espace. Les experts du marché estiment que le NVM va doubler d’ici 2020, en augmentant sa présence dans les deux applications autonomes et embarquées. Aussi les appareils intelligents tels que les tablettes et les téléphones ont été une force motrice pour augmenter la demande de capacité de stockage. L’objectif principal de cette thése est la technologie de CBRAM. Une introduction de son Etat - de - l’art, principe de fonctionnement et des applications futures a été donné dans le présent chapitre. Récemment, de nombreuses entreprises et laboratoires de recherche présentés CBRAM avec oxydes métalliques intégrés comme couche résistive. Les dispositifs montrent des améliorations de ﬁabilité telle que la conservation des données, l’endurance et le soudage par refusions par rapport à la technologie précédente qui était basée sur chalcogénures comme couche isolante [36], [8]. Les principales applications nous avons ciblé étaient hautes températures et applications de faible puissance.

A.2 CBRAM étude de la conservation des don- nées

Dans ce chapitre, nous examinons le comportement à haute température des mé- moires CBRAM à base d’oxyde. Une méthodologie pour optimiser la stabilité dés les états haute et basse résistance est présentée. Un modéle numérique est développé capable de simuler la dissolution du filament au fil du temps. Cela nous permet d’éta- blir une corrélation claire entre la morphologie filamenteuse et la stabilité des états ON / OFF. Il est montré que l’optimisation des conditions de programmation de la mémoire conduit à une fenêtre de mémoire stable jusqu’à 250 °C. La technologie CBRAM est trés prometteuse en tant que futurs mémoires non volatiles à usage gé- néral des microcontrôleurs (MCU) en raison de sa faible tension de fonctionnement, le comportement de commutation rapide, le coût d’intégration faible et une bonne CMOS compatibilité. Néanmoins, afin de permettre à la technologie, la stabilité en température élevée doit être adressée (en particulier, pour démontrer l’intégrité des données aprés la température maximale de soldering-reflow). Dans ce chapitre, le rôle de SET et RESET conditions sur le comportement de rétention (taux de perte

92 A – Résumé en français

Figure A.5. Le rapport de la fenêtre en fonction de la température pour différents ReRAM les technologies. Lorsque la température augmente, la marge de fenêtre est réduite. En intégrant une couche d’interface mince, la fenêtre est augmentée de prés de 1 décennie [8], [37], [39], [47]–[64]. de données et de l’énergie d’activation) est clarifiée. Nous montrons que l’optimisation des conditions de programmation peut considérablement agrandir la rétention de la mémoire à haute température. Les données expérimentales sont expliquées au moyen de simulations numériques, ce qui démontre une corrélation claire entre le filament morphologie / taux de dissolution et les conditions de fonctionnement de la mémoire. Sur la figure Fig. A.5, la forte dépendance de la fenêtre de programmation et la T apparaît, en négligeant les effets de la durée de cuisson (généralement plus de 24 heures) et de programmation / effacement conditions. Chaque point correspond à une technologie donnée, tenu compte de la CBRAM et ReRAM en général [8], [37], [39], [47]–[64]. Le graphique explique le compromis entre l’endurance et la stabilité thermique. Comme nous pouvons notification, lorsque la température augmente, la marge de la fenêtre commence à diminuer à partir de 6 décennies à prés de 1 décennie. Si les conditions fortes sont utilisées pour le cycle du dispositif (à atteindre la fenêtre de programmation de haut), moins de stabilité de la température est remarqué. La technologie CBRAM étudié dans ce travail est composé d’un Ta / GdOx / CuTeGe / TiN empilés comme montré sur la Fig. A.6a. La cellule de mémoire consiste en une résistance plus un transistor utilisé comme sélecteur (1T1R). Les caractéristiques typiques IV de commutation (Formation, SET et RESET) dans les modes quasi statiques sont illustrées sur la Fig.A.6b. Dans ce qui suit, les expériences sont effectuées en mode pulsé. Des simulations numériques 2D de la dissolution de filaments ont été réalisées

93 A – Résumé en français

(a) (b)

Figure A.6. (a) Des schémas de cellules CBRAM pour les structures 1T1R. (b) Caractéristiques IV typique de la structure CBRAM lors du formation, SET et les opérations de réinitialisation. pour comprendre les résultats de rétentions expérimentales. Nous supposons que la résistance LRS est commandée par la largeur du filament, tandis que la résistance HRS dépend de la largeur du filament résiduelle et de la hauteur (Fig. A.7). Le filament est composé d’atomes de Cu répartis réguliérement dans la couche résistive, chaque atome étant traité de maniére indépendante. La concentration de Cu dans le filament est ajustée dans l’axe X afin de tenir compte de la forme cylindrique du filament : en effet, la concentration en Cu est plus élevée dans le centre du filament que dans la proximité des bords. Ce facteur de correction nous permet d’utiliser des simulations 2D, émulant un comportement filamentaire 3D. Pendant cuire, atomes de Cu migrent suivant une loi de Fick avec un coefficient de diffusion D. La concentration Cu locale est calculée localement afin d’en extraire la résistivité locale en tout point de l’électrolyte basé sur une loi de semi-conducteurs. Les pentes des caractéristiques de rétention LRS / HRS (heure) (tracé en échelle logarithmique) sont extraits, conduisant à les paramétres vON et | vOFF |, respectivement (Fig. A.8). Plus grand sont vON et | vOFF |, le pire est le temps de rétention. à partir du graphique sur la Fig. A.8 nous avons extrapolé le paramétre vON . Ce paramétre décrit le coefficient de dérive, on peut exprimer qualitativement la perte de rétention de données en fonction du temps [42]. Ceci est donné par une loi de puissance comme suit :

v R = R0 · (t/t0) (A.1) Si l’on suppose un facteur 10 de le rapport R , le coeﬃcient de dérive calculée R0 aprés 1 × 105 s correspond à une valeur d’environ 0.15 à 0.2. Au-dessus de cette valeur, le comportement de rétention est stable et inférieure à cette valeur, le comportement de rétention est instable.

94 A – Résumé en français

Figure A.7. Configuration de filament LRS et HRS utilisé pour les simulations de rétention. En supposant que la loi d’un Fick pour Cu diffusion au cours de cuisson, la concentration de Cu locale et cellulaire la résistance sont calculés par un modéle de percolation.

Figure A.8. LRS mesurées et les caractéristiques de rétention HRS à 200 °C correspondant à un courant de conformité ISET = 100 µA. Le paramétre vON et vOFF sont extrait pour chaque cas. Ils suivent une loi de puissance.

Les courbes de rétention pour l’état ON sont tracées sur la figure Fig. A.9 pour diverses conditions SET, conduisant à une propagation RON initiale de plus de 2 décennies. Plus la résistance initiale n’est élevée, plus la stabilité LRS. On peut remarquer que les courbes expérimentales sont bien produites par notre modéle numérique. Ce résultat est confirmé par la diminution de vON que le premier RON diminue (Fig. A.10a). En particulier, les données expérimentales et le modéle indiquent que 5 lorsque RON < 1 × 10 Ω, le filament est suffisamment épaisse pour être stable dans le temps. Pour RON plus, la percolation ne devient dominante et le filament est plus sensible à la diffusion Cu dans l’électrolyte au cours de cuisson, conduisant à LRS

95 A – Résumé en français

Figure A.9. Caractéristiques LRS simulées et mesurées à 130 °C pour divers initial RON correspondant à des courants de conformité ISET allant de 20 µA à 200 µA. Haute ISET correspond à LRS plus stables.

(a) (b)

Figure A.10. (a) Simulées et mesurées pentes LRS (vON ) extrait de rétention à 130 °C en fonction de la premiére RON . Une vON de 0.15 est supposé assurer suffisamment grande fenêtre de la mémoire aprés 10 ans à 130 °C. LRS stables sont ainsi observées jusqu’à 100 kΩ. (b) Pente de HRS (vOFF ) en fonction de ROFF à 130 °C. Dans l’encart de la caractéristiques de rétention avec diffé- rents ROFF initial sont présentés. Supérieur ROFF initial montre un meilleur comportement de rétention. instabilité. Fig. A.10b, nous avons tracé les caractéristiques de rétention HRS mesurées et simulées pour diverses ROFF initiale obtenue en ajustant la tension de RESET (RE- SET à puce). Il semble qu’une ROFF plus élevée conduit à une plus grande stabilité et HRS une vOFF inférieure. Nous affirmons que la hauteur du filament restant dans l’électrolyte est réduite car les conditions RESET sont renforcées. Ainsi, ce qui conduit à un plus grand écart entre le filament et l’électrode restante supérieure à

96 A – Résumé en français

(a) (b)

Figure A.11. (a) Caractéristiques de conservation des mêmes ROFF initial, mais programmé avec différentes conditions LRS. Le paramétre vOFF correspondant à ROFF . (b) νOFF parameter corresponding to the HRS and its dependency on the ROFF . base de Cu, ce qui empêche la reconstruction d’une voie conductrice au cours de cuisson. Ensuite, nous avons examiné l’impact de la valeur RON sur la stabilité HRS (Fig. A.11b). Nous montrons que, pour une ROFF initiale donnée, la stabilité HRS se dégrade lorsque la mémoire a déjà été réglée à une faible RON . Pour confirmer cette tendance, Fig. A.10b vOFF rapports en fonction de RON . Les deux expériences et simulations présentent une pente plus élevée (correspondant par HRS à un comportement stable) comme RON augmente. Cela peut être expliqué comme suit : un RON inférieure conduit à un filament restant plus épais, ce qui donne à plusieurs atomes de Cu dans le filament en mesure de se reconnecter à l’électrode supérieure. Fig. A.12a il est représenté le profil de refusions. La mesure est effectuée à T = 260 °C pendant 15 min. La distribution de la résistance avant et aprés refusions est indiqué pour LRS et HRS en Fig. A.12b. Les deux états montrent un comportement de SMT stable.

Figure A.13 résume la vON et vOFF pentes, extrait lors des mesures de rétention à 130 °C en fonction du courant de programmation ISET . A | vmax | de valeur de 0.15 est représenté dans le graphique, et correspond à un maximum de volume arbitraire pour assurer suffisamment grande fenêtre de mémoire au bout de 10 ans à 130 °C. Ce graphique nous permet d’identifier une fenêtre d’exploitation optimale de cette technologie entre 30 µA et 100 pA, confirme ainsi le potentiel de faible puissance de la technologie de CBRAM. Il convient également de noter que cette fenêtre peut encore être agrandie en augmentant les conditions RESET (et donc le ROFF ), permettant de réduire vOFF sans dégrader la stabilité LRS. Pour un courant de programmation faible (Fig. A.14), LRS est le contrôle de la durée de

97 A – Résumé en français

(a) (b)

Figure A.12. (a) Le proﬁl de soudure par refusion. Les mesures ont été ef- fectuées à 260 °C pendant 15 min. CDF de distribution cumulative des LRS et HRS avant et aprés la soudure. (b) Cumulative distribution CDF of the LRS and HRS before and after soldering.

vie alors que pour haute ISET , HRS devient le point limite. De plus, nous pouvons remarquer que la température de fonctionnement maximale de 10 ans de rétention est considérablement augmenté pour la hausse des courants SET. Ainsi, il faut garder à l’esprit que dans les technologies de mémoire résistive, les énergies d’activation et les températures de fonctionnement sont strictement corrélées au SET et RESET conditions de programmation. Les états ON et OFF des caractéristiques de rétention ont été mesurés à diverses températures, (85 °C - 300 °C ) avec curent de programmation égal à 30 µA, 80 µA et 100 µA (Fig. A.14). Le critére du temps de défaillance a été ﬁxé à une variation critique ROFF d’un facteur 2 (graphiques Arrhenius en Fig. A.15). L’utilisation d’un RON courant de programmation bas, LRS est a le contrôle de la durée de vie alors que pour haute ISET HRS joue le rôle essentiel. De plus, nous pouvons remarquer que la température de fonctionnement maximale de 10 ans de rétention a considérablement augmenté pour la hausse des courants de SET (250 °C pour ISET = 80 µA).

A.2.1 Conclusion Dans ce chapitre, un aperçu de l’état-of-the-art de CBRAM comportement de ré- tention des données à des températures élevées a été montré. Les résultats expéri- mentaux et des modéles ont été utilisés pour expliquer la perte de rétention pour les diﬀérentes technologies de CBRAM. Arrhenius a été utilisé pour extraire la tempé- rature qui assure 10 ans de conservation des données. Des algorithmes de programmation ont été proposés aﬁn d’améliorer les caractéristiques de rétention. Dans les

98 A – Résumé en français

Figure A.13. Pentes (vON ) et (vOFF ) de LRS (carré) et HRS (cercle) comme fonction de le courrant de SET utilisé pour déﬁnir la premiére RON pendant la rétention à 130 °C.A vmax de 0.15 est supposé assurer suﬃsamment grande fenêtre de la mémoire aprés 10 ans de données rétention. Une fenêtre d’exploitation stable au cours de la rétention apparaît donc quand les courants entre 30 µA et 200 µA sont utilisés.

Figure A.14. Caractéristiques de rétention LRS et HRS à diﬀérentes tem- pératures (130 °C - 300 °C), avec des courants de programmation initiale est égale à 80 µA ou 100 µA. essais de température accélérée, le temps de rétention diminue avec la taille décrois- sante CFS, qui est associée à la diﬀusion des postes vacants / ions de CFs pendant

99 A – Résumé en français

Figure A.15. Time to-fail-Arrhenius pour trois est égal à 30 µA, 80 µA et 100 µA. La capacité de rétention de 10 ans, est extrapolée à 50 °C pendant 30 µA et 250 °C pour 100 µA. Pour cette ﬁgure, ne parviennent pas critÃĺre de temps correspond à un variation de ROFF d’un facteur 2. RON

la haute cuisson de température. Ces filaments peuvent être plus faibles ou même cassé pendant le processus de cuisson, ce qui conduit à augmenter RON et l’échec de rétention, et les filaments peuvent être rompues plus facilement que la tempé- rature est augmentée. Les algorithmes de SET et RESET sont une seule impulsion de tension (SVP) et une série de rampe d’impulsion (RPS : écriture vérifie-écriture) en mode. Aussi un compromis entre SET et RESET conditions de programmation est suggéré. Certains groupes ont proposé deux techniques d’ingénierie de Cu-alliage électrode active à améliorer la robustesse du pont, et anti-Cu électrode inerte diffusive pour supprimer Cu diffusion à partir du pont. Un alliage de Ru est reconnu en tant que candidat de futurs étaux de barriére pour les interconnexions de Cu en raison de la faible résistivité et une bonne résistance d’adhérence au cuivre. Le compromis entre la résistance et la stabilité thermique a été élucidé. Si les conditions fortes sont utilisées pour faire défiler le dispositif (afin d’atteindre un niveau élevé fenêtre de programmation), moins de stabilité de la température est remarqué. Nous avons démontré que les conditions de programmation dans CBRAM à base d’oxyde peuvent être optimisés afin d’atteindre un faible courant électrique SET (30 µA) et l’exploitation modérée de la fenêtre de température, ou stable 250 °C comportement et 100 µA de courant SET. Basé sur des données expérimentales et des simulations, le mécanisme physique régissant l’échec de réétention de CBRAM à base d’oxyde a été clarifié. En particulier, une corrélation claire entre la forme du filament (en fonction de SET et RESET conditions) LRS et HRS stabilité thermique a été établi.

100 A – Résumé en français

A.3 Dispositifs CBRAM bicouches pour amélio- rer les performances de la mémoire

Stabilité à haute température [8], [42], une grande marge de fenêtre et une bonne endurance [11], [10] sont nécessaires pour les applications de mémoire non-volatile de pointe. Cependant la combinaison de ces caractéristiques essentielles est difficile et nécessite des améliorations tant au technologique [39], [72] [36]. et de la conception des niveaux [36]. Dans ce travail, nous proposons une CBRAM à base d’oxyde opti- misé basé sur une bicouche électrolyte solide [48], [70], [72]. L’objectif était d’élargir la réégion isolante lorsque la mémoire est à l’état résistif élevé, afin d’améliorer les performances de la mémoire (fenêtre de méémoire, la stabilité thermique et endurance). Les principales caractéristiques de la pile proposée seront prises en compte et les mécanismes physiques impliqués seront discutés. Les dispositifs CBRAM étu- diés dans le présent document sont décrits dans la figure. A.16a. L’ééchantillon de référence CBRAM monocouche utilise un oxyde métallique déposé par PVD comme couche résistive [42]. Un bouchon métallique agit comme électrode de fond, tandis que l’électrode supérieure consiste en une couche d’alimentation d’ions à base CuTex [11]. En CBRAM bicouches, 5A Al2O3 ou HfO2 ont été déposéés par ALD en tant qu’interface de fond entre le bouchon métallique et la couche réésistive résultant en une Ta/GdOx /Al2O3/CuTeGe/TiN etTa/GdOx /HfO2/CuTeGe/TiN dispositifs. A noter que la cellule de mémoire consiste en un transistor de sélection et un élément a changement de résistance (1T1R). Les caractéristiques de courant-tension pendant les opérations de formation et SET / RESET sont représenté sur la Fig. A.16b en haut pour le dispositif de la monocouche et sur la Fig. A.16a en bas pour des dispositifs de bicouches. Nous pouvons remarquer que pour les deux échantillons d’une tension plus élevée est requise pendant la opération de formation, autour de 2.5V pour les bicouches et 1.2V pour les monocouches. La tension de SET est éga- lement autour de 1V. Le courant pendant SET et RESET sont environ 100 µA. Fig. A.16a et la Fig.A.16b la résistance à l’état vierge (R0) mesurée à faible VREAD = 0.1V avec la formation de tension Formant en mode quasi-statique sont respectivement indiquées pour les dispositifs CBRAM monocouche et bicouches.

Il apparaÃőt que l’ééchantillon présente une bicouche R0 accrue (> 1 GΩ) et VF orming par rapport à la référence monocouche. En outre, R0 supérieur et VF orming sont mesurés avec une interface Al2O3 inférieure, en raison de constant diélectrique plus élevée dâĂŹAl2O3 par rapport à HfO2. Il faut également remarquer qu’un CBRAM 48A monocouche présente encore plus bas R0 et VF orming que la bicouche, en dépit de la même épaisseur physique de la pile totale (Fig. A.17a et Fig. A.17b). Fig. A.18 nous partons de la State High résistive (HRS) et augmenter progressivement VWL ou VBL−SET . RON similaires et VSET sont obtenus au 1er ordre entre mono et bicouches CBRAM.

101 A – Résumé en français

(a) (b)

Figure A.16. (a) Schéma de résistances CBRAM étudié dans ce travail (le CBRAM cellule étant une structure 1T1R) Nous avons éétudié les dispositifs monocouches et bicouches. (b)(En haut) Caractéristiques IV pour les dispositifs GdOx monocouche formés et ﬁxé à VWL = 1V et réinitialisé à VBL = 1.2V. (En bas) les caractéristiques IV pour bicouche dispositifs GdOx / Al2O3.

(a) (b)

Figure A.17. (a) Les valeurs de résistance fraîches pour les dispositifs de CBRAM étudiés ce travail. (b) Les valeurs moyennes et les écarts types de formation pour des tensions diﬀérents échantillons de CBRAM. Nous avons éétudié les dispositifs monocouches et bicouches .

Les mesures de mode pulsé ont été réalisées aﬁn d’évaluer la vitesse de commutation de la mémoire. Fig. A.19 nous avons commencé à partir de la Résistive état

102 A – Résumé en français

Figure A.18. RON en fonction du SET VWL pour les 2 échantillons étudiés (1 µs impulsions). ROFF entre chaque cycle RESET est également représenté. (b) RON comme fonction de SET VBL−SET pour les 2 échantillons étudiés (1 µs impulsions). ROFF entre chaque cycle RESET est également représenté.

Figure A.19. ROFF en fonction du RESET VWL−RESET pour les 2 échantillons étudiés (1 µs impulsions). RON entre chaque cycle SET est également représenté. (b) ROFF comme fonction de RESET VBL−RESET pour les 2 échantillons étudiés (1 µs impulsions). RON entre chaque cycle SET est également représenté. faible (LRS) et appliqué des impulsions RESET de 1 µs, en augmentant progressivement la ligne de mot RESET (VWL) ou ligne de bit (VBL) tensions. Entre chaque opération RESET, l’CBRAM est remis à l’état ON. Les cellules sont remises à zéro pour des tensions inférieures (VBL < 1.2V) sur la référence monocouche en raison de la pile plus mince, mais à des tensions plus élevées (VBL > de 1.6V) une fenêtre plus grande marge est atteint sur le CBRAM bicouche (plus d’une décennie de gains). L’impact de la largeur d’impulsion est représentéée à la Fig. A.20a, A.20b pour GdOx /Al2O3 CBRAM, indiquant des tensions typiques de 2.2V et -1.5V SET et RESET ou 99.9% des cellules commute à 1 µs , respectivement. CBRAM endurance nécessite une optimisation et une analyse minutieuse pour atteindre des caractéristiques de haute performance. Dans ce travail, trois méca- nismes principaux ont été identiﬁés comme responsables de la diminution de la

103 A – Résumé en français

(a) (b)

Figure A.20. (a) Distribution à l’échelle normale des cellules RESET en fonction de la tension d’impulsion pour GdOx /Al2O3 CBRAM. (b) Dis- tribution à l’échelle normale de SET les cellules en fonction de la tension d’impulsion pour GdOx /Al2O3 CBRAM. marge de la fenêtre au cours de l’endurance (Fig. A.21) : la dérive HRS (diminution de valeur moyenne ROFF ), la rupture (R coincé dans les LRS aprés un RESET) et SET ineﬃcace (R coincé dans HRS aprés SET).

Figure A.21. HRS et distributions normales LRS illustrant la déﬁnition de taux de panne (BD), les cellules coincés dans HRS (BH) et la dérive HRS.

104 A – Résumé en français

(a) (b)

Figure A.22. (a) Pourcentage de cellules rompues (BD) et de la marge de fenêtre (Ratio) en fonction de VSET aprés 1000 cycles pour GdOx /Al2O3 CBRAM. (b) BD et le taux HB par rapport au VSET ﬁxe | VBL−RESET | = 1.75V aprÃĺs 1000 cycles pour GdOx /Al2O3 CBRAM.

Afin d’optimiser les caractéristiques d’endurance, des tensions SET et RESET ont été ajustés pour limiter ces phénoménes. Figure A.22a rapporté l’impact RESET VBL : augmenter VBL−RESET améliore la marge de fenêtre (courbe rouge), mais augmente le pourcentage de cellules rompues aprés 1 × 103 cycles (courbe bleue). En ce qui concerne SET (Fig. A.22b), les résultats VBL−SET insuffisants dans un pourcentage élevé de cellules coincés dans HRS (courbe rouge), tout en augmentant VBL−SET trop de résultats dans un plus grand nombre de cellules brisées (courbe bleue). Sur la base de cette étude préliminaire, nous avons pu déterminer les meilleures conditions SET / RESET pour chaque échantillon de CBRAM. Les conditions de programmation au cours de SET sont : VWL−SET = 1V, VA = 2V (monocouche) et 2.5V (bicouche) et la durée d’impulsion est de 1 µs. Alors que pendant le fonctionnement RESET : VWL−RESET = 2.5V, VBL = 2V (monocouche) et 1.7V (bicouche) et la durée d’impulsion est de 1 µs. Les caractéristiques d’endurance sont rapportées sur la figure A.23a pour les appareils mono et bicouche. Une nette amélioration des caractéristiques d’endurance est obtenue lorsque bicouches sont intégrées en tant que couches résistives, avec plus d’une décennie entre LRS et HRS aprés 1 × 105 cycles. Une partie de cette amélioration peut être expliquée par le fait que pour une fenêtre de mémoire fixe, des tensions de fonctionnement plus faibles sont nécessaires pour SET / RESET bicouche CBRAM, la réduction de la dégradation progressive de la pile de la mémoire pendant le cycle. Dans tous les échantillons, une dérive progressive de la résistance HRS apparaît pendant le cyclisme. On peut remarquer mieux sur la Fig. A.23b, comme le nombre d’augmentations de cycle, ROFF diminue et ainsi que BD taux augmente. Cela se traduit par la fermeture de la fenêtre de la

105 A – Résumé en français

(a) (b)

Figure A.23. (a) Les caractéristiques d’endurance des mono et bicouche sont présentés. Dispositifs bicouche présentent jusqu’à 1 × 105 cycles avec une décennie stable OFF/ON. (b) CDF de R tel que le nombre de cycles augmente de la premiére à 1 × 104 cycle pour les LRS et HRS. mémoire et de la dégradation de l’endurance [73]. Afin d’analyser l’origine de la dérive de la résistance HRS pendant le cycle, nous avons effectué une séquence "smart" RESET aprés le cyclisme. En particulier, la réinitialisation des impulsions de 1 µs sont appliquées, augmentant progressivement l’amplitude VBL de 1.5V à 2.5V, jusqu’à une valeur de résistance cible est atteinte (Fig. A.24a). L’expérience a été effectuée sur des mono et bicouche CBRAM. Figure A.24b montre les résistances aprés le 1er cycle, 1 × 104 cycle et aprés la séquence RESET intelligente. Il semble que la Smart Reset permet de récupérer complétement la valeur ROFF initiale dans le cas de GdOx /Al2O3 CBRAM. D’un autre cas, la déérive de la résistance est irréversible sur la référence monocouche, quelle que soit la tension de réinitialisation appliquée. Sur la base de ces données, nous proposons l’interprétation suivante. La ROFF décroissante au cours du cycle peut être expliqué par deux mécanismes : la production et l’accumulation d’atomes résiduels Cu (à incandescence résiduelle) défaut de la réésistance couche. Dans le cas de la monocouche CBRAM (Fig. A.25), on suppose que le les défauts créés dans l’oxyde métallique sont à l’origine de la dégradation de l’endurance. Dans le cas des bicouches (Fig. A.25), nous avons en plus Cu accumulation dans le fond une interface qui réduit la valeur ROFF proche de celle de la référence monocouche. Appliquer un RESET intelligent pour la bicouche, Cu peut être ééliminé, ce qui augmente l’intervalle d’isolement dans la couche résistive et la résistance HRS correspondant. Ainsi, ROFF peut récupérer sa valeur initiale, comme indiqué précédemment (Fig.A.24b).

106 A – Résumé en français

(a) (b)

Figure A.24. (a) Les sequence d’endurance des "smart" RESET sont pré- sentés. (b) CDF de R tel que le nombre de cycles augmente de la premiére à 1 × 104 cycle pour les LRS et HRS.

Figure A.25. Description schématique de la production et de l’accumulation de défauts de Cu dans la couche résistive pour la déégradation HRS lors de l’endurance pour monocouche. Dans le cas de bicouches nous prendre un fil en Cu résiduel dans la couche inférieure qui peut être éliminé par l’application d’un effacement intelligent comme on le voit sur la figure A.24a.

Par conséquent, en utilisant une procédure de réinitialisation intelligente au cours du cycle permet de maintenir une fenêtre de mémoire constante de 2 décennies pour 5 1 × 10 cycle (Fig. A.26a) dans GdOx /Al2O3. Les tensions appliquées au cours de SET intelligente et opération de RESET sont indiqués sur la ﬁgure A.26b. Nous pouvons remarquer une augmentation progressive de la tension RESET de -1.5V à

107 A – Résumé en français

(a) (b)

Figure A.26. (a) Caractéristiques d’endurance intelligents pour GdOx /Al2O3. (b) SET et RESET tensions intelligentes appliquées pendant le cyclisme.

-2V afin pour maintenir un HRS stables au fil du temps. Aprés 1000 cycles, une correction est également VSET fait pour compenser l’impact de RESET. Pour décrire les caractéristiques d’endurance, nous avons utilisé un modéÃĺle empirique qui met en corrélation la résistance de l’électrolyte solide à la NT densité volume de piége (voir la figure A.27a) Comme indiqué ci-dessous : [74].

RHRS(NT , tb) = RLRS · (Π/2 · σT · NT · λ · exp(−(Erel/4KT ) + (tb/2λ))+ −1 + exp(−tb/λe)) (A.2)

Oú σT est la section transversale de piége, λ et λe sont les constantes de tunneling, Erel est l’énergie de détente pour les piéges chargés et k, T sont la constante et la tempéérature de Boltzmann. L’augmentation de NT donne naissance à un courant de fuite aprés un RESET, donnant ainsi lieu à un ROFF inférieur. Sur la base de cette équation, nous te aménagé évolution ROFF et dérive des piéges correspondant NT se trouve à suivre une loi de puissance en fonction du nombre de cycles : NT = A·[log(#cycles)]a+B, a=3. Le paramétre A (taux de génération de piége) est réduite de plus d’un facteur 2 quand un bicouche GdOx / Al2O3 est utilisé par rapport à la référence monocouche (Fig. A.27b). Enﬁn, sur la base du modéle, nous avons estimé le piége et contributions Cu à la déérive ROFF en comparant les valeurs ROFF aprés le cyclisme avec et sans Smart Reset ﬁnal (Fig. A.28). GdOx / Al2O3 bicouche réduit la densitéé de piéges généré de 50% par rapport à la référence monocouche. Les caractéristiques de réétention des données sont rapportées à 200 °C pour les 3 échantillons de la Fig. A.29a. Les deux HRS et LRS présentent un comportement stable. Les conditions de programmation au cours de SET sont : VWL−SET = 1V, VA

108 A – Résumé en français

(a) (b)

Figure A.27. (a) Le montage et les caractéristiques d’endurance expérimentales. (b) Nombre des piéges comme un numéro de fonction de cycles pour 3 échantillons a en utilisant la formule NT = A · [log(#cycles)] + B, a=3.

Figure A.28. Nombre des piéges calculée pour chaque échantillon en utilisant la modéle empirique de TAT, tb ﬁxe = 1.5 nm. Relation de R en fonction de NT est calculée selon [74].

= 2V (monocouche) et 2.5V (bicouche) et la durée d’impulsion est de 1 µs. Alors que pendant le fonctionnement RESET : VWL−RESET = 2.5V, VBL = 2V (monocouche) et 1.7V (bicouche) et la durée d’impulsion est de 1 µs. Il est important de noter que le gain de marge de fenêtre obtenue avec bicouches reste stable au ﬁl du temps, même aprés le temps de cuisson de 1 × 105 s. Aucune activation est mesurée sur des échantillons GdOx / Al2O3 jusqu’à 250 °C (Fig. A.29b).

109 A – Résumé en français

(a) (b)

Figure A.29. (a) La distribution de CDF de LRS et les caractéristiques de ré- tention HRS à 200 °C et 250 °C. (b) CDF de LRS et HRS pour le temps de cuisson initiale et ﬁnale pour appareils mono et bicouches.

A.3.1 Conclusion

Dans ce chapitre, nous avons proposé des dispositifs bicouches CBRAM capables d’améliorer la mémoire les performances. Comme on le voit dans la littérature, bicouches offrent une meilleure lecture de l’immunité de déranger, ROFF supérieur et une meilleure endurance ou la conservation des données en fonction de la technologie par rapport aux dispositifs monocouche de CBRAM. Ces amééliorations ont été expliquées par les mécanismes de formation des CF dans la couche résistive ou de l’interface de fond. Algorithmes pour améliorer la fenêtre de programmation ont été proposées, soit en fixant RESET amplitude et la variation de la durée d’impulsion, soit en fixant la durée d’impulsion RESET et augmentant l’amplitude de tension. Un compromis entre ces paramétres peut donner la meilleure performance. Dans notre travail, nous avons intégré mince couche de HfO2 ou Al2O3 avec GdOx . La marge de fenêtre est augmentée de plus d’une décennie, et présente une stabilité à 1 × 105 s à 250 °C pour les dispositifs de bicouches. Une endurance de 1 × 105 cycles est atteinte. Un modéle empirique est proposé de calculer la résistance à l’éétat OFF (HRS) dérive pendant le cycle. La génération de défauts et à l’accumulation progressive de Cu dans l’électrolyte sont pris en compte et dé corrélés.

110 A – Résumé en français

(a) (b)

Figure A.30. (a) La distribution CDF pour vierge la résistance du général 3 CBRAM mesuréée dans les mini-réseaux. résistance Pristine est du ordre de quelques GΩ et est comparable entre les appareils 1T1R et mini-tableaux. (b) Ré- partition de la tension formant, chacun se compose de 64 bits. Un procédé de formation "intelligent" est appliqué.

A.4 Génération 3 CBRAM pour des applications a basse puissance

Dans ce chapitre, nous allons nous concentrer sur une nouvelle technologie de CBRAM qui a l’avantage de courte programmation d’impulsion et de faible consommation d’énergie. Les détails ne seront pas divulgués en raison des politiques confidentielles de l’entreprise. Nous allons principalement concentrés sur la méthodologie afin de caractériser les performances technologiques et les propriétés électriques des appareils testés. La structure reste un empilement MIM, mais les deux IBL et RL a été modifiée par rapport à la seconde / métal-oxyde CBRAM génération de Cu. Les dispositifs sont intégrés dans la BEOL du transistor CMOS. Mini Arrays macros sont composées de 64 bits chacun. à l’intérieur d’une tranche, plus de 100 puces sont mesurables, en fournissant des données statistiques satisfaisantes. Fig. 5.3a la résistance vierge est présentée pour toutes les matrices à l’intérieur d’une tranche de 200 nm. Les mesures de lecture sont effectuées à basse tension de lecture de 0.1V. Fig. A.30a est représenté le CDF de la réésistance vierge pour 6 mini-réseaux. La valeur médiane est d’environ 200 MΩ et est comparable entre 1T1R et mini-réseaux. Les caractéristiques courant-tension typiques sont représentées sur la Fig. 5.4 pour VWL−SET = 1V (Correspondant à 100 µA. Nous pouvons extraire la formation, SET et RESET courants et tensions. VF orming est presque 2.5V et VSET est d’environ 1.5V. Réinitialiser la tension (SET) est inférieure à 1V.

111 A – Résumé en français

(a) (b)

Figure A.31. (a) Impact du courant de conformité sur LRS à partir de l’état vierge et en augmentant progressivement le courant jusqu’à des valeurs de saturation LRS. (b) Impact de la tension RESET sur les HRS et LRS. Pas de panne est remarquéée pour HRS jusqu’à 3V.

Impact du courant de compliance sur LRS à partir de l’état vierge et peu à peu l’augmentation du courant jusqu’à des valeurs de saturation LRS est représentée sur la Fig. A.31a. LRS typiques sont autour de 10 kΩ. Impact de la tension de RESET sur les HRS et LRS est repréésenté sur la figure A.31b. Une rééinitialisation progressive se fait, à partir de bas V et l’augmentation de VBL−RESET jusqu’à 3V. Pas de panne ou inverse parasite SET sont remarquéés pour HRS jusqu’à 3V, confirmant la robustesse du métal-oxyde. HRS typiques sont de l’ordre de 1 MΩ. LRS augmente également V supérieur à 1V. En fait, comme une tension supérieure de remise à zéro est utilisée, il est plus difficile de faire reculer l’appareil dans ses LRS. Les signaux mesurés avec un oscilloscope pendant SET et RESET sont présentés sur la Fig. A.32a et A.32b. Les mesures en utilisant des impulsions de 20 ns sont possibles avec ce setup. Les caractéristiques d’endurance et la distribution de la résistance jusqu’à 500 cycles sont représentées sur la Fig. A.33. Les appareils sont programméés à 20ns. Prés de 1 décennie est stable aprÃĺs 1000 cycles. Des mesures à diverse durée d’impulsion sont effectuées pour étudier l’impact sur les LRS et HRS et la fenêtre de programmation. Fig. A.34a, le CDF de résistance est tracée pour LRS et HRS. Les valeurs de résistance indiquent la distribution pour la mesure de l’endurance jusqu’à 1000 cycles. Comme nous augmentons les impulsions de 20 ns à 1000 ns, LRS dérive vers des valeurs plus faibles. L’appareil affiche un comportement plus "conducteur". Aucune modulation évidente est remarqué pour HRS, indépendamment de largeurs d’impulsion. Prés de 1 décennie est stable pendant 20 ns / 1000 cycles. Fig. A.34b est montré le comportement d’endurance, tracée dans les distributions CDF pour LRS. Varier durée d’impulsion à un impact sur LRS

112 A – Résumé en français

(a) (b)

Figure A.32. (a) Les signaux sur WL, BL et Anode pendant le fonctionnement du SET sont mesurées avec un oscilloscope. (b) Les signaux sur WL, BL et Anode pendant le fonctionnement RESET mesurée à l’aide d’un oscilloscope. Impulsions de 20 ns sont possibles lors de SET et RESET.

Figure A.33. Comportement d’endurance du dispositif 1T1R programmé à 20 ns pour conditions SET / RESET. La distribution CDF de LRS et HRS, 2% de BD est remarqué et à 50% à peu prés une décennie de la fenêtre de mémoire est affichée. de prés d’un facteur 5. En tant que largeur d’impulsion augmente, diminue LRS. Afin de quantifier le pourcentage de cellules qui n’a pas correctement basculer du cycle à cycle, nous avons calculé la probabilité de défaillance en utilisant un critére d’échec : RON > 20 kΩ (Ce qui correspond plus ou moins à la valeur moyenne RON ) et ROFF < 100 kΩ (qui correspond plus ou moins à la valeur moyenne ROFF ). Une

113 A – Résumé en français

(a) (b)

Figure A.34. (a) Répartition des LRS et HRS pendant SET et RESET pour des impulsions variant de 20 ns à 1 µs. (b)(b) CDF de LRS pour des impulsions variant de 20 ns à 1 µs. Un facteur 5 de modulation R est remarqué. LRS médians et l’écart-type calculé pour chaque largeur d’impulsion.

(a) (b)

Figure A.35. (a) Illustration de la déﬁnition de la probabilité de défaillance pour LRS et HRS, les mesures sont eﬀectuées à 50 ns. (b) Le défaut probabilité extrait pour chaque durée d’impulsion pour LRS et HRS.

illustration des critéres d’échec pour RON et ROFF a été représentée sur la figure A.35a. La probabilité calculée pour chaque condition est représentée sur le graphique de la Fig. A.35b. Comme la durée d’impulsion est augmentée, LRS probabilité de défaillance progressivement diminué, passant de 20% à 0%. La même tendance est indiquée pour HRS. Nous voulons quantifier le pourcentage de cellules écrites étant donné la programmation tension et de courant, de le faire, nous utilisons un critére défini comme la probabilité d’écrire les cellules à une certaine valeur LRS : P(RON < 20 kΩ. Comme

114 A – Résumé en français on le voit sur la Fig.A.36, environ 95% des cellules commutées correctement à 20ns durant 1000 cycles. Si l’on calcule la consommation d’énergie à 20 ns :

−4 −9 E = Vprogram · Iprogram · PW = 2.8 · 10 × 10 · 20 × 10 = 5.6 picoJ (A.3)

Grace au comportement de SET rapide, cette technologie est convient pour de- sapplications à faible consommation d’énergie.

Figure A.36. Impact dâĂŹécriture réussie (SET) des opérations sur impulsion différente largeurs. De plus, les mesures sont effectuées VBL différents au cours de RESET et le impact sur LRS est étudié.

Fig.A.37a et sur la Fig. A.37b sont donnés la médiane et la résistance percentile des valeurs pendant le dépistage SET allant VA et VWL−SET respectivement. Para- métres RESET sont fixés : VWL−RESET = 2.7V, VBL−RESET = 2.2V et la largeur d’impulsion de 1 µs. Entre chaque opération SET, une opération de réinitialisation est effectuée. Pour atteindre un LRS inférieur à 100 kΩ, VA devrait être supérieur à 1.8V et VWL−SET supérieur à 0.65V. La valeur de saturation de LRS est d’environ 1 kΩ. Fig. A.38a et sur la Fig. A.38b sont présentées les valeurs de résistance lors de RESET criblage respectivement allant VBL−RESET et VWL−RESET . Paramétres SET sont fixés : VWL−SET = 1V, VBL−SET = 2.6V et de largeur d’impulsion de 1 µs. Entre chaque opération de rééinitialisation, une opération SET est effectuée. Les valeurs sont représentées dans la médiane et percentiles. Pour avoir un HRS supérieur à 100 kΩ, VBL−RESET doit être supérieure à 1.6V et VWL−RESET supérieur à 2.2V. La valeur de saturation de HRS est autour de 1 MΩ. Impact de la largeur de pulse en endurance : Dans Fig. A.39 les cellules ont été programmées à différents largeurs d’impulsion de 100 ns, 200 ns, 500 ns et 1 µs pendant les opérations de SET et RESET. VWL−SET est fixé à 1.2V. D’abord, les

115 A – Résumé en français

(a) (b)

Figure A.37. (a) Le criblage de la tension d’anode pendant le fonctionnement du SET. Départ de HRS, la tension est augmentée progressivement jusqu’à ce que la transition vers LRS se produit (saturation de R indépendante de la tension appliquée). Entre chaque opération, une opération de réinitialisation est terminée. (b) Filtrage de la tension de grille au cours de opération SET. Impulsions de 1 µs sont appliquées.

(a) (b)

Figure A.38. (a) Le criblage de la tension de ligne de bits pendant l’opération de réinitialisation. Départ à partir LRS, la tension est augmentée progressivement jusqu’à ce que la transition se produit à HRS (Saturation de R indépendante de la tension appliquée). Entre chaque opération, une opération SET est fait. (b) Filtrage de la tension de grille pendant l’opération de réinitialisation. A partir de LRS, la tension est augmentée progressivement jusqu’à ce que la transition HRS se produit. Pulse de 1 µs sont appliquées. appareils sont recyclés jusqu’à 100 cycles et les meilleurs paramétres sont identiﬁés en termes de marge de fenêtre et taux BD. En fait, comme nous diminuer la largeur

116 A – Résumé en français

Figure A.39. Mesures d’endurance, les valeurs méédianes (et percentiles) et CFDs sont présentéés pour différents PW pendant SET / RESET. Impulsions varient de 100 ns à 1 µs. Les mesures sont effectuées dans des dispositifs miniarray. d’impulsion plus mauvais comportement de rétention est remarquée. Plus de temps est nécessaire pour stabiliser la mise en place du filament. Comportement d’endurance stable est affiché jusqu’à 200ns, avec prÃĺs de 2 décennies en valeur moyenne et le taux HRS BD de 10. Impact du courant de programmation et de la durée d’impulsion : Dans la figure A.40 cellules ont été programmés à différentes VWL−SET (0.65, 0.8V, 1V et 1.25V) et variable largeur d’impulsion de 100 ns, 200 ns, 500 ns et 1 µs pendant SET et RESET ont éété utilisés. D’abord, les dispositifs sont recyclés jusqu’à 10 fois et les meilleurs paramétres sont identifiés termes de marge de fenêtre et taux BD. En fait, comme nous diminuons la largeur d’impulsion pire comportement d’endurance est remarqué, avec une plus grande vitesse BD et pire marge de fenêtre. Aussi une meilleure endurance est indiquée pour VWL−SET > 0.8V. Ceci peut être corrélé à la taille des filaments, le courant plus éélevé signifie un filament plus épais et plus robuste. Stable comportement d’endurance est montré jusqu’à 200ns, avec prés de 2 déécennies en valeur moyenne. Impact de la tension RESET VBL−RESET en endurance : En Fig. A.41 cellules ont été programmées à différentes VBL−SET (2, 2.2V, 2.4V et 2.6V) à largeur d’impulsion fixe de 500 ns et VBL−SET de 1V. D’abord, les dispositifs sont recyclés jusqu’à 10 fois et les meilleurs paramÃĺtres sont identifiés en termes de marge de fenêtre et taux BD. HRS semble plus bien distribué comme VBL−RESET est augmentée, mais pas

117 A – Résumé en français

Figure A.40. Caractéristiques de distribution pour les mesures d’endurance en mini-arrays sont indiquéés. Les deux PW et VBL−SET sont variés pendant le fonctionnement du SET. de dégradation est constaté pour les deux LRS et HRS aprÃĺs 10 cycles. Supérieur VBL−RESET , induit plus de stress dans l’oxyde et plus d’oxygÃĺne les postes vacants, qui déégradent l’HRS. Une fois que nous avons un aperÃğu de la combinaison de nos paramétres SET / RESET, nous avons décidé de tester nos structures jusqu’à 1 × 106 cycles pour 100 ns (Fig. A.42a) et 500 ns (Fig. A.42b). Nos appareils montrent un bon comportement jusqu’à 1 × 105 cycles, aprés que la fenêtre de mémoire est complétement fermée. Pour la durée d’impulsion de 100 ns il semble que HRS dérive complétement LRS, tandis que pour les deux 500ns LRS et HRS sont responsable de la dégradation de l’endurance. Aussi la variabilité et erratiques points de cycle de pour le cycle sont remarquéés. La principale contribution peut être due à la nature filamentaire du filament. Comme on le voit dans la littérature [75], [77], le filament peut être composé de quelques-unes atomes, et chaque atome peut avoir un point crucial dans le comportement de l’appareil. Les postes vacants dâĂŹoxygéne sont générés lors de l’augmentation du nombre de cycles, et filament morphologie peut être créé, dégradant ou non les performances du dispositif au cours de chaque cycle. Figure A.43a représente le comportement des dispositifs souligné à une tempé- rature élevée de 200 °C pendant 24 heures. Les graphiques représentent LRS et HRS pour difféérents VWL−SET . La rétention est stable pour VWL−SET > 0.8V. Ceci peut être mis en corrélation avec des filaments de la morphologie. à mesure que le courant passe à travers le dispositif, un plus grand filament (diamÃĺtre) est créé, plus robuste et plus difficile à dissoudre. Le dispositif est plus conducteur et LRS est plus faible. En ce qui concerne HRS, caractééristiques de rétention montrent une dérive vers HRS ou HRS en fonction des conditions de programmation. En effet, un grand

118 A – Résumé en français

Figure A.41. Mesures d’endurance, les valeurs médianes (et percentiles) et CFDs sont présentéés pour diﬀérents VBL−RESET jusqu’à 2.6V. Les mesures sont faites dans les dispositifs mini-array.

filament résistif (résultant de RESET opération aprés courant élevé SET) est plus susceptible de se reconnecter avec les électrodes au cours de cuisson, dégradant sa stabilité. Les caractéristiques de rétention de donnéées sont montrées pour VWL−SET fixe de 0.8V à trois différents tempéératures pendant un temps total accumulé au four de 24 heures est montré à la Fig. A.43b. La dérive LRS est remarquée pour LRS. En fait, si le courant de programmation bas est utilisé, un mince filament est créé, ce qui est trés robuste et il peut facilement se dissoudre pendant la cuisson à des températures élevées. Lorsque la température est augmentée de 115 °C à 200 °C, également HRS tend à la dérive vers des valeurs plus élevées. On peut l’expliquer par la morphologie du filament : diffusion verticale du filament peut se produire, en recréant le filament et la réduction la valeur ROFF .

A.4.1 Conclusion

Dans ce chapitre, troisiéme technologie CBRAM génération a été étudiée en termes de ﬁabilitéé et les performances de la mémoire. Géénie des matériaux a été fait pour

119 A – Résumé en français

(a) (b)

Figure A.42. (a) Endurance mesures pour appareils 1T1R jusqu’à 1 × 106 cycles pour 100 ns sont présentés. Aprés 1 × 105 cycles, la dérive vers HRS LRS semble être le principal facteur de fermeture de la fenêtre de mémoire. (b) Les mesures d’endurance pour les appareils 1T1R jusqu’à 1 × 106 cycles pour 500 ns. Aprés 1 × 105 cycles, les deux HRS dérivent vers LRS et LRS vers HRS sont responsables de la dégradation de l’endurance.

(a) (b)

Figure A.43. (a) Les caractéristiques de rétention de données sont montrées pour difféérentes VWL-SET à 200 °C pendant 24 heures. (b) Des caractéris- tiques de rétention de données sont montrées pour différentes tempéératures à VWL=0.8V pendant 24 heures. toute la structure MIM. L’idée était d’améliorer le comportement d’endurance, com- binée à une bonne stabilité thermique. Les valeurs de formation semblent être autour de 3V et sont relativement plus élevés que les dispositifs avec GdOx (2.5V), mais plus courtes impulsions de programmation sont utilisées (jusqu’à 20ns), ce qui signifie moins de consommation d’énergie est utilisée pour programmer nos appareils. Im- pulsions typiques de 1 µs ont été utilisés pour commuter des cellules GdOx CBRAM.

120 A – Résumé en français

Aussi MOx semble mieux résister rupture de tension par rapport à GdOx . Le comportement d’endurance a été étudié pour les deux 1T1R et dispositifs mini-array. Différentes conditions P/E ont été utilisés au cours des opérations SET/RESET. Leur impact sur le comportement de l’endurance a été étudié et analysé et les meilleurs paramétres ont été identifiés pour atteindre 1 × 105 cycles pour 100 ns. Endurance ont été réalisées et LRS ou HRS semble être responsable pour l’endurance la dégradation en fonction des conditions de programmation. Variabilité est remarquée de cellule à cellule et d’un cycle à nos structures, et nous avons essayé de trouver nos meilleures conditions pour surmonter ce probléme. Prés de 2 décennies de fenêtre de la mémoire ont été présentés pour 100 ns / 1 × 105 cycles. La conservation des données a été réalisée pour des températures allant jusqu’à 200 °C pendant 24 heures de temps de cuisson. Nous avons remarqué que les deux LRS et HRS ont tendance à se dégrader, mais en suivant les mécanismes de défaillance différents en fonction des conditions de programmation.

A.5 Conclusions General

Dans cette thése, nous avons abordé le comportement de rétention des données à des températures élevées, en commençant par une vue d’ensemble de l’Etat de l’Art de la CBRAM. Les résultats expérimentaux et modéles ont été présentés pour expliquer la perte de rétention pour les différentes technologies de CBRAM. Arrhenius a été utilisé pour extraire la température qui assure 10 ans de conservation des données. Des algorithmes de programmation ont été proposés afin d’améliorer les caractéristiques de la rétention. Dans les essais de température accélérée, il est ap- paru que le temps de rétention diminue avec la diminution de la taille des CF, qui est associée à la diffusion des postes vacants / ions de CF lors de la cuisson à haute température. Le compromis entre la résistance et la stabilité thermique a été élucidé. Si les conditions fortes sont utilisées pour faire défiler l’appareil (pour atteindre la fenêtre de programmation de haut), moins de stabilité en température est obtenue. Nous avons démontré que les conditions de programmation dans CBRAM à base d’oxyde peuvent être optimisés afin d’atteindre un faible courant électrique SET (30 µA et l’exploitation modérée de la fenêtre de température, ou stable comportement à 250 °C et 100 µA courant de SET. Basé sur des données expérimentales et des simulations, le mécanisme physique régissant l’échec de rétention de CBRAM à base d’oxyde a été clarifié. En particulier, une corrélation claire entre la forme du filament (en fonction de SET et RESET conditions) et LRS et HRS stabilité thermique a été mise en place : la hausse des courants de conformité entraîne un filament plus épais, plus robuste et difficile à RESET. D’autre part, des courants faibles de programmation se traduisent par un filament plus faible, plus facile à dissoudre pendant le temps de cuisson. Nous bicouches également proposés CBRAM dispositifs capables d’améliorer les performances de la mémoire. Comme on le voit

121 A – Résumé en français dans la littérature, bicouches offrent une meilleure lecture de l’immunité de déran- ger, supérieur ROFF et une meilleure endurance ou la conservation des données (en fonction de la technologie) par rapport aux dispositifs monocouche de CBRAM. Ces améliorations ont été expliquées par les mécanismes de formation des CF dans la couche résistive ou de l’interface de fond. Des algorithmes pour améliorer la fenêtre de programmation ont été proposées, soit en fixant RESET amplitude et faire varier la durée d’impulsion, soit en fixant une durée d’impulsion de réinitialisation et l’augmentation de l’amplitude de tension. Un compromis entre ces paramétres peut donner la meilleure performance. Dans notre travail, nous avons intégré mince couche de HfO2 ou Al2O3 avec GdOx . La marge de fenêtre est augmentée de plus d’une décennie, et présente une stabilité jusqu’à 1 × 105 cycles à 250 °C pour les dispositifs de bicouches. Une endurance de 1 × 105 cycles cycles est atteinte. Un modéle empirique est proposé de calculer la dérive de résistance de l’état OFF (HRS) au cours du cycle. La génération de défauts et à l’accumulation progressive de Cu dans l’électrolyte sont pris en compte et dé corrélés. En conclusion, l’intégration d’une interface de fond dans un dispositif de CBRAM permet de réduire la concentration de défauts 50%, améliorant ainsi les caractéristiques de la fenêtre de mémoire et d’endurance. La fenêtre plus grande résulte un éécart plus important entre le filament et le reste L’électrode inférieure. Enfin, nous avons discuté de la troisiéme géénérationde de CBRAM technologie. Génie des matériaux a éété fait pour toute la structure MIM. L’objectif éétait d’améliorer le comportement d’endurance, combinée à une bonne stabilité thermique tout en gardant l’utilisation de matéériaux simples, faciles à intégrer dans la technologie CMOS. Former des valeurs autour de 3V (à savoir relativement plus élevé que les appareils avec GdOx (2.5V)) ont été présentés, mais plus courtes impulsions de programmation ont été utilisés (jusqu’à 20 ns), ce qui indique que moins de consommation d’énergie est utilisée pour programmer nos appareils. Impulsions typiques de 1 µs ont été utilisés pour commuter des cellules GdOx CBRAM. Aussi MOx semble mieux résister rupture de tension par rapport à GdOx . Le comportement d’endurance a été étudié pour les deux 1T1R et dispositifs mini-array. Différentes conditions P / E ont été utilisés au cours des opérations SET / RESET. Leur impact sur le comportement de l’endurance a été étudié et analysé et les meilleurs paramétres ont été identifiéés pour atteindre 1 × 105 cycles pour 100 ns. Endurance ont été réalisés, et les deux LRS et HRS sont responsables de la dégradation de la résistance en fonction des conditions de programmation. La largeur d’impulsion diminue, la HRS diminue. Le filament a besoin d’une impulsion plus grande pour former et stabiliser. Variabilité a été remarquée de cellule à cellule et d’un cycle à nos structures, et des conditions optimisées ont été identifiées pour surmonter ce probléme. Prés de 2 décennies de fenêtre de la mémoire ont été présentés pour 100 ns / 1 × 105 cycles. La conservation des données a été réalisée pour des températures allant jusqu’à 200 °C pendant 24 heures de temps de cuisson. Nous avons remarqué que les deux LRS et HRS ont tendance à se dégrader, mais

122 A – Résumé en français en suivant les mécanismes de défaillance différents en fonction des conditions de programmation. Ceci peut également être mis en corrélation avec la morphologie du filament. Des filaments plus épais, formés par un grand courant de programmation sont plus robustes et stables à la conservation des données.

A.5.1 Perspectives Les travaux futurs peuvent être faits pour optimiser les performances de l’appareil CBRAM. Fiabilité en termes de rétention et d’endurance doit être optimiséée afin de permettre CBRAM industrialisation et être compatible avec les exigences du marché du NVM. Génie des matériaux est nécessaire afin de trouver les meilleurs matériaux, qui sont peu coûteux et facile à intégrer dans la technologie CMOS actuelle. En particulier, la qualité de la couche résistive pour réduire la concentration de dééfauts et la production au cours de SET et RESET opérations devraient être améliorées, afin de limiter la déégradation CBRAM pendant l’endurance. Variabilité reste l’un des problémes cléés en particulier pour HRS, et devraient être traitées dans plus de détails, afin d’améliorer l’uniformité du comportement de l’appareil. En effet, la distribution de la réésistance à l’échelle empêche de grande densité MRAM l’intégration. Des algorithmes de programmation peuvent également être envisagés afin de corriger le comportement d’endurance. Donc, les algorithmes de correction doivent être développés pour maintenir une fenêtre stable. "Endurance intelligente" par exemple, peut aider à contrôler en permanence et maintenir HRS stables. Formation à puce pour une meilleure fiabilité (limitation de l’énergie fournie au systéme pendant l’opération de formation) doit être éégalement mis en œuvre.

123 Appendix B

Author’s publications

International conferences

[1] M. Barci, J. Guy, G. Molas, E. Vianello, A. Toffoli, J. Cluzel, A. Roule, M. Bernard, C. Sabbione, L. Perniola, and B. De Salvo, «Impact of SET and RE- SET conditions on CBRAM high temperature data retention», in Reliability Physics Symposium, 2014 IEEE International, Jun. 2014, 5E.3.1–5E.3.4. doi: 10.1109/IRPS.2014.6860677. [2] M. Barci, G. Molas, A. Toffoli, M. Bernard, A. Roule, C. Cagli, J. Cluzel, E. Vianello, B. De Salvo, and L. Perniola, «Bilayer metal-oxide cbram technology for improved window margin and reliability», in Memory Workshop (IMW), 2015 IEEE International, IEEE, 2015, pp. 1–4. [3] G. Molas, E. Vianello, F. Dahmani, M. Barci, P. Blaise, J. Guy, A. Toffoli, M. Bernard, A. Roule, F. Pierre, et al., «Controlling oxygen vacancies in doped oxide based cbram for improved memory performances», in Electron Devices Meeting (IEDM), 2014 IEEE International, IEEE, 2014, pp. 6–1. [4] G. Molas, J. Guy, M. Barci, F. Longnos, G. Palma, E. Vianello, P. Blaise, B. De Salvo, and L. Perniola, «Conductive bridge ram (cbram): functionality, reliability and applications», in International Conference on Solid State Devices and Materials (SSDM) 2015, 2015. [5] M. Barci, J. Guy, G. Molas, E. Vianello, A. Toffoli, J. Cluzel, A. Roule, M. Bernard, C. Sabbione, L. Perniola, et al., «Impact of set and reset conditions on cbram high temperature data retention», in Journal of the Electron Devices Society, 2016 IEEE International, IEEE, 2016.

124 B – Author’s publications

Patents

[1] G. Molas and M. Barci, Living resistive memory device, US Patent 20,160,111,637, Apr. 2016.

125 Bibliography

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