A 7 Bit 3.52 Ghz Current Steering DAC for Wigig Applications

A 7 bit 3.52 GHz Current Steering DAC for WiGig Applications

Maria Helena Casaca da Trindade

Thesis to obtain the Master of Science Degree in

Electrical and Computer Engineering

Supervisors: Prof. Jorge Manuel dos Santos Ribeiro Fernandes Eng. António Ilídio Rocha Leal

Examination Committee: Chairperson: Prof. Gonçalo Nuno Gomes Tavares Supervisor: Prof. Jorge Manuel dos Santos Ribeiro Fernandes Members of Committee: Prof. João Manuel Torres Caldinhas Simões Vaz

June 2016

Acknowledgements

Firstly, I would like to thank Synopsys for the opportunity to develop this thesis with their collaboration and using their resources. In particular, I would like to thank Engineer António Leal for all his guidance and help with practical knowledge which was essential to the project. I would also like to thank all of the DACs team at Synopsys for their insightful tips throughout the project. I would also like to thank Professor Jorge Fernandes for giving me the opportunity to develop this thesis and for all the guidance throughout the project. My colleagues Marta Freire and João Ribeiro should be mentioned. I would like to thank Marta for the friendship we developed during these 5 years at Técnico where we shared an insane amount of hours working on projects and labs. I would also like to mention João who is also developing a thesis at Synopsys and with whom I shared many concerns and questions about the project during our lunch breaks. My parents must also be mentioned for their support throughout my whole life, allowing me to take my Master’s Degree and especially during the months I developed the thesis. Even away they listened to my concerns and victories and encouraged me every step of the way. My grandfather who during the development of this thesis I lost to the battle against cancer but to whom I dedicate this thesis. The person who always valued my education and always encouraged me to thrive for success. My grandmother who was always there for me, to comfort me and support me. I would also like to thank my brother for his insightful tips about life and about success which make me always thrive for the best. I would also like to refer my aunt and uncle for their encouragement and support. Finally, I would like to thank my friends, especially my best friend Sara Ribeiro, who although many times could not count with my presence during these months, was always there for me with kind words of encouragement.

Abstract

A Digital to Analog Converter (DAC) is a system that translates an input digital code into a sum of electrical units that appear at the output as an analog electrical signal. In this thesis a DAC to be used in the 60 GHz radio frequency (RF) band extended from the standard Wi-Fi is developed. This converter developed in a 28 nm CMOS technology works with 7 bit resolution input data at a sampling rate of 3.52 GHz. The architecture used in this DAC is the Current Steering which consists of four main blocks: Current Source, Driver Circuit, Biasing Circuit and Decoder. The Current Source generates the current of a branch associated with a bit of the input code that will be switched on/off to the output, being the output the sum of the currents of the branches that are active. The Driver Circuit synchronizes and shapes the signals that control the switches in each current source. The Biasing Circuit generates a stable voltage that bias the Current Source transistors. The Decoder translates the input bits into thermometer bits. In this project there is an initial study of the subject to understand the constraints of this type of converter, a development of a mathematical model to initially predict the behavior of the circuit, a dimensioning of the complete schematic circuit and finally the layout of the dimensioned circuit. In each phase of the project the results will be further analyzed and the decisions about the procedure followed will be further discussed.

Keywords: Digital to Analog Converter, Current Steering, WiGig, 28 nm, High Update Rate

Resumo

Um Conversor Digital Analógico (DAC) é um sistema que traduz um código de entrada digital numa soma de unidades eléctricas resultando à saída um sinal eléctrico analógico. Nesta tese é desenvolvido um DAC para ser utilizado na banda de rádio frequência dos 60 GHz, extensão do standard Wi-Fi. Este conversor, desenvolvido numa tecnologia de 28 nm CMOS, funciona para códigos de entrada de 7 bit a uma frequência de amostragem de 3.52 GHz. A arquitectura utilizada é a “Current Steering” constituída por quatro blocos principais: fonte de corrente,“Driver”, circuito de polarização e descodificador. A fonte de corrente gera a corrente de cada ramo associado a um bit do código de entrada que será activado ou não para a saída, resultando esta como a soma das contribuições dos ramos da fonte de corrente que estão activos. O circuito de “Driver” sincroniza e molda as formas de onda que controlam os interruptores em cada fonte de corrente. O circuito de polarização gera uma tensão estável que polariza os transístores da fonte de corrente. O descodificador traduz os bits de entrada em bits termómetro. Neste projecto é feito um estudo do tema de forma a compreender as restrições deste tipo de conversor, é elaborado um modelo matemático para prever o comportamento do circuito, é feito o dimensionamento do esquemático do circuito e por fim é feito o layout do circuito dimensionado. Em cada fase do projecto os resultados obtidos são analisados e as decisões tomadas em relação ao procedimento seguido são discutidas.

Palavras-chave: Conversor Digital Analógico, “Current Steering”, WiGig, 28 nm, frequência de amostragem elevada

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Contents

1. Introduction...... 1

1.1 Motivation ...... 1

1.2 State of the Art ...... 2

1.3 Technology: 28 nm CMOS ...... 3

2. Digital to Analog Converter: Definition and Characterization ...... 6

2.1 Performance Specifications ...... 6

2.2 DAC Architectures ...... 8

3. Current Steering Architecture...... 14

3.1 Different Codification Schemes ...... 14

3.2 Basic Blocks ...... 15

3.3 Static/Dynamic Analysis ...... 20

3.3.1 Static Behavior ...... 20

3.3.2 Dynamic Behavior ...... 23

4. Design Methodology of the DAC ...... 25

4.1 Level of Segmentation ...... 25

4.2 Current Source Design ...... 27

4.3 Biasing Circuit Design ...... 33

4.4 Latch and Driver Circuit Design ...... 37

4.5 Decoder Architecture ...... 40

4.6 Clock Driver ...... 44

4.7 Design Constraints ...... 45

4.7.1 Matching ...... 45

4.7.2 Output Impedance ...... 45

4.7.3 Switching Errors ...... 46

4.7.4 Timing Inaccuracies ...... 48

4.8 Results and Conclusions ...... 49

5. Layout ...... 55

5.1 Layout Rules and Techniques ...... 55

5.2 Results of the Layout Blocks ...... 58

5.2.1 Latch Bank ...... 58

5.2.2 Switches and Cascode ...... 60

5.2.3 Current Source ...... 62

5.2.4 Biasing Circuit ...... 64

5.2.5 Clock Driver ...... 67

5.2.6 Registers and Decoder Block ...... 69

5.2.7 Complete DAC ...... 71

6. Results and Conclusions ...... 73

7. Future Work...... 77

8. References ...... 78

9. Attachments ...... 81

List of Figures

Figure 1 – Example of the device scaling by 훼. [19] ...... 4 Figure 2 – Example of some metrics of the DAC...... 7 Figure 3 – Output spectrum of the DAC with representation of the harmonics of the signal and the SFDR...... 8 Figure 4 –Example of the resistor string DAC architecture...... 9 Figure 5 – Example of the binary weighted resistor DAC architecture...... 10 Figure 6 – R-2R resistor ladder DAC architecture...... 10 Figure 7 – Example of the capacitor DAC architecture...... 11 Figure 8 – Example of a Current Steering architecture with two types of implementation a) The Binary Implementation and b) The Unary Implementation...... 12 Figure 9 - Types of Output: a) Single-Ended Output and b) Differential Output...... 13 Figure 10 – Current Steering Architecture with a segmented implementation...... 15 Figure 11 – Basic Block Diagram for a Segmented Current Steering DAC...... 16 Figure 12 – Example of the topology of a driver...... 17 Figure 13 – Example of the topology of a) level shifter and b) latch...... 17 Figure 14 – Example of the topology of a current cell a) single and b) cascode...... 18 Figure 15 – Schematic of a basic current mirror...... 19 Figure 16 – Schematic of a cascode current mirror...... 20 Figure 17 – Comparison between the INL_yield obtained by [17] through Monte Carlo simulations and the INL_yield obtained through the High Level Model of the DAC developed in this project...... 26 Figure 18 – Topology of the basic current cell...... 28 Figure 19 – Topology of the current source cell with a cascode transistor...... 29 Figure 20 – a) Schematic of the basic current cell, b) Output impedance seen from the drain of the switch transistor over frequency...... 30 Figure 21 – a) Schematic of the basic current cell with cascode topology, b) Output impedance of the cell over frequency...... 31 Figure 22 – Example of the current mirror of the Biasing Circuit for the Current Source Array. . 33 Figure 23 – Example of the circuit for the Reference Current Generator...... 34 Figure 24 – Circuit of the one stage OpAmp and the second stage which is the current reference...... 35 Figure 25 – Circuit of the Voltage Reference Generator...... 36 Figure 26 – Schematic of the Current Reference of the OpAmp...... 37 Figure 27 – Example of a driver with crossing point due to rise and fall time...... 38 Figure 28 – Flip Flop used in the Driver...... 39 Figure 29 – Diagram of the behavior of the flip flop...... 40 Figure 30 – Thermometer Row and Column Decoder Matrix Architecture...... 41

Figure 31 – Local Decoder of the Thermometer Decoder Matrix...... 41 Figure 32 – Logic Circuits for each of the outputs of the Row and Column Decoder...... 42 Figure 33 – Scheme of the Decoding Block of the DAC...... 43 Figure 34 – Schematic of the Register...... 43 Figure 35 – Driver circuit using a cascade of inverters to drive a capacitive load...... 44 Figure 36 – Spike in the common node due to switching errors...... 46 Figure 37 – Output signal influence on the common node of the Current Source...... 48 Figure 38 – The ideal sampling moments (dashed line) and the actual sampling moments due to jitter...... 49 Figure 39 - Waveforms of the Input Bits, the Clock and the Output Differential Signal for the Complete Schematic Circuit...... 50 Figure 40 – Frequency Spectrum for the Differential Output of the DAC for the Complete Schematic Circuit in typical corner...... 51 Figure 41 – Variation in layer line with minimum width during fabrication...... 56 Figure 42 – Example of layout using Common-centroid technique...... 57 Figure 43 – Example of layout using Cross-Coupling technique...... 57 Figure 44 – Layout Planning of the Circuit...... 58 Figure 45 - Layout of the Latch...... 59 Figure 46 - Layout of the Bank of Latches...... 59 Figure 47 - Layout of the Switch and Cascode transistors of the LSB bit and a thermometer bit...... 61 Figure 48 - Layout of the Latches, Switches and Cascode...... 61 Figure 49 - Scheme of the Common Centroid used in the Matrix of the Current Source...... 62 Figure 50 - Layout of the Matrix of Current Source Transistors...... 62 Figure 51 – Layout of the Current Source, Cascode, Switches and Latches...... 63 Figure 52 - Layout of the Voltage Reference Generator...... 65 Figure 53 - Layout of the Current Reference Generator...... 65 Figure 54 - Layout of the OpAmp...... 65 Figure 55 – Layout of the Biasing Reference of the OpAmp...... 66 Figure 56 - Layout of the Complete Biasing Circuit...... 66 Figure 57 - Layout of the Clock Driver...... 68 Figure 58 – Layout of the Latency Equalizer...... 70 Figure 59 – Layout of a Register...... 70 Figure 60 – Layout of the Local Decoder of the Matrix Decoder...... 70 Figure 61 - Layout of the Decoder of the Thermometer Bits...... 70 Figure 62 – Layout of the complete Registers and Decoder Block...... 71 Figure 63 – Layout of the Complete DAC...... 72 Figure 64 – INL_yield for segmentation 6MSB/1LSB for 휎퐿푆퐵(퐼)/(퐼) = 0.0424 for a differential output...... 81

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Figure 65 – DNL_yield for segmentation 6MSB/1LSB for 휎퐿푆퐵(퐼)/(퐼) = 0.0424 for a differential output...... 81 Figure 66 – INL_yield for segmentation 7MSB/0LSB for 휎(퐼)/(퐼) = 0.05 for a differential output...... 82 Figure 67 – DNL_yield for segmentation 7MSB/0LSB for 휎퐿푆퐵(퐼)/(퐼) = 0.05 for a differential output...... 82 Figure 68 - Spectrum of output voltage of the DAC for the circuit with the layout blocks for the typical corner...... 90

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List of Tables

Table 1 – Comparison of published arts with similar specifications...... 3 Table 2 – Dimension of the transistors in the Current Source...... 32 Table 3 - Output Current and Output Impedance of the Current Source after dimensioning. .... 32 Table 4 – Values of the current references 퐼푅푒푓, 퐼푅푒푓1 and 퐼푅푒푓2 after dimensioning of the biasing circuit...... 34 Table 5 – Specifications of the OpAmp obtained after dimensioning...... 35 Table 6 – Voltage Reference obtained after dimensioning of the Voltage Reference Generator...... 36 Table 7 – Biasing Current for the OpAmp after dimensioning of the Current Reference Circuit of the OpAmp...... 37 Table 8 – Rise and Fall Times of the Driver Circuit...... 38 Table 9 – Value of the Crossing Point of the Control Signals of the Switches...... 39 Table 10 – Truth Table for the Row and Column Decoders of the Thermometer Decoder...... 42 Table 11 – Decoding and Latency Time of the Thermometer Decoder and Latency Equalizer . 43 Table 12 – Dynamic Performance of the Complete Schematic Circuit...... 52 Table 13 – Dynamic Performance of the Schematic Circuit for a 1 훺 resistance in the supply voltage...... 53 Table 14 - Dynamic Performance of the Schematic Circuit for Monte Carlo simulations...... 54 Table 15 - Dynamic Performance of the DAC considering the circuit with the extracted Layout of the Bank of Latches...... 59 Table 16 – Dynamic Performance Comparison between the Schematic circuit and the circuit with the extracted Layout of the Bank of Latches ...... 60 Table 17 – Dynamic Performance Comparison between the circuit with the extracted Layout of the Bank of Latches and the extracted Layout of the Current Source Block...... 64 Table 18 – Dynamic Performance Comparison between the Layout of the Bank of Latches and the Layout of the Current Source Block...... 67 Table 19 – Dynamic Performance comparison between the circuit with the Layout of the Current Source Block and Biasing Circuit and the circuit with the Layout of the Current Source Block, Biasing Circuit and Clock Driver...... 69 Table 20 – Dynamic Performance of the DAC considering the Layout of the Current Source Block, the Biasing Circuit, the Clock Driver and the Decoder...... 74 Table 21 – Dynamic Performance of the DAC considering the Layout of the Current Source Block, the Biasing Circuit, the Clock Driver and the Decoder with a resistance of 1 훺 in the supply voltage...... 75 Table 22 - Performance Comparison of Published arts with the work developed...... 76 Table 23 – INL/DNL specification computed through the high level model of the DAC for a given segmentation...... 83

Table 24 – Dynamic specifications not considering jitter computed through the high level model of the DAC...... 83 Table 25 – Dynamic specifications considering jitter computed through the high level model of the DAC...... 83 Table 26 – Dimensions of the transistor of the Current Reference Generator...... 83 Table 27 – Dimensions of the transistors of the OpAmp...... 84 Table 28 – Dimensions of the transistors of the Voltage Reference Generator...... 84 Table 29 - Dimensions of the transistors and resistor of the Current Reference of the OpAmp. 84 Table 30 - Dimensions of the transistors of the Driver...... 84 Table 31 - Dimensions of the transistors of the Flip Flop of the Driver...... 84 Table 32 - Dimensions of the transistors of the Local Decoder...... 85 Table 33 – Dimensions of the transistors of the Row and Column Decoders...... 85 Table 34 - Dimensions of the transistors of the Latency Equalizer...... 85 Table 35 - Dimensions of the transistors of the Register...... 86 Table 36 - Dimensions of the transistors of the Clock Driver...... 86 Table 37 – Corners Description ...... 87 Table 38 - Dynamic Performance of the DAC considering the Layout of Latches, Switches, Cascode and Current Source transistors...... 88 Table 39 - Dynamic Performance of the DAC considering the Current Source Block and the Biasing Circuit...... 88 Table 40 - Dynamic Performance of the DAC considering the Layout of the Current Source Block, the Biasing Circuit and the Clock Driver...... 89 Table 41 – Differences in the Dynamic Performance between the layout and schematic...... 91

List of Acronyms

DAC – Digital to Analog Converter SNDR – Signal to Noise plus Distortion Ratio INL – Integral Non-Linearity Error DNL – Differential Non-Linearity Error LSB – Least Significant Bit MSB – Most Significant Bit SFDR – Spurious Free Dynamic Range SNR – Signal to Noise Ratio THD – Total Harmonic Distortion ADC – Analog to Digital Converter VHDL - VHSIC Hardware Description Language W – Width L – Length DEM – Dynamic Element Matching DC – Direct Current FFT – Fast Fourier Transform BW – Bandwidth OpAmp – Operational Amplifier

LVT – Low Vt

HVT – High Vt SUC – Stacked Unit Cell GS – Giga Samples

1. Introduction

The project described in this report consists on the development of a Digital to Analog Converter (DAC) with 7 bit resolution and a sampling rate of 3.52 GHz to be used in communication systems exploring the high frequency spectral band around 60 GHz. The resulting DAC needs an SNDR (Signal to Noise plus Distortion Ratio) of about 35 dB and an INL/DNL (Integral Non-Linearity Error / Differential Non-Linearity Error) of about 1 LSB. The DAC is to be implemented in a 28 nm CMOS technology. This chapter presents the motivation for developing this system, the work already done in this field and a brief analysis of the technology in which the circuit is going to be implemented.

1.1 Motivation

Telecommunications systems nowadays require high performance and high speed digital and analog systems integrated on one chip at the lowest possible cost. These new telecommunication devices have evolved towards broadband systems with moderate signal-to- noise ratios using data converters that according to [1] have to operate at ever increasing sampling rates, but requiring less precision. An example of these new requirements is the use of the 60 GHz radio frequency (RF) band extended from the standard Wi-Fi, also known as WiGig (IEEE 802.11ad standard), with ultra-wide communication bandwidth. This allows the equipment to achieve multi gigabit per second data rates in indoor wireless transmissions. In this standard according to [2] and [3], it is possible to use two modulation schemes in transmission: the single carrier (SC) with frequency sampling of 3.52 GHz and bandwidth of 1.76 GHz and the orthogonal frequency-division multiplexing (OFDM) with frequency sampling of 2.64 GHz and a bandwidth of 2.16 GHz. Since the information transmitted through wireless is digital data but the signals used in the devices are analog signals, like current or voltage, it is essential to use data converters. In most systems-on-chip, according to [4], these data converters often limit the performance of the overall system, so it is essential they achieve the appropriate speed and resolution to enable high data rates. In the case of ultra-wideband systems like WiGig the requirement nowadays is for very high speed but low resolution data converters. Today there is a growing need for energy efficient systems, especially in the communications mass market. Reducing the power consumption of the devices and hence having a more efficient system can be achieved by downscaling the technology. However the scaling of the technology in DACs is very challenging because the reduction of the gate oxide thickness imposes a limit to the maximum voltage that can be applied to the device, forcing in many cases the circuits to be design with two supply voltages. Moreover, the threshold voltage of the transistors cannot be scaled accordingly. So designing DACs becomes more challenging because the freedom of voltage margins are much lower. These most advanced CMOS technologies also feature reduced voltage gain of the transistors, increasing the distortion of the

DAC as stated in [5]. Another major challenge on DACs designed for communication applications, according to [6], is that they require a large SFDR, which is not straightforward to achieve at high signal frequencies. This project will be a contribution to the development of DACs which combine a high update rate and a low power supply. Since these two specifications combined in scaled technologies like the 28 nm present a challenge to the designers, this project will be a step forward in achieving the performance required while meeting these specifications. Through the use of different approaches to the topologies of the different blocks of the DAC, the correct operation of the circuit for low power supply will be assured. The correct dimensioning of the circuit will guarantee the required specifications while a careful layout will assure the minimum losses and enhance the maximum performance.

1.2 State of the Art

The first records of the use of a DAC are not in electronic form but rather in hydraulic form by the use of a metering system, using water tanks, in the nineteenth century in the Ottoman Empire. Throughout the years as the telecommunication systems evolved so have the specifications for data converters. The need for systems with larger capacity and higher speed resulted in the enhancement and proliferation of the electronic data converters. Throughout the years there were many factors helping to spread these systems: not only the proliferation of discrete transistor circuits during the sixties, but a number of integrated circuit building blocks became available which led to size and power reductions in data converters. In more recent years there is the trend for power consumption reduction, and along with it, of the supply voltages. The drop in supply voltages to 5 V, 3.3 V, 2.5 V, and 1.8 V have followed as CMOS line spacing shrank to 0.6 µm, 0.35 µm, 0.25 µm, and 0.18 µm. The resulting smaller surface mount and chip-scale packages, according to [7], results in a "smart partitioning" that can offer a higher performance and more cost effective solution, much more adaptable to different systems than the simple system on chip. Nowadays depending on their purpose we can find DACs with an accuracy around two dozens of bits or update rates of a few Gigasamples/s, not simultaneously since there is a trade-off between resolution and update rate. An example of the high accuracy DACs is the 15 bit DAC presented in [8] and an example of the high update rate DACs is the 8GS/s 6 bit DAC presented in [9]. Regarding the specifications of this project we can find some examples of papers that have similar content. In recent publications like [10], a DAC intended for WiGig applications with a sampling rate of 3.1 GS/s, 6 bit resolution, a SFDR ≥ 37.2 dB and a SNDR ≥ 29 dB over the Nyquist input in a 90 nm technology is presented. The approach when designing this DAC, in order to have a wide linear band, was to use a topology with SUC (Stacked Unit Cell). In order to reduce the power consumption and the hardware overhead, a full binary topology was

implemented. Some other examples with similar specifications are presented in Table 1 regarding the contents in [11], [12] and [13]. In [11] a DAC with a 3.5 GS/s sampling rate, 6 bit resolution and a SFDR > 40 dB over 800 MHz was implemented in a 28 nm technology. In this design the use of a cascode topology is avoided, so the voltage headroom for the current source transistor increases and a CML (Current-Mode Logic) data switching scheme is used providing natural differential signaling for the switches of the current source. In [12] is presented a DAC with a 3.3 GS/s sampling rate, 6 bit resolution and a SFDR of 36.4 dB at a Nyquist input signal, implemented in a 90 nm technology. Similar to [10] this paper presents a SUC implementation in order to reduce the parasitic capacitance in the current source by reducing the interconnection from the current source to the current switch. Finally in [13] a DAC with 3 GS/s sampling rate, 6 bit resolution and a SFDR > 36 dB over the Nyquist frequency at 3 GS/s is implemented in a 90 nm technology. The main difference to the other publications is that it uses what they call a bipolar topology for the current source with both NMOS and PMOS transistors which presents half of the power consumption of an implementation with only either NMOS or PMOS transistors.

Table 1 – Comparison of published arts with similar specifications.

Reference [10] [11] [12] [13] Sampling Rate (GS/s) 3.1 3.5 3.3 3 Resolution (bit) 6 6 6 6 Technology (nm) 90 28 90 90

SFDR @ 푓푠/2 (dB) 37.2 30.6 36.4 36.0

SNDR @ 푓푠/2 (dB) 29 n.a. n.a. n.a. INL/DNL (LSB) 0.09/0.06 0.03/0.03 0.25/0.22 0.07/0.05 Power Consumption (mW) 17.7 53.0 47.0 8.3 Core Area (푚푚2) 0.038 0.035 0.055 0.045

1.3 Technology: 28 nm CMOS

The trend across the years on integrated circuits has been for lower cost, higher speed, higher density and lower power consumption devices. According to [14] scaling the transistors dimensions has been the key for today systems with higher performance, reduced cost and reduced physical size. In this reduction the limits of the CMOS (Complementary Metal Oxide Semiconductor) have been reached and surpassed while the basic design of the transistors has been kept almost the same.

The downscale of the technology has set a lot of demands on the properties of the 푆푖푂2 gate oxide. Although it offers several advantages and its properties and processing techniques have been analysed for decades, there is a limitation on the ability to further reduce the gate oxide thickness without risking the breakdown of the device. Recently this reduction has been

slower, when compared with previous pace, because of issues like the process controllability, high leakage current or reliability. A very small variation on the device thickness can result in changes in the device operation condition which makes it very difficult to maintain device tolerances. The exponential increase in the gate dielectric leakage current causes concerns regarding the standby power dissipation, reliability and lifetime of the transistor. The reduction of both voltage level and gate oxide thickness when scaling down the dimensions of the MOSFET results in a higher source to drain leakage current. Since the electron thermal voltage (푘푇/푞) is constant for room temperature, then the ration between the operating voltage and the thermal voltage shrinks, so the thermal diffusion electrons lead to a higher leakage current. In general according to [15] the ideal scaling of the technology follows three essential rules: 1. Reduce all the lateral and vertical dimensions by a constant 훼 (훼 < 1); 2. The threshold and supply voltages are reduced by 훼; 3. The doping levels of the devices are increased by 훼. The idea is to ensure that the electric fields in the transistor are kept constant since all these parameters scale proportionally. One of the main impacts of the ideal scaling is the reduction of the supply voltage but in reality the technology scaling has not followed the ideal trend. The threshold voltage of MOS transistors has not scaled similarly to the device dimensions since there are limitations regarding short-channel effects, which doesn’t allow to obtain the benefits presented in the ideal scaling. When having a constant scaling 훼, like shown in Figure 1 the physical dimensions of the device (gate length (L), gate width (W), oxide thickness (푡표푥) and junction depth (푋푗)) the supply voltage (푉퐷퐷) and the threshold voltage (푉푡) are all reduced by a factor of 훼. So, while the circuit 2 density increases by 훼 the depletion width (푊푑) decreases by the same factor which is possible by increasing the substrate doping by 훼. This results in a scaling down of the gate capacitance

(퐶푔 = 푊퐿휀표푥/푡표푥) and the drain saturation current (퐼퐷푠푎푡) by 훼. The intrinsic switching delay of the transistor is reduced by 훼 since 휏~퐶푔푉퐷퐷/퐼퐷푠푎푡 so the performance of the device increases. 2 At the same time the power dissipation 푃~퐼퐷푠푎푡푉퐷퐷 is reduced by 훼 so the power density remains the same (푃/(푊퐿)).

Figure 1 – Example of the device scaling by 휶. [19]

The main concerns in scaling for 28 nm CMOS technology according to [16] are the stress effects (induced by interface boundaries between materials with different dopant densities) which can be mitigated by the use of dummies and equally spaced devices. These stress effects can cause mobility variation, which influences the bandwidth, the current mismatch and the gain of the device; diffusion proximity which results from the dopant atoms scattered from adjacent photoresist that can cause a variation in Vt and the gate leakage which is due to quantum tunneling effect that can cause noise, mismatch and it can be a low frequency limiter. In order to improve the performance of the MOSFET we can apply enhancing of the carrier transport properties of silicon by strain-induced modification of the electronic band structure or use high-k gate dielectric and metal gate electrodes which have higher 퐶표푥. Since there are limitations in both scaling by constant voltage which results in an increase of the electric fields and scaling by constant electric field since the threshold voltage scaling has not followed the trend, new innovative solutions for the scaling of the transistors have been studied to ensure the reliability and performance of the devices.

2. Digital to Analog Converter: Definition and Characterization

The DAC is a system that reconstructs an analog waveform according to a digital word input. It acts like a sample and hold circuit throughout the signal reconstruction. During each clock cycle, the output, which is given according to the input word, is steady so the resulting signal is a series of modulated rectangular pulses. In order to achieve the performance specifications required in a DAC, there are a number of important parameters defined by [17] that need to be measured. Depending on the intended use of the DAC some of these parameters matter most for achieving the specifications. The difference to the ideal behavior is characterized by a number of performance metrics that characterize the DAC static and dynamic performance.

2.1 Performance Specifications

There are many different characterization parameters of the DAC, according to its use, that are useful in comparing the different architectures possible to use. So it is important to know the meaning of each one, so that we can analyze its performance according to the intended purpose of the DAC. Some of the more important parameters are:  Gain Error: The gain error is defined as the deviation of the slope of the transfer function actually observed compared with the ideal transfer function (theoretically specified).  Offset Error: The offset error is defined as the constant DC offset of the transfer function of the DAC, with respect to the ideal transfer function.  Quantization Error: Analog signals represented with a finite number of bits will have an error between the analog value and its digital representation. This error is the quantization error and limits the maximum achievable dynamic range of the converter.  Monotonicity: A converter is monotonic if the output increases progressively when applying a ramp at the converter input. Monotonicity is guaranteed if the deviation from a best-ﬁt straight line is less than half an LSB.  Differential Non-Linearity Error (DNL): The differential non-linearity error measures the worst case of deviation between the actual and the ideal step size on two adjacent codes. It is a measure of the degree to which the steps between the codes are uniform. A good DNL implies good resolution and a good noise performance since all the steps have almost the same size, as stated by [18].  Integral Non-Linearity Error (INL): The integral non-linearity error represents the deviation of the DAC's transfer function from the ideal. It is a measure of the degree to

which the line deviates from the ideal straight line through all the states. A good INL results in a good accuracy and low distortion of a digital waveform being converted.  Effective Number of Bits (ENOB): Defines the number of bits that an ideal converter would have under the same conditions of the converter considered and is given by: SNDR − 1.76 ENOB = bit (1) 6.02  Resolution: The resolution of a DAC has been defined by [19] as “The number of bits used to produce each analog output level. The higher is the number of bits, the smaller is the analog (voltage or current) output step that could be output level generated. An N- bit resolution implies producing 2N distinct analog levels”.

Figure 2 – Example of some metrics of the DAC.

 Settling Time: The settling time is defined as the time needed for the output to experience a full scale transition and to settle within a specified error band around its final value.  Slew Rate: The slew rate is the maximum rate at which the output of the DAC can change with the changing input and it is given by: 푑푉 SR = 표푢푡 (2) 푑푡  Spurious Free Dynamic Range (SFDR): SFDR is defined as the usable dynamic range of a DAC before spurious noise interferes and distorts the signal as represented in

Figure 3. It is the ratio between the power of the fundamental (푃푠) and the power of the

largest spur (푃푑푖푠푡표푟) from DC to the full Nyquist bandwidth (퐹푠/2): 푃 SFDR = 10 log ( 푠 ) dB (3) 푃푑푖푠푡표푟

Figure 3 – Output spectrum of the DAC with representation of the harmonics of the signal and the SFDR.

 Signal to Noise Ratio (SNR): SNR is defined as the ratio of the power of the fundamental signal to the integrated noise power. Where N the number of bits, the theoretical SNR is given by: SNR = 6.02 푁 + 1.76 dB (4)  Signal to Noise-plus-Distortion Ratio (SNDR): The definition of SNDR given by [18] is

the ratio of the power of the fundamental signal (푃푠) to the total noise (푃푛) and harmonic

power at the output (푃푖), when the input is a sinusoid.

푃푠 SNDR = 10 log ( ∞ ) dB (5) 푃푛 + ∑푖=2 푃푖  Total Harmonic Distortion (THD): The THD is defined as the ratio of the sum of the

power harmonic components (푃푖) to the power of the fundamental signal (푃푠). ∑∞ 푃 THD = 10 log ( 푖=2 푖) dB (6) 푃푠

2.2 DAC Architectures

The architecture used for a DAC depends on the performance parameters in which we have interest. The output value of the DAC can be formed using voltage, current, charge or time. Some DACs enable high resolution but require a large area while others may consume more power but are faster. So there are three main classes of DACs based on the type of output they provide: resistors (voltage), capacitors (charge) and current sources (current). Every one of them generates a certain quantity at the output according to the digital input code.

 Resistor string DAC

In this architecture 2N resistors, where N is the number of bits of the input digital code, are connected either between two reference voltages or one reference voltage and ground. The reference voltage is divided in 2N parts, corresponding each node of the resistor string to a portion. The input code controls the switches, passing the correct voltage to the output. In Figure 4 it is shown an example of this architecture with a resistor string DAC. Although it is a very simple architecture and guaranteed to be monotonic, according to [17], high resolution DACs, higher than 8 bit, occupy a large area of silicon and the delay through the switching network becomes a great limitation of the DAC speed of operation. Since the impedance of the resistor string is dependent on the position in the ladder and the time constant formed by the ladder impedance and the loading capacitor is dependent on the position and the signal value this architecture will show distortion at high frequency signals, as stated in [20]. In order to reduce this dependency, according to [21], the output impedance of the resistor string must be sufficiently high compared to the total resistance of the string. This architecture requires an amplifier/buffer as an output stage so it serves as a high impedance voltage amplifier/buffer.

Figure 4 –Example of the resistor string DAC architecture.

 Binary weighted resistor DAC

In the structure of this converter, as presented in [17], there are N binary weighted resistors, where each resistor in the string has a value proportional to the weight of the bit it represents. The output of this architecture is obtained from the sum of the different current contributions of the bits that are active. The architecture described for the binary weighted resistor has an example in Figure 5. The main advantage compared to the resistor string is that each bit has only one resistor and one switch but the difference in value of the resistors is very

wide for high resolution DACs. Not only there are large values for resistors but there is no guaranteed monotonicity and the output may be susceptible to glitches. In this converter, the output impedance must be very low, so the current distribution does not depend on the actual setting of the switches. In the case of this architecture the need of an output amplifier/buffer is related with the need of a low impedance current summing node for the current to voltage conversion by using a resistive feedback architecture.

Figure 5 – Example of the binary weighted resistor DAC architecture.

 R-2R resistor ladder DAC

This topology makes use of switches associated to voltage sources or current sources, as presented in Figure 6. It is similar to the binary weighted but the resistors only take two values, either R or 2R. Although compared with the previous solutions we have twice the number of resistors, this architecture can be implemented using only combinations of resistors R. These differences result in a smaller area and higher accuracy with low power consumption. The disadvantage of this topology is the fact that if the switch in the first vertical branch has 1% larger resistance, the current will split in 0.495 and 0.505 portions limiting the achievable resolution.

Figure 6 – R-2R resistor ladder DAC architecture.

In general, according to [21], the bandwidth of the buffer is a limitation to the overall bandwidth of the converter. Regarding the main applications, these types of converters are used in limited low-resolution and low-cost applications like offset correction.

 Capacitor DAC

In this architecture if all the capacitors have the same value, it needs a thermometer decoded input, using a thermometer decoder explained in Section 3.2. For an architecture similar to the resistor string DAC with a binary structure, it is possible an implementation with capacitors with different values. If a bit is active, the capacitor associated with the bit switches its charge from ground to the reference voltage, resulting the output voltage of the DAC as the sum of all the charges of the capacitors which have active bits as an input [17]. A simple example of this architecture is presented in Figure 7. The main limitation of this architecture is the mismatch between the capacitors, which result in non-linearity errors. The main differences of this architecture to the resistor scheme is that since there is no need for a constant current flow it is possible to achieve a good power efficiency and the jitter has a difference influence on the output. While for voltage and current domain the overall packet consists of the time period multiplied by the current or voltage amplitude which changes the signal, for charge the total magnitude of the packet remains the same even if the transfer charges has a little delay [20]. Examples of application of this architecture are DACs that are used in pipeline ADCs or SAR ADCs.

Figure 7 – Example of the capacitor DAC architecture.

 Current Steering DAC

This architecture provides a current, through the combination of the values of different current sources. This converter is built with active current sources in which the current cell can

not be turned on or off, instead they have to be steered, to the appropriate summing node(s) so the biasing required for these circuits is not disturbed. There are three possible implementations of the coding of the bits that control the switches of the current sources: the binary implementation, the unary implementation and the segmented implementation. The binary implementation and the unary implementation of the Current Steering DAC are represented in Figure 8 a) and Figure 8 b) respectively. The three implementations of the DAC will be further discussed in Section 3.1.

Figure 8 – Example of a Current Steering architecture with two types of implementation a) The Binary Implementation and b) The Unary Implementation.

The output of this architecture can be of two types: a single-ended output or a differential output. While the first type is mostly used for low frequency instrumentation and control applications, the differential output is nowadays the primary choice when the spectral purity and signal quality regarding noise and distortion is the main concern. When a switch is turned on it connects a fixed output impedance to the output node, whereas when it turns off its impedance becomes very large. So, the total output impedance is the combination of the parallel output impedances of the cells that are switched on. Since in a differential output the output signal is the difference of two single ended outputs with opposite polarity signals, the harmonic distortion due to even-order tends to be suppressed and the signal tends to be somewhat immune to disturbance and noise on common circuit nodes. The use of a differential output also allows the use of only a single ended output by using just one of the output nodes.

In Figure 9 a) is represented the topology of a single ended output and in Figure 9 b) a differential output. In general this architecture combines a small area with a high update rate.

Figure 9 - Types of Output: a) Single-Ended Output and b) Differential Output.

3. Current Steering Architecture

Through the analysis of the different architectures for implementing a DAC and taking into account the specifications to be pursued in this project, the architecture that is most suitable is the Current Steering. The resistor string architecture enables high resolution but at the cost of a large area and it has a limitation on speed because of the large capacitance input in the buffer. This buffer is a great inconvenient since it has a large power consumption and introduces distortion to the circuit. The capacitor architecture has been shown not to be a suitable solution for telecommunication systems, according to [17], because of its nonlinear behavior, resulting from the driver needed for the capacitors that can have a nonlinear behavior. Also as it happens for the resistor string, this circuit requires a buffer that has the same inconveniences explained before. The Current Steering has an output in current form, it has a lower cost in terms of area, is intrinsically faster and has a more linear behavior than the resistor and capacitor based architectures, although in general it has a large power consumption, it has proved to be the best solution for the wanted specifications.

3.1 Different Codification Schemes

There are three different types of codification schemes for the bits of the input code: the binary implementation, the unary implementation and the segmented implementation. These different implementations take advantage of different characteristics of the topology, since the segmentation of a DAC is a crucial parameter because there is a trade-off between the linearity, the area, the THD, the glitch energy and the segmentation level of the DAC. ▶ The Binary Implementation In this implementation the coding of the current sources is binary, every switch switches to the output a current twice as large as the one of the less significant bit before. In this way the input code can automatically control the switches with no need for additional decoding logic. This kind of implementation doesn’t always show a monotonic behavior and suffers from a large DNL and dynamic error. The current sources are all the same but are grouped and switched in groups of 2i current sources, where i is the number corresponding to the bit weight. ▶ The Unary Implementation The current sources in this implementation are thermometer coded, having every current source the same value. The input code is converted to a thermometer code which controls the switches of each current source independently. This architecture has the advantage of being monotonic because only one additional current source needs to be switched so that the output has an extra LSB. When compared with the binary implementation, it has good DNL error and small dynamic switching errors. Due to the coding and decoding needed it is a lot more complex and increases significantly the area and power consumption.

▶ The Segmented Implementation Another approach to the current steering architecture is adapting both of the implementations, the unary and the binary, and combine them to take advantage of the best aspects of both. Usually the least significant bits are implemented using the binary architecture and the most significant bits are implemented using the unary implementation. This results in better compromise between the power, area, complexity of the circuit and the parameters of analysis of the circuit.

Figure 10 – Current Steering Architecture with a segmented implementation.

Although INL is independent of the segmentation, the more binary bits used the higher the DNL is, so in general we should use the maximum number of thermometer decoded bits. The restriction in this analysis, as described in [22], is that the area of the circuit highly increases with the number of bits used in thermometer code.

3.2 Basic Blocks

It is essential to understand the different basic blocks that constitute the DAC with Current Steering architecture since each block has a specific function in the circuit and the design of each component is essential to guarantee the overall performance. Since there are three different types of codification schemes for the input bits that control the switches the basic blocks will vary according to the implementation chosen. Examples of the blocks of a segmented Current Steering DAC are represented in Figure 11. For example, for the segmented implementation, which is a combination of the other two implementations, the basic blocks of a Current Steering DAC are the Thermometer Decoder, Latency Equalizer, Latch and Driver Circuit, Biasing Circuit, Cascode Current Source and Current Source. This gives a general view of the basic blocks that may need to be dimensioned when designing the circuit. The basic principle of operation of the Segmented Current Steering is that the N input bit code is split in NLSB least significant bits and NMSB (N = NLSB + NMSB) most significant bits.

The NMSB bits are thermometer decoded and while the decoding occurs the NLSB bits are delayed in the Latency Equalizer. When the processing of all the bits is finished the current sources are commuted according to the bits by complementary switches synchronized by latches and drivers circuits.

Figure 11 – Basic Block Diagram for a Segmented Current Steering DAC.

 Thermometer Decoder

According to the type of implementation of the Current Steering architecture it must be needed the use of a thermometer decoder for the switching scheme. The thermometer decoder receives the input bits of the DAC and translates the input code and the thermometer code at its output. This component, as stated in [17], can be of three major types: ▶ Row and column decoder: Combines the two types of decoder, the row decoder and the column decoder, from the combination of both signals it determines if the switch associated with the current source is active or not. This type of architecture is very simple to implement but the switching scheme optimization is not very flexible. ▶ VHDL decoder: This decoder allows any switching scheme because it implements the row and column decoder in one single block in VHDL and the array for the current sources and the array for the switches and the drivers are different. The major drawback is that the update rate depends on the standard library cell available but it has a high level of automation. ▶ Custom made decoder: Using a custom made decoder allows the designer a high speed DAC since it exploits the optimal solution for the implementation. Although it requires a lot more effort in design, not only it results in high update rate but since the designer can verify the timing constraints at every point of the circuit it may improve its dynamic behavior.

 Latency Equalizer

In this implementation where the least significant bits of the input code are not thermometer decoded and directly control the switches of the current sources there is the need for a latency equalizer that guarantees the same overall delay on all the bits that go to the driver and switches. Since going through the decoder adds a delay to the most significant bits we have to guarantee that the current sources are active at the same time for all the bits, hence the need for a latency equalizer for the least significant bits.

 Latch and Driver

This block includes the drivers, the level shifters and latches. The driver provides the signals that control the switches associated with each current cell. It guarantees that both switch transistors of the current cell are never simultaneously off, preventing glitches at the output. The idea is to generate complementary waveforms that assure that when a transistor is turned off the other is turned on. Generating waveforms with non-symmetrical crossover assures this behavior on the switch transistors. An example of a topology of a driver used in the circuit presented in [21] is represented in Figure 12.

Figure 12 – Example of the topology of a driver. The level shifter has the function of converting the voltages of digital logic circuits, where the input bits are processed in the DAC, to the voltages of the analog circuits. As an example, the digital logic circuit can have a different supply voltage than the analog circuit, so we have to convert the voltages from one part of the circuit to the other. Some examples of the topology of the level shifter and of the latch associated with this level shifter are presented in Figure 13 a) and Figure 13 b). The latches associated with the level shifter assure the synchronization and shape of the signals to improve the dynamic performance of the circuit. These latches are inserted between the level shifter and the driver, the first latch is active at high level and captures the output of the level shifter when the clock signal is “high”, and the other latch is active at low level and provides its output to the driver when the clock signal is “low”. To ensure the correct operation at the moment of capture all outputs of the digital decoder must be established.

Figure 13 – Example of the topology of a) level shifter and b) latch.

 Current Source

The block of the Current Source Array includes all the current sources that are activated by the driver and latch circuit according to the bits of the input code. The topology selected for the configuration of each current cell has to take into account random errors that can be minimized by the area of the transistor operating as current source and the effect of finite output impedance that can be mitigated by recurring to the cascode configuration. The simplest topology presented in Figure 14 a) consists of two MOS transistors (Msw) operating as switches in saturation steering the current from one transistor to the other according to complementary gate signals and a single MOS transistor (Mcs) operating in saturation with constant gate-source voltage. To ensure higher output impedance we can use a cascode current cell, as used in many literature examples like [22], which has a second MOS transistor (Mcas). This circuit, presented in Figure 14 b), seen by Vout has the output resistance of a double cascode and it is not such a limitation for the SFDR.

Figure 14 – Example of the topology of a current cell a) single and b) cascode.

 Biasing Circuit

The correct functioning of the Current Source Circuit is dependent on the Biasing Circuit which defines the gate voltages for the cascode and current source transistors. The Biasing Circuit usually consists on a set of current mirrors. The design of these current mirrors depends on important aspects like the supply voltage, process and temperature, output resistance and matching. For the current mirror represented in Figure 15 the transistors have to operate in saturation to guarantee 퐼표푢푡 as a stable current. The expression for the drain current for both

푀푁1 and 푀푁2 transistors in saturation, neglecting channel length modulation, is given by:

1 푊 2 IRef = 퐼퐷1 ≈ 휇푛퐶표푥 ( ) (푉퐺푆 − 푉푡) (7) 2 퐿 푀푁1

1 푊 2 (8) Iout = 퐼퐷2 ≈ 휇푛퐶표푥 ( ) (푉퐺푆 − 푉푡) 2 퐿 푀푁2

Since these two identical transistors have equal 푉퐺푆, if they operate in saturation and 푊 푊 have ( ) = ( ) , they carry equal current since from (7) and (8) we can conclude that: 퐿 푀푁1 퐿 푀푁2 푊 ( ) 퐿 I = 푀푁2 I (9) out 푊 REF ( ) 퐿 푀푁1

Figure 15 – Schematic of a basic current mirror.

So this circuit allows a precise copying of the reference current independently of the process and temperature, since we can control the ratio between the current by adjusting the ratio of their dimensions. Usually in current mirrors the same length (L) is used in all transistors so the errors due to side diffusion of the source and drain areas can be neglected. Also, as stated in [15], in short channel devices the threshold voltage shows dependency on the channel length, so the ratio between the currents is defined only by the width of the transistors. This analysis was based on the fact that the channel length modulation (휆) can be neglected but in reality and especially for minimum length transistors, this effect has significant impact on the currents copied. Considering this effect the previous relations for the current drain of the transistors 푀푁1and 푀푁2 result:

1 푊 2 I퐷1 = 휇푛퐶표푥 ( ) (푉퐺푆 − 푉푇퐻) (1 + 휆푉퐷푆푀푁1) (10) 2 퐿 푀푁1

1 푊 2 (11) I퐷2 = 휇푛퐶표푥 ( ) (푉퐺푆 − 푉푇퐻) (1 + 휆푉퐷푆푀푁2) 2 퐿 푀푁2 푊 ( ) (1 + 휆푉 ) (12) 퐿 퐷푆푀푁2 I = 푀푁2 I 퐷2 푊 D1 ( ) (1 + 휆푉퐷푆 ) 퐿 푀푁1 푀푁1

Although 푉퐷푆푀푁1 = 푉퐺푆푀푁1 = 푉퐺푆푀푁2due to the circuit associated at the drain node of

푀푁2, 푉퐷푆푀푁2 may not be equal to 푉퐺푆푀푁2so the current relation is not only dependent on the ratio between the dimensions of the transistors. So, to minimize the effect of the channel length modulation a topology, as the one represented in Figure 16, with a cascode transistor (푀푁3) in the current source may be used.

The transistor 푀푁3 allows the 푀푁2 transistor to be less sensitive due to the circuit that is connected to the 푀푁3 drain.

Figure 16 – Schematic of a cascode current mirror.

To ensure that 푉퐷푆푀푁1 ≈ 푉퐷푆푀푁2 in order to have a good current mirroring and since both sources are connected to ground, 푉퐷푀푁1 ≈ 푉퐷푀푁2, we need to ensure that the gate voltage of 푀푁3 is 푉푔 = 푉퐺푆푀푁3 + 푉퐷푆푀푁1.

3.3 Static/Dynamic Analysis

The design of a Current Steering DAC for high resolution or high update rates like the one presented in this project requires a thorough understanding of its static and dynamic behavior. The performance of the DAC due to its static behavior is related with the matching of the current source transistors. According to [5] there are two types of errors associated with this matching, the random errors due to process variations but also the systematic error due to various gradients. The dynamic behavior of the DAC has a main constraint due to the fact that for high speed, the second and third harmonic distortion, in the frequency domain, are a limitation for the spurious free output signal bandwidth. It is crucial to understand this constraints and how to reduce their effect on the performance of the DAC so we can achieve better results.

3.3.1 Static Behavior

The static performance of a DAC, as stated in [5] is intrinsically related with the mismatch of the current source transistors in this architecture. The mismatch can be defined as

the variation in physical quantities of identically designed devices. The matching errors consist of both random and systematic errors which have to be considered. The systematic mismatch comes from for example gradients in process parameters, like oxide thickness, doping or temperature. They can be overcome by using appropriate switching schemes, calibration or randomization. The random errors are due to random variations during the fabrication process of different DACs, in the same process technology, resulting in a different INL performance. Although the variation may be due to random errors it is essential to predict it within certain boundaries. The static matching of the current sources sets a lower limit to the INL that is possible to achieve and to the distortion performance of the DAC. According to [23] the current mismatch has four major physical effects: edge effects, implantation and surface-state charges, oxide effects and mobility effects. The yield figure associated with the INL on DACs defines the percentage of functional DACs that have a smaller performance than the specification of half an LSB. Taking into account the research on [10] there are different approaches that can be used to calculate this yield: ▶ The Lakshmikumar Approach: It gives us a formula to estimate the yield that is based on the assumption that there is no correlation between the outputs of the DAC, however it has been considered too optimistic since it only takes into account two outputs and ignores the rest. ▶ The Monte Carlo Approach: It calculates the output current of the DAC for every digital input code, taking into account that every current source has a random value derived from a Gaussian distribution, and calculates the yield by the ratio of the number of functional DACs and the total number of try-outs. ▶ The New INL_Yield Formula: The idea is that if an INL error occurs when passing through all the possible codes generated by the 2N-1 digital input words that there is a 50% chance that the error still exists for the code 2N. It doesn’t require the computation time of the Monte Carlo approach since it is the application of a formula. In general, although it requires more time of computation, the Monte Carlo approach is more used when making an estimation of the yield since it provides more accurate results than the formulas available. For a MOS transistor in strong inversion the relative standard variation of the drain current is given by:

2 2 2 ∆퐼 퐴훽 퐴푉 푔푚 휎2 ( 퐷) = + 푡 . ( ) (13) 퐼퐷 푊퐿 푊퐿 퐼퐷 In the long-channel approximation and according to [5] by the Pelgrom Model presented in [23] it is given by: ∆퐼 퐴2 퐴2 4 2 퐷 훽 푉푡 (14) 휎 ( ) = + . 2 퐼퐷 푊퐿 푊퐿 (푉퐺푆 − 푉푡)

where 퐴훽 and 퐴푉푡 are constant parameters dependent of the technology matching, WL is the area of the matched transistors and (푉퐺푆 − 푉푡) is the gate overdrive voltage. The mismatch of the transistors can be predicted by this model according to [15] and by analysis of the expression it is possible to conclude that the mismatch error is mainly influenced by the area of the transistor (WL) and that we should have high gate-source overdrive voltage to minimize threshold voltage mismatch. Since the area necessary for the current sources determines the parasitic capacitances it will impact the dynamic performance of the DAC even when employing cascode transistors. For smaller transistor dimensions in modern CMOS technologies, according to [21], the matching behavior will be affected by other effects related with the accuracy of the photolithographic process and influence of pocket implants. Regarding the systematic errors the main contributors according to [17] are: ▶ Transistor Mismatch Effect: Due to the fact that the mismatch behavior of a transistor is dependent of its surroundings it can have a negative effect on the static performance of the DAC. To overcome this effect it should be used dummy transistors around the current sources to ensure identical surroundings. ▶ Voltage Drop in the Ground Line: The fact that there is a voltage drop along the ground line will result in non-linearity errors because it will change the output current of different transistors on the same row. This effect on NMOS current sources can be minimized by either using appropriate switching schemes or by using wide power supply lines. ▶ Process and Temperature Gradients: Increasing one bit in the resolution of the DAC can double the area occupied by the unity current source and doubles the number of current sources in the current source array. So increasing four times the area of the current source array for every extra bit results in an area so large that gradients have to be considered. These temperature and process gradients cause non-linearity errors that by using special switching schemes can be compensated. When the random errors are the main contributor for the matching precision by estimating the yield it is possible to understand the minimal requirement and through adjustment of the active area keep the INL under one LSB. So, it is essential to compensate the systematic errors in order to keep the random errors dominant, which can happen by using appropriated switching schemes for the current sources. These switching schemes are layout techniques that make the different interconnection between the decoder and the switches of the current sources in order to have optimal process and temperature gradients for the arrays. The use of DEM (Dynamic Element Matching) techniques increases the static linearity beyond the limits imposed by random mismatch. According to [21] when using thermometer decoded arrays the elements to use for a given input code are not unique. Since, in principle, the members of the array are not distinguishable, an input code can be represented by different combinations of these elements. It takes advantage of this redundancy of the code representation to guarantee that errors from individual elements are averaged out over time. This averaging perception results in an increase in the static accuracy of the DAC. Instead of directly addressing the DAC elements, it shuffles the data vector and the elements chosen are

different according to this shuffling for each sampling interval. An example of these techniques is the DWA (Data Weighted Averaging) which is a rotation algorithm that cycle through all the elements at the maximum rate. The first element to be switched on in the current sampling period is the first element to be switched off in the previous cycle. Current Source calibration is another technique that tries to minimize the mismatch before the elements are used. It can be done once after fabrication or continuously in the background. All the elements are measured and their output is trimmed to the desired value. Each of the current sources is compared with a constant reference and the difference between the output current of the element and the reference current is minimized by changing the value of the element. All of these techniques have an advantage for systems where the accuracy of the DAC is the main concern.

3.3.2 Dynamic Behavior

Since most applications, emphasizing the telecommunications applications, are mainly in the frequency domain, both the dynamic and static performance are important because their non-linearity errors reflect as noise and distortion in the frequency domain. The major contributors for the dynamic performance of the DAC are according to [17]: timing errors, capacitive feedthrough from the digital control signals to the output node, voltage stability of the drain node of the current source transistors and dependency of the output impedance. ▶ Timing Errors: An example of the timing errors that can have an effect on the performance is the synchronization of the control signals of the switches of the current sources. If they are not exactly matched it may result in a glitch error in the output of the DAC. The solution is to use synchronization blocks immediately before the input of the switch transistors, so that any delay can be compensated. ▶ Capacitive Feedthrough: The switch transistors of the current sources form a feedthrough path, because of their gate-drain capacitance, between the digital control signals and the output. Using a low voltage swing at the input of the switches or by cascoding the switch transistors the glitch error originated can be minimized. The first solution is easier to implement since it can use the synchronization circuit used for timing errors. On the other hand, the cascode can increase the area and can result in distortion because it interferes with the symmetrical operating principle of the current cell. ▶ Voltage Swing: If there is a time interval where both switch transistors are conducting it will result in a glitch at the output. So it is necessary to have a switch driver that can assure a non-symmetrical crossover of the control signals at the input of the switch transistors. This block can be associated with the synchronization circuit referred for timing errors. However, for fast switching, the static current of the driver circuit can become quite large and be susceptible to variations of the supply voltage and temperature.

▶ Output Impedance: The output impedance becomes a major factor for the dynamic performance when we are designing a high resolution DAC since we design the current cells to have large output impedance so that the INL is very low. Although the cascode of the current source transistors result in a good INL specification it is only true over a limited frequency bandwidth, because it has a pole and a zero at finite frequencies. Changing the location of this pole and zero is not trivial because they are dependent on the gate length L which is dictated by matching considerations. A solution for this problem is changing the frequency dependency of the output impedance by placing an extra cascode transistor on top of either the switch transistors or the current sources transistors resulting in a different frequency behavior and increasing the DC value.

4. Design Methodology of the DAC

In the previous chapters not only the essential parameters when designing a DAC were defined, but also the different architectures and especially the Current Steering Architecture was further analyzed. In this chapter we go step by step through the designing methodology of a DAC with Current Steering Architecture applying the restrictions and specifications of the DAC required in this project.

4.1 Level of Segmentation

The first issue to be addressed when designing the DAC is the level of segmentation. According to the different segmentation schemes referred in Section 3.1 there are three different types of codification: the unary, the binary and the segmented. To define the level of segmentation, we can apply different approaches but for this specific project we used the Monte Carlo Approach with simulations for different levels of segmentation and analysis of the results. According to those conclusions the level of segmentation for this specific DAC is defined. Using this approach each of the 2푁 − 1 current sources has a random value derived from its Gaussian distribution with mean value I and standard deviation σ(I). For each digital input code, the output current of the DAC is calculated and compared to its ideal value. If the difference is larger than one LSB the DAC is considered not functional and is rejected. For each value of σ(I) we repeat this procedure a great number of times (>10000 times) to obtain reliable results. We can obtain the INL_yield dividing the number of functional DACs, which achieve a difference lower than one LSB and the total number of tries. In general, the resolution of the DAC is determined by the mismatch of the current sources while the update rate is determined by the switch transistors. The dependency of the DNL error is related with the segmentation level so that in the unary implementation each transition has the same probability of determining the DNL error, while in the binary implementation each transition has different probability that has to be simulated. So, the DNL error strongly increases with the number of bits in binary implementation, compared with the unary implementation. Even though the INL is independent of the number of LSB bits in binary codification (NLSB), an increase of these bits results in an increase of the DNL, which as seen in [22] results in an increase of THD and glitch energy. The first step in determining the level of segmentation was to make a high level model of the DAC. This model consisted in a program developed in Matlab that computes the INL/DNL of the DAC for each input code having as input variables: the level of segmentation (NLSB - number of bits in binary coding and NMSB – number of bits in thermometer coding), the standard deviation of the LSB current source (σLSB(I)/I), the sampling frequency (Fs), the input frequency

(Fi) and the input signal. To measure the INL/DNL the input signal is a ramp that starts in code 0 and ends in code (2푁 − 1) where N is the total number of bits of the DAC. From this computation we could

either obtain the INL_yield/DNL_yield according to the input code for one given value of

σLSB(I)/I or the INL_yield/DNL_yield according to a given value of σLSB(I)/I for a range of

σLSB(I)/I values. In order to guarantee that the INL/DNL model developed is according to the real circuit the results obtained were compared with the results presented in Figure 4.1 in [17] for a DAC with 10 bit resolution for a range of σLSB(I)/I from 0 to 0.4. For a segmentation of 3 bits in binary codification and 7 bits in unary codification and for an output current not considering the output impedance of the DAC the results obtained using this model in comparison with the ones presented in [17] are represented in Figure 17. For considerations regarding the level of segmentation of the DAC in this project the INL/DNL was computed using the output voltage considering the output impedance of the DAC for more accurate results. This output voltage can be computed considering either a single ended output or a differential output.

Figure 17 – Comparison between the INL_yield obtained by [17] through Monte Carlo simulations and the INL_yield obtained through the High Level Model of the DAC developed in this project.

The dynamic performance of the DAC was also considered in the model through the spectral analysis of the SFDR, SNDR, SNR, THD and ENOB. After computing the output voltage of the DAC, the FFT (Fast Fourier Transform) of the signal was computed and plotted considering only the Nyquist band (퐹푠/2) and all the dynamic metrics referred were computed. Finally, this model also considers one more parameter which is the effect of jitter in the output signal of the DAC. For a given maximum value of jitter considered, the output signal of the DAC is computed and the FFT of the signal is generated making the same type of analysis. Since in this project we pretended to develop a DAC with sampling frequency of 3.52

GHz and a bandwidth of 1.76 GHz, an input signal with Fi = 1.76 GHz and a sampling frequency of Fs = 3.52 GHz were considered in the analysis. To determine the level of segmentation of the

DAC the INL/DNL was calculated for segmented implementation with 6 bits in unary implementation and 1 bit in binary implementation and for a thermometer implementation with 7 bits in unary codification for either a single ended or a differential output. The results of these simulations considering different σLSB(I)/I are presented in Figure 64, Figure 65, Figure 66 and Figure 67 (see Attachments). The values obtained in this analysis are represented in Table 23 (see Attachments) and regarding the dynamic specifications of the DAC without considering jitter for a segmented implementation with 6 bits in unary implementation and 1 bit in binary implementation and for a codification with 7 bits thermometer decoded for a differential output the results are represented in Table 24 (see Attachments). Regarding the dynamic specifications of the DAC considering jitter the results are presented in Table 25 (see Attachments). Since an extra bit in unary codification doubles the area occupied by the latches and increases the complexity of the layout and since by comparison of the dynamic metrics and of the INL/DNL the differences between the two segmentations are not relevant to consider the use of 7 bits in unary implementation, a segmentation with 6 bits in unary codification and 1 bit in binary codification was chosen for the DAC.

4.2 Current Source Design

The simplest design of the current cell is a single MOS transistor biased with constant gate to source voltage that operates in saturation region. The switching consists in two MOS transistors operating as switches with complementary gate signals. The design of this current cell requires a minimum area for the transistor of the current source, so the random errors are small and their impact on the relative standard deviation can be neglected. The area of the transistor can be obtained taking into account the formula (13) obtained from the Pelgrom Model. Defining the value required for the yield, we derive the precision for the current cell 휎 ( 푖퐿푆퐵) and obtain the minimum area: 푖퐿푆퐵 4퐴2 휎 2 1 2 푉푡 푖퐿푆퐵 (푊퐿)푚푖푛 = (퐴훽 + 2) / ( ) (15) 2 (푉퐺푆 − 푉푡) 푖퐿푆퐵 퐼 1 푊 푖 = 퐹푆 = 휇 퐶 (푉 − 푉 )2 (16) 퐿푆퐵 2푁 2 0 표푥 퐿 퐺푆 푡 From these expressions we conclude that the only degree of freedom is the gate overdrive voltage given by:

푉푂푉 = 푉퐺푆 − 푉푡 (17) Increasing the gate overdrive voltage results in a decreased of the minimum area required. So in order to define this voltage we can choose it so that the current source minimizes the systematic errors. For large values of area, the mismatch is mainly determined by 퐴훽. These systematic errors, stated in [17], are mainly caused by the layout and can be optimized by the switching scheme and a careful layout generation but the finite output

impedance is a major effect. To minimize this effect we can use a topology with cascode configuration. The simple single current source topology with NMOS is presented in Figure 18 and based on that topology we can analyze the output impedance of the circuit. The small signal output impedance for the current source and the switch is given by:

푅표푢푡 ≈ 푔푚푆푊 ∙ 푟푑푠푆푊 ∙ 푟푑푠퐶푆 (18) where 푔푚푆푊 is the transconductance of the switch transistor, 푟푑푠 is the drain to source resistance of the switch transistor (푟푑푠푆푊 ) and of the current source transistor (푟푑푠퐶푆) as presented in [24].

Figure 18 – Topology of the basic current cell.

In general the output impedance of one single transistor is not high enough to meet the required static output impedance requirements and the large area defined by the matching requirements results in a very large parasitic capacitance that deteriorates the high frequency linearity. Using the cascode topology, presented in Figure 19, as stated in [5] increases the output impedance in both DC and high frequencies. For the cascode topology the output impedance is given by:

푅표푢푡 ≈ 푔푚푆푊 ∙ 푔푚퐶퐴푆 ∙ 푟푑푠푆푊 ∙ 푟푑푠퐶푆 ∙ 푟푑푠퐶퐴푆 (19) where 푔푚퐶퐴푆 is the transconductance of the cascode transistor and 푟푑푠퐶퐴푆 is the drain to source resistance of the cascode transistor. The transconductance and the drain to source resistance in general are given by:

2퐼퐷 푊 푔푚 = = √2퐼퐷퐾 ( ) (20) 푉푂푉 퐿

1 2퐿√푉퐷푆 − 푉푂푉 + ∅0 푟푑푠 = = (21) 휆퐼푠푎푡 퐾푑푠퐼푠푎푡 where K is the number of LSB sources in parallel, 퐼퐷 is the drain current, 퐾푑푠 is a constant of the technology, 퐼푠푎푡 is the drain to source saturation current, 휆 is the channel length modulation parameter and ∅0 is also a technology constant, the built-in junction potential presented in [24]. Since the topology of the circuit is the same for all current sources only the sizes of their

transistors need to be scaled from the basic current cell, which usually is the LSB current source, according to their weight. While the DAC static and dynamic performance is mainly determined by the performance of the basic current source cell, the design of the other components of the DAC is mainly determined by the speed requirements.

Figure 19 – Topology of the current source cell with a cascode transistor.

The output impedance of the DAC is a design constraint of the circuit because the finite output impedance of the DAC is a cause for distortion. According to [25] the output impedance of the DAC is modulated by the input signal since the output resistance of the DAC is dependent on the number of cells connected to the output. It means that since the output impedance is dependent on the input code then the output current of the DAC is also code dependent. So this modulation generates both static (INL) and dynamic errors. The output current is converted to a voltage through a combination of a linear load resistor and the DAC output resistance, which results in distortion. The INL of the converter is affected by this impedance by: 푅 푁2 퐼푁퐿 ≈ 푙표푎푑 (22) 4 푅표푢푡 where Rload is the linear load resistance, N is the number of current cells connected to the output and Rout is the output resistance of a current cell as presented in [5]. Although in most cases we can achieve the INL specification, it is only true over a limited frequency bandwidth since the output impedance of the cell is given by: 푗휔퐶 1 + 0 푔 푚푆푊 (23) 푅표푢푡 = 푟0푆푊 (1 + 푔푚푆푊 (푟0퐶푆//퐶0)) = 푟0푆푊 (1 + 푔푚푆푊 푟0퐶푆) [ ] 1 + 푗휔퐶0푟0퐶푆

where as we see in Figure 20 a), 푟0푆푊 is the output impedance of the switch transistor, 푔푚푆푊 is the transconductance of the switch transistor and 푟0퐶푆 is the output impedance of the current source transistor. From this expression we can conclude that the pole and the zero, illustrated in Figure 20 b), are at:

1 pole = (24) 2휋퐶0푟0퐶푆

푔푚 푧ero = 푆푊 (25) 2휋퐶0 The pole can be shifted to higher frequencies by minimizing the output impedance of the current source transistor (푟0퐶푆), but this resistance depends on the length of the gate which is determined by the matching considerations and the current 퐼퐷푆 determined by the full scale output signal. For this reason for high resolution designs and designs with a large capacitance 퐶0, as presented in [25], the output signal bandwidth is severely limited by the non- linearity introduced by the output impedance.

Figure 20 – a) Schematic of the basic current cell, b) Output impedance seen from the drain of the switch transistor over frequency.

Even though most of the times when using the cascode topology, presented in Figure 21 a), we can meet the requirements for INL the frequency bandwidth is still limited. According to [21] for the cascode topology the required linear SFDR is given by:

1 푟0퐶퐴푆푔푚푆푊푟0푆푊 SFDRreq ≈ ≈ 4 (26) 퐻퐷3 푍푙표푎푑푁

From (26) we see that the harmonic distortion (퐻퐷3) decreases when the channel length of the cascode and switch increases or when the overdrive voltage of the switch decreases. The bandwidth of the SFDRreq is the transition between zone 3 and zone 4 shown in Figure 21 b) given by: 1 BW = (27) 2휋푟푂퐶퐴푆 퐶1 The maximum bandwidth is achieved by using large gate overdrive on the switch transistors and minimum length on the switch and cascode transistors. All these main constraints need to be taken into account in the design of the circuit in order to guarantee the requirements for the DAC. Also all the specifications regarding the static and dynamic behavior of the circuit, discussed in Section 3.3, need to be considered.

Figure 21 – a) Schematic of the basic current cell with cascode topology, b) Output impedance of the cell over frequency.

According to [21] in a fully differential architecture only the even harmonics will be suppressed, while the odd harmonics will not be canceled in the output signal. So the main contribution for the limitation on the SFDR of the DAC will be given by the third harmonic.

For |Zout| ≫ N|Zload| the third harmonic distortion (HD3) is given by: N2A 2 Z 2 N2A 2 Z 2 sin load sin load (28) HD3 ≈ ∙ | 2| ≈ ∙ | 2 | 2 (2Zout + NZload) 16 Zout where Asin is the normalized amplitude of the sine wave processed by the DAC, Zload is the load impedance, N is the number of current sources of the DAC, Zout is the output impedance of the unit current source. The third harmonic distortion (HD3) is related with the SFDR by:

SFDR ≈ −20 log10 HD3 (dB) (29) In the case of the DAC in this project we have:

Zload = 50Ω

Asin = 1 N = 2Nbit = 128 SFDR > 35 dB which results in an output impedance for the unit current source of:

Zout > 12 kΩ

To assure a voltage swing in the output of Vswing = 0.45 V the full scale current (IFS) of the DAC is:

Vswing 0.45 IFS = = = 9 mA (30) Zload 50 The current of the LSB current source is given by:

IFS Iout = ≈ 70.87μA (31) LSB 2Nbit − 1 The current of each MSB current source for a segmentation of 1LSB/6MSB is given by:

IoutMSB = 2IoutLSB ≈ 141.73μA (32)

To make the dimensioning of the transistors of the current source the following procedure was used: 1. Determine initial values for the W and L of the current source transistor using the equations (13) and (14), the values of the NMOS and PMOS parameters for the 28nm ( ) technology, the maximum value of σLSB I obtained from the high level model and the drain I current to assure the desired voltage swing. The cascode transistor and the switch transistor are dimensioned using equation (14) and obtaining the W/L relation. Consider the minimum L for both transistors. The values of the NMOS and PMOS parameters for the 28nm technology used are:

Aβ = 1.2 %μm

AVt,n = 2 mVμm

AVt,p = 2 mVμm 2. Simulate the circuit in order to verify the state of the transistors (all transistors of the current source must be in saturation region); 3. Make the necessary adjustments on the W and L to guarantee the correct state of the transistors in all corners. 4. Measure the output impedance of the current source to guarantee the minimum output impedance in all corners. Using this process the dimensions of the transistors in the LSB current source obtained are shown in Table 2.

Table 2 – Dimension of the transistors in the Current Source.

Transistor W [흁풎] L [흁풎]

푀푐푠 < 1: 8 > 2 ∗ 1.9 0.5

푀 2 ∗ 0.9 0.04 푐푎푠 푀푠푤 2 ∗ 0.9 0.03

The resulting current and output impedance obtained in the current source after the dimensioning is presented in Table 3 considering simulation in corners. The corners considered in all simulations of the circuit are described in Table 37 (see Attachments).

Table 3 - Output Current and Output Impedance of the Current Source after dimensioning.

퐈퐨퐮퐭퐌퐒퐁 = ퟐ퐈퐨퐮퐭퐋퐒퐁 풁풐풖풕 (풌훀) Circuit Worst Best Worst Best Typical Typical Corner Corner Corner Corner Current Source 136 155 169 15.4 45.2 100

4.3 Biasing Circuit Design

The correct design of the Biasing Circuit is essential to the correct functioning of the DAC. This block directly feeds the transistors of the current source. The main concern when dimensioning the current source reference is to guarantee that it is independent of the power supply and of the temperature so the resulting current that is mirrored is as stable as possible. The mirroring circuit for the current source and cascode transistors consists on a cascode current mirror. The architecture chosen for this type of current mirror is shown in Figure

22. The reference current IRef2 defines the voltage VCAS which is the gate voltage of the cascode transistor of the current source cell while the reference current IRef1 defines the voltage VCS which is the gate voltage of the current source transistor. The two cascode mirrors are formed by transistors MCS2, MCAS2 and MCS3, MCAS3. The transistors MCS2 and MCS3 are multiple of the

MCS and the transistors MCAS2 and MCAS3 are multiple of the MCAS.

Biasing Circuit Current Source

Figure 22 – Example of the current mirror of the Biasing Circuit for the Current Source Array.

To generate the reference currents IRef1 and IRef2 the reference generator circuit used is shown in Figure 23. This circuit consists on a set of current mirrors. The current reference Iref is generated in the resistor RRef. The Operational Amplifier (OpAmp) bias the gate of the transistor

MP1 in order to guarantee that the voltage in RRef is equal to VRef which is the voltage reference of the OpAmp. The resistor RRef is chosen so the current IRef has the desired value. The use of the transistor MP2 as a cascode makes this current reference much more stable, so in order to bias MP2 (Vcasc) the circuit with transistors MP3, MN1, MP4 and MN2 is used. The cascode current mirror with transistors MP5, MP6 and MN3 defines the gate voltage (Vgcas) for the cascode transistors MN4, MN7 and MN9, while the cascode current mirror with transistors MP7, MP8, MN6,

MN4 and MN5 defines the gate voltage (Vgsrc) of transistors MN6 and MN9. The branch with

transistors MN6 and MN7 defines the current IRef2, while the one with transistors MN8 and MN9 defines the current IRef1.

Figure 23 – Example of the circuit for the Reference Current Generator.

The resulting reference currents IRef, IRef1 and IRef2 after the dimensioning of the circuit, considering corners, are presented in Table 4. All transistors in the biasing circuit were dimensioned to be in saturation and to have the higher ∆ (∆= VDS − VDSsat) possible to guarantee the best current mirroring possible. The dimensions of the transistors of the Reference Current Generator are presented in Table 26 (see Attachments).

Table 4 – Values of the current references 푰푹풆풇, 푰푹풆풇ퟏ and 푰푹풆풇ퟐ after dimensioning of the biasing circuit.

퐈퐑퐞퐟 (훍퐀) 퐈퐑퐞퐟ퟏ (훍퐀) 퐈퐑퐞퐟ퟐ (훍퐀) Circuit Worst Best Worst Best Worst Best Typical Typical Typical Corner Corner Corner Corner Corner Corner Current Reference 153 170 188 54.7 60.7 66.9 177 219 243 Generator

The OpAmp used in this circuit is a one stage differential amplifier represented in Figure

24, where 푀푃1 and 푀푃2 work as the second stage of the amplifier and 퐶푐 is a capacitor that enhances the Miller Effect and ensures that the OpAmp has a dominant pole. Usually this capacitor has the value of 20% of the impedance seen by the output of the OpAmp. The reference current of the OpAmp (Ibias) is mirrored to MON5 by the current mirror former by

MON6 and MON5. Since 푉푖푛− and 푉푖푛+ have the same value ensure by the biasing of 푀푃1, which generates a current that goes through RRef and results in a voltage equal to VRef, the mirrored current in MON5 is equally divided through MOP1 and MOP2 which are saturated. The dimensioning of the OpAmp has taken into account the 푉표푢푡 nedeed to correctly bias 푀푃1, a gain of about 40 dB to ensure a variation on the reference current lower than 10% and a phase margin higher than 45 degrees to ensure the stability of the circuit.

The results regarding the specifications obtained after dimensioning the circuit considering corners are presented in Table 5. The dimensions of the transistors of the OpAmp are presented in Table 27 (see Attachments).

Table 5 – Specifications of the OpAmp obtained after dimensioning.

Gain (dB) Phase Margin (º) 푽풐풖풕 (V) Circuit Worst Best Worst Best Worst Best Typical Typical Typical Corner Corner Corner Corner Corner Corner OpAmp 36.1 43 47.9 52.7 57.7 63.7 0.201 0.386 0.55

Figure 24 – Circuit of the one stage OpAmp and the second stage which is the current reference.

The voltage reference 푉푅푒푓 of the OpAmp is generated by a voltage reference generator based on the one presented in [26]. This voltage reference generator was chosen since it is very low power, works for low supply voltages from 0.9 V to 4 V and produces a voltage reference of about 670 mV. It works for the circuit since the voltage reference needed for the OpAmp was about 600 mV and the supply voltage of the circuit is 0.9 V. Through the use of this voltage reference generator it was avoided the use of another higher supply voltage to supply a circuit like a bandgap voltage reference to generate the reference voltage. The schematic of this voltage reference generator is represented on Figure 25. In this circuit the start-up circuit is used to ensure that the initial stable state is achieved, using transistors 푀1푆, 푀2푆 and 푀3푆. The main part of the circuit, the current generator, consists on four branches with transistors 푀1 through 푀8, that generate a current as independent as possible of the supply voltage, which is injected in transistors 푀9 and 푀10. The reference voltage at the output is independent of the temperature since this current becomes independent of the temperature because it is compensated by the temperature dependence of the 푉퐺푆푀10, when 푀10 is diode-connected.

All transistors in this circuit are LVT (lower 푉푡) operating in saturation except transistors

푀1 and 푀3, which are HVT transistors with a higher 푉푡, and operate in the subthreshold region.

This ensures that while 푀1 and 푀3 are in the subthreshold region, 푀2 and 푀4 are saturated.

Figure 25 – Circuit of the Voltage Reference Generator.

The resulting voltage reference (Vref) obtained using this circuit after dimensioning considering corners is presented on Table 6. The dimensions of the transistors of the Voltage Reference Generator are presented in Table 28 (see Attachments).

Table 6 – Voltage Reference obtained after dimensioning of the Voltage Reference Generator.

Vref (V) Circuit Worst Corner Typical Best Corner ∆= 퐕퐑퐞퐟퐁퐂 − 퐕퐑퐞퐟퐖퐂 Voltage Reference 0.558 0.621 0.687 0.129 Generator

Since the variations of 푉푖푛− and 푉푖푛+ of the OpAmp are not very limiting for the operation of the circuit, the difference of 129 mV of the reference voltage in the corners becomes acceptable.

The circuit for the current reference Ibias of the OpAmp is the one presented in Figure

26. The current is generated in the resistor (Rbias) and mirrored to 푀푃퐶2. This circuit presents some variation on the resulting current since the value of the resistor varies and the current is not independent on the supply voltage and temperature. But since the OpAmp is able to support the variations this circuit was chosen for its simplicity. The values of the biasing current after dimensioning are presented in Table 7. The dimensions of the transistors of the Current Reference Circuit of the OpAmp are presented in Table 29 (see Attachments).

Table 7 – Biasing Current for the OpAmp after dimensioning of the Current Reference Circuit of the OpAmp.

퐈퐛퐢퐚퐬 (훍퐀) Circuit Worst Corner Typical Best Corner Current Reference of 9.61 18 28.3 the OpAmp

Figure 26 – Schematic of the Current Reference of the OpAmp.

4.4 Latch and Driver Circuit Design

The dynamic performance of a current steering DAC according to [27] is greatly related with the degradation caused by the imperfect synchronization of the control signals at the switches. In order to minimize this effect a careful design of the driver is necessary. The latches are part of the driver circuit and assure the synchronization and shape of the control signals at the switches. The driver has the function of shifting the crossing point of the differential control signals of the switches to assure that they are never in the off state simultaneously and performs their final synchronization. In some simple circuits, the intrinsic delay between the two complementary outputs is used to lower the crossing point of the control signals of the switch transistors. For high speed circuits, this type of driver can limit the frequency operation because of the combination of the intrinsic delay and the feedthrough of the steep control signals. The circuit that drives the differential switch should ensure that both switches are never completely off at the same time so that the current from the current source is always flowing at a constant value. The solution is to use a type of driver that sets the crossing point of the control signals by using different rise and fall times for the driver’s differential output. An example of this type of driver used in [28] can be seen in Figure 27, where an extra PMOS is placed in parallel with each cross-coupled PMOS at the top of the circuit in order to obtain immediate charging of the output nodes with falling inputs. By doing this, the intrinsic

delay is removed from the operation of the circuit. We use NMOS pass-transistors in the input path in order to keep a single phase input clock and to deal with low power supply. This results in a rise time much faster than the fall time of the driver circuit, and a high crossing point of the differential output can be achieved directly at the output of the latch. A lower crossing point is achieved by scaling of the gate width of the PMOS or NMOS. The small inverters at the bottom of the circuit assure the stabilization of the synchronized inputs and suppress the clock feed through.

Figure 27 – Example of a driver with crossing point due to rise and fall time.

This driver was used in the project since it is fully functional for clock speeds higher than 1 GHz. Using this configuration the driver was dimensioned in order to guarantee that the rise and fall time of the control signals were lower than 25% of the clock signal to ensure that the control signal is fully established before the edge of the clock. The crossing point of the control signals was established to be lower than the 푉푡 of the switch transistors to guarantee that the switches are not simultaneously off. Taking into consideration a clock of 3.52 GHz the rise and fall time of the control signals can not be higher than 71 ps. The values for the rise and fall time of the driver were obtained and are shown in Table 8. The values of the crossing point are shown in Table 9. The dimensions of the transistors of the driver are presented in Table 30 (see Attachments).

Table 8 – Rise and Fall Times of the Driver Circuit.

Rise Time (퐩퐬) Fall Time (퐩퐬) Circuit Worst Best Worst Typical Typical Best Corner Corner Corner Corner Driver 26.2 17.9 15 65.2 40.9 33.7

Table 9 – Value of the Crossing Point of the Control Signals of the Switches.

Crossing Point (푽) Circuit Worst Best Typical Corner Corner Driver 0.391 0.334 0.267

During the development of the project it was noticed that the synchronization of the signals at the input of the driver was critical. Since there is a delay between the decoding of the bits and the data being available at the driver input there is a need to add a flip flop to hold the value of the data before the edge of the clock. So in order to assure that for all corners the data at the input of the driver was correct the circuit presented in Figure 28 was used.

Figure 28 – Flip Flop used in the Driver.

The value of Data_In is stored in the flip flop during the rising edge of CLK̅̅̅̅̅ and the value is hold until the next rising edge of CLK̅̅̅̅̅, since the Latch is activated by the signal CLK which has the rising edge on the falling edge of CLK̅̅̅̅̅ this guarantees that the signals IN_N and IN_P are kept constant until CLK has a rising edge. An example of the behavior of this circuit is presented in the diagram of Figure 29. The dimensions of the transistors of the flip flop are presented in Table 31 (see Attachments).

Figure 29 – Diagram of the behavior of the flip flop.

4.5 Decoder Architecture

After defining the level of segmentation of the DAC and when using either a segmented codification or a unary codification there is a need for a thermometer decoder. For designing this decoder and as stated in the Section 3.2 there are three types of decoders: the row and column decoder, the VHDL decoder and the custom made decoder. The design of the decoder described in [16] when using a row and column decoder may result in a larger accumulation of systematic and graded errors, since in a classical design a complete row of cells has to be turned on before switching the following row. When the number of bits increases the complexity of the design increases immensely and using a complete digital solution with VHDL becomes a much more expedite solution. The main disadvantage of this solution is the lost in update rate of the design since its performance is limited by the standard library cells used. The use of custom made decoder is useful when we intend the optimal solution in terms of high update rate for the design but it requires a lot of effort, when sometimes although the solution achieved by the other types of decoders is worst, it assures the defined limits and it compensates in time dispended with design. In the case of this project since we only have 7 bits and we need to use 6 bits in the thermometer decoder the row and column decoder seems to be the most adequate solution. A representation of the decoding scheme where each 3 bits of the 6 MSB are used to decode 7 rows or 7 columns of the matrix is represented in Figure 30. There are an additional row and column which are a combination of supply voltage and ground. The matrix has 63 local decoders each associated with a current source with the logic presented in Figure 31.

Figure 30 – Thermometer Row and Column Decoder Matrix Architecture.

Figure 31 – Local Decoder of the Thermometer Decoder Matrix.

The logic circuit of the row and column decoder is the same since we use the bits in sequence, for the row decoder the bits 퐵1, 퐵2 and 퐵3 and for the column decoder the bits 퐵4, 퐵5 and 퐵6, considering 퐵0 the LSB bit which is not thermometer decoded. The corresponding logic circuit was deducted from the truth table presented in Table 10 and the circuit is presented in Figure 32 while dimensions of the transistors after dimensioning are shown in Table 33 (see Attatchements).

Table 10 – Truth Table for the Row and Column Decoders of the Thermometer Decoder.

Binary Code Thermometer Code B3 B2 B1 T7 T6 T5 T4 T3 T2 T1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 1 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 1 0 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Using a Karnaugh’s map to deduct the Boolean equations that match the previous truth table and making simplifications to only use NAND, NOR and NOT gates the resulting equations are:

T1 = B̅̅1̅̅.̅퐵̅̅2̅.̅̅퐵̅3̅ (33)

T2 = ̅퐵̅̅2̅.̅퐵̅̅3̅ (34) ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ (35) T3 = (퐵3. (퐵1 + 퐵2))

T4 = 퐵̅̅3̅ (36) ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ (37) T5 = (B3 + (퐵1. 퐵2))

T6 = 퐵̅̅2̅̅+̅̅̅퐵̅̅3̅ (38)

T7 = B̅̅1̅̅+̅̅̅퐵̅̅2̅̅+̅̅̅̅퐵̅3̅ (39)

Figure 32 – Logic Circuits for each of the outputs of the Row and Column Decoder.

When doing the design of the logic circuits the restriction was to make sure that they are as fast as possible. Taking this into consideration the delay between the data coming out of the registers and being available for the latches is presented in Table 11, where WC is the worst corner, Typ the typical corner and BC the best corner, either in picoseconds (ps) or in percentage of the clock period time (%). To ensure that the data of all the bits is available for the latches at the same time a Latency Equalizer was used for the LSB bit, which consists on an inverters chain with four inverters. The dimensions of the transistors of the register are shown in Table 35 (see Attachments).

Table 11 – Decoding and Latency Time of the Thermometer Decoder and Latency Equalizer

Decoding Time Circuit WC(ps) WC(%) Typ (ps) Typ (%) BC (ps) BC (%) Thermometer 69 24.3 37.7 13.32 23.9 8.42 Decoder Latency Time WC(ps) WC(%) Typ (ps) Typ (%) BC (ps) BC (%) Latency 57.2 20.14 32.8 11.55 24.7 8.7 Equalizer

The resulting decoding scheme for the DAC is represented in Figure 33.

Figure 33 – Scheme of the Decoding Block of the DAC.

The topology of the registers used to ensure the synchronization of all the bits is represented in Figure 34. In this circuit the clock signal has a delay (CLK_late) ensured by the inverters in the clock driver to make sure that when applied to 푀푃푅1, 푀푁푅1, 푀푃푅4 and 푀푁푅4 all the data is transferred to the output before the new data comes in. The transistors 푀푃푅5, 푀푁푅5, 푀푃푅8 and 푀푁푅8 all let the data go to the second part of the circuit before the first part is activated by the clock. The data is stored in the register on the rising edge and it is available at the output on the falling edge of the clock.

Figure 34 – Schematic of the Register.

4.6 Clock Driver

The clock driver is used to drive the large capacitive loads of the on chip and off chip loads. It is used a buffer circuit which consists in a string of inverters between the bonding pad and the on chip circuit to reduce the delay between the two. This cascade of inverters is dimensioned taking into consideration the input load (퐶푖푛) and the output load (퐶푙표푎푑) that need to be driven. Each of the N inverters of this chain is larger than the previous by a factor of 훼 (the width of each inverter is multiply by a factor of 훼), resulting that each inverters input capacitance is larger than the previous inverter input capacitance by a factor of 훼 as presented in Figure 35. The factor 훼 and the number of inverters used are chosen so that: 1 (40) 퐶 푁 α = [ 푙표푎푑] 퐶푖푛

The loading ratio between the propagation delay of the direct drive (푡푑푖푟) of the capacitances and the use of the cascade of inverters (푡푐푎푠) is given by: 퐶 ln ( 푙표푎푑) (41) 푡 퐶 퐶 훼 r = 푐푎푠 = 훼푁 푖푛 = 푖푛 푡푑푖푟 퐶푙표푎푑 퐶푙표푎푑/퐶푖푛 ln 훼 From equation (41) we conclude that the ratio r has a local minimum for 훼 = е ≅ 2.718. According to [27] as long as 훼 is set between 2 and 4 the deviation from the minimum delay is less than 5%. To ensure that the load is correctly driven 퐶푙표푎푑 is usually considered greater than the real 퐶푙표푎푑. For small loading ratios the speed improvement and area overhead of the cascade may not be justified.

Figure 35 – Driver circuit using a cascade of inverters to drive a capacitive load.

Considering the design in this project the approximated values for 퐶푖푛 ≅ 0.003 푝퐹 and

퐶푙표푎푑 ≅ 0.3 푝퐹 measured in the circuit resulted in a number of stages for the string of inverters, considering ≅ е : 퐶 (41) 푁 = ln ( 푙표푎푑) = 4.6 퐶푖푛 Since N is an integer number the cascade of inverters was dimensioned using 5 inverters and 2 < 훼 < 4 in each of the stages of the inverter. The dimensioning of the inverters took into consideration the shape of the clock signal to ensure the steepest transitions.

4.7 Design Constraints

The design of the DAC has to take into consideration its main constraints since they affect the behavior of the circuit. They can be crucial when trying to meet the specifications and matching the requirements, so understanding how to reduce their effect or how to take advantage of them becomes essential. According to [25] the potential of the Current Steering DAC to achieve high speed operation is similar to the potential to exhibit non-linear behavior, so the knowledge of the main problems and their causes is crucial to achieve the higher performance possible. High frequency linearity is mostly dependent on the time domain errors like the output impedance modulation, switching behavior and timing inaccuracies.

4.7.1 Matching

The transistor mismatch in the current source can be a source of nonlinearity for the circuit, since a deviation from the ideal current cell behavior will result in a spectral impurity. In order to reduce its effect, a good matching with an area of the gate wide enough, short distances between transistors and an ensured similar environment through the use of dummies needs to be used. We can also apply other techniques such as calibration or dynamic element matching (DEM), considered in [4], but it has been shown that although it reduces the mismatch for lower frequencies, it can even degrade the performance for high frequencies. This mismatch error is mainly determined by the area of the current source transistor. To ensure that the mismatch of the threshold voltage is not dominant, the voltage overdrive of the current source has to be large. Since the area required for one current source determines de parasitic capacitance (퐶0) that can affect the high frequency performance, even with cascode topology, we have to ensure that even if the technology enforces a small overdrive voltage the area penalty due to matching requirements is not too high.

4.7.2 Output Impedance

The output of the DAC is given by the combination of the output impedance of its individual cells. Not only the output impedance has an impact on the resulting SFDR of the DAC but it is also modulated by the input signal. Considering that the output impedance of each individual cell is given by the combination of a resistor in parallel with a capacitor, the total output resistance of the DAC is a function of the input signal and the time constant of the output pulses is modulated by the input signal. This effect becomes stronger than the resistive since the DAC output has a stronger capacitive than resistive nature. For each additional cell that is switched on the time constant at the DAC output increases, so the transition between all cells turned off and one turned on has a lower time constant than the transition between 63 cells turned on and 1 turned off and 64 cells turned on. As the input signal varies, the normalized pulse shape at the output becomes less or more steep accordingly as explained by [25].

In conclusion the output impedance is a limitation due to amplitude losses caused by the modulated output impedance and the frequency dependency of the impedance. As stated in [20] and analyzed before, the output impedance causes the second harmonic distortion to be the main cause of errors, being this effect reduced by the use of a differential output rather than a single ended output.

4.7.3 Switching Errors

The switching of the MOS transistors shows problems related with their nonlinear V/I nature and the fact that the switch transistors share a common node which suffers from their interaction. The first problem according to [25] is related with the characteristic of the MOS transistor which presents a switching on and switching off asymmetrical behavior. While one switch transistor turns on it reaches a different operation region in a different time than the one that turns off, resulting that when both transistors are driven by complementary gate signals during a period of time both switches will not be conducting. The fact that both switches will not be conducting during a period of time results in a choking of the node that connects the switches and the cascode transistor, which discharges abruptly, creating current spikes as represented in Figure 36. As soon as one of the transistors is turned on it is forced to recharge this node instead of delivering the current to the output which prolongs the current spike until the capacitance associated with this node is charged. Each unit cell only contributes to this phenomenon if it is switching and in proportion of its weight, so for a thermometer implementation all the cells have the same contribution. This effect on the common node can cause extra problems related with the fact that if the voltage at the node drops significantly due to its discharge then due to the parasitic capacitances between drain and gate the gate voltages of the cascode and current source transistors can be affected and their operation region can change.

Figure 36 – Spike in the common node due to switching errors.

The glitch at the output due to the first problem only has contribution of the switching cells since the cells that remained on from the previous sample do not influence, being the total glitch the sum of the independent contributions and after this spike the pulse settles to its DC value. In a thermometer DAC the same pulse shape appears every time the cells are switching since all the cells have the same ratio of glitch to sample. In this case there will not be a nonlinear behavior because the normalized pulse will always be independent of the input signal. On the other hand for a binary DAC the individual pulse is dependent on the binary value of the input and a nonlinear relation between the pulse and the input code causes distortion. The fact that the voltage at the common node of the switches and cascode varies will be a source of nonlinearity for either a binary and thermometer implementation. The variation in the transient of the common node is propagated to the gate voltages of the source and cascode transistor through their parasitic gate drain capacitance and these voltages become correlated with the number of cells that are switching and their weight. The resulting current in each cell is then affected in the same way and the spike created by each of them is proportional to the number of switching cells. Since the gate voltages (VgCS and VgCAS ) are global parameters to all the cells and their transient is modulated by the switching, the response of all cells, independently if they are switching or not, suffers from this modulation. This error is not due to the individual contributions but rather generated by the interaction in a common node which affects a signal that is a parameter to all the cells. Even if we resort to decoupling capacitances and the use of many transistors it does not eliminate the problem completely. The second problem is also related with the interaction between the cells via a common node that is shared. While the previously analyzed problem is related with the dependency of the interaction that causes the spike to appear at the common node this problem relates to the fact that the switching branch that is turned on can not shield the common node between the cascode transistor and the switches and the output signal appears at the common node. For a variation in the output a variation in the transient signal at the common node will appear and all switch transistors once again will be affected in the same way by a function of the input signal. The problem does not only result from the interaction on the common node between the cascode transistor and the switches but also due to the fact that the output node (푉표푢푡) is shared as represented in Figure 37. This modulation will affect the dynamic behavior of the switching devices depending on the code value of the input signal.

Figure 37 – Output signal influence on the common node of the Current Source.

4.7.4 Timing Inaccuracies

A timing mismatch of the DAC elements occurs when some of the cells are updated with a slightly different timing compared to others and this difference can be a source of nonlinearity as stated in [21]. According to [25] timing inaccuracies in the cells nowadays are related with the clock signal distribution network, clocked units, drivers and switches. It is essential to ensure that the clock signal reaches many locations of the DAC simultaneously and with the correct shape because a difference in the clock arrival between two points or a clock signal with an incorrect pulse shape may cause functional errors in the DAC clocked elements. These inaccuracies can be the result of mismatch in the geometrical characteristics of the interconnecting wires, imperfect balancing of the distribution of the interconnecting wires, variations in the supply and ground, crosstalk between clock lines and switching lines or environmental spatial variations that affect the circuit. Some examples of errors that can result from these inaccuracies are differences between the control signals of the switches of different cells which will generate similar but skewed current pulses and variations in the crossing point of the control signals which results in spikes in the common node that vary from cell to cell. The conversion in data converters is triggered by a clock signal, the sampling clock. If there is any timing uncertainty affecting the sampling, it has an influence on the signal being synthesized. A timing error changes the moment in which the sample is taken from the signal, as represented in Figure 38. In the simplest analysis it is considered that the sample moments are define with infinite precision, when in practice these time moments have limited bandwidth so the rising edge has not an infinite slope.

Figure 38 – The ideal sampling moments (dashed line) and the actual sampling moments due to jitter.

The clock jitter is this timing uncertainty that causes the sample moments to shift slightly from their position and sample the signal in a different position. For data converters it is assumed that the jitter is a random process with rms value 휎푡푗. According to [21] the value of the SNR affected by the jitter is given by:

SNR푗푖푡푡푒푟 = −20 log10(2휋푓푖 휎푡푗) (26) This relation is valid for the ratio between the signal power and the noise in half of the sampling band as stated by [30]. For high frequency signals (푓푖) the content of the signal is much more affected by these timing errors than for low frequency signals which change slowly. If the cause of the jitter are noisy sources then the contribution for the signal will be noise, on the other hand if the cause are deterministic sources then it will result in tones or distortion. In the case of the converter some examples of causes of jitter can be: unequal propagation paths of clocks, interference from subdivided clocks and loading of clock lines.

4.8 Results and Conclusions

The complete dimensioning of the circuit took into consideration the correct dimensioning of each individual block and their constraints as explained throughout all the sections of Chapter 4. The procedure followed for each new dimensioned individual block was to add the blocks that had already been dimensioned and to consider them in the simulation. This procedure guaranteed that for all corners the results obtained for a certain block that depended on others was the most accurate. Whenever a new block was dimensioned all the other blocks, even if they were already dimensioned, that depended on it were simulated and their correct functioning for all corners was assured. After the dimensioning of all the blocks the complete circuit was simulated as a whole considering the variations in corners and the SFDR, SNDR, SNR, THD and 푉표푢푡 were measured. The 푉표푢푡 was measured directly from the differential output waveform obtained while the SFDR, SNDR, SNR and THD were computed through a Matlab program given the equally spaced points of the output waveform of the DAC. The values for these measures are presented in Table 12.

The input signal considered in the simulation was a codification of the 7 bits to obtain a sine wave at the output. The input signal has a frequency of 푓푖푛 = 1.73 퐺퐻푧 to assure that the fundamental tone was observable and that the sampling of the signal and the posterior analysis in the Matlab program was correct. The frequency spectrum is analyzed from 0 Hz to the Nyquist frequency, which is half of the sampling rate, in this case 1.76 퐺퐻푧 since the sampling rate is defined by input clock which is 푓푐푙표푐푘 = 3.52 퐺퐻푧. Using 푓푖푛 = 1.73 퐺퐻푧 has a frequency close to 푓푐푙표푐푘/2 = 1.76 퐺퐻푧 assures that the spectrum is correctly analyzed. In Figure 39 is represented for the typical corner the input signal corresponding to the 7 different bits (blue waveforms), the clock (red waveform) and the corresponding differential output signal (black waveform) obtained.

Figure 39 - Waveforms of the Input Bits, the Clock and the Output Differential Signal for the Complete Schematic Circuit.

The differential output of the DAC (푉표푢푡) varies for the typical corner between 0.53 V and

-0.53 V. Since the maximum voltage output of the DAC corresponds to 푉푠푤푖푛푔 which is the output voltage for the full scale current this result is according to the dimensioned since the

DAC was projected to have at least 푉푠푤푖푛푔 = 0.45 푉.

To further analyze the dynamic performance of the DAC the FFT of the differential output signal was computed and the spectrum for the signal was obtained for the typical corner and is represented in Figure 40.

Figure 40 – Frequency Spectrum for the Differential Output of the DAC for the Complete Schematic Circuit in typical corner.

The spectrum of the signal gives us information about the spectral impurities and the dominant harmonics of the signal. From Figure 40 we can observe that the highest spur occurs at 1.68 GHZ with 49.0 dB which corresponds to the SFDR. Since the input signal has a frequency of 1.73 GHz the harmonics that observable in the spectrum shown are the 1푠푡 harmonic at 1.73 GHz which is the fundamental tone with 0 dB, the image of the 2nd harmonic at 55 MHz, the image of the 3rd harmonic at 1.68 GHz. The 3푟푑 harmonic becomes the main limitation for the SFDR since the 2푛푑 harmonic is suppressed because the even harmonics are suppressed when the output is differential as explained in Section 4.2. In the case of the typical corner the 2푛푑 harmonic at 55 MHz presents 70.2 dB.

Table 12 – Dynamic Performance of the Complete Schematic Circuit.

Corner # SFDR (dB) SNDR (dB) SNR (dB) THD (dB) |푽풐풖풕|풎á풙 (V) 0 49.0 40.3 40.3 -73.7 0.53 1 45.7 40.2 40.2 -67.4 0.52 2 49.8 41.2 41.2 -65.7 0.54 3 49.8 41.1 41.1 -73.7 0.55 4 49.7 41.6 41.6 -71.5 0.58 5 49.1 41.1 41.1 -70.5 0.49 6 49.7 41.5 41.5 -69.0 0.50 7 49.6 41.1 41.1 -75.4 0.57 8 49.8 41.4 41.4 -75.7 0.55 9 46.8 40.6 40.6 -68.6 0.50 10 49.8 41.5 41.5 -67.6 0.54 11 49.5 41.1 41.1 -74.9 0.54 12 49.7 41.5 41.5 -74.0 0.57 13 49.0 41.0 41.0 -68.9 0.49 14 49.8 41.5 41.5 -66.8 0.50 15 49.7 41.3 41.3 -74.3 0.52 16 49.7 41.5 41.5 -73.8 0.54

From the results obtained for the schematic circuit we can conclude that the worst SFDR performance happens for the variations of corner 1 which presents a SFDR of 45.7 dB and the best performance of 49.8 dB occurs with the variations of corners 2, 3, 8, 9, 10 and 14. So between the best and worst corners the circuit presents a difference of 4.1 dB in performance. Regarding the SNDR the specification is for a SNDR around 35 dB which is guaranteed in all corners being the worst value obtained for corner 1 of 40.2 dB. Since the values obtained concern the ideal circuit where the connections between devices are considered ideal this assures a margin of 5.2 dB for the losses in the layout circuit for the worst corner. The best SNDR performance is of 41.6 dB and occurs for corner 4, which represents a difference of 1.4 dB between the best and the worst corner. From equation (4) we can compute that for 7 bit the ideal SNR of the circuit is given by: SNR = 6.02 푁 + 1.76 = 43.9 dB Through comparison of the results obtained for the SNR we conclude that the maximum difference to the ideal SNR is of 3.7 dB for corner 1 which presents a SNR of 40.2 dB. The best SNR occurs for corner 4 which presents a SNR of 41.6 dB which is still 2.3 dB lower than the ideal value.

Concerning the THD the best corner which presents a lower harmonic distortion is corner 8 with -75.7 dB while the worst corner which presents the highest harmonic distortion is corner 2 with – 65.7 dB.

The Vswing of the DAC which corresponds to the |푉표푢푡|푚á푥 where all the bits are ‘1’ and the current is at full scale varies from 0.49 V through 0.58 V for a 푅푙표푎푑 of 50 Ω the full scale output current of the DAC varies from 9.8 mA through 11.6 mA. Since the schematic circuit does not consider the connections to real supply voltages which is not true for the real circuit the complete circuit was simulated considering a resistance of 1 Ω in the supply voltage. To further analyze the results the difference (Δ) between the values for the SNDR obtained in Table 12 and the values obtained for the schematic circuit in similar conditions considering the resistance in the supply voltage (Δ = 푆푁퐷푅푛표 푟푒푠푖푠푡푎푛푐푒 −

푆푁퐷푅 푠푢푝푝푙푦 푟푒푠푖푠푡푎푛푐푒) was computed. The results obtained for this simulation and analysis are presented in Table 13.

Table 13 – Dynamic Performance of the Schematic Circuit for a 1 휴 resistance in the supply voltage.

Corner |푽풐풖풕|풎á풙 ΔSNDR SFDR (dB) SNDR (dB) SNR (dB) THD (dB) # (V) (dB)

0 42.2 38.9 38.9 -74.60 0.56 1.4 1 39.0 36.9 36.9 -75.0 0.51 3.3 2 37.2 35.3 35.3 -62.0 0.55 5.9 3 41.6 38.6 38.6 -68.9 0.56 2.5 4 42.8 39.1 39.1 -74.6 0.58 2.5 5 42.6 39.1 39.1 -75.4 0.49 2.0 6 44.2 39.7 39.7 -76.1 0.52 1.8 7 44.5 39.9 39.9 -66.6 0.55 1.2 8 44.4 39.8 39.8 -65.0 0.57 1.6 9 40.4 37.9 37.9 -71.0 0.50 2.7 10 40.4 37.8 37.8 -71.6 0.52 3.7 11 42.5 39.1 39.1 -63.4 0.54 2.0 12 43.4 39.4 39.4 -63.3 0.60 2.1 13 41.4 38.4 38.4 -85.5 0.48 2.6 14 40.6 37.8 37.8 -79.6 0.50 3.7 15 43.5 39.5 39.5 -70.7 0.51 1.8 16 44.3 39.7 39.7 -68.8 0.53 1.8

Comparing both simulations in the same conditions but considering the resistance in the supply voltage or not, we can conclude that the resistance in the supply voltage can really impact the circuit even degrading the SNDR performance by 5.9 dB as obtained for corner 2. It

was observed that the influence of the different switching blocks of the circuit resulted in harmonic spurs that degraded the performance. A solution for this issue is to have larger supply lines and independent supply voltages between the blocks, subjects that will be further analyzed in Chapter 5. The worst dynamic performance regarding the SFDR and SNDR obtained was for corner 2 with a SFDR of 37.2 dB which corresponds to a degradation of 12.6 dB in the SFDR and a SNDR of 35.3 dB which corresponds to a degradation of 5.9 dB in the SNDR. It is also interesting to analyze the results for the Monte Carlo simulations for the complete schematic circuit. Since it was not possible to run 10000 simulations for the complete schematic circuit, which allows to draw conclusions, 100 runs for each of the corners presented in Table 14 were simulated.

Table 14 - Dynamic Performance of the Schematic Circuit for Monte Carlo simulations.

Corner Mean Value (dB) σ (68.3%) 3 σ (99.7%) # (dB) (dB) 0 46.9 2.1 6.3 1 42.3 1.9 5.8 2 45.3 1.7 5.1 3 47.0 1.6 4.9 4 49.3 1.1 3.2

From the results presented in Table 14 we can conclude that considering the 100 runs the maximum 3 σ occurred for corner 0 with a difference to the mean value of 6.3 dB while the results for σ presented a difference of 2.1 dB. From this results we can consider that even with Monte Carlo simulations the circuit assures the performance in terms of SFDR. In these simulations the minimum supply voltage considered was 0.8 V instead of the 0.855 V considered for the rest of the simulations which is even restrictive to the circuits operation.

5. Layout

The layout of a circuit is the definition of the geometry of the masks that are used in fabrication when layering the metals, the n-well, the active region, the polysilicon, the contacts and 푛+ and 푝+ implants. With recent technologies the layout and packaging have become a greater limitation on the circuits’ performance. While the scaling of the device resulted in an increase of the speed of the transistors, there are also non idealities and interactions in the layout that limit the speed and precision. Nowadays the integrated circuits require more metal layers in the new generations of technology since these circuits are very dependent on the quality of the interconnects. These interconnections are mainly characterized by their series resistance and parallel capacitance and heavily impact the performance. While the resistance is a greater limitation when associated with supply and ground lines, which causes voltage drops, the distributed resistance and capacitance in long signal lines introduces delay. Since in general the upper levels of metal have a lower capacitance per width unit but they usually have a higher minimum allowable width than the lower layers, for a given length, the total capacitance can be only slightly lower for the top metal layers. The different metal lines also suffer from parallel and border capacitances between them which also can affect the performance of the circuit. A usual solution for this last problem is the use of shielding layers between them and the use of contacts that assure that the surface exposed to the different layer is lower.

5.1 Layout Rules and Techniques

For each specific technology there are a set of defined rules that need to be applied during the layout of the circuit in order to ensure the proper fabrication of the transistors and interconnects despite the variations that may occur during each step of fabrication. Another aspect taken into consideration when designing the layout is the layout techniques used to minimize the unwanted known effects like mismatch, noise, etc. Some examples include the use of transistors with multiple fingers, the use of symmetry and the reference distribution.

 Layout Rules

▶ Minimum Width: Regarding the width defined on a mask, in general the allowable width increases with the increasing thickness of a layer. So as the technologies scale the thickness has to decrease accordingly. The minimum width, according to [15], is imposed by the lithography and processing capabilities of the technology. An example of the variations that may occur in the layer and explain the need for a minimum width that ensures that the line is correctly layered is represented in Figure 41.

푊푚푖푛 Ideal Layer Line

Real Layer Line

Figure 41 – Variation in layer line with minimum width during fabrication.

▶ Minimum Spacing: There is the need of a minimum spacing between two consecutive geometry designs in the same layer because if they are too close they can be shorted and also for cases where the implant should not overlap for example a poly line. ▶ Minimum Enclosure: The minimum enclosure is a rule specially to ensure that despite tolerances the devices and contacts remain contained in the current layers either for example the n-well or implant or even the correct layers of contact. ▶ Minimum Extension: The rule of minimum extension applies to layers that have to be extended beyond the limit of others, as an example the gate polysilicon of a transistor has to be extended beyond the active area to ensure the correct function of the transistor at the edge. Other specific rules to the technology in use may have to be applied to ensure the DRC (Design Rule Check) of the layout.

 Layout Techniques

▶ Multifinger Transistors: The use of transistors with multiple fingers, opposed to large transistors with only one finger, reduces in general the area of the Source/Drain junction and the gate resistance. However there is a conflict between minimizing the gate resistance noise and reducing the Source/Drain perimeter capacitance so there needs to be a compromise between the two. ▶ Symmetry: The symmetric layout of circuits ensures that all the considered devices have the same surrounding environment. In general the use of symmetry in circuits suppresses the effect of common-node noise and even-order nonlinearity. When dealing with large transistors the gradients can cause considerable mismatches in the devices, so the use of a specific technique of symmetry, the “common-centroid” configuration allows for the first-order gradients along both axes to be cancelled. In this configuration the idea is to decompose each transistor in two halves that are placed diagonally opposite to each other and connected in parallel as represented in Figure 42. To suppress the linear gradients the cross coupling technique can also be used where all four halves of the two transistors are placed in the same axis and we can either connect the first half with the last one or each one of the middle with the one in the opposing side as presented in Figure 43.

Figure 42 – Example of layout using Common-centroid technique.

Figure 43 – Example of layout using Cross-Coupling technique.

▶ Reference Distribution: Regarding the reference distribution there may be systematic mismatches due to the fact that a large number of circuits are connected to the same bias current or voltage. According to [31] in order to ensure that the VDD and ground lines have values closer to the ideal the widths of the conductors supplying and returning the currents to the circuit should be increased, by doing this the series resistance is reduced.

5.2 Results of the Layout Blocks

The design of the layout of the circuit was planned to minimize the area occupied and to assure that the connections between the blocks were also minimized. The process followed during the dimensioning of the blocks in which each block was designed individually and connected to the blocks that had been already designed was also followed for the layout. After the layout of each block the resistances and capacitances of the block were extracted and the block was simulated. The circuit was separated in four different blocks for layout as represented in Figure 44: Clock Driver, Biasing Circuit, Decoder and Current Source. The Decoder block includes the decoder and the registers while the Current Source block includes the latches, cascodes, switches and current source transistors.

Figure 44 – Layout Planning of the Circuit.

5.2.1 Latch Bank

The operation of the asynchronous decoder suffers from a lot of circuit imperfections that may result in data skew, variations of the waveform shape and logic glitches of the output waveforms. The latch and driver circuit shape these different waveforms to identical and very accurately synchronized waveforms that control the switches. Any difference between the different latches translates in a timing error which as seen in Section 4.7 is one of the main sources of distortion in the circuit. So being the latch so critical for the dynamic performance of the circuit this was the first block to be planned in the layout. All the connections in this circuit were planned to be symmetric and to be the smallest possible since the capacitance effects presented to be critical. To reduce the interaction between the different signals in the latch circuit decoupling lines of supply voltage were used between the signal lines. The layout of each individual latch circuit is presented in Figure 45 while the complete block of latches is presented in Figure 45.

Figure 45 - Layout of the Latch.

Figure 46 - Layout of the Bank of Latches.

After the layout of the complete block of latches was complete the equivalent resistances and capacitances of the circuit were extracted and the circuit was simulated considering the rest of the blocks in schematic and the results for the dynamic performance are presented in Table 15.

Table 15 - Dynamic Performance of the DAC considering the circuit with the extracted Layout of the Bank of Latches.

Corner # SFDR (dB) SNDR (dB) SNR (dB) THD (dB) |푽풐풖풕|풎á풙 (V) 0 48.0 40.0 40.7 -48.0 0.54 1 38.2 36.5 36.6 -53.6 0.53 2 40.3 37.8 37.9 -53.1 0.56 3 40.1 37.7 37.8 -54.0 0.56 4 43.2 39.2 39.4 -53.6 0.54 5 41.9 38.7 38.8 -57.5 0.49 6 42.8 38.6 38.7 -55.9 0.53 7 42.9 39.2 39.2 -57.6 0.50 8 44.5 39.5 39.6 -56.3 0.52 9 39.4 37.3 37.4 -54.9 0.51 10 41.7 38.6 38.7 -53.9 0.50 11 41.1 38.3 38.4 -55.1 0.51 12 42.8 39.0 39.1 -54.4 0.54 13 41.1 38.3 38.3 -56.3 0.47 14 41.7 38.2 38.3 -55.0 0.50 15 43.1 39.2 39.3 -56.6 0.50 16 44.6 39.5 39.6 -55.5 0.54

To better understand the differences between the schematic circuit and the circuit with the layout of the bank of latches a comparison between the best and worst corners of the layout simulation and the values for the same corners in the schematic, considering as critic the value of the SNDR, is presented in Table 16.

Table 16 – Dynamic Performance Comparison between the Schematic circuit and the circuit with the extracted Layout of the Bank of Latches

Simulation Corner # SFDR (dB) SNDR (dB) SNR (dB) THD (dB) |푽풐풖풕|풎á풙 (V)

Schematic 1 45.7 40.2 40.2 -67.4 0.52

Layout 1 38.2 36.5 36.6 -53.6 0.53

Schematic 16 49.7 41.5 41.5 -73.8 0.54

Layout 16 44.6 39.5 39.6 -55.5 0.54

For the schematic circuit we concluded that the worst corner was corner 1 with 40.2 dB of SNDR. For the circuit with the layout of the latches we can observe that the worst corner is also corner 1 with a SNDR of 36.5 dB, which corresponds to a degrading in performance of 3.7 dB. The |Vout|máx for corner 1 presents an increase of 1 mV which corresponds to an increase of about 2% of the current. The SFDR presents a decrease of 7.5 dB from the schematic circuit to the circuit with the layout of latches. This corner was greatly impacted by the layout circuit since it operates for the lower supply voltage of 0.855 V and all the devices are slow, so the parasitic resistances and capacitances extracted and considered greatly impact the circuit operation. Regarding the best corner in both situations the best SNDR was for corner 16 with a degradation in performance of 5.1 dB. In this case the |Vout|máx was the same for both simulations. From Figure 45 we can see that the area of the unit latch is 32.33 μm² (17.38 μm × 1.86 μm) while from Figure 46 we see that the complete bank of latches occupies an area of 1740.4 μm² (100.14 μm × 17.38 μm).

5.2.2 Switches and Cascode

The bank of latches synchronizes and shapes the waveforms that control the switches. As explained in Section 4.7 another main constraint and source of dynamic degradation for the circuit are the switches so the layout of this block was done after the layout of the bank of latches also with the constraint of keeping the connections symmetric and small to reduce the parasitic capacitance and resistance of the circuit. With the purpose of reducing the connections between the blocks and to minimize the occupied area the layout of the cascode transistors was

done with the switches. The complete cells for 1 bit thermometer decoded and for the LSB bit are presented in Figure 47.

Figure 47 - Layout of the Switch and Cascode transistors of the LSB bit and a thermometer bit.

The block of latches was connected to the block of switches and cascode transistors and the resistance and capacitance of the complete circuit was extracted. These blocks were replaced in the schematic by the equivalent extracted block and the complete circuit was simulated. The layout of the complete block is presented in Figure 48.

LATCHES

SW + CAS

Figure 48 - Layout of the Latches, Switches and Cascode.

The circuit with latches, switches and cascode transistors occupies an area of 2188 휇푚² (100.14 휇푚 × 21.85 휇푚).

5.2.3 Current Source

To complete the current source block the layout of the matrix of current sources transistors was added to the block of latches, switches and cascode transistors. To improve the layout of this block a common centroid technique was used in the matrix of current sources to decrease the effects of the gradients. Each current source of a thermometer bit was divided in 16 transistors while the current source of the LSB was divided in 8 transistors adding 8 dummy transistors. The scheme of the common centroid of the complete cell is presented in Figure 49. The layout of the matrix of the current source transistors is presented in Figure 50.

Figure 49 - Scheme of the Common Centroid used in the Matrix of the Current Source.

Figure 50 - Layout of the Matrix of Current Source Transistors.

To further improve the layout of the circuit a row/column with 4 dummy transistors was added to each side of the matrix in order to minimize etch effects on the transistors guaranteeing that all the current source transistors are in the same conditions. The complete layout circuit with latches, switches, cascodes, dummies and current source is presented in Figure 51.

Figure 51 – Layout of the Current Source, Cascode, Switches and Latches.

The complete circuit presents a length of about 113.5 휇푚 and a width of about 133.8 휇푚. The parasitic capacitance and resistance of the circuit were extracted and the complete circuit was simulated being the results for the dynamic performance presented in Table 38 (see Attachments). A comparison between the best and worst corner for the circuit with the extracted layout of the bank of latches (Layout 1) and the extracted layout of the complete Current Source Block (Layout 2) is presented in Table 17.

Table 17 – Dynamic Performance Comparison between the circuit with the extracted Layout of the Bank of Latches and the extracted Layout of the Current Source Block.

Simulation Corner # SFDR (dB) SNDR (dB) SNR (dB) THD (dB) |푽풐풖풕|풎á풙 (V)

Layout 1 1 38.2 36.5 36.6 -53.6 0.53

Layout 2 1 42.7 38.8 39.2 -49.9 0.43

Layout 1 7 42.9 39.2 39.2 -57.6 0.50

Layout 2 7 49.8 41.1 41.2 -55.3 0.47

Considering the results for this layout block presented in Table 38 (see Attachments) we can conclude that the worst corner is corner 1 with an SNDR of 38.8 dB while the best corner is corner 7 with an SNDR of 41.1 dB. From the comparison presented in Table 17 we can conclude that there was an improvement for SFDR, SNDR and SNR. For corner 1 the improvement was of 4.5 dB in the SFDR and of 2.3 dB in the SNDR. For corner 7 the SFDR increased 6.9 dB while the SNDR increased 1.9 dB. Although there was an improvement in the dynamic performance, the

|Vout|máx decreased for all corners. For corner 1 there was a decrease of 0.1 V in the output full scale voltage of the DAC which corresponds to a 20% decrease in the output current. This decrease can be explained by the voltage drops in the connections of the block which changed from ideal to connections with parasitic resistance. This voltage drops changed the biasing voltages considered for the transistors in the ideal circuit and resulted in a decreased of the current produced by the current source.

5.2.4 Biasing Circuit

The current source and cascode transistors are biased by a stable current generated in the biasing circuit as explained in Section 4.3. This biasing circuit includes the Current Reference Generator presented in Figure 53; the Voltage Reference Generator with the layout presented in Figure 52; the OpAmp presented in Figure 54 and the Biasing Reference for the OpAmp presented in Figure 55. In this layout there was special attention in the OpAmp to ensure that the layout was as much symmetrical as possible so both branches of the differential pair would see the same capacitances and resistances. For the Current Reference Generator there was special attention to divide the transistors in fingers to minimize the occupied area.

Figure 53 - Layout of the Current Figure 52 - Layout of the Voltage Reference Generator. Reference Generator.

Figure 54 - Layout of the OpAmp.

Figure 55 – Layout of the Biasing Reference of the OpAmp.

All these individual blocks were connected to each other and the complete biasing circuit is presented in Figure 56.

Figure 56 - Layout of the Complete Biasing Circuit.

. The Biasing Circuit Block presents a length of 20.85 휇푚 and a width of 80.5 휇푚. After the complete layout of the Biasing Circuit, the block was replaced in the schematic by the equivalent extracted block and the complete circuit was simulated. The results of this simulation are presented in Table 39 (see Attachments). A comparison between the best and worst corner for the circuit with the extracted layout of the Current Source Block (Layout 2) and the circuit with the extracted layout of the Current Source Block and of the Biasing Circuit (Layout 3) is presented in Table 18.

Table 18 – Dynamic Performance Comparison between the Layout of the Bank of Latches and the Layout of the Current Source Block.

Simulation Corner # SFDR (dB) SNDR (dB) SNR (dB) THD (dB) |푽풐풖풕|풎á풙 (V)

Layout 2 1 42.7 38.8 39.2 -49.9 0.43

Layout 3 1 42.7 38.9 39.2 -49.5 0.46

Layout 2 7 49.8 41.1 41.2 -55.3 0.47

Layout 3 7 49.8 41.4 41.6 -55.3 0.4

Considering the results for this simulation presented in Table 39 (see Attachments) we can conclude that the worst corner is corner 1 with an SNDR of 38.9 dB while the best corner is corner 7 with an SNDR of 41.4 dB. From the comparison presented in Table 18 we can conclude that the dynamic performance regarding the SFDR remained the same for both corners, while the SNDR increased 0.1 dB for corner 1 and 0.4 dB for corner 7. The SNR remained the same for corner 1 and increased 0.4 dB for corner 7. The THD increase for corner 1 and remained the same for corner 7. Regarding the |Vout|máx there was an increase of 0.03 V for corner 1 and a decrease of 0.07 V for corner 7. It is possible to conclude, since the performance remained similar to the previous, that the performance of the circuit was not majorly impacted by the layout of this block.

5.2.5 Clock Driver

The layout of the Clock Driver was planned according to the rest of the blocks layout as presented in Figure 44. Since the resistance is the main constraint for the propagation of the clock signal throughout the Clock Driver, large metal lines were drawn through the propagation path resulting the layout presented in Figure 57. To minimize etch effects and ensure that the transistors in the Clock Driver were in the same conditions dummy transistors were used to surround the circuit.

Figure 57 - Layout of the Clock Driver.

The resistances and capacitances of the complete Clock Driver block were extracted and the complete circuit was simulated considering the previous blocks. The results of this simulation are presented in Table 40 (see Attachments). The complete circuit presents a length of 11.91 휇푚 and a width of 50.14 휇푚. A comparison between the best corners and worst corners for the circuit with the extracted layout for the blocks of the Current Source and Biasing Circuit (Layout 3) and the extracted layout for the blocks of the Current Source, Biasing Circuit and Clock Driver (Layout 4) is presented in Table 19.

Table 19 – Dynamic Performance comparison between the circuit with the Layout of the Current Source Block and Biasing Circuit and the circuit with the Layout of the Current Source Block, Biasing Circuit and Clock Driver.

Simulation Corner # SFDR (dB) SNDR (dB) SNR (dB) THD (dB) |푽풐풖풕|풎á풙 (V)

Layout 3 1 42.7 38.9 39.2 -49.5 0.46

Layout 4 1 42.1 38.2 38.9 -46.2 0.47

Layout 3 7 49.8 41.4 41.6 -55.3 0.4

Layout 4 7 49.9 41.1 41.7 -49.9 0.4

Considering the results for this layout block presented in Table 40 (see Attachments) we can conclude that the worst corner is corner 1 with an SNDR of 38.2 dB while the best corner is corner 7 with an SNDR of 41.4 dB. From the comparison presented in Table 19 we can conclude that the dynamic performance regarding the SFDR decreased for 0.6 dB corner 1 while for corner 7 increased 0.1 dB. The SNDR decreased 0.7 dB for corner 1 and 0.3 dB for corner 7. The SNR decreased

0.3 dB for corner 1 and 0.1 dB for corner 7. Regarding the |Vout|máx there was an increase of 0.01 V for corner 1 while for corner 7 remained the same. The main difference between the two simulations is that the THD increased for all corners.

5.2.6 Registers and Decoder Block

The Decoder Block considers the Registers, Latency Equalizer and Decoder of the Thermometer Bits. The layout of this block was planned to have the same width has the Bank of Latches since each decoder of the Matrix Decoder connects to an individual latch. To minimize delays between the decoding a tree distribution of the input clock of the registers was used. In this block the resistance associated with the supply of the circuit for both the supply voltage and ground line appeared to be critic so large metal lines and direct vias to the transistors were used to minimize the connections. Each individual block of the Decoder Block was done in separate and then the complete circuit was connected. The layout of a register is presented in Figure 59, the layout of the Latency Equalizer is presented in Figure 58, the layout of the Local Decoder of the Matrix Decoder is presented in Figure 60 and the Decoder of the Thermometer Bits is presented in Figure 61.

Figure 59 – Layout of a Register. Figure 58 – Layout of the Latency Equalizer.

Figure 60 – Layout of the Local Decoder of the Matrix Decoder.

Row and Column Decoder

Local Decoders

Figure 61 - Layout of the Decoder of the Thermometer Bits.

All the blocks were correctly positioned and connected resulting the complete Registers and Decoder Block presented in Figure 62. The complete circuit presents a length of 100.88 μm and a width of 31.85 μm.

Latency

Registers Equalizer Registers

Row and Column Decoder

Local Decoders

Figure 62 – Layout of the complete Registers and Decoder Block.

5.2.7 Complete DAC

After the layout of each block was complete the blocks were connected according to the previous plan presented in Figure 44. The resulting layout of the complete DAC is presented in Figure 63. The analog input/outputs were routed to the bottom part of the circuit while the digital inputs were routed to the upper part of the circuit. In this layout there was special attention to the routing of the supply voltages in order to assure the minimum resistance, using large metal lines and different metals stacked to make the routing. Separate voltage supplies were considered to mitigate the effects of the switching blocks. The Registers, Decoder and Latches were connected to one voltage supply, the Clock Driver was connected to another voltage supply and the Biasing Circuit and Current Source transistors were connected to another voltage supply. This layout is presented in the project since the positions of the blocks and the total area of the circuit will not change during the further improvements to the layout. During this layout the routing between the Biasing Circuit and the Current Source Block appear to be critical to the performance of the circuit so there will be further improvement to this routing.

Registers

Decoder

Latches + Switches + Cascodes

Clock Driver Clock

Matrix of Current

Sources

Biasing Biasing Circuit

Figure 63 – Layout of the Complete DAC.

The complete layout presents a length of 170 μm and a width of 170 μm which results in a total area of 0.0289 mm2.

6. Results and Conclusions

In this chapter a revision of the work developed and of the results obtained in this project will be presented. A comparison between the initial results and the final results obtained will be analyzed and conclusions will be drawn. In this project a DAC working with a 7 bit input code at a 3.52 GHz update rate was planned, dimensioned and the layout of the blocks dimensioned was designed. A mathematical model of the DAC was initially developed to allow the draw of conclusions about the maximum

σLSB(I)/I of the current source and about the segmentation of the DAC that met the specifications required. From the use of this model it was concluded that a segmentation of 6 bits in unary implementation and 1 bit in binary implementation was the best suited to meet the requirements. After the segmentation was defined the blocks of the circuit were planned and dimensioned. The best topologies for each block and the results obtained for each one after dimensioned were presented. The low power supply is a constraint in meeting the requirements in terms of dimensioning the circuit, the voltage margins in the circuit. The complete schematic circuit was simulated in corners and the results were analyzed considering the ideal circuit, the effect of a resistance in the supply voltage and the comparison between the circuit with and without the flip flop was made. From the simulation with the schematic circuit we concluded that the best performance in terms of SNDR of the circuit, which is the specification for this project, was of 41.6 dB and the worst performance was of 40.2 dB. For all corners the specification of 35 dB of SNDR was achieved. The layout of the circuit was planned being presented the considerations taken in the layout of each specific block and the final dynamic performance for the extracted blocks was obtained and analyzed. Finally the complete circuit with the blocks extracted was simulated and the results are presented in Table 20. Although the final routing of the circuit is missing from the layout considered we can draw conclusions about the performance of the circuit. It is considered that there will be some loss with the final routing since it adds resistance and capacitance to the connections but the main circuit is considered in this results. The spectrum for the differential output voltage of the DAC for the typical corner (corner 0) is presented in Figure 68 (see Attachments). The differences between the schematic performance and the layout performance in terms of SFDR (∆SFDR), SNDR (∆SNDR), SNR (∆SNR), THD (∆THD) and |Vout|máx (∆Vout) were measured and are presented in Table 41 (see Attachments). From this results we can conclude that the greatest degradation from the schematic circuit to the layout circuit is in the THD which presents differences of 25.1 dB for corner 11 and in the output voltage of the circuit which presents a difference of 0.24 V in corner 8.

The increase of the THD from the schematic circuit to the layout is expected since the supply of the circuit is affected by the real resistances and capacitances extracted. These connections suffer from the operation of the circuit and harmonic components appear in the spectrum. Also nonlinearities regarding synchronism and timing inaccuracies tend to appear and reflect as distortion in the performance. The difference of 0.24 V in the output voltage correspond to a decrease of 44% in the output current of the DAC. These differences as explained were observed during the layout of the Current Source Block, so there is a need to revisit this block and improve any connections that may be causing voltage drops in the biasing of the transistors, resulting in a loss of output current. Regarding the SFDR for corner 3 there is a loss of 5 dB from the schematic to the layout while for corner 10 there is a loss of 1.6 dB in the SNDR and of 1.5 dB in the SNR. These losses in performance reflect the increase in the distortion from the schematic to the layout.

Table 20 – Dynamic Performance of the DAC considering the Layout of the Current Source Block, the Biasing Circuit, the Clock Driver and the Decoder.

Corner # SFDR (dB) SNDR (dB) SNR (dB) THD (dB) |퐕퐨퐮퐭|퐦á퐱 (V) 0 48.8 40.5 41.0 -50.4 0.44 1 43.2 39.1 39.5 -50.5 0.45 2 47.7 40.5 40.8 -51.1 0.42 3 44.8 39.6 40.1 -49.0 0.51 4 48.4 40.3 40.7 -50.9 0.51 5 50.0 41.0 41.4 -51.2 0.35 6 48.4 40.5 40.8 -51.8 0.27 7 50.1 41.3 41.6 -52.1 0.40 8 47.8 40.6 40.9 -52.5 0.31 9 46.0 40.0 40.4 -49.4 0.44 10 47.7 39.9 40.0 -55.6 0.41 11 47.0 40.2 40.7 -49.8 0.47 12 50.1 40.4 40.8 -50.6 0.49 13 47.8 40.4 40.9 -50.3 0.48 14 47.4 40.6 40.8 -54.2 0.39 15 50.0 41.0 41.4 -51.2 0.30 16 49.8 40.4 40.7 -52.4 0.45

From the results presented in Table 20 we conclude that the circuit meets the specification of 35 dB of SNDR for all corners for a clock frequency of 3.52 GHz and an input frequency of 1.73 GHz of the digital input code. The SFDR varies from 43.2 dB in corner 1 to 50.1 dB in corner 7 and corner 12. The worst SNDR performance occurs for corner 1 with 39.1 dB while the best performance occurs for corner 7 with 41.3 dB of SNDR. Regarding the SNR it varies from 39.5 dB for corner 1 to 41.6 dB in corner 7. The highest THD occurs for corner 3 with -49 dB while the lowest occurs for corner 10 with -55.6 dB. The output voltage of the DAC

varies from 0.27 V in corner 6 which is 0.18 V lower than the 0.45 V expected to 0.51 V in corners 3 and 4. The circuit was also tested for the extracted layout blocks considering a resistance of 1 Ω in the supply voltage this results and the difference (Δ SNDR) between the SNDR obtained for the layout with and without the resistance are presented in Table 21 .

Table 21 – Dynamic Performance of the DAC considering the Layout of the Current Source Block, the Biasing Circuit, the Clock Driver and the Decoder with a resistance of ퟏ 휴 in the supply voltage.

SFDR SNDR 횫 퐒퐍퐃퐑 Corner # SNR (dB) THD (dB) |퐕퐨퐮퐭|퐦á퐱 (V) (dB) (dB) (dB)

0 46.4 40.1 40.3 -53.7 0.44 0.4 1 40.5 37.9 38.0 -55.7 0.45 1.2 2 42.6 38.8 39.1 -51.6 0.42 1.7 3 43.4 39.2 39.4 -53.3 0.51 0.4 4 45.9 39.8 40.0 -54.4 0.47 0.5 5 49.8 41.1 41.3 -54.9 0.35 -0.1 6 46.5 39.9 40.1 -52.6 0.29 0.6 7 49.9 41.2 41.3 -56.0 0.40 0.1 8 45.6 39.8 40.0 -53.2 0.33 0.8 9 44.5 39.6 39.7 -56.2 0.43 0.4 10 46.8 40.5 40.6 -58.0 0.40 -0.6 11 47.2 40.4 40.6 -55.4 0.49 -0.2 12 49.8 40.3 40.5 -55.5 0.50 0.1 13 44.5 39.7 39.9 -53.4 0.38 0.7 14 42.5 38.4 38.5 -54.8 0.33 2.2 15 49.4 40.6 41.0 -52.4 0.44 0.4 16 48.7 38.7 38.9 -53.5 0.40 1.7

From the results presented in Table 21 we can conclude that as seen for the schematic circuit the resistance in the supply voltage degrades the SNDR performance for most corners. For corner 14 there is even a degradation of 2.2 dB in the SNDR. In this case the worst corner is corner 1 with a SFDR of 37.9 dB which is still above the 35 dB required. Although the layout circuit considering the resistance in the supply voltage met the specification of 35 dB of SNDR for all corners, since the routing between the layout blocks was not considered in these simulations it is expected some loss in the performance of the circuit. Since this routing adds parasitic resistance and capacitance to the circuit the distortion will increase. However these results assure a margin of 2.9 dB for the worst corner to the required SNDR. In the circuit the current measured in the power supply is of 28 mA which for a supply voltage of 0.9 V results in a power consumption of 25.2 mW.

The performance achieved in the DAC designed and of the published arts with similar content referred in Table 1 is presented in Table 22.

Table 22 - Performance Comparison of Published arts with the work developed.

Reference [10] [11] [12] [13] This work Sampling Rate (GS/s) 3.1 3.5 3.3 3.0 3.5 Resolution (bit) 6 6 6 6 7 Technology (nm) 90 28 90 90 28

SFDR @ 푓푠/2 (dB) 37.2 30.6 36.4 36.0 40.5

SNDR @ 푓푠/2 (dB) 29 n.a. n.a. n.a. 37.9 INL/DNL (LSB) 0.09/0.06 0.03/0.03 0.25/0.22 0.07/0.05 n.a Power Consumption 17.7 53.0 47.0 8.3 25.3 (mW) Core Area (푚푚2) 0.038 0.035 0.055 0.045 0.029

Although the results presented for the other published arts refer to the fabricated chip an initial comparison of the performance achieved can be made. Regarding the work presented in [10], [12] and [13] the sampling rate of these devices are lower than the sampling rate achieved in this project, the resolution is only of 6 bit instead of 7 bit and the technology used is different since the circuit was fabricated in 90 nm. Since the resolution is lower from the one presented in this project the SNDR performance achieved by the published arts is expected to be lower. Even so, the SFDR performance is still 3.3 dB higher than the one achieved by [10] at

푓푠/2 and the SNDR is 8.9 dB higher. In [11] the sampling rate is similar to this project and the device was fabricated in the same technology of 28 nm. Although the resolution is only 6 bit the

SFDR achieved at 푓푠/2 is still 9.9 dB lower than the one achieved in this project. However reservations concerning the fact that the values presented in the published arts are for the fabricated chip need to be made, since the performance can be degraded from the layout simulations. These simulations consider mathematical models while in the fabricated circuit there are more nonlinearities and interactions that are not taken into consideration. It also needs to be considered the fact that the DAC presented in this project was design for industrial production under analysis for corner, assuring the correct functioning for all conditions. This analysis is not presented for the published arts considered, neither the output voltage swing is mentioned, which for applications purpose a 0.45 V can be appealing.

7. Future Work

The next steps in the development of the DAC will be to improve the layout connections between the blocks to enhance the performance of the circuit. When the complete layout is finished the circuit PADs that connect the inputs and outputs of the circuit in the chip will be added to the circuit. The planning of the position of these PADs has been initiated with the analog outputs and inputs routed to one side of the circuit while the digital inputs and outputs have been routed to the other side of the circuit. These PADs also have protections that assure that the discharges that may happen when the circuit is connected do not affect the circuit. After this step the circuit will be sent to fabrication. The final chip will be tested regarding the static and dynamic performance in order to compare the results with both the schematic and layout results. The testing of the circuit will include the INL/DNL, measures of the dynamic performance, regarding the SFDR, SNDR, SNR and THD and the power consumption of the device. The results obtained for this testing will be compared with published arts with similar content as the ones referred in Table 1 and conclusions will be drawn regarding the performance of the converter.

8. References

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[19] P. Udawant, “Capacitance Effects ON D/A Converters,” M.Tech credit seminar report, Electronic systems group, EE. Dept., November 2003.

[20] B. Razavi, “Introduction to A/D conversion,” October 2014. [Online]. Available: http://www.seas.ucla.edu/brweb/teaching/215D_S2012/ADC1.pdf.

[21] M. Clara, High-Performane D/A-Converters, Berlin: Springer, 2013.

[22] M. Delgado-Restituto, J. F. Fernández-Bootello, R. d. Rio, J. M. d. l. Rosa e J. Ruiz- Amaya, “A 0.13µm CMOS Current Steering D/A Converter for PLC and VDSL Applications,” [Online]. Available: http://digital.csic.es/bitstream/10261/3847/1/DCIS05b.pdf.

[23] A. C. J. Duinmaijer, M. J. M. Pelgrom e A. P. G. Welbers, “Matching Properties of MOS Transistors,” IEEE Journal of Solid-State Circuits, pp. Vol.24, Nº5, pp. 1433-1439, October 1989.

[24] E. Alarcón, M. Albiol e J. L. González, “Mismatch and Dynamic Modeling of Current Sources in Current-Steering CMOS D/A Converters: An Extended Design Procedure,” IEEE Transactions on Circuits and Systems I, pp. Vol. 51, Nº1, pp. 159-169, January 2004.

[25] K. Doris, A. van Roermund e D. Leenaerts, Wide-Bandwidth High Dynamic Range D/A Converters, Dordrecht, Netherlands: Springer, 2006.

[26] G. De Vita e G. Iannaccone, “A Sub-1-V, 10ppm/ºC. Nanopower Voltage Reference Generator,” IEEE Journal of Solid-State Circuits, Vol.42, Nº7, pp. 1536-1542, July 2007.

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[29] R. L. Geiger, VLSI Design Techniques for Analog and Digital Circuits, McGraw-Hill Book

Company, 1990.

[30] M. J. Pelgrom, Analog-to-Digital Conversion, New York: Springer, 2010.

[31] R. J. Baker, CMOS Circuit Design, Layout and Simulation, New Jersey: John Wiley & Sons, Inc., 2010.

9. Attachments

Figure 64 – INL_yield for segmentation 6MSB/1LSB for 흈푳푺푩(푰)/(푰) = ퟎ. ퟎퟒퟐퟒ for a differential output.

Figure 65 – DNL_yield for segmentation 6MSB/1LSB for 흈푳푺푩(푰)/(푰) = ퟎ. ퟎퟒퟐퟒ for a differential output.

Figure 66 – INL_yield for segmentation 7MSB/0LSB for 흈(푰)/(푰) = ퟎ. ퟎퟓ for a differential output.

Figure 67 – DNL_yield for segmentation 7MSB/0LSB for 흈푳푺푩(푰)/(푰) = ퟎ. ퟎퟓ for a differential output.

Table 23 – INL/DNL specification computed through the high level model of the DAC for a given segmentation.

Codification 흈푳푺푩(푰)/푰 INL_yield(99.75%) [LSB] DNL_yield(99.75%) [LSB] 6MSB/1LSB 0.0453 0.90690 0.32108 7MSB/0LSB 0.05 0.99965 0.21594

Table 24 – Dynamic specifications not considering jitter computed through the high level model of the DAC.

Codification 푭풔[푮푯풛] 푭풊[푮푯풛] THD[dB] SFDR[dB] SNR[dB] ENOB[bit] SNDR[dB] 6MSB/1LSB 3.52 1.76 - 52.9 43.7 7.0 43.7 7MSB/0LSB 3.52 1.76 - 50.5 43.7 7.0 43.7 6MSB/1LSB 3.52 0.342 -51.0 54.1 44.0 6.9 43.2 7MSB/0LSB 3.52 0.342 -51.6 53.5 44.0 6.9 43.3

Table 25 – Dynamic specifications considering jitter computed through the high level model of the DAC.

Codification Jitter[%] 푭풔[푮푯풛] 푭풊[푮푯풛] THD[dB] SFDR[dB] SNR[dB] ENOB[bit] SNDR[dB] 6MSB/1LSB 10 3.52 1.76 - 46.9 26.5 4.1 26.5

7MSB/0LSB 10 3.52 1.76 - 44.5 26.7 4.1 26.7 6MSB/1LSB 10 3.52 0.342 -55.0 57.3 39.6 6.3 39.5

7MSB/0LSB 10 3.52 0.342 -52.5 55.0 39.7 6.3 39.5 6MSB/1LSB 5 3.52 1.76 - 48.5 32.3 5.1 32.3

7MSB/0LSB 5 3.52 1.76 - 46.7 32.1 5.0 32.1 6MSB/1LSB 5 3.52 0.342 -55.0 57.4 42.9 6.8 42.6

7MSB/0LSB 5 3.52 0.342 -52.2 53.1 42.9 6.7 42.4 6MSB/1LSB 2.5 3.52 1.76 - 47.5 36.8 5.8 36.8

7MSB/0LSB 2.5 3.52 1.76 - 46.0 36.9 5.8 36.9 6MSB/1LSB 2.5 3.52 0.342 -54.4 57.8 44.5 7 44.1

7MSB/0LSB 2.5 3.52 0.342 -54.0 55.5 44.3 7.0 43.9

Table 26 – Dimensions of the transistor of the Current Reference Generator.

Transistor W[흁풎] L[흁풎] Transistor W[흁풎] L[흁풎] Transistor W[흁풎] L[흁풎]

푴푷ퟏ 9*2.6 0.14 푴푷ퟔ 15*2.6 0.21 푴푵ퟕ 220*0.14 0.3

푴푷ퟐ 15*2.6 0.21 푴푵ퟑ 32*0.14 0.3 푴푵ퟖ 40*0.5 0.5

푴푷ퟑ 0.25 3*0.14 푴푷ퟕ 9*2.6 0.14 푴푵ퟗ 53*0.14 0.3

푴푵ퟏ 0.14 0.14 푴푷ퟖ 15*2.6 0.2 푴푪푺ퟑ < ퟏ: ퟖ > 2*1.9 0.5

푴푷ퟒ 0.3 0.14 푴푵ퟒ 155*0.14 0.3 푴푪푨푺ퟑ 2*0.9 0.04

푴푵ퟐ 0.14 0.14 푴푵ퟓ 112*0.5 0.5 푴푪푺ퟐ < ퟏ: ퟔ > 2*1.9 0.5

푴푷ퟓ 9*2.6 0.14 푴푵ퟔ 140*0.5 0.5 푴푪푨푺ퟐ 2*0.9 0.04

Table 27 – Dimensions of the transistors of the OpAmp.

Transistor W[흁풎] L[흁풎]

푴푶푷ퟏ 0.15 0.09

푴푶푷ퟐ 0.15 0.09

푴푶푷ퟑ 2.25 0.4

푴푶푷ퟒ 2.25 0.4

푴푶푵ퟓ 0.44 0.09

푴푶푵ퟔ 0.45 0.09

Table 28 – Dimensions of the transistors of the Voltage Reference Generator.

Transistor W[흁풎] L[흁풎] Transistor W[흁풎] L[흁풎] Transistor W[흁풎] L[흁풎]

푴ퟏ 2.6 0.03 푴ퟓ 2.3 0.14 푴ퟗ 2.1 0.6

푴ퟐ 0.14 0.9 푴ퟔ 1.65 0.14 푴ퟏퟎ 2 0.9

푴ퟑ 2.6 0.03 푴ퟕ 0.14 0.6 푴푺ퟏ 0.14 0.11

푴ퟒ 0.14 0.12 푴ퟖ 0.14 0.12 푴푺ퟐ 0.4 0.03

푴푺ퟑ 0.14 0.03

Table 29 - Dimensions of the transistors and resistor of the Current Reference of the OpAmp.

Transistor W[흁풎] L[흁풎]

푴푪푷ퟏ 2.6 0.45

푴푪푷ퟐ 3*1.15 0.9

푴푪푵ퟏ 2.6 0.06 Resistor R[풌훀]

푹풃풊풂풔 7

Table 30 - Dimensions of the transistors of the Driver.

Transistor W[흁풎] L[흁풎]

푴ퟏ 0.14 0.03

푴ퟐ 0.4 0.03

푴ퟑ 0.14 0.03

푴ퟒ 0.14 0.03

Table 31 - Dimensions of the transistors of the Flip Flop of the Driver.

Transistor W[흁풎] L[흁풎] Transistor W[흁풎] L[흁풎]

푴푷ퟏ 0.14 0.03 푴푷ퟒ 0.4 0.03

푴푵ퟏ 0.4 0.03 푴푵ퟒ 0.4 0.03

푴푷ퟐ 0.14 0.03 푴푷ퟓ 0.4 0.03

푴푵ퟐ 0.14 0.03 푴푵ퟓ 0.4 0.03

푴푷ퟑ 0.4 0.03 푴푷ퟔ 0.4 0.03

푴푵ퟑ 0.4 0.03 푴푵ퟔ 0.4 0.03

Table 32 - Dimensions of the transistors of the Local Decoder.

Local Decoder Transistor W[흁풎] L[흁풎] Transistor W[흁풎] L[흁풎]

푴푷ퟏ 2*2.6 0.03 푴푵ퟐ 1.3 0.03

푴푷ퟐ 2*2.6 0.03 푴푵ퟑ 1.3 0.03

푴푷ퟑ 1.3 0.03 푴푵ퟒ 1.3 0.03

푴푵ퟏ 1.3 0.03

Table 33 – Dimensions of the transistors of the Row and Column Decoders.

T1 T2 T3 Transistor W[흁풎] L[흁풎] Transistor W[흁풎] L[흁풎] Transistor W[흁풎] L[흁풎]

푴푷ퟏ 20*2.6 0.03 푴푷ퟏ 9*2.6 0.03 푴푷ퟏ 9*2.6 0.03

푴푷ퟐ 20*2.6 0.03 푴푷ퟐ 9*2.6 0.03 푴푷ퟐ 9*2.6 0.03

푴푷ퟑ 20*2.6 0.03 푴푵ퟏ 9*2.6 0.03 푴푷ퟑ 9*2.6 0.03

푴푵ퟏ 45*2.6 0.03 푴푵ퟐ 9*2.6 0.03 푴푵ퟏ 9*2.6 0.03

푴푵ퟐ 45*2.6 0.03 푴푵ퟐ 9*2.6 0.03

푴푵ퟑ 45*2.6 0.03 푴푵ퟑ 9*2.6 0.03

푴푵ퟒ 45*2.6 0.03 푴푵ퟒ 9*2.6 0.03

T4 T5 T7 Transistor W[흁풎] L[흁풎] Transistor W[흁풎] L[흁풎] Transistor W[흁풎] L[흁풎]

푴푷ퟏ 7*2.6 0.03 푴푷ퟏ 9*2.6 0.03 푴푷ퟏ 18*2.6 0.03

푴푵ퟏ 7*2.6 0.03 푴푷ퟐ 9*2.6 0.03 푴푷ퟐ 18*2.6 0.03

T6 푴푷ퟑ 9*2.6 0.03 푴푷ퟑ 18*2.6 0.03

Transistor W[흁풎] L[흁풎] 푴푷ퟒ 9*2.6 0.03 푴푵ퟏ 9*2.6 0.03

푴푷ퟏ 9*2.6 0.03 푴푵ퟏ 9*2.6 0.03 푴푵ퟐ 9*2.6 0.03

푴푷ퟐ 9*2.6 0.03 푴푵ퟐ 9*2.6 0.03 푴푵ퟑ 9*2.6 0.03

푴푵ퟏ 9*2.6 0.03 푴푵ퟑ 9*2.6 0.03

푴푵ퟐ 9*2.6 0.03

Table 34 - Dimensions of the transistors of the Latency Equalizer.

Transistor W[흁풎] L[흁풎]

푴푷ퟏ 2*2.6 0.03

푴푵ퟏ 2*2.6 0.03

푴푷ퟐ 2*2.6 0.03

푴푵ퟐ 2*2.6 0.03

푴푷ퟑ 2*2.6 0.03

푴푵ퟑ 2*2.6 0.03

푴푷ퟒ 2*2.6 0.03

푴푵ퟒ 2*2.6 0.03

Table 35 - Dimensions of the transistors of the Register.

Transistor W[흁풎] L[흁풎] Transistor W[흁풎] L[흁풎]

푴푷푹ퟏ 6*2.6 0.03 푴푷푹ퟓ 6*2.6 0.03

푴푵푹ퟏ 6*2.6 0.03 푴푵푹ퟓ 6*2.6 0.03

푴푷푹ퟐ 16*2.6 0.03 푴푷푹ퟔ 16*2.6 0.03

푴푵푹ퟐ 16*2.6 0.03 푴푵푹ퟔ 16*2.6 0.03

푴푷푹ퟑ 16*2.6 0.03 푴푷푹ퟕ 16*2.6 0.03

푴푵푹ퟑ 16*2.6 0.03 푴푵푹ퟕ 16*2.6 0.03

푴푷푹ퟒ 6*2.6 0.03

푴푵푹ퟒ 6*2.6 0.03

Table 36 - Dimensions of the transistors of the Clock Driver.

NAND Inverter 2 - 3x Inverter 4 - 20x Transistor W[흁풎] L[흁풎] Transistor W[흁풎] L[흁풎] Transistor W[흁풎] L[흁풎]

푴푷ퟏ 2*1.64 0.03 푴푷ퟏ 2*0.9 0.03 푴푷ퟏ 2*0.9 0.03

푴푷ퟐ 0.41 0.03 푴푵ퟏ 2*0.8 0.03 푴푵ퟏ 2*0.8 0.03

푴푵ퟏ 2.58 0.03 Inverter 3 - 8x Inverter 5 - 55x

푴푵ퟐ 4*2.58 0.03 Transistor W[흁풎] L[흁풎] Transistor W[흁풎] L[흁풎]

Inverter 1 - 1x 푴푷ퟏ 2*0.9 0.03 푴푷ퟏ 2*1.3 0.03

Transistor W[흁풎] L[흁풎] 푴푵ퟏ 2*0.8 0.03 푴푵ퟏ 2*1.2 0.03

푴푷ퟏ 2*0.9 0.03

푴푵ퟏ 2*0.8 0.03

Table 37 – Corners Description

# PMOS NMOS Bipolar Resistor Capacitor Supply Voltage Temperature (V) (ºC) 0 Typical Typical Typical Typical Typical 0.900 50 1 Slow Slow Slow Slow Slow 0.855 125 2 Slow Slow Slow Slow Slow 0.855 -40 3 Slow Slow Slow Slow Slow 1 125 4 Slow Slow Slow Slow Slow 1 -40 5 Fast Fast Fast Fast Fast 0.855 125 6 Fast Fast Fast Fast Fast 0.855 -40 7 Fast Fast Fast Fast Fast 1 125 8 Fast Fast Fast Fast Fast 1 -40 9 Fast Slow Fast Fast Fast 0.855 125 10 Fast Slow Fast Fast Fast 0.855 -40 11 Fast Slow Fast Fast Fast 1 125 12 Fast Slow Fast Fast Fast 1 -40 13 Slow Fast Slow Slow Slow 0.855 125 14 Slow Fast Slow Slow Slow 0.855 -40 15 Slow Fast Slow Slow Slow 1 125 16 Slow Fast Slow Slow Slow 1 -40

Table 38 - Dynamic Performance of the DAC considering the Layout of Latches, Switches, Cascode and Current Source transistors.

Corner # SFDR (dB) SNDR (dB) SNR (dB) THD (dB) |푽풐풖풕|풎á풙 (V) 0 47.4 40.1 40.4 -52.6 0.44 1 42.7 38.8 39.2 -49.9 0.43 2 43.8 38.9 38.9 -51.5 0.44 3 46.3 40.1 40.4 -51.4 0.46 4 47.8 39.9 40.1 -52.9 0.47 5 48.1 40.7 40.9 -54.2 0.43 6 49.5 40.6 40.8 -55.0 0.45 7 49.8 41.1 41.2 -55.3 0.47 8 49.7 40.8 40.9 -55.5 0.31 9 44.3 39.9 40.1 -51.0 0.43 10 46.9 39.3 39.7 -51.2 0.42 11 46.5 40.3 40.4 -53.2 0.45 12 49.4 40.7 40.9 -52.1 0.47 13 47.2 40.0 40.5 -52.6 0.37 14 45.5 39.2 39.2 -52.0 0.32 15 50.1 41.0 41.2 -52.6 0.41 16 49.7 40.6 40.9 -55.7 0.39

Table 39 - Dynamic Performance of the DAC considering the Current Source Block and the Biasing Circuit.

Corner # SFDR (dB) SNDR (dB) SNR (dB) THD (dB) |푽풐풖풕|풎á풙 (V) 0 48.1 40.4 40.6 -57.2 0.44 1 42.7 38.9 39.2 -49.5 0.46 2 44.9 39 39.3 -50.5 0.43 3 44.4 39.6 39.9 -51 0.48 4 47.3 39.8 39.9 -53.7 0.47 5 49.8 41.1 41.4 -52.9 0.34 6 48.4 40.3 40.5 -54.2 0.3 7 49.8 41.4 41.6 -55.3 0.4 8 49.7 40.7 40.9 -54.5 0.32 9 45.7 40 40.4 -51.1 0.43 10 47.4 39.5 39.7 -51.6 0.41 11 46.6 40.3 40.6 -52.4 0.46 12 49.2 40.8 41.1 -53.1 0.47 13 48.2 40.4 40.7 -52.6 0.38 14 46.1 39.6 39.9 -51.8 0.32 15 50 41 41.2 -53.7 0.41 16 45.4 38.4 38.5 -54.8 0.39

Table 40 - Dynamic Performance of the DAC considering the Layout of the Current Source Block, the Biasing Circuit and the Clock Driver.

Corner # SFDR (dB) SNDR (dB) SNR (dB) THD (dB) |푽풐풖풕|풎á풙 (V) 0 48.0 40.0 40.7 -48.0 0.43 1 42.1 38.2 38.9 -46.2 0.47 2 44.5 39.1 39.1 -48.1 0.44 3 43.9 39.1 39.7 -47.7 0.51 4 48.1 40.1 40.9 -48.1 0.48 5 49.0 40.7 41.4 -49.0 0.35 6 48.3 40.3 40.9 -49.0 0.28 7 49.9 41.1 41.7 -49.9 0.40 8 47.8 40.3 40.8 -49.7 0.31 9 44.4 39.1 40.0 -46.7 0.44 10 45.9 39.3 40.4 -45.9 0.40 11 46.5 39.9 40.6 -48.2 0.49 12 48.3 40.3 41.0 -48.3 0.43 13 47.9 40.2 40.9 -48.4 0.39 14 46.5 39.7 40.8 -46.5 0.31 15 49.2 40.6 41.2 -49.2 0.44 16 45.5 38.9 39.2 -50.1 0.39

Figure 68 - Spectrum of output voltage of the DAC for the circuit with the layout blocks for the typical corner.

Table 41 – Differences in the Dynamic Performance between the layout and schematic.

Corner # 횫 퐒퐅퐃퐑 (퐝퐁) 횫 퐒퐍퐃퐑 (퐝퐁) 횫 퐒퐍퐑 (퐝퐁) 횫 퐓퐇퐃 (퐝퐁) 횫 |퐕퐨퐮퐭|퐦á퐱 (V) 0 -0.2 0.2 0.7 23.3 -0.09 1 -2.5 -1.1 -0.7 16.9 -0.07 2 -2.1 -0.7 -0.4 14.6 -0.12 3 -5.0 -1.5 -1.0 24.7 -0.04 4 -1.3 -1.3 -0.9 20.6 -0.10 5 0.9 -0.1 0.3 19.3 -0.14 6 -1.3 -1.0 -0.7 17.2 -0.23 7 0.5 0.2 0.5 23.3 -0.17 8 -2.0 -0.8 -0.5 23.2 -0.24 9 -0.8 -0.6 -0.2 19.2 -0.06 10 -2.1 -1.6 -1.5 12.0 -0.13 11 -2.5 -0.9 -0.4 25.1 -0.05 12 0.4 -1.1 -0.7 23.4 -0.09 13 -1.2 -0.6 -0.1 18.6 -0.10 14 -2.4 -0.9 -0.7 12.6 -0.20 15 0.3 -0.3 0.1 23.1 -0.07 16 0.1 -1.1 -0.8 21.4 -0.14