BCM8706
®
XAUI™ TO SERIAL 10G BASE-LRM TRANSCEIVER
FEATURES SUMMARY OF BENEFITS
• Meets and exceeds industry standard • MDIO interface compliant to IEEE 802.3ae Clause 45 with extended • IEEE 802.3ae indirect address register access • IEEE802.3aq • Single reference clock input, enables use of low-cost 25-MHz crystal • High-performance mode supports 300m of MMF fiber. or 156.25-MHz oscillator.
• Low-power mode supports 220m of MMF, as specified in the 802.3aq • Integrated micro-controller, no external memory required standard. • Support for XENPAK/X2 3.0 and XPAK MSA Optical Module • Integrated AGC with a dynamic range of 60 mV–700 mV standards and the emerging SFP+ standard
• Multiple interface support • Simplifies manufacturability with integrated built-in self test (BIST) • 4 Lane XAUI™ (3.125 Gbps) and loopback modes on the 10-G serial and XAUI interfaces. • XFP/XFI • Programmable amplitude control on 10G serial transmitter • Standard I2C serial interface support for external E2 and XFP. • PMD - Serial 10.3125-Gbps CML • XAUI link synchronization/deskew
• Receive equalization on XAUI and 10G serial interfaces • XGXS 8B/10B error detection ENDEC
• Power dissipation: < 1.5W (Low-power mode) • PCS 64B/66B scrambler/descrambler
• Core Supply: 1.0V; I/O: 3.3V • Reference clock output for XFP module reference clock APPLICATIONS • Loss-of-signal detection
• Link activity indicator outputs • XENPAK, X2 Modules for LRM
• XAUI transmit pre-emphasis for transmission over backplanes • Direct attach to SFP+ modules • Network interface cards (NICs)
BCM8706 Functional Block Diagram
XAUI
OTX RS XGXS 10.3125 Media Gbps Access BCM8706 MAC Controller Interface MMF EDC ORX REFCLK 25M or 156.25M MDC MDIO IC2 Optical PMD
Management Interface E2 OVERVIEW
BCM8706
XAOP 8B/10B Serializer Encoder XAON 64/66B CDR and MMF EDC PDIP Synchronizer AGC Deserializer DSP Core PDIN
Descrambler Gearbox 3.125 Gbps XDOP Decoder Randomizer
8B/10B Elastic FIFO Serializer XDON Encoder 322.26M Gbps
312.5M 10.3125 8K ROM uC 156.25M CMU 8K RAM SPI SPI 25 MHz, 156.25 MHz REFCLKP RefClk REFCLKN Block 312.5M 312.5M
322.26M Sync. Detect Lane DLL and Lane Sync Alignment XAIP FIFO De-serializer 8B/10B 64/66B XAIN Decoder Synchronizer CMUR and PDOP Descrambler Serializer PDON
Decoder Gearbox 3.125 Elastic FIFO Gbps Sync. Detect Lane DLL and Lane Sync Alignment XDIP De-serializer 8B/10B FIFO XDIN Decoder
MDIO MDC Management and PRTAD[4:0] Control RSTB Interface OPRXLOS LASI OPTMPFLT XAUI BIST Generator Optics OPBIASFLT SDA I2C Serial PMDBISTGenerator Control SCL Interface XAUI BIST Checker and OPPWFLT PMDBISTChecker Status OPTXENB JTAG PRBS Genertor and Checker OPRSTB
BCM8706 Reference Design The BCM8706 incorporates a receive equalizer that supports Electronic PMD and XAUI clock recovery is performed on the device by Dispersion Compensation (EDC) over multimode fiber (MMF). The synchronizing directly to the respective incoming data streams. An EDC equalizer is designed for applications over MMF covering external 25-MHz or 156.25-MHz oscillator is required for the reference distances up to 220m of OM1, OM2, OM3 fiber as per the IEEE clock input. standard. The BCM8706 will be fully compliant with the IEEE802.3aq The BCM8706 Ethernet LRM PHY is a fully integrated SerDes (10.3125 standard. In enhanced performance mode, the BCM8706 is capable of Gbps) interface device performing the extension functions for a 10-GbE supporting up to 300m over OM1, OM2, and OM3 fiber. Reconciliation Sublayer (RS) interface. The XGXS, PCS, and PMA An onboard microcontroller implements the control algorithm for the functions include 8B/10B coding, 64B/66B coding, SerDes, Clock MMF EDC DSP Core. Multiplication Unit (CMU), and Clock and Data Recovery (CDR). On-chip clock synthesis is performed by the high-frequency low-jitter The BCM8706 is available in a 13 mm × 13 mm, 256-pin FBGA, RoHS phase-locked loops for the PMD and XAUI output retimers. Individual compliant package.
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8706-PB00-R 05/16/06