Aluminum Gallium Nitride / Gallium Nitride High Electron Mobility Transistor Fabrication and Characterization Examining Committee: Chair: Dr
ALUMINUM GALLIUM NITRIDE 1 GALLIUM NITRIDE HIGH ELECTRON MOBILITY TRANSISTOR FABRICATION AND CHARACTERIZATION
David W. DiSanto B.Sc. (Eng), Queen's University, 1995 M.Sc., University of British Columbia, 1997
THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY
In the Department of Physics
O David W. DiSanto 2005
SIMON FRASER UNIVERSITY
Fall 2005
All rights reserved, This work may not be reproduced in whole or in part, by photocopy or other means, without permission of the author. APPROVAL
Name: David W. DiSanto
Degree: Doctor of Philosophy (Physics)
Title of Thesis: Aluminum Gallium Nitride / Gallium Nitride High Electron Mobility Transistor Fabrication and Characterization Examining Committee: Chair: Dr. Karen L. Kavanagh Professor of Physics
Dr. Colombo R. Bolognesi Senior Supervisor Professor of PhysicsIEngineering Science
Dr. Simon P. Watkins Supervisor Professor of Physics
Dr. Michael L.W. Thewalt Supervisor Professor of Physics
Dr. David M. Broun Internal Examiner Assistant Professor of Physics
Dr. David L. Pulfrey External Examiner Professor of Electrical Engineering University of British Columbia
Date Approved: November 25,2005 SIMON FRASER ' ulvivmsinl Ibra ry
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Simon Fraser University Library Burnaby, BC, Canada ABSTRACT
In the last decade, All-,GaXN/GaNHigh Electron Mobility Transistors (HEMTs) have been intensively studied because their intrinsic electrical properties make them attractive for high power microwave device applications. Despite much progress, current slump continues to be a problem, limiting output power, reducing reliability, and complicating device modelling. In this work, a complete A~I-,G~,N/G~NHEMT fabrication procedure was developed, and electrical characteristics related to current slump, microwave modelling, and delay time analysis were explored.
Low resistance ohmic contacts were achieved, enabling high channel current densities. Schottky contacts were developed with a new ion implant isolation architecture, enabling gate leakage currents 2 to 4 orders of magnitude lower than typical results from the literature.
Through pulsed current-voltage measurements, the importance of bias stresses in the gate-source region was demonstrated for the first time. In contrast to the conventional "virtual gate" model, gate-source stresses were shown to be more important than gate- drain stresses when biased near threshold.
Slow slump transients were studied by passivating transistor surfaces with ultra- thin layers. These results excluded dielectric strain and electron injection reduction as viable passivation mechanisms. A novel model was proposed associating slow slump behaviour with trapping of many electrons at screw dislocation sites.
The effect of slump on RF properties was examined through microwave measurements by extracting the parasitic source and drain resistances without special biasing. Besides significantly improving the accuracy of small-signal modelling, we were able to show the bias dependence of parasitic resistances which confirmed the effect of source-side bias stressing.
The question of channel electron velocities in nitride transistors remains controversial. We determined an effective electron velocity of - 1.9 x 1 o7 cmls through two methods. We first extracted effective velocities through delay time analysis, and then through the small-signal model elements. To our knowledge, this was the first time an equivalent model extraction led to self-consistent electron velocity values for nitride transistors. Finally, our equivalent circuit model showed the correct interrelation between frequency response and access resistances. The cohesive picture of current slump, equivalent circuit model extraction, and delay time analysis gives a high degree of confidence in these results. ACKNOWLEDGEMENTS
I am indeed fortunate to have worked under the guidance of Prof. Colombo Bolognesi. His contagious enthusiasm, originality, and desire to succeed have helped me grow into a better scientist. His dedication to me and our work was instrumental in every successful endeavour of this project. Without doubt, completion of this work would not have been possible if not for his unwavering support through some very difficult times.
A number of people have contributed specifically to the nitride project. In particular I am grateful to Hassan Maher, with whom I did much work on wet etching. Thanks also to Alex Kwan who made some helpful changes to the PSmith software package. I am also thankful to Haifeng Sun for his work with me on many experiments during the last year.
Others at the S.F.U. Compound Semiconductor Device Laboratory have made more general contributions to my work. Thanks to Georg Soerensen for continually keeping the cleanroom running smoothly and help in all programming, software, and computer related issues. Martin Dvorak's original PSmith program made my life a lot easier and was an important part of my data analysis. In addition, Nick Tao, Hongang Liu, Yuping Zeng, Liguang Zheng, Jian Qing Wu, Selena Lam, Arpal Dosanjh and Nourredine Matine have all provided me with interesting discussions and ideas over the years. Their presence has made my life at work enjoyable and, besides being great co- workers, I count all of these people as friends.
Lastly, I would like to thank my incredible wife, Lori Ann, who's patience, love, and encouragement fuelled me daily. It is Lori Ann and my children, Emma, Isaac, and Nicolas who made everything worthwhile. In many respects, this thesis represents countless hours mortgaged from my family. Though it may take a lifetime, this is a debt I intend to repay with interest. TABLE OF CONTENTS
.. Approval ...... 11 ... Abstract ...... 111 Acknowledgements ...... v Table of Contents ...... vi List of Figures ...... ix List of Tables ...... xvi Chapter 1: Introduction ...... 1 1.1 Overview ...... 1 1.2 The Case for GaN ...... 2 1.3 Challenging Issues Presented by GaN ...... 5 1.3.1 Lack of Native Substrates ...... 5 1.3.2 Thermal Management ...... 6 1.3.3 Lack of Conventional Wet-Etchants...... 6 1.3.4 Current Slump & RF Dispersion ...... 7 1.3.5 Immaturity of Modelling ...... 8 1.4 Synopsis of Dissertation ...... 8 Chapter 2: Basic Theory of Operation...... 10 Overview ...... 10 FET Operation ...... 10 MESFET Operation ...... 11 HEMT Operation ...... 13 ...... 15 Polarisation and 2DEGs. .in All-,Ga,N/GaN Heterostructures Spontaneous Polarisation...... 15 Piezoelectric Polarisation ...... 16 Formation of the 2DEG ...... 17 Trapping in Semiconductor Materials ...... 20 Chapter 3: All-.GaXNIGaN HEMT Fabrication...... 23 3.1 Overview ...... -23 3.2 Device Layer Structure ...... 24 3.3 Schottky Contacts ...... 25 3.3.1 Schottky Contact Theory ...... 25 3.3.2 Schottky Contact Results ...... 26 3.3.3 Electron Beam Lithography of Schottky Gates ...... 29 Ohmic Contacts ...... 3 1 Ohmic Contact Theory ...... 32 Ohmic Contact Results ...... 33 Implant Isolation ...... 36 Implant Isolation Introduction ...... 36 Implantation Results ...... 36 Wet-Etching of All-,Ga,N/GaN HEMTs ...... 39 Wet-Etching Background ...... 39 Wet-Etching with Potassium Persulphate ...... 39 Etch Results on Al1.,GaXN/GaN HEMTs ...... 40 Ultimate Failure of PEC Wet-Etching ...... 42 Chapter 4: Current Slump and Pulsed Characterisation of All-,Ga,N/GaN HEMTs ...... 44 Introduction ...... -44 Pulsed I- V Measurements ...... 46 Virtual Gate Model of Current Slump ...... 46 Pulsed I- V Characteristics of AlI.,GaXN/GaN HEMTs ...... 48 Thin Surface Passivation Layers ...... 58 Trapping in Al1.,GaXN/GaN HEMTs ...... 59 Passivation of Slow Transients ...... 60 Summary...... 72 Chapter 5: High-Frequency Characterisation of Al1..GaXNIGaN HEMTs ...... 73 Introduction ...... -73 Microwave Measurements ...... 74 Typical Small-Signal Modelling of All., GaxN/GaN HEMTs ...... 76 Equivalent Circuit Diagram ...... -76 Extraction of Intrinsic Circuit Elements ...... 78 Extraction of Extrinsic Circuit Elements ...... 80 Equivalent Circuit Simulation ...... 83 Questions Surrounding Equivalent Circuit Results ...... 87 HotFET Extraction of the Source and Drain Resistance ...... 89 HotFET Extraction of the Source Resistance ...... 90 Hot Extraction of the Drain Resistance ...... 93 Determination of z for R, and Rd Extraction ...... 94 Hot Circuit Extraction Results ...... 97 Delay Time Analysis and Effective Velocity in All., GaxN/GaN HEMTs ...... -102 Delay Time Analysis Principles ...... 103 Delay Time Measurements of Wet-etched Devices: ColdFET Parasitics ...... 106 Delay Time Analysis of Implant Isolated Devices: Hot Parasitics ...... 111 Chapter 6: Summary and Future Work ...... 116 6.1 Summary...... 116 6.1.1 Fabrication ...... 116
vii 6.1.2 Source Side Current Slump ...... 117 6.1.3 Passivation ...... 117 6.1.4 Small-Signal Modelling ...... 118 6.2 Future Work ...... 119 6.2.1 Passivation ...... 119 6.2.2 Slump at Dislocations ...... 119 6.2.3 Schottky Contact Improvement ...... 120 6.2.4 Ohmic Contact Improvement ...... 120
... Vlll LIST OF FIGURES
Figure 1-1: Energy gap vs. lattice constant for most type IV and 111-V semiconductors...... 2
Figure 1-2: r-valley effective electron masses of various 111-V and 11-VI semiconductors. Data taken from [I]...... 3
Figure 1-3: Transistor I- V curve showing current slump in an All-,Ga,N-GaN HEMT fabricated at SFU's CSDL. Before (solid) and after (dashed) exposure to a slump bias. Current is normalised to gate width. V,, begins at +1 V and drops in 1 V increments. Slump bias exposure was Vds = 10 V, V,, = -8 V prior to measurement...... 7
Figure 2- 1: Schematic diagram of a MESFET with Vds > 0 and V,, < 0. Here x is the distance along the depletion region, L, is the gate length, a is the thickness of the channel layer, d(x) is the depletion region thickness, and b(x) is the thickness of the undepleted channel...... 11
Figure 2-2: (a) An idealised AlGaNiGaN heterostructure before junction is complete. (b) 2DEG formation after completion of the junction...... 13
Figure 2-3: Layer structure of a typical All-,GaXN/GaNHEMT. Vertical scales are greatly exaggerated. The GaN channel is Unintentionally Doped (UID). The All-,Ga,N barrier may be Si- doped, or may be undoped and rely on the polarisation fields to form the 2DEG...... 14
Figure 2-4: Transistor I- V characteristics of a typical All-,Ga,N/GaN HEMT fabricated in the SFU CSDL. Vgs begins at +1 V and drops in 1 V increments...... 15
Figure 2-5: Spontaneous polarisation vector of Ga-faced GaN in the wurtzite phase. From [40] ...... 16
Figure 2-6: Spontaneous and piezoelectric polarisation vectors in All-,GaxN and GaN...... 17 Figure 2-7: Final net polarisation induced charges at interfaces of All-,Ga,N/GaN heterojunction. Electric field in All-,Ga,N is indicated...... 17
Figure 2-8: Band diagram for All-,Ga,N/GaN HEMT as barrier thickness grows...... 19
Figure 2-9: Capture and emission of electrons from deep trap states...... 20
Figure 3- 1: Typical layer structure of an A1GaNIGa.N HEMT used in this dissertation...... 24
Figure 3-2: (a) Schottky contact prior to connection of metal and semiconductor. (b) After connection, significant conduction is possible only when the junction is forward-biased. When the semiconductor is heavily doped n-type the contact becomes ohmic because of tunnelling through the thin barrier...... 26
Figure 3-3: Reverse Schottky characteristics showing the very low leakage currents achievable in the A1l~xGaxN/GaNsystem. The black line is from a device fabricated using the CSDL implant isolation through the gate metal, the blue line is fiom Zhou et al. [64] and is typical of most HEMT results while the dashed red line is a MOSHFET result from Khan et al. [65]...... 28
Figure 3-4: Forward diode characteristic of an A1l~xGaxN/GaNHEMT. The dashed line is a fit to Equation 3-1 with n = 1.23...... 28
Figure 3-5: Photoresist exposure profile for electron beam lithography. The light dose defines the gate head while the heavy dose defines the gate foot. The profile after development is shown as the dashed line...... 29
Figure 3-6: Achievable electron beam T-gate sizes on bare GaN surface exposed using the CSDL JEOL 6400 scanning electron microscope and controlled by the Nanometre Pattern Generation System...... 30
Figure 3-7: Finished T-gate device with gate length L, - 0.2 pm. Source is the contact on the left, drain is on the right ...... 30
Figure 3-8: (a) Typical metal-semiconductor contact for 111-V materials resulting in a Schottky barrier. (b) Metal-semiconductor contact with a heavily doped cap layer resulting in a thin Schottky barrier through which electrons tunnel, leading to ohmic behaviour...... 32 Figure 3-9: I- V characteristics of an ohmic contact as-deposited (black), after annealing for 30 s at 800 OC (blue), and after a further 30 s anneal at 850 "C (red)...... 34
Figure 3-1 0: Typical post-annealing ohmic contact morphology...... 35
Figure 3- 11 : SRIM simulated implant isolation damage in Alo.3G~.7N/GaN (200 A I2 pm)...... 37
Figure 3-12: SRIM simulated damage for 200 keV He through NiIAu (40014000 A) into Alo.3Ga0,~NlGaN(200 &2 pm)...... 38
Figure 3-13: Transconductance of devices fabricated with gate deposition after implant (red) and gate deposition before implant (black) ...... 38
Figure 3-14: Finished PEC etched electron beam device...... 4 1
Figure 3-15: RF performance of a 0.15 pm PEC wet-etched device. Current gain (lh2112)is extrapolated to 0 dB forfT, Power gain (U) is extrapolated to 0 dB for fMAX...... 42
Figure 3-16: Poor PEC etch on high quality MOCVD grown All,GaxN/GaN layers. The dark flat region near the centre is the desired mesa top. Unetched material still remains around the mesa...... 43
Figure 4- 1: High-fi-equency dispersion demonstrated by the difference between AC (red) and DC (black) characteristics. V,, begins at 0 V and drops in 1 V increments...... 45
Figure 4-2: Illustration of the virtual gate effect. Occupied surface states partially deplete the channel in the gate-drain region...... 47
Figure 4-3 : Measurement cycle of the DiVA pulsed system. The system sits at the quiescent point Q and pulses around the I- V characteristic. V,, begins at 0 V and drops in 1 V increments...... 48
Figure 4-4: Comparison of conventional DC measurement (red) with pulsed I-V measurement (black). Pulsed measurements were made with a quiescent point of Vds= 0 V and V,, = 0 V. V,, begins at 0 V and drops in 1 V increments...... 50
Figure 4-5: Comparison of slumped Q = (10,-5) V (red) with unslumped Q = (0,O) V (black) pulsed I- V measurements. V,, begins at 0 V and drops in 1 V increments...... 5 1 Figure 4-6: Comparison of slumped Q = (10,-5) V (red) with unslumped Q = (0,O) V (black) pulsed I- V measurements under UV light exposure. Vgsbegins at 0 V and drops in 1 V increments...... 51
Figure 4-7: Demonstration of slump induced by various drain voltages. Vgs= 0 V for each line...... 53
Figure 4-8: Demonstration of slump induced by various gate voltages. Vgs= 0 V for each line...... 53
Figure 4-9: DC (red) and Q = (0,O) V pulsed I-V (black) characteristics for unstressed, non-passivated HEMT. Vgsbegins at 0 V and drops in 1 V increments...... 54
Figure 4-10: Complementary biasing of gate-drain and gate source regions. (a) Ql with Vgs= 0 V and Vds= 8 V.(b) Q2 with Vgs= -8 V and Vds=
Figure 4- 11 : Pulsed I- V characteristics of complementary biases. Vgsbegins at 0 V and drops in 1 V increments. Black: gate-drain stress: Ql = (8,O) V Red: gate drain and gate-source stress: Q2 = (0,-8) V ...... 56
Figure 4- 12: Pulsed I- V characteristics measured at Vgs= 0 V normalised to maximum unstressed drain current value...... 57
Figure 4- 13: Transistor I- V characteristics for a 1 x 100 pm2 as-fabricated transistor. Bias stressing induces a significant current slump (red) compared to ustressed (black). Vgsbegins at +1 V and drops in 1 V increments...... 6 1
Figure 4-14: Transistor I- V characteristics for a 1 x 100 pm2 transistor following a 10 min ozone surface treatment. Current slump is effectively passivated. The post-stress characteristic (red) shows little slump compared to the unstressed characteristic (black). Vgs begins at +1 V and drops in 1 V increments...... 62
Figure 4- 15: Slow current transients in as-fabricated transistors, compared with stable current levels in ozone-treated sample. Inset: Ozone treatment reduces the reverse gate leakage by one order of magnitude...... 63
Figure 4-1 6: Operation free of slow current slump after NiO passivation. The I- V characteristics after significant stress bias (red) display very little slump compared to the unstressed characteristics (black). Vgsbegins at +1 V and drops in 1 V increments...... 64
xii Figure 4- 17: Operation with little slow current slump after passivation with 5 A of Ni. The I- V characteristics after significant stress bias (red) display little slump compared to the unstressed characteristics (black). Vgs begins at +1 V and drops in 1 V increments ...... 65
Figure 4-1 8: Contact potential image of an All-,Ga,N/GaN heterostructure on Sic. Areas of low potential extend far around each dislocation. From Eguchi et aZ.[107]...... 67
Figure 4- 19: Contact potential passing over two dislocations (the BB' line in Figure 4-1 8) in an All-,Ga,N/GaN heterostructure. From Eguchi et aZ.[107] ...... 68
Figure 4-20: Comparison of modelled (red) and measured (black) potential profile at tip height around dislocation. Modelled potential has N, = 5000 electrons per dislocation. Note: modelled data is given a DC offset to overlay with Eguchi et aZ.'s result ...... 70
Figure 4-2 1: Schematic representation of a revised virtual gate model: trapped charges partially deplete the 2DEG around dislocations forcing current flow lines to percolate between depletion zones. This diagram assumes a dislocation density of 1o8 ~m-~...... 7 1
Figure 5- 1: RF performance of a 0.15 pm PEC wet-etched device. Current gain (lhz112)is extrapolated to 0 dB forfT, Power gain (U) is extrapolated to 0 dB forfMa...... 75
Figure 5-2 (a): HEMT and MESFET equivalent circuit schematic...... 77
Figure 5-2 (b): Cross-section of MESFET indicating physical origin of each circuit element. The intrinsic circuit is enclosed in dashed box...... 77
Figure 5-3: Extraction of Rs, Rd, and Rg using Miras-Legros method. Extracted values have weak dependencies on the degree of forward bias...... 83
Figure 5-4 (a): Transconductance (g,) and output conductance (gd,) frequency response extracted from the sample device...... 85
Figure 5-4 (b): Frequency response of extracted equivalent circuit capacitors (Cgs,Cgd, and Cds)...... 85
Figure 5-4 (c): Frequency response of extracted z value for sample device...... 86
Figure 5-4 (d): Frequency response of extracted R; value for sample device...... 86
... Xlll Figure 5-5: Smith chart demonstrating quality of fit for ColdFET extracted equivalent circuit. The modelled S22 is highlighted in red...... 87
Figure 5-6: Noisy source inductance extraction from hot Z-parameters using Equation 5-23. An assumed value of z = 1 ps is used here...... 91
Figure 5-7: Extraction of the source resistance from hot Z-parameters using Equation 5-24. An assumed value of z= 1 ps is used here...... 92
Figure 5-8: Extraction of the drain resistance fiom hot Z-parameters as in Equation 5-27. Rs = 34 R fiom Figure 5-7...... 94
Figure 5-9: Extraction procedure. flow. chart for hot determination of the entire equivalent circuit...... 96
Figure 5-10: Smith chart demonstrating quality of fit for HotFET extracted equivalent circuit (black). The ColdFET modelled S22 is overlaid in red for comparison. Notice the superior match in S22 for the HotFET result...... 99
Figure 5-1 1: HotFET extracted Rs and Rd as a hction of Vdswith Vgsheld constant at Vgs= -4.2 V...... -100
Figure 5-12: HotFET extracted Rs and Rd as a function of V,, with Vdsheld constant at Vds= 8 V...... 10 1
Figure 5- 13 : Idealised charging delay plot showing how extrapolation allows for determination of ZRC and qnt+ zd...... 104
Figure 5-14: Idealised drain delay plot demonstrating how extrapolating to Vch - - 0 yields zd and qnt+ z~c...... 105
Figure 5- 15 : Charging delay plot for a wet-etched device. Parasitic resistances were ColdFET extracted as Rs = 3 1 R and Rd = 72 R...... 107
Figure 5-16: Drain delay plot for a wet-etched device. Parasitic resistances were ColdFET extracted as Rs = 31 R and Rd = 72 R...... 107
Figure 5- 17: Delay times for wet-etched devices with different parasitic resistances. Extraction to Rs + Rd = 0 yields a true intrinsic delay time...... 108
Figure 5-18: Total delay time as a function of access resistance. The measured total delay time does not agree with Tasker's prediction (Equation 5-3 1) based on the extracted intrinsic circuit elements...... 110
xiv Figure 5-19: RC charging delay using intrinsicfT and fMAxwith Rs and Rd subtracted). R, and Rd were determined using HotFET method...... 1 12
Figure 5-20: Drain delay plot using intrinsic fT and fMAx (with R, and Rd subtracted). Rs and Rd were determined using the HotFET method. The lack of drain delay is very clear...... 113
Figure 5-2 1: Effective electron velocity under the gate as determined from delay time analysis. The resistances in these results were determined using the HotFET method...... 113
Figure 5-22: Comparison of the Tasker prediction with HotFET extracted data. The agreement is excellent contrary to the very poor agreement achieved from ColdFET extraction in Figure 5-18...... 115
Figure 6-1: Comparison of the Tasker prediction with HotFET extracted data (reproduced from Figure 5-22). The intercept illustrates the performance level that could be achieved through reduction of the contact resistance...... 12 1 LIST OF TABLES
Table 1-1: Properties of common semiconductors. Johnson's Figure-of-Merit (JFOM) is normalised to Si. Taken from [3-51...... 4
Table 5- 1: Extracted intrinsic circuit elements using ColdFET values of R, = 20Q Rs= 30Q andRd=48i2 ...... 84
Table 5-2: ColdFET extracted resistances after 15 minute application of stress biases. ColdFET measurements were done at Vds = 0 V, V,, =
Table 5-3: Intrinsic circuit elements using ColdFET values and "HotFET" extraction at operating bias. Pad inductances and capacitances were the same for both devices...... 98
xvi CHAPTER 1: INTRODUCTION
1. Overview
Microwave power devices are continuing to grow in importance as the demand for wireless mobile communication increases and pushes the limitations of current technology. The applications for high-power, high-speed devices include X-band (8-12 GHz) radar and millimetre-wave communication links for military applications. In addition, applications such as wireless internet access, digital television, and videophone services place increasing demands on bandwidth, thus requiring a new set of technologies. The market has been aggressively pushing for faster and higher power devices for the last decade.
Fabricating devices capable of delivering high power is important because it decreases the number of devices in a given application. This reduces material production costs, increases reliability, reduces losses in circuits, and eases impedance matching. The market for high-power devices has traditionally been dominated by silicon LDMOS (Laterally-Diffused Metal Oxide Semiconductor) and GaAs power devices. For most base-station applications LDMOS is the preferred technology due to its high gain, linearity, power carrying abilities, and above all, low cost. As with all silicon-based technologies, LDMOS has benefited from continual incremental improvements and has been able to keep up with market demands. However, there are inherent limitations to Si-based devices because of their poor electron transport properties compared to 111-V semiconductors. GaAs 0 r
InA s - b
3 4 5 6 7 Lattice Constant (A) Figure 1-1: Energy gap vs. lattice constant for most type IV and III-V semiconductors.
GaAs-based devices are well-suited to high-frequency operation because of their high electron mobility. However, despite having a relatively wide bandgap, GaAs devices lag behind LDMOS in terms of operating voltage. In addition, the low thermal conductivity of GaAs creates heat management challenges in high power applications. With the speed limitations of LDMOS coupled with the power handling restrictions inherent with GaAs-based devices there arises the need for material systems which can meet the simultaneous requirements of speed and power.
1.2 The Case for GaN
Figure 1-1 demonstrates that there is a whole class of materials which are, in principle, capable of delivering superior power and breakdown characteristics because of their wide bandgap. Their wide bandgap also allows these materials to operate at much higher temperatures before the intrinsic carrier concentration is high enough to destroy the ability of external voltages to control the charge density. GaN
0 0.5 1 1.5 2 2.5 3 3.5 4 Bandgap E (eV) g Figure 1-2: r-valley effective electron masses of various 111-V and 11-Yl semiconductors. Data taken from [I].
In semiconductors there is always a trade-off between speed and power because the bandgap and carrier effective masses are directly connected. Figure 1-2 demonstrates how the electron effective mass increases with bandgap in a number of 111-V and 11-VI materials. However, despite their wide bandgap, GaN and Sic have excellent electron transport properties. While the electron mobility of Sic and GaN is noticeably smaller than other semiconductors, their high saturated velocity still allows them to achieve high W performance levels. Their high electron saturated velocity, high breakdown voltage, wide bandgap, and relatively high thermal conductivity make these materials ideally suited for high-frequency power applications. Table 1- 1 contrasts the material parameters for major semiconductors. The ability to balance power and speed is most commonly expressed by combining the critical electric breakdown field and the saturated velocity as in Johnson's Figure-Of-Merit (JFOM) [2]. Table 1-1: Properties of common semiconductors. Johnson 's Figure-of-Merit (JFOM) is normalised to Si. Takenfrom 13-51.
Material E, (eV) '4 %at Eb K JFOM
InP JVVV
Diamond 5.45 2.7 1O.( 20 90
Because of their excellent electron transport properties the 111-nitrides and Sic have received the most interest for high-power, high-frequency device applications. Indeed, both materials systems have undergone significant development over the last decade [4, 6-81. Sic vastly outperforms GaAs and Si-based devices and has been able to achieve power densities of 5.2 ~lmm'at 3.5 GHz 191. On the other hand, field-plated All-,Ga,N/GaN High Electron Mobility Transistors (HEMTs) have achieved 32.2 Wlmm and 30.6 Wlmm at 4 and 8 GHz respectively1 [lo]. Even at high frequencies GaN-based devices have remarkable power carrying ability:Lee et al. have shown 5 Wlmm at 26 GHz [1 1] and 4.13 Wlmrn at 35 GHz [12]].
The above details show that despite success with Sic-based devices, the performance levels achievable with GaN are still significantly higher. In addition to having high figures of merit, when GaN is coupled with AlN and InN there is considerable leeway in bandgap engineering and the advantages inherent with heterostructures are readily realised. Most importantly, the All-,Ga,N/GaN heterostructure allows for the fabrication of HEMTs with Two Dimensional Electron Gas (2DEG) concentrations above 1013 cm-2 due to the very large conduction band discontinuity. It is for this reason that GaN-based devices are able to achieve such remarkable performance levels.
1.3 Challenging Issues Presented by GaN
1.3.1 Lack of Native Substrates
Presently, GaN layers are not grown on GaN substrates and typically show dislocation densities from 10' to 10'' ~m-~.Sapphire is the most common substrate in use but it suffers from poor thermal conductivity and very high lattice mismatch to GaN (14%). Sic substrates provide for smaller lattice mismatch (3%) and higher thermal conductivity but unit costs remain high at around $l/mm2 [13]. Others, such as Nitronex Corporation [14], have achieved some success using Si substrates allowing for low cost and high thermal conductivity [15]. It is also possible to grow low dislocation GaN on non-native substrates using epitaxial lateral overgrowth [16, 171 but this process leaves only a fraction of the material usable and is not widely used for RF device applications.
There has been research work into the manufacture of native substrates through high pressure growth [18, 191. While they have grown platelets with dislocation densities on the order of lo2 ~m-~,the achievable substrate sizes presently limit their use to research activities only. Growth of thick GaN layers on non-native substrates by Chemical Vapour Deposition (CVD) [20] and Hydride Vapour Phase Epitaxy (HVPE) [21] followed by backside removal to relieve strain also have promise for providing native substrates. However, these processes are still in the earliest stages of development and for the foreseeable future GaN-based devices will continue to be fabricated on highly dislocated material grown by heteroepitaxy.
1 Because transistor sizes vary from laboratory to laboratory it is common practice to normalise total power (in Watts) by the total gate width (in mm) so as to quote power densities per unit width in W/mm. 1.3.2 Thermal Management
Because of its low cost, GaN-based devices are most commonly grown on sapphire. However, in addition to having a poor lattice match with GaN, sapphire also has a very low thermal conductivity of 0.35 W/cm•‹K. Since the nitrides are typically used for power applications this creates significant thermal management issues. Flip-chip bonding [22, 231 has become a popular method for sinking unwanted heat but this process adds to the cost and complexity of device fabrication. Use of Sic substrates aids in shedding heat due to it's high thermal conductivity. Even so, the power levels achievable in GaN devices still make thermal management a very important consideration no matter which substrate is chosen.
1.3.3 Lack of Conventional Wet-Etchants
GaN and Al1,GaxN are highly ionic materials and form very strong chemical bonds. Despite an intensive search, there are no conventional wet-etches for use in the GaN system of devices. Fortunately, all 111-nitrides can effectively be etched using C12- based dry-etching techniques [24] such as Reactive Ion Etching (RIE) and ICP (Inductively Coupled Plasma) etching. However, a typical problem associated with dry- etching is the introduction of etch induced damage; this is a by-product of the ion bombardment associated with dry-etching. Etch induced damage is particularly troublesome in recess etching for gate deposition. Dry-etched recesses have been shown to lead to poor idealities and high leakage currents in Schottky contacts [25, 261. In spite of this, others have had success in using carefully designed, low damage, dry-etching for gate recessing in All-,Ga,N/GaN HEMTs [27, 281. Even so, low-damage dry-etches in GaN still cannot match the effectiveness of wet-etches in most conventional semiconductors. For this reason it is unusual to see All-,Ga,N/GaN HEMTs with heavily doped cap layers for ohmic contact formation as they require recess etching. Because of this, contact resistances in All-,Ga,N/GaN HEMTs continue to be problematically high. To overcome this limitation, some groups, including our own, have attempted photoelectrochemical (PEC) wet-etching which utilises UV light to aid in the etching procedure [29-321. This process has yielded some encouraging results in the past, but has been less successful as higher quality material has become available.
1.3.4 Current Slump & RF Dispersion
All-,Ga,N/GaN HEMTs suffer uniquely from so called "current slump" and "RF dispersion". Current slump is a general term referring to a distinct compression of the drain current characteristic after application of a significant operating bias as shown in Figure 1-3. RF dispersion is a specific aspect of current slump where the same drain current compression is exaggerated in AC measurements compared to DC. Current slump is a central limiting issue in the power performance of All-,Ga,N/GaN HEMTs and much work has been done studying the cause of this phenomenon and various ways to mitigate
5 10 15 Drain-Source Voltage V (V) ds
Figure 1-3: Transistor I-V cuwe showing current slump in an A11,GaXN-GaN HEMT fabricated at SFU's CSDL. Before (solid) and after (dashed) exposure to a slump bias. Current is normalised to gate width. V,, begins at +I V and drops in 1 V increments. Slump bias exposure was Vds= 10 V, VRs= -8 Vprior to measurement. its effects. Si3N4has become the standard passivation layer for All-,Ga,N/GaN HEMTs as it has been shown to reduce the deleterious effects of dispersion [33, 341. However, even with the use of Si3N4 passivation, the study and reduction of current slump is still a primary concern in GaN research.
1.3.5 Immaturity of Modelling
Modelling of semiconductor devices is critical in understanding factors which may affect their performance. This allows greater understanding of the underlying physics and aids optimisation in both materials growth and device fabrication. In addition, device modelling is critical in circuit design and lowers development costs by reducing the time and effort between design and fabrication of working prototypes. Despite a decade of intensive work, modelling of All-,Ga,N/GaN HEMTs has not reached full maturity. Monte-Carlo simulations are difficult because the material parameters are not all known. The piezo and polarisation effects (see Section 2.2) complicate the behaviour immensely. It is also difficult to get good results with circuit modelling, which is not surprising considering the problems outlined above. Modelling devices with significant heating is tricky, but adding the complication of carrier trapping from a wide variety of trap states [35] makes RF modelling a difficult task.
1.4 Synopsis of Dissertation
The present dissertation covers a wide spectrum of GaN research from basic fabrication to understanding of device physics. Chapter 2 outlines some basic HEMT device physics and discusses some of the properties on All-,Ga,N/GaN HEMTs which make them so interesting. Prior to beginning this thesis no work had been done on GaN materials in our group. As a result, all initial work on this project revolved around the most basic fabrication techniques: optimisation of ohmic and Schottky contacts and mesa isolation. While Chapter 3 discusses these fabrication steps, it does so in only a cursory way as these are merely the building blocks needed to build devices on which we can study the more interesting device effects. Chapter 4 presents results related to the problem of current slump. In particular, the effect of the source-side slump is presented. As well, novel thin passivation layers are shown to ameliorate slow transients in All-,Ga,N/GaN HEMTs and a new model explaining this slump effect is discussed. Chapter 5 discusses the bulk of the high-frequency results. Besides fabricating high performance devices we were able to extract the equivalent circuits for these devices using a novel method which allows subtraction of the parasitic resistances at each individual bias. This technique allows us to probe the effects of current slump on RF measurements. In addition, these results also allow us to determine the intrinsic device delay times leading to an accurate determination of the effective electron velocity under the gate. Finally, Chapter 6 provides a summary and possibilities for future research. CHAPTER 2: BASIC THEORY OF OPERATION
2.1 Overview
While the most widespread application of GaN-based devices is in the fabrication of blue and UV LEDs, the fabrication of microwave power devices has attracted much attention because of large potential markets. The world market for transistors is divided between bipolar and field effect transistors, depending on application. For GaN applications there has been research into both Heterojunction Bipolar Transistors (HBTs) and High Electron Mobility Transistors (HEMTs). State-of-the-art AlGaNIGaN HBTs generally still offer poor performance and typically have current gains of -10 [36, 371. Makimoto et al. have achieved promising results with GaNIInGaN DHBTs having current gains greater than 2000 [38] and breakdown voltages above 50V [39]. However, the progress made in HBTs has been very slow owing mostly to the poor acceptor activation in the base layer. As a result, most research has focussed on field effect transistors with both Metal Semiconductor Field Effect Transistors (MESFETs) and HEMTs receiving considerable attention. In this dissertation, the work has focussed on AII,GaxN/GaN HEMTs and this chapter will discuss the theory behind the operation of HEMTs, 2 Dimensional Electron Gas (2DEG) formation, and electron trapping.
2.2 FET Operation
The HEMT is a heterojunction device with superior performance to its homojunction counterpart, the MESFET. However, in order to understand HEMT operation it is very instructive to look at the MESFET as a starting point because the conceptual details of its behaviour are more easily grasped.
Since the electron velocity saturates in semiconductors, we can approximate the electron velocity as in Equation 2-2,
pE for E < Esat
'sat for E 2 Esat
Here Esatis the magnitude of the electric field at which electrons reach their saturation velocity vsat, p is the electron mobility. Once electrons have reached the saturated velocity there is also current saturation through the device. We can imagine that the electron has an overall effective velocity veff as it travels under the gate. This quantity obviously depends on the fraction of time the electrons spend accelerating to the saturated velocity. From Equation 2-1 we see that once the velocity saturates the open cross-section of the channel must remain constant for current continuity. We can then write the current in terms of an effective velocity and channel thickness,
We can also write this in terms of the charge per unit width under the gate Q,,
where L, is the gate length. We can then determine the transconductance of the device,
Here Cgs is the gate-source capacitance. gm is important because it is related to the transistor cut-off frequency fT (in the simplest approximation) as follows: To achieve highest powers and speeds requires simultaneously maximising the cut-off frequency, fT, and the drain current, Id. Maximising the current through the device implies increasing the channel conductivity as much as possible (Equation 2-1). This is typically accomplished through increased channel doping. However, high channel doping causes decreased mobility and effective velocity through impurity scattering. This effect compromises the high-frequency performance of the device (Equation 2-5). In this way, a device designer must trade-off between MESFET power performance, and bandwidth because the carrier density is closely related to the transport characteristics. While this kind of trade-off is typical in homojunction devices, it is possible to achieve high current density, high mobility, and high saturated velocity simultaneously with the use of a heterojunction channel. This provides the rationale for a HEMT structure.
2.1.2 HEMT Operation
The basic principles outlined in MESFET operation also apply to the operation of a HEMT. However, instead of carrying current in a thick channel, a HEMT relies on the formation of a two dimensional electron gas at the heterojunction interface. Figure 2-2 shows an idealised AlI,Ga,N/GaN heterojunction. In the most common HEMT structures, the wide badgap barrier is doped n-type while the narrow bandgap channel remains undoped. As a result, electrons diffuse from the wide badgap material into the
@7 Ecl 1 1 1 1 EFll - 111111 1-11 - EF lmc Ec2 -eEc
11111 -EF2
(4 (b) Figure 2-2: (a) An idealised AlGaN/GaN heterostructure before junction is complete. (b) 2DEG formation after completion of the junction. Source - Ohmic Gate - Schottky Drain - Ohmic
A11,GhN Barrier I
1 Buffer Layer
Semi-insulating Substrate
Figure 2-3: Layer structure of a typical All,GaxN/GaN HEMT. Vertical scales are greatly exaggerated. The GaN channel is UnintentionuIly Doped (UZD). The AI,,Ga,N barrier may be Si-doped, or may be undoped and rely on the polarisation fieCds to form the 2DEG.
narrow bandgap material to minimise their energy as in 2-2(a). This process continues until a balanced Fermi level is formed in the two materials and equilibrium is established. Because of the resulting electrostatics, a new triangular well forms on the narrow bandgap side of the heterojunction; it is here that the 2DEG forms as in Figure 2-2(b). In the above structure, a doped barrier provides electronsto the undoped channel, thus spatially separating the channel charge carriers from theirionised donors. In this manner, the heterostructure channel is capableof delivering high carrier concentration with high mobility as impurity scattering is minimised in the undoped channel. As an added advantage, surface scattering is also reduced by moving the current-carrying region below the barrier.
A typical A~I-,G~,N/G~NHEMT structure is shown in Figure 2-3. Electrons move from the source ohmic contact into the 2DEG channel formed in the unintentionally doped GaN. Electrons travel from thesource to the drain and the current is modulated by the intervening Schottky gate. Conceptually, the channel modulation in a HEMT differs from that of a MESFET in that it is not the channel cross-sectionthat is modulated by the 5 10 Drain-Source Voltage Vds (V) Figure 2-4: Transistor I-V characteristics of a typical Al1,GaxN/GaN HEMT fabricated in the SFU CSDL. Vgsbegins at +I V and drops in 1 V increments.
gate, but the electron concentration in the 2DEG. Figure 2-4 shows a typical transistor characteristic for a HEMT fabricated in our lab.
2.2 Polarisation and 2DEGs in All-,Ga,N/GaN Heterostructures
For most semiconductors the carriers in the 2DEG originate entirely from n-type bulk dopants within the barrier, but the situation is not so simple for the 111-nitrides. The All-,Ga,N/GaN material system has built-in polarisation fields which help induce 2DEG formation in an unique way. In fact, these polarisation fields are strong enough to allow for the formation of a 2DEG without any barrier doping at all [40].
2.2.1 Spontaneous Polarisation
A1-N and Ga-N bonds are highly ionic and each carries a strong dipole. For example, because the electronegativity of N is much higher than that of Ga, the electron Figure 2-5: Spontaneous polarisation vector of Ga-jaced GaN in the wurtzite phase. From [40]. wave function around the Ga-N pair is offset to the nitrogen side.The effect is even more exaggerated in the Al-N pair. This is a special feature of the 111-nitrides as the degree of spontaneous polarisation is more than five times greater than in most 111-V semiconductors [41]. Figure 2-5 shows GaN grown in the Ga-face orientation which is the norm for high performance All-,Ga,N/GaN heterostructures[42]. The c-axis polarisation vector points from the nitrogen to the gallium, as indicated, and creates an internal electric field pointing in the opposite direction, thisis referred to as "spontaneous polarisation". In an AII-,Ga,N/GaN HEMT both the GaN and All-,Ga,N layers have spontaneous polarisation vectors which point in thesame direction, from the N to the Ga(A1) towards the substrate (Figure2-6).
2.2.2 Piezoelectric Polarisation
The lattice constants a, and c, for GaN are slightly larger than those for AlN. As a result, thin All-,GaxN layers grown on GaN are tensile strained (theGaN is relaxed due to the thick buffer grown on the chosen substrate). In the nitride system the piezoelectric constants are more than tentimes greater than those typical in most111-V's [41] and this Figure 2-6: Spontaneous andpiezoelectric polarisation vectors inAII-xGaxN and GaN.
GaN
++++++++++++++++SOP3
Figure 2-7: Final net polarisation induced charges at interfaces of AII,GaxN/GaN lzeterojunction. Electric field in AII,GaxN is indicated. creates very large polarisations. In Ga-faced material under tensile strain the piezoelectric polarisation due to the deformation of the All-,Ga,N layer points parallel to the spontaneous polarisation vectors, e.g. towards the substrate in Figure 2-6. A thorough treatment calculating the size of the spontaneous and piezoelectric polarisations in the All-,Ga,N and GaN systems is given by Ambacher et al. [40].
2.2.3 Formation of the 2DEG
Figure 2-6 shows the polarisation vectors in the All-,Ga,N and underlying GaN. Within the All-,Ga,N layer there are two polarisation vectors Ppe,AIGaNand Psp,~IGa~for the piezoelectric and spontaneous polarisations respectively. The polarisation in the All-,Ga,N causes dipole charges to form at the borders of the material with a negative sheet charge at the surface and an equal positive sheet charge at the All-,Ga,N-GaN junction. The polarisation in the GaN layer causes a negative sheet charge at the All-,Ga,N-GaN junction and an equal positive sheet charge on the bottom surface. Since the total polarisation in the All-,Ga,N is larger, the overall result is a net positive sheet charge at the All-,Ga,N-GaN interface. The sheet density of the polarisation induced charges is given by Equation 2-6 [43],
where Dl and D2 are the electric displacement vectors, and P1 and P2 are the polarisation vectors on either side of an intersecting plane with normal vector n. Note that Equation 2- 6 is true because there are no external electric fields acting on the material. Figure 2-7 shows the final polarisation-induced charge densities at each interface as well as the direction of the electric field in the All-,Ga,N layer. Within the All-,GaxN layer the magnitude of the electric field is shown as follows:
Notice that the bottom GaN and All-,Ga,N-GaN interfaces are both positive while the charge density at the top All-,Ga,N interface is negative. The critical point to remember is that the interface sheet charges here are not free carriers. They are induced charges as in a typically polarised dielectric. However, it is the presence of these charges and the polarisation induced electric field in the All-,Ga,N which allows for 2DEG formation without barrier doping.
Before 2DEG formation, the electric field in the All-,Ga,N barrier is constant and does not change with thickness (assuming the thickness of the barrier is much less than its lateral extent). Therefore, an electron on the All-,Ga,N surface increases its electronic potential linearly with the All-,Ga,N thickness. This causes the bands in the All-,Ga,N layer to slant upwards towards the free surface due to the polarisation induced field. Figure 2-8 shows an idealised, undoped All-,Ga,N/GaN junction with two possible barrier thicknesses, tl and t2. As shown in Figure 2-8, as the thickness of the barrier is increased the valence band moves upwards towards the Fermi level. There are no donor GaN
Figure 2-8: Band diagramfor AIl,GaxN/GaN HEMT as barrier thickness grows. atoms in the barrier so at tl no 2DEG is formed. However, once a critical thickness t2 has been reached the valence band at the All-,GaXN surface rises past the Fermi level and begins to shed electrons. Once electrons are liberated from the valence band they move to the most energetically favourable location which is at the All-,GaXN/GaNjunction where they directly screen the positive polarisation-induced charges. The holes from the liberated electron-hole pairs stay at the All-,GaXN surface where they compensate for the negative polarisation induced charges there. Note that once free charge carriers begin to form on the surface and 2DEG they screen the polarisation induced charges and decrease the field. Therefore, with increasing thickness the 2DEG concentration asymptotically approaches the polarisation induced charge density [42,44].
Ibbetson et al. [44] points out that any donor-like surface states which exist within the forbidden gap will be emptied before the valence band. If the surface state density is higher than the polarisation induced charge density the valence band is not needed as a charge source. A number of groups have been able to fit their 2DEG data to single surface state energies varying from 1.42 to 1.74 eV below the conduction band [42, 44- 471. Of course, it is unlikely that only one surface state is at play, and many states with different energies and densities can contribute electrons to the 2DEG, but the concept remains the same [48].
The fundamental idea to draw from these considerations is that the semiconductor surface is an important source of charge carriers for the 2DEG. This is critical to All-,Ga,N/GaN HEMT performance because surfaces can be affected by many factors, such as growth conditions, passivation, chemical exposure, ambient exposure, and others. This effect suggests that the performance of All-,Ga,N/GaN HEMTs is strongly dependent on the type of surface passivation used. In fact, most practical devices show surface related non-idealities since they are, by definition, surface-controlled devices. Sometimes these can be difficult to control as the behaviour of surface states can be significantly affected by simple surface processes as shall be demonstrated in later chapters.
2.3 Trapping in Semiconductor Materials
AII,Ga,N/GaN HEMTs show strong current slump which is widely considered to be caused by electron trapping. Traps are very often surface related so it is not unreasonable to suppose they may contribute to current slump effects in All-,Ga,N/GaN HEMTs. Aside from surface effects, traps may also be formed by dislocations, point defects or impurities. A brief description of trap kinetics will aid in understanding the time dependence of current slump on trap energies.
E" Figure 2-9: Capture and emission of electronsfrom deep trap states. Consider a deep trap of energy ET which is below the conduction band of energy Ec as in Figure 2-9. An electron is captured by the trap when it transfers from the conduction band down to the trap state. Assuming that the capture rate is proportional to the density of electrons in the conduction band and to the number of empty trapping states, NT[I -AET)], we have the following 1491:
where Rc is the total capture rate, vth is the electron thermal velocity, On is the capture cross-section, n is the conduction band electron density, and NT[l -AET)] is the density of unoccupied trap states. HereAET) is the Fermi-Dirac function given as follows:
(2-9)
Once an electron is captured it can leave the capture state in two possible ways: 1) The electron can be emitted back to the conduction band after some characteristic time, in this case the deep state is said to be a trap. 2) The deep state can capture a hole which sends the electron down to the valence band, in this case the deep state is said to be a generatiodrecombination centre. We will focus on trapping states where the electron is sent back to the conduction band.
Since the conduction band is readily able to accept carriers the emission probability is governed by the number of filled traps. Therefore, the emission rate is
where Re is the total emission rate, N~ET)is the number of occupied trap states, and en is the emission probability per unit time. In equilibrium the emission and capture rates are equal which leads to a determination of the emission probability per unit time given by where ni is the intrinsic carrier concentration.
Equation 2-11 has consequences for trapping behaviour in All-,Ga,N/GaN HEMTs. If an initial bias creates an equilibrium occupation of trapping states then the recovery from this trapped behaviour is governed by the emission rate, en. As we see from Equation 2- 11, this emission process is thermally activated and strongly controlled by the energetic separation of the trapping state from the conduction band. We then see that fast recoveries of trapping states are associated with shallow traps with small values of (Ec- ET). On the other hand, the presence of slow trap recovery indicates that deeper trap states are involved. CHAPTER 3: All-,Ga,N/GaN HEMT FABRICATION
3.1 Overview
The work leading to this dissertation was the first effort with nitride-based semiconductors at the SFU Compound Semiconductor Device Laboratory. As a result, fabrication processes needed to be developed from the earliest stages, beginning with contact formation. An effective HEMT device requires at least three basic process steps.
1) Ohmic contacts with low contact resistance. Good edge acuity is also important to avoid shorting to the Schottky contacts.
2) Schottky contacts with high barrier height I low leakage current, forward diode idealities close to unity, and small gate length.
3) Inter-device isolation resulting in high sheet resistance to minimise conduction outside the device active regions.
In All-,Ga,N/GaN HEMTs a device passivation/encapsulation step is also common and this aspect of device fabrication is discussed separately in Chapter 4.
Through the course of this project we have been successful in fabricating devices which meet all of the above criteria and this chapter covers the basic concepts behind device fabrication utilised in this thesis. UID GaN I Low Temperature AIN Buffer
Substrate (Sapphire or Sic) I I
Figure 3-1: Typical layer structure of an AlGaN/GaN .HEMT used in this dissertation.
3.2 Device Layer Structure
The layer structures explored in this dissertation have consisted almost entirelyof simple AII-,G~,N/G~Nheterojunctions. Much work is being done on AIN barrier devices such as All-,Ga,N/AIN/GaN 1150-521 as well as compositeI channel structures such as A1l~,Ga,N/Inl-yGa,N[53, 541. While these structures may lead to improved performance, at present, the simple AII.,Ga,N/GaN HEMT is by far the dominant high performance nitride device.
Layers were provided by a number of sources such as the National Research Council of Canada, Emcore, RF Micro Devices, and Cornell University. Since this work relied on externally grown epitaxiallayers, without the opportunity to modify the sample design, our device design approach necessarily focussed on novel processing methods. Some layers were grown by MBE and others by MOCVD and as a result there is variation in the exact details of each structure such as mobility, barrier thickness, A1 content, 2DEG concentration, defect density,and surface roughness. Despite the layer-to- layer variations the vast majority of material properties fell within a narrow range typical of most samples. Figure 3-1 gives a typical HEMT structure for devices fabricated in our laboratory. Normally, layers had a 200-300 A thick Alo.3Gw.7Nbarrier on - 2 pm of unintentionally doped GaN. The barrier layer was typically undoped or Si-doped at - 10" cmm3.AS a result of polarisation doping, the resultant 2DEG in both cases normally had a sheet density of - 1x1013 cm-2and a mobility of 800-1000 cm2~-s.
3.3 Schottky Contacts
The gates of devices were formed by Schottky contacts, the quality of which greatly affected device performance. The critical elements at play for the Schottky contacts are diode idealities close to unity, low gate leakage current to allow for effective channel modulation, and small gate length to improve cut-off fkequency.
3.3.1 Schottlq Contact Theory
Ideally, fabrication of quality Schottky contacts on n-type material requires the use of metals with large work functions. Besides Om, the metal-semiconductor junction must be thermally stable and the gate metal must also be highly conductive to minimise the gate resistance. Figures 3-2(a) and (b) show the formation of a metal-semiconductor junction when the metal work function is higher than that of the n-type semiconductor,
@,, > Os. Electrons transfer fkom the semiconductor to the metal until the Fermi levels align as in Figure 3-2(b). The barrier for electron flow from the semiconductor to the metal is given as qVo = q(Om - Os) without an applied bias. This barrier decreases to q(Vo - V) for forward biasing, (positive polarity bias on the metal), and increases to q(Vo + V) for reverse biasing (negative on the metal). In the forward-biased case electrons flow easily into the metal whereas for reverse biases there is no electron transfer as the barrier is too high. Note that in either biasing case electron flow from the metal to the semiconductor is restricted by the barrier Om - X, where x is the electron affinity of the semiconductor. I
metal I semiconductor
Figure 3-2: (a) Schottky contact prior to connection ofmetal and semiconductor.(b) After connection, significant conduction is possible onlywhen the junction isforward- biased When the semiconductor is heavily doped n-typetlze contact becomes olzmic because of tunnelling tlzrouglz tlze thin barrier.
3.3.2 Schottky Contact Results
The most common Schottky metal used on GaN-based HEMTs is nickel. Others have achieved good results with Pd [55, 561 and Pt [56-581, indeed we have also achieved excellent performance with Pt-based gates [30, 591. However, even though Ni (5.35 eV) [60] has a smaller work function than Pt (5.65 eV) [60], we ultimately settled on Ni- based gates to improve yield and reliability as our Pt gate electrodes often suffered from poor adhesion. Others have had the same difficulty with Pt-based Schottky metals [61, 621.
The Schottky gate metallisations for our samples were Ni-Au bilayers of thickness 250 and 4500 A respectively. The underlying Ni layer acts as the Schottky metal while the thick Au helps to reduce the parasitic gate resistance. The contacts were un-annealed and achieved very good leakage characteristics. Figure 3-3 shows the reverse gate leakage between the Schottky gate and the source ohmic contact and demonstrates the outstanding reverse leakage characteristics of which GaN-based devices are capable. The Schottky reverse leakage current of the gate-source diode remains only -10'~ mA/mm for a reverse bias of -20 V. Indeed, we have measured devices to -100 V
(maximum of our machinery) with leakage currents of only 3 x mA/mm. This is still far from reaching breakdown current densities2. Leakage current results for our devices usually range from to 10" mA/mm while results of 10" mA/m are considered disappointing using our implant isolation method (see Section 3.4). The reverse leakage current for a HEMT processed using conventional dry-etching is shown in blue and
allows 1 mA/m at Vgs= -20 V. This result is typical or even better than those of most groups. The dashed red line in Figure 3-3 shows the leakage current for an All-,GaxN/GaN Metal Oxide Semiconductor Heterostructure Field Effect Transistor (MOSHFET) fabricated with a Si02 layer between the gate metal and semiconductor to reduce leakage currents. Our conventional HEMT is able to achieve leakage currents similar to the MOSHFET but without the degradation of transconductance associated with the increased gate to channel distance. We attribute our low leakage currents to our implant isolation technique outlined in Section 3.5.
Figure 3-4 shows the forward diode characteristics for a Ni/Au Schottky gate on an All-,GaXN/GaNHEMT. The current in a Schottky diode follows the relationship 1631
where V is the applied voltage, k is Boltzmann's constant, T is the temperature, I. is the reverse saturation current, and n is the ideality factor. For HEMT structures the ideality diverges from unity and its value is a good indication of the quality of the metal- semiconductor interface. We have found that idealities of 5 1.4 indicate a Schottky junction of good quality. The dashed line in Figure 3-4 fits to Equation 3-1 with an ideality of 1.23 and I, = 6.6 x Ncm2. Note that the divergence at high voltage is due to resistance in series with the diode.
Reverse breakdown is normally defined as the voltage at which the leakage current reaches 1 mA/mm.
27 Gate-SourceVoltageb' (V) gr
Figure 3-3: Reverse Schottky characteristics showing the very low leakage currents achievable in the AII,GuxN/GaN system Tlze black heis from a device fabricated using the CSDL implant isolation througlz the gate medal, the blue line is from Zhou et al. [64] and is typical of most HEMT results wlzile the dashed red line is a MOSHFET result from Khan et al. [65].
I .5 2.25
Gate-SourceVoltage I' (V) 2s Figure 3-4: Forward diode clzaracteristic of an All,GaxN/GaN HEMT. The dashed line isafit to Equation 3-1 with n = 1.23. Heavy Light Dose Dose
I PMMA
Figure 3-5: Photoresist exposureprofile for electron beam lithography. Tlze light dose defines tlze gate head while the heavy dose defines tlze gate foot. Tlze profile after development is shown as the dashed he.
3.3.3 Electron Beam Lithography of Schottky Gates
As shown in equation 2-5, decreasing the gate length reduces the transit time under the gate and is critical for development of high-frequency devices. Contact optical lithography employed in our laboratory can typically produce gate lengths down to 0.7 pm. In this dissertation we chose to probe smaller, high performance devices for the bulk of the measurements. In order to fabricate devices of 0.25 pm and below, we utilised electron beam (e-beam) lithography for gate definition.
A tri-layer PMMA~/PMGI~PMMAelectron beam resist process was developed which allows independent control of the size of the gate foot and gate head. This is done by utilising different doses and developers of different aggressiveness for each layer. The size of the gate head is defined by the top PMMA layer while the size of the foot is defined by the bottom PMMA layer. The intermediate PMGI layer provides the necessary undercut for lift-off.
' PMMA:polymethyl methacrylate 4 PMGI:Polymethylglutarimide 5 6 Foot Dose (nCIcm) Figure 3-6: Achievable electron beam T-gate sizeson bare GaN surface exposed using the CSDL JEOL 6400 scanning electron microscopeand controlled by tlze Nanometre Pattern Generation System.
Figure 3-7: Finished T-gate device with gate length Lg - 0.2 ym. Source is tlze contact on the left, drain is on tlze right. There is a compromise to be made between foot size and device yield for each process. Figure 3-6 demonstrates devices of 0.1 pm can be fabricated on planar material. However, close to an ohmic contact the photoresist is thicker so the gates tend to be larger, with lower yield in that vicinity. In order to account for the reduction in yield due to non-planarity near ohmic contacts we chose a foot dose of 4 nC/cm and were able to achieve gate lengths of - 0.2 pm with yields approaching 100 %. A finished e-beam T- gate is shown in Figure 3-7.
3.4 Ohmic Contacts
Ohmic contacts allow current to pass into and out of the underlying semiconductor with ease. Formation of ohmic contacts with low resistivity is critical for optimal device performance. As described in Chapter 2.1.1, the cut-off frequency of a FET is strongly determined by the transconductance, gm,of the device.
The transconductance in Equation 3-3 is the extrinsic transconductance, that is, the overall transconductance offered by the device, including the parasitic ohmic contacts. The transconductance, and thus fT, in 3-3 can be increased by reducing the resistivity of the ohmic contacts.
Equation 3-4 shows how the extrinsic transconductance is related to the intrinsic transconductance gmo.The value of gmois determined by the layer quality and basic gate geometry and represents the maximum transconductance value that is attainable for the device. R,, the source resistance, is the resistance between the top of the source ohmic contact, through the semiconductor, to the gate edge. Equation 3-4 expresses how the source resistance is a parasitic circuit element and the reduction of these parasitic elements results in improved device performance. t--* heavily doped
Figure 3-8: (a) Typical metal-semiconductorcontact,for 111- V materials resulting in a Schottky barrier. (b) Metal-semiconductor contactwith a heavily doped cap layer resulting in a thin Schottky barrier throughwlziclz electrons tunnel, leading to ohmic belzaviour.
3.4.1 Ohmic Contact Theory
Formation of a good ohmic contact ideally requires choosing a metal with a very small work function. Figure 3-8 (a) shows a metal-semiconductor junction where the metal work function, gornis greater than the semiconductorwork function, gos. This is typical of 111-V materials and is a Schottky contact as deposited as described earlier. In order to achieve ohmic behaviour the most common technique is to use a heavily doped cap layer directly underneath the ohmic metal. While the barrier height is still q(om-~), the depletion region thickness is very small and electrons readily tunnel into the semiconductor leadingto ohmic behaviour. If it is not possible to utilise a heavily doped cap the junction will have a barrier to electron flow. In this case, the barrier height is reduced by minimising the metal work function (see Section 3.2 on Schottky contacts). For this reason, metals with lowwork functions tend to imke the best ohmic contacts and ohmics on GaN-based materials are no exception. Other considerationsmay also figure in the selection of ohmic metals such as the need for high conductivity and stability of the metal - semiconductor contact. 3.4.2 Ohmic Contact Results
The usual contact scheme in All-,Ga,N/GaN HEMT structures typically utilises a bi-layer of Ti and A1 as contact metals because of their low work functions (4.33 and 4.28 eV respectively) [60]. Auger [66, 671 and XPS [67] measurements of TiIA1 contacts indicate that true ohmic behaviour begins when annealing allows the A1 to diffuse through the Ti to the underlying semiconductor. While it may seem that A1 alone would be sufficient to provide ohmic behaviour, the contacts are greatly improved by the presence of Ti. TEM [68, 691 measurements show that upon annealing the Ti interacts with the semiconductor surface to form TiN. This reaction consumes nitrogen atoms leaving nitrogen vacancies which act as donors in the semiconductor [70, 711 making the barrier thinner and easier to tunnel through. In addition, TiN fortunately has a very low work function (3.74 eV) [68].
The most common ohmic metallisation in use today utilises Ti/Al/Ni/Au [72, 731. In this scheme the TiIA1 bilayer creates the ohmic contact while the Ni supposedly separates the Au from the ~1~.However, auger depth profiling of Ti/Al/Ni/Au ohmic contacts in our laboratory showed that the Ni cannot prevent intermixing of the A1 and Au and the exact role of the Ni layer is still under investigation.
In this work we have typically used Ti/Al/Au (600/1000/500 A) [74] ohmic contacts. These contacts were Schottky-like on deposition, and annealing was necessary for ohmic behaviour. Figure 3-9 shows I-V characteristics of an ohmic during a typical annealing process. Note the transition from Schottky-like behaviour to linear, low resistance ohmic contacts. Since duration and temperature of ohmic annealing depended on the characteristics of each layer, a new ohmic optimisation would be required for all new structures. Typically, our annealing results indicated optimal temperatures between 800 and 850 "C for 60 s were suitable for most structures. In light of this, our typical procedure used rapid thermal annealing in pure N2 for 30 s at 800 "C followed by another 30 s at 850 "C. We have found this recipe reliably yields good results on a wide variety of layer structures.
5 Mixing of Au and A1 can lead to "purple plague", a highly resistive alloy.
3 3 -
7 800C 30s -----850C 30s
11 1 11111111111l11111~
-6 - 4 -2 0 2 4 Voltage (V)
Figure 3-9: I-V characteristics of an ohmic contact as-deposited (black), after annealing for 30 s at 800 OC (blue), and after a furtlze,~30 s anneal at 850 OC (dashed red).
Contact resistances were determinedusing the ,transmissionline method (TLM) method with circular contacts. A thorough treatmentof circular TLM structures can be found in Williams [75]. The Ti/Al/Au ohmic contact scheme utilised in this dissertation typically yielded contact resistances of R,-0.5-0.75 R-mm and specific contact resistivities of r, - 1x lo-' R-cm2.
An additional advantage to the ohmic contact scheme employed in this research is that the Ti/Al/Au is a relatively thin metallisation. At 2100 A the Ti/Al/Au ohmic metallisation is approximately halfthe thickness of most Ti/Al/Ni/Au schemes. This is an advantage when the Schottky gate is formed as the thin ohmic contact maximises the planarity of the surface and minimisesthe disturbance to the Schottky-level resist. This is particularly important for gates with close spacing to the ohmic contacts. Lastly, the Ti/Al/Au ohmics we employ yielded excellent edge acuity. Some Ti/Al/Ni/Au contact schemes we tested showed bleeding of the ohmic metal into the active region between contacts upon high temperature annealing. In addition, the edge roughness of the Ti/Al/Ni/Au ohmics was greater than the Ti/Al/Au. Both of these effects could result in a short between ohmic and Schottky making it difficult to fabricate gates with small spacing between contacts.This difficulty was minimised with the Ti/Al/Au scheme. A finished circular TLM structure is shown in Figure 3-10 as an example of typical ohmic contact morphology.
Figure 3-10: Typical post-annealing olzmic contact mo,~plzology. 3.5 Implant Isolation
3.5.1 Implant Isolation Introduction
Conventional isolation in GaN processing is done by dry-etching techniques [24, 76, 771, but our laboratory is not equipped for this and an ion implant isolation procedure was instead developed. Ion implant isolation is an attractive process because surface planarity is maintained and this technique has been used by a number of other groups in All-,Ga,N/GaN HEMT processing [78-811. In this process, the semiconductor is selectively bombarded by energetic ions. These ions cause considerable damage to the crystal structure of the semiconductor and create high, deep-level state densities, rendering the semiconductor insulating. The active areas of each device are protected with a thick mask, in our case a photoresist bilayer of PMGI / ~~52146.
3.5.2 Implantation Results
Since All-,Ga,N/GaN HEMTs are highly surface sensitive devices, we endeavoured to fabricate the gate as early as possible into the process run to avoid surface contamination to the most critical areas. To this end, we developed an implantation process which is done after gate deposition. This is opposite to conventional implantation procedures which usually reserve gate deposition until after isolation. Gate fabrication prior to isolation means that the implant energies must be carefully chosen to provide the necessary damage after travelling through the gate metal outside of the active region. In order to accomplish this, we simulated ion implantation into AII,GaxN/GaN HEMTs using the SRIM (Stopping Ranges of Ions in Matter) program [82]. We finally determined that a triple implant consisting of phosphorus (75 keV) and helium (50 and 200 keV) would create suitable damage at all required thicknesses. Figure 3-1 1 shows the resultant vacancy density of this implant schedule on bare Alo.3Gao.7N/GaN,while Figure 3-12 shows the damage levels created in the semiconductor after passing through the gate
6 AZ5214 is an industry standard photoresist based on propylene glycol and 1-methyl-2-pyrrolidone.
36 metal. The fluence schedule needed to achieve these resultswas as follows, P (75 keV) =
1.OX 10'?cm2, He (50 keV) = 3.5~10'~/cm~, He (200 keV) = 6.0x10'~/cm~.
Very effective isolation is achieved with this implant techniqueand exposed material is rendered non-conducting with sheet resistances typicallyin the range of 10'~-10'~Q/0. In addition, isolation after gate deposition improves deviceperformance. Figure 3-13 demonstrates the improvement in transconductance achieved by implant isolation through the gate metal compared to a conventional implant prior to gate deposition. Our gate leakage currents are also smaller than thosetypically achieved by other groups and we believe this approach is responsible forour superior results.
P : 75 keV - He: 50 keV - He:200 keV fg\,-Il-Total Damage i \, \ \ \ \ 1111111111~111i,
0 2000 4000 6000 8000 1 lo4 1.2 lo4
Depth into Seniiconductor (A) Figure 3-11: SRZM simulated implant isolation damage in AL'~.~G~~.~N/G~N(200 A /2
P)* 4000 6000 8000 Depth into Semiconductor (A) Figure 3-12: SRIM simulated damagefor 200 keV He through NYAu (~OO/~OOOA) into Alo.3Gao.,N/GaN (200 &2 p).
Gate After Implant --- Gate Before Implant
- 1 0
Gate-Source Voltage V (V) 8" Figure 3-13: Transconductanceof devices fabricated with gate deposition after implant (red) and gate deposition before implant (black). 3.6 Wet-Etching of All-,Ga,N/GaN HEMTs
Wet-etching is an important technique for most semiconductor manufacturing processes. This is especially true for the formation of gate recesses where the ion bombardment damage associated with dry-etching is detrimental to device performance. Despite the advantages of wet-etching it is seldom used in processing of the III-nitrides. The lack of natural wet-etches makes the use of dry-etching almost universal. However, a number of groups, including our own, have attempted to fabricate devices using novel wet approaches.
3.6.1 Wet-Etching Background
Several groups have searched for conventional wet-etchants for GaN-based devices but have come up empty handed 1831. In light of this, a number of groups began experimenting with etching techniques which are enhanced by the introduction of laser light 183, 841 or UV-light 183, 851. The technique used most successfully in GaN processing has been PhotoElectroChemical (PEC) etching. In PEC etching the sample becomes part of an electrochemical cell and is etched under illumination from an energetic source, all while immersed in a corrosive solution. For this technique to be successful, electron-hole pairs must be formed in the semiconductor which aid in the formation of gallium oxides that can be etched. Youtsey et al. 1851 created a successful apparatus where GaN was connected to a Pt wire through a Ni washer; this system required no external bias. With UV light exposure they were able to smoothly etch GaN in KOH. Most etching techniques are a variation of this method.
3.6.2 Wet-Etching with Potassium Persulphate
Etching of GaN requires the formation and subsequent etching of gallium oxides, usually in KOH. It would then be natural to attempt to mix a strong oxidant with KOH in order to etch the continually forming oxide layers. The use of potassium persulphate (K2S2O8)as the active oxidant was first suggested by Bardwell et al. [29] and was also utilised in the work described in this dissertation.
A proposed etching mechanism for this etch chemistry of KOH + K2S2O8+ UV is as follows [86]:
The purpose of the UV light is to create holes which enhance the formation of the gallium oxide, Ga203 (step 1). The etch reaction occurs between KOH and gallium oxide as indicated in step 2. Once the holes are consumed we find there is an excess of electrons in the semiconductor. Eventually, any new holes created by the UV light quickly recombine with the oversupply of electrons and further etching is significantly reduced. It is the presence of the K2S2O8which enables the excess electrons to be consumed (step 3). In our work, we found that the use of K2S2O8 alone is not sufficient to allow for usable etch rates. We also had to have the sample in contact with a platinum electrode to aid the oxidation reaction and enable quick etching of the GaN.
3.6.3 Etch Results on All-,Ga,N/GaN HEMTs.
While the semiconductor could indeed be etched in a solution of KOH + K2S2O8+ UV it became clear that the etch rate was strongly affected by the proximity to the Pt electrode. Material closest to the electrode was etched rapidly while areas on the opposite side of the wafer were only partially etched. This is easily understood because as the material etches towards the channel, the resistance to the Pt electrode increases. Ultimately, the regions farthest from the electrode are connected by such a large resistance that the etch rate is negatively affected. In order to overcome the high access resistance to the electrode, Pt was evaporated onto the active regions of the sample. This allowed each device to have an individual local Pt electrode and etching would take place localised around the mesa region. Following PEC mesa etching the Pt electrode was removed in a solution of HC1:HN03:H20 (7:8:1) at 100 "C. Ohmic and Schottky level fabrication then proceeded as discussed earlier. Using this technique we were able 1:o fabricate some of the only wet- etched processed HEMTs on All-,Ga,N/GaN heterostructures. Figure 3-14 shows a completed PEC wet-etched device.
Finished devices had excellent electrical characteristics. DC results had high current density (1 050 mA/mm) and transconductance (2 10 mS/mm). Figure 3- 15 shows RF results with cut-off frequencies of fT - 70 GHz and fblAx - 90 GHz for a gate length of 0.15 pm. A survey of current literature indicates that this result remains the record for wet-etched device technologies.
Figure 3-14: Finished PEC etched electron beam device. Frequency(GHz) Figure 3-15: RF performance of a 0.15 pm PEC wet-etched device. Current gain flh211') is extrapolatedto 0 dBfor f~,Power gain (U) is extrapolated to 0 dB for fMm.
3.6.4 Ultimate Failure of PEC Wet-Etching
With high quality DC and RF results, the PEC wet-etching process outlined above seemed a strong candidate for wide-spread use. The process was easily controlled, simple, and suitable for batch processing. However, as the quality of the received epilayers improved, the etch process became less effective. In particular, the etch depth was highly non-uniform. Figure 3-16 shows the normal PEC etch process with higher quality All-,Ga,N/GaN material. Careful study of the etch process at it progressed indicated that etching initialised at defects in the All-,Ga,N barrier. Once penetration of the All,Ga,N occurred, the underlying GaN etched preferentially at that locale resulting in the extremely rough morphology illustrated in Figure 3-16. Because of worsening difficulties in the etch process due to improved material quality, the PEC wet-etch isolation process was discontinued in favour of ion implantation. figure 3-1 6: Poor PEC etch on high quality MOCVD grown AII,Ga,N/GaN layers. The dark flat region near the centre is the desired mesa top. Unetched material still remains around the mesa. CHAPTER 4: CURRENT SLUMP AND PULSED CHARACTERISATION OF All_,Ga,N/GaN HEMTS
4.1 Introduction
While the power performance of All,Ga,N/GaN HEMTs has improved steadily, RF devices based on this technology are not yet widely commercially available. The power handling capabilities of AlI,GaXN/GaN HEMTs, although impressive, have not yet reached their maximum potential. As well, reliability of GaN-based devices has been very poor. Presently, the primary issue affecting output power and reliability is the presence of "RF dispersion" and "current slump". In particular these effects are most important in limiting the RF power performance under large signal operation.
RF dispersion is a specific term which refers to the frequency variation of performance when compared to DC measurements [87]. We show low frequency example of this effect in Figure 4-1 where the DC characteristics differ markedly from the AC ones. In this case, the AC data was measured with an analog Tektronix curve tracer scanning the I-V curve at 60 Hz.
Current slump on the other hand is a more general term describing decreased output current after the application of a significant bias to the device. This is more general because it refers to the behaviour of very fast and slow transients in the recovery of drain current after bias changes. Fast transients are often demonstrated by gate and drain lag measurements [88]. In these measurements fast current recovery transients are measured which usually have delay times in the microsecond to nanosecond regime. Slow transients on the other hand can demonstrate delay times of tens of seconds. 0 1 2 3 4 5 6 7 8 Drain-SourceVoltage I' (V) ds
Figure 4-1: High-frequency dispersion demonstrated by the difference between AC (red) and DC (black) characteristics. V,, begins at 0 V and drops in 1 V increments.
RF dispersion can be thought of as a particular manifestation of current slump. The current response delays demonstratedby gate and drain lag measurements showthat current compression in high-frequency dispersion occurs because the output current simply cannot follow the rapidly changing applied bias. Henceforth, we will discuss all detrimental effects in terms of current slump only.
It is widely accepted that current slump isprinlarily caused by the deleterious effects of surface states. In particular, charge trapping by these states, leading to channel depletion, is thought to cause decreased drain currents [89]. Thus far, current slump is primarily mitigated by the deposition of passivation layers, with Si3N4 as the most effective presently in use. However, the mechanism by which passivation reduces current slump is still an area of ongoing research. The advantages inherent to GaN-based devices are most pronounced at high frequency, voltage, and power. It is in these regimes that current slump is most severe and any degradation of performance in these area limits the usefulness of these devices. As a result, understanding current slump and passivation is critically important to the transition of All-,Ga,N/GaN HEMTs from the research to commercial environment. In this chapter we address some questions pertaining to current slump and passivation. Current slump in All-,Ga,N/GaN HEMTs is studied to determine where slump occurs in the device. We show for the first time that the source region can induce a significant slump. In addition, we use very thin passivation layers to demonstrate a novel slump mechanism, and develop a new picture of surface charge distribution for the "virtual gate" model of slump.
4.2 Pulsed I-V Measurements
Pulsed I- V measurements are ideal for examination of current slump effects. Very short pulses and low duty cycles reduce device heating which may otherwise mask important behaviours. However, the most important aspect of pulsed measurements is the ability to examine trapping behaviour in the semiconductor. For this reason, we utilised pulsed I-V measurements in the examination of fast trapping effects in Al1.,GaXN/GaN HEMTs.
4.2.1 Virtual Gate Model of Current Slump
To date, current slump has been discussed in terms of charged surface states inducing a "virtual gate" in the gate-drain region of the transistor [89, 901. In this model electrons are injected from the gate onto the device surface where they are trapped by surface states as shown in Figure 4-2. The effectiveness of surface passivation films in reducing current slump suggests that charged states in the extrinsic transistor surface are indeed largely responsible for the slump [90]. As discussed in Chapter 3, surface states are also intimately involved in the formation of the 2DEG at the All-,Ga,N - GaN interface. When filled, and negatively charged, such surface states act to deplete electrons from the 2DEG channel. Charged surface states
GaN Channel
Partially depleted Buffer Layer channel
Semi-insulating Substrate
Figure 4-2: Illustration of tlze virtual gate effect. Occupied surface states partially deplete tlz e clzannel in the gate-drain region.
If charged surface states cannot de-trap quickly enough to respond to the input signal the trapped surface charge will cause sluggishness in the device response during large-signal operation. Since populated surface states will appear as a constant negative sheet charge on the surface of the device the trapped electrons havethe same effect as a gate with negative bias over all regions where surface states are occupied.This "virtual gate" is constant and does not modulate as the physical gate does. The effect of the virtual gate is to deplete electrons in the 2DEG below resulting in higher access resistances leadingto reduced current and power performance.
The virtual gate model proposes that occupied surface states are limited to the gate-drain region. This assumption appears reasonable because the largest fields appear on the drain side of the gate and as a result, electron inj~ctionshould be strongest there. Indeed, this assumption is supported by recent Kelvin force measurements whichshow a link between drain current and surfacepotential in the gate-drain area [90, 911. However, a limitation of the Kelvin force technique isthat it is purely static (DC) and cannot probe dynamic or transient slump effects. In contrast, our examination was concerned with 0 1 2 3 4 5 6 7 8
Drain-Source Voltage k' (V) ds
Figure 4-3: Measurement cycle of the DiVA pulsed system. The system sits ut the quiescent point Q and pulses around the I- V characteristic. V,, begins at 0 V and drops in 1 V increments.
current slump over small time scales so we use pulsed 1-V measurements to examine the drain current after various stressbiases.
4.2.2 Pulsed I- V Characteristicsof All-,Ga,N/GaN HEMTs.
4.2.2.1 Pulsed MeasurementsWith Accent Optoelectronics DiVAD265
The Accent Optoelectronics DiVA265 [92] is a dynamic I-V measurement tool which allows for pulsed device characterisation. The device is a dual-channel synchronous pulse source measurement unit andin this work we examine the I-V characteristics using 200 ns pulses.
The DiVA pulses throughthe I- V characteristic from a central quiescent bias point as illustrated in Figure 4-3. In this example the quiescent point, Q, is Vd, = 5 V and V,, = - 4 V. If we suppose a measurement is made with a pulse length of 200 ns and pulse spacing of 1 ms then the I-V curve is traced as follows: the device stays at the quiescent
point, Q, with Vds = 5 V, Vgs = -4 V, for 0.9998 ms and then pulses to the voltage Vl (Vds
= 0 V, Vgs = 0 V) in Figure 4-3. The pulse to Vl lasts only 200 ns and the current and voltage are measured at the end of the Vl pulse. The bias is then returned to the quiescent
point where it remains at Vds = 5 V, Vgs = -4 V for another 0.9998 ms. Next, the device is pulsed to V2 (Vds = 0.5 V, Vgs = 0 V) and remains there for 200 ns while the current is measured. This process of continually returning to the quiescent point between pulsed measurements proceeds until the entire parameter space is mapped out.
Mapping the I-V curves in the above manner is very useful, particularly if recovery of the slump transients takes longer than 200 ns. In this case, the effect of slump induced by the quiescent point has not faded when the current is measured during the pulse phase. In this manner, the shape of the pulsed I-V characteristic reflects the level of slump induced by the quiescent point bias. Using this technique, the efficacy of different biases in causing slump was examined.
4.2.2.2 Pulsed Measurement of Slump in All-,Ga,N/GaN HEMTs
The epitaxial layers in this study were All-,Ga,N/GaN grown by MOCVD on Sic. The barrier layer was 220A Si-doped AIO.~GQ.~Nyielding a 2DEG concentration of
1.1 x 1~'~cm'~. Ohmic contacts were formed by Ti/Al/Ni/Au evaporation (3OO/18OO/4OO/15OOA) and rapid thermal annealing at 850•‹Cfor 40s. T-gates with a 0.23 x 50 pm2 footprint were fabricated by electron beam lithography and Ni/Au (25014500A) evaporation and lift-off Devices were electrically isolated by PIHe ion implantation. Devices were not passivated since the present intent is the characterization of current slump rather than its suppression. Our devices typically featured f~= 50 GHz and f- =
110 GHz at a bias of Vds= 7 V and Id = 200 mA/mm. For all measurements the sample was connected to the DiVA via 100 pm pitch RF microprobes through a GSG coplanar waveguide. 5 10 Drain-Source VoltgaeIfds (V)
Figure 4-4: Comparison of conventional DC measrirement (red) with pulsed I-V measurement (black). Pulsed measurements were made with n quiescent point of Vds= 0 V and V, = 0 V.V,, begins at 0 V and drops in I V increments.
We applied different quiescent biasesto All-,Ga,N/GaN HEMTs to examine the slump induced as a function of gate-drain and gate-source voltage. Henceforth, each quiescent point Q will be represented by a pair of numbers Q = (Vds, Vzs). i.e. Q = (10,-3)
represents a quiescentpoint of Vds= 10 V and Vgs= -3 V.
Figure 4-4 shows conventional DC I-Vcharacteristics overlaid with pulsed I-V
characteristics taken at Q = (0,O). The I- V characteristics were pulsed over a range of Vds = 0 to 15 V and V,, = -7 to 0 V. While the conventionalDC measurements yielded Idss= 645 mNmm and g, = 128 mS/mm, the Q = (0,O) pulsed measurements yielded g, = 200 mS/mm and Idss continues to rise even past 970 mA/mm. The Q = (0,O) results represent the most ideal behaviour, free of heating effects and withslump at a minimum. J I0
Drain-Source Voltagc I/ (v) ds
Figure 4-5: Comparison of slumped Q = (10,-5) V (re4 witlt unslumped Q = (0.0) V (black) pulsed I- V measurements. GSbegins at 0 V and drops in I V increments.
J 10
Drain-Sourcc Voltage 1, (v) ds
Figure 4-6: Comparkon of slumped Q = (10,-5) V (re4 with unslumped Q = (0,O) V (black) pulsed I- V measuremen ts under UV ligltt exposllre. V, begins at 0 V and drops in I V increments. The impact of slump becomes apparent when the gate-source voltage or gate- drain voltage are increased. Figure 4-5 compares characteristics taken with quiescent points of Q = (0,O) and Q = (10,-5). In this case the typical threshold voltage was -7 V.
This data demonstrates that the fields associated with a stress bias of Q = (10,-5) cause electrons to occupy traps, leading to significant current slump.
Our measurements show that after being filled, surface trap recovery is difficult. Figure 4-6 compares the pulsed response with UV light7 continuously incident to the surface of a device with Q = (0,O) V (unslumped) and Q=(lO,-5) V (slumped). We see that the application of UV light increased both the unslumped and slumped response current by roughly 200 mA/mm. This indicates that the current increase during UV illumination is due to the formation of excess electron-hole pairs and not trap recovery. One might expect that this is evidence that the traps are not surface related but occur under the gate. However, we have found that the same exposure to UV light does an excellent job of recovering slumped current after the removal of a slump bias. The difference between the Q = (0,O) V and Q = (10,-5) V results shown in Figure 4-6 (UV on) occurs because the slump bias continually repopulated the surface traps. In this case, traps are populated quickly and the emission time, even in the presence of UV light, is longer than the pulse length.
Lastly, with a slightly different layer structure we demonstrate that both Vgsand
Vdsare capable of inducing slump. Figure 4-7 shows the Vgs= 0 V line for slump biases of constant Vgswith Q = (0, -6), Q = (5, -6), Q = (10, -6), and Q = (20, -6) V. This demonstrates that increasing the drain voltage enhances population of surface states.
Similarly, Figure 4-8 shows the Vgs= 0 V line for slump biases of constant Vdswith Q =
(8, 0) and Q = (8,-2), Q = (8,-4), Q = (8,-5), and Q = (8,-6) V which demonstrates the effectiveness of the gate voltage in populating surface states.
Blak-Ray B 100A UV light source. 5 10 Drain-Source Voltage I' (V) ds
Figure 4-7: Demonstration of slump induced by various drain voltages. Vgs = 0 V for each line.
5 10 15 Drain-Source Voltage I' (V) ds
Figure 4-8: Demonstration of slump induced by various gate voltages. Vgs = 0 V for each line. 4.2.2.3 Gate-Source Slumpin All-,Ga,N/GaN HEMTs
It should be noted that for Figures 4-7 and 4-8 the gate-drain voltage increases in both cases. The virtual gate hypothesis postulates that at high biases electrons are injected from the gate metal into surface states in drainaccess region as illustrated earlier in Figure 4-2. It is believed that the gate-drain region dominates currentslump behaviow due to the high field there. While Figures 4-7 and 4-8 are consistent with chargingof the gate-drain region at higher gate-drain biases, the questim remains whether it is possible that electrons are injected into the source access region in the same way. If true. the slump model of Figure 4-2 would have to be adjusted to include additional surface depletion of the 2DEG in the source access region.
Through judicious choice of stress biases in pulsed I-V measurements, we examined the importanceof the source access region on current slump in A~I,G~,N/G~N HEMTs. In the present work we applied pulsed I-Vmeasurements to show that the gate-
5 10
Drain-Source Voltage 1' (V) ds
Figure 4-9: DC (red) and Q= (0,O) Vpuised I-V (black) characteristicsfor unstressed, nun-passivated HEMT. V,, begins at 0 V and drops in 1 V increments. source region can in fact play a significant, and even dominant, role in current slump taking place in non-passivated All-,Ga,N/GaN power HEMTs.
Figure 4-9 shows representative DC device characteristics (red): they reveal a
maximum current density Idss,static = 750 mA/mm, a transconductance of gm,st,ic =I90 mS/mm, and a threshold voltageof VTmstatic= -6 V. The pulsed I-Vcharacteristics (black) were measured with a quiescent pointQ = (0,O) V xid 200 ns pulses with a 2 ms
separation. The short duty cycle eliminates heating effects and result inIdss,pulsed > 1000
mA/mm, gm,pulsed= 200 mS/mm, and a threshold voltageof VT.pulsed= -7 V.
Next, we intentionally induced currentslump in our devices by applying biases of the order of Vr between the gate and ohmic electrodes. \Ye exposed the difference in the role of the gate-source (G-S) and gate-drain (G-D) region stresses by using complementary quiescentbiases for the pulsed I-Vmeasurements. In the first case, only
the gate-drain region is stressed (quiescent bias Q1 = (8,O) V, source grounded), whereas both the source-gate and the gate-drain regions are stressed in the second case (quiescent bias Q2 = (0,-8) V, source grounded). As shown in Figure 4-10, both stress conditions result in a -8 V stress to the G-D region, but they differ inwhether or not the G-S region is stressed. Figure 4-1 1 compares the resulting characteristics:Ql only stresses the gate- drain region of the transistor and induces a mild current slump reducing the maximum drain current by approximately 20% (200 mA/mm) compared to the Q = (0,O) result. In contrast, Q2 results in an extreme manifestation of slu_xp when the G-S region of the
Source Gate Drain Source Gate Drain OV OV 8V ov -8V ov
Figure 4-10: Complementary biasing of gate-drain and gate source regions. (a) Ql with Vg,9= 0 V and Vd.9= 8K (b) Q2 with Vg.%= -8 V and V,r, = 0 V. 5 10 Drain-SourceVoltage I: (V) ds
Figure 4-11: Pulsed I- V characteristics of comp1ementc.rt-y biases. V,, begins at 0 V and drops in I V increments. Black: gate-drain stress: Ql = (8,O) V Red: gate drain and gate-source stress: Qz = (0,-8) V transistor is stressed in addition. It is interesting to note that while both quiescent points entail an -8 V reverse bias across the gate-drain region, the strong current slump is only associated with the reverse bias at the gate-source region.The strong asymmetry between stress conditions Ql and Q2 can be understood by noting that stressing the G-S region depletes the source access region. Thus effectively throttling Id by degrading the source resistance Rs and simultaneously increasing the gate-channel reversebias at the entrance of the channel, leadingto large drops in Id and g,,.
Finally, we show in Figure 4-12 that moderate G-5 stresses induced a more severe current slump than stronger G-D stresses, indicating that the effects of G-S and G-D stresses on current slump were not simply additive. Figure 4-12 plots the normalised Vg, = 0 V drain current values for different quiescent biases, with normalisationto a 'virgin' slump-free state. We see that a quiescent point of Vds= 14 V, Vgs= 0 V (Q4) only resulted in slightly more slump than Vds= 7 V, Vgs= 0 V (Q3).Fig. 3 also shows the effect of a 1111111111111111111111111111111
0 5 10 15
Drain-Source Voltage lids(V)
Figure 4-12: Pulsed I-V clzaracteristics measured at V,, = 0 V normalised to maximum unstressed drain current value.
quiescent point of Vds= 0 V, Vgs= -7 V (Qs) for comparison: simultaneously stressing the G-S and G-D spaces with -7 V (VT)thus induces a far stronger current slump than a-14 V (2 VT)stress across the G-D region alone.
These results demonstrate that reversebias electrical stress of the G-S junction in All-,GaxN/GaN HEMTs induces a strong slump that proves far more severe than that resulting from an equal stress at the G-D junction. The G-S induced slump should alsobe mitigated by surface passivation techniques,but its complete eradicationmay prove more difficult than for the G-D space because of the sensitivity of FET performance to source degradation. The finding is of importance to the design of high-efficiency power amplifiers which may run deep into pinch-off, hence subjecting the gate-source (G-S) region to large reverse bias stresses. Additionally, FET-based transmit-receive switches routinely drive gate-source junctions deep into the pinch-off regime: some configurations result in equal G-S and G-D reverse bias stresses during an RF cycle [93]. Source-side induced slump may impact the performance of T/R switches and may provide an alternate mechanism for the source resistance modulation invoked by Trew [4] to explain the decreased performance of GaN-based power amplifiers with higher drive levels.
4.3 Thin Surface Passivation Layers
Current slump in All-,Ga,N/GaN field-effect transistors subjected to high RF- drive levels and/or to bias stresses is attributed to the presence of surface trapping states whose nature remains to be identified. Although current slump manifestations can be alleviated with various surface films, the exact passivation mechanism remains a matter of debate in the community.
While the virtual gate hypothesis has enjoyed much conceptual success, the physical nature of the involved surface states remains to be determined. Furthermore, the possibility that current slump involves trapping levels in either the buffer or All-,Ga,N barrier layers has not been ruled out at this point, although the success experienced with Si3N4 surface passivation films suggests that the sample surface is intimately involved in manifestations of current slump [34, 941. Even here, the reasons behind the success of passivating thin films remain an open topic of discussion. Some have suggested that dielectric films such as Si3N4directly passivate electrically active surface states [94], but others have assigned the improved device performance to the suppression of electron injection due to the dielectric film [95], or to strain associated with the dielectric film and the piezoelectric character of GaN [96]. A broad variety of novel thin films such as Hf02 [97], MgO [98], and Sc2O3[98] has also been investigated for passivation layers. Despite much materials development and characterization work, the community remains without a clear cause-and-effect understanding of the origin of surface states and their passivation in All-,Ga,N/GaN HEMTs. This is a very important issue because current slump limits practical performance and impedes the commercialization of All-,Ga,N/GaN HEMTs. The present section seeks to clarify the origin of slow current slump transients in All-,Ga,N/GaN HEMTs, and sheds new light on the passivation mechanism in All -,Ga,/GaN HEMTs. 4.3.1 Trapping in All-,Ga,N/GaN HEMTs
We first note that very slow transients associated with current slump can have recovery times on the order of seconds to tens of seconds. This suggests that deep level traps must be involved in the process because carrier emission rates from deep level
centres decrease exponentially as the trap separation from the relevant band (Ec - ET or
ET - Ev) increases [49]. Indeed, measurements on HEMTs have shown that slow transients with time constants of > 1 s are associated with a 1.43 eV deep trap that is much attenuated when the sample surface is encapsulated with Si3N4 [94]. Much shallower deep centres with a separation of 0.3 eV from the relevant band edge lead to current transients with microsecond time constants (too fast to account for slow transient slump), as shown by Meneghesso et al. by extensive numerical simulations [99]. The vast majority of known impurities and point defects have activation energies < 0.75 eV in wurtzite GaN [35] (with the exception of the GaNwith ET - EV= 0.59 to 1.09 eV, and CN with ET - Ev = 0.89 eV): from a carrier emission rate point of view it appears that impurities, vacancies and most antisite defects are too close to the conduction and valence bands to be associated with the slow transient slump commonly observed in
A1 I -,Ga,N/GaN HEMTs.
If most impurities and point defects do not sit deep enough in the forbidden gap, there is ample theoretical evidence [loo-1021 that threading dislocations in GaN epitaxial layers give rise to a multitude of deep level states distributed across the GaN energy gap. For example, Lee et al. [loo] reported that full-core dislocations lead to energy levels - 1.4 eV below Ec: such deep levels would be consistent with the deep levels associated with slow current transients in AlI.,GaXN/GaN HEMTs [94]. In a separate experimental study, Miller et al. have demonstrated that dislocations in GaN are electrically active and that a preferential oxidation of dislocations at the surface of samples brings about a significant reduction of leakage current in macroscopic Schottky contacts fabricated on All -,Ga,N/GaN layers [103].
We have examined slow current slump transients before and after various simple passivation procedures. The effectiveness of these methods in mitigating slow current slump transients indicates that dislocations have a previously unknown role in contributing to current slump in All-,Ga,N/GaN HEMTs.
4.3.2 Passivation of Slow Transients
4.3.2.1 Ozone Passivation
In the present section, we show that a simple oxidising ultraviolet ozone exposure on as-fabricated devices successfully passivates slow current transients in All-,Ga,N/GaN HEMTs implemented without any other surface treatment or passivation. The ozone treatment has been shown to result in a very thin surface oxide (1.5 to 2.5 nm) that is compositionally distinct from native All-,Ga,N surface oxides when probed by XPS [104]. Our results shed new light on the All-,Ga,N/GaN HEMT surface passivation problem because they show that an ultra-thin surface film is sufficient to largely eradicate the long time constant current transients associated with deep traps. The large trap ionization energies associated with dislocations in GaN, and the propensity for preferential oxidation of threading dislocations [I031 on exposed surfaces both suggest that the elimination of slow current transients by ozone exposure operates by the passivation of threading dislocations where they intersect the sample surface. We further elaborate below on the these findings and their implications after describing the experimental work.
Our commercially available All-,Ga,N/GaN HEMT material was grown on a sapphire substrate by MOCVD. The layer stack consisted of a 200 A A10.24G~.76Nbarrier (50 A undopedl 150 A Si-doped / 50 A undoped) on a GaN buffer, yielding a channel electron concentration of 1.15 x 1013 ~m-~.Ohmic contacts were formed by Ti/Al/Au
(600/1000/500 A) evaporation followed by rapid thermal annealing, and 1 x 100 pm2 Ni/Au (250/4000 A) gates of were formed by optical lithography, electron beam evaporation and lift-off. Inter-device isolation was by P/He ion implantation. No dielectric film was used in order to allow access to the sample surface. Two sets of devices were used for comparison: non-passivated as-fabricated benchmark devices, and transistors subjected to a 10 minute exposure in an Ultra Violet Ozone Cleaning System Drain-Source VoltageI,' (V) ds
Figure 4-13: Transistor I- V characteristicsfor a 1 x 100 ,um2 as-fabricated transistor. Bias stressing induces a significant current slump (red) compared to unstressed (black). V,, begins at +I V and drops in 1 V increments.
(UVOCS). Our UVOCS system lamps provided5 mw/cm2at h = 256 nm and heated the sample to -50 OC during exposure: the treatmentwas therefore very mild.
Current slump recovery measurements were performed by first subjecting HEMTs to a "stress bias" of Vds= 10 V, Vgs= -8 V for a duration of 4 minutes. Upon removal of the stress bias a full DC I-V characteristic was measured. Figure 4-13 shows severe drain current dropinduced by exposure to the stress bias. Both sets of curves were taken for the range Vds= [0 to 151 V and V,, = [+1 to -81 V. The characteristics in black provide comparison to an unstressed device, and the red characteristics were taken immediately following the removal of the stress bias. The drain current is greatly suppressed by the stress bias on the as-fabricated transistors.
In contrast, Figure 4-14 shows the effect of ozone exposure on current slump by comparing the pre-stress (black traces) and post-stress (red traces) characteristics for the 5 10 Drain-Source Voltage Y (V) ds
Figure 4-14: Transistor I- V characteristics for a I x 100 ,um2 transistor following a 10 mitz ozone surface treatment. Current slump is effectively passivated. Tlze post-stress clzaracteristic (red) shows little slump compared to tlze unstressed clzaracteristic (black). V,, begins at +I Vand drops in 1 Vincrement.~.
same device. Current slump is greatly reduced by the ozone treatment, showingthat a simple 10 minute exposure to ozone without any other surface treatment largely suppresses slow current slump.
Another demonstration of the removal of slow slump transients was made by subjecting the device to a stress bias of Vds= 10 V and V,, = -7V. After removal of this stress the time evolution of the drain current with Vd, =10 V, V,, = 0 V was measured. Figure 4-15 shows a sampled time measurement demonstrating that ozonepassivation leads to a quick recovery to its steady state value. Unpassivated devices though, have a much slower response. The inset of Figure 4-15 shows the reverse gate leakage current measured in the device of Figure 4-14, before and after ozone passivation, showingthat the ozone treatment reduces the reverse gate leakage cu-rent by as much as an order of magnitude. This is what one might expect by analogy with the selective dislocation ".LO .h'I"- 1.10 Asfabricated - Ozone treated @
Slump Recovery (I/ =]Or/. V =-7V1o V =IOV, k' =Or/) ds 2s ds 3s
3 0 4 0 Time (seconds)
Figure 4-15: Slow current transients in as-fabricated transistors, compared with stable current levels in ozone-treated sample. Inset: Ozone treatment reduces the reverse gate leakage by one order of magnitude.
oxidation results of Miller et al. [103]. It should also be noted that the ozone passivation effect was only temporary. After 24 hours devices reverted back to their slump behaviour.
4.3.2.2 Passivation with thin layers of Ni and NiO
In a similar experiment on a similar sample, we passivated All-,Ga,N/GaN HEMTs with thin layers of Ni and NiO. In the case of NiO passivation we deposited 70 A of Ni by electron beam evaporation. The sample was oven annealed at 700 OC for 5 minutes in ambient environment.It has been shown that this procedure allows for the formation of NiO with a bandgap of - 4 eV [105].
For all samples a slump response similar to Figure 4-13 occurred when I-V characteristics were measured immediatelyafter the removal of a slump bias. However, Drain-Source Voltage I' (V) da
Figure 4-16: Operation free of slow current slump &er NiO passivation. The I-V characteristics after significant stressbias (red) display very little slump compared to the unstressed characteristics (black).Vgs begins at +I If and drops in 1 V increments.
with the deposition of the NiO layer the I-V characteristics were found to be free of slow
current slump effects. Figure 4-16 shows that the I- V characteristics of a NiO passivated device measured immediately after a 4 minute stress bias (Vds= 10 V, Vgs = -9 V) (red) did not differ appreciably from those measured without a prior slump bias (black).
Perhaps a more extreme example of ultra-thin passivation layers can be shown in Figure 4-17 where it is shown that DC slump can be effectively ameliorated by evaporation of 5 8, of Ni over the entire sample surface. Note, however, that the V,, = +1 V line in figure 4-17 does in fact indicate that a small amount of DC slump is present. This is probably because a 5 8, film of Ni is unlikely to achieve full coverage of the sample surface. It is also worth stating that 5 8, Ni layer is likely oxidised by the ambient to NiO.
The effectiveness of thin ozone deposited oxides. NiO, and Ni layers in reducing slow current slump gives insight into the passivation mechanism of these deep trapping 5 10
Drain-Source Voltage 1' (V) ds
Figure 4-1 7: Operation with little slow currentslump ajter passivation with 5 A of Ni. The I-V cltaracteristicsafter significant stressbias (red) display little slump compared to the unstressed characteristics (black). V,, begins at +I V and drops in 1 V increments.
states. While the effectiveness of Si3N4 passivatior has been attributed to strain associated with the dielectric film and the piezoelectric character of GaN [96], this
explanation is not plausible for such thin passivation layers. In particular, the 5 Pi passivation layer of Ni is in the realm of a single monolayer.
In addition to excluding strain as a viable passivation mechanism, ourpassivation layers dictate that suppression of electron injection due.to the dielectric film [95] is not a viable explanation for the success of such ultra-thin films. We propose that the passivation mechanism of ozone oxide, NiO, and thin Ni are the same: that they directly passivate trapping states associated with dislocations.
The role of dislocations in current slump is independently supportedby Irokawa et al. [lo61 by gate-lag measurements on nominally identical layers grown on c-plane sapphire and on free-standing GaN substrates. The term gate-lag is used to describe the slow transient response of the drain current to abrupt changes in the gate voltage. Lattice- matched devices with a dislocation density of -lo6 cm-2 featured a much weaker current slump effect when compared to the HEMTs grown on sapphire with a dislocation density of -lo9 cm2, leading Irokawa et al. to the conclude that slump is related to the threading dislocation density. Because the transistors grown on sapphire were under tensile strain while the HEMTs on GaN were strain-free, the effect of strain could not be categorically ruled out as a reason for the current slump reduction [106]. By contrast, our passivation layers are so thin [I041 that they are inconsequential from a strain standpoint and we may safely conclude the ozone passivation of surface states does not operate through a strain mechanism. When considered together, our data, the dislocation oxidation work of Miller et al. [I031 and that of Irokawa et al. [I061 firmly establish that dislocations intersecting the sample surface are intimately involved in current slump.
Lastly, it should be noted that neither ozone, NiO, or Ni passivation was able to remove current slump as seen in pulsed measurements. This was the first demonstration that fast and slow trapping effects can be controlled separately and is a convincing argument that different kinds of trapping centres are involved for each. This is consistent with a model where slow trapping is connected to dislocations (which are deep trapping centres) whereas fast slump effects are related to shallower defects or impurities. Figure 4-18: Contact potential image of an AII,GajV/GaN lzeterostructure on Sic. Areas of low potential extendfar around each dislocation. From Eguclzi et al.[107].
4.3.2.3 Charging of Dislocations
There is still a significant difficulty with the above claim that dislocations are responsible for slow- slump transients in All-,Ga,N/GaN HEMTs. Whereas GaN layers grown on sapphire or Sic substrates exhibit threading dislocation densities of 10'-10~~ ~m-~,surface charge densities >1012 cm-2are necessary to noticeably deplete a channel sheet charge of -1013 cm-2 via the virtual gate effect: this requires that each dislocation trap many hundreds, or even thousands of electrons.
The charging of dislocations in AII_,Ga,N/GaN HEMTs has been studied using Kelvin Probe Force Microscopy (KFM) by Eguchi et ul. [107]. Figures 4-18 and 4-19 show Eguchi et al.'s contact potential measurements for an All-,Ga,N/GaN heterostructure with a barrier of 200 8, and GaN channel of 3 pm. Regions of low potential extend well beyond the physical size of the dislocation indicating that the 0 1111 1111 1111 1111 0 0.5 1 1.5 2 Position (pm)
Figure 4-19: Contact potential passing over two dislocations (the BB' line in Figure 4- 18) in an AIl,Ga,N/GaN heterostructure. From Eguchi et al. [I 071.
dislocations may be negatively charged causing depletion of the 2DEG in the regions nearby.
In order to determine if Eguchi et al.'s result is consistent with trapping of large number of electrons we simulated the potential profile above the surface of an AII,GaxN/GaN heterostructure with a line charge passing vertically through the 2DEG. The system we used to determine the potential profile consisted of a line charge with N, electrons evenly distributed down the length, L, of the dislocation. The charged length of the dislocation was assumed to pass through both the barrier and channel. The 2DEG was placed a distance, t, below the sample surface. The system has circular symmetry and the potential can be determined for any distance, r, from the dislocation.
It is not enough to determine only the potential from the single line charge as the 2DEG density will adjust to the potential in the region around the dislocation. To determine the potential of the dislocation in the presence of the 2DEG we used the well- known image charge method, treating the 2DEG as a conducting plate. In order to do this, a line of the same length and with N,positive charges was reflected around the 2DEG and the potential of the two line charges was calculated.
From the electrostatics of a finite line charge it is simple to show that the potential at the surface of the semiconductor is given as follows:
Equation 4.1 allows for the determination of the potential on the plane of the semiconductor surface. However, the data by Eguchi et al. was measured with a sample- probe distance of 30-50 nm as communicated by one of the authors. In order to determine the potential at the probe location above the surface, software was written to solve the Laplace equation above the surface of the semiconductor,
Laplace's equation was solved using the finite difference method and Neumann mirror-image boundary conditions for an iterative algorithm [108, 1091. The Neumann boundary conditions were set at the edges of a 2 pm x 2 pm square in the plane of the surface around the dislocations. The boundary conditions were set 1 pm above the surface in the vertical direction. The solution largely converges after - 500 iterations with 1000 iterations yielding a further change of only 2%.
The best fit result is achieved with each dislocation holding Ne - 5000 electrons and the simulated potential with Ne = 5000 electrons is overlaid with Eguchi et al.'s work in Figure 4-20. Note that the modelled results are for a point dislocation and a point probe while the probe tip itself is stated to have a diameter of - 60 nm. To account for the probe size we simulated the potential at a height of h = [(probe hei,ghtl2+ (probe dia~neter)~]~.'.We used a probe height of 40 nrn and probe diameter of 60 nrn and so simulated the potential at h = 70 nm above the surface of the semiconductor. In addition, Eguchi et al. state that the diameter of the dislocations is from 20 to 60 nm but they have been treated as lines with no lateral size. Despite these shortcomings, these simulation results clearly show that dislocations in All-,Ga,N/GaN heterostructures are capable of storing many thousands of charges. With 5000 charges per dislocation it is possible to affect the average 2DEG concentration for dislocation densities of 10' to 10" ~m-~.One would expect the numbers of electrons in dislocations to increase as significant slump biases are added, increasing the fields, and injecting more electrons from the gate into the surface
200 -
- .-m -C a d U m -C 00 50 -
0 1111 IIIIIIIIIIIIII~
0 0.5 1 1.5 2 Position (pm)
Figure 4-20: Comparison of modelled (red) and measured (black) potential profile at tip height around dislocation. Modelled potential has N, = 5000 electrons per dislocation. Note: modelled data is given a DC offset to overlay with Eguchi et al.'s result. states.
The capture of multiple electrons by extended defects in GaN was recently examined by Look et al. [I101 by analysing electron holography data [I 111. When normalised per c-axis parameter, their results were consistent with 1.7 electrons per unit c, where the c-axis parameter is 5.185 A. Our results analysing KFM measurements of All-,Ga,N/GaN heterostructures indicated a density of - 1 electron per unit c.
With highly charged dislocations affecting the slump characteristics of the drain current we propose that the original virtual gate model be revised from one where a uniform surface sheet charge induces channel depletioc. (Figure 4-2), to one of multiple discrete virtual gates (one per emerging charged dislocation at the sample surface) as shown in Figure 4-21. The access resistance is increased by forcing current flow lines to percolate through a network of partially depleted channel pockets which effectively reduces the open channel transistor width.
Dislocation density= 10'
Figure 4-21: Sclzematic representation of a revised virtual gate model: trapped charges partially deplete the 2DEG around dislocatiovlsforcing currentjlow lines to percolate between depletionzones. This diagram assumes a dislocation density of lo8 ~m-~. 4.4 Summary
Current slump and passivation of A~I-,G~,N/G~NHEMTs was examined. Through high-frequency pulsed measurements it was found that both gate and drain biases can result in current slump. In particular, it was demonstrated that slump not only occurs in the gate-drain region but also can occur in the gate-source region. This is an important discovery as the source resistance is particularly destructive to device performance. This result is also confirmed by equivalent circuit extraction described in Chapter 5.
Passivation of slow transients was accomplished through deposition of ultra-thin layers. NiO, Ni, and ozone oxidation layers were demonstrated to be effective in reducing the effect of slow trapping states. In addition, the fact that these passivation techniques did not alter the fast slump behaviour indicates that fast and slow slump behaviours are controlled by different kinds of trapping centres. This was the first demonstration that slump states can be controlled separately.
The slow slump removal was correlated with the passivation of dislocations intersecting the sample surface. Dielectric strain and reduction in gate injection currents were shown not to be viable explanations for the effectiveness of ultra-thin film passivation in mitigating slow slump effects. Simulations of KFM results show that dislocations can hold enough electrons to significantly affect the conductivity of the 2DEG. An alternate virtual gate model was proposed where dislocations operate as the primary trapping centre for slow transients. This creates heavily depleted pockets around each dislocation, increasing the parasitic resistances and causing decreased currents. CHAPTER 5: HIGH-FREQUENCY CHARACTERISATION OF All-,Ga,N/GaN HEMTS
5.1 Introduction
High-frequency characterisation is critically important to the evaluation and optimisation of HEMTs and other high-speed devices. While the basic cut-off frequencies fT and f~mare the most commonly quoted figures-of-merit describing W behaviour, much additional information is available from high-frequency measurements. fT and fMm are typically determined from scattering parameter (S-parameter) measurements, but other quantities related to the device under test (DUT) can be explicitly determined from these same measurements. In particular, an entire equivalent circuit model can be extracted for each device. A device's equivalent circuit is important because it allows one to determine the circuit response, and because model elements should be directly correlated with physical parameters within the semiconductor itself. For this reason, with an equivalent circuit determined, one can examine the behaviour of a device under different conditions and infer details about the underlying physics involved.
In this chapter, an extraction methodology to determine the equivalent circuit model for All-,Ga,N/GaN HEMTs is explored. In particular, the equivalent circuit was determined for devices under operation, and full parameter extraction was accomplished without special biasing test conditions. With this information we were able to examine slump behaviour at GHz frequencies and accurately extract the effective electron velocity under the gate while simultaneously accounting for the current slump effect. 5.2 Microwave Measurements
The high-frequency response of devices was characterised through their scattering parameters (S-parameters) which were measured to 40 GHz on the equipment available at SFU. S-parameters are voltage ratios of the transmitted signal to the incident signal (S12, S21), and the reflected signal to the incident signal (SI~,S~~).W signals were applied through 2.9 mm GGB coaxial cables to the DUT which was connected via GGB 40A Picoprobes. The entire S-parameter measurement system was controlled by an HP 85 10B network analyser. A good introductory treatment of high-frequency S-parameter measurements can be found in [112].
Raw S-parameters were measured at the input to the HP 8510 and the effects of the connecting cables served to mask the results from the DUT. To overcome this effect, a Short-Open-Load-Through (SOLT) calibration was done to move the measurement plane to the tips of the GGB Picoprobes. This calibration was carried out within the HP 85 10B and effectively removed the impact of the connecting cables.
With the measurement plane at the end of the cables, it was necessary to shift it further towards the device. Each device had large area, coplanar waveguide TiIAu pads which led from the source, drain, and gate to an open area on the sample. The purpose of these pads was to provide a large, soft probing surface with which the Picoprobes could connect to provide reliable, repeatable measurements. Because of their large areas, the pads had significant capacitances associated with them which affected the measured performance of the DUT. However, on each sample, blank "dummy" pads were fabricated to allow for subtraction of the pad effects, a process called "de-embedding". Open circuited pads allowed for determination of the pad capacitances while short- circuited pads allowed for determination of the pad inductances. Once S-parameters for the DUT, open, and short pads were measured, they were converted to Y-parameters (admittance) and the de-embedded Y-parameters of the transistor were determined as in equation 5- 1 [I 131, where YDUTrepresents the Y-parameters of the DUT (which includes the transistor and pads together). Yo,,,, Yshort,and Yt,,, are the Y-parameters of the open dummy pad, short dummy pad, and the de-embedded transistorrespectively.
After de-embedding, the actual transistor S-parameters were available for analysis. The primary quantities used in high-frequency evaluation are thecurrent gain
cut-off frequency, fi.,and the maximum frequency of oscillation, fMAx. fT is the unity current gain frequency under short-circuit conditions and was determined by
extrapolating lh21 l2to 0 dB [114],
AMAXwas determined by extrapolation of power gain to unity. Both lhzl12and U were extrapolated at -20 dB1decade as is the norm. There are many different types of power gain utilised in analysis of RF devices but the most commonly used quantity for
Figure 5-1: RF performance of a 0.15 pn PEC wet-etched device. Current gain flhlrf)iF extrapolated to 0 dB for fT, Power gain (uis extrapolated to 0 dB for fW. determination of fM is Mason's Unilateral Gain (U) [115]. fT was the most important quantity used in this thesis as it could be directly related to the electron velocity as in Equation 2-5, while fMm was included primarily for completeness. Figure 5-1 shows the
cut-off frequencies for an AlGaNIGaN HEMT fabricated in our lab with Lg = 0.15 pm. Here fT - 70 GHz and fMm - 90 GHz.
5.3 Typical Small-Signal Modelling of All-,Ga,N/GaN HEMTs
5.3.1 Equivalent Circuit Diagram
The purpose of small-signal modelling is to represent the behaviour of the transistor in the form of conventional lumped circuit elements. This technique is particularly useful as the lumped elements are often directly correlated to physical entities within the device structure. Figures 5-2 (a) and (b) show the typical small-signal model of a MESFET device as proposed by Dambrine et al. [116].
The circuit schematic shown in Figure 5-2 (a) can be directly related to the physical device in 5-2 (b). Notice in Figure 5-2 (a) that the device is divided into two separate regions: the "intrinsic" device which encompasses the elements directly within the gate region where modulation occurs, and the "extrinsic" device, which also includes the parasitic resistances and inductances of the ohmic contacts. Here Rs, Rd, and Rg are the parasitic resistances of the source, drain, and gate respectively, while L,, Ld, and Lg are the parasitic inductances of the same. The source and drain resistances form between the top of the ohmic metal and the edge of the depletion region, while the gate resistance occurs down the length of the gate finger. The parasitic inductances associated with the ohmic contacts are small, and since the ohmics are almost entirely covered by the access pads, the inductances, L,, Ld, and Lg are the same as those determined by the short pad measurement.
For the intrinsic device, the drain current is represented by vggmoiJJ"'whereg,, is the intrinsic transconductance, o is the angular frequency of the input signal, wz is the Gate -
b Source Figure 5-2 (a): HEMT and MESFET equivalent circuit schematic.
Figure 5-2 (6): Cross-section of MESFET indicating physical origin of each circuit element. The intrinsic circuit is enclosed in dashed box.
phase difference between the gate voltage and the drain current, and vgsis the small- signal gate voltage.
The conducting channel and the gate metal are separated by the depletion region which acts as the dielectric between two plates of a capacitor. This gate capacitance is represented by two values, C,, and Cgd. From Figure 5-2 (b) one can see that Cgd represents the capacitance between the gate and the narrowest part of the channel on the drain side. C,, on the other hand models the capacitance to the source side. On the source side, the gate capacitance changes with the depletion region thickness, but it is effectively modelled as a single capacitor C, in series with a charging resistance Ri.
Not all current from the drain and source is able to be modulated by the gate. In particular at high drain voltages electron confinement decreases and current through the substrate can occur yielding an output conductance. The output conductance of the device
is modelled as a resistance or conductance between the drain and source, Rds = l/gds. Finally, the capacitive connection between drain and source (usually through the substrate) is modelled as Cds.
The above model was developed for MESFET characterisation but is easily used to model HEMTs. All elements have the same meaning except for the gate capacitance because in a HEMT there is not a depletion region in the same manner as in a MESFET. Instead of a classical depletion region of varying thickness, the density of the 2DEG under the gate varies with position.
5.3.2 Extraction of Intrinsic Circuit Elements
Once the S-parameters of the intrinsic device are known, the elements of the intrinsic model, g,,, gd,, Cgs,Cgd, Cds, Z, and Ri, are readily determined. The relationship between the S-parameters and the intrinsic elements was first elucidated by Minasian [ll7] who was able to achieve good agreement between modelled and measured data to 10 GHz on GaAs MESFETs. For this extraction technique the S-parameters are converted to Y-parameters and directly related to elements in the equivalent circuit. Because of this, this technique has become the most popular method to extract the intrinsic circuit and has been extended for models of greater complexity [118- 1201. For the intrinsic circuit shown in Figure 5-2 the circuit elements are related to the intrinsic Y-parameters at each frequency, o,as follows [116, 1211:
y22 = gds + jW('ds + 'gd )?
where D = 1 + w 222C,Ri .
The real and imaginary parts of Equations 5-3 to 5-7 can be rearranged to allow determination of each of the intrinsic elements [121]: The seven elements of the intrinsic equivalent circuit can be unambiguously determined once the S-parameters of the intrinsic circuit are known. Note that the above method is explicit and there are no fitting parameters needed in circuit determination.
5.3.3 Extraction of Extrinsic Circuit Elements
Determination of the intrinsic circuit elements in the above manner is relatively straightforward once the S-parameters for the intrinsic circuit are known. However, before the intrinsic circuit can be determined, the effect of the parasitic inductances (L,, Ld, Lg) and parasitic resistances (R,, Rd, Rg) must be removed. In fact, extraction of accurate and meaningful parasitic resistances is one of the most difficult issues in equivalent circuit extraction.
As described earlier, the parasitic inductances associated with the ohmic contacts are effectively included with the short measurements of the dummy pads. Determination of the parasitic resistances though is much more problematic. Some have proposed the use of DC measurements to determine the parasitics but these techniques assume these DC values apply to RF device behaviour. This is particularly important because the resistances may have a distributed nature which can lead to large discrepancies. For
example, for a statically measured gate resistance Rg,~c,a value of Rg,~~= Rg,~~/3 is typically used for RF measurements to account for the distributed nature of the gate contact. Others have used optimisation programs to determine the extrinsic resistances [122]. These programs start with seed resistances (theoretical or determined through DC measurements) and use optimisation routines which vary the parasitic resistances to give the closest match to the measured S-parameters. The primary problem with this technique is that numerically optimised solutions do not necessarily correlate to physically realistic solutions, and may get trapped in local minima.
5.3.3.1 Typical ColdFET Extraction
The most robust method for determining the parasitic resistances of the equivalent circuit is through "ColdFET" measurements as first described by Diamant and Laviron [123]. The ColdFET method utilises high-frequency S-parameter measurements with
specially biased transistors. Devices are normally biased with Vds= 0 V (hence "cold") and with the gate-source junction forward-biased with V,, - +2 V for most nitride devices. The principle behind this technique is that when strongly forward-biased, the gate capacitances present negligible impedances, leaving only resistances and inductances in the FET equivalent circuit model. Dambrine et al. [I161 demonstrated that this technique can be used to extract accurate equivalent circuits for GaAs MESFETs up to 26.5 GHz. The use of ColdFET measurements has been the most popular method to characterise high-frequency parasitic resistances, however, this technique is highly dependent on the level of forward biasing. If the device is not forward-biased enough then the reactive nature of the gate cannot be ignored; but the required bias level is not always obvious. Secondly, even if a suitable forward bias can be determined it may result in irreversible damage to the DUT. Many HEMTs, such as InP-based devices, cannot withstand the forward biases required for accurate determination of the parasitic resistances. For the All-,Ga,N/GaN HEMTs in our laboratory, we found that subjecting devices to high forward biases resulted in degradation of the Schottky diode ideality. This brings into question whether the ColdFET results directly correlate to healthy, well- behaved devices.
5.3.3.2 Miras-Legros ColdFET Extraction
In order to overcome the difficulties in conventional ColdFET measurements outlined above we used a technique based on the work of Miras and Legros [124] where the ColdFET forward bias is limited and the effect of the gate reactance is accounted for.
In this method the cold bias of Vds= 0 V is still used but much smaller forward gate biases are acceptable.
Since the inductances are previously subtracted in our methodology, the Z-parameters of the ColdFET measurements are given as follows [124]: ext ext Rch ZI2 = Z21 =' R, + -, 2
where Cgch is the parasitic capacitance under the gate, Rgch= nkTlqI, is the Schottky dynamic resistance, and Rch is the channel resistance under the gate.
z has the only frequency dependent elements which must be fitted. Re(z~~) and 1m(z;~) have the following forms:
At high-frequency, 1m(z;p) determines the value of c = Cgchin 5-19. Knowing
Cgch the frequency response of Re(z;') determines the value of b = Rgch. Once determined, 5-15, 16 and 17 yield three equations in four remaining unknowns: Rs, Rd, R,, and Rch. In the case of A1l-xGaxN/GaNHEMTs in particular, the parasitic resistances Rs, Rd are very high because of the significant contact resistances relative to other semiconductors. In addition, the devices examined in this dissertation had small gate lengths so the channel resistance is also expected to be small. For this reason, Rch does not figure importantly into the results as it is swamped by the other values. Indeed, estimating a reasonable value of Rchshows that its impact on the other parameters is very small. Even doubling the value of Rchbeyond what would otherwise be expected changes the values of Rs and Rd by less than 3%. Thus, the parasitic resistances, Rs, Rd, and R,, can be determined from the Z-parameters of the extrinsic device using Equations 5-1 5, 5-1 6, and 5-17. Figure 5-3 shows extracted values of Rs, Rd, and R, as a function of forward bias and demonstrates this methods superiority to conventional ColdFET measurements. The extracted resistances are largely insensitive to the degree of forward bias, as well, the -0.5 0 0.5 1 1.5 2 2.5 3 Forward Gate Bias V (V) gs
Figure 5-3: Extraction of Rs, Rd, and R, using Miras-Legros method. Extracted values have weak dependencies on the degree of forward bias.
resistances can also be calculated for very low biases, avoiding the possibility of device damage.
5.3.4 Equivalent Circuit Simulation
After calculation of pad capacitances, inductances, and parasitic resistances the intrinsic circuit elements were calculated with Equations 5-8 through 5-14 yielding a fully determined AlI..,GaXN/GaN HEMT equivalent circuit. Table 5-1 shows the extracted circuit elements for a 0.23 pm x 50 pm device with Lgs = 1 pm, and Lgd= 3.6 p.m. The bias for this extraction was chosen as that with optimal frequency response as indicated by the highest fT value. Figures 5-4 (a) to (d) show the frequency response of the extracted parameters. For most parameters the extracted value was chosen as an average between 10 and 30 GHz. The extraction quality was examined by simulating the S-parameters of the equivalent circuit and comparing the results to the raw measured S-parameters. The best way to compare S-parameters is by plotting them on a Smith chart (which is a plot of normalised complex reflection coefficient overlaid with an impedance and/or admittance grid). The Smith chart of Figure 5-5 demonstrates the S11, S12, S21,and S22fit quality of the simulated equivalent circuit data to the measured results. This shows that the modelled S-parameters closely follow the behaviour of the measured device. For the device in question here the modelled results give an fT of 61.3 GHz compared to the measured value of 61.0 GHz. This excellent agreement was typical of all equivalent circuit extractions we conducted.
Table 5-1: Extracted intrinsic circuit elements using ColdFET values of Rg = 20 0, Rs=30Q andRd=48LR.
I Circuit Parameter Value I 2 0 25 Frequency(GHz) Figure 5-4 (a): Transconductance (g,J and output conductance (gt1&frequency response extractedfrom the sample device.
Frequency(GHz) Figure 5-4 (b): Frequency response of extracted equivar'ent circuit capacitors (C@, Cgd, and C&. Frequency (GHz)
Figure 5-4 (c): Frequency response of extracted z value for sample device.
Frequency (GHz)
Figure 5-4 (d): Frequency response of extracted Rivalue for sample device. Figure 5-5: Smith chart demonstrating qualityoffit for ColdFET extracted equivalent circuit. The modelled SZ is Iziglzlighted in red.
5.3.5 Questions Surrounding Equivalent Circuit Results
Despite the overall good agreement there was a slight discrepancy in S22 where the measured data appears to be following a tighter circle than the modelled results; this is highlighted as the red line in Figure 5-5. S22 represents the impedance into the drain side and the tighter circle indicates the resistive component on the drain side may be higher than the model indicates.
Pulsed I-Vresults in Chapter 4 indicated that the applied bias strongly affects the behaviour of the access (gate-source and gate-drain) regions of the devices. In particular, current slump caused a decrease in the effective electron concentrations in these regions. Since the source and drain resistances depend directly on the sheet resistances of the access regions it stands to reason that these values are bias dependent. Table 5-2: ColdFET extracted resistances after 15 minute application of stress biases. ColdFET measurements were done at Vds= 0 V, Vgs= +I V.
Stress Bias Source Resistance Drain Resistance Rs (a) Rd (a)
The bias dependencies of the source and drain resistances are problematic for equivalent circuit modelling because of the assumption that ColdFET results apply across the entire range of operating biases. While the ColdFET results are normally taken with
Vds = 0 V, Vgs = +1-2 V, the actual device operating voltages were quite different. For the
device shown in this section the operating voltage was Vds = 8.0 V, Vgs = -3.8 V where the access resistances may be quite different than those determined at the ColdFET bias.
To test the applicability of the ColdFET determined parasitic resistances, Rs and Rd, measurements were made immediately after application of aggressive stress biases. The purpose of this measurement was to determine whether the bias previous to the ColdFET measurement affected the values of the extracted resistances: In other words, we tested whether or not the device parasitics maintained a memory of previous bias conditions. To this end, a stress bias was applied to the device for 15 minutes. Immediately following the stress bias the setup was reconfigured to take ColdFET
S-parameter measurements with Vds = 0 V and Vgs = +1 V. Table 5-2 demonstrates how the extracted ColdFET resistances vary with the initial stress bias. The data shows that aggressive stress biases resulted in larger ColdFET extracted resistances, reflecting the effects of slump. This test was far from accurate because of the time delays involved. After removal of the initial stress bias the reconfiguration of the biasing circuit took - 15 s after which the ColdFET measurement cycle took another 45 s, this gives significant time for memory of the previous stress bias to be lost. Also, pulsed measurements indicated that positive gate biases tended to aid in the removal of slump. Therefore, at least two mechanisms worked to reduce the manifestation of bias memory in the present measurements. The fact that we still observed memory effects strongly suggests that ColdFET-determined resistances do not reflect the resistances experienced by devices under active biasing. We now turn to the development of a reliable at-bias extraction method for the equivalent circuit model.
5.4 HotFET Extraction of the Source and Drain Resistance
The limitations of ColdFET determination of the parasitic resistances, Rs and Rd, have so far been completely ignored in the GaN literature. ColdFET determination of Rs and Rd is commonly used in equivalent circuit extraction of All-,Ga,N/GaN HEMTs and the assumption that the ColdFET extracted values apply to all biases is widely accepted in the field [125, 1261. However, our ColdFET measurements after stress biases demonstrate that this assumption is incorrect for GaN-based devices when they demonstrate slump effects. Since, as seen in Chapter 4, the degree of slump depends on the applied bias, a method must be utilised which extracts the parasitic resistances at each operating bias. This kind of "HotFET" or "at bias" extraction elucidates important effects otherwise missed by conventional ColdFET methods.
DC techniques [I271 have been utilised to determine hot values for the parasitics, however, as demonstrated in Chapter 4, the slump characteristics of All-,Ga,N/GaN HEMTs during DC and RF operation are very different, therefore, DC values of Rs and Rd are of questionable validity in high-frequency modelling.
While techniques which use pure optimisation to measured S-parameters can lead to invalid element values, others have achieved good results using hybrid methods utilising direct measurement and optimisation together. In particular Campbell et al. [128, 1291 and Shirakawa et al. [130] directly extract the intrinsic circuit elements while using an optimisation routine to determine the parasitic resistances. In these schemes the central assumption is that the equivalent circuit elements should be frequency invariant and the optimisation routine is based on adjusting the extrinsic parasitics to minimise any variation. With this technique they were able to achieve good agreement with measured S-parameters to 40 GHz and 62.5 GHz respectively. However, using these techniques, the drain resistance could vary wildly, even achieving negative values [129].
The HotFET method utilised in this dissertation is based on the work of Manohar et al. [I311 whereby the parasitic resistances are self-consistently determined from measured S-parameters without optimisation techniques nor assumptions about the frequency invariance of the extracted parameters. The parasitic resistances, R, and Rd, are directly extracted from the measured S-parameter data.
5.4.1 HotFET Extraction of the Source Resistance
The first step in directly determining the parasitic resistance, R,, while actively biased, is relating the measured S-parameters to the parasitic elements. To accomplish this, we examine the Z-parameters of the intrinsic circuit as follows:
ext - Y12 z12 = z12 - R, - joL, = , Y11Y22 - Y12Y21
ext - Y21 z~~= z~~ - R, - joL, = (5-21) YllY22 - Y12Y21
Here 212, ~21,y11, y12, y21, and y22 correspond to the intrinsic circuit, while z,","' and z;:' correspond to the extrinsic, measured Z-parameters. The right hand sides of Equations 5-20 and 5-21 are just the standard Z to Y conversion equations.
Equating the denominators of Equations 5-20 and 5-21 and substituting values from Equations 5-3 and 5-5 yields Figure 5-6: Noisy source inductance extraction from hot 2-parameters using Equation 5-23. An assumed value of z = 1 ps is used here.
Note that in arriving at Equation 5-22 we have assumed that oRiCgs(( 1. Indeed, this term is typically less than 0.05 for our devices.
By equating the real and imaginary parts of Equation 5-22 we obtain two equations which eventually allow the determination of R,:
where X, = {sin(wr)[Irn(z;~)- 1rn(zgt)l+ cos(wr)[Re(z~')- Re(Z;;')]}
where X2 = w {cos(Wr)[Irn(z~~') - Im(z;;f )b sin(wr)[~e(z;;~) - Re(z;;' )] } o 5 1013 1 1014 1.510'~ 210'~ 2.5 10l4 3 1014
x2 Figure 5- 7: Extraction of the source resistancefrom hot 2-parameters using Equation 5-24. An assumed value of z = 1 ps is used here.
~m(z~) Plotting vs. & in Equation 5-23 yields a slope of 5 and an intercept CL) gmo of L,. A plot of ~e(z;;') vs. & in Equation 5-24 yields the same slope but an intercept of Rs. The plot of our data fit to Equation 5-23 was extremely noisy and is shown in Figure 5-6. Note that the slope of the line is not obvious, nor does extrapolation to the y- intercept lead to an obviously distinct value of L,. The slope of the plot in Figure 5-6 also varies greatly depending on which frequency range of data is used. However, the value of L, is unimportant as we were able to accurately determine it from short-circuit measurements of the contact pad. It is the determination of Rs from Equation 5-24 which is the critical piece of information from this analysis. Figure 5-7 shows Equation 5-24 plotted in order to determine Rs for an All-,Ga,N/GaN HEMT fabricated in our lab. z was assumed with an initial setting of 1 ps and Rs was determined to be 34 !2 as labelled from the intercept. 5.4.2 Hot Extraction of the Drain Resistance
Once a value for Rs is known it is possible to calculate a corresponding value of Rd. In order to calculate Rd we see from equation 5-4 that the real part of the intrinsic yl2 is zero. By using the Y to Z-parameter conversion we get the following:
Note that the Y and Z-parameters here are for the intrinsic device. In order to get the intrinsic Z-parameters we must first subtract the parasitic resistances and inductances,
R, jwL, [zll 2121 = [2:' z:lt ] - [R, + R, + jw(~,+ L, ) + . (5-26) 221 222 zgt zgt R, + j wL, R, + R, + jw(L, + L,) I
At this point, the parasitic elements are all known except for Rd. Once Rs, R,, L,, Ld, and L, are subtracted from the Z-parameters it is possible to determine Rd by substitution of 5-26 into 5-25. These equations yield Rd as follows:
Here the primed Z-parameters are those that result from the removal of Rs, R,, L,, Ld, and L,. Once these parasitics are determined it is possible to directly calculate Rd without any fitting requirements. Figure 5-8 shows Rd as a function of frequency using
Rs = 34 SZ from Figure 5-7, in this case Rd is approximately 200 SZ. Frequency (GHz) Figure 5-8: Extraction of the drain resistance from hot 2-parameters as in Equation 5- 2 7. R, = 34 LRfrom Figure 5- 7.
5.4.3 Determination of zfor Rs and Rd Extraction
The basic equations for the calculation of Rs (5-24) and Rd (5-27) are now known, however, unlike Rd, the final determination of Rs requires the use of an unknown parameter, z. It is unclear which value of z in Equation 5-24 gives an appropriate fit of ~e(z,,) vs. z. Since Equation 5-23 and 5-24 plots should have the same slope (Cgd/gmo),Manohar suggests varying zuntil the slopes match. This is not possible for our devices because of significant noise in the plot of Equation 5-23. Even for RF data taken with the highest degree of signal integration possible, the plot of 5-23 was not smooth enough to definitively match slopes with 5-24. Instead, an alternate technique was utilised to determine the appropriate value of zfor the Rs extraction.
To determine z, an initial value qnitial = 1 ps was chosen. With this value of z we calculated Rs from the intercept of 5-24 (as in Figure 5-7). Knowing Rs we were then able to subtract it from the Z-parameters and determine Rd from Equation 5-27. With all extrinsic parasitics determined we then calculated the intrinsic elements g,,, gd,, Cgs,Cgd, Cds, Zfinal,and Ri (Equations 5-8 to 5-14). If the original, assumed value of Zinitial was correct then it should match the extracted value zfinal.If the two values did not match then a new value of qnitialwas chosen, closer to the extracted zfinal.This process was continued until the difference between qnitialand zfinalwas minimised.
The total cycle of hot parameter extraction is outlined in the flow-chart in Figure 5-9. The process is divided into six main steps:
(1) De-embedding of the pad capacitance. Gives extrinsic device Z-parameters. (black)
(2) Determination of parasitic inductances, L,, Ld, and L,. (blue)
(3) ColdFET determination of R,. @ink)
(4) Hot determination of Rs and Rd. (red)
(5) Hot determination of the intrinsic circuit elements. (green)
(6) If zfinal# qnitialthen step 4 is repeated with a new value of Gnitial.
It is worth noting that z is not a fitting parameter. z is varied only to ensure self- consistency, not quality of fit. This results in a direct extraction of hot equivalent circuit elements compared to other types of analysis which rely on optimisation routines.
One may question the use of ColdFET R, values in the equivalent circuit when we have argued that this is inappropriate for Rs and Rd. However, R, is fundamentally different from Rs and Rd because it is related to the resistance of the gate finger metal stripe and the metal-semiconductor interface quality which should be independent of slump. For this reason, ColdFET results for R, should be valid for the hot measurements. R, and Rd on the other hand depend directly on the resistance of the semiconductor active region and so must be modelled hot. Indeed, using ColdFET modelling of R, has been incorporated successfully in fit-based hot modelling [132]. Measure Hot S-Parameters - Measure pad S-parameters for Measure ColdFET Convert to Y-parameters.+ "Short" - convert+ to Z. S-parameters -+ Convert to Y Measure pad S-parameters for Dcterminc L,, Ld,and L, Determine extrinsic "cold" "Opcn" - convcrl to Y J (Equations) Y-para~nctcrsby subtract~ng + pad capacitanccs (Open) from Determine extrinsic parameters. De-cmbcd pad Calculatc R, (Equation 5-1 5) capacitanccs (Opcn) from the hot valucs. (Equation 5- 1). Convert to Z
v -, Choose input value ?,,,,,,I for R, plot. + Determine R, ftom intercept of Rd,R,,, L,, Ld,Lg from extrinsic cxt Z-parameters to gct intrinsic Re( ZI2) VS. (Equation 5- & Z-parameters - Con\/crt to Y 24) + Subtract R,, R,, L,, LdLC from Calculate intrinsic elcn~cnts,g,,. Z-pararnetcrs to gct 2'- paranlctcrs. .c I Determine Rd (Equation 5-24) ,
R, and Rd.
Equivaletit circuit is correct
Figure 5-9: Extraction procedure flow chart for hot determimction of the entire equivalent circuit. 5.4.4 Hot Circuit Extraction Results
5.4.4.1 Equivalent Circuit Results and S-parameter Agreement
In order to verify the effectiveness of this extraction process we simulated S-parameters for a hypothetical device with full parasitics included. Once the S-parameters were created we used the procedure above to extract the equivalent circuit values. Using these techniques we were able to extract the original equivalent circuit element values of the hypothetical device without any prior knowledge of their magnitudes. Since this process was a direct extraction and not an optimisation, we were able to extract the original equivalent circuit elements with perfect precision. This success demonstrates the effectiveness of this procedure in analysing the equivalent circuit diagram in Figure 5-2(a).
The results in Figures 5-7 and 5-8 are typical extraction results for Rs and Rd. Those results represent an Alo,3G~.7N/GaNHEMT with barrier thickness of 220 A over a 1 pm GaN channel and electron mobility of 1070 cm2/V-s. When self-consistent, the extracted z value is typically - 0 ps. A full extraction of all the hot equivalent circuit parameters with these parasitic values is shown in Table 5-3; the ColdFET extracted values are shown for contrast.
Note that there is very little consensus on the physical meaning of z. Some have
set z as the ratio of gate length and saturated velocity, but measurements show z does not directly scale with gate length [133]. It has been argued through simulations that z is a meaningless parameter and instead should be ignored with the addition of other capacitances to the equivalent circuit [134]. Ladbrooke, on the other hand, argues that z is related to the transit time across the drain extension of the depletion region [133, 1351. Ladbrooke's interpretation is consistent with our delay time analysis results, shown later in this chapter, which indicate a drain delay of zd - 0 ps. In any case, the final value of z Table 5-3: Intrinsic circuit elements using ColdFET values and "HotFET" extraction at operating bias. Pad inductances and capacitances were the same for both devices.
Circuit Parameter ColdFET Value HotFET Value
extracted from equivalent circuit analysis is based entirely on internal consistency with the initial assumed value, so the result of z- 0 ps is not too troubling.
Note also that the Cgd/gmoratio for the HotFET result is 1.4 x 10'13 ~42which is in good agreement with the slope of the R, determination plot (Figure 5-7) which yielded 1.6~10-l3 F.Q.
In order to examine the efficacy of the HotFET extraction technique, the extracted circuit was simulated and compared to the measured data as shown in Figure 5-10. The agreement between the hot extraction and measured data was superior to that of the cold extraction shown previously in Figure 5-5. The cold extraction yielded a fit error of Figure 5-10: Smith chart demonstrating quality offitjk HotFET extracted equivalent circuit (black). The ColdFET modelled SZ is overlaid irz red for comparison. Notice the superior match in SZ2for the HotFET result.
1.6 % compared to only 1.2 % for the hot. The difference is especially apparentin the match to S22 where the HotFET result largely resolves the mismatchoriginally seen in the ColdFET values. This improved match can be directly attributed to the larger value of Rd extracted using the hot methodology.
5.4.4.2 Variation of Parasitic Resistances with Bias
The ColdFET quality of fit was further degraded compared to the hot measurements at higher biases. The superior outcome from hot modelling of the transistors resulted entirely from the bias dependent nature of the source and drain resistance. When these parasitic resistanceswere determined through ColdFET modelling the same values of Rs and Rd were used in the extraction procedure, regardless of 4 6 8 10 12 14 16 Drain-Source Voltage V (V) ds Figure 5-11: HotFET extracted Rs and Rd as a function of Vh with Vgsheld constant at Vgs= -4.2 K operating bias. This is effective when the parasitics are bias independent but as shown here, this is not the case when devices suffer the effects of slump.
Figure 5-1 1 shows the variation of the source and drain resistance for a HEMT operating with different drain voltages. As the drain voltage increased from 6 V to 15 V there was a dramatic increase in Rd from 240 R to 490 R. In this case, the source bias was held constant at Vgs= -4.2 V and the source resistance was largely flat, only increasing from 33 R to 40 R.
Figure 5-12 shows the variation of the parasitic resistances for constant drain voltage (Vds= 8 V)and varying gate voltages. In this case the source resistance increased from - 30 R to 125 R as Vgswas swept from -3.8 to -4.8 V. The drain resistance also showed a significant increase, going from 250 R to 5 15 R over the same Vg,sweep.
In light of the work in Chapter 4 these results seem reasonable and can be explained as follows: For the results in Figure 5-1 1, the increased drain voltage would be 600 -
500 - -
400 - -
300 - -
200 -
- R 100 S - -_-__ - - - I I I I I I I I I I I I I I 0 -5 -4.8 -4.6 -4.4 -4.2 -4 -3.8 -3.6 Gate-Source Voltage V (V) gs Figure 5-12: HotFET extracted Rs and Rd as a function of V,, with VdFheld constant at v*=sv. expected to yield a significant increase in the field on the drain side of the gate. This increased field in turn led to current injection from the gate metal into the gate-drain region. These injected charges were trapped in the gate-drain region resulting in a decrease of the 2DEG charge density, manifesting itself as an increase in the drain resistance. For higher drain voltages the gate-drain field, charge injection, and slump were enhanced, resulting in increasing drain resistance with Vd, as demonstrated in Figure 5-11.
The results in Figure 5-12 show that for increased gate-source voltage both the drain and source resistances increased. In particular, they increased as the bias approached the threshold voltage. The increase of the source resistance confirms the earlier pulsed results which indicated that source side slump is an important effect in the operation of AlI,GaXN/GaN HEMTs because otherwise one would expect the source resistance to be bias independent. Note also that it is the gate-source voltage which induced the increase in Rs,not the drain-source voltage. This is also in agreement with our pulsed results which showed that the gate-source bias induces a stronger slump effect than the gate-drain bias.
5.5 Delay Time Analysis and Effective Velocity in All_,Ga,N/GaN HEMTs.
Examining the high-frequency performance of FETs can lead to understanding of the behaviour of electrons as they pass through the device. In the case of Al1,GaxN/GaN HEMTs this is a particularly contentious issue as there is wide disagreement between theoretical predictions and experimental results. For example, Monte Carlo simulations of All-,Ga,N/GaN HEMTs have predicted extremely high peak electron velocities which have not been matched by experimental results. Kolnik et al. have predicted peak and saturated velocities of - 2.5 x lo7cm/s and 2 x lo7cm/s respectively for bulk GaN [136]. For Alo,3G~.7N/GaNheterostructures, Yu et al. have predicted peak and saturated velocities of - 3.2 x lo7 cm/s and 2.6 x lo7 cm/s [137]. These results significantly surpass extracted velocities for working A1l.xGaxN/GaN HEMTs which have typically yielded values in the range of 1.2 - 1.3 x 1o7 cmls [138, 1391. One might argue that a HEMT has a significant spatial variation in the electric field and electrons would not be expected to travel at the peak or saturated velocity throughout the entire device. Since Al1~,GaxN/GaNchannels show relatively low electron mobilities compared to standard 111-V HEMTs, and with high peak velocity electric fields (-140 kVIcm), it seems reasonable to expect that a significant region of the channel operates below vSat. While this is true, one must note that when devices are biased for optimal frequency response the average field under the gate will be distributed around the value achieving highest average velocity. An example of this is found in results by Singh et al. [140], who have conducted Monte Carlo simulations of a 0.25 pm device using a velocity-field distribution with a peak velocity of 2.5 x lo7 cds. Their result gives an overall effective velocity under the gate of - 2.2 x lo7 cm/s which is still significantly higher than 1.2-1.3 x 1o7 cm/s experimentally determined from high-frequency measurements. A common estimate of the effective velocity is made by using the total delay time
(htd = 112.nfT) and the gate length, L,. This approach is far too simplified if one wants to determine the true effective velocity in nitride materials. In order to resolve the difference between the theoretically expected and measured velocities we have made delay time analysis measurements on our Al1,GaxN/GaN HEMTs. The purpose of delay time analysis is to separate the total delay time into separate components related to electron motion in the active region of the device.
5.5.1 Delay Time Analysis Principles
Delay time analysis is based on the work of Moll et al. [141] which demonstrated that the total delay time can be divided into three basic components,
1) zt,,, is the total delay time and is determined as 112.nfT.
2) z;,t is the intrinsic delay time. This is the time required for an electron to traverse the physical dimension of the gate.
3) TRC is the RC charging delay time. As the gate voltage changes, the channel charge distribution changes. To move charge in and out through an element that behaves as a capacitor yields an RC delay.
4) ~d is the drain delay time. At drain biases past saturation the depletion region is no longer totally confined under the physical dimensions of the gate. As the drain bias increases the depletion region encroaches into the gate-drain region. zd is the time required for electrons to traverse this extra region. Inverse Current 11 d Figure 5-13: Zdealised charging delay plot showing how extrapolation allows for determination of ZRC and G,,, + zd
The division of the total delay time into these three elements requires examining the total delay time under different bias conditions. An idealised example of a charging delay plot is given in Figure 5-13. In this plot qOt,l is given as a function of the inverse drain current (l/Id). Each measurement of Id is taken for a single value of Vds, but for varying values of Vgs. The change in current represents gate modulation of the channel. Since Vds is fixed, the extension of the depletion region into the gate-drain region should not change so zd is expected to be constant. Also, small changes in Vgs do not make large changes in the velocity profile of electrons under the gate so qnt should be constant. For example in [I401 the velocity profile under the gate does not significantly change between Vgs = -2 V and -4 V. However, the channel resistance may show great change for high gain devices even for moderate changes in Vgs. For this reason the increasing trend in Figure 5-13 represents degradation in the RC delay as the channel resistance gets larger with increased gate reverse-bias. Extrapolating the line to l/Id = 0 is imagining that
Id= 00 (i.e. the channel resistance is 0). Therefore, the y-intercept is the delay time with 5 +T int RC
Channel Voltage V,, = VdS - I,(R + R ) s d Figure 5-14: Zdealised drain delay plot demonstrating how extrapolating to VA = 0 yields zd and qnt+ z~c.
ZRC = 0 and so represents qnt + zd. The difference between the intercept and each data point is the charging delay at each individual bias.
In order to determine the drain delay, one examines the variation in the total delay with the channel voltage. To determine the channel voltage, Vch, one simply removes the voltage drop across the parasitic resistances.
Here then Vch represents the voltage gain from the source side to the drain side of the depletion region.
An idealised drain delay plot is given in Figure 5-14 showing the variation in zt,td as a function of Vch.A similar explanation applies to the drain delay as with the charging delay. When the channel voltage is increased the depletion region pushes further into the gate-drain region resulting in an increase to the delay time, zd, required to traverse it. Smaller channel voltages create smaller drain extensions and ultimately, for a channel voltage of Vch = 0, there is no extension of the depletion region toward the drain. The y- intercept at Vch = 0 is the delay time with zd = 0 and represents qnt + z~c.The difference between the best bias and the y-intercept represents the drain delay at that bias.
Having determined the charging delay and the drain delay at the optimal bias, the intrinsic delay is simply found from Equation 5-28. Since the intrinsic delay represents the time required for an electron to transit beneath the physical gate, the effective electron velocity is easily determined as v,~=Lglqnt.
5.5.2 Delay Time Measurements of Wet-etched Devices: ColdFET Parasitics
The material used in this analysis consisted of piezo-doped Alo,36G~.74N/GaN HEMTs grown by MOCVD on sapphire. The A10.36G~.64Nbarrier was 200 thick and the structure yielded a 2DEG density of 1.7 x 1013 ~m-~with a mobility of 1,070 cm2/V.s. Samples were wet-etched in a K2S2O8solution as outlined in Chapter 3. 0.2 pm Ni/Au gates were fabricated by electron beam lithography and the ohmic contact resistance was - 1 CI-rnm as determined through TLM measurements.
The gates were fabricated to conform to a very small range of gate-source spacings and varying gate-drain spacings. The gate length was constant at 0.20 k 0.01 pm as measured with the SEM. The gate-source spacing was 1.0 h 0.1 pm and the gate-drain spacing fell in a broad range of 0.5 < Lgd< 4.5 pm. Devices were 50 pm wide.
In order to determine fT, high-frequency S-parameter measurements were made for a wide range of gate and drain biases. Figure 5-1 5 shows a sample charging delay plot of qod vs. l/Id (with qot,l = 1/2nfT). The delay time behaviour is linear for low values of Id as expected, and easily extrapolated to l/Id = 0. In the example of Figure 5-15 the intercept is determined to be qnt + zd = 3.97 ps. The charging delay, as indicated on the plot is found to be 0.53 ps. Note, these delay times correspond to the optimal bias which was found to be Vds = 13 V and Vgs = -4.5 V. 11111111111 11111111111111111
0 0.5 1 1.5 Inverse Current 111 (llm A) d Figure 5-15: Charging delay plot for a wet-etched device. Parasitic resistances were ColdFET extracted as Rs = 31 0and Rd = 72 l2
0 5 10 15 2 0 Channel Voltage Vch= Vds- Id(Rs+ Rd) (V)
Figure 5-16: Drain delay plot for a wet-etched device. Parasitic resistances were ColdFET extracted as Rs = 31 0and Rd = 72 l2 In this case, R, and Rd were extracted using ColdFET measurements in order to
determine the channel voltage as in Equation 5-29. The drain delay plot of Gota, vs. Vchis shown in Figure 5-16. This data also shows a linear behaviour at high Vch values, indicating that the depletion region is extending into the gate-drain region. The y-
intercept yields a value of ZRC + Zint = 3.83 ps and zd = 0.67 ps. Since zd and ZRC were
determined, the intrinsic delay time is easily found to be qnt = 3.30 ps. It might seem
natural then that the effective electron velocity is 0.2 pm 1 3.30 ps = 0.6 x 10' cmls. However, we found the determination of the effective velocity to be complicated by the high parasitic resistances.
The above delay time analysis procedure was conducted for a number of devices of varying gate-drain spacing. These results showed that increasing the gate-drain spacing caused a significant increase in the intrinsic delay time while leaving the drain delay and charging delay largely invariant. A more meaningful representation of these results is
r Orint
0 2 0 40 6 0 80 100 120 Total Access Resistance R + Rd (a) S
Figure 5-1 7: Delay times for wet-etched devices with different parasitic resistances. Extraction to Rs+ Rd = 0 yields a true intrinsic delay time. shown in Figure 5-17 where the qnt, ZRC,and zd are plotted against the total parasitic access resistance, Rs + Rd.
As seen in Figure 5-17, the drain delay and charging delay were not dependent on the parasitic resistances. The implication for zd is that the depletion region did not extend through the entire gate-drain region to the drain contact or else we would see zd increase with (Rs + Rd). This result is typical of FETs in most material systems, however, based on electroluminescence measurements others have argued that the depletion region in All-,GaXN/GaN HEMTs extends all the way to the drain contact [142]. Our drain delay measurements show that this huge drain extension does not occur. A simple calculation renders this kind of extension impossible as one would note that for Lgd= 4.5 pm the time for an electron to traverse a depletion region this wide would be - 15 ps even if travelling at a peak velocity of 3 x lo7 cds. Such a delay would mean that any device with Lgd = 4.5 pm could never achieve more than - 11 GHz in performance, much less than the 38 GHz demonstrated by our devices with that spacing.
A weakness in the methodology outlined by Moll et al. [141] is that it does not consider the impact of the parasitic resistances on the extracted delay times. Normally this is not an issue as the parasitic resistances are low in most HEMT technologies. However, for high resistance GaN-based devices it is important to account for the significant parasitics. It is clear (as seen in Figure 5-17) that the parasitic resistances have a strong impact on the intrinsic delay time. Since we are interested in the delay time of the true intrinsic device, this would necessitate calculating qnt for Rs and Rd of zero. The extrapolation of the qnt plot to (Rs + Rd) = 0 gives the true transit time for the intrinsic device, qrmsit= 0.61 ps. From this extracted transit time we calculated the effective electron velocity under the 0.2 pm gate to be - 3.3 x lo7 cds [144]. At the time, this result was very satisfying as it closely agreed with Monte Carlo predicted results and represented the first extraction of electron velocities beyond the typical values of 1 x lo7 cds.
There are however, some problems with the above results. The first issue is purely conceptual. If the intrinsic delay time is truly intrinsic then one would expect that it would be independent of the extrinsic parasitic values, i.e., when the electron is travelling under the gate how does it know what resistance values are attached to the exterior of the active region? However, the greatest concern in these results relates to the slope and intercept of qOtalvs. (R,+ Rd)as shown in Figure 5-1 8.
Extracting hzl from the equivalent circuit diagram shows a relationship between fT and the circuit parameters [143].
In the devices measured here the typical equivalent circuit elements were Cgs= 30 fF, Cgd= 4.8 fF, gm = 9.5 mS, and gds = 0.2 mS. As a result, the expected slope of qOtal vs. (Rs+ Rd)is only 5.6 fF from Equation 5-31. Howe>"er,the slope from the measured
Tasker Prediction
40 6 0 SO Total Access ResistanceR +Rd (R) S Figure 5-18: Total delay time as a function of access resistance. The measured total delay time does not agree with Tasker's prediction (Equation 5-31) based on the extracted intrinsic circuit elements. results in Figure 5-18 exhibits a slope of 30 fF, far exceeding the expected value. The "Tasker" line is a plot of Equation 5-31 overlaid with the total delay time measured data for comparison.
A reasonable explanation for the discrepancy between the Tasker prediction and extracted results is that the ColdFET extracted values, Rs and Rd, were too small. In Figure 5-1 8 the data points with the smallest values of (R, + Rd)would show the smallest amplification in their values if extracted through hot measurements while the largest values of (Rs + Rd)would experience the greatest increase. The result of this would be to shift the data points in Figure 5-1 8 to the right, with those of highest (Rs+ Rd)shifting the most. The outcome would be to flatten the curve and decrease the slope to a more reasonable value like that predicted by Equation 5-3 1. However, the unavoidable outcome of this treatment is to decrease the effective velocity from the artificially inflated number determined from the delay time analysis using ColdFET resistances While using hot equivalent circuit values seems logical given that we know ColdFET measurements give artificially low parasitic resistance results, it was the discrepancies in this delay time analysis that actually inspired the work to determine hot parasitic values.
5.5.3 Delay Time Analysis of Implant Isolated Devices: Hot Parasitics
To utilise hot parasitics in the determination of intrinsic delay times we utilised HEMTs grown on Sic with 220 8+ barrier of Alo.3Gao.7Non 1 pm thick GaN. Ohmic contacts were TiIAllAu and gates were NiIAu with gate lengths typically between 0.25 and 0.27 pm. Isolation was by Help ion implantation. S-parameter measurements were made with the longest integration time allowed by the HP8510B to ensure the data was smooth enough to extract values of Rs and Rd.
Two significant changes were made to the delay time analysis of these devices. First, the parasitic source and drain resistances were found via hot extraction as outlined in Section 5.4. Note that this means the source and drain resistances are different for each bias. Secondly, when plotting z in the "charging delay" and "drain delay" plots we utilised the intrinsic values offi.. That is, we subtracted Rs and Rd from the measured 0.5 1 Inverse Current l/Id(l/mA)
Figure 5-1 9: RC charging delay using intrinsicfT and fMfl (with Rsand Rd subtracted). Rs and Rd were determined using HotFET method.
Z-parameters before determiningh. This meant that the delay times truly corresponded to the intrinsic device.
A sample charging delay plot using hot parasitic values is shown in Figure 5-19. This shows the same linear behaviour between z and l/Id seen earlier. In this case, the charging delay was found to be ZRC = 0.2 ps while the value of qnt+ zd was 1.3 ps.
A sample drain delay plot is shown in Figure 5-20. Here we see a significant difference compared to the values determined using ColdFET parasitics. In this case the plot of z was flat with channel voltage leading to a drain delay of zd = 0 ps. This indicates that the drain edge of the depletion region does not intrude into the gate-drain region, or rather, is much smaller that ZRC and qnt. This result is not surprising because of the high 2DEG density in All-,Ga,N/GaN HEMTs. While HEMTs in most material systems have 2DEG densities of - 1012 ~m-~,the All,GaxN/GaN system has - 1013 cmm2so much less material will be depleted into the drain region. 0 5 10 15 2 0 Channel Voltage V = Vds- Id(R + Rd) (V) ch s
Figure 5-20: Drain delay plot using intrinsic fT and fMm (with Rs and Rd subtracted). Rs and Rd were determined using the HotFET method. The lack of drain delay is very clear.
0 5 0 100 150 200 250 300 350 Total Access Resistance R + Rd (R) S Figure 5-21: Effective electron velocity under the gate as determined from delay time analysis. The resistances in these results were determined using the HotFET method. The complete set of delay times for this device was TRC = 0.2 ps, zd = 0 ps, and qnt
= 1.3 ps. For a gate length of L, = 0.24 ym this delay time corresponds to an effective
velocity of v,~= 1.85 x 1 0' cds. We executed this kind of hot delay time analysis on all devices with sufficiently low noise in the data to allow for determination of Rs and Rd at all biases. Using the values of qnt and the various gate lengths we were able to extract values of the true effective velocity in these devices. The variation of v,ff with (Rs+ Rd)is shown in Figure 5-2 1. This demonstrates that the effective velocity of electrons under the gate is independent of the access resistance when HotFET determinations are used thus eliminating one of the objections arising from the delay time analysis in Chapter 5.5.2.
For the hot extraction, the average effective electron velocity was found to be - 1.9 x 10' cds. This is close to the value of 2.2 x 1 0' cdspredicted by Singh et al. [I401 in simulations of devices very similar to those fabricated in our lab. However, our electron velocities still do not reach the same level as predicted by Yu et al. [I371 with peak and
saturated velocities of 3.2 and 2.6 x 1 0' cdsrespectively. Our initial delay time analysis [144] work was followed up by others [125, 145, 1461 who did similar analyses on passivated devices which reduces the significant increase in the parasitic resistances with bias. In this way they minimised the need to utilise hot values of Rs and Rd and their
results of veff= (1.6 - 1.85) x 1 0' cdswere consistent with ours.
The other objection to ColdFET delay time analysis raised in Chapter 5.5.2 was the strong disagreement between the measured and calculated dependence of Gota, with (R, +
Rd). Figure 5-22 shows q0tal versus (Rs + Rd) for a number of devices using the hot
extraction technique. For these devices, average parameters were g, = 15.9 mS, gds =
1.09 mS, C,, = 19.7 fF, and Cgd= 4.26 fF. The red "Tasker" line in Figure 5-22 shows a plot of Equation 5-31 using these elements and demonstrates the excellent agreement achieved using hot extraction results compared to the very poor agreement in our initial measurements show in Figure 5-1 8.
With the average equivalent circuit parameters above, the simple intrinsic delay time estimate of qnt,,St = Cgslgmoyields 19.7 fFl15.9 mS = 1.24 ps. For a 0.24 ym gate this
corresponds to a velocity estimate of 1.94 x 10' cds. This value agrees very well with 100 150 200 250 3 00 350 Total Access Resistance R + R (R) s d Figure 5-22: Comparison of the Tasker prediction with HotFET extracted data. The agreement is excellent contrary to the very poor agreement achieved from ColdFET extraction in Figure 5-18.
the average velocity obtainedthrough the (much more sophisticated) delay timeanalysis. This demonstrates that the simple estimates of effective electron velocityare valid ifand only ifthe parasitic resistances are correctly accounted for.
The level of self-consistency achieved through these measurements isremarkable. Utilising delay time analysis and hot extraction of the parasitic source and drain resistances we were able to extract an effective electron velocityof - 1.9 x lo7 cm/s. This was in close agreement with thevalue of 1.94 x 10' cmls calculated by simple estimates from the extracted equivalentcircuit values. This was all accomplished while yielding the Tasker-predicted dependencies between frequency response and access resistance,giving a high degree of confidence in these results. CHAPTER 6: SUMMARY AND FUTURE WORK
6.1 Summary
The 111-nitrides are an increasingly important materials system for high-frequency and optoelectronic applications. In particular, Al1,GaxN/GaN HEMTs hold great promise for future high-frequency, high power applications. Still, a number of issues limiting the performance levels of these devices remain unresolved. This dissertation has focussed on exploring some of the difficulties associated with All-,Ga,N/GaN HEMTs and supplied some answers to outstanding questions.
6.1.1 Fabrication
The work involved in this dissertation laid the foundations for the fabrication of nitride devices at the SFU Compound Semiconductor Device Laboratory. Ohmic contacts were developed with contact resistances of - 0.5 Qmrn and good edge acuity. A Schottky contact fabrication process was developed which resulted in very low leakage currents, usually in the range of 1 to dm.These results are much better than those achieved by most groups where dmis the norm. We modelled and demonstrated a novel implant isolation procedure which yielded high sheet resistivities of - 10'~-10'~Q/U. We believe this isolation procedure contributed to the low leakage currents in our Schottky contacts. In addition, we developed a T-gate electron beam lithography procedure which allowed for fabrication of devices with gate lengths of - 0.2 pm. Lastly, we also explored the application of photoelectrochemical wet-etching to the fabrication of All-,Ga,N/GaN HEMTs. As a result of these techniques, we were able to achieve cut-off frequencies up to 70 GHz. 6.1.2 Source Side Current Slump
Using pulsed I-V characterisation we were able to examine fast slump effects in All-,Ga,N/GaN HEMTs. We found that while both gate-source and drain-source voltages were able to induce slump, the gate-source bias was more important in determining the level of slump. By using complementary biasing we were able to demonstrate that current slump is not limited to the gate-drain region alone as was previously thought, but may also occur in the gate-source region. In fact, in some instances source-side slump could be the dominant mechanism involved in performance degradation. This is important for a number of applications where devices are driven to threshold.
6.1.3 Passivation
We used 10 minute ozone exposure cycles to passivate the surface of All-,Ga,N/GaN HEMTs. We found that this procedure could passivate slow transients but not fast current slump. This was the first demonstration that trapping states could be controlled separately and pointed to the possibility of different slump mechanisms for fast and slow slump states.
We showed the effectiveness of ultra-thin layers such as ozone oxide, NiO, and a 5 Ni film in passivating slow transients. The success of such thin layers convincingly proves that passivation of slow transients is not related to strain induced by the dielectric as some had proposed [95]. It also excluded electron injection reduction as a viable explanation for passivation 1961. The results of this dissertation support the notion that surface states are directly passivated by the deposited layer.
Our results, taken in context with others [103, 1061, indicate that dislocations are intimately involved in slow current slump transients. Simulations of Kelvin Force Probe Microscopy (KFM) measurements [I071 were made assuming dislocations were uniform line charges. It was found that KFM potential measurements were consistent with each dislocation holding many thousands of charges. Because of these results, a modified virtual gate hypothesis was proposed where depletion zones occur around each dislocation causing lines of current to percolate through arrays of charged dislocations in the access regions. The smaller conducting cross-section results in reduced current, manifesting itself as slow slump transients.
6.1.4 Small-Signal Modelling
An extraction procedure was developed to extract the equivalent circuit model for All-,Ga,N/GaN HEMTs. ColdFET modelling was applied to devices and full equivalent circuits were extracted. Using delay time analysis with these results, we were able to calculate the intrinsic transit time for electrons under the gate and extracted electron velocities consistent with Monte Carlo simulations. In the course of this analysis we discovered shortcomings in the ColdFET extraction technique as they failed to account for slump effects on the parasitic resistances.
A HotFET modelling technique was developed which allowed for the extraction of each parasitic resistance under active bias conditions. We found the source and drain parasitic resistances could diverge strongly from their ColdFET values. In particular, our RF measurements indicated the presence of source side slump near threshold, just as had been seen in earlier pulsed I-V measurements. Using HotFET values for parasitic resistances, we were able to extract equivalent circuits which were very accurate in simulating the measured S-parameters up to 40 GHz.
Using HotFET equivalent circuit modelling, we conducted delay time analysis on unpassivated All-,Ga,N/GaN HEMTs. We found that the drain delay in these devices was smaller than we could resolve, indicating that the depletion region does not extend appreciably into the drain region. The Tasker equation [I431 predicts the correlation between the intrinsic circuit elements, the parasitic resistances, and the total transistor delay time. Using the HotFET extraction technique, we were able to yield excellent agreement with the Tasker equation, contrary to what was achieved using the more conventional ColdFET extraction technique. We were also able to extract the effective electron velocity under the gate and calculated a value of veff- 1.9 x lo7cds. 6.2 Future Work
There is still much work to be done in the optimisation of All-,Ga,N/GaN HEMTs. In particular, some of the work in this dissertation can be expanded in the future.
6.2.1 Passivation
While not perfectly effective, passivation with Si3N4 has become the standard processing technique to minimise the effects of slump. In this dissertation, we studied the effects of slump and so the use of Si3N4passivation was not as critical. However, in the future, Si3N4 passivation will likely be mandatory for the success of nitride device physics at Simon Fraser University. Questioiis remain whether the ultra-thin passivation layers realised at SFU will enhance Si3N4 passivation to achieve improved device performance.
HotFET device modelling should be an effective method to determine the effectiveness of passivation techniques. When fast current slump is minimised the HotFET extracted resistances should tend toward their ColdFET values. The difference between the two can be used as a measure of passivation efficacy. In this way, various passivation techniques can be evaluated.
In addition, the success of ultra-thin layers in passivating slow transients begs the question of what other novel layers will be effective for device passivation. There are many important discoveries to be had in this area.
6.2.2 Slump at Dislocations
Correlating KFM, pulsed I-V, and slow slump measurements of passivated and unpassivated dislocations would provide further proof that slow current slump is caused by charging of dislocations. In addition, KFM measurements of the potential around dislocations at different biases should show greater charging for stronger stress biases. This research could be done in collaboration with other groups. 6.2.3 Schottky Contact Improvement
While we have achieved good Schottky leakage currents it may still be possible to realise improved performance. We have made no reliability studies on our devices and Schottky contact degradation is one of the key areas of concern. It is possible that some of our passivation techniques could enhance or reduce the reliability of the Schottky contacts, but this has not been studied.
Schottky contacts can also contribute to reducing the parasitic drain and source resistances. Even if the contact resistance can be reduced to zero, the source and drain resistance will still be limited by the sheet resistance of the semiconductor and the spacing between the gate and ohmic contacts. To reduce the parasitic resistances one can utilise self-aligned technology with electron-beam T-gates as part of the ohmic contact mask. This minimises the gate-source and gate-drain spacings. However, since the ohmic contacts are fabricated after the gate, fabrication of Schottky contacts able to withstand 850 "C ohmic annealing temperatures becomes necessary. The development of high temperature gates are also of great interest for industrial applications where high temperature environments are involved.
6.2.4 Ohmic Contact Improvement
Even state of the art All-,Ga,N/GaN HEMTs have contact resistances that are very high compared to every other 111-V materials system. One of the primary reasons for poor contact resistances is that implementation of heavily doped cap layers in All-,Ga,N/GaN HEMTs is very difficult because of the lack of effective wet-etch chemistries. If PEC wet-etching techniques could be further refined to allow for reliable, repeatable results then heavily doped cap layers could be realised.
Another method of improving the ohmic contacts could be by implantation of dopants into the source and drain regions. Thermal activation would result in a heavily doped layer under the contacts and reduced resistances. This technique has been attempted [147, 1481 but further improvement is possible. 100 150 200 250 3 00 Total Access Resistance R t Rd (0)
Figure 6-1: Comparison of the Tasker prediction with HotFET extracted data (reproduced from Figure 5-22). The intercept illustrutes the performance level that could be achieved tlzrouglz reduction of the contact resistance.
The effect of ohmic contact reduction is illustrated in Figure 6-1. Our best results for devices shown above had a total delay time of - 2.5 ps, which corresponds to a cut- off frequency of fT = 64 GHz. High contact resistances and current slump both contributed to reduced performance. Ifone can totally remove the effects of the contact resistances, those same layers are capable of achieving a total delay time of 1.5 ps, corresponding to fT = 106 GHz. This demonstrates the high performance levels achievable for optimisedAll-,Ga,N/GaN HEMT devices. References
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