Selecting the Correct CMOS PLD—An Overview of Advanced Micro Devices’ CMOS Plds Advanced Micro Application Note Devices

Selecting the Correct CMOS PLD—An Overview of Advanced Micro Devices’ CMOS PLDs Advanced Micro Application Note Devices

INTRODUCTION A second major benefit of electrical erasability is the ease of reprogramming the device by the user. This The purpose of this application note is to provide a sur- saves time when prototyping, and allows for recovery of vey of AMD’s CMOS PLDs (Programmable Logic De- large volumes of devices that may need to be vices). This includes both PAL (Programmable Array reprogrammed for a variety of reasons, such as mid- Logic) devices and the more general realm of PLDs to production bug fixes. Erasure takes place automatically which PAL devices belong. With the proliferation of by the device programmer, and is completely transpar- parts, the selection of the best PLD for your application ent to the user. may seem difficult. If you are a new PLD user, this overview will guide you through the wide variety of different Low Power device architectures, speed, and power grades. This tu- torial should increase your understanding of the basic The most well-known attribute of CMOS is low power characteristic features that make a device appropriate consumption. All PALCE (Programmable Array Logic for a given application. CMOS Electrically-Erasable) devices are offered in half- power versions; they require at most half the supply cur- Figure 1 shows a “CMOS PAL Selection Route Map.” rent of their first-generation bipolar counterparts. Some This can be used as a convenient model of the discus- devices are also offered in quarter-power versions. This sion throughout this paper. It can also be used as a ref- is achieved by taking the latest process technology and erence guide when you are selecting a PLD for a designing to favor even lower power over the fastest particular application. speed possible. The Benefits of AMD’s CMOS PLDs CMOS uses less current than bipolar because most of the current flow only takes place while the transistors Before addressing individual products, it is important to are actually switching. With bipolar, current flows understand why CMOS technology is used in PLDs. through the transistors all the time. AMD’s half- and There are two universal benefits of AMD’s CMOS PLDs: quarter-power CMOS devices take advantage of this as electrical erasability and low power. much as possible. However, in order to achieve high Electrical Erasability speed it is necessary to operate some transistors on the chip in the linear region. Because this circuitry is essen- Because PLDs are programmable, electrical erasability tially always switching, the power consumption does not is probably the most important advantage that CMOS go to zero as it would in a conventional CMOS device. technology can bring. AMD’s electrically-erasable CMOS has benefits that make it superior to both UV- Lower power requirements are ideal for applications erasable CMOS and bipolar technologies. The most im- which have tight power budgets, such as mobile tele- portant advantage is the ability to erase the device communications. Smaller power supplies also reduce electrically in a matter of seconds as opposed to hours cost and lowers heat dissipation. This results in smaller for UV-based technologies, and not at all in the case of cooling fans, or perhaps no fan at all. It also allows the bipolar. The chief benefit to the user is a very high quality system designer to pack everything even tighter since device. This is realized through the ability to erase and less empty space is needed for air circulation. This can reprogram the device many times at various test points make the circuit board fit in a smaller package, again in the factory. In fact, the quality is so good that program- reducing cost. ming and post-programming functional rejects are virtu- ally non-existent.

Publication# 17402 Rev. B Amendment /0 1-11 Issue Date: February 1996 AMD

Start Here

Global Clocks & Individual Macrocell Resets/Presets Sync or Clocks & Resets/Presets Async Synchronous Design? Asynchronous More Output Drive 16V8HD 15 ns 16V8 20RA10 5/7.5/10/15/25 ns 7/10/15/20 ns Lower Power More Inputs More Flexibility More PTs & I/Os 16V8Z 20V8 12/15/25 ns 5/7.5/10/15/25 ns 610 15/25 ns

More PTs & I/Os Lower Power More Flexibility 22V10Z 22V10 15/25 ns 5/7.5/10/15/25 ns More Inputs 29MA16 25 ns More PTs, I/Os & 24V10 Clocks More PTs 15/25 ns & I/Os 26V12 7/10/15/20 ns MACHTM More Flexibility More I/Os Family Density 5/7/10/12/15/20 ns 610 & 15/25 ns Speed

More PTs & I/Os

29M16 17402B-1 25 ns

More Flexibility Means Choice of: JK, SR, T & D Flipflops, I/P & O/P Macrocells, Latch or Reg. Macrocells

Asynchronous Clocking

Figure 1. CMOS PAL Selection Route Map

1-12 Selecting the Correct CMOS PLD—An Overview of Advanced Micro Devices’ CMOS PLDs AMD Zero-Power The Selection Process Some devices are also offered in zero-standby power When selecting a CMOS PLD, start by determining both versions. Instead of always operating certain transistors the functional and size requirements for your in the linear region to achieve high speed, this circuitry application. can shut down and the device goes into standby mode. Standby mode is defined as anytime the inputs do not Functional Requirements switch for an extended period of time (typically 50 ns). The functional requirements of a given application are When this happens the current consumption will almost what determine which device architecture should be go to zero (ICC < 15 or 30 µA). The outputs will maintain used. The functional criteria include such issues as the the current state held while the device is in standby clocking scheme, macrocell flexibility and output drive. mode. The clocking scheme can be synchronous, where all When any input switches, the internal circuitry is fully en- registers within a device use the same clock signal, or abled and the power consumption returns to normal. asynchronous, where each register can be clocked indi- This feature results in considerable power savings for vidually using any logic signal or combination of logic operation at low to medium frequencies. signals available to the device. These two alternatives are illustrated in Figure 2. Zero-standby devices are desirable for a number of reasons. In portable and field-installed equipment that rely on batteries, battery life is extended. In solar powered systems, fewer solar cells are required.

Q Q QQ

CLK

a. Registers with Synchronous Clocking

Q Q Q

b. Registers with Asynchronous Clocking 17402B-2

Figure 2. Basic Clocking Schemes

Macrocell flexibility refers to the ability to configure the controls, polarity, and feedback. This concept will be fur- output in various ways. A macrocell (Figure 3) takes the ther illustrated as each device macrocell is explained basic sum-of-products logic and adds functionality throughout the selection process. through features like storage elements, optional path

Inputs AND OR Macrocell Outputs

17402B-3

Figure 3. PLD Block Diagram with the Macrocell Included

Selecting the Correct CMOS PLD—An Overview of Advanced Micro Devices’ CMOS PLDs 1-13 AMD Size Requirements devices best suited for simple state machines, encod- ers, decoders, muxes, and similar logic applications. The combination of number of inputs and outputs re- For these applications, D-type registered or combinato- quired determines the device size that should be used. rial (non-registered) logic is needed. The first choice is The number of product terms required to implement a the PALCE16V8, PALCE20V8, or PALCE24V10, de- particular design also factor into this decision. pending on the number of inputs or outputs needed. The best approach to selecting the appropriate device is The macrocells (Figure 4) can be configured to use to begin with the simplest and smallest devices and up- combinatorial or D-type registered outputs in any combi- grade as necessary to accommodate your application. nation. The D-type register operates very simply; data presented at the D input of the register will be clocked Combinatorial and Synchronous into the register on the rising edge of the clock signal. Applications The output can be configured as active low- or active high-output depending on the requirements of the Starting from the top of the flow chart in Figure 1 and tak- downstream devices and the efficiency of the logic. ing the path for synchronous designs leads one to those

To Adjacent 1 1 Macrocell 1 1 OE 1 0 0 0 VCC 0 X 0 1 1 0

SL0X SG1 1 1 0 X I/OX DQ 1 0

SL1X CLK Q

1 0 1 1 0 X From Adjacent SG1 SL0X Pin

17402B-4

Figure 4. PALCE16V8 Macrocell

1-14 Selecting the Correct CMOS PLD—An Overview of Advanced Micro Devices’ CMOS PLDs AMD More Product Terms and I/O’s The PALCE26V12, a 28-pin version of the 22V10 in- creases versatility by adding more inputs and outputs, If the application requires the features of the and by adding another global clock. Any macrocell can PALCE16V8 macrocell, but requires more programma- use one of the two clocks. This allows the logic to be par- ble gate functions, move further down the flowchart. The titioned giving greater design flexibility. In addition, reg- next device, the PALCE22V10 (Figure 5) has varied istered outputs can be configured as bidirectional pins product term distribution. The number of product terms on the 26V12. varies among outputs, with up to 16 product terms on some outputs. In addition, it has global synchronous Since historically most applications in bipolar technol- preset and asynchronous reset product terms. These ogy had been done in PAL16R8, PAL20R8, and are connected to all macrocells configured as registers, PAL22V10 families, these types of applications can facilitating easy power-up and system reset. This versa- easily have their power lowered with half-, quarter-, and tility contributes significantly to the 22V10 being the zero-power versions of the PALCE16V8, PALCE20V8, world’s most popular PAL architecture. When combined or PALCE22V10. with the PALCE16V8 family, these two device families will likely handle about 80% of PLD applications.

AR 10 11 DQ 00 I/On CLK Q 01

SP S1 S0

17402B-5

Figure 5. PALCE22V10 Macrocell Diagram

Table 1. Summary of the PALCE16V8 and PALCE22V10 Family Architectures

Macrocell Dedicated Product Device Type Inputs I/O’s Clocks Terms PALCE16V8 16V8 8–10 8 1 7–8 PALCE20V8 16V8 10–12 8 1 7–8 PALCE24V10 16V8 14 10 1 7–8 PALCE22V10 22V10 12 10 1 8–16 PALCE26V12 22V10 14 12 2 8–16

Selecting the Correct CMOS PLD—An Overview of Advanced Micro Devices’ CMOS PLDs 1-15 AMD Table 2. Summary of the Speed and Power high-output drive capability. This compares to 24 mA Requirements for the PALCE16V8, PALCE20V8, low-output and 3.2 mA high-output drive for other and PALCE22V10 Families of Devices PALCE16V8 devices. The PALCE16V8HD also has some unique macrocell features. Because this device is Device and Speed Grade ICC designed to drive a bus, it can be configured with open- PALCE16V8H-5 125 mA static drain outputs. Open-drain (open-collector) configura- PALCE16V8H-7/-10 115 mA at 25 MHz tion is sometimes used in bus applications because it PALCE16V8H-15/-25 90 mA at 15 MHz provides controlled VOH, termination, and wire-NOR capability. Because the PALCE16V8HD is designed to PALCE16V8Q-15/-25 55 mA at 15 MHz take inputs directly from a noisy bus, all inputs have PALCE16V8Z-25 15 µA in standby mode 200 mV input threshold hysteresis to improve noise im- PALCE20V8H-5 125 mA static munity. The inputs can be configured as direct or PALCE20V8H-7/-10 115 mA at 25 MHz latched, making additional buffering devices unnecessary. Additionally, the macrocell can be configured as PALCE20V8H-15/-25 90 mA at 15 MHz either a D- or T-type register. The T-type register is more PALCE20V8Q-15/-25 55 mA at 15 MHz efficient for counter applications because fewer product PALCE22V10H-5 140 mA at 25 MHz terms are consumed as hold states. PALCE22V10H-7 140 mA at 25 MHz Complex Functions PALCE22V10H-10 120 mA at 25 MHz For those applications that require D, T, J-K, or S-R reg- PALCE22V10H-15/25 90 mA static ister capability, the PALCE610 (Figure 6) has this flexi- PALCE22V10Q-25 55 mA static bility. This device has 16 macrocell outputs and four PALCE22V10Z-15/25 30 µA in standby mode dedicated inputs. The J-K, S-R, and T registers allow easy implementation of counters and larger state Bus Applications machines. For applications that require bus interaction, the PALCE16V8HD features 64 mA low-output and 16 mA

I I/O16 I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 CLK1

2 8 2 8 2 8 2 8 2 8 2 8 2 8 2 8 Programmable AND Array 40 x 160

2 8 2 8 2 8 2 8 2 8 2 8 2 8 2 8

CLK2 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1

17402B-6

Figure 6. PALCE610 Block Diagram

1-16 Selecting the Correct CMOS PLD—An Overview of Advanced Micro Devices’ CMOS PLDs AMD More Flexibility be available as an input. Eight of the 16 macrocells have dual feedback capability. This means that these macro- Moving down to the bottom of the flow chart reveals a cells have two independent feedback paths: one from more flexible device than the PALCE610. Applications the register and one from the I/O pin. The other eight that make use of embedded, or buried, registers can macrocells have single feedback, where both paths are take advantage of the PALCE29M16 (Figure 7). Buried available but, only one or the other can be used. Since register operation is very useful when a state machine almost every pin is an I/O pin this device has 29 avail- uses state bits that do not need to be brought outside the able inputs to the programmable AND array. chip. This allows the pin associated with the macrocell to

I/O I/O CLK/LE I/OF7 I/OF6 I/O7 6 I/O5 4 I/OF5 I/OF4

I/CLK/LE

OE I/O I/O I/O I/O I/O I/O I/O I/O V

V V LOGIC PTs V V LOGIC LOGIC V V LOGIC LOGIC V LOGIC LOGIC LOGIC 2 MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL OE PTs

2 8 8 12 16 16 12 8 8 2

Programmable AND Array 58x188

2 8 8 12 16 16 12 8 8 2

OE PTs I/O I/O I/O I/O V I/O I/O V V I/O V V I/O V V 2 LOGIC V LOGIC LOGIC LOGIC LOGIC LOGIC LOGIC LOGIC OE MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL PTs

I/OF I/OF I/O I/O I/O I 0 -I 2 I/OE 0 1 0 12I/O3I/OF23I/OF 17402B-7

Figure 7. PALCE29M16 Block Diagram

Selecting the Correct CMOS PLD—An Overview of Advanced Micro Devices’ CMOS PLDs 1-17 AMD The macrocells (Figure 8) can be configured as latches is available using a global product term to define the or registers. Latch operation allows the flip-flop in the preload condition. Preload capability allows arbitrary macrocell to become transparent while the latch is en- states to be loaded directly into the register, making it abled. When the latch is disabled, the flip-flop will hold unnecessary to cycle through long, complex vector se- the current state. This kind of operation is useful in sam- quences to get the device in a particular state. This is ple and hold applications. Also, the register or latch may normally only performed by the device programmer be used with the macrocell input pin for synchronizing when it performs functional tests. The preload product signals. The active level of the latch enable, as well as term allows preload to be engaged by hand, without the the clock edge (rising or falling) are both programmable. need for supervoltages (voltages above VCC needed to engage preload on most PLDs). Like the PALCE22V10, there is varied product term distribution among the macrocells. Also, preload capability

V COMMON CC 0 1 I/OE PIN 1 1 OE PTs FOR BANKS 1 0 OF 4 MACROCELLS 0 0 COMMON S6 S7 ASYNCHRONOUS PRESET 1 1 P0 PRESET 0 1 1 D Q 1 0 I/O X 0 P 7 Q 0 0 S3 S0 S1 CLK/LE 1 1 1 0 CLK/LE V I/CLK/LE 0 1 RESET 0 0 S S4 S5 2

COMMON ASYNCHRONOUS RESET

R TO AND ARRAY X

TO AND ARRAY 17402B-8

Figure 8. PALCE29M16 Macrocell Diagram

1-18 Selecting the Correct CMOS PLD—An Overview of Advanced Micro Devices’ CMOS PLDs AMD Asynchronous Applications combinatorial or as a synchronous register, output enable/disable is controlled by a product term. If asynchro- Starting at the top of the flow chart again, but this time nous register mode is desired, the same product term is taking the path for asynchronous applications, you will used as a clock and the macrocell is always enabled. find PALCE20RA10. The PALCE20RA10 is the simplest of the asynchronous devices. Each macrocell As mentioned above, the PALCE610 can act as a syn- (Figure 9) is clocked individually using one product term chronous or asynchronous PAL device. As shown, a per macrocell. Also, reset, preset, and output enable are special function product term can be steered to control controlled individually with one product term each. either the output enable or the macrocell clock. In the lat- There is also a global output enable pin which is com- ter mode, each register can be individually clocked. bined with the product term enable to determine if the output is enabled or disabled. If your application requires the basic features of the PALCE29M16, except with individual macrocell control, A dedicated global preload pin allows all registered ma- the PALCE29MA16 (Figure 11) should be considered. crocells to be preloaded simultaneously using normal Four product terms in each macrocell are dedicated to TTL levels. control clocking, output enable, asynchronous reset, and asynchronous preset. These functions are con- The PALCE610 has the distinction of bridging the gap trolled either globally or in blocks on the PALCE29M16. between synchronous and asynchronous register clock- A common clock pin and output enable pin are still main- ing. The PALCE610 macrocells can be clocked via indi- tained, but the user has a choice of using either the com- vidual product terms for each macrocell, or the mon control pin or individual macrocell control via the macrocells can be clocked in banks of eight via two dedi- control product term. cated clocks. This is done by using a clock/output enable mux (Figure 10). If the macrocell is configured as

PL OE

1 AP D Q Output PL 0 P S0 AR

17402B-9

Figure 9. PALCE20RA10 Macrocell Diagram

Selecting the Correct CMOS PLD—An Overview of Advanced Micro Devices’ CMOS PLDs 1-19 AMD

VCC 1 0 1 CLK 0

1 0

17402B-10

D Register

Figure 10. PALCE610 Macrocell (Configured as a D-Register) with the Output Enable/Clock Mux

VCC 0 1 COMMON I/OE PIN 1 1 1 0 INDIVIDUAL OE 0 0 INDIVIDUAL S6 S7 ASYNCHRONOUS PRESET 1 1 P0 0 1 1 PRESET I/OF D Q 1 0 x 0 P 3 0 0 S3 Q S0 S1 COMMON 1 1 CLK/LE (PIN) 1 0

V CLK/LE INDIVIDUAL 0 1 RESET CLK/LE 0 0 S2 S4 S5

INDIVIDUAL ASYNCHRONOUS RESET

TO AND ARRAY RFx

TO AND ARRAY

17402B-11 Figure 11. PALCE29MA16 Macrocell

1-20 Selecting the Correct CMOS PLD—An Overview of Advanced Micro Devices’ CMOS PLDs AMD MACH Devices MACH devices use PAL blocks that are interconnected using a switch matrix. The members of the families are At the bottom of the flow chart, both the synchronous differentiated by the number of pins, macrocells, clocks, and asynchronous design paths converge into the and the amount of interconnect. The MACH 1 family has MACH Family. MACH devices extend AMD’s PLD offer- output macrocells; the MACH 2 family has output and ings into the realm of what is referred to as mid-density. buried macrocells. All signals, whether registered or Mid-density devices allow multiple smaller PLD designs combinatorial can be buried. The basic macrocell, com- to be consolidated into one device. Mid-density covers mon to both families resembles the PALCE22V10 mac- replacement of just a couple of smaller PAL devices, all rocell with the additional choice of using D- or T-type the way up to designs that would traditionally be done registers. The MACH211 is illustrated in Figure 12. with small gate arrays. These devices span from 900 to 3600 gates, with 32 to 64 macrocells, and are offered in 44- to 84-pin packages.

I0–I1, I/O0–I/O7 I/O8–I/O15 I3–I4

8 8

I/O Cells I/O Cells 8 8 8 8 8 8 2 Macrocells Macrocells Macrocells Macrocells

OE OE 44 x 68 44 x 68 4 AND Logic Array AND Logic Array and and Logic Allocator Logic Allocator

26 26

Switch Matrix

26 26

44 x 68 44 x 68 AND Logic Array AND Logic Array and and 2 Logic Allocator Logic Allocator OE OE

2 Macrocells Macrocells Macrocells Macrocells 8 8 8 8 8 8

I/O Cells I/O Cells 8 8

I/O24–I/O31 I/O16–I/O23 CLK0/I2, CLK1/I5 17402B-12

Figure 12. MACH211 Block Diagram

Selecting the Correct CMOS PLD—An Overview of Advanced Micro Devices’ CMOS PLDs 1-21 AMD Both synchronous and asynchronous versions are SUMMARY available. The asynchronous MACH215 macrocell Selecting the appropriate PLD for a given application in- looks more like a PALCE20RA10 macrocell, rather than volves matching your requirements with various device PALCE22V10 type macrocells. The synchronous de- capabilities. Following the guidelines in this article along vices are better suited to structured designs; the asyn- with the “CMOS PAL Selection Route Map” makes it chronous MACH215 is better suited for random logic easier. collection. AMD’s wide array of electrically-erasable CMOS PLDs, All MACH devices have the advantage of fast (5, 7, 10, combined with strong third party support through our 12, 15, and 20 ns), predictable timing, which is a unique SM advantage when compared to other mid-density PLDs. FusionPLD relationships, means an excellent selection of devices, software, and programming hardware. This gives you a virtual toolbox of solutions for your system logic requirements, along with the strong technical support you expect.

1-22 Selecting the Correct CMOS PLD—An Overview of Advanced Micro Devices’ CMOS PLDs