IEE5008 –Autumn 2012 Memory Systems Overview of the NAND Flash High- Speed Interfacing and Controller Architecture
Nina Mitiukhina Electrical Engineering and Computer Science International Graduate Program National Chiao Tung University [email protected]
Nina,Chih -MitiukhinaYuan, Chang 2012 2012 Outline Introduction NAND Flash Background NAND Flash Device Operation NAND Flash Interface NAND Flash Controller Functions The ONFI Standard Challenge of designing ONFI 3.0 Overview of Specific NAND Flash Controller Features Conclusions Reference
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 2 Introduction NAND Flash enabling new markets
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 3 Introduction NAND Flash pricing converges with HDD
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 4 Introduction Price/performance positioning of different storage technologies With the use of new sophisticated controllers, SSDs are getting closer to having best of both worlds – HDD costs and DRAM like performance
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 5 Introduction Growing need for higher speed interfacing NAND
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 6 Introduction Performance demand with a growth of storage interface
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 7 Introduction Comparison of the number of bits for various memory storage arrays
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 8 NAND Flash Background A little bit oh history: Toshiba’s Flash Memory chronicle
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 9 NAND Flash Background Inherent limitations of NAND Flash Technology Shipped with a number of bad blocks Requires a serialized data interface After experiencing multiple erase cycles, is wearing down; reliability degradation
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 10 NAND Flash Background NAND SD vs. MMC
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 11 NAND Flash Background NAND vs. NOR
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 12 NAND Flash Background SLC vs. MLC Complicated programming sequence
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 13 NAND Flash Background SLC vs. MLC Smaller memory window between neighbouring levels
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 14 NAND Flash Background SLC vs. MLC Degraded performance
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 15 NAND Flash Background Data Organization
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 16 NAND Flash Device Operation Block erase
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 17 NAND Flash Device Operation Read operation Page opening (~ 50us) Data transfer (~ 20ns)
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 18 NAND Flash Device Operation Write operation (part 1) Incremental Step Pulse Programming plus verify scheme
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 19 NAND Flash Device Operation Write sequence (part 2) Shift data in shift registers Issue command to program data into page
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 20 NAND Flash device Operation Interleave access Data bandwidth: Data transfer time + Page access time
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 21 NAND Flash Interface NAND Flash Interface Evolution
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 22 NAND Flash Interface SDR Asynchronous vs. Toggle Mode DDR Faster Operation Speed Less Power Consumption
Asynchronous Interface with bi-directional DQS signal for reads and writes
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 23 NAND Flash Controller Improves chip performance Integrated controller Smaller chip size Cheaper cost Dedicated (External) controller Faster time to the market More flexible design, large variety of compatible parts available on the market
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 24 NAND Flash Controller Example: Flexible ONFI 2.2 compliant Controller for High Capacity MLC and High-Speed Data Transfer
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 25 NAND Flash Controller Brief description of functional blocks: DCU – Design Control Unit Provide enable/disable signal to the DMA, SUI units, ECC module; provide control signal to NCU. Execute boot sequence. Interrupt controller.
SIU – Signalling Interface Unit Coordinating interaction between the system interface and internal bus.
DMA – Direct Memory Access Speeds up data transfer between a device on the system bus and a memory, decreasing system bus burden.
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 26 NAND Flash Controller Brief description of functional blocks (part 2): FIFO – 32 bit wide module Data transferring between input module and NCU when command sequence is executed.
NCU – NAND Controller Unit Responsible for generation of the device access sequences.
ECC – Error Correction unit Correction code calculation.
PHY Provides DDR data interface for the new high-speed devices.
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 27 NAND Flash Controller Core implementation results ASIC FPGA (Altera vs. Xylinx)
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 28 ONFI Standard
Recognizing the need for a common NAND interface, the ONFI Workgroup formed in May 2006.
Today the ecosystem is comprised of NAND Flash users and suppliers, including more than 100 leading technology companies.
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 29 ONFI Standard Major changes in ONFI revisions
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 30 Challenge of designing ONFI 3.0 Released on March 15, 2011 NV-DDR2 interface enabling 400MT/s Differential signaling for DQS and RE DQS latency adjustment External Vref On-Die-Termination Reduced input voltage levels (SSTL_18) Vpp enablement
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 31 Challenge of designing ONFI 3.0 MLC, SLC performance
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 32 Challenge of designing ONFI 3.0 Data Interface Support
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 33 Challenge of designing ONFI 3.0 Differential Signaling Twice the noise immunity of the single ended signaling Reduced sensitivity to SSO (simultaneously switching output noise) Electromagnetic Interference reduction Enhanced Common Mode Noise tolerance
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 34 Challenge of designing ONFI 3.0 DQS latency adjustment Pre-toggles DQS until valid DQS is stabilized Tighter control of duty ratio Adjustable latency – from 1 to 4 cycles
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 35 Challenge of designing ONFI 3.0 Signalling Features (Vref + SSTL_18) SSTL_18 Signaling > 200 MT/s only supported with 1.8 Vcc Industry Standard compatible Higher speed, lower power consumption External Vref Reduce effects from external GND bounce Enables tighter setups/holds due to controlled voltage reference
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 36 Challenge of designing ONFI 3.0 On-Die-Termination
Challenge of designing ONFI 3.0
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 37 Overview of Specific NAND Flash Controller Features Error Correction Bad Block Management Wear Leveling strategies
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 38 Error Correction ECC requirement range from 1-bit correction per 512 bytes to 40-bit per 1kbyte.
, where N in the number of bits per block, E is the number of errors in a block and p is a bit error rate
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 39 Error Correction Overview of relative ECC strength
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 40 Bad Block Management Skip Block Method Algorithm creates the bad block table, data is stored in the next good block, skipping the bad block. Reserve Block Method Bad blocks are not skipped but replaced by good blocks by redirecting FTL to a known free good block.
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 41 Wear Leveling Controller maintains the lookup table to translate PBA to LBA used by the host
Wear-leveling methods: 1) Dynamic: Write to the available erased block with the lowest erase count. 2) Static: Select the available target block with the lowest overall erase count , erase the block if necessary, write new data to the block.
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 42 Wear Leveling Static vs. Dynamic
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 43 Conclusions NAND Flash benefits include high storage density, low cost and low power requirements, however inherent limitations of the technology are severe and require careful controller design.
A well designed controller delivers the maximum bandwidth of the NAND Flash device, whereas poorly designed one only reduces system performance.
New generation high-performance interfacing NAND Flash based SSD with integrated controller unit can face growing industry demands.
Nina,Chih- MitiukhinaYuan, Chang NCTU IEE5008 Memory Systems 2012 44 References
[1] R. Micheloni, L. Crippa, and A. Marelli. Inside NAND Flash Memories. Springer, Chapter 7, 2010 [2] W. Doug (2006, 06) An overwiev of NAND Flash Memory controllers. LinuxDevices[eWeek] Available: http://www.linuxfordevices.com/c/a/Linux-For-Devices-Articles/An-overview-of-NAND-Flash-memory- controllers/ [3] NAND Flash White Paper, Eureka Technology Inc., los Altos, 2012. Available: http://www.eurekatech.com/scripts/mymail.pl [4] W. Doug (2012, 10) Flash Technology: 200-400Mbps and Beyond. Available: http://www.jedec.org/sites/default/files/doug_wong.pdf [5] T. Grunzke (2011, 07) ONFI 3.0 Enabling 400 MT/s. Available: http://extmedia.micron.com/webmedia/onfi3/onfi30.html [6] K. Schurman (2011, 01) Toggle Mode NAND Flash. White paper [Hard hat area] Available: http://www.computerpoweruser.com/digitalissues/computerpoweruser/CP____1101__/44.html [7] E. Deal (2009, 06) Trends in NAND Flash Memory Error Correction. Available: http://www.cyclicdesign.com/index.php/ecc-trends-in-nand-flash [8] Bad Block Management in NAND Flash Memory, Micron Technology Inc., Boise, 2011 [9] Wear –Leveling Techniques in NAND Flash Devices, Micron Technology Inc., Boise, 2008 [10] NAND Flash Memory Controller IP Core, CAST Inc., Woodcliff Lake, 2011
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