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Discovery Visual Environment User Guide Discovery Visual Environment User Guide G-2012.09 September 2012 Comments? E-mail your comments about this manual to: [email protected]. Copyright Notice and Proprietary Information Copyright © 2012 Synopsys, Inc. All rights reserved. This software and documentation contain confidential and proprietary information that is the property of Synopsys, Inc. The software and documentation are furnished under a license agreement and may be used or copied only in accordance with the terms of the license agreement. No part of the software and documentation may be reproduced, transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written permission of Synopsys, Inc., or as expressly provided by the license agreement. Right to Copy Documentation The license agreement with Synopsys permits licensee to make copies of the documentation for its internal use only. Each copy shall include all copyrights, trademarks, service marks, and proprietary rights notices, if any. Licensee must assign sequential numbers to all copies. These copies shall contain the following legend on the cover page: “This document is duplicated with the permission of Synopsys, Inc., for the exclusive use of __________________________________________ and its employees. This is copy number __________.” Destination Control Statement All technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader’s responsibility to determine the applicable regulations and to comply with them. Disclaimer SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Registered Trademarks (®) Synopsys, AEON, AMPS, Astro, Behavior Extracting Synthesis Technology, Cadabra, CATS, Certify, CHIPit, CoMET, Confirma, CODE V, Design Compiler, DesignWare, EMBED-IT!, Formality, Galaxy Custom Designer, Global Synthesis, HAPS, HapsTrak, HDL Analyst, HSIM, HSPICE, Identify, Leda, LightTools, MAST, METeor, ModelTools, NanoSim, NOVeA, OpenVera, ORA, PathMill, Physical Compiler, PrimeTime, SCOPE, Simply Better Results, SiVL, SNUG, SolvNet, Sonic Focus, STAR Memory System, Syndicated, Synplicity, the Synplicity logo, Synplify, Synplify Pro, Synthesis Constraints Optimization Environment, TetraMAX, UMRBus, VCS, Vera, and YIELDirector are registered trademarks of Synopsys, Inc. Trademarks (™) AFGen, Apollo, ARC, ASAP, Astro-Rail, Astro-Xtalk, Aurora, AvanWaves, BEST, Columbia, Columbia-CE, Cosmos, CosmosLE, CosmosScope, CRITIC, CustomExplorer, CustomSim, DC Expert, DC Professional, DC Ultra, Design Analyzer, Design Vision, DesignerHDL, DesignPower, DFTMAX, Direct Silicon Access, Discovery, Eclypse, Encore, EPIC, Galaxy, HANEX, HDL Compiler, Hercules, Hierarchical Optimization Technology, High-performance ASIC Prototyping System, HSIMplus, i-Virtual Stepper, IICE, in-Sync, iN-Tandem, Intelli, Jupiter, Jupiter-DP, JupiterXT, JupiterXT-ASIC, Liberty, Libra-Passport, Library Compiler, Macro-PLUS, Magellan, Mars, Mars-Rail, Mars-Xtalk, Milkyway, ModelSource, Module Compiler, MultiPoint, ORAengineering, Physical Analyst, Planet, Planet-PL, Polaris, Power Compiler, Raphael, RippledMixer, Saturn, Scirocco, Scirocco-i, SiWare, Star-RCXT, Star-SimXT, StarRC, System Compiler, System Designer, Taurus, TotalRecall, TSUPREM-4, VCSi, VHDL Compiler, VMC, and Worksheet Buffer are trademarks of Synopsys, Inc. Service Marks (sm) MAP-in, SVP Café, and TAP-in are service marks of Synopsys, Inc. SystemC is a trademark of the Open SystemC Initiative and is used under license. ARM and AMBA are registered trademarks of ARM Limited. Saber is a registered trademark of SabreMark Limited Partnership and is used under license. All other product or company names may be trademarks of their respective owners. ii Contents 1. Getting Started . 1-1 Overview . 1-2 Enabling Debugging . 1-3 Debug Options. 1-3 Required Files . 1-4 Invoking DVE. 1-5 64-bit Mode . 1-6 Interactive Mode . 1-6 Starting an Interactive Session from the DVE GUI. 1-7 Post-Process Mode . 1-11 Using the -vpd command . 1-11 Loading the Design Database File in the DVE GUI . 1-11 Using Session File . 1-13 Using the -session command . 1-13 Loading a Session File in the DVE GUI . 1-13 Using Tcl Scripts . 1-14 Passing DVE Arguments from Simulator Runtime Command Line 1- 14 Saving a Session or Layout. 1-16 Contents iii Saving the Current View . 1-18 Restoring a Saved Simulation . 1-20 Closing a Database . 1-22 Exiting DVE . 1-22 DVE Log Files . 1-22 DVE Licensing Queuing . 1-23 DVE Setup Files . 1-24 Managing User Setup Files . 1-26 Usage. 1-26 Typical Symbols Used in DVE. 1-28 Special Symbols Used in DVE. 1-29 Low Power Symbols Used in DVE. 1-30 2. Using the Graphical User Interface . 2-1 Overview of DVE Window Configuration. 2-2 Creating a Window Title for All Views and Panes . 2-6 Managing DVE Panes and Views . 2-8 Managing Target Views . 2-9 Maximizing View . 2-11 Docking and Undocking Views and Panes . 2-13 Dragging and Dropping Docked Windows . 2-13 The Console Pane. 2-14 The Watch Pane . 2-15 The Memory View . 2-16 Setting Properties of Signal in Memory View. 2-16 C, C++, and SystemC Code . 2-19 Contents iv Using the Menu Bar and Toolbar. 2-20 Searching Signals or Scopes . 2-20 Mapping to the Location of the Source Files . 2-22 Interactive Mode . 2-22 Use Model . 2-22 Post-process Mode . 2-23 Use Model . 2-23 Editing Preferences . 2-24 Using Context-Sensitive Menu . 2-24 3. Using the Hierarchy and Data Panes . 3-1 The Hierarchy Pane . 3-2 Scope Types and Icons . 3-3 Filtering the objects in the Hierarchy Pane. 3-5 Navigating Open Designs . 3-5 Expanding and Collapsing the Scope . 3-6 Rearranging Columns in the Hierarchy Pane . 3-6 Populating Other Views and Panes . 3-7 Displaying Variables in the Data Pane . 3-7 Dragging and Dropping Scopes . 3-7 Dumping Signal Values . 3-9 Moving Up or Down in the Hierarchy Pane . 3-10 The Data Pane . 3-16 Viewing Signals and Values. 3-17 Filtering the Signals . 3-18 Forcing Signal Values . 3-19 Viewing Interfaces as Ports . 3-23 Viewing $unit Signals. 3-26 Contents v Debugging Partially Encrypted Source Code. 3-28 4. Using the Source View . 4-1 Loading Source Code . 4-2 Loading a Source View from the Hierarchy Pane . 4-2 Loading a Source View from the Assertion View . 4-3 Displaying Source Code from a File . 4-4 Using the Mouse in the Source View. 4-5 Working with the Source Code . 4-6 Expanding and Collapsing Source Code View . 4-6 Displaying Include File as Hyperlink . 4-6 Example . 4-6 Editing Source Code . 4-10 Selecting and Copying Text to the Clipboard. 4-11 Color-coding the Source File . 4-11 Setting Desired Color for Inactive 'ifdef `else Code in DVE . 4-13 Usage Example . 4-14 Navigating the Design from the Source View . 4-17 Navigating Code in Interactive Simulation. 4-18 Setting Breakpoints in Interactive Simulation . 4-18 Managing Breakpoints . 4-20 Setting Breakpoints in a Class Object . 4-24 Creating Conditional Breakpoints. 4-27 Debugging During Initialization of SystemVerilog Static Functions and Tasks . 4-32 Enabling Static Debug in DVE . ..
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