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USOO6342892B1 (12) Patent (10) Patent No.: US 6,342,892 B1 Van Hook et al. (45) Date of Patent: Jan. 29, 2002

(54) VIDEO GAME SYSTEMAND 4,404,629 A 9/1983 Albaugh ...... 395/590 COPROCESSOR FOR VIDEO GAME SYSTEM (List continued on next page.) FOREIGN PATENT DOCUMENTS (75) Inventors: Timothy J. Van Hook, Menlo Park; Howard H. Cheng, San Francisco; EP O 632 407 A1 1/1995 EP O 633 533 A2 1/1995 Anthony P. DeLaurier, Sunnyvale; EP O 649 118 A2 4/1995 Carroll P. Gossett, Mountain View; EP O 676 719 A2 10/1995 Robert J. Moore, Sunnyvale; Stephen EP O 676 726 A2 10/1995 J. Shepard, Cupertino; Harold S. EP O 627 699 A2 11/1995 Anderson, Morgan Hill; John Princen, EP O 681 267 A2 11/1995 Sunnyvale; Jeffrey C. Doughty, Palo JP 4-106594 8/1992 Alto; Nathan F. Pooley, Mountain WO WO 94/10641 5/1994 View; Byron Sheppard, Santa Cruz, all WO WO94/10685 5/1994 of CA (US); Genyo Takeda, Osaka; WO WO94/27205 11/1994 Shuhei Kato, Shiga, both of (JP) OTHER PUBLICATIONS (73) Assignees: Co., Ltd., Kyoto (JP); Silicon Johnson, Matthew, A Fixed-Point DSP For Graphics, Inc., Mountain View, CA Engines, Aug. 1989, IEEE, Los Alamitos, CA, pp. 63-77. (US) (List continued on next page.) (*) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 Primary Examiner Kee M. Tung U.S.C. 154(b) by 0 days. (74) Attorney, Agent, or Firm Nixon & Vanderhye P.C. (57) ABSTRACT (21) Appl. No.: 09/186,137 A low cost high performance three dimensional (3D) graph (22) Filed: Nov. 5, 1998 ics System can model a world in three dimensions and Related U.S. Application Data project the model onto a two dimensional viewing plane Selected based on a changeable viewpoint. The viewpoint (62) Division of application No. 08/561.718, filed on Nov. 22, can be changed on an interactive, real time basis by oper 1995. ating user input controls Such as game controllers. The System rapidly produces a corresponding changing image (51) Int. Cl." ...... G06T 1100 (which can include animated cartoon characters or other (52) U.S. Cl...... 345/503; 34.5/541; 345/419; animation for example) on the Screen of a color television 345/542; 463/32; 463/43; 463/44 Set. The richly featured high performance low cost System (58) Field of Search ...... 345/430, 501-503, gives consumers the chance to interact in real time inside 34.5/507–509, 512,519, 513,523-525, magnificent Virtual 3D Worlds to provide a high degree of 522, 302, 419, 542, 541, 530, 552, 553, image realism, excitement and flexibility. An optimum fea 544, 531,561, 520, 619, 643; 463/30-34, ture set/architecture (including a custom designed graphics/ 40-45 audio coprocessor) provides high quality fast moving 3D (56) References Cited images and digital Stereo Sound for Video game play and other graphics applications. U.S. PATENT DOCUMENTS RE31,200 E 4/1983 Sukonick et al...... 395/520 38 Claims, 105 Drawing Sheets

138. SERAL PERIPHERAL FROM INTERFACESECURITY PROCESSORINCL) FF S NT INTRSTM RDRAMMEMORY UPF08MBEXPANDABLE y INTO CPJ SERAL wres ------MPS 4B CP INTERFACE NERFACE DISPLAYLIST Texture i AUDIO i GRAPHICS i DATA l---- S.PLAYLIST 18b. 3 (OMMANDsAUDIO coloracesEEElla FRAME instructions--- 11

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US 6,342,892 B1 Page 2

U.S. PATENT DOCUMENTS IEEE CG&A, “A New VLSI Graphics Copressor, The 4,789,927 A 12/1988 Hannah ...... 395/800 Intel82786” Calen Shines, Oct. 1986 pp. 49–55.* 4,799,635 A 1/1989 Nakagawa ...... 395/442 Open GL Programming Guide, “The Official Guide to 4,823,120 A 4/1989 Thompson et al. Learning OpenGL, Release 1,” OpenGL Architecture 4,824,106 A 4/1989 Ueda ...... 463/33 Review Board, Jackie Neider, Tom Davis, Mason Woo, 4,825,391 A * 4/1989 Merz ...... 395/131 Copyright 1993 by Silicon Graphics, Inc. 4.951,232 A 8/1990 Hannah ...... 395/122 Open GLReference Manual, “The Official Reference Docu 4970,636 A 11/1990 Snodgrass et al. ment for OpenGL, Release 1,” OpenGL Architecture 5,038.297 A 8/1991 Hannah ...... 395/122 REview Board, Copyright 1992 by Silicon Graphics, Inc. 5,051,737 A 9/1991 Akeley et al...... 395/134 MIPS User's Manual, First Edition, 5,070.479 A 12/1991 Nakagawa ...... 395/182.09 by Joe Heinrich, Copyright 1993 by MIPS Technologies, 5,113,490 A 5/1992 Winget ...... 395/119 5,187,796 A * 2/1993 Wang et al...... 71.2/4 Inc. 5,193,145 A 3/1993 Akeley ...... 395/123 MIPS Microprocessor R4000 User's Manual, Second Edi 5,227,863 A 7/1993 Bilbrey et al. tion, by Joe Heinrich, Copyright 1994 by MIPS Technolo 5,230,039 A 7/1993 Grossman et al...... 395/130 gies, Inc. 5,265,199 A 11/1993 Catlin ...... 395/122 MIPS Risc Architecture, “Introducing the R4000 Technol 5,266,941 A 11/1993 Akeley et al. . ... 34.5/201 ogy,” by Gerry Kane and Joe Heinrich, Copyright 1992 by 5,291,189 A 3/1994 Otake et al...... 34.5/201 MIPS Technologies, Inc. 5,307.450 A 4f1994 Grossman ...... 395/123 MIPS Open Risc Technology, “R4400 Microprocessor Prod 5,343,558 A 8/1994 Akeley ...... 395/126 5,347,618 A 9/1994 Akeley ...... 395/121 uct Information,” by Satya Simha, MIPS Technologies, Inc., 5,357,604 A 10/1994 San et al...... 463/31 Sep. 27, 1993. 5,369,739 A 11/1994 Akeley ...... 395/134 Indy Product Guide, Indy-TMG-(09/93), Copyright 1993 5,388,841. A 2/1995 San et al...... 463/44 by Silicon Graphics, Inc. 5,394,170 A 2/1995 Akeley et al. . ... 34.5/201 OpenGL, It's Everywhere, Information Sheet, OPGL-BRO 5,469,535 A * 11/1995 Jarvis et al...... 34.5/503 (07/93), Copyright 1993 by Silicon Graphics, Inc. 5,491,498 A * 2/1996 Koyama et al...... 34.5/189 Reality Engine/Reality Engine', Graphics Subsystems, Data

5,541,923 A 7/1996 Kato ...... 395/427 Sheet, Copyright 1993 by Silicon Graphics, Inc. 5,553,864 A 9/1996 Sitrick ...... 463/31 Indy Technical Report, Indy-TR (06/93) Copyright 1993 by 5,561,746 A * 10/1996 Murata et al...... 345/419 Silicon Graphics, Inc. 5,701,444. A 12/1997 Baldwin 5,732,224 A 3/1998 Gulick et al. Reality Engine in Visual Simulation Technical Overview, 5,768,393 A 6/1998 Mukojima et al. RE-Vissim-TR(8/92), Copyright 1992 by Silicon Graphics, 5,791,994 A 8/1998 Hirano et al...... 463/43 Inc. 5,797.028 A 8/1998 Gulick et al. Architectural Overview, DL0001-02, Copyright 1992, 1993 by Rambus Inc. OTHER PUBLICATIONS SH7600 Series Super H Risc Engine, Overview, Hitachi Wayner, Peter, Silicon For 3-D, Sep., 1994, , Peter manual, Oct. 17, 1994. borough, NH, pp. 191-192. This is What its Like To Give Your Next Product A32-Bit Wilson, Chip Vendors May Exterminate Frame Buffers, EE Risc Controller, Hitachi America, Ltd. brochure, 1994. Times-News 1995, Mar. 27, 1995. Instruction Manual, Sega, Hayward, Califor “Battle Zone/Cabaret', Atari Inc. (1980), pp. 12–13 & VHS nia.H3701–926–0–01 (1994). Videotape. Sega Genesis 32X Instruction Manual, Sega, Redwood City Perry et al., associate editors, “Special Report, Consumer .#672–2116 (1994). Electronics, Video games: the electronic big bang, IEEE Knuckles Chaotix Instruction Manual, Sega, Redwood City, Spectrum, pp. 20-32, Dec. 1982. California, #84503 (1995). Johnstone, “Keeping Nintendo Competitive,” Wired, Jan. 3D BallZ Instruction Booklet, , San Jose, Califor 1994, pp. 76–77. nia, #3050-00231 Rev. A. “The Creation of Battlezone' from Arcade Sonic 2 The Hedgehog Instruction Manual, Sega, Hayward, (Undated). California, #672–0944 3701–925–0–01 (1992). “Battlezone by Atari Coin Op-True Facts” & “Army PR Newswire, Sony Enters the CD-ROM-Based Video Battlezone” (memoranda). Game, New York, Ny. May 31, 1991. Super Nintendo Entertainment System. Sony PlayStation Instruction Manual, and informational Vortex game cartridge for the SNES. materials, Sony Computer Entertainment Inc. 1995. “The i750F) video processor; A Total Multimedia solution”, 6 Photographs of Sony PlayStation: 1) top case and compact K. Hainey et al., Communications of the ACM, vol. 34, No. disk; 2) hand controller; 3) internal circuitboards (top view); 4, 4/91, pp 64-78.* 4) internal circuit boards (top view); 5) compact disk reader Proceedings, Annual Conf. Series, (bottom view); and internal main circuit board (bottom 1993, Aug. 1–6, 1993, “Leo: A System for Cost Effective 3D view). Shaded Graphics' Deeing et al. pp 101-108.* * cited by examiner U.S. Patent Jan. 29, 2002 Sheet 1 of 105 US 6,342,892 B1

U.S. Patent Jan. 29, 2002 Sheet 2 of 105 US 6,342,892 B1

U.S. Patent Jan. 29, 2002 Sheet 3 of 105 US 6,342,892 B1

X U.S. Patent Jan. 29, 2002 Sheet 4 of 105 US 6,342,892 B1

U.S. Patent US 6,342,892 B1

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Fig.O 4A G START) 1.20a EXAMPLE OVERALL GET OR GENERATE DISPLAY LIST & GRAPHICS PROCESSING STORE IN MAIN MEMORY 12Ob

LOAD GRAPHCS MICROCODE INTO SIGNAL PROCESSOR MAN PROCESSOR 120C 1 OO GIVE DISPLAY LIST LOCATION TO SIGNAL PROCESSOR

122a 1. FETCH THE DISPLAY LIST

122b

PROCESS THE DISPLAY LIST SIGNAL e MATRIXDEF. PROCESSOR O XFORMVERTICES 400 GENERATE DPTRIANGLE COMMAND

122C

GIVE TRIANGLE COMMAND TO DISPLAY PROCESSOR

RENDER TRIANGLE 126a DISPLAY SPECIFIED BY TRIANGLE COMMAND PROCESSOR 500 WRITE PIXELS TO FRAME 126b BUFFER 118

WRITE 118 TO TELEVISION SCREEN VIDEO INTERFACE 210 U.S. Patent US 6,342,892 B1

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U.S. Patent Jan. 29, 2002 Sheet 10 Of 105 US 6,342,892 B1

RESET

160a Fic. 5A 9 EXECUTE BOOT ROM; PERIPHERAL EXAMPLE CPU SECURITY CHECK INTERFACE NITALIZATION ROUTINE BOOT ROM

160b JUMP TO CARTRIDGE ROM

1600

INITIALIZE HARDWARE STORAGE DEVICE ROM

160 START DRAM CONTROLLER

60e

COPY GAME PROGRAM FROM CARTRIDGE ROM TODRAM

160f

JUMP TODRAM

------

DRAM EXECUTE GAME PROGRAM U.S. Patent Jan. 29, 2002 Sheet 11 Of 105 US 6,342,892 B1

MAIN MEMORY (BANKO)

MAIN MEMORY 300 BANK 1 307 RDRAMREGISTERS

SIGNAL PROCESSOR DATA MEMORY 404

SIGNAL PROCESSOR INST. MEMORY 402

COPROCESSOR2OO REGISTERS

CARTRIDGE DOMAIN 2

CARTRIDGE DOMAIN 1 76 CARTRIDGE DOMAIN 2

CARTRIDGE DOMAIN 1

PIF BOOT ROM 150

PIF STATUS REGISTER

CARTRIDGE DOMAIN 1

EXTERNAL SYSAD DEVICES Fig. 5B EXAMPLE CPU MEMORY MAP U.S. Patent Jan. 29, 2002 Sheet 12 Of 105 US 6,342,892 B1 Fig. 6 COPROCESSOR 200 4. SP INSTRUCTION MEMORY SCALAR VECTOR UNIT UNIT

410 420 MEMORY

500 212

514 RASTERIZER DRAM CONT. TEXTURE UNIT

COLOR COMBINER

214

CPU VIDEOOUT AUD10H CARTRIDG E GAME(SERIAL CONTROLLERS I/O) U.S. Patent Jan. 29, 2002 Sheet 13 Of 105 US 6,342,892 B1

TO/FROM 102. PROCESSOR 100 CM5 BUSY 402 ADBUS O O D O O O O. O. O (5 BITS)-132BS)------COPROCESSOR CPUNLREG1107 202 200 CBUS INTERFACE (M(MI) 454 N(32 BIT ADDRESS DBUS AUDIO (64. BITDATA)1200 / 208 (3 BITS)

TO 402404 ID INTERFACEFFE SIGNAL 209 PROCESSOR 407 MIDEO BUS (8BITS) TO WDAC 144

507 1300 |DISPLAY 204 SERIAL BUS PROCESSOR (3 BITS) TOIFROM

PF 138 MEMORY

PARALLEL BUS (16 BITSAID)

PARATEINTERFACE DEVICE 54 104

1407 1007a 206 RAMINTERFACE (RI) 212a 212b RAM CONTROLLER (RAC)

1007b 106 AID BUS (9BITS)

300 Fig. 6A RDRAM, REG SYSTEM EXAMPLE 307 BUS STRUCTURE U.S. Patent Jan. 29, 2002 Sheet 14 Of 105 US 6,342,892 B1 Fig. 7 214 SIGNAL PROCESSOR 400

CPUCONTROL REGISTERS

DMA CONTROLLER ADR/DATA

218 "X"BUSTODP AUDIO; D BUFR DATA GMDS MEMORY MEMORY-- (4KB) BUFFERVI

REGISTER REGISTERFILE(O) REGISTER FILE(1) REGISTERFILE(7) (32 REGS) (32 REGS) (32 REGS)

DATA PATH (ADDERS DATA PATH (O) DATAPATH(1) DATA PATH(7) SHIFTERS) (MULTI+ ADDERS) (MULTI+ ADDERS) (MULTI+ ADDERS) U.S. Patent US 6,342,892 B1

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U.S. Patent Jan. 29, 2002 Sheet 21 of 105 US 6,342,892 B1

CHANNE, SAMPLE PLAYLIST

TASKLIST

2 DISPLAYLIST XFORM /

DISPLAYIST

DISPLAYORPLAYLIST

110(2)

10(3) Fig. 8 TASKLIST U.S. Patent Jan. 29, 2002 Sheet 22 of 105 US 6,342,892 B1

Fig. 9 LOAD DISPLAY LIST EXAMPLE MICROCODE LOAD ROUTINE

CPU HALTS SIGNAL PROCESSOR

CPU USES DMA TO LOAD 604 BOOT MICROCODEMODULE INTO SIGNAL PROCESSOR NSTRUCTION MEMORY

606

CPU LOADS TASK HEADER NTO SIGNAL PROCESSOR DATA MEMORY

608

CPU SETS SIGNAL PROCESSOR PROGRAM COUNTER TO O

610

CPUCLEARS SIGNAL PROCESSOR HALT STATUS U.S. Patent Jan. 29, 2002 Sheet 23 of 105 US 6,342,892 B1 Fig. 10 SIMPLE SPDISPLAY LIST PROCESS EXAMPLE

62 SEATTRIBUTES

64

66 GENERATE VERTICES

GENERATE DPTRANGE 68 COMMAND U.S. Patent Jan. 29, 2002 Sheet 24 of 105 US 6,342,892 B1

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FC T2A EXAMPLE "DOUBLE PRECISION" VALUE

16-BIT INTEGER PART 16-BIT FRACTIONAL PART

FC 2:3 EXAMPLE MATRIX FORMAT

16-BIT SIGNED INTEGER VALUE(O) 16-BIT SIGNED INTEGER VALUE(1) NTEGER PARTS

16-BIT SIGNED INTEGER VALUE(15)

16-BIT FRACTIONAL VALUE(O)

16BIT FRACTIONAL VALUE (1) FRACTIONAL PARTS

16-BIT FRACTIONAL VALUE(15) U.S. Patent Jan. 29, 2002 Sheet 26 0f 105 US 6,342,892 B1

4.08

VERTEX O 408 (O) VERTEX 1 408(1) VERTEX 2 408 (2) FG 3A

VERTEX 15 408 (15) VERTEX BUFFER

408 (1) FG 33 408 (1)(a) 408 (1) (b) 408 (1) (c) 408 (1) (d) 408 (1) (e) 408 (1)(f)

408 (1) (g) 408 (1) (h) 408 (1) (i) 408 (1) () 408 (1) (k) 408 (1) (I) 408 (1) (m) 408 (1) (n) 408 (1) (o) 408 (1) (p) 408 (1) (q) Z. Scr.frac 408 (1) (r) i/Wint 408 (1) (s) i/W.frac 408 (1) (t) 408 (1) (u) FLAGS (E.G.,CLIPTEST RESULTS) 408 (1) (v) 408 (1) (W)

EXAMPLE VERTEX DATA STRUCTURE U.S. Patent Jan. 29, 2002 Sheet 27 of 105 US 6,342,892 B1

TABLE ENTRY (4)

BASEADRO

BASE ADR

BASEADR2

BASE ADR 5

PHYSICAL ADDRESS

EXAMPLESIGNAL PROCESSORSEGMENT ADDRESSING

FG 3C U.S. Patent Jan. 29, 2002 Sheet 28 Of 105 US 6,342,892 B1

702 Fig. 14 EXAMPLE AUDIOSOFTWARE ARCHITECTURE 704

SEQUENCE

CPU 700 SYNTHESIS DRIVER 706

AUDIOSYNTHESIS 708 SP400 MICROCODE

U.S. Patent Jan. 29, 2002 Sheet 29 of 105 US 6,342,892 B1 Fig. 15 SIMPLE SPPLAYLIST PROCESSEXAMPLE

START

70 SETUP BUFFERS

72

SETATTRIBUTES O WOLUME

SPECIFYSIGNAL PROCESSING TYPE

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76

SAVE TO MAN MEMORYBUFFER U.S. Patent Jan. 29, 2002 Sheet 30 0f 105 US 6,342,892 B1

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U.S. Patent Jan. 29, 2002 Sheet 31 of 105 US 6,342,892 B1 Fig. 18 DISPLAY PROCESSOR PROCESSING

TRI, RECT 550 LOADTILE BLOCK, LOAD TLUT RASTERIZE SETSCISSOR

TEXTURE MEMORY TEXTURE COORDS.

COLOR SHADECOLOR CONVERTIFILTER

CHROMA KEY

TEXTURE COLOR

Z, COVERAGE, WE

FRAMEBUFFER

U.S. Patent Jan. 29, 2002 Sheet 32 Of 105 US 6,342,892 B1

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PRIMITIVE COLOR || || || ||

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LOD FRACTION PRIMITIVE LOD FRACTION || || | | || || I I I II IsIts Ilsall,

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KEY: WIDTH, RGB

COMBINED ALPHA COVERAGE

antialius en 0

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PRIMITIVE ALPHA

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COPYIFILL MODE BLENDED PIXEL U.S. Patent Jan. 29, 2002 Sheet 48 of 105 US 6,342,892 B1

Fig. 32 COLORPIXELFORMAT

5 5 5 3

Fig. 33DEPTH PIXELFORMAT

14 4 U.S. Patent Jan. 29, 2002 Sheet 49 of 105 US 6,342,892 B1 Fig. 33A WRITE ENABLE GENERATION PXELAPHA COPYPXELS RANDOM DTHERALPHA BLEND COLORALPHA

COPY MODE INDEXPEXEL

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U.S. Patent Jan. 29, 2002 Sheet 51 0f 105 US 6,342,892 B1

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RINTERFACE 1000 212b 214d DBUS 106

RAMBUS RAC TOIFROM MAN MEMORY 300

CONTROL

CBU 214C Fig. 36 EXAMPLE MEMORY INTERFACE

MINTERFACE 1102

102a

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U.S. Patent Jan. 29, 2002 Sheet 60 of 105 US 6,342,892 B1

1066(R)

DIRTY BITS WALD BITS (R)

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FG 43C SI/PIFDMA READREQUEST REGISTER(W) 324

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U.S. Patent Jan. 29, 2002 Sheet 86 of 105 US 6,342,892 B1

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