Design of Radio Frequency Power Amplifiers for High

DESIGN OF RADIO FREQUENCY POWER AMPLIFIERS FOR

HIGH EFFICIENCY AND HIGH LINEARITY

______

A Thesis

Presented

to the Faculty of

California State University, Chico

______

In Partial Fulfillment

of the Requirement for the Degree

Master of Science

Electrical and Computer Engineering

Electronic Engineering Option

______

Tian He

Fall 2009 DESIGN OF RADIO FREQUENCY POWER AMPLIFIERS FOR

HIGH EFFICIENCY AND HIGH LINEARITY

A Thesis

Tian He

Fall 2009

APPROVED BY THE INTERIM DEAN OF THE SCHOOL OF GRADUATE, INTERNATIONAL, AND INTERDISCIPLINARY STUDIES:

______Mark J. Morlock, Ph.D.

APPROVED BY THE GRADUATE ADVISORY COMMITTEE:

______Adel A. Ghandakly, Ph.D. Uma Balaji, Ph.D., Chair Graduate Coordinator

______Ben-Dau Tseng, Ph.D. ACKNOWLEDGMENTS

The author wishes to thank Dr. Uma Balaji for her guidance throughout this thesis work, without her I could not possibly have gotten into this area.

I would like to thank Dr. Ben-Dau Tseng, who as a committee member gave many suggestions, some of which were really valuable to me.

I am also indebted to Steve Eckart for his kindness and his professional work during the implementation of this thesis work.

I would also like to thank Ryan Baker, Simon Wood, and Ray Pengelly from

Cree, Inc. for their support on the transistor used in this thesis work. Many thanks to

AWR Corporation for providing free educational licenses of Microwave Office. Many thanks to Oliver Zhu from Taconic for donating board materials used in this thesis. Many thanks to Chico State alumnus Ken Beals for bringing equipments used to measure the designed amplifier.

Finally, I would like to thank my dear parents, sister, family, friends, and everyone who helped and sponsored my study in California State University Chico, without whom this thesis work would have been impossible.

iii TABLE OF CONTENTS

PAGE

Acknowledgments ...... iii

List of Tables...... vi

List of Figures...... vii

Abstract...... x

CHAPTER

I. Introduction...... 1

Transistor Transfer Characteristic ...... 2 Amplifier Classes ...... 3 Linearity Analysis ...... 10 Compression Analysis...... 12 Power Match and Load Pull Method...... 15

II. Load Pull Design Procedure...... 17

Input Matching Theory...... 18 Design Procedure...... 21

III. Class F Amplifier Theory and Design...... 32

Class F Theory...... 32 Circuit Design...... 35

IV. Design Implementation and measurements...... 47

PCB Design ...... 47 Measurement ...... 47

iv CHAPTER PAGE

V. Doherty Amplifier Modification ...... 53

Introduction ...... 53 The Doherty Amplifier...... 54 Realization Problems and Known Remedies ...... 59 A New Configuration ...... 62 Simulation Results...... 70 Conclusions ...... 71

VI. Conclusions and Future Work...... 72

Conclusions ...... 72 Future Work...... 73

References ...... 74

v LIST OF TABLES

TABLE PAGE

1. Conventional Amplifier Modes ...... 4

2. Substrate Properties...... 39

3. Component List...... 48

4. Measurement Results...... 51

vi LIST OF FIGURES

FIGURE PAGE

1. Typical FET Transfer Characteristic Generated from Simulation in AWR Microwave Office ...... 2

2. General FET Transfer Characteristic (gm Represents the Slope) ...... 4

3. Illustration of Conduction Angle ...... 5

4. Fundamental and DC Current Amplitude vs. Conduction Angle...... 6

5. Calculation of Drain Voltage Using Superposition Principle...... 7

6. IVCurve Example to Shown the Knee Voltage ...... 8

7. Efficiency Characteristic and Output Power Capability As a Function of Conduction Angle...... 10

8. Linearity of Different Amplifier Classes ...... 12

9. Illustration of Drain Current Clipping of Reduced Conduction Angle .... 13

10. Effects of Clipped Drain Current on Output Power Compression ...... 14

11. Impact of Package Parasitic Components on Load Termination...... 15

12. Optimal Source and Load Impedances of a Transistor...... 18

13. Model to Investigate the Relationship Between Gate Power and Gate Voltage...... 19

14. Maximum Power Transfer Illustration ...... 20

15. Illustration of How a Larger Load Resistance Could Make the Transistor Output Power Increase Faster but Compress Earlier ...... 22

16. Circuit Setup to Get the Transfer Characteristic of the Transistor ...... 23

vii FIGURE PAGE

17. Transfer Characteristic of the Transistor ...... 23

18. Load Pull Method ...... 24

19. Load Pull Contour on the Whole Smith Chart Area...... 26

20. Shrinked Sweep Region...... 27

21. Second Load Pull Analysis with Shrinked Sweep Region ...... 28

22. Matching Networks of the Design Example...... 29

23. Amplifier Circuit Prototype ...... 30

24. Output Power and PAE vs. Input Power...... 31

25. Effects of Third Order Harmonic on Sinusoidal Waveform...... 34

26. Circuit To Get Gate Bias Voltage...... 36

27. Ideal Input Matching Network Designed Using Transmission Lines...... 37

28. Ideal Output Network Designed Using Transmission Lines ...... 37

29. Amplifier Using Ideal Components...... 38

30. Output Power and PAE vs. Input Power of the Amplifier Using Ideal Components...... 38

31. Microstrip Substrate Definition ...... 40

32. TXLine, Used to Convert Between Electrical Characteristics and Physical Ones ...... 40

33. Four Microstrip Lines with a Junction...... 41

34. Illustration of the Junction ...... 42

35. Top Level Lossy Amplifier Circuit ...... 43

36. Lossy Input Network ...... 44

viii FIGURE PAGE

37. Lossy Output Network...... 45

38. Output Power and PAE vs. Input Power of the Amplifier Using Realistic Lossy Components ...... 46

39. Final Layout...... 48

40. Final PCB Board...... 49

41. Measurement Setup Diagram...... 49

42. Measurement Setup Picture ...... 50

43. Forward Gain of the Whole System, Including the Pre-Amplifier, the Amplifier and the Attenuator ...... 52

44. Doherty Amplifier Structure...... 55

45. Amplitude of Fundamental Device Voltage ...... 57

46. Doherty Amplifier, Efficiency vs. Input Voltage Level ...... 59

47. Use of Class C amplifier as the Auxiliary Amplifier...... 61

48. Doherty Amplifier with Arbitrary ZT and RL...... 63

49. Fundamental Device Current of the Main (Class B) Amplifier, and the Auxiliary (Class C) Amplifier ...... 64

50. Overall Efficiency of the New Configuration...... 68

51. Required Auxiliary DC Drain Voltage vs. r...... 69

52. Simulated Results of the Doherty Amplifier ...... 70

53. Comparison of the Class B Amplifier and the Doherty Amplifier ...... 71

ix ABSTRACT

DESIGN OF RADIO FREQUENCY POWER AMPLIFIERS FOR

HIGH EFFICIENCY AND HIGH LINEARITY

Tian He

Master of Science in Electrical and Computer Engineering

Electronic Engineering Option

California State University, Chico

Fall 2009

The aim of this thesis work is to investigate two of the most important characteristics of Radio Frequency power amplifiers, namely, efficiency and linearity.

First, the fundamental theory of power amplifier design at a single power level is discussed, followed by a standard design procedure developed to give maximum efficiency at a single power level. Then the Class F amplifier theory is introduced as a way of further increasing the efficiency, based on which a Class F amplifier is designed and implemented.

The Doherty amplifier design and practice as a way of boosting the back-off efficiency and in the mean time maintaining high linearity is discussed. A new Doherty amplifier design approach is proposed. This approach accepts the insufficient current of

x the auxiliary device rather than changing it to meet the prescribed behavior, thus simplifying the circuit. It is capable of giving comparable back-off efficiency and maintaining high linearity.

CHAPTER I

INTRODUCTION

Radio frequency (RF) power amplifiers (PA), as the name indicates, have two distinct features:

1. These amplifiers work at radio frequency, which is customarily associated from VHF to the S band [1]. The Microwave frequency range has been traditionally associated with radar systems operating in the C band and above.

2. Output power is relatively large, in practice, at least 1 Watt. At such a high level, life expectancy of expensive test equipments is greatly reduced, and large heat sinks are commonly used. Essentially, the primary duty of a power amplifier is to convert

DC power into AC power as efficiently as possible, requiring as little input power as possible. However, depending on the application, different parameters are emphasized.

For example, for mobile devices where the battery life is crucial and large pieces of heat sink are impossible, efficiency is the primary goal; While for base stations where cooling facilities have at least the space, more heat dissipation is tolerable although undesirable, but due to the prevalence of signals with a very high PAR1 (easily reaching 6dB back- off), the efficiency in a power range instead of a single power level becomes crucial. One always desires all, but one can never have all. At some point, decisions have to be made on which is desired more.

1 Peak to Average Ratio of power

1 2

This chapter will begin with the transfer characteristic of transistors, which is the very key to understanding many aspects of RF power amplifier design. Then amplifier classes will be defined and analyzed, followed by nonlinear analyses. In the end, load line matching is introduced and explained.

Transistor Transfer Characteristic

Field Effect Transistors (FETs) are voltage controlled current sources

(VCCS), as shown in Figure 1. When Vgs is less than the threshold voltage (in this case

2.6 V), the drain current Ids is 0. As Vgs increases, the transistor enters the turned-on region, and Ids increases in a nonlinear fashion. And eventually, Ids will remain almost a constant.

Fig. 1. Typical FET transfer characteristic, generated from simulation in AWR Microwave Office. X-axis is the drain-source voltage. Y-axis is the drain source current. As an n-channel FET, it is only an example. What will be discussed is general and not limited to n-channel FET.

In the turned-on region, although the transfer characteristic is nonlinear, if the gate voltage scale is very small, nonlinearity becomes hardly legible, then the transistor could be treated as a linear system—this is the so-called small signal analysis. For power amplifiers, the required output power is so high that normally the whole turned-on region is involved, thus small signal analysis becomes inaccurate. However, as long as the transistor works solely in the turned-on region, it could still be approximated as a linear system. This is the theoretical foundation of linear power amplifier design.

Amplifier Classes

Conventionally, depending on different gate bias points, there are four amplifier classes—Class A, Class AB, Class B and Class C, all of which use VCCS as the transistor model. If transistors are modeled as switches, there are Class D and Class E.

Then again, if modulation is considered, there is Class F. At the higher range RF frequencies, switch model is hardly realistic since no transistors can switch fast enough.

In this section and throughout this thesis, transistors are modeled as VCCS. Thus, only the four conventional classes will be introduced and explained. As for Class F, it will be illustrated in detail in Chapter III.

Before we proceed, Figure 1 needs to be modified to simplify the analysis.

First, the turned-on region is weakly nonlinear thus is approximated by a linear function.

Then, the threshold voltage is normalized to 0. In the end, the point (Vmax, Imax) is where the drain current just reaches the maximum value. The modified transfer characteristic is shown in Figure 2. Simple figure notwithstanding, it is the key to understanding many aspects in RF power amplifier design and will be revisited many times.

Fig. 2. General FET transfer characteristic (gm represents the slope).

Depending on where the gate quiescent point Vq is, amplifiers are classified four modes, namely Class A, AB, B and C, as shown in Table 1. Conduction angle  indicates the proportion of the RF cycle for which conduction occurs, as illustrated in

Figure 3. Note that only Class A mode conducts currents in the whole RF cycle.

TABLE 1 CONVENTIONAL AMPLIFIER MODES

Mode Vq Quiescent Current Conduction Angle  A 2

AB (, 2)

B 0 0  C 0 (0, )

Fig. 3. Illustration of conduction angle.

For those reduced angle amplifiers, the corresponding current waveforms are not sinusoidal any more, it contains significant amount of harmonics. To simplify the analysis, the output termination is assumed to be a perfect harmonic short circuit, along with a resistive termination RL at the fundamental, leaving the DC component Idc and fundamental component I1, both of which are functions of  and Ipk:

(1)

(2)

In order to better understand the effect of reducing conduction angle,

Equations 1 and 2 are plotted in Figure 4. It is obvious that the DC component keeps decreasing as the conduction angle decreases, while the fundamental component in Class

Conduction angle 

Fig. 4. Fundamental and DC current amplitude vs. conduction angle. Ipk is normalized to 1.

AB mode is higher than that in Class A mode. Class B mode has the same fundamental component value with Class A, but a smaller DC component.

To analyze the efficiency and output power capability of amplifiers in different modes, other than the device current, it is necessary to know the drain voltage.

A general amplifier structure is shown in Figure 5(a) and explained as follows:

1. Since the primary concern here is the drain voltage, the input circuit is represented by a voltage source for simplicity.

2. The “RF Choke” is an inductor, whose inductance is large enough to prevent the RF signal from flowing into the DC source.

3. The “DC blocking capacitor” as the name indicates prevents DC current from flowing into the load. It is required that the impedance of the capacitance is negligible at the desired RF frequency.

Fig. 5. Calculation of drain voltage using superposition principle. I1 is the fundamental drain current. Idc is the DC drain current.

Since the whole circuit is linear except for the transistor, superposition principle could be applied to get the drain voltage Vd. The process is shown in Figure 5(b and c). It can be seen that the DC component of the drain voltage is determined by the

DC bias Vdc, thus these two will not be differentiated in this thesis. Also the fundamental drain voltage swing V1 is determined by I1 • RL, thus it seems that V1 could be as large as possible as long as RL is large enough. However, this is not true because the transistor drain has a knee voltage Vknee, under which value the VCCS model becomes invalid and so does the whole analysis above, as shown in Figure 6. To avoid this, the maximum V1 should be Vdc - Vknee.

Fig. 6. IVCurve example to shown the knee voltage.

The fundamental output power could be expressed as:

(3)

While the DC power is:

(4)

Define the drain efficiency as:

(5)

From Equations 1 and 2, the ratio of I1 and Idc is solely the function of conduction angle . While V1 could be controlled by the selection RL to reach the maximum value Vdc - Vknee. Here to simplify the analysis, it is assumed that Vknee = 0, in which case Equation 5 could be expressed as:

(6)

And the optimum load resistance that maximizes output voltage swing is:

(7)

If the input power is considered, there is another efficiency definition, which is called

Power Added Efficiency (PAE):

(8)

However, in this thesis, unless stated otherwise, the drain efficiency will be used.

With the efficiency discussed, it is worthwhile to compare the output power capability of different amplifier classes. In order to proceed, several conditions need to be met:

1. Input voltage swing Vgs needs to be accommodated to make sure Ipk is the same for all modes. And it should not reach the point Vmax.

2. Drain DC voltage Vdc is the same all modes.

3. Optimum load resistance Ropt is assumed for all modes, though, depending on different conduction angle, Ropt will be different. However, all that matters is that maximum drain voltage swing is achieved.

4. Output power is calculated relatively to Class A.

With the above conditions met, along with Equations 2 and 3, it is easy to derive

(9)

Based on Equations 6 and 9, the efficiency characteristic and output power capability as functions of conduction angle are plotted in Figure 7.

Conduction angle 

Fig. 7. Efficiency characteristic and output power capability as a function of conduction angle.

It can be seen from Figure 7 that Class AB has higher efficiency as well as output power than Class A; Class B has exactly the same output power with but a higher efficiency than Class A; Class C has ever-increasing efficiency but drastically decreasing output power.

Linearity Analysis

In RF power amplifier design, linearity is examined with reference to input and output power. Consider the general amplifier structure shown in Figure 5(a), the

11 output power naturally is the fundamental power delivered to RL, which is P1 as specified in Equation 3. The input power is, as will be proved in the next chapter, proportional to the square of gate voltage swing ,wwhere Vgs = Vq + Vin • cos(ωt). Thus, in order to analyze the amplifier linearity, the relationship between P1 and nneeds to be established.

If the load resistance RL is set to be optimum load resistance Ropt at maximum

Vin, P1 could be represented by:

(10)

With the above equation, all we need to do is to represent I1 by Vgs. The simplest case is Class A, where I1 = gm • Vin, leaving , from which it is shown that Class A amplifiers are indeed linear amplifiers.

As for the reduced angle amplifiers, from Figure 2, as long as Vgs does not reach Vmax, we have:

(11)

which, after being substituted for Ipk from Equation 2, gives:

(12)

Since the conduction angle  is a function of Vq and Vin, as shown in the following:

(13)

Combining Equations 10, 12, and 13

(14)

If Vq is 0, meaning it is Class B mode, then  will always be  no matter how

Vin changes, P1 becomes a linear function of . Thus, Class B amplifiers are also linear amplifiers. However for other reduced conduction angle amplifiers, the relationship between P1 and wwould not be linear because  will always change with Vin. To sum up, Class A amplifiers are linear; reduced conduction angle amplifiers are nonlinear by nature except for Class B amplifiers. This can be shown in Figure 8.

Fig. 8. Linearity of different amplifier classes.

Compression Analysis

It is mentioned in the previous section that Vgs should not exceed Vmax to prevent the drain current clipping. Now it is time to investigate the impact this clipping.

Figure 9 illustrates drain current clipping of reduced conduction angle amplifiers. (Vmax, Imax) is as indicated in Figure 2. Here the gate voltage swing obviously

t

Fig. 9. Illustration of drain current clipping of reduced conduction angle.

surpasses Vmax, causing the drain current to be clipped. Beside the conduction angle , define angle , which represents the proportion of a RF cycle for which current clipping occurs, as indicated in Figure 9.  could be represented by:

(15)

Equation 15 is also true for Class A amplifiers. After applying Fourier analysis to the drain current shown in Figure 9, it is not difficult to get the fundamental drain current

(16)

For Class A amplifier, the fundamental drain current is simpler than Equation

16, for it only has one variable . The relationship is:

(17)

Again, assume the presence of Ropt that keeps the drain voltage swing at its maximum value Vdc - Vknee, the fundamental output power versus input power could be calculated based on Equations 13, 15, 17, and 16, which is plotted in Figure 10, where power compression is shown.

Fig. 10. Effects of clipped drain current on output power compression.

Power Match and Load Pull Method

It is already mentioned that as the input power increases, in order to prevent drain current from reaching Imax too early, and the fundamental drain voltage from reaching Vdc - Vknee too early, the load resistance has to be Ropt in Equation 7. With this in mind, it seems that all we need to do is to design an impedance transformer that transforms the output load impedance into Ropt. However, in practice, especially at RF frequencies, FETs are not simply VCCS. There are parasitic components, as indicated in

Figure 11.

Fig. 11. Impact of package parasitic components on load termination. The block between input tab and output tab represents the transistor.

So the task becomes finding the right ZL at plane B so that Ropt will be presented at plane A. This is called power match, in comparison to conjugate match. If the parasitic components are available from the manufacturer, power matching becomes an algebraic manipulation. However, if the transistor is modeled behaviorally, this would become impossible.

A simple solution is set the drain current to its maximum swing, and sweep ZL to get the value which gives maximum output power. This method is called load pull method. It was first introduced by Steve Cripps in 1983 [2] and well explained in his book [3]. In the following chapter, a design routine will be developed based on this method.

CHAPTER II

LOAD PULL DESIGN PROCEDURE

The transistor data sheet from the manufacture usually specifies a list of optimal source and load impedances of the transistor at different frequencies, under a certain bias setting. The manufacture obtains these values experimentally. A general example is shown in Figure 12. If one happens to design under the specified conditions, then the task is simplified into transforming the source and load impedances into those listed in the table.1

However, the manufacture can only give these parameters at certain frequencies and a certain bias setting. One has to know how to get these parameters. In this chapter, a design procedure is developed based on load pull method [2]. This procedure assumes that a transistor model is available from the manufacturer and a CAD tool is also available. Usually in the industry, the RF PA designers would possess a CAD tool. AWR Corporation’s Microwave Office is used to demonstrate the procedure in this work. However, the functionalities involved are general and can be found in other CADs too. The theoretic foundation of the design procedure is almost covered thoroughly in

Chapter I, except for the input matching theory, which will be discussed first in before introducing the procedure.

1 It is in fact not that simple, considering others factors such as Quality factor, phase frequency response etc.

17 18

Fig. 12. Optimal source and load impedances of a transistor.

Source: Adapted from Cree, Inc., CGH40010 Rev 2.0 Preliminary – December 2008. Retrieved October 5, 2009 from the World Wide Web: http://www.cree.com/cn/products/pdf/CGH40010.pdf

Input Matching Theory

At the input side of the amplifier, what matters is how much gate voltage swing is available given a certain input power. However, this problem is often replaced with maximum power transfer from the input to the gate without further explanations. In this section, the relationship between these two problems will be investigated.

First, it is necessary to establish the model to investigate the relationship between gate power and gate voltage. Figure 13(a) shows the transistor with a transmission line attached to the gate. This transmission line represents the last

Fig. 13. Model to investigate the relationship between gate power and gate voltage.

infinitesimal piece of any input matching network. And the point of interest is labeled in red, which is the gate. Figure 13(b) further simplifies the model, where Zin is the input impedance looking into the gate of the transistor. Note that the transistor as a nonlinear device does not really has a linear parameter Zin. However, we can analyze it at a certain harmonic frequency, usually the fundamental frequency, which is so called “large signal impedance.”

The relationship between reflection coefficient Гin and Zin is

(18)

The gate voltage and current can be represented by

(19)

The gate power is

(20)

Substitute Equations 18 and 19 into 20, after some rearrangement we have

(21)

Considering

(22)

Equation 21 can be further simplified into

(23)

It is thus obvious that maximum gate power indeed corresponds to maximum gate voltage swing.

Now all that is left is to make sure maximum power is delivered to the gate.

This problem is relatively straightforward. In Figure 14, the input matching network is

Fig. 14. Maximum power transfer illustration.

represented by a black box named IMN. Again, the transmission line with a line impedance of Z0 represents the minute connection. Since only inductors, capacitors and transmission lines are used to design IMNs, they are assumed to be ideal and lossless.

Thus to get maximum gate power P2 is equivalent to maximizing P1. It then becomes the classical conjugate matching problem. All we need to do is to make sure , in which case P1 is represented by

(24)

In most cases, Zs and Z0 are both 50Ω so that Гs becomes zero, maximizing

2 P1.

Design Procedure

It is now possible to develop a practical design procedure based on the theory introduced so far. To make the procedure easier to understand, it is assisted by a Class

AB amplifier example. The transistor in the example is Cree CGH40010 GaN HEMT; the frequency is 2.5GHz; and the CAD tool chosen is AWR Microwave Office, the use of which is available from the documentation of AWR Corporation [4]. Some key points that have been used in this work are to be mentioned. Although the whole procedure is performed in a CAD tool, the procedure can also be performed experimentally with a transistor device.

Step 1: Get the Transfer Characteristic of the Transistor

As discussed in Chapter I, the optimal load resistance Ropt is chosen to increase the power compression point in the output versus input power transfer characteristic. It is not difficult to see that if the load resistance is greater than Ropt, before reaching the maximum value, the drain voltage swing thus the output power is

2 Details of derivation are available in Chapter 2 of R. Ludwig, RF Circuit Design Theory and Applications. Upper Saddle River, NJ: Prentice-Hall, Inc., 2000.

22 actually greater, as indicated in Figure 15. If one desires to sweep the load impedance to get the value that delivers the most output power, the gate voltage swing has to be large

Fig. 15. Illustration of how a larger load resistance could make the transistor output power increase faster but compress earlier. The green dotted lines are boundaries that prevent the operation of the case RL > Ropt from compression. The red dashed lines are to help understand the comparison of voltage swings of the two cases.

enough to make Ids reach Imax. This information could of course be retrieved from the IV curve. But it is more obvious in the transistor transfer characteristic.

The circuit setup to get the transistor transfer characteristic is shown in Figure

16, while the result is shown in Figure 17. Note that the Ids vs. Vgs transfer characteristic has multiple traces depending on different drain bias voltages, listed as parameters from p1 to p7. This is mostly because thermal effects are considered in the model. But this does not interfere with threshold gate voltage and Vmax, whose values are Vth = -2.58V and Vmax = 1.21V approximately.

Vin=-6 SWPVAR ID=SWP1 VarName="Vin" Values=stepped(-6,5,0.2) UnitType=None DCVS ID=V2 Xo . . . Xn V=Vds V

2 CGH40010F_r4a ID=40010F1 1 Tcase=25 RTH=5 Vds=6 SWPVAR DCVS 4 Th 3 ID=SWP2 ID=V1 VarName="Vds" V=Vin V Values=stepped(6,30,4) UnitType=None

Xo . . . Xn

Fig. 16. Circuit setup to get the transfer characteristic of the transistor.

Fig. 17. Transfer characteristic of the transistor.

Step 2: Get the Optimum Load Impedance Zload

In RF circuit simulation, harmonic balance ports are widely used mainly due to two reasons. One, time domain analyses at such high frequencies take a long time to complete. Two, in practice, power instead of voltage is used as the measurement quantity.

However, in this step, if harmonic balance port is used as the input port, it takes some extra steps to tune the gate voltage swing so that it will reach Vmax. For this reason, the whole input side is represented by an ideal voltage source, as shown in Figure 18, where the offset is set to be the gate bias voltage, and the magnitude is just enough to make the swing reach Vmax.

Fig. 18. Load pull method. Note for the bias tee component HBTUNER2, the reflection coefficients seen into port 1 is configured at the fundamental frequency, the second harmonic, as well as the third harmonic frequency.

Now it is time to sweep the load impedance to get the optimum load impedance Zload that gives maximum output power, beyond which the amplifier will be driven into compression. To do this, an element called HBTUNER2 (Harmonic Balance

Lossless Tuner with Bias Tee) is used. It is a frequency-dependent, lossless network which transforms the impedance seen at port 2 to user-defined impedance seen at port 1.

Note that as a Class AB amplifier it is supposed to have harmonic short at the output side, in this case up to 3rd order, which is usually enough. That is why the second and third

5 order harmonic reflection coefficients Г2f0 = Г3f0 = 0.99180 . Since the reflection coefficient at fundamental frequency Гf0 is the one that is going to be swept, the start value in the configured in the schematics can be anything, in this example it is set to the default value 0.5  0.

Next, a measurement of the output power needs to be performed so that it can be used later on to plot the contour. Since this contour is actually a 2D contour, it is advised that at each swept output impedance point there is only one measurement value.

If not, MWO will take the first data point. For that reason, the frequency range is set to be a single frequency point of interest.

Next, perform load pull analysis with the “AWR Load Pull Wizard.” Note that since the gate voltage swing is set to make the drain current reach its maximum value, nonlinearity becomes so severe that the CAD tool will almost definitely fail to converge at certain output impedance points. Normally when a convergence failure happens in simulation, one has to solve the problem in order to proceed (solutions are usually provided by the CAD developer). However, in this case, it is highly possible that the impedance point which gives convergence failure is not of interest at all, and all we want

26 is a rough contour that indicates where the optimum load impedance might be. For that reason, to save time, one can simply choose “continue sweep on failure” in the harmonic balance advanced settings to begin with. The obtained contour is shown in Figure 19,

p1: = 26 LPCS(44,26,1) Load Pull Data Contourp1 Graph p2: = 27

8 Swp Max Pout . 1.0

p80

6 337 p3: = 28 . p9 p10

0 0 p11 . p12 2 p4: = 29

p13 4

. 0 p14 0 p5: = 30 3. p15 0 p6: = 31 p16 4.

2 p17 . . 5 0 p7: = 32

p18 p8: = 33 10.0 p9: = 34 10.0 p7 0 0.2 0.4 0.6 0.8 1.0 2.0 3.0 4.0 5.0 p10: = 35 p6 p5

p4 p11: = 36

0 . 0 1

p3 - p12: = 37 p2

. 0

0 .

- 5

- p13: = 38

0 . 4

- p14: = 39

3 4 - . p15: = 40 0

. p16: = 41

2 6 - . 0 - p17: = 42 8 . Swp Min 0

-1.0 1 p18: = 43

Fig. 19. Load pull contour on the whole smith chart area.

from which it is observed that output impedance that falls on contour p18 can deliver

43dBm output power. Now shrink the sweeping range into an area that roughly speaking only covers the inside of p17, as shown in Figure 20. Perform another load pull analysis to get even better and more accurate load pull contour closer to the optimum value. The result is shown in Figure 21. Note that the contour covers more sweeping region that

Fig. 20. Shrinked sweep region.

specified, but that is not an important problem since the region of interest is known. It can be seen that a much smaller p18 is available that delivers 0.5dB more output power that previous result. At this stage, any point on p18 could be chosen as the load impedance.

But, note that p18 actually crosses the x axis twice, indicating two possible solutions that do not involve reactive values. This is desirable because it will simplify the matching network design. Out of these two points, the one that is further from the origin allows a matching network with a higher quality factor. Thus, the desired load reflection coefficient is -0.4, which gives Zload = 21.43Ω. The result can be verified by setting Гf0 =

-0.4 in HBTUNER2 and measuring the output power.

Step 3: Get the Optimum Source Impedance Zsource

It is already proved in the previous section that the input network design is just a matter of conjugate match at the fundamental frequency. Thus the optimum source impedance Zsource is actually the conjugate of the impedance Zin looking into the gate of

Fig. 21. Second load pull analysis with shrinked sweep region.

the transistor, which can be measured from Figure 18. In this case Zin = 1.704 + j 

3.012Ω, thus the optimum source impedance is 1.704 – j  3.012Ω.

Step 4: Design the Matching Networks

This step is really fundamental in any RF circuit design. There are several design variants for matching networks. Choice of a matching network can depend on parameters such as circuit dimension, quality factor, bandwidth, and the availability of components. Figure 22 shows one possible configuration of matching networks, where all the components are ideal. Note that there is a series capacitor on both side of the transistor to block the DC current from flowing into the source and the load. Also at the

Fig. 22. Matching networks of the design example.

load side there is a harmonic trap that presents an open circuit at the designed frequency

2.5GHz, and a short circuit for all other harmonics, so that only the fundamental frequency power is transmitted.

Step 5: Bias the Circuit and Simulate

The design of bias networks plays an important role in establishing stable operations, since at lower frequencies the impedance presented to the transistor is mainly determined by the bias circuitry. Figure 23 shows the complete amplifier prototype with the bias networks, as well as the matching networks. All components are ideal. Since for power amplifiers the most important parameter is efficiency, no resistive network is present in the bias network. Transmission line “TL2” is a quarter-wave TL with 100Ω line impedance. It blocks fundamental frequency signals from flowing into the voltage source, presents a further second harmonic short circuit, and passes the DC voltage to the

CAP CAP ID=C3 ID=C4 C=1e5 pF C=100 pF

DCVS ID=V2 V=28 V

DCVS ID=V1 V=2.1 V TLIN ID=TL2 TLIN IND Z0=100 Ohm ID=TL1 ID=L2 EL=90 Deg CAP Z0=32.73 Ohm L=1e5 nH F0=2.5 GHz ID=C6 EL=90 Deg PORT_PS1 C=1000 pF F0=2.5 GHz P=1 Z=50 Ohm PStart=18 dBm CAP 2 PStop=28 dBm ID=C1 PORT C=5.27 pF PStep=1 dB CGH40010F_r4a P=2 ID=40010F1 CAP Z=50 Ohm 1 IND Tcase=25 ID=L3 ID=C5 RTH=5 L=0.4053 nH C=10 pF

Th IND 4 3 ID=L1 L=0.597 nH

Fig. 23. Amplifier circuit prototype.

drain. At the gate side, inductor “L2” works as a RF Choke. Both voltage sources are connected with a large capacitor in parallel to prevent sudden change of the voltage.

Figure 24 shows the output power and power add efficiency (PAE) versus input power. It is shown that before the amplifier reaches power compression; the efficiency is well above 60%.

Step 6: Optimization with Lossy Components

Once the prototype is verified by simulation, the ideal components need to be replaced with realistic lossy ones. This would require further tuning and optimization, details of which are covered in the documentation of the CAD tools.

PAE(PORT_1,PORT_2)[1,X] (R) Prototype DB(|Pcomp(PORT_2,1)|)[1,X] (L, dBm) Prototype Output power and PAE vs. input power 44 70

42 60

40 50 PAE Output power (dBm) 38 40

36 30 18 20 22 24 26 28 Power (dBm)

Fig. 24. Output power and PAE vs. input power.

CHAPTER III

CLASS F AMPLIFIER THEORY

AND DESIGN

The Class F amplifier is a special kind of reduced angle amplifier with load harmonic control to shape the drain voltage in a way that it does not or rarely does coincide with drain current, thus greatly reducing the power dissipated by the device, and hence increasing the efficiency. In the Class F amplifier design, the transistor is modeled as a controlled current source as opposed to a switch in Class D and Class E designs. In this chapter, first the theory of Class F amplifiers is explained, and then based on this, along with what has been discussed so far, a Class F amplifier is designed.

Class F Theory

For conventional reduced angle amplifiers such as Class AB, Class B and

Class C amplifiers, the load should present perfect short circuits to all the drain current harmonics. If the load network fails to do so, the drain voltage will change from a sinusoidal wave to other shapes due to the existence of harmonic components. It is possible to manipulate the load network in some ways so that a square wave or similarly shaped drain voltage signal is generated, ultimately increasing the efficiency. This type of amplifier is termed as the Class F amplifier.

32 33

Before getting into details of how to design such a load network, it is beneficial to discuss the problem mathematically. It is fairly easy to prove using Fourier analysis that a square wave does not have even harmonics. On the other hand, by adding higher and higher order odd harmonics with proper coefficients, a sinusoidal wave will gradually become a square wave. Consider the simplest case of the drain voltage as in

Equation 25, where only a 3rd harmonic component is added.

(25)

Note that it is assumed the 3rd order harmonic component of the drain current carries the opposite sign of the fundamental one, which is true for Class AB amplifiers.

Because of this, and the fact that a negative 3rd harmonic load resistance is not practical, here in Equation 25 the 3rd order voltage component carries a negative sign as well. This would not be necessary if Class C is considered. However, this detail is not going to affect the final conclusion and thus is not fully unfolded.

Figure 25 shows the squaring effects of 3rd order harmonic on sinusoidal waveforms, where V1 is normalized to 1. It is fairly easy to prove from Equation 25 that

1. As long as V3/V1 < 1/9, the voltage waveform will only have peak values at

 = n(n = 0, +1,+2, …), and the peak voltage will keep decreasing to

2. As soon as V3/V1 < 1/9, the voltage waveform will grow other peaks, but the voltage peak still keeps decreasing until V3/V1 = 01/6, where the minimum Vpk is reached:

Fig. 25. Effects of third order harmonic on sinusoidal waveform.

3. As V3/V1 becomes greater than 1/6, the voltage peak begins to increase. At approximately the point when V3/V1 = 0.4,

Vpk = V1

All three cases stated above are shown in Figure 25. The special case when

V3/V1 = 1/9 is termed as maximum flat case. In general, any value of V3/V1 between (0,

0.4) generates a lower peak voltage than V1 by a factor of k. This means that without changing the DC power, the drain fundamental voltage could be increased by a factor of k without causing the overall drain voltage to shoot over the maximum voltage swing, so that the efficiency is also increased by a factor of k and the power compression will occur at a larger input power level. This is the essence of the Class F structure.

Although the waveform can be squared up more with higher order odd harmonics, the mathematical procedure to determine the optimum case becomes more

35 and more cumbersome. Also, there is a matter of realization. Thus, here only up to 3rd order is discussed.

Now it is time to consider the design of the load network to shape the drain voltage as desired. First, it is necessary to present a short circuit for all the even harmonics of the drain current. This can be easily done by adding a short circuited quarter-wave transmission line. Next, the fundamental load resistance R1 and third order load resistance R3 need to be selected carefully so that V3/V1is 1/6, or at least in the range of (0, 0.4). This would require the frequency analysis of the drain current. Ideally, this is quite easy once the bias condition is determined. However, in practice it is far more complicated. For one thing, the device is not exactly a VCCS in the turned-on region. For another the knee effect could produce substantial amount of harmonics. The folklore notion is that the odd order harmonics should be presented with an open circuit for best efficiency performance. This is justified mathematically by Cripps [3].

In short, the Class F amplifier in practice is usually a reduced angle amplifier with short circuit termination for even order harmonics and open circuit termination for odd ones.

Circuit Design

A 2.5GHz single tone Class F power amplifier is designed and fabricated. The transistor chosen is Cree CGH40010 GaN HEMT. The design is based on a large signal model provided by Cree. Analysis is performed using AWR Microwave Office. The design uses optimum load and source impedances provided by Cree, Inc. under the bias condition VDD = 28V and IDQ = 200mA. Since the drain bias voltage is given directly,

36 while the gate bias voltage VGG is not, it is necessary to tweak the gate voltage until IDQ becomes 200mA, as shown in Figure 26.

2 200 mA 200 mA DCVS ID=V1 0.00305 mA V=-2.096 V CGH40010F_r4a DCVS 1 ID=40010F1 ID=V2 0.00305 mA Tcase=25 V=28 V RTH=5

4 Th 3

5.58e3 mA

Fig. 26. Circuit to get gate bias voltage.

Step 1: Circuit Design with Ideal Components

With the bias voltages and load/source impedance available, a prototype can be built with ideal components. Figure 27 shows the input network. A quarter-wave transmission line “TL3” is used to prevent RF signal from flowing into the DC voltage source. Figure 28 shows the output network, where “TL3” and “TL4” together presents an open circuit to the drain at the 3rd order harmonic of the designed frequency, “TL5” works as the RF choke and also presents a short circuit to the drain at the 2nd order harmonic of the designed frequency. The top level schematic of the amplifier is shown in

Figure 29. This schematic is analyzed with Microwave Office. And the output

Fig. 27. Ideal input matching network designed using transmission lines.

Fig. 28. Ideal output network designed using transmission lines.

Fig. 29. Amplifier using ideal components.

power/PAE vs. input power plot is shown in Figure 30. It is observed that maximum efficiency of this configuration is 84.34%, with an output power of more than 39dBm.

However it should be noted that at that point the amplifier has already reached well into compression.

Output power (L, dBm)

PAE (%) (R)

Ideal 26 dBm 40 84.39 90

39 80

26 dBm 39.047 dBm

38 70 PAE (%) Output power (dBm) power Output 37 60

36 50 20 22 24 26 28 30 Power (dBm)

Fig. 30. Output power and PAE vs. input power of the amplifier using ideal components.

Note that if the circuit is simple, this step could actually be passed and design can start directly with realistic lossy components.

Step 2: Convert the Ideal Circuits Into Realistic Ones

First, the board and the metal material used for transmission line need to be determined. In this case, Taconic ORCER RF-35 is chosen to be the board material with a thickness of 60mils, while the metal is 1oz1 copper. RF-35 has a stable = 3.5 over a wide frequency band from 2GHz to 10GHz, and a dissipation factor of 0.0018 at 2.5GHz.

The parameters above are listed in Table 2 and can be used to configure the Microstrip

Substrate Definition (i.e., MSUB in Microwave Office) as shown in Figure 31.

TABLE 2 SUBSTRATE PROPERTIES

Substrate Properties Value Dielectric constant (relative permittivity) 3.5 Board thickness 60mils (1.52mm) Copper thickness 1oz (35µm) Copper resistivity relative to gold 0.7727 Dissipation factor (loss tangent) 0.0018

With substrate definition readily available, the ideal lossless transmission line expressed in phase form can be converted into lossy realistic transmission lines. This can be done manually through equations available in RF Circuit Design Theory and

Applications [1]. However, this can be quite cumbersome. Here an embedded tool in

Microwave Office called TXLine is used (Figure 32). It can be accessed under “Tools-

>TXLine.”

1 Note that oz (ounce) is actually a unit of mass. In the PCB industry, it is widely used to express the thickness of the metal with oz. The conversion is done like this: distribute 1 oz metal evenly to an area of 1ft2, the thickness is what 1 oz represents. In the case of copper, 1 oz represents 35m.

Fig. 31. Microstrip substrate definition.

Fig. 32. TXLine, used to convert between electrical characteristics and physical ones.

Two problems need to be addressed while using non ideal lumped elements and transmission lines in practice.

One is that the lumped components of certain value at such high frequencies might not be available. Take Figure 29 for example. The DC blocking capacitors “C1” and “C2” have a value of 1000pF. This is already close to the upper bound of chip capacitors at 2.5GHz. Thus, it should be replaced with a smaller, more practical capacitor. However, the reason why such large capacitance was chosen at the first place was to make sure the impedance of the capacitor is small enough at operating frequency to be ignored. If the capacitance is changed to a much smaller value, say 1pF, then the matching network needs to be redesigned. Therefore, it is suggested that this should be considered at the stage of ideal circuit design to save some repetitive work. In this design example, 0.7pF is chosen as the DC blocking capacitance, thus the matching network is redesigned (directly with practical microstrip lines though).

Another problem is the effects of the microstrip line junction on the lengths of the lines connected to it. Figure 33 shows four microstrip lines connected by a junction component named “MCROSS.” When designing the impedance network four such

Fig. 33. Four microstrip lines with a junction.

42 transmission lines are connected to an artificial “point,” which has no physical dimensions whatsoever. But in practice, it is necessary to investigate the junction.

Figure 34 is from the help file of the “MCROSS” component in Microwave

Office. It is used here to explain how to connect several lines together. W1 to W4 are

Fig. 34. Illustration of the junction.

width of the connected lines, whose reference planes are the black dashed lines in

Microwave Office, meaning the “MCROSS” component is bounded by the black dashed lines. However, in practice the artificial “point” mentioned above is usually transformed into two reference planes represented by the red dashed line. For this reason, if the line connected to port 1 has a length of L in the design, once it is connected in Microwave

Office with MCROSS, 0.5 · W4 has to be subtracted from L. The same principle applied for all other ports.

Step 3: Tuning and Optimization

Tuning or optimization is inevitable after the conversion (or the direct design using lossy components), for small variations of transmission line length can affect the

43 performance severely at GHz frequencies. Using the optimizer in Microwave Office, it is fairly easy to make the matching network present the desired impedance at a certain frequency.

In this example, when it comes to the load network, first tune the harmonics termination to get 2nd order harmonic short and 3rd order harmonic open. Then tune the

nd fundamental matching to make the load impedance Zload. Note that short at 2 order harmonic can be quite accurate, while open circuit at 3rd order harmonic may not necessarily yield infinite impedance. The best value in this example is 2200ohms, which is good enough to get a high efficiency. The final schematics are shown in Figure 35,

Fig. 35. Top level lossy amplifier circuit.

Figure 36, and Figure 37. Note that several capacitors in different capacitance ranges are connected in parallel in the bias circuits. This is to provide a high frequency short circuit, and prevent sudden changes of the bias voltages. The simulated results of output power and PAE versus input power is shown in Figure 38, where it is observed that both power and efficiency are lower than their counterparts in the ideal case.

Fig. 36. Lossy input network.

Fig. 37. Lossy output network.

Output power (L, dBm)

PAE (%) (R) 25 dBm Lossy 76.34 40 80

39 72.5

25 dBm 38.766 dBm 38 65 PAE (%) PAE Output power (dBm) power Output 37 57.5

36 50 20 21 22 23 24 25 26 27 Power (dBm)

Fig. 38. Output power and PAE vs. input power of the amplifier using realistic lossy components.

CHAPTER IV

DESIGN IMPLEMENTATION AND

MEASUREMENTS

PCB Design

Microwave Office provides a layout view that shares the single intelligent database with the schematic view, which eliminates the need for design synchronization and back annotation. Basically, this means a component in the schematics is connected with a layout cell either automatically or through configuration. In this example, we have

TLs, lumped components, a transistor. TLs have built in layout cells, while the latter two kinds require new layout cells being created and linked manually. Details can be found in the Microwave Office documentation.

The layout view is shown in Figure 39, the list of components is shown in

Table 3, and the final PCB board is shown in Figure 40.

Measurement

Equipment

The designed power amplifier requires 25dBm input power, and generates in simulation 38.766 dBm output power. The RF Network Analyzers are usually not designed to handle such a high power level, especially the output power. For this reason, another calibrated power amplifier needs to be connected to port 1 of the Network

47 48

Fig. 39. Final layout.

TABLE 3 COMPONENT LIST

Designator Part number Capacitance

C1, C8 HFC1610VTTER70 0.7 pF

C2, C6 AQ137A390FA7ME 39 pF

C3, C7 AQ137A101FA7ME 100 pF

C4, C5 TPSE476K035S0200 47 uF

Fig. 40. Final PCB board.

Analyzer to boost the input power to 25dBm, and an attenuator is connected to port 2 of the Network Analyzer to reduce the output power to a moderate level. The diagram of this setup is shown in Figure 41. And a picture of the measurement setup is shown in

Figure 42.

Fig. 41. Measurement setup diagram.

Fig. 42. Measurement setup picture.

A complete list of test equipment is provided as follows:

 Agilent 8714ES 300kHz—3000MHz RF Network Analyzer.

 Agilent N5746A System DC Power Supply, used to provide gate biasing.

 Tektronix PS280 DC Power Supply, used to provide drain biasing and DC power.

 Mini-Circuit ZVE-8G+ 2000MHz—8000MHz 30dB Amplifier.1

 Anritsu 30dB Attenuator.

Procedure

1. Set the frequency range of the network analyzer to be 2.45GHz — 2.55GHz, as the amplifier is designed at 2.5GHz. Then calibrate it.

2. Connect the attenuator to the network analyzer to get the actual attenuation

Gatten at 2.5GHz.

1 Noted in this chapter as “pre-amplifier,” to prevent possible confusion.

3. Connect only the pre-amplifier and the attenuator to the network analyzer to get the actual overall gain Gaux of these two auxiliary devices at 2.5GHz.

4. Calculate the pre-amplifier gain Gpre at 2.5GHz according the equation Gpre +

Gatten = Gaux.

5. Set the power level of the network analyzer to be 25dBm - Gpre, so that the output power of the pre-amplifier will be 25dBm, which is fed into the power amplifier.

The RF output should be off.

6. Connect the DC power supplies to the amplifier and turn the transistor on.

7. Turn on the RF output of the network analyzer. Measure the S21 of the whole system at 2.5GHz. The gain of the amplifier Gamp can be calculated from equation

Gamp = S21 - Gaux.

Results

Following the procedure described above, the measurement results are shown in Table 4. The system gain S21 is shown in Figure 43.

TABLE 4 MEASUREMENT RESULTS

Gatten Gaux Gpre S21 Gamp Ids

-29.4dB -5dB 24.4dB 10.785dB 15.785dB 0.55A

Fig. 43. Forward gain of the whole system, including the pre-amplifier, the amplifier and the attenuator.

Since

the PAE is

CHAPTER V

DOHERTY AMPLIFIER MODIFICATION

Introduction

So far, it has been assumed that the input power of amplifiers is a constant, which is just enough to make the drain current reach its maximum value, not more and not less. When the input power is backed off from this level, the efficiency will decrease dramatically. In reality, this is a serious problem, for the applications of power amplifiers involve complex communication systems where the signals are rarely at a single power level. Thus, it is important to find a way to keep the efficiency high in a range of input power level.

The variation of the input power level from a signal source brings another problem—linearity. Although in previous chapters the output versus input power function has been, it has never been of primary concern since only one input power level is considered. With varied input drive, a nonlinear amplifier will no doubt cause output distortions.

The two problems described above have been under the attentions of researchers for many years. And many structures have been proposed to tackle one or both of them to some degree. Among them, the Doherty amplifier structure originally proposed by William H. Doherty in 1936 [5] is a good candidate for its simplicity, and its ability to keep the efficiency high in the back-off region, in the meantime maintain a

53 54 linear power transfer. The problem is that the original application used tubes instead of solid state transistors, while there are some features the former have and the latter don’t, it is just these features that make the Doherty amplifier readily realizable. In this chapter, first the main theory is introduced, followed by known realization techniques and in the end a new structure will be proposed.

The Doherty Amplifier

Before introducing the Doherty amplifier, it is beneficial to explain the underlying theory of how to maintain the efficiency as the input power decreases. The drain efficiency is, as described in Chapter I,

Where Vfund and Ifund are fundamental drain voltage and current, Vdc and Idc are drain DC voltage and current. For simplicity, suppose the amplifier is working in the Class B mode. When the input power decreases from the maximum, Ifund and Idc will decrease at the same rate, due to the fact that Class B amplifiers have a constant conduction angle.

Also, Vdc does not change with the input power. Thus to maintain the efficiency, Vfund has to be a constant as the input power decreases. However, as long as the load is a passive network, Vfund = Ifund · ZL, it is inevitable that Vfund will decrease as Ifund decreases. Thus, it is necessary to introduce active components into the load network, so that ZL will increase as Ifund decreases, ultimately keeping a constant drain voltage swing.

That is what the Doherty amplifier is about.

The typical Doherty amplifier structure is shown in Figure 44(a), where an auxiliary amplifier is inserted to the load. Perfect load harmonic trap is assumed and for simplicity not shown in the figure, thus only the fundamental component is considered.

The main amplifier is, from Figure 44(b), a Class B amplifier. The auxiliary amplifier works only in the 6 dB back-off region1 with twice the transconductance of the main. The realization of such an amplifier will be discussed later. For now, only the theoretical analysis is concerned. Ropt is 2 · Vdc/ Imax, the optimum load resistance of the single

Class B amplifier derived based on load line theory introduced in Chapter I.

Fig. 44. Doherty amplifier structure.

1 When the input voltage is half the maximum value, the input power is 6 dB less than the peak power.

From Figure 44(a), without referring to Figure 44(b), it is not difficult to derive

(26)

When , from Figure 44(b), the fundamental currents I1 and I2 can be expressed as

(27)

Here I2 lags I1 by 90. This can compensate the phase delay of the main amplifier due to the quarter wave transmission line. Insert Equation 27 into 26, we have

(28)

Note that V1 becomes irrelevant of Vin, more importantly it keeps constant at the value of maximum voltage swing, ensuring the highest efficiency of the main amplifier.

Another way of interpreting such a structure is by looking at how Z1 changes with Vin. From Equation 27 and 28,

It is obvious that as Vin decreases from Vmax to Vmax /2, the main amplifier load impedance Z1 will increase from Ropt to 2Ropt, thus maintaining the high efficiency of the main amplifier.

When , the auxiliary amplifier is turned off, thus the

Doherty structure becomes a single Class B amplifier, where

V1 = 2Ropt · gm · Vin (29)

Combining Equation 28 and 29, the amplitudes of voltage V1 and V2 are plotted in Figure 45.

Fig. 45. Amplitude of fundamental device voltage.

About linearity, notice that the two active devices are both working in the linear region, and the rest of the circuits are simple passive components, thus the power transfer should be linear. To prove it, when , based on Equation

27 and 28, the output power is

When , the auxiliary amplifier is turned off. Based on Equation 29, the output power is

Thus, no matter whether the auxiliary device is on or not, the output power is always proportional to the input power. The combined structure is linear.

The final analysis is efficiency. However, without knowing the implementation detail, we will not know the DC drain current of the auxiliary amplifier, making it impossible to calculate the efficiency in the 6 dB back-off region. But, as will be discussed in the next section, in practice the auxiliary amplifier usually works in Class

C mode, with certain bias control or input power control, or increased periphery. We

2 know that the ratio between Id and Ifund increases as the conduction angle increases, we also know the fundamental component of the auxiliary amplifier drain current. Thus, it is reasonable to calculate the DC drain current of the auxiliary amplifier assuming the conduction angle is always . The real efficiency can only be higher than this.

In the lower 6 dB regime only the main amplifier works; the efficiency will be

In the upper 6 dB regime, both amplifiers work; the efficiency is estimated to be no lower than

2 The mathematical expression is , where  is the conduction angle.

The overall efficiency is plotted in Figure 46. It can be seen that the efficiency reaches the maximum value for both maximum input power condition, and the 6 dB back-off condition. In the middle there is a small dip, this is because V2 is less than Vdc in the whole region.

0.8

0.7

0.6

0.5

0.4

0.3

Overall drain efficiency drain Overall 0.2

0.1

0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Normalized amplitude of input voltage V /V in max

Fig. 46. Doherty amplifier, efficiency vs. input voltage level.

Realization Problems and Known Remedies

In theory, the Doherty structure could solve both linearity and efficiency enhancement problems simply and elegantly. And it worked well on tube amplifiers.

However, when it comes to realization in solid state transistors, there are two main problems.

One is that the solid state transistor at high frequency cannot be simply modeled as a clean controlled current source, it has parasitic components attached. This has two consequences. One, the optimum load at peak input power is changed from Ropt

Ropt to Zopt1, at 6 dB back-off input power is changed from 2Ropt to Zopt2. Thus, the task of changing the load impedance from Ropt to 2Ropt as the input power decreases now becomes changing it from Zopt1 to Zopt2, which is much more difficult to tackle. The second consequence is the auxiliary amplifier cannot be considered as a totally open circuit as it is turned off. Thus, the power from the main amplifier will leak into the parasitic components of the auxiliary one, leading to an output power decrease. The first one is still under research and as far as the author knows there hasn’t been a good solution. The second consequence however is easily avoided by using an additional impedance converter at the auxiliary side, as described in detail by Youngoo Yang et al.

[6].

The other problem is, as mentioned in the previous section, the realization of the auxiliary device to generate such a current as I2, shown in Figure 44(b). Since the auxiliary amplifier is not turned on until the input voltage reaches half the maximum, an intuitive solution would be a Class C amplifier with a bias gate voltage of -Vmax/2.

However, the fundamental drain current of a Class C amplifier increases far slower than that of a Class B amplifier, as shown in Figure 47. Recall from Figure 44(b) that I2 is required to increase twice as fast as I1 in the upper 6 dB region. There are several techniques to deal with this problem.

One: Scale Up the Periphery of the Auxiliary Device

This method can be understood from Figure 47, where it is shown that a scaling factor of 2.5 is required in order for I2 to reach 0.5 · Imax when Vin = Vmax. This would result in a power utilization factor of -2.4 dB, at maximum input level. According

0.5 Main(gate biased at 0) 0.45 Auxil.(gate biased at -Vmax/2)

0.4

0.35

0.3

0.25

0.2

0.15

0.1

0.05

Normalized fundamental device current (Imax=1) device current fundamental Normalized 0 0 0.5Vmax Vmax 1.5Vmax Input voltage amplitude

Fig. 47. Use of Class C amplifier as the auxiliary amplifier.

to Cripps [3], this number is large enough to detract from the Doherty concept, despite its other benefits, not to mention that the increased cost. A similar solution is to use two

Class C amplifiers as the auxiliary device, so that I2 can approximately reach 0.4 · Imax when Vin = Vmax, which has the same disadvantages.

Two: Dynamic Bias Control

Another way of realizing I2 is by gradually increasing the gate quiescent voltage of the auxiliary transistor from to 0 as the input drive increases from Vmax/2 to

Vmax. This would clearly require a controller, which would in turn increase the size and cost of the circuit.

Three: Uneven Power Drive

Note from Figure 47 that since the gate of the auxiliary device is biased at

-Vmax/2, the drain current peak will not reach Imax until Vin = 1.5 · Vmax, and when it does, the fundamental drain current is close to 0.45 · Imax. If the input power is such unevenly

62 divided to the main and auxiliary amplifier that Vinaux = 1.5 · Vinmain, what is shown in

Figure 44(b) could be approximated. Details were explained by Jangheon Kim et al. [7].

This method is relatively easy to implement compared to solution 2, and cheaper than solution 1. The problem is, when utilizing Class C modes, the large negative swing of input voltage coincides with the drain output voltage peak, which is precisely the worst condition for reverse breakdown for any kind of transistor. Inducing more input power to the auxiliary Class C amplifier definitely makes this problem worse.

A New Configuration

In the 1930s, there were no solid state transistors, and what Doherty had in mind were tubes. Compared to a transistor, especially a FET, a tube has considerable more flexibility in its characteristics. Tubes, in general, do not display either of the compression mechanisms which are such important constraints in RF transistors, and they may also have extra grids which make the transconductance into a controllable parameter. In particular, the gm and Imax can be varied substantially. Doherty made use of a few such old tube tricks in order to approximate the required drive conditions for the main and auxiliary devices [3]. But unfortunately, such approximation becomes difficult when it comes to transistors.

Thus instead of trying to match the old circuit configuration with modern devices, it is worthwhile to start from the characteristics of solid state transistors, and come up with a new configuration.

There are two key features of this new configuration. One, the original

Doherty structure is the same, but the load resistance RL and the quarter wave line

63 impedance Zr as shown in Figure 48 are to be determined by the device currents. This feature however is not new. Similar work was done before and well explained by Masaya

Iwamoto et al. [8]. The difference between this work and previous ones brings up the second feature—the auxiliary current is accepted as it is, no scaling up the periphery, no bias control, no uneven power dividing.

Fig. 48. Doherty amplifier with arbitrary Zr and RL.

From Figure 48, it can be derived that

(30)

The goal still is to make V1 a constant during the input power back-off region, with a value of Vmaindc. Again, to simplify the discussion, the main amplifier is set to work in

Class B mode, while the auxiliary amplifier in Class C mode. The transistors used are identical.

Suppose the gate of the Class C amplifier is biased at –r · Vmax, where

. The transfer characteristics of both devices are shown in Figure 49. Note that the auxiliary transfer characteristic is actually weakly nonlinear, which can be approximated by a linear function

(31)

and I1 is

(32)

0.5 Main(Class B) 0.45 Auxiliary(Class C) Auxiliary linear approximation 0.4

0.35

0.3

0.25

0.2

0.15

0.1

0.05

Normalized fundamental device current (Imax=1) deviceNormalized current fundamental 0 0 rVmax Vmax Input voltage amplitude

Fig. 49. Fundamental device current of the main (Class B) amplifier, and the auxiliary (Class C) amplifier. The gate of the auxiliary amplifier is biased at –r · Vmax, where .

Insert Equation 31 and 32 into 30,

(33)

To make V1 independent upon Vin in the upper region (e.g., Vin ≥ r · Vmax),

gmZr = gaRL (34)

Substituting for gm and ga from Equation 31 and 32,

(35)

With gmZr = gaRL, V1 becomes

V1 = r · Zr · ga Vmax

Suppose the DC drain voltage of the main amplifier is Vmaindc, to maximize the efficiency in the upper region V1 has to equal to Vmaindc. Since

(36)

We have

which, after substituting for ga from Equation 31, and Zr from Equation 35, becomes

(37)

With Equation 35 and 37, once Ropt is determined based on load line theory, and r is chosen to get a specific back-off region, Zr and RL become readily available to keep the main amplifier in its maximum efficiency in the back-off region.

To calculate the overall efficiency, as well as power transfer linearity, it is necessary to find out the device DC currents Imaindc and Iauxdc, the auxiliary fundamental device voltage V2, as well as the auxiliary DC voltage Vauxdc.

Since the main device is in Class B mode, the ratio between the DC current and fundamental current is a constant,

which, after substituting for I1 from Equation 32, becomes

(38)

However for the auxiliary device, since the conduction angle changes as Vin changes in the upper region, the ratio between the DC current and the fundamental is a function of Vin,

where  is the conduction angle. Substituting for I2 from Equation 31,

(39)

The fundamental device voltage of the auxiliary amplifier is

V2 = -jZTI1 = - jZT · gmVin (40)

To avoid voltage clipping, Vauxdc has to be greater or equal than the magnitude of V2 at all input level. This would require

Vauxdc = max(ZT · gmVin) = ZT · gmVmax = RL · gaVmax (41)

It is now possible to calculate output fundamental power as well as the DC power. From

Equation 32 and 33,

From Equation 31 and 40,

Thus, the total fundamental output power is

(42)

which is clearly proportional to the input power, thus the power transfer is linear.

From Equation 36 and 38, the DC power dissipated by main amplifier is

From Equation 39 and 41, the DC power dissipated by the auxiliary amplifier is

Thus, the total DC power is

(43)

With Equation 42 and 43, the drain efficiency can be calculated by Pout/Pdc. Complicated algebra notwithstanding, it is just a function of Vin and r. Figure 50 plots the overall efficiency vs. input voltage level for three different values of r. It can be seen that the new configuration does manage to keep the efficiency high in the specified back-off region.

0.9 r=0.3 0.8 r=0.5 r=0.7 0.7

0.6

0.5

0.4

Overall efficiency 0.3

0.2

0.1

0 0 0.3Vmax 0.5Vmax 0.7Vmax Vmax Input voltage amplitude

Fig. 50. Overall efficiency of the new configuration.

There is one aspect of the new approach that has not been fully discussed.

That is the DC voltage requirement of the auxiliary amplifier. Substitute Equation 31 and

37 for ga and RL from Equation 41, after some rearrangement,

(44)

which is plotted in Figure 51. The minimum ratio is 2.2774, which happens at r = 0.69.

When r = 0.5, the ratio is 2.5575, meaning the DC drain voltage of the auxiliary device should be 2.5575 times higher than that of the main, if 6 dB back-off power region is desired.

Ratio of Auxiliary DC voltage over main DC voltage 2 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 r

Fig. 51. Required auxiliary DC drain voltage vs. r.

Simulation Results

A Doherty amplifier with 6 dB power back off is designed and simulated in

Microwave Office to test the proposed approach. The Curtice model is used for the main and auxiliary amplifiers. The simulated results of the Doherty amplifier are shown in

Figure 52, where we can see the distinctive 6 dB back-off high efficiency, and moderate linear power transfer. A Class B amplifier with the same transistor model is also designed

Fig. 52. Simulated results of the Doherty amplifier.

for comparison. Figure 53 compares the power added efficiency (PAE) performance versus the output power. Note that the upper limit of the Class B output power is set to its compression point. It is shown that although the Class B implementation has higher efficiency in the region close to its compression, the Doherty amplifier clearly has an advantage in the back-off region.

Conclusions

This chapter has explained theory and various realization problems of the

Doherty amplifier. A new configuration is presented to work with insufficient auxiliary current. It has the advantage of not requiring additional circuitry to boost the auxiliary current, in the mean time maintaining a high efficiency in the desired back-off region.

Fig. 53. Comparison of the Class B amplifier and the Doherty amplifier.

The drawback is that two different drain voltages are needed for the two devices, with the

Class C drain voltage more than twice higher than the Class B drain voltage.

CHAPTER VI

CONCLUSIONS AND FUTURE WORK

Conclusions

In this work, the transistor characteristic has been analyzed. Based that amplifier classes were introduced, and the load pull power amplifier design theory was discussed, as well as the amplifier nonlinearity and compression. The notion that maximum power transfer at the input side of the amplifier generates maximum gate voltage has been mathematically proved. A standard procedure has been developed to design power amplifiers at a single input power level with maximized efficiency. A design example was given to explain and verify the proposed standard procedure.

The Class F amplifier theory has been discussed in detail. A Class F amplifier at 2.5GHz has been designed with the GaN HEMT device CGH40010 provided by Cree,

Inc. The design has also been implemented. And optimization was performed to cater to the use of non ideal components in practice. Test results show that it delivers 12W output power with an efficiency of 75.75%, at the input power level of 25 dBm.

The Doherty amplifier design and practice as a way of boosting the back-off efficiency and in the mean time maintaining high linearity has been explained. Various realization issues were introduced. A new Doherty amplifier design approach has been proposed. This approach accepts the insufficient current of the auxiliary device rather

72 73 than changing it to meet the prescribed behavior, thus simplifying the circuit. Simulation results show that it gives comparable high efficiency without affecting linearity.

Future Work

When it comes to the realization of Doherty amplifiers, there are three main issues:

1. Insufficient auxiliary current.

2. Complex instead of real optimum load impedance.

3. Power leakage due to the parasitic components of the auxiliary device.

The first issue has been investigated and a solution proposed in this thesis work. The other two issues will be investigated as an extension to the present work.

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