<<

DESIGN AND OPTIMIZATION OF

FERROELECTRIC VARACTORS

Thesis

Submitted to

The School of Engineering of the

UNIVERSITY OF DAYTON

In Partial Fulfillment of the Requirements for

The Degree of

Master of Science in Electrical Engineering

By

Hailing Yue

Dayton, Ohio

December, 2012

DESIGN AND OPTIMIZATION OF BARIUM

FERROELECTRIC VARACTORS

Name: Yue, Hailing

APPROVED BY:

Guru Subramanyam, Ph.D. Monish Chatterjee, Ph.D. Advisory Committee Chairman Committee Member Professor and Department Chairperson Professor School of Engineering School of Engineering

Robert Penno, Ph.D. Committee Member Professor School of Engineering

John G. Weber, Ph.D. Tony E. Saliba, Ph.D. Associate Dean Dean, School of Engineering School of Engineering & Wilke Distinguished Professor

ii

ABSTRACT

DESIGN AND OPTIMIZATION OF BARIUM STRONTIUM TITANATE

FERROELECTRIC VARACTORS

Name: Yue, Hailing University of Dayton

Advisor: Dr. Guru Subramanyam

Barium-Strontium-Titanate(BST) based varactors are designed at specific capacitances under 0V dc bias on CMOS compatible low-resistivity substrate. The BST varactor device operation is based on the nonlinear tunability of BST thin film sandwiched between two metal layers in a revised conductor- backed coplanar waveguide(CBCPW) transmission line configuration. The varactor capacitance at 0V dc bias is determined by the overlap area between the CPW signal line in the top metal electrode and a tapered shunt line in the bottom electrode. Therefore a series of devices with fixed 0 V capacitances ranging were designed and fabricated based on changing their corresponding overlap areas according to the original parallel plate capacitance equation. A schematic model is also utilized to extract the designed and measured capacitances. The relationship between the sizes of overlap areas and the extracted capacitances from the electromagnetic and schematic models is demonstrated by a reasonable agreement with the experimental measurements from fabricated devices.

iii

DEDICATION

Dedicated to my husband, Jian Gao, my son, William Gao, and my parents, Han Yue and

Mei Xu.

iv

ACKNOWLEDGEMENTS

First and foremost I offer my sincerest gratitude to my advisor, Dr. Guru

Subramanyam, who has supported me throughout my graduate study with his patience and knowledge whilst allowing me the room to work in my own way. I attribute the level of my Master’s degree to his advice, insight, encouragement and effort.

In my daily work I have been blessed with a friendly and cheerful group of fellow colleagues. In the laboratory I have been aided for almost two years in running the Vector

Network Analyzer by Henry Zhang, a fine technician who always offers the detailed and accurate measurement data. Dustin Brown and Mark Patterson tutored me in how to design and optimize the devices and to analyze the data from them by integrating the microwave theory into the AWR simulating software. I was also educated in the use of

Pulsed Laser Deposition(PLD) system under their guidance. I also would like to thank

Dustin, Mark and other the working staff in AFRL who provided the supplies as well as the effort in fabricating the samples for my research work.

My committee members, Professor Monish Chatterjee and Professor Robert

Penno, lectured me on the theory of electromagnetics, transmission lines and waveguide, and digital communications, which stabilized my academic background and assisted me in exploring advanced agile microwave devices related to my research.

v

The Department of Electrical Engineering in University of Dayton has provided the support and equipment I have needed to produce and complete my thesis and funded my studies.

Finally, I thank my parents, parents-in-law, and my husband for supporting me all my studies at University of Dayton at all possible angles.

vi PREFACE

Silicon based transistors with fast transit times and high oscillation frequencies makes it possible to develop Monolithic Microwave ICs (MMICs) for frequencies up to

100GHz. Along with transistors, varactors are one of the most widely used components used in microwave technology for analog tuning purposes. Today no varactors with high enough Q-factor and tuneability are available for frequencies above

10GHz.The Q-factor of the semiconductor varactors decrease significantly with the increased frequency. This gap can be filled by the ferroelectric varactors. Considerable progress has been achieved in tunable permittivity ferroelectrics in developing ferroelectric varactors with performance better than semiconductor analogs at the high frequency range.

The work described in this thesis responds to the need of the MMIC compatible ferroelectric varactors with optimized performances (improved Q, high isolation, low insertion loss) at high frequencies.

vii TABLE OF CONTENTS

ABSTRACT ...... iii

DEDICATION ...... iv

ACKNOWLEDGEMENTS ...... v

PREFACE ...... vii

LIST OF ILLUSTRATIONS ...... xi

LIST OF TABLES ...... xvii

CHAPTER 1 INTRODUCTION ...... 1

1.1 Scope ...... 6

1.2 Outline ...... 7

CHAPTER 2 EXISTING VARACTOR TECHNOLOGIES ...... 8

2.1 RF-MEMS Varactors ...... 9

2.2 Semiconductor Varactor Diodes ...... 12

2.3 Ferroelectric Varactors ...... 16

2.4 Conclusion ...... 18

2.5 Ferroelectric Varactors in this Work ...... 18

CHAPTER 3 FERROELECTRIC MATERIALS ...... 19

3.1 Basics of Ferroelectric Material ...... 19

3.1.1 Applications in Ferroelectric (polar) Phase...... 21

3.1.2 Applications in Paraelectric (non-polar) Phase ...... 22

3.2 Figure of Merits ...... 23

viii

3.3 Barium Strontium Titanate ...... 24

CHAPTER 4 FABRICATION OF THIN FILM FERROELECTRIC VARACTORS ...... 27

4.1 Thin Film Processing Using Pulse Laser Deposition ...... 27

4.2 Thin Film Device Processing ...... 29

4.3 Electrodes Selection ...... 30

4.4 Electrode Patterning ...... 30

4.4.1 Lift-off Route ...... 30

4.4.2 Wet/dry Etching Route ...... 31

4.5 Substrate Micromachining and Passivation ...... 31

4.5.1 Common Substrates ...... 32

4.5.2 Low-resistivity Silicon as a Substrate ...... 33

4.5.3 Metal-semiconductor Ohmic Contacts Formation ...... 35

CHAPTER 5 CB-CPW BASED THIN FILM VARACTOR DESIGN ...... 40

5.1 Parallel Plate Varactor Design ...... 40

5.2 Coplanar Plate (CPW) Varactor Design ...... 41

5.3 Conductor Backed Coplanar Waveguide (CBCPW) Varactor Design ...... 43

5.4 Finalized Coplanar Waveguide (CPW) Parallel Plate Varactor Design ...... 44

5.5 Concept to Proof ...... 45

CHAPTER 6 EQUIVALENT SCHEMATIC MODEL ...... 48

6.1 Equivalent Circuit Parameters ...... 48

6.2 Extraction of Electrical Parameters from Simulation Data ...... 50

CHAPTER 7 DATA AND MEASUREMENTS ...... 52

7.1 Matching Extracted Capacitances from Designed and Measured Data ...... 52

7.2 Matching Other Extracted Electrical Parameters from Designed and Measured Data ...... 53

7.3 Tuning Capabilities Analysis ...... 53

CHAPTER 8 FUTURE WORK AND CONCLUSIONS ...... 57

ix 8.1 BST Thickness and Analysis ...... 58

8.2 Standard Device Variation ...... 66

8.3 Cascaded Standard Device ...... 67

BIBLIOGRAPHY ...... 70

APPENDIX ...... 77

x

LIST OF ILLUSTRATIONS

Figure 1 An authentic switchboard from 1924 and telephone cable being pulled into underground conduit - Lead covered cable, 1953[1]...... 1

Figure 2 Telephone pole line construction in New York, about 1903[1] ...... 1

Figure 3 Spectrum usage of modern wireless standards[2] ...... 2

Figure 4 (a) Multiple parallel transceivers for each frequency band, versus (b) one flexible transceiver for multiple frequencies.[3] ...... 4

Figure 5 A generic transceiver ...... 4

Figure 6 A single band RF frontend of a mobile phone ...... 5

Figure 7 A simplified example of two design options for a dual-band transmit[5] and receive filter in a mobile phone that supports 4 frequency bands[5]...... 6

Figure 8 Cross-section of a planar RF-MEMS electro-static switched ...... 9

Figure 9 A parallel plate Gap-tuned electrostatic RF MEMS varactor by Young and

Boser which has a Q of 62 at 1 GHz and tuning ratio ~1.25 from 2.11pF to 2.46Pf at

5V[44]...... 11

Figure 10 A three parallel plate RF MEMS varactor with a moveable dielectric in the center with a Q of 13.2 at 1GHz and tuning ratio of 1.25 by Dec and Suyama[45]...... 11

Figure 11 An area-tuned comb-structured MEMS varactor with a Q of 34 at 500MHz and tuning ratio of 2 by Yao et al[46]...... 11

xi

Figure 12 Cross-section of a Schottky varactor diode and the equivalent circuit model . 12

Figure 13 Cross-section of a ferroelectric varactor and the equivalent circuit model ...... 17

Figure 14 Parallel plate equivalent schematic model ...... 17

Figure 15 (a) the P (E) response of a linear capacitor, in (b) a nonlinear capacitor in the ferroelectric phase (with hysteresis) and in (c) a nonlinear capacitor in the paraelectric phase (without hysteresis)[22] ...... 20

Figure 16 BST in the ferroelectric phase structure[31] ...... 25

Figure 17 PLD simplified setup[35] ...... 28

Figure 18 DC resistivity versus real and imaginary part of permittivity[47] ...... 34

Figure 19 DC resistivity versus frequency[47] ...... 34

Figure 20 Cross sectional view of all layers ...... 38

Figure 21 Conventional Parallel-Plate Varactor and its equivalent schematic model ...... 40

Figure 22 Single layer Coplanar-Plate varactor structure ...... 41

Figure 23 Conductor-Backed Coplanar Plate Varactor and its equivalent schematic model...... 43

Figure 24 Finalized Coplanar Waveguide (CPW) Parallel Plate Varactor Design ...... 44

Figure 25 Finalized device dimensioning (µm) ...... 45

Figure 26 Schematic model used to extract electrical parameters ...... 49

Figure 27 Extracted parameters of 0.8pF device from EM structure model ...... 50

Figure 28 Extracted parameters of 2.4pF device from EM structure model ...... 51

Figure 29 Extracted parameters of 4.8pF device from EM structure model ...... 51

Figure 30 Designed capacitance versus measured capacitance extracted from schematic model...... 52

xii

Figure 31 0.8pF device measured from 0V to 5V ...... 54

Figure 32 Electrical parameters measured at 0V ...... 55

Figure 33 Electrical parameters measured at 5V ...... 55

Figure 34 Qint values at each voltage level at 1GHz ...... 56

Figure 35 Simulated S21 magnitudes for 0.1µm, 0.25µm, 0.75µm BST thicknesses (solid lines). The black dashed line represents the tunable S21 magnitude of the equivalent schematic model matched for 0.75µm BST thickness. In this case the effective varactor capacitance is 0.51pF for 0.75µm BST thickness...... 59

Figure 36 Simulated S21 phases for 0.1µm, 0.25µm, 0.75µm BST thicknesses (solid lines).

The black dashed line represents the tunable S21 phase of equivalent schematic model matched for 0.75µm BST thickness. In this case the effective varactor capacitance is

0.57pF for 0.75µm BST thickness...... 59

Figure 37 Simulated S11 magnitudes for 0.1µm, 0.25µm, 0.75µm BST thicknesses (solid lines). The black dashed line represents the tunable S11 magnitude of the equivalent schematic model matched for 0.75µm BST thickness. In this case the effective varactor capacitance is 0.57pF for 0.75µm BST thickness...... 60

Figure 38 Simulated S11 phases for 0.1µm, 0.25µm, 0.75µm BST thicknesses (solid lines).

The black dashed line represents the tunable S11 phase of equivalent schematic model matched for 0.75µm BST thickness. In this case the effective varactor capacitance is

0.69pF for 0.75µm BST thickness...... 60

Figure 39 Simulated S21 magnitudes for 0.1µm, 0.25µm, 0.75µm BST thicknesses (solid lines). The black dashed line represents the tunable S21 magnitude of the equivalent

xiii schematic model matched for 0.1µm BST thickness. In this case the effective varactor capacitance is 3.03pF for 0.1µm BST thickness...... 61

Figure 40 Simulated S21 phases for 0.1µm, 0.25µm, 0.75µm BST thicknesses (solid lines).

The black dashed line represents the tunable S21 phase of the equivalent schematic model matched for 0.1µm BST thickness. In this case the effective varactor capacitance is

3.03pF for 0.1µm BST thickness...... 61

Figure 41 Simulated S11 magnitudes for 0.1µm, 0.25µm, 0.75µm BST thicknesses (solid lines). The black dashed line represents the tunable S11 magnitude of the equivalent schematic model matched for 0.1µm BST thickness. In this case the effective varactor capacitance is 3.03pF for 0.1µm BST thickness, which corresponds with the results from matching S21 magnitudes...... 62

Figure 42 Simulated S11 phases for 0.1µm, 0.25µm, 0.75µm BST thicknesses (solid lines).

The black dashed line represents the tunable S11 phase of the equivalent schematic model matched for 0.1µm BST thickness. In this case the effective varactor capacitance is

3.96pF for 0.1µm BST thickness...... 62

Figure 43 S11 magnitudes for BST dielectric constants of 100, 300, 600 (solid lines). The black dashed line represents the tunable S11 magnitude of the equivalent schematic model matched for BST dielectric constant of 600. In this case the effective varactor capacitance is 1.26pF for BST dielectric constant of 600...... 63

Figure 44 S21 magnitudes for BST dielectric constants of 100, 300, 600 (solid lines). The black dashed line represents the tunable S21 magnitude of the equivalent schematic model matched for BST dielectric constant of 600. In this case the effective varactor capacitance is 1.11pF for BST dielectric constant of 600...... 64

xiv

Figure 45 S11 magnitudes for BST dielectric constants of 100, 300, 600 (solid lines). The black dashed line represents the tunable S11 magnitude of the equivalent schematic model matched for BST dielectric constant of 100. In this case the effective varactor capacitance is 0.18pF for BST dielectric constant of 100...... 64

Figure 46 S21 magnitudes for BST dielectric constants of 100, 300, 600 (solid lines). The black dashed line represents the tunable S11 magnitude of the equivalent schematic model matched for BST dielectric constant of 100. In this case the effective varactor capacitance is 0.12pF for BST dielectric constant of 100...... 65

Figure 47 Standard device variation ...... 66

Figure 48 Comparison between the variation and standard configuration ...... 67

Figure 49 Two-stage cascaded device ...... 68

Figure 50 Equivalent circuit of the cascaded device ...... 68

Figure 51 S-parameter magnitudes of two-stage cascaded device simulation and matching results ...... 69

Figure 52 S-parameter phases of two-stage cascaded device simulation and matching results ...... 69

Figure 53 Top view of 0.8pF device ...... 77

Figure 54 S-parameters matching at 0V for 0.8pF device ...... 78

Figure 55 S-parameters matching at 5V for 0.8pF device ...... 78

Figure 56 Top view of 1.2pF device ...... 79

Figure 57 S-parameters matching at 0V for 1.2pF device ...... 80

Figure 58 S-parameters matching at 5V for 1.2pF device ...... 80

Figure 59 Top view of 1.6 pF device ...... 81

xv

Figure 60 S-parameters matching at 0V for 1.6pF device ...... 82

Figure 61 S-parameters matching at 5V for 1.6pF device ...... 82

Figure 62 Top view of 2.0pF device ...... 83

Figure 63 S-parameters matching at 0V for 2.0pF device ...... 84

Figure 64 S-parameters matching at 5V for 2.0pF device ...... 84

Figure 65 Top view of 2.4pF device ...... 85

Figure 66 S-parameters matching at 0V for 2.4pF device ...... 86

Figure 67 S-parameters matching at 5V for 2.4pF device ...... 86

Figure 68 Top view of 3.2pF device ...... 87

Figure 69 S-parameters matching at 0V for 3.2pF device ...... 88

Figure 70 S-parameters matching at 5V for 3.2pF device ...... 88

Figure 71 Top view of 4.0pF device ...... 89

Figure 72 S-parameters matching at 0V for 4.0pF device ...... 90

Figure 73 S-parameters matching at 5V for 4.0pF device ...... 90

Figure 74 Top view of 4.8pF device ...... 91

Figure 75 S-parameters matching at 0V for 4.8pF device ...... 92

Figure 76 S-parameters matching at 5V for 4.8pF device ...... 92

xvi

LIST OF TABLES

Table 1 Characteristic of commercial varactor diodes[21] ...... 16

Table 2 The ferroelectric and paraelectric phase of a ferroelectric material...... 21

Table 3 Common substrate comparison[40] ...... 32

Table 4 Metals forming ohmic contact in a variety of [43] ...... 36

Table 5 Ohmic contact stack materials and properties[42] ...... 38

Table 6 Overlap areas calculated from designed capacitances ...... 47

Table 7 Comparison of capacitances between starting EM structure design, EM simulated design and measured design...... 53

Table 8 Extracted electrical parameters from EM structure at 0V ...... 53

Table 9 Extracted electrical parameters of 0.8pF device ...... 56

Table 10 Extracted Effective Capacitances from 0.1,0.25,0.75µm standard devices simulations. 63

Table 11 Extracted Effective Capacitances from dielectric constant of 100, 300, and 600 of standard devices simulations...... 65

Table 12 Extracted Electrical Parameters for 0.8pF device from 0V to 5V ...... 79

Table 13 Extracted Electrical Parameters for 1.2pF device from 0V to 5V ...... 81

Table 14 Extracted Electrical Parameters for 1.6pF device from 0V to 5V ...... 83

Table 15 Extracted Electrical Parameters for 2.0pF device from 0V to 5V ...... 85

Table 16 Extracted Electrical Parameters for 2.4pF device from 0V to 5V ...... 87

Table 17 Extracted Electrical Parameters for 3.2pF device from 0V to 5V ...... 89

xvii

Table 18 Extracted Electrical Parameters for 4.0pF device from 0V to 5V ...... 91

Table 19 Extracted Electrical Parameters for 4.8pF device from 0V to 5V ...... 93

xviii

CHAPTER 1

INTRODUCTION

Figure 1 An authentic switchboard from 1924 and telephone cable being pulled into underground conduit - Lead covered cable, 1953[1].

Figure 2 Telephone pole line construction in New York, about 1903[1]

1

The commercial long-distance communication began from the switchboard operating room where operators took shifts on the switchboards (Figure 1) with telephone cables (Figure 1) connected through the telephone poles (Figure 2) to other telephones.

The communication was established by manually switching telephone lines between users. Today we are at the so-called 3G generation wireless communication system where telephone technology has been revolutionized and is only one of the various options people choose to communicate. There are wireless standards for all kinds of applications

(long-range, short-range, voice, data, images, broadcast, etc.): GSM, GPS, WCDMA,

WiFi (IEEE 802.11a/b/g/n), Bluetooth, and Ultra Wideband (UWB) (Figure 3), which are distributed over a wide range of spectrum and set very different specifications[2]. Instead of having a separate receiver and handheld device for every standard, customers want to have all functionality integrated in one multi-standard device which can offer services which can roam and hand-over between services, e.g. between WLAN indoor and cellular when leaving the office building and simultaneously handle different services

(e.g. operate GSM and GPS at the same time)[3].

Figure 3 Spectrum usage of modern wireless standards[2]

2

This creates problems for the designers of the circuitry used to transmit and receive wireless signals, since each circuit is typically dedicated to operate at one single frequency band. Therefore, multiple circuits and antennas, each operating at a certain band, may be required in a multifunctional phone. This duplication of circuitry creates obvious cost and space issues.

In order to build such a multi-frequency transceiver, different solutions exist. The most straightforward way is to integrate several dedicated transceivers in parallel, one for each frequency (Figure 4(a))[4]. This may be power efficient since every frequency has an optimized transceiver (while the others are turned off), but it is a very expensive solution in terms of chip area and cost. Therefore, a transceiver with reconfigurable building blocks (Figure 4(b)) where circuits could be reconfigured in such a way as to operate across a wider frequency spectrum, is much more desirable. This is the concept of a “flexible” or “reconfigurable” transceiver, which has gained considerable interest recently[4].

3

Figure 4 (a) Multiple parallel transceivers for each frequency band, versus (b) one flexible transceiver for multiple frequencies.[3] One example is a dual-band transmit and receive band-pass filters in a mobile phone RF- frontend which consists of a number of electronic circuits. The RF-frontend is the last block of hardware that a signal will travel through the transceiver as shown in

Figure 5.

Figure 5 A generic transceiver A single band RF front-end as shown in Figure 6 consists of at least a power amplifier (PA), a low-noise amplifier (LNA), a transmit and a receive (duplex) filter, an antenna, and an impedance matching network. The antenna receives and transmits the RF

4 signal. The power amplifier amplifies the incoming signal for further processing.

Impedance matching network is designed to have an optimal power flow from the source to the load to avoid reflections. Preferably the load of the impedance matching network has to absorb all of the power transmitted from the source. The duplex band-pass filter contains a receive and a transmit band. This band-pass filter strongly suppresses out-of- band signals and only in a limited frequency band. A single band RF front-end is realized without any tunable components.

Figure 6 A single band RF frontend of a mobile phone For a dual-band mobile phone frontend which supports two frequency bands as shown in Figure 7[5]. The left design has four separate electronic circuits which support each a single frequency band in which the phone can either receive or transmit signals.

The design on the right has a single electronic tunable circuit which supports four or more frequency bands.

5

Figure 7 A simplified example of two design options for a dual-band transmit[5] and receive filter in a mobile phone that supports 4 frequency bands[5]. This approach would lower costs and lead to a smaller device. Circuit tuning can be done using tunable , also referred to as varactors. These are electrical components that change their intrinsic property (capacitance) with an application of an external control signal[6]. Varactors can be used to tune key properties of a circuit, such as center frequency, antenna impedance and channel bandwidth. These modifications allow the same circuit to be used with a number of different operational frequencies.

1.1 Scope

The main work of this thesis is dedicated to thin film ferroelectric MIM (metal- insulator-metal) tunable capacitors on CMOS compatible Si substrate. These devices are also called thin film ferroelectric varactors. The dielectric layer used in our device are

Barium-Strontium-Titanate- (BST). Our model was demonstrated to be able to be realized at a specified 0-V capacitance by using the basic parallel-plate capacitance equation to compute the corresponding overlapping areas.

6

The advantages of implementing the technology of these devices are a low cost, passive integration on cost-effective substrates, the relatively high permittivity of thin ferroelectric films (typically εr = 100–1000), and hence its miniaturization potential due to its high capacitance , continuous low-voltage tuning (typically < 40 Vdc ), and no moving parts like in MEMS[5].

1.1 Outline

This thesis starts with a literature study on relevant tunable capacitor technologies with a focus on the trade-off between tuning ratio and quality factor in Chapter 2. In

Chapter 3, a brief introduction is given on the basic properties of ferroelectrics with a focus on thin film Barium Strontium Titanate. In Chapter 4, the basic thin film processing technologies and fabrication process flow tailored for ferroelectric varactors and issues for low-resistivity Silicon as our substrate are illustrated. In Chapter 5 work is presented on our classic model designed with 0-V capacitances from 0.8pF to 4.8pF using the basic parallel plate capacitance equation. In Chapter 6 the equivalent circuit model is presented for extracting the electric parameters. In Chapter 7 the measurement results are analyzed in terms of its equivalent circuit parameters and the design concept is demonstrated on

CMOS low-resistivity Si substrate. This thesis ends with the conclusions and future work in Chapter 8.

7

CHAPTER 2

EXISTING VARACTOR TECHNOLOGIES

In this chapter three contemporary varactor technologies are introduced to show their potential for reconfigurable microwave applications: micro-machined capacitors

(RF-MEMS), semiconductor varactor diodes, and dielectric (ferroelectric) varactors. The concentration is on the trade-off between tuning ratio η=Cmax/Cmin and quality factor Q since it is the most-concerning issue for varactor technologies[7].

For each technology, parallel-plate configuration is employed. The capacitance is expressed by,

A C  0 r d 2-1

where the relative permittivity of the dielectric material between the two plates εr ,

-12 the permittivity of free space ε0=8.854×10 F/m, the overlap area between two metal plates A and the thickness of the dielectric material d.

The capacitance can be varied in,

8

1. RF-MEMS capacitors: through a change in the distance h between two

electrodes for planar capacitors or effective electrode overlapping area

A for comb-like structures, or by a movable dielectric[8,9];

2. Varactor diodes: through a change in the depletion layer width h in the

semiconductor;

3. Dielectric (ferroelectric) varactors: through a change in dielectric

constant εr of the dielectric material.

2.1 RF-MEMS Varactors

Figure 8 Cross-section of a planar RF-MEMS electro-static switched capacitor RF-MEMS varactors contain movable parts and can be configured as continuously tunable capacitors[8]. Such devices are usually large in physical sizes, compared to other devices discussed due to the actuator that moves the mechanical parts and low εr of the dielectric material. One way to realize a RF MEMS varactor is to use the electrostatic actuation method as shown in Figure 6, which is based on the mechanical stability of parallel-plate capacitors under an electrostatic force[9]. In the equivalent circuit model, Re is the resistance of the electrode and CMEMS is the MEMS capacitance.

Using the fact that the top plate can be moved to a gap height hmems =2g/3 before it collapses on the bottom plate. The tuning ratio can be written as,

9

eA + C C 2g / 3 f h = MEMS,MAX = 2-2 C eA MEMS,MIN + C g f

Where Cf if the fringing-field and parasitic capacitance to ground of the MEMS structure and input/output transmission line.

There is no fundamental difference in gap tuning, area tuning and movable dielectric tuning (Figure 9,10,11), since the dielectric layer (air or vacuum) is basically lossless and the electrode losses dominant performance of unpackaged planar RF-MEMS capacitively switched devices[8]. The dielectric losses for common substrates such as

SiO2 and Si3N4 are negligible (tanδ<0.003). Therefore the losses mainly come from the resistive electrodes, whereas in other discussed technologies the inherent losses often dominate over the electrode losses[8]. Parasitic effects, such as coupling to the substrate, can be reduced by isolating substrates[8]. For a best estimate these effects are neglected and the quality factor as a function of η, Q(η) can be expressed as,

-1 CMEMS,MAX Q = wReCMEMS,MAX = wReCMEMS,MIN = wReCMEMS,MINh 2-3 CMEMS,MIN

where ω is the angular frequency, Re is the resistance of the electrode, CMEMS,MAX and CMEMS,MIN are the maximum and minimum MEMS capacitance, and tuning ratio η=

CMEMS,MAX/ CMEMS,MIN.

The measurement data from literature shows that the RF-MEMS electrostatic capacitive switch exhibits a high Q across the tuning range at 2GHz[10-15]. The

10 actuation voltage, and operating frequency differs in some cases but in the range between

0.5-5GHz. The Q decreases with increasing η.

Figure 9 A parallel plate Gap-tuned electrostatic RF MEMS varactor by Young and Boser which has a Q of 62 at 1 GHz and tuning ratio ~1.25 from 2.11pF to 2.46Pf at 5V[44].

Figure 10 A three parallel plate RF MEMS varactor with a moveable dielectric in the center with a Q of 13.2 at 1GHz and tuning ratio of 1.25 by Dec and Suyama[45].

Figure 11 An area-tuned comb-structured MEMS varactor with a Q of 34 at 500MHz and tuning ratio of 2 by Yao et al[46]

11

2.2 Semiconductor Varactor Diodes

A varactor diode is a P-N junction diode that changes its capacitance through the variation of the diode depletion layer width with applied DC voltage superimposed on an

AC signal[16]. The diode is operated under reverse bias conditions and this gives rise to three regions. At either end of the diode are the P and N regions where current can be conducted. However around the junction is the depletion region where no current carriers are available. As a result, current can be carried in the P and N regions, but the depletion region is an insulator. In the case of the varactor diode, it is possible to increase and decrease the width of the depletion region by changing the level of the reverse bias. This has the effect analogous to changing the distance between the plates of the capacitor.

Figure 12 Cross-section of a Schottky varactor diode and the equivalent circuit model

As shown in Figure 7, the depletion layer hvc is controlled by the electric field and determines the capacitance value. The equivalent lumped-element model is shown on the right of Figure 7. The interconnect losses and electrode losses are given by Re, the depletion region capacitance of the p-n junction by Cvc and the resistance of the

12 semiconductor by Rsemi.

An increase in DC bias increases the depletion layer width, which (in case of a

Schottky varactor diode) starts from below the top electrode, reducing the capacitance[17,18]. Therefore the ratio between maximum and minimum depletion layer width also equals to the tuning ratio,

C h  max vc,max 2-4 Chmin,min vc

The minimum and maximum depletion layer widths and the breakdown voltages for Silicon can be calculated as follows[17].

The minimum depletion layer width

2 2kT h 0 s () 2-5 vcbi,min qN q

-19 where εs is the relative permittivity of the semiconductor, q=1.6×10 C, N is the

-3 - concentration in cm , the built-in voltage ϕbi=0.75, the Boltzman constant κ=1.38×10

23J/K, and the temperature T=300K.

The maximum depletion layer

20 s 2kT hVvc,max() bi  r ,max  qN q 2-6

where Vr,max is the maximum reverse breakdown voltage.

13

In case of uniformly doped Si,

2 Ec, vc , Si hE vcr ,max Si c vc 0 Si , , , Vr,max, Si  22qN 2-7

where εr,Si=11.7.

The maximum dielectric field at breakdown in Si can be described as

4 105 E  c,, vc Si 1 N 1 log10 16 310  2-8 for a uniform doping concentration. Generally, a heavily doped single-sided (hyper- abrupt) varactor diode with high carrier concentration is employed to support a large change in depletion-width leading to a higher Q and η. To achieve a wider voltage dynamic range or a higher breakdown voltage, low carrier concentration is required and thus a large-series resistance resulting in a low Q due to lowly doped semiconductor[9,19],

h vc,max  Q1  R Cx dx (())  0 r 2-9 semi vc,max   hvc,min hvc,min 

where Cvc,max is the maximum capacitance of the varactor diode at hvc,min, Rsemi is the resistance of the semiconductor which is obtained by integrating the resistivity ρ(x) from hvc,min to hvc, max. The electrode and interconnect loss Re is eliminated for best estimation.

The resistivity is expressed as,

14

1 ()x  2-10 N() x qn

where x is the depth of doping profile and μn is the mobility.

Using a power-law doping profile,

n x (xhx ) ( )~ n 2-11 vc,min  hvc,min which can be substitute into

n1 1  1 Qh 0 r  vc ,min  2-12 n 1

A uniform doping profile (abrupt) is obtained for n=0, and for a hyper-abrupt doping profile n>>0 which gives a larger tuning range than a uniform doping profile. By changing n, the Q(η) of different doping files can be studied[19].

In literature, the dependences of quality factor Q and the maximum tuning ratio η on the concentration N is studied for Si diodes[19]. The Q decreases with increasing η. Calculated Q(η) data for Si has a Q>50 at 5GHz[20,21]. Increasing the dopant concentration increases the quality factor, but lowers the breakdown voltage and tuning range. If the dopant concentration is very high, tunneling can occur at the junction, further reducing the tuning range. Typical values of tuning ratio, Q and breakdown voltage of commercial varactor diodes are listed in Table 1[21].

15

Device type CT(nF) Q η tuning ratio VR=4V,f=1MHz VR=4V,f=50MHz C4/C60,f=1MHz 1N 5139 6.8 350 2.9 1N 5140 10 300 3.0 1N 5141 12 300 3.0 1N 5142 15 250 3.0 1N 5143 18 250 3.0 1N 5144 22 200 3.4 1N 5145 27 200 3.4 1N 5146 33 200 3.4 1N 5147 39 200 3.4 1N 5148 47 200 3.4 Table 1 Characteristic of commercial varactor diodes[21] 2.3 Ferroelectric Varactors

Ferroelectrics are a class of with a spontaneous polarization which can be reversed in an electric field [22]. Unlike conventional dielectrics used in the integrated circuit technology, the relative permittivity εr of ferroelectric material can be changed when a DC voltage is applied to the capacitor. Therefore the tuning ratio η can be expressed by,

C   max r,max C  minr ,min 2-13

Ferroelectric varactors are smallest in physical sizes because of its high permittivity εr (100-1000) compared with the permittivity of semiconductor materials(~12).

16

Figure 13 Cross-section of a ferroelectric varactor and the equivalent circuit model Under a fixed dc bias, the varactor device can be modeled as a conventional parallel plate capacitor using lumped elements as shown in figure above, which includes the capacitance Cfe of the dielectric material between two parallel plate, a shunt resistor

Rp which represents the dielectric loss of the ferroelectric material, a series resistor Rs which represents the parasitic conductor and interconnect/electrode resistance, and an series inductor Ls which represents the parasitic conductor inductance.

Figure 14 Parallel plate equivalent schematic model

For the best estimation result, parasitic coupling Ls and dielectric loss Rp are ignored as shown in Figure 9, leading to the total impedance and the Q factor as,

1 QRC  s max 2-14

17

The mathematical approximation loosely follows the measurement due to the thin film processing variation and operating conditions, which is not discussed here[23,24].

Data on thin film ferroelectrics, using different deposition techniques, which have resulted in a high tunability and low loss for BaxSr1-xTiO3 at 1-10GHz, is given in [25] and [26]. The Q factor differs from 40-150 with maximum tuning ratio η between 1-4.

The Q decreases with increasing η.

2.4 Conclusion

The trade-off between losses and tuning ratio of three varactor technologies at microwave frequencies has been discussed. All technologies show an increased loss for higher tuning capability. The above discussion excludes the packaging and interconnects effects on the performance, which must be optimized for each of the technologies.

At present, for continuous, moderate tuning performance (η=1-3), highly-doped

GaAs varactor diodes could offer the best performance[27]. Ferroelectric varactors is the second alternative if small physical sizes and low-cost processing are mandatory.

2.5 Ferroelectric Varactors in this Work

Ferroelectric varactors in this work are based on Barium Strontium Titanate (BST) material used for RF applications which has the potential for reconfigurable continuous low-voltage tuning, high capacity density (εr=100-1000 for thin films), good temperature stability and no moving parts. Our devices were processed for small physical area consumption, passive integration on cost-effective (CMOS compatible ) substrates, fast fabrication processing, and simplified packaging.

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CHAPTER 3

FERROELECTRIC MATERIALS

This chapter summarizes the basic properties and characterization techniques of ferroelectric materials that are relevant to microwave tunable devices, as an introduction to the studies on BST-based varactors presented in the remainder of this thesis.

3.1 Basics of Ferroelectric Material

Ferroelectrics are a class of dielectrics with a spontaneous polarization, which can be reversed in an electric field [28]. In capacitors the dielectric layer is located in between two electrodes. Unlike conventional dielectrics used in the integrated circuit technology, the relative permittivity εr of ferroelectric material is a nonlinear function of the electric field E.

An applied voltage results in an orientation of the polarization in the electric field

E. The polarization P in ferroelectrics is remnant after the applied voltage is removed, is reversible, and saturates with increasing |E| [29]. In this case, a single material can exhibits two phase structures. The P(E) curves of a linear capacitor, and that of a nonlinear ferroelectric capacitor in the ferroelectric and the paraelectric phases are

19

CHAPTER 3. FERROELECTRIC MATERIALS AND PROPERTIES at a constant operation temperature T . The P(E)curves of a linear capacitor, and that of a nonlinear ferroelectric capacitor in the fer roel ectric and the parael ectric phases are depicted in Figure 3.1 with a brief summary of various properties of the two crystal phase structures given in Table 3.1. A single material can exhibits two crystal phase struct ures. In this disser tation the mater ialwill be named a ferroelectric capacitor, even if the temperature response is studied at in the paraelectric phase.

depicted in Figure 10.

PP P P EEE

Figure 15 (a) the P (E) response of a linear capacitor, in (b) a nonlinear capacitor in the ferroelectric phase (with hysteresis) and in (c) a nonlinear capacitor in the paraelectric phase (without hysteresis)[22] T < Tc T > Tc As shown(a) in Figur e 10 , a linear capacitor (b) has a constant ε r, since (c) the slope

remains unaltered. The εr of a nonlinear capacitor reduces with increasing |E| due to the F igur e 3.1 –In (a) the P (E )response of a linear capacitor, in (b) a nonlinear ca- pacitsaturationor in the off etherro polarization.electric pha Ats thee ( wphaseith htransitionysteres temperatureis) and in of(c a) nonlineara nonlin capacitorear cap acitor in the paralect ric phase (without hysteresis). the changes shape from tetragonal to cubic. The actual phase transition

point, which affects the εr, is modeled by the Curie-Weiss relation for small-signals at 0 Fer r oelect r ic phase Par aelect r ic phase V in the paraelectric phase TTc non-centrosymmetric centrosymmet ric

e.g., tet0CrCurieagonal crystal cubic cr ystal  r  3-1 hysterTTesis0 no hysteresis sp ontaneous polarization Ps no Ps −12 tywithpic εa0l l=y 8.85·10higher ε F/mr , η thean permittivityd tan δε ofty freepic space,ally h CigCurieh ε ther ,a Curiend l oconstant,wer η anandd Tt0an δε the Curie-Weiss phase transition temperature. T is equal to or a few degrees Celsius less Table 3.1 –The ferroelectric and paraele0ctric phase of aferroelectric material.

than the Tc [30].

A linear capacitor has a constant εr ,since the slope remains unaltered (see A brief summary of various properties of the two crystal phase structures is given Figure 3.1a and also a measurement example in Figure 5.14). The εr of a noinnl Tableinear 1[30ca].p acitor reduces with increasing |E | due to the saturation of

32

20

Phase Ferroelectric Paraelectric Temperature Range TTc Crystal structure Tetragonal Cubic Hysteresis(Pe) Yes No Relative Permittivity εr Higher Higher Tuning ratio η and loss tan δ Higher Lower Table 2 The ferroelectric and paraelectric phase of a ferroelectric material. 3.1.1 Applications in Ferroelectric (polar) Phase

Ferroelectrics may be in polar (ferroelectric) or non-polar (paraelectric) phases. In ferroelectric phase the polarization vs. electric field dependence is characterized by a hysteresis loop. The ferroelectric/dielectric properties of the ferroelectrics are associated with the electric dipoles in the crystal[30]. Memory cells are one of the main applications of ferroelectrics in polar (ferroelectric) phase, where the hysteresis loop with two equilibrium states of the spontaneous polarization is used to store binary information in non-volatile memory cells[30].

P.van der Sluis from Philips Research Laboratories has shown ferroelectric

Schottky diodes which show promising nonvolatile memory properties and the potential for integration into complementary metal-oxide-semiconductor CMOS circuits. It has been demonstrated that on-resistances reach down to 100 V, on/off ratios up to 107, switching voltages below 100 mV, operating temperatures up to 180 °C, and switching times below 50 ns[48].

Ferroelectrics in polar phase have not been considered for applications in tunable microwave devices because most ferroelectrics in polar phase are also piezoelectric whose transformation cause large losses at relatively low microwave frequencies

21

(<10GHz). Domain wall movements may also cause additional losses at low frequencies[30].

3.1.2 Applications in Paraelectric (non-polar) Phase

In the paraelectric (non-polar) phase the ferroelectric is characterized by a high dielectric permittivity which depends strongly on temperature, applied external electric field and mechanical stress[30]. The dependence of the permittivity on the applied electric field in paraelectric phase is the main character used in phase, frequency and amplitude agile microwave devices. A capacitor using a paraelectric phase ferroelectric as a dielectric, also called a varactor, is the basic building block of these systems.

Components like switches, phase shifters, tunable bandpass/bandstop filters etc. based on ferroelectric varactors are the main interest subject in this thesis and may have advantages over competing technologies in electric/microwave performance, reduced control power consumption, sizes and cost.

Courrèges etc. has demonstrated a three-pole tunable Ka-band coplanar filter that includes six high-Q BST ferroelectric capacitors. It tunes from 29 GHz up to 34 GHz

(17%) with low bias voltages ranging from 0 V to 30 V. The filter has fractional bandwidths of 9.5–12.2%. It has a good insertion loss for this category of Ka-band ferroelectric filters, which is between 6.9 dB (0 V) and 2.5 dB (30 V)[49].

Sazegar M. etc. validated two designs for compact continuously tunable phase shifters are presented employing integrated ferroelectric varactors based on screen- printed barium–strontium–titanate thick film in coplanar strip configuration. The

22 proposed designs have total lengths of 2.1 and 3.8 mm and provide a differential phase shift of more than 360 and a figure of merit of 51 /dB at 10 GHz[50].

Kim W. etc proposed a new integrated phased array antenna which integrates a ferroelectric coplanar waveguide phase shifter with the continuous transverse stub (CTS) array. The phase shifter employs a multi-dielectric substrate and includes a thin layer of between the signal conductors and the ferroelectric material to reduce the insertion losses and produce good impedance matching. An integrated two elements phased array antenna is developed and demonstrates linearly polarized radiation with ±

20° of beam scanning between the unbiased and biased states of the ferroelectric phase shifter[51].

3.2 Figure of Merits

In microwave applications low losses and low hysteretic effects are preferred.

Therefore, for RF applications thin film ferroelectric capacitors in the paraelectric phase are often desired, in addition to the low temperature dependence.

In the literature the performance of ferroelectric capacitors operating at microwave frequencies is assessed by several Figure of Merits. The most important performance parameters, during optimization, for ferroelectric BST varactors at RF are the total quality factor [31]

1 Q  3-2 tan with the total loss tangent tan δ. The tan δ in this thesis is defined as ratio of the imaginary part of the dielectric constant and the real part. The loss-tangent determined

23 the dielectric losses in the material. Detailed dielectric loss mechanisms of ferroelectric capacitors have been explained in [26,32]. The intrinsic quality factor is expressed as

1 Qint  3-3 tane with solely the dielectric loss tanδe. The output of a vector network analyzer measurement consists of S-parameters, which is converted to the quality factor (Q or Qint), since this is the most common parameter for circuit designers.

The tuning ratio is expressed as

 (0V )  C  r dc r, MAX  MAX 3-4 r()VC dc r, MIN MIN with the maximum capacitance Cmax at 0 Vdc and the minimum capacitance Cmin at the applied DC voltage (typically at the breakdown voltage), and the tunability

(0VV ) ( ) tunability  r dc r dc 3-5 r()V dc

In this thesis the equations of the Q, Qint, η and tunability are employed.

3.3 Barium Strontium Titanate

Over the years BaxSr1−xTi1+yO3+z (BST) has shown promising material properties with respect to tuning ratio, dielectric loss, good temperature behavior, size and integration. By mixing BaTiO3 with SrTiO3 a BST composition is created. Bulk single crystalline BaTiO3 has a T0 = 388 K [31], is in the ferroelectric phase at room

24 temperature, and has a high tuning ratio. Solid solutions of BaTiO3 and SrTiO3 shift the transition temperature close to room temperature to tailor the tuning ratio and loss.

Figure 16 BST in the ferroelectric phase structure[31] For barium strontium titanate (BST) in the ferroelectric phase as shown in Figure

11. The (Ti) is in the center of the octahedron, is shifted relative to the atoms in the ferroelectric phase and is relatively free to move in the octahedron [31].

When the Ti has moved from the center, a permanent dipole moment is formed, and the domains are formed in the ferroelectric [31].

An external electric field changes the direction of the polarity and more domains will be aligned towards the direction of the electric field [28]. The ferroelectric phase induces a hysteretic P(E) behavior which is dominated by the movement of domain walls

[29]. Hysteresis causes an increase in dielectric loss and a steeper P(E) slope compared to a capacitor in the paraelectric phase, which increases the εr(0Vdc) and Cmax. On the other hand, the paraelectric phase exhibits a centro-symmetric cubic crystal structure without any spontaneous polarization nor hysteresis, resulting in a lower dielectric loss and εr.

Experimental results have shown that in thin films the relative permittivity εr, the tuning ratio η, and the phase transition temperature T0 are lower, and the phase transition temperature region becomes wider compared to bulk [32,33,34]. A positive side-effect in thin films is that the εr is much less sensitive to temperature and these are

25 therefore preferred in RF applications. A lower maximum εr compared to bulk materials is not important at high frequencies where capacitance values are typically small. The tuning ratio of thin films can already be sufficient for low-voltage applications.

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CHAPTER 4

FABRICATION OF THIN FILM FERROELECTRIC VARACTORS

Synthesis of the ferroelectric film is the central process in the fabrication of tunable thin film ferroelectric devices. Various chemical and physical processes are widely used to produce quality thin films. Pulse Laser Deposition (PLD) is introduced and used since it has been demonstrated to produce high quality dielectric (ferroelectric) thin films[35].

In addition to the quality of the thin films, the performance of the devices strongly depend on the electrode/ferroelectric interface and misfit strains, which require a careful selection of the materials and structure of the electrodes when it comes to growth of ferroelectric films on based metal/electrode used in parallel-plate varactors. The processes used for patterning of the electrodes and dielectric (ferroelectric) films are also introduced in this section.

4.1 Thin Film Processing Using Pulse Laser Deposition

PLD belongs to a group called physical vapor deposition (PVD). PVD in general converts the material into vapor by physical means and the vapor is transported from its source to the substrate to form the thin film.

27

In case of PLD (Figure 12), the material, which is commonly called the target, is stricken into vapor by a focused pulsed laser beam (typically 30ns pulses with energy in the range 0.01-0.1J and at a repetition frequency of 10Hz). Both the focusing lens and the laser are external to the vacuum chamber. For high efficiency of radiation absorption by target material, lasers with radiation in UV spectrum, typically excimer (ArF,KrF,etc) are used. Above the threshold laser energy, a luminous plume of material is ejected normal to the target surface. The ejected material is deposited on a substrate that is suitably positioned and heated. The deposition process is controlled by rotating the target, varying the target-substrate distance and varying the lens-target distance. Typically turbo-pumps are used to evacuate the chamber to the high-vacuum (20-5 to 10-7 mbar). The turbo- pumps allow a rapid turnaround time and avoid hydrocarbon contamination in the chamber. A rotary pump is used in the second pumping port for pumping the deposition gas (oxygen for growth of ferroelectric films). The pressure in the chamber is controlled by a needle valve. The removable shutter is positioned across the substrate prior to the deposition to allow the target to be cleaned by ablating the surface with the laser beam without contamination of the substrate[35].

Figure 17 PLD simplified setup[35]

28

PLD allows easy reproduction of the target’s stoichiometry in the deposited film through the chamber. The desired stoichiometry of the film is achieved by using targets with same stoichiometry. The large-area pulsed-laser deposition system, suited in particular for depositing ferroelectric thin films of high quality on Si wafers of 3’’ and 4’’ in diameter[35].

For our BST thin films, the typical growth conditions are, annealing temperature

600ºC, laser energy at the target 250mJ/cm2 using KrF excimer laser (24nm wavelength)and oxygen ambient pressure 75mT[36].

4.2 Thin Film Device Processing

The ferroelectric capacitor structure, depending on device application, may be designed, fabricate and utilized as varactors. Passives such as CPW lines, inductors, and

IDCs etc., are fabricated together with bottom and/or top electrode metallization.

Ferroelectric varactors used in tunable microwave devices have two basic configurations: parallel-plate and coplanar-plate[37]. The configuration of the given capacitor defines a certain set of processing steps for device manufacturing. For our device, we have a combination of both configurations: the top electrode is patterned as CPW configuration and the bottom electrode is also used to form the overlap varactor area, while the ferroelectric film is sandwiched between the bottom and top electrodes.

In this part the basic fabrication process flows of our combined parallel-plate coplanar thin film ferroelectric devices in are considered including some aspects of processing the electrodes, substrate passivation and micromachining.

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4.3 Electrodes Selection

The main difference of manufacturing of the ferroelectric parallel-plate devices, in comparison with the standard IC capacitor technologies, is that the high temperature and oxygen environment (used for ferroelectric film growth) requires special bottom electrodes. Typically the bottom electrodes consist of refractory metals (Pt and/or Au) and contain additional adhesive and buffer layers[38].

4.4 Electrode Patterning

4.4.1 Lift-off Route

The patterning of the electrode can be realized using lift-off process or wet/dry etching using masks of photoresist. For the lift-off route the electrode is deposited on the mask of photoresist. The main condition for the proper lift-off process is the separation between the parts of the layer deposited on top of the substrate and top of the photoresist.

This requires formation of the undercuts at photoresist edges. The undercuts allows reproducible lift-off of the films with thickness even exceeding the resist thickness where the films are deposited by evaporation. The maximum thickness of the deposited layer is limited by the condition of separation. The condition of low microwave loss in metal requires thickness of 2-3 skin depth which for Au, for example, is approximately, 0.5μm at 20GHz. The standard image reversal (negative) photoresists allows lift-off of the films with thickness up to 5 μm. The layers intended for lift-off patterning are usually deposited using e-beam evaporation and the lift-off route is accomplished by soaking in the photoresist remover and results in patterned electrode[37].

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4.4.2 Wet/dry Etching Route

For wet/dry etching route, the electrode stack is deposited first on the ferroelectric film and patterned by wet/dry etch through a mask of photoresist (positive). The refractory based electrodes (Pt/Au) have proved difficult to etch chemically. In general, wet etching is used for patterning of Cu/Ti based electrode stacks. In addition, the chemical etchant should be selective and not dissolve the ferroelectric film or cause its degradation. The dry etching techniques (ion milling, reactive plasma etc) may be used for any material under careful etching rate calibration or use of stop end techniques to prevent damage of ferroelectric’s active area. The main issue for the wet/dry etching techniques is the under-etch which increases with layer thickness. The etching by ion milling results in either sloped sidewalls, or ear shaped edges from re-deposition of the material on the mask which is difficult to remove[37].

In general, the lift-off technique is considered to be gentler and non-destructive, in comparison with wet/dry etching, because it avoids exposing of the ferroelectric (active area) to aggressive chemicals, reactive plasma or ion radiation. For this reason the lift-off routs are more frequently used for patterning of the electrode stacks in coplanar-plate and the top electrodes in parallel-plate devices.

4.5 Substrate Micromachining and Passivation

Low resistivity Si is currently used as a substrate for development of microwave devices because of its low cost and integration capabilities. The main issue in using Si as a substrate is the surface conductivity induced by the positive charges (most probably oxygen vacancies) in the native and deposited SiO2 layers. This conductive surface layers cause extra microwave losses and parasitic coupling/field dependences, at present

31 micromachining and/or additional passivation layers are used to overcome these problems. Details of such techniques are discussed elsewhere[39].

4.5.1 Common Substrates

Substrate Permittivity Loss tangent Structure CTE.106 24@295K (18- LaAlO 3×10-4@300K Single Crystal 10@25C 3 35GHz) MgO 9.8 9×10-3@10GHz Single Crystal 8@100C 3.826@1MHz 1.5×[email protected] SiO Amorphous 0.55@20-320c 2 3.82@24GHz 3.3×10-4@24GHz

-4 Sapphire (Al2O3) 11.5@1MHz 8.6 @1.0MHz Single Crystal 5.3@25C Alumina Poly- 9.9@1MHz 10-4@10GHz 8.1@25-600c (Al2O3,99.6%) crystalline 11.7 (ρ >1.0Ohm Silicon 0 ωρ ε ε Single Crystal 2.6@25C cm) 0 0 L Table 3 Common substrate comparison[40] The BST thin films of same thickness and under the same processing conditions exhibit different properties using different substrate materials. The substrate materials as shown in Table 2[39] considered for our tunable ferroelectric devices are semiconductors

(Si) and single crystal dielectrics (Al2O3 Sapphire)[40,41]. Single crystal substrate

(sapphire) have been extensively considered for tunable ferroelectric devices, since they allow epitaxial growth of ferroelectric films such as BaxSr1-xTiO3. The good quality of the ferroelectric films is the main advantages of the single crystal substrate. However, they are not cost effective to use, partly due to the small sizes and cost of the available crystalline wafers. On the other hand, large scale applications of the ferroelectric components and devices depend on the integration possibilities of microwave ferroelectric components with semiconductors[40,41]. Considerable efforts have been concentrated on the development of CMOS based microwave applications, where

32 ferroelectric varactors are integrated with MOS transistors. Therefore Low resistivity Si is used as the substrate material for integration purposes.

4.5.2 Low-resistivity Silicon as a Substrate

The complex permittivity of semiconductor silicon depends on not only on frequency but also the conductivity (density of free charge carriers.) The real and imaginary part of the permittivity, as well as the loss tangent can be expressed as[37],

' Re{  }  L 1 '' Im{ } 00   1 tan  00   L

-12 where ε0=8.85×10 F/m is the dielectric constant of vacuum, εL=11.7 is the dielectric constant of silicon, ω=2πf is the angular frequency, ρ0 is the static (DC) resistivity

(1/ζ0)[37].

33

Figure 18 DC resistivity versus real and imaginary part of permittivity[47] As shown in Figure 13, the real part of the permittivity is independent of resistivity above 1 Ohm cm, including low-resistivity silicon (ρ<0.2 Ohm cm) and decreases with decreasing resistivity. The imaginary part of the permittivity is linearly inverse proportional to the resistivity.

Figure 19 DC resistivity versus frequency[47]

34

From frequency-resistivity chart shown in Figure 14, we can easily using low resistivity Silicon (ρ<0.2Ohm cm) as a lossy ground plane or lossy or good dielectric. In the dashed area, above scattering frequency and below about 100GHz low resistivity

Silicon maybe regarded as a lossy substrate with loss tangent inverse proportional to resistivity and frequency. Therefore the low resistivity Silicon is often used as a lossy ground plane in low frequency and digital ICs. At THz and infrared frequencies silicon is a good, transparent dielectric with extremely low losses regardless its resistivity.

4.5.3 Metal-semiconductor Ohmic Contacts Formation

Formation of good ohmic contact between metal and semiconductor is an extremely important process for fabricating high-performance semiconductor devices and integrated circuits. In general, an ohmic contact is referred to a non-injecting contact in which the current–voltage ( I–V ) relationship under both the reverse- and forward-bias conditions is linear and symmetrical[43]. However, in reality, a contact is considered ohmic if the voltage drop across the metal–semiconductor interface is small compared to the voltage drop across the bulk semiconductor. Table 4 gives a list of metals that are used in forming the ohmic contacts on a wide variety of semiconductors[43].

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Semiconductor Metals

Ge(N) Ag-Al-Sb,Al,Au,Bi,Ai-Au-P,Sb,Sn,Pb-Sn

Ge(P) Ag-Al,Au,Cu,Ga,Ga-In,In,Al-Pd,Ni,Pt,Sn

Si(N) Ag-Al,Al-Au,Au,Ni,Pt,Cu,In,Ge-Sn,Au-Sb,Al-Cu

Si(P) Ag,Al,Al-Au,Au,Ni,Pt,Sn,In,Pb,Ga,Ge,Al-Cu

GaAs(N) Au-Ge (88%,12%)-Ni,Ag-In (95%,5%)-Ge,Al-Cu

GaAs(P) Au-Zn (84%,16%),Ag-In-Zn,Ag-Zn

GaP(N) Ag-Te-Ni,Al,Au-Si,Au-Sn,In-Sn

GaP(P) Au-In,Au-Zn,Ga,In-Zn,Zn,Ag-Zn

Table 4 Metals forming ohmic contact in a variety of semiconductors[43]

Formation of ohmic contacts can be achieved in a number of ways (Table 5).

These include (1) choosing a metal with a lower work function than that of an n-type semiconductor (i.e.,φm<φs) such that the potential barrier between the metal and the semiconductor is small enough for the thermionic emission to tunnel through both directions of the metal–semiconductor contact; (2) deposition of a thin and heavily doped epilayer of the same doping type as the substrate to form an n++/n or p++/p high– low junction structure on the semiconductor surface. By using such a structure, the barrier width between the metal and the heavily doped n++ or p++ layer can be greatly reduced, and hence quantum-mechanical tunneling of charge carriers through such a thin barrier becomes possible. In this case, the barrier becomes essentially transparent to the charge carriers, and the specific contact resistance is usually very small. The heavily doped layer can be readily grown using alloying, thermal diffusion, ion implantation, or epitaxial growth with a suitable dopant impurity on the growth layer[42]. This approach of forming ohmic contact has been quite successful for both the silicon and GaAs IC

36 technologies. Finally, it should be pointed out that good ohmic contacts on p-type III-V compound semiconductors are in general more difficult to achieve than their n-type counterparts. This is due to the fact that a p-type III-V compound semiconductor surface is much easier to oxidize than an n-type surface during metallization or simple exposure to the air[42].

37

Material Ann. Temp. Doping Contact Resistance

(°C) (cm-3) (Ω•cm2)/( Ωmm)

Au 500 n 10-1 Ω•cm2

Al 500 n 10-1 Ω•cm2

Ti/Al 900 n 8Χ10-6 Ω•cm2

Ti/Al/Au 750 n 6 Χ 10-6 Ω•cm2

Ti/Al/Pt/Au 850 n 12 Χ 10-6 Ω•cm2

Table 5 Ohmic contact stack materials and properties[42]

Figure 20 Cross sectional view of all layers For the reported device (Figure 15), a Ti adhesion layer of 20nm was deposited on the low resistivity Si substrate followed by 800 nm of a combination of Ti/Al/Au/Pt ohmic contact stack patterned by standard positive photoresist liftoff photolithography in an e-beam evaporation system and 30 seconds of RTA at 1000 ºC which defines the

38 bottom electrode stack. A layer of BaxSr1-xTiO3 thin-film was deposited on the entire surface by PLD method using a KrF excimer laser (248nm wavelength) and annealed at

600ºC with oxygen pressure of 75mT for 30 minutes in the chamber[42]. The thickness of BST layer is about 400nm. After the BST deposition, the top metal layer of 800nm of

Au/Pt was patterned using the same liftoff technique and deposited using e-beam evaporation.

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CHAPTER 5

CB-CPW BASED THIN FILM VARACTOR DESIGN

Ferroelectric varactors used in tunable microwave devices have two basic designs: parallel-plate and coplanar-plate[37]. In both designs the tuning is achieved by applying

DC voltage to the plates which causes a reduction of permittivity of the ferroelectric film and hence the capacitance. The reported device design is a combination of both configurations. The conventional parallel plate varactor configuration will be reviewed at first. Then the coplanar component will be added into the parallel plate varactor design.

At last our finalized design will be illustrated based on the previous knowledge.

5.1 Parallel Plate Varactor Design

Figure 21 Conventional Parallel-Plate Varactor and its equivalent schematic model

40

In parallel-plate varactors the ferroelectric film is sandwiched between two electrodes as shown in Figure 16 who has a capacitance value,

C( VVDCr )( ADC0 ) d / 5-1

The maximum tuneability of the capacitance is expressed as,

CC(0) V ( ) ()V  dc 5-2 dc C(0)

For parallel-plate configuration, the thicker ferroelectric films require higher tuning DC voltages and better power handling capability. The thickness of the film can be tailored down to 3-5V tuning voltage in order to adapt to CMOS technology. Also the parallel-plate varactors can easily be cascaded and a common bottom electrode which may be used to apply the DC voltage[37].

5.2 Coplanar Plate (CPW) Varactor Design

Figure 22 Single layer Coplanar-Plate varactor structure In coplanar-plate (CPW) configuration (without a bottom metal electrode), the

Ground-Signal-Ground plates are on top of the ferroelectric films and the substrate is

41 directly placed under the ferroelectric films (Figure 17). In this case, the non-tunable partial capacitances associated with the fringing field in the substrate and the air, Csub and

Cair are in parallel with the capacitance associated with the ferroelectric film, resulting in

“screening” effects, capacitance tuneability smaller than the tuneability of the ferroelectric thin film.

CC(0) V f ( dc ) ()Vdc  5-3 CCfsub(0)  C air

Coplanar-plate varactors are relatively easier to fabricate since one mask is enough for the whole device. Moreover, by simply changing the slot width between the plates, one can always easily allow to trade low-tuning against higher Q-factor and vice versa. For small gap widths the required tuning voltage is small and the tuneablity is large since more DC and microwave fields are confined in the ferroelectric film (In contrast to parallel-plate varactors where the electric field is perpendicular to the film, the electric field in coplanar-plate varactors is predominantly in the plane of the film). In this case, the “screening” effects are also reduced but the Q-factor of the varactor is smaller too.

For a given ferroelectric film, the Q-factor can be increased by increasing the gap width, thus the tuning voltage and tuneablity are compromised[37].

42

5.3 Conductor Backed Coplanar Waveguide (CBCPW) Varactor Design

Figure 23 Conductor-Backed Coplanar Plate Varactor and its equivalent schematic model By inserting a bottom electrode under the ferroelectric thin film, a conductor- backed coplanar plate (CB-CPW) varactor is created. In this case, the effective varactor capacitance is determined by the overlapping area between the CPW signal line in the top electrode and the bottom ground pad Cs in series with the two Ground-Ground capacitances Cg between top and bottom electrode as shown in Figure 18.

43

5.4 Finalized Coplanar Waveguide (CPW) Parallel Plate Varactor Design

Figure 24 Finalized Coplanar Waveguide (CPW) Parallel Plate Varactor Design For microwave applications, a capacitance on the order of several pF is enough.

Because of the high capacitance density of the ferroelectric material, the structure in

Figure 18 needs to be modified for a much smaller overlapping area. As shown in Figure

19, instead of a large single ground plane, the bottom electrode is modified to have identical ground plates as the top electrode, and a tapered shunt line shorting the two ground plates, therefore a much smaller effective overlapping area is yielded: between the center CPW signal line in the top electrode and a tapered shunt line in the bottom electrode. Since the two Ground-Ground capacitances Cg are too large compared with the

Signal-Ground capacitance Cs and the three capacitances Cg, Cs, and Cg are in series, only the Signal-Ground capacitance Cs takes effect and is considered to be the effective varactor capacitance. The dimension of our standard device with an overlapping area of

5µm by 5µm from top view is given in Figure 20.

44

Figure 25 Finalized device dimensioning (µm) As shown in Figure 20, the overall device area is 450µm by 500µm. The CPW

Ground-Signal-Ground dimensions in top metallic layer are 150µm/50µm/150µm. The spacing between center signal line and ground conductors is 50µm. The bottom electrode consists of two ground conductors identical to the CPW ground lines in top electrode, and a tapered shunt line shorting two ground conductors[43].

5.5 Concept to Proof

From Equation 5.1, the varactor effective capacitance Cs can be calculated by substituting the effective overlapping area A (5µm by 5µm from Figure 20), the thickness d and the relative permittivity εr of the ferroelectric thin film into the equation. The thickness of the thin film d is known (usually taken as 0.25-0.4µm for best film quality).

Past work has shown a relative permittivity of 500 of BST thin film under a 0V DC bias[43]. Therefore we can easily manipulate the effective capacitances by simply

45 changing overlapping area A using Equation 5.1. If we have targeted effective capacitance values, the corresponding devices can easily be designed with their calculated overlapping areas!

CAtarget0 d(0)(0)  /r Cd(0) target 5-4 Adesign 0 r (0)

To prove this concept, eight varactor overlapping areas for the designed capacitances from 0.8pF to 4.8pF were calculated in Table 3. For example the device with effective capacitance 0.8pF will be designed with an overlap area of 112.9 µm2 and be named as Device 1.

46

Device Number Capacitance Effective overlap Area (pF) (µm2) 1 0.8 60.2 2 1.2 90.4 3 1.6 120.5 4 2.0 150.6 5 2.4 180.7 6 3.2 240.9 7 4.0 301.2 8 4.8 361.4 Table 6 Overlap areas calculated from designed capacitances The Electromagnetic (EM) Model of each device were simulated and a schematic model was utilized to extract and verify the designed capacitance in the next chapters.

After the devices are fabricated, the same schematic model is utilized to extract the measured effective capacitances. The concept of designing devices at specific effective capacitances by simply changing their effective overlap areas is demonstrated by a reasonable agreement of the extracted effective capacitances from both EM and schematic models with the experimental measurements.

47

CHAPTER 6

EQUIVALENT SCHEMATIC MODEL

AWR Microwave Office 2010 software is used to construct the EM structures and the schematic model, and then computes the scattering parameters over the predefined frequency range. The experimental measurement of the fabricated device can also be imported to this environment. The EM structure predicts the ideal performance of the designed physical dimensions and geometries layer by layer (Figure 21). The schematic model using lumped elements, has been created elsewhere, is used to extract the electrical parameters by matching the EM simulation or experimental measurements with the values of each electrical component [43].

6.1 Equivalent Circuit Parameters

As shown in Figure 21, the signal line connects the input to output, represented by two CPW transmission lines in between, with the varactor shunted to the ground. The capacitor C(V) models the effective capacitance of the varactor calculated using Equation

5.1. The shunt resistor Rd(V) is in parallel with C to model the leakage conductance of the varactor,

Rd ( V ) 1/(2 fC ( V )tan ) 6-1

48

Where f is the operating frequency and tanδ is the loss tangent of the BST thin film.

The series resistor Rs and the inductance of the line Ls model the parasitic effects and

can be calculated as,

Rlwts  / () 6-2

Where ζ is the conductivity of the bottom metal electrode, w is the width of the conductor, l is the length of the line shunting to ground, and t is the thickness of the conductor.

Lsg ( Zfl0 / (2 )sin(2  / )) 6-3

Where Z0 is the characteristic impedance of the CPW transmission line, f is the operating frequency, λg is the guidewavelength[43].

Figure 26 Schematic model used to extract electrical parameters

49

6.2 Extraction of Electrical Parameters from Simulation Data

For the EM simulated results of the device with designed capacitance of 0.8pF, 2.4pF, and 4.8pF (corresponding to overlap areas of 112.9 ,169.4, and 225.9 µm2 in Table 3) shown in Figure 22-24, the matched capacitance of 0.78 pF, 2.875 pF, and 5.175pF are obtained after tuning each electrical component to match the simulated results. Likewise, the electrical parameters of the experimental measurements of the fabricated devices can also be extracted from this schematic model and will be shown in the chapter.

S21

S11

Figure 27 Extracted parameters of 0.8pF device from EM structure model

50

S21

S11

Figure 28 Extracted parameters of 2.4pF device from EM structure model

S21

S11

Figure 29 Extracted parameters of 4.8pF device from EM structure model

51

CHAPTER 7

DATA AND MEASUREMENTS

7.1 Matching Extracted Capacitances from Designed and Measured Data

The extracted capacitances of the designed and measured devices are shown in

Figure 25 and compared with desired capacitances in Table 4. A close match is observed for smaller overlap areas (device 1 and 2). As the overlap area increases, the deviations between designed and measured capacitances become more significant and measured capacitances are lower than designed capacitances.

6 Measured Capacitance 5 Designed Capacitance

4

3 (pF)

Capacitance 2

1

0 1 2 3 4 5 6 7 8 Device Number

Figure 30 Designed capacitance versus measured capacitance extracted from schematic model

52

|C Measured- CEM| Device No. CDesign CEM CMeasured CEM (pF) (pF) (pF)

1 0.8 0.78 0.85 0.09 2 1.2 1.14 1.2 0.05 3 1.6 1.68 1.45 0.14 4 2 2.212 1.85 0.17 5 2.4 2.95 2.125 0.28 6 3.2 3.4 3.748 0.10 7 4 4.38 3.648 0.17 8 4.8 5.286 4 0.10 Table 7 Comparison of capacitances between starting EM structure design, EM simulated design and measured design.

7.2 Matching Other Extracted Electrical Parameters from Designed and Measured Data

The other electrical parameters of eight devices at 0V bias are tabulated in Table 5.

As the overlap area A increases, the series resistance Rs decreases while changes in Ls and Rd are insignificant.

CDesign CMeasured Ls Rs Rp

(pF) (pF) (nH) (Ω) (Ω) 0.8 0.85 0.011 1 743 1.2 1.2 0.011 3.25 823 1.6 1.45 0.011 3.25 823 2 1.85 0.0215 1.85 823 2.4 2.125 0.006 1.85 823 3.2 3.748 0.006 1.85 823 4 3.648 0.006 1.85 823 4.8 4 0.006 0.65 500 Table 8 Extracted electrical parameters from EM structure at 0V 7.3 Tuning Capabilities Analysis

In order to explore the tuning behavior, each of the devices was measured from 0GHz to 15GHz by applying a dc bias. Figure 26 shows the results of 0.8pF device as the dc

53 bias increased from 0V to 5V. The isolation is about 8dB (Figure 27) and the insertion loss is below 5dB up to 15GHz (Figure 28). The extracted electrical parameters for 0.8pF device at each voltage level are summarized in Table 6. The capacitance in this case is tunable by about a factor of 2 and the changes in other components’ values turn to be insignificant. In addition, as the dc bias increases, the quality factors calculated at 1GHz also increases (Figure 29).

S21

S11

Figure 31 0.8pF device measured from 0V to 5V

54

S21

S11

Figure 32 Electrical parameters measured at 0V

S21

S11

Figure 33 Electrical parameters measured at 5V

55

Voltage C L Rs Rp (V) (pF) (nH) (Ω) (Ω) 0 0.85 0.011 1 743 1 0.8 0.011 1 743 2 0.75 0.011 1 743 3 0.7 0.011 1 743 4 0.6 0.011 1 743 5 0.5 0.011 1 743 Table 9 Extracted electrical parameters of 0.8pF device

The matching curves and extracted electrical parameters for other devices are shown in the Appendix.

350.00

300.00 Qs at 0V 250.00 Qs at 1V 200.00 Qs at 2V

Qs 150.00 Qs at 3V 100.00 Qs at 4V Qs at 5V 50.00

0.00 0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 4.8 Device Capacitance(pF)

Figure 34 Qint values at each voltage level at 1GHz

56

CHAPTER 8

FUTURE WORK AND CONCLUSIONS

Eight BST varactors were designed with capacitances from 0.8pF to 4.8pF by using Equation 5.1 to determine the effective varactor areas. By using a schematic model to extract the electrical parameters, the designed capacitances were found to have a reasonable agreement with the measured capacitances for 0.4µm BST thicknesses and 0V

BST relativepermittivity of 500. This result gives a tool for a reasonable estimation on future designs and analysis. The dielectric tunability of the 0.8pF device is about 2:1.

This is also a first demonstration of our devices which can be integrated on a CMOS compatible low-resistivity Si substrate by applying an ohmic contact stack as the bottom metal layer.

However, these results can be optimized by exploring the optimal BST thickness, relative permittivity, electrodes, and patterning in order to reduce the parasitic effects therefore the best tunability and quality factor could be achieved. The rest of the section shows the simulations for future directions.

Section 8.1 gives the comparisons on different BST thickness and relative permittivities. Section 8.2 shows the simulation results of variations from the standard

57 devices in order to reduce the series parasitic resistance, which directs to the potential future explorations in optimizing our standard version and other advanced microwave devices. Section 8.3 presents a cascaded version of our standard device for tunable notch filter applications.

8.1 BST Thickness and Relative Permittivity Analysis

As stated in Chapter VI, our calculations are based on a BST thickness of 0.4µm and εr of 600. It would be interesting to know how the performance of our device would change with varying BST thicknesses and dielectric constants.

Using our standard device configuration (5µm by 5µm overlapping area), the magnitudes and angles of S-parameters for BST thickness of 0.1, 0.25, and 0.75µm are compared in Figure 30-37, and the magnitudes of S-parameters for BST dielectric constants of 100, 300 and 600 are compared in Figure 38-41.

58

Figure 35 Simulated S21 magnitudes for 0.1µm, 0.25µm, 0.75µm BST thicknesses (solid lines). The black dashed line represents the tunable S21 magnitude of the equivalent schematic model matched for 0.75µm BST thickness. In this case the effective varactor capacitance is 0.51pF for 0.75µm BST thickness.

Figure 36 Simulated S21 phases for 0.1µm, 0.25µm, 0.75µm BST thicknesses (solid lines). The black dashed line represents the tunable S21 phase of equivalent schematic model matched for 0.75µm BST thickness. In this case the effective varactor capacitance is 0.57pF for 0.75µm BST thickness.

59

Figure 37 Simulated S11 magnitudes for 0.1µm, 0.25µm, 0.75µm BST thicknesses (solid lines). The black dashed line represents the tunable S11 magnitude of the equivalent schematic model matched for 0.75µm BST thickness. In this case the effective varactor capacitance is 0.57pF for 0.75µm BST thickness.

Figure 38 Simulated S11 phases for 0.1µm, 0.25µm, 0.75µm BST thicknesses (solid lines). The black dashed line represents the tunable S11 phase of equivalent schematic model matched for 0.75µm BST thickness. In this case the effective varactor capacitance is 0.69pF for 0.75µm BST thickness.

60

Figure 39 Simulated S21 magnitudes for 0.1µm, 0.25µm, 0.75µm BST thicknesses (solid lines). The black dashed line represents the tunable S21 magnitude of the equivalent schematic model matched for 0.1µm BST thickness. In this case the effective varactor capacitance is 3.03pF for 0.1µm BST thickness.

Figure 40 Simulated S21 phases for 0.1µm, 0.25µm, 0.75µm BST thicknesses (solid lines). The black dashed line represents the tunable S21 phase of the equivalent schematic model matched for 0.1µm BST thickness. In this case the effective varactor capacitance is 3.03pF for 0.1µm BST thickness.

61

Figure 41 Simulated S11 magnitudes for 0.1µm, 0.25µm, 0.75µm BST thicknesses (solid lines). The black dashed line represents the tunable S11 magnitude of the equivalent schematic model matched for 0.1µm BST thickness. In this case the effective varactor capacitance is 3.03pF for 0.1µm BST thickness, which corresponds with the results from matching S21 magnitudes.

Figure 42 Simulated S11 phases for 0.1µm, 0.25µm, 0.75µm BST thicknesses (solid lines). The black dashed line represents the tunable S11 phase of the equivalent schematic model matched for 0.1µm BST thickness. In this case the effective varactor capacitance is 3.96pF for 0.1µm BST thickness.

62

BST Thickness(µm) 0.1 0.25 0.75 Extracted C from S21 magnitude(pF) 0.51 1.2 3.03 Extracted C from S21 phase(pF) 0.57 1.29 3.03 Extracted C from S11 magnitude(pF) 0.57 1.29 3.03 Extracted C from S11 phase(pF) 0.69 1.62 3.96 Table 10 Extracted Effective Capacitances from 0.1,0.25,0.75µm standard devices simulations. As shown in Table 7, each column gives the extracted capacitances for the same thickness from different matching parameters (S21 and S11 magnitudes and phases).

Generally for our simulator S21 magnitudes and phases gives identical results and S11 phases deviates more.

Figure 43 S11 magnitudes for BST dielectric constants of 100, 300, 600 (solid lines). The black dashed line represents the tunable S11 magnitude of the equivalent schematic model matched for BST dielectric constant of 600. In this case the effective varactor capacitance is 1.26pF for BST dielectric constant of 600.

63

Figure 44 S21 magnitudes for BST dielectric constants of 100, 300, 600 (solid lines). The black dashed line represents the tunable S21 magnitude of the equivalent schematic model matched for BST dielectric constant of 600. In this case the effective varactor capacitance is 1.11pF for BST dielectric constant of 600.

Figure 45 S11 magnitudes for BST dielectric constants of 100, 300, 600 (solid lines). The black dashed line represents the tunable S11 magnitude of the equivalent schematic model matched for BST dielectric constant of 100. In this case the effective varactor capacitance is 0.18pF for BST dielectric constant of 100.

64

Figure 46 S21 magnitudes for BST dielectric constants of 100, 300, 600 (solid lines). The black dashed line represents the tunable S11 magnitude of the equivalent schematic model matched for BST dielectric constant of 100. In this case the effective varactor capacitance is 0.12pF for BST dielectric constant of 100.

BST εr 100 300 600 Extracted C from S21 magnitude (pF) 0.12 0.54 1.11 Extracted C from S11 magnitude (pF) 0.18 0.64 1.26 Table 11 Extracted Effective Capacitances from dielectric constant of 100, 300, and 600 of standard devices simulations. As shown in Table 8, each column gives the extracted capacitances for the same thickness from different matching parameters (S21 and S11 magnitudes and phases).

Generally it is impossible to perfectly match both S21 and S11.

65

8.2 Standard Device Variation

Figure 47 Standard device variation The series parasitic effect can possibly be reduced by using the configuration in Figure 42. The simulator cannot predict the difference between this variation and the standard configuration as shown in Figure 43.

66

Figure 48 Comparison between the variation and standard configuration 8.3 Cascaded Standard Device

A notch filter can be easily achieved by cascading two or more standard devices. As shown in Figure 44, two identical standard devices are cascaded in series. Using the schematics shown in Figure 45, the extracted electrical parameters and simulated results are shown in Figure

46 and Figure 47.

67

Figure 49 Two-stage cascaded device

Figure 50 Equivalent circuit of the cascaded device

68

Figure 51 S-parameter magnitudes of two-stage cascaded device simulation and matching results

Figure 52 S-parameter phases of two-stage cascaded device simulation and matching results

69

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76

APPENDIX

Figure 53 Top view of 0.8pF device

77

Figure 54 S-parameters matching at 0V for 0.8pF device

Figure 55 S-parameters matching at 5V for 0.8pF device

78

Voltage C L Rs Rp Qs at 1GHz Qs at 10GHz (V) (pF) (nH) (Ohmn) (Ohmn) 0 0.85 0.011 1 743 187.34 18.73 1 0.8 0.011 1 743 199.04 19.90 2 0.75 0.011 1 743 212.31 21.23 3 0.7 0.011 1 743 227.48 22.75 4 0.6 0.011 1 743 265.39 26.54 5 0.5 0.011 1 743 318.47 31.85 Table 12 Extracted Electrical Parameters for 0.8pF device from 0V to 5V

Figure 56 Top view of 1.2pF device

79

Figure 57 S-parameters matching at 0V for 1.2pF device

Figure 58 S-parameters matching at 5V for 1.2pF device

80

Voltage C L Rs Rp Qs at 1GHz Qs at 10GHz (V) (pF) (nH) (Ohmn) (Ohmn) 0 1.2 0.011 3.25 823 40.83 4.08 1 1.1 0.011 3.25 823 44.54 4.45 2 1.05 0.011 3.25 823 46.66 4.67 3 1 0.011 3.25 823 49.00 4.90 4 0.95 0.011 3.25 823 51.57 5.16 5 0.7 0.011 3.25 823 69.99 7.00 Table 13 Extracted Electrical Parameters for 1.2pF device from 0V to 5V

Figure 59 Top view of 1.6 pF device

81

Figure 60 S-parameters matching at 0V for 1.6pF device

Figure 61 S-parameters matching at 5V for 1.6pF device

82

Voltage C L Rs Rp Qs at 1GHz Qs at 10GHz (V) (pF) (nH) (Ohmn) (Ohmn) 0 1.45 0.011 3.25 823 33.79 3.38 1 1.4 0.011 3.25 823 35.00 3.50 2 1.35 0.011 3.25 823 36.29 3.63 3 1.2 0.011 3.25 823 40.83 4.08 4 1.05 0.011 3.25 823 46.66 4.67 5 0.85 0.011 3.25 823 57.64 5.76 Table 14 Extracted Electrical Parameters for 1.6pF device from 0V to 5V

Figure 62 Top view of 2.0pF device

83

Figure 63 S-parameters matching at 0V for 2.0pF device

Figure 64 S-parameters matching at 5V for 2.0pF device

84

Voltage C L Rs Rp Qs at 1GHz Qs at 10GHz (V) (pF) (nH) (Ohmn) (Ohmn) 0 1.85 0.0215 1.85 823 46.53 4.65 1 1.8 0.0215 1.85 823 47.82 4.78 2 1.7 0.0215 1.85 823 50.63 5.06 3 1.65 0.0215 1.85 823 52.17 5.22 4 1.5 0.0215 1.85 823 57.38 5.74 5 1.45 0.0215 1.85 823 59.36 5.94 Table 15 Extracted Electrical Parameters for 2.0pF device from 0V to 5V

Figure 65 Top view of 2.4pF device

85

Figure 66 S-parameters matching at 0V for 2.4pF device

Figure 67 S-parameters matching at 5V for 2.4pF device

86

Voltage C L Rs Rp Qs at 1GHz Qs at 10GHz (V) (pF) (nH) (Ohmn) (Ohmn) 0 2.125 0.006 1.85 823 40.51 4.05 1 2.053 0.006 1.85 823 41.93 4.19 2 1.972 0.006 1.85 823 43.65 4.36 3 1.927 0.006 1.85 823 44.67 4.47 4 1.8 0.006 1.85 823 47.82 4.78 5 1.648 0.006 1.85 823 52.23 5.22 Table 16 Extracted Electrical Parameters for 2.4pF device from 0V to 5V

Figure 68 Top view of 3.2pF device

87

Figure 69 S-parameters matching at 0V for 3.2pF device

Figure 70 S-parameters matching at 5V for 3.2pF device

88

Voltage C L Rs Rp Qs at 1GHz Qs at 10GHz (V) (pF) (nH) (Ohmn) (Ohmn) 0 3.748 0.006 1.85 823 22.97 2.30 1 3.668 0.006 1.85 823 23.47 2.35 2 3.568 0.006 1.85 823 24.12 2.41 3 3.448 0.006 1.85 823 24.96 2.50 4 3.248 0.006 1.85 823 26.50 2.65 5 2.868 0.006 1.85 823 30.01 3.00 Table 17 Extracted Electrical Parameters for 3.2pF device from 0V to 5V

Figure 71 Top view of 4.0pF device

89

Figure 72 S-parameters matching at 0V for 4.0pF device

Figure 73 S-parameters matching at 5V for 4.0pF device

90

Voltage C L Rs Rp Qs at 1GHz Qs at 10GHz (V) (pF) (nH) (Ohmn) (Ohmn) 0 3.648 0.006 1.85 823 23.59 2.36 1 3.418 0.006 1.85 823 25.18 2.52 2 3.068 0.006 1.85 823 28.06 2.81 3 2.968 0.006 1.85 823 29.00 2.90 4 2.768 0.006 1.85 823 31.10 3.11 5 2.568 0.006 1.85 823 33.52 3.35 Table 18 Extracted Electrical Parameters for 4.0pF device from 0V to 5V

Figure 74 Top view of 4.8pF device

91

Figure 75 S-parameters matching at 0V for 4.8pF device

Figure 76 S-parameters matching at 5V for 4.8pF device

92

Voltage C L Rs Rp Qs at 1GHz Qs at 10GHz (V) (pF) (nH) (Ohmn) (Ohmn)

0 4 0.006 0.65 500 61.24 6.12 1 3.5 0.006 0.65 500 69.99 7.00 2 3.42 0.006 0.65 500 71.63 7.16 3 3.32 0.006 0.65 500 73.79 7.38 4 3.27 0.006 0.65 500 74.92 7.49 5 3.12 0.006 0.65 500 78.52 7.85 Table 19 Extracted Electrical Parameters for 4.8pF device from 0V to 5V

93