DOCSLIB.ORG

Ultrasparc Iii User's Manual

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text

Load more

UltraSPARC ™-IIi User’s Manual Sun Microelectronics 901 San Antonio Road Palo Alto, CA 94303 USA 800 681-8845 http://www.sun.com/microelectronics Part No.: 805-0087-01 Copyright © 1997 Sun Microsystems, Inc. All Rights reserved. THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED"AS IS" WITHOUT ANY EXPRESS REPRESENTATIONS OR WARRANTIES. IN ADDITION, SUN MICROSYSTEMS, INC. DISCLAIMS ALL IMPLIED REPRESENTATIONS AND WARRANTIES, INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. This document contains proprietary information of Sun Microsystems, Inc. or under license from third parties. No part of this document may be reproduced in any form or by any means or transferred to any third party without the prior written consent of Sun Microsystems, Inc. Sun, Sun Microsystems and the Sun Logo are trademarks or registered trademarks of Sun Microsystems, Inc. in the United States and other countries. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. in the United States and other countries. Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsystems, Inc. The information contained in this document is not designed or intended for use in on-line control of aircraft, air traffic, aircraft navigation or aircraft communications; or in the design, construction, operation or maintenance of any nuclear facility. Sun disclaims any express or implied warranty of fitness for such uses. Contents Preface xxxvii Overview xxxvii A Brief History of SPARC and PCI xxxviii How to Use This Book xxxix Textual Conventions xxxix Contents xl 1. UltraSPARC-IIi Basics 1 1.1 Overview 1 1.2 Design Philosophy 2 1.3 Component Description 3 1.3.1 PCI Bus Module (PBM) 5 1.3.2 IO Memory Management Unit (IOM) 6 1.3.3 External Cache Control Unit (ECU) 6 1.3.4 Memory Controller Unit (MCU) 7 1.3.5 Instruction Cache (I-cache) 8 1.3.6 Data Cache (D-cache) 9 1.3.7 Prefetch and Dispatch Unit (PDU) 9 1.3.8 Translation Lookaside Buffers (iTLB and dTLB) 9 1.3.9 Integer Execution Unit (IEU) 9 iii 1.3.10 Floating-Point Unit (FPU) 10 1.3.11 Graphics Unit (GRU) 10 1.3.12 Load/Store Unit (LSU) 11 1.3.13 Phase Locked Loops (PLL) 11 1.3.14 Signals 11 2. Processor Pipeline 13 2.1 Introductions 13 2.2 Pipeline Stages 14 2.2.1 Stage 1: Fetch (F) Stage 15 2.2.2 Stage 2: Decode (D) Stage 15 2.2.3 Stage 3: Grouping (G) Stage 15 2.2.4 Stage 4: Execution (E) Stage 16 2.2.5 Stage 5: Cache Access (C) Stage 16 2.2.6 Stage 6: N1 Stage 16 2.2.7 Stage 7: N2 Stage 17 2.2.8 Stage 8: N3 Stage 17 2.2.9 Stage 9: Write (W) Stage 17 3. Cache Organization 19 3.1 Introduction 19 3.1.1 Level-1 Caches 19 3.1.2 Level-2 PIPT External Cache (E-cache) 20 4. Overview of I and D-MMUs 23 4.1 Introduction 23 4.2 Virtual Address Translation 23 5. UltraSPARC-IIi in a System 27 5.1 A Hardware Reference Platform 27 5.2 Memory Subsystem 28 iv UltraSPARC-IIi User’s Manual • October 1997 5.2.1 E-cache 29 5.2.2 DRAM Memory 30 5.2.3 Transceivers 31 5.3 PCI Interface—Advanced PCI Bridge 31 5.4 RIC Chip 33 5.5 UPA64S interface (FFB) 33 5.6 Alternate RMTV support 34 5.7 Power Management 34 6. Address Spaces, ASIs, ASRs, and Traps 35 6.1 Overview 35 6.2 Physical Address Space 35 6.2.1 Port Allocations 36 6.2.2 Memory DIMM requirements 36 6.2.3 PCI Address Assignments 38 6.2.4 Probing the address space 39 6.3 Alternate Address Spaces 39 6.3.1 Supported SPARC-V9 ASIs 40 6.3.2 UltraSPARC-IIi (Non-SPARC-V9) ASI Extensions 41 6.4 Summary of CSRs mapped to the Noncacheable address space 48 6.5 Ancillary State Registers 52 6.5.1 Overview of ASRs 52 6.5.2 SPARC-V9-Defined ASRs 53 6.5.3 Non-SPARC-V9 ASRs 54 6.6 Other UltraSPARC-IIi Registers 55 6.7 Supported Traps 56 7. UltraSPARC-IIi Memory System 59 7.1 Overview 59 7.2 10-bit Column Addressing 62 7.3 11-bit Column Addressing 65 Contents v 8. Cache and Memory Interactions 67 8.1 Introduction 67 8.2 Cache Flushing 67 8.2.1 Address Aliasing Flushing 68 8.2.2 Committing Block Store Flushing 69 8.2.3 Displacement Flushing 69 8.3 Memory Accesses and Cacheability 69 8.3.1 Coherence Domains 70 8.3.2 Memory Synchronization: MEMBAR and FLUSH 72 8.3.3 Atomic Operations 74 8.3.4 Non-Faulting Load 76 8.3.5 PREFETCH Instructions 76 8.3.6 Block Loads and Stores 78 8.3.7 I/O (PCI or UPA64S) and Accesses with Side-effects 78 8.3.8 Instruction Prefetch to Side-Effect Locations 79 8.3.9 Instruction Prefetch When Exiting RED_state 79 8.3.10 UltraSPARC-IIi Internal ASIs 79 8.4 Load Buffer 80 8.5 Store Buffer 81 8.5.1 Stores Delayed by Loads 81 8.5.2 Store Buffer Compression 81 9. PCI Bus Interface 83 9.1 Introduction 83 9.1.1 Supported PCI features: 83 9.1.2 Unsupported PCI features: 84 9.2 PCI Bus Operations 84 9.2.1 Basic Read/Write Cycles 84 9.2.2 Transaction Termination Behavior 84 9.2.3 Addressing Modes 85 vi UltraSPARC-IIi User’s Manual • October 1997 9.2.4 Configuration Cycles 85 9.2.5 Special Cycles 85 9.2.6 PCI INT_ACK Generation 86 9.2.7 Exclusive Access 86 9.2.8 Fast Back-to-Back Cycles 86 9.3 Functional Topics 87 9.3.1 PCI Arbiter 87 9.3.2 PCI Commands 87 9.4 Little-endian Support 89 9.4.1 Endian-ness 89 9.4.2 Big- and Little-endian regions 90 9.4.3 Specific Cases 92 10. UltraSPARC-IIi IOM 95 10.1 Block Diagram 96 10.2 TLB Entry Formats 96 10.2.1 TLB CAM Tag 96 10.2.2 TLB RAM Data 98 10.3 DMA Operational Modes 98 10.3.1 Translation Mode 99 10.3.2 Bypass Mode 100 10.3.3 Pass-through Mode 101 10.4 Translation Storage Buffer 101 10.4.1 Translation Table Entry 102 10.4.2 TSB Lookup 102 10.5 PIO Operations 104 10.6 Translation Errors 104 10.7 IOM Demap 105 10.8 Pseudo-LRU replacement algorithm 105 10.9 TLB Initialization and Diagnostics 106 Contents vii 11. Interrupt Handling 107 11.1 Overview 107 11.1.1 Mondo Dispatch Overview 108 11.2 Mondo Unit Functional Description 108 11.2.1 Mondo Vectors. 108 11.3 Details 112 11.4 Interrupt Initialization 113 11.5 Interrupt Servicing 114 11.6 Interrupt Sources 114 11.6.1 PCI Interrupts 115 11.6.2 On-board Device Interrupts 115 11.6.3 Graphic Interrupt 115 11.6.4 Error Interrupts 115 11.6.5 Software Interrupts 115 11.7 Interrupt Concentrator 116 11.8 UltraSPARC-IIi Interrupt Handling 117 11.8.1 Interrupt States 117 11.8.2 Interrupt Prioritizing 117 11.8.3 Interrupt Dispatching 118 11.9 Interrupt Global Registers 120 11.10 Interrupt ASI Registers 121 11.10.1 Outgoing Interrupt Vector Data<2:0> 121 11.10.2 Interrupt Vector Dispatch 121 11.10.3 Interrupt Vector Dispatch Status Register 122 11.10.4 Incoming Interrupt Vector Data<2:0> 122 11.10.5 Interrupt Vector Receive 123 11.11 Software Interrupt (SOFTINT) Register 124 viii UltraSPARC-IIi User’s Manual • October 1997 12. Instruction Set Summary 127 13. VIS™ and Additional Instructions 135 13.1 Introduction 135 13.2 Graphics Data Formats 135 13.2.1 8-Bit Format 135 13.2.2 Fixed Data Formats 136 13.3 Graphics Status Register (GSR) 137 13.4 Graphics Instructions 138 13.4.1 Opcode Format 138 13.4.2 Partitioned Add/Subtract Instructions 139 13.4.3 Pixel Formatting Instructions 140 13.4.4 Partitioned Multiply Instructions 147 13.4.5 Alignment Instructions 154 13.4.6 Logical Operate Instructions 156 13.4.7 Pixel Compare Instructions 159 13.4.8 Edge Handling Instructions 161 13.4.9 Pixel Component Distance (PDIST) 164 13.4.10 Three-Dimensional Array Addressing Instructions 165 13.5 Memory Access Instructions 168 13.5.1 Partial Store Instructions 168 13.5.2 Short Floating-Point Load and Store Instructions 170 13.5.3 Block Load and Store Instructions 172 13.6 Additional Instructions 178 13.6.1 Atomic Quad Load 178 13.6.2 SHUTDOWN 179 14. Implementation Dependencies 181 14.1 SPARC-V9 General Information 181 14.1.1 Level-2 Compliance (Impdep #1) 181 14.1.2 Unimplemented Opcodes, ASIs, and ILLTRAP 181 Contents ix 14.1.3 Trap Levels (Impdep #37, 38, 39, 40, 114, 115) 182 14.1.4 Alternate RSTV support 182 14.1.5 Trap Handling (Impdep #16, 32, 33, 35, 36, 44) 183 14.1.6 SIGM Support (Impdep #116) 183 14.1.7 44-bit Virtual Address Space 184 14.1.8 TICK Register 185 14.1.9 Population Count Instruction (POPC) 186 14.1.10 Secure Software 186 14.1.11 Address Masking (Impdep #125) 186 14.2 SPARC-V9 Integer Operations 187 14.2.1 Integer Register File and Window Control Registers (Impdep #2) 187 14.2.2 Clean Window Handling (Impdep #102) 187 14.2.3 Integer Multiply and Divide 187 14.2.4 Version Register (Impdep #2, 13, 101, 104) 188 14.3 SPARC-V9 Floating-Point Operations 189 14.3.1 Subnormal Operands & Results; Non-standard Operation 189 14.3.2 Overflow, Underflow, and Inexact Traps (Impdep #3, 55) 190 14.3.3 Quad-Precision Floating-Point Operations (Impdep #3) 191 14.3.4 Floating Point Upper and Lower Dirty Bits in FPRS Register 192 14.3.5 Floating-Point Status Register (FSR) (Impdep #13, 19, 22, 23, 24) 193 14.4 SPARC-V9 Memory-Related Operations 196 14.4.1 Load/Store Alternate Address Space (Impdep #5, 29, 30) 196 14.4.2 Load/Store ASR (Impdep #6,7,8,9, 47, 48) 196 14.4.3 MMU Implementation (Impdep #41) 196 14.4.4 FLUSH and Self-Modifying Code (Impdep #122) 196 14.4.5 PREFETCH{A} (Impdep #103, 117) 197 14.4.6 Non-faulting Load and MMU Disable (Impdep #117) 197 14.4.7 LDD/STD Handling (Impdep #107, 108) 198 14.4.8 FP mem_address_not_aligned (Impdep #109, 110, 111, 112) 198 x UltraSPARC-IIi User’s Manual • October 1997 14.4.9 Supported Memory Models (Impdep #113, 121) 198 14.4.10 I/O Operations (Impdep #118, 123) 198 14.5 Non-SPARC-V9 Extensions 199 14.5.1 Per-Processor TICK Compare Field of TICK Register 199 14.5.2 Cache Sub-system 199 14.5.3 Memory Management Unit 199 14.5.4 Error Handling 200 14.5.5 Block Memory Operations 200 14.5.6 Partial Stores 200 14.5.7 Short Floating-Point Loads and Stores 200 14.5.8 Atomic Quad-load 200 14.5.9 PSTATE Extensions: Trap Globals 200 14.5.10 Interrupt Vector Handling 202 14.5.11 Power Down Support and the SHUTDOWN Instruction 203 14.5.12 UltraSPARC-IIi Instruction Set Extensions (Impdep #106) 203 14.5.13 Performance Instrumentation 203 14.5.14 Debug and Diagnostics Support 203 15.
Recommended publications
  • Ultrasparc Iii

    Ultrasparc Iii

    UltraSparc IIi Kevin Normoyle and the Sabre cats One size doesn’t fit all SPARC chip technology available in three broad product categories: • S-Series (servers, highest performance) • I-Series (price/performance, ease-of-use) • E-Series (lowest cost) Tired: Marginal micro-optimizations Wired: Interfaces and integration. 2 of 26 Desktop/High end embedded system issues • Ease of design-in • Low-cost • Simple motherboard designs • Power • Higher performance graphics interfaces • Low latency to memory and I/O • Upgrades • The J word 3 of 26 UltraSPARC-IIi System Example Module 72-bit DIMM 72-bit DIMM SRAM SRAM UltraSPARC IIi SRAM 75MHz/72-bit XCVRs clocks 100MHz/64-bit 66 or 33 MHz UPA64S 32-bit device 3.3v example: Creator3D graphics APB Advanced PCI Bridge (optional) 33MHz/32-bit 33MHz/32-bit Can use PC-style SUPERIO chips 5v/3.3v 5v/3.3v (boot addressing / INT_ACK features) 4 of 26 Highlights • TI Epic4 GS2, 5-layer CMOS, 2.6v core, 3.3v I/O. • Sun’s Visual Instruction Set - VIS(TM) - 2-D, 3-D graphics, image processing, real-time compression/decompression, video effects - block loads and stores (64-byte blocks) sustain 300 MByte/s to/from main memory, with arbitrary src/dest alignment • Four-way superscalar instruction issue - 6 pipes: 2 integer, 2 fp/graphics, 1 load/store, 1 branch • High bandwidth / Low latency interfaces - Synchronous, external L2 cache, 0.25MB - 2MB - 8-byte (+parity) data bus to L2 cache (1.2 GByte/s sustained) - 8-byte (+ECC) data bus to DRAM XCVRs (400 MByte/s sustained) or UPA64S (800 Mbyte/s sustained) - 4-byte PCI/66 interface.
  • Sun Fire E2900 Server

    Sun Fire E2900 Server

    Sun FireTM E2900 Server Just the Facts February 2005 SunWin token 401325 Sun Confidential – Internal Use Only Just The Facts Sun Fire E2900 Server Copyrights ©2005 Sun Microsystems, Inc. All Rights Reserved. Sun, Sun Microsystems, the Sun logo, Sun Fire, Netra, Ultra, UltraComputing, Sun Enterprise, Sun Enterprise Ultra, Starfire, Solaris, Sun WebServer, OpenBoot, Solaris Web Start Wizards, Solstice, Solstice AdminSuite, Solaris Management Console, SEAM, SunScreen, Solstice DiskSuite, Solstice Backup, Sun StorEdge, Sun StorEdge LibMON, Solstice Site Manager, Solstice Domain Manager, Solaris Resource Manager, ShowMe, ShowMe How, SunVTS, Solstice Enterprise Agents, Solstice Enterprise Manager, Java, ShowMe TV, Solstice TMNscript, SunLink, Solstice SunNet Manager, Solstice Cooperative Consoles, Solstice TMNscript Toolkit, Solstice TMNscript Runtime, SunScreen EFS, PGX, PGX32, SunSpectrum, SunSpectrum Platinum, SunSpectrum Gold, SunSpectrum Silver, SunSpectrum Bronze, SunStart, SunVIP, SunSolve, and SunSolve EarlyNotifier are trademarks or registered trademarks of Sun Microsystems, Inc. in the United States and other countries. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. in the United States and other countries. Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsystems, Inc. UNIX is a registered trademark in the United States and other countries, exclusively licensed through X/Open Company, Ltd. All other product or service names mentioned
  • Sun Ultratm 5 Workstation Just the Facts

    Sun Ultratm 5 Workstation Just the Facts

    Sun UltraTM 5 Workstation Just the Facts Copyrights 1999 Sun Microsystems, Inc. All Rights Reserved. Sun, Sun Microsystems, the Sun logo, Ultra, PGX, PGX24, Solaris, Sun Enterprise, SunClient, UltraComputing, Catalyst, SunPCi, OpenWindows, PGX32, VIS, Java, JDK, XGL, XIL, Java 3D, SunVTS, ShowMe, ShowMe TV, SunForum, Java WorkShop, Java Studio, AnswerBook, AnswerBook2, Sun Enterprise SyMON, Solstice, Solstice AutoClient, ShowMe How, SunCD, SunCD 2Plus, Sun StorEdge, SunButtons, SunDials, SunMicrophone, SunFDDI, SunLink, SunHSI, SunATM, SLC, ELC, IPC, IPX, SunSpectrum, JavaStation, SunSpectrum Platinum, SunSpectrum Gold, SunSpectrum Silver, SunSpectrum Bronze, SunVIP, SunSolve, and SunSolve EarlyNotifier are trademarks, registered trademarks, or service marks of Sun Microsystems, Inc. in the United States and other countries. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. in the United States and other countries. Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsystems, Inc. UNIX is a registered trademark in the United States and other countries, exclusively licensed through X/Open Company, Ltd. OpenGL is a registered trademark of Silicon Graphics, Inc. Display PostScript and PostScript are trademarks of Adobe Systems, Incorporated, which may be registered in certain jurisdictions. Netscape is a trademark of Netscape Communications Corporation. DLT is claimed as a trademark of Quantum Corporation in the United States and other countries. Just the Facts May 1999 Positioning The Sun UltraTM 5 Workstation Figure 1. The Ultra 5 workstation The Sun UltraTM 5 workstation is an entry-level workstation based upon the 333- and 360-MHz UltraSPARCTM-IIi processors. The Ultra 5 is Sun’s lowest-priced workstation, designed to meet the needs of price-sensitive and volume-purchase customers in the personal workstation market without sacrificing performance.
  • The Interactive Performance of SLIM: a Stateless, Thin-Client Architecture ✽ ✽ ✝ Brian K

    The Interactive Performance of SLIM: a Stateless, Thin-Client Architecture ✽ ✽ ✝ Brian K

    17th ACM Symposium on Operating Systems Principles (SOSP’99) Published as Operating Systems Review, 34(5):32–47, December 1999 The interactive performance of SLIM: a stateless, thin-client architecture ✽ ✽ ✝ Brian K. Schmidt , Monica S. Lam , J. Duane Northcutt ✽ Computer Science Department, Stanford University {bks, lam}@cs.stanford.edu ✝ Sun Microsystems Laboratories [email protected] Abstract 1 Introduction Taking the concept of thin clients to the limit, this paper Since the mid 1980’s, the computing environments of proposes that desktop machines should just be simple, many institutions have moved from large mainframe, stateless I/O devices (display, keyboard, mouse, etc.) that time-sharing systems to distributed networks of desktop access a shared pool of computational resources over a machines. This trend was motivated by the need to provide dedicated interconnection fabric — much in the same way everyone with a bit-mapped display, and it was made as a building’s telephone services are accessed by a possible by the widespread availability of collection of handset devices. The stateless desktop design high-performance workstations. However, the desktop provides a useful mobility model in which users can computing model is not without its problems, many of transparently resume their work on any desktop console. which were raised by the original UNIX designers[14]: This paper examines the fundamental premise in this “Because each workstation has private data, each system design that modern, off-the-shelf interconnection must be administered separately; maintenance is technology can support the quality-of-service required by difficult to centralize. The machines are replaced today’s graphical and multimedia applications.
  • Just the Facts Sunwin Token #333632

    Just the Facts Sunwin Token #333632

    Sun FireTM V480 Server Just the Facts SunWIN token #333632 September 2002 Version 2.7 Notice: This document continues to be restricted to internal usage only because of references to internal web pages. With the removal of these references, selected sections of the document may be provided to customers and/or selling channels as required. Competitive information and relative positioning should always remain as internal documentation only. Copyrights ©2000, 2001 Sun Microsystems, Inc. All Rights Reserved. Sun, Sun Microsystems, the Sun logo, Sun Fire, Ultra, UltraComputing, Sun Enterprise, Sun Enterprise Ultra, Starfire, Solaris, Sun WebServer, OpenBoot, Solaris Web Start Wizards, Solstice, Solstice AdminSuite, Solaris Management Console, Sun Enterprise Authentication Mechanism, SunScreen, Solstice DiskSuite, Sun StorEdge, Sun StorEdge LibMON, Solstice Site Manager, Solstice Domain Manager, Solaris Resource Manager, ShowMe, ShowMe How, SunVTS, Solstice Enterprise Agents, Solstice Enterprise Manager, Java, ShowMe TV, Solstice TMNscript, SunLink, Solstice SunNet Manager, Solstice Cooperative Consoles, Solstice TMNscript Toolkit, Solstice TMNscript Runtime, SunScreen EFS, PGX, PGX32, SunSpectrum, SunSpectrum Platinum, SunSpectrum Gold, SunSpectrum Silver, SunSpectrum Bronze, SunStart, SunVIP, SunSolve, and SunSolve EarlyNotifier are trademarks or registered trademarks of Sun Microsystems, Inc. in the United States and other countries. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. in the United States and other countries. Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsystems, Inc. Microsoft, Netware, Macintosh, Lotus, Oracle, Sybase, Intel, Veritas, Windows, Linux, HP-UX and AIX are the respective trademarks of their owners. UNIX is a registered trademark in the United States and other countries, exclusively licensed through X/Open Company, Ltd.
  • Sun Ultratm 2 Workstation Just the Facts

    Sun Ultratm 2 Workstation Just the Facts

    Sun UltraTM 2 Workstation Just the Facts Copyrights 1999 Sun Microsystems, Inc. All Rights Reserved. Sun, Sun Microsystems, the Sun Logo, Ultra, SunFastEthernet, Sun Enterprise, TurboGX, TurboGXplus, Solaris, VIS, SunATM, SunCD, XIL, XGL, Java, Java 3D, JDK, S24, OpenWindows, Sun StorEdge, SunISDN, SunSwift, SunTRI/S, SunHSI/S, SunFastEthernet, SunFDDI, SunPC, NFS, SunVideo, SunButtons SunDials, UltraServer, IPX, IPC, SLC, ELC, Sun-3, Sun386i, SunSpectrum, SunSpectrum Platinum, SunSpectrum Gold, SunSpectrum Silver, SunSpectrum Bronze, SunVIP, SunSolve, and SunSolve EarlyNotifier are trademarks, registered trademarks, or service marks of Sun Microsystems, Inc. in the United States and other countries. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. in the United States and other countries. Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsystems, Inc. OpenGL is a registered trademark of Silicon Graphics, Inc. UNIX is a registered trademark in the United States and other countries, exclusively licensed through X/Open Company, Ltd. Display PostScript and PostScript are trademarks of Adobe Systems, Incorporated. DLT is claimed as a trademark of Quantum Corporation in the United States and other countries. Just the Facts May 1999 Sun Ultra 2 Workstation Figure 1. The Sun UltraTM 2 workstation Sun Ultra 2 Workstation Scalable Computing Power for the Desktop Sun UltraTM 2 workstations are designed for the technical users who require high performance and multiprocessing (MP) capability. The Sun UltraTM 2 desktop series combines the power of multiprocessing with high-bandwidth networking, high-performance graphics, and exceptional application performance in a compact desktop package. Users of MP-ready and multithreaded applications will benefit greatly from the performance of the Sun Ultra 2 dual-processor capability.
  • Sun Enterprisetm 220R Server Just the Facts

    Sun Enterprisetm 220R Server Just the Facts

    Sun EnterpriseTM 220R Server Just the Facts Copyrights 1998, 1999 Sun Microsystems, Inc. All Rights Reserved. Sun, Sun Microsystems, the Sun logo, Sun Enterprise, Ultra, UltraComputing, Sun Enterprise Ultra, Starfire, Solaris, Solstice, Sun Enterprise SyMON, Sun WebServer, IPX, NFS, VIS, Sun StorEdge, OpenBoot, Solaris Web Start Wizards, Solstice AdminSuite, Solaris Management Console, Sun Enterprise Authentication Mechanism, SunScreen, Solstice DiskSuite, Solstice Backup, Sun StorEdge LibMON, Solstice Site Manager, Solstice Domain Manager, Solaris Resource Manager, ShowMe How, Solstice Enterprise Manager, Solstice Enterprise Agents, ShowMe TV, Java, SunLink, Solstice SunNet Manager, SunScreen EFS, Solstice Cooperative Consoles, Solstice TMNscript, Solstice TMNscript Runtime, SunCD, SunVTS, SunSpectrum, SunSwift, SunFastEthernet, SunFDDI, SunTRI/P, SunHSI/P, PGX, PGX32, SunATM, SunSpectrum Platinum, SunSpectrum Gold, SunSpectrum Silver, SunSpectrum Bronze, SunStart, SunVIP, SunSolve, and SunSolve EarlyNotifier are trademarks, registered trademarks, or service marks of Sun Microsystems, Inc. in the United States and other countries. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. in the United States and other countries. Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsystems, Inc. UNIX is a registered trademark in the United States and in other countries, exclusively licensed through X/Open Company, Ltd. Just the Facts November 1999 Positioning Figure 1. Sun EnterpriseTM 220R System Exceptional Processing Power in a Compact Footprint The Sun EnterpriseTM 220R server is the latest member of Sun’s powerful line of servers for enterprise network computing based on the UltraSPARCTM processor technology. This next-generation workgroup server brings multiprocessing power, UltraSCSI disks, and the industry-standard peripheral component interconnect (PCI) I/O bus to a highly modular, rack-optimized 4RU (rack unit) design.
  • Dynamic Helper Threaded Prefetching on the Sun Ultrasparc® CMP Processor

    Dynamic Helper Threaded Prefetching on the Sun Ultrasparc® CMP Processor

    Dynamic Helper Threaded Prefetching on the Sun UltraSPARC® CMP Processor Jiwei Lu, Abhinav Das, Wei-Chung Hsu Khoa Nguyen, Santosh G. Abraham Department of Computer Science and Engineering Scalable Systems Group University of Minnesota, Twin Cities Sun Microsystems Inc. {jiwei,adas,hsu}@cs.umn.edu {khoa.nguyen,santosh.abraham}@sun.com Abstract [26], [28], the processor checkpoints the architectural state and continues speculative execution that Data prefetching via helper threading has been prefetches subsequent misses in the shadow of the extensively investigated on Simultaneous Multi- initial triggering missing load. When the initial load Threading (SMT) or Virtual Multi-Threading (VMT) arrives, the processor resumes execution from the architectures. Although reportedly large cache checkpointed state. In software pre-execution (also latency can be hidden by helper threads at runtime, referred to as helper threads or software scouting) [2], most techniques rely on hardware support to reduce [4], [7], [10], [14], [24], [29], [35], a distilled version context switch overhead between the main thread and of the forward slice starting from the missing load is helper thread as well as rely on static profile feedback executed, minimizing the utilization of execution to construct the help thread code. This paper develops resources. Helper threads utilizing run-time a new solution by exploiting helper threaded pre- compilation techniques may also be effectively fetching through dynamic optimization on the latest deployed on processors that do not have the necessary UltraSPARC Chip-Multiprocessing (CMP) processor. hardware support for hardware scouting (such as Our experiments show that by utilizing the otherwise checkpointing and resuming regular execution). idle processor core, a single user-level helper thread Initial research on software helper threads is sufficient to improve the runtime performance of the developed the underlying run-time compiler main thread without triggering multiple thread slices.
  • Day 2, 1640: Leveraging Opensparc

    Day 2, 1640: Leveraging Opensparc

    Leveraging OpenSPARC ESA Round Table 2006 on Next Generation Microprocessors for Space Applications G.Furano, L.Messina – TEC-EDD OpenSPARC T1 • The T1 is a new-from-the-ground-up SPARC microprocessor implementation that conforms to the UltraSPARC architecture 2005 specification and executes the full SPARC V9 instruction set. Sun has produced two previous multicore processors: UltraSPARC IV and UltraSPARC IV+, but UltraSPARC T1 is its first microprocessor that is both multicore and multithreaded. • The processor is available with 4, 6 or 8 CPU cores, each core able to handle four threads. Thus the processor is capable of processing up to 32 threads concurrently. • Designed to lower the energy consumption of server computers, the 8-cores CPU uses typically 72 W of power at 1.2 GHz. G.Furano, L.Messina – TEC-EDD 72W … 1.2 GHz … 90nm … • Is a cutting edge design, targeted for high-end servers. • NOT FOR SPACE USE • But, let’s see which are the potential spin-in … G.Furano, L.Messina – TEC-EDD Why OPEN ? On March 21, 2006, Sun made the UltraSPARC T1 processor design available under the GNU General Public License. The published information includes: • Verilog source code of the UltraSPARC T1 design, including verification suite and simulation models • ISA specification (UltraSPARC Architecture 2005) • The Solaris 10 OS simulation images • Diagnostics tests for OpenSPARC T1 • Scripts, open source and Sun internal tools needed to simulate the design and to do synthesis of the design • Scripts and documentation to help with FPGA implementation
  • Sun Ultratm 25 Workstation & Sun Ultra 45 Workstation Just the Facts

    Sun Ultratm 25 Workstation & Sun Ultra 45 Workstation Just the Facts

    Sun UltraTM 25 Workstation & Sun Ultra 45 Workstation Just the Facts SunWIN Token# 473547 SunWIN Token# 460409 Copyrights © 2006 Sun Microsystems, Inc. All Rights Reserved. Sun, Sun Microsystems, the Sun logo, Ultra, Sun Blade, Java, Solaris, Java, NetBeans, Sun Fire, Sun StorEdge, SunLink, SunSpectrum, SunSpectrum Platinum, SunSpectrum Gold, SunSpectrum Silver, SunSpectrum Bronze, SunSolve, SunPCi, and SunVTS are trademarks or registered trademarks of Sun Microsystems, Inc. in the United States and other countries. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. in the United States and other countries. Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsystems, Inc. UNIX is a registered trademark in the United States and other countries, exclusively licensed through X/Open Company, Ltd. Ultra 25/45 JTF - 12/10/07 Sun Confidential – Internal Use Only 2 Table of Contents Positioning.....................................................................................................................................................................4 Introduction...............................................................................................................................................................4 Product Family Placement .......................................................................................................................................5 Sun Ultra 45 vs Sun Ultra 25 Workstation...............................................................................................................5
  • Ultrasparctm II Microprocessor

    Ultrasparctm II Microprocessor

    UltraSPARCTM II Microprocessor High-Performance, Highly-Scalable, Multiprocess- The UltraSPARC II processor microarchitecture is designed ing, 64-bit SPARC™ V9 RISC Microprocessor to provide up to 4-way glueless multiprocessing support and supports up to 64-way systems. The processor sup- ports multiple L2 cache speeds and sizes to enable high- performance multiprocessing systems. Balanced overall system performance requires optimal performance along three critical levels: memory band- width, media processing, and raw compute performance. A highly-scalable, high-performance system interconnect ensures a bottleneck-free computing environment result- ing in high memory bandwidth. VIS™ (Visual Instruction Set) multimedia extensions boost the performance of graphics-intensive multimedia applications, and thus reduce overall system costs by eliminating the need for a special-purpose media processor. And the UltraSPARC II delivers superior raw compute performance by using the Placeholder for illustration or photo most innovative RISC microprocessor architecture and state-of-the-art process technology. The UltraSPARC II processor not only helps the system designer by implementing industry-standard testing and instrumentation interfaces, it also uses Error Checking & Correction (ECC) and parity to increase system reliability. With high performance, high scalability, and high reliabil- ity, the UltraSPARC II is the processor of choice for today’s workstations and servers. FEATURES • Full 64-bit implementation of SPARC V9 architecture • 100% binary compatibility with previous versions of SPARC systems The state-of-the-art UltraSPARC™ II processor is the second • Built-in MP support (glueless 4-way and up to 64-way) generation in the UltraSPARC s-series microprocessor fam- • High-performance UPA system interconnect ily.
  • S U N U Ltra™ 60 Workstation

    S U N U Ltra™ 60 Workstation

    S UN ULTRA™ 60 WORKSTATION THE NEXT LEVEL IN MULTIPROCESSING WORKSTATIONS. .................... .................... It’s the perfect combination of raw multiprocessing performance and sophisticated next-generation technologies—a high-powered, flexible system that’s ready for today’s compute-intensive challenges. And for whatever’s next. The Sun Ultra™ 60 workstation accommodates two powerful, 450-MHz UltraSPARC™-II modules, with horsepower to drive demanding applications. And the combination of fast UltraSCSI disk, 66-MHz PCI technology, and the 120-MHz, 1.9 GB/sec., crossbar-switch UPA interconnect delivers exceptionally fast processing and throughput. • Graphics are no less advanced, with Creator3D and Elite3D able to handle applications like geotechnical, simulation, seismic analysis, and medical imaging. Plus, dual-head and 24-inch monitor support means more visible display area—and more productivity. The Sun Ultra 60 workstation. HIGHLIGHTS •Up to two 450-MHz or 360-MHz • Modular design and 120-MHz,1.9 GB/sec. • Two Creator3D or Elite3D m3 graphics • Supports previous-generation memory, UltraSPARC-II modules and 4-MB cache UPA interconnect allows easy upgrade cards, or one Elite3D m6 card, with disk, and graphics cards, protecting for exceptional application performance. to next-generation processors, graphics one Creator3D 0r one Elite m3 provide hardware investments. • 100% binary compatible with entire cards, and peripherals. outstanding performance for • Dual-bus 66-MHz PCI technology, product line—which protects your • Rigorous testing ensures a robust, well- demanding graphics applications. 10-/100-BaseT Ethernet, and UltraSCSI investment. engineered system and years of uptime. disk provide the industry’s best I/O and networking capabilities. .................... SUN ULTRA 60 SPECIFICATIONS PROCESSOR OPTIONS MONITOR OPTIONS 24-in.