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Ultrasparc Iii User's Manual UltraSPARC ™-IIi User’s Manual Sun Microelectronics 901 San Antonio Road Palo Alto, CA 94303 USA 800 681-8845 http://www.sun.com/microelectronics Part No.: 805-0087-01 Copyright © 1997 Sun Microsystems, Inc. All Rights reserved. THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED"AS IS" WITHOUT ANY EXPRESS REPRESENTATIONS OR WARRANTIES. IN ADDITION, SUN MICROSYSTEMS, INC. DISCLAIMS ALL IMPLIED REPRESENTATIONS AND WARRANTIES, INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. This document contains proprietary information of Sun Microsystems, Inc. or under license from third parties. No part of this document may be reproduced in any form or by any means or transferred to any third party without the prior written consent of Sun Microsystems, Inc. Sun, Sun Microsystems and the Sun Logo are trademarks or registered trademarks of Sun Microsystems, Inc. in the United States and other countries. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. in the United States and other countries. Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsystems, Inc. The information contained in this document is not designed or intended for use in on-line control of aircraft, air traffic, aircraft navigation or aircraft communications; or in the design, construction, operation or maintenance of any nuclear facility. Sun disclaims any express or implied warranty of fitness for such uses. Contents Preface xxxvii Overview xxxvii A Brief History of SPARC and PCI xxxviii How to Use This Book xxxix Textual Conventions xxxix Contents xl 1. UltraSPARC-IIi Basics 1 1.1 Overview 1 1.2 Design Philosophy 2 1.3 Component Description 3 1.3.1 PCI Bus Module (PBM) 5 1.3.2 IO Memory Management Unit (IOM) 6 1.3.3 External Cache Control Unit (ECU) 6 1.3.4 Memory Controller Unit (MCU) 7 1.3.5 Instruction Cache (I-cache) 8 1.3.6 Data Cache (D-cache) 9 1.3.7 Prefetch and Dispatch Unit (PDU) 9 1.3.8 Translation Lookaside Buffers (iTLB and dTLB) 9 1.3.9 Integer Execution Unit (IEU) 9 iii 1.3.10 Floating-Point Unit (FPU) 10 1.3.11 Graphics Unit (GRU) 10 1.3.12 Load/Store Unit (LSU) 11 1.3.13 Phase Locked Loops (PLL) 11 1.3.14 Signals 11 2. Processor Pipeline 13 2.1 Introductions 13 2.2 Pipeline Stages 14 2.2.1 Stage 1: Fetch (F) Stage 15 2.2.2 Stage 2: Decode (D) Stage 15 2.2.3 Stage 3: Grouping (G) Stage 15 2.2.4 Stage 4: Execution (E) Stage 16 2.2.5 Stage 5: Cache Access (C) Stage 16 2.2.6 Stage 6: N1 Stage 16 2.2.7 Stage 7: N2 Stage 17 2.2.8 Stage 8: N3 Stage 17 2.2.9 Stage 9: Write (W) Stage 17 3. Cache Organization 19 3.1 Introduction 19 3.1.1 Level-1 Caches 19 3.1.2 Level-2 PIPT External Cache (E-cache) 20 4. Overview of I and D-MMUs 23 4.1 Introduction 23 4.2 Virtual Address Translation 23 5. UltraSPARC-IIi in a System 27 5.1 A Hardware Reference Platform 27 5.2 Memory Subsystem 28 iv UltraSPARC-IIi User’s Manual • October 1997 5.2.1 E-cache 29 5.2.2 DRAM Memory 30 5.2.3 Transceivers 31 5.3 PCI Interface—Advanced PCI Bridge 31 5.4 RIC Chip 33 5.5 UPA64S interface (FFB) 33 5.6 Alternate RMTV support 34 5.7 Power Management 34 6. Address Spaces, ASIs, ASRs, and Traps 35 6.1 Overview 35 6.2 Physical Address Space 35 6.2.1 Port Allocations 36 6.2.2 Memory DIMM requirements 36 6.2.3 PCI Address Assignments 38 6.2.4 Probing the address space 39 6.3 Alternate Address Spaces 39 6.3.1 Supported SPARC-V9 ASIs 40 6.3.2 UltraSPARC-IIi (Non-SPARC-V9) ASI Extensions 41 6.4 Summary of CSRs mapped to the Noncacheable address space 48 6.5 Ancillary State Registers 52 6.5.1 Overview of ASRs 52 6.5.2 SPARC-V9-Defined ASRs 53 6.5.3 Non-SPARC-V9 ASRs 54 6.6 Other UltraSPARC-IIi Registers 55 6.7 Supported Traps 56 7. UltraSPARC-IIi Memory System 59 7.1 Overview 59 7.2 10-bit Column Addressing 62 7.3 11-bit Column Addressing 65 Contents v 8. Cache and Memory Interactions 67 8.1 Introduction 67 8.2 Cache Flushing 67 8.2.1 Address Aliasing Flushing 68 8.2.2 Committing Block Store Flushing 69 8.2.3 Displacement Flushing 69 8.3 Memory Accesses and Cacheability 69 8.3.1 Coherence Domains 70 8.3.2 Memory Synchronization: MEMBAR and FLUSH 72 8.3.3 Atomic Operations 74 8.3.4 Non-Faulting Load 76 8.3.5 PREFETCH Instructions 76 8.3.6 Block Loads and Stores 78 8.3.7 I/O (PCI or UPA64S) and Accesses with Side-effects 78 8.3.8 Instruction Prefetch to Side-Effect Locations 79 8.3.9 Instruction Prefetch When Exiting RED_state 79 8.3.10 UltraSPARC-IIi Internal ASIs 79 8.4 Load Buffer 80 8.5 Store Buffer 81 8.5.1 Stores Delayed by Loads 81 8.5.2 Store Buffer Compression 81 9. PCI Bus Interface 83 9.1 Introduction 83 9.1.1 Supported PCI features: 83 9.1.2 Unsupported PCI features: 84 9.2 PCI Bus Operations 84 9.2.1 Basic Read/Write Cycles 84 9.2.2 Transaction Termination Behavior 84 9.2.3 Addressing Modes 85 vi UltraSPARC-IIi User’s Manual • October 1997 9.2.4 Configuration Cycles 85 9.2.5 Special Cycles 85 9.2.6 PCI INT_ACK Generation 86 9.2.7 Exclusive Access 86 9.2.8 Fast Back-to-Back Cycles 86 9.3 Functional Topics 87 9.3.1 PCI Arbiter 87 9.3.2 PCI Commands 87 9.4 Little-endian Support 89 9.4.1 Endian-ness 89 9.4.2 Big- and Little-endian regions 90 9.4.3 Specific Cases 92 10. UltraSPARC-IIi IOM 95 10.1 Block Diagram 96 10.2 TLB Entry Formats 96 10.2.1 TLB CAM Tag 96 10.2.2 TLB RAM Data 98 10.3 DMA Operational Modes 98 10.3.1 Translation Mode 99 10.3.2 Bypass Mode 100 10.3.3 Pass-through Mode 101 10.4 Translation Storage Buffer 101 10.4.1 Translation Table Entry 102 10.4.2 TSB Lookup 102 10.5 PIO Operations 104 10.6 Translation Errors 104 10.7 IOM Demap 105 10.8 Pseudo-LRU replacement algorithm 105 10.9 TLB Initialization and Diagnostics 106 Contents vii 11. Interrupt Handling 107 11.1 Overview 107 11.1.1 Mondo Dispatch Overview 108 11.2 Mondo Unit Functional Description 108 11.2.1 Mondo Vectors. 108 11.3 Details 112 11.4 Interrupt Initialization 113 11.5 Interrupt Servicing 114 11.6 Interrupt Sources 114 11.6.1 PCI Interrupts 115 11.6.2 On-board Device Interrupts 115 11.6.3 Graphic Interrupt 115 11.6.4 Error Interrupts 115 11.6.5 Software Interrupts 115 11.7 Interrupt Concentrator 116 11.8 UltraSPARC-IIi Interrupt Handling 117 11.8.1 Interrupt States 117 11.8.2 Interrupt Prioritizing 117 11.8.3 Interrupt Dispatching 118 11.9 Interrupt Global Registers 120 11.10 Interrupt ASI Registers 121 11.10.1 Outgoing Interrupt Vector Data<2:0> 121 11.10.2 Interrupt Vector Dispatch 121 11.10.3 Interrupt Vector Dispatch Status Register 122 11.10.4 Incoming Interrupt Vector Data<2:0> 122 11.10.5 Interrupt Vector Receive 123 11.11 Software Interrupt (SOFTINT) Register 124 viii UltraSPARC-IIi User’s Manual • October 1997 12. Instruction Set Summary 127 13. VIS™ and Additional Instructions 135 13.1 Introduction 135 13.2 Graphics Data Formats 135 13.2.1 8-Bit Format 135 13.2.2 Fixed Data Formats 136 13.3 Graphics Status Register (GSR) 137 13.4 Graphics Instructions 138 13.4.1 Opcode Format 138 13.4.2 Partitioned Add/Subtract Instructions 139 13.4.3 Pixel Formatting Instructions 140 13.4.4 Partitioned Multiply Instructions 147 13.4.5 Alignment Instructions 154 13.4.6 Logical Operate Instructions 156 13.4.7 Pixel Compare Instructions 159 13.4.8 Edge Handling Instructions 161 13.4.9 Pixel Component Distance (PDIST) 164 13.4.10 Three-Dimensional Array Addressing Instructions 165 13.5 Memory Access Instructions 168 13.5.1 Partial Store Instructions 168 13.5.2 Short Floating-Point Load and Store Instructions 170 13.5.3 Block Load and Store Instructions 172 13.6 Additional Instructions 178 13.6.1 Atomic Quad Load 178 13.6.2 SHUTDOWN 179 14. Implementation Dependencies 181 14.1 SPARC-V9 General Information 181 14.1.1 Level-2 Compliance (Impdep #1) 181 14.1.2 Unimplemented Opcodes, ASIs, and ILLTRAP 181 Contents ix 14.1.3 Trap Levels (Impdep #37, 38, 39, 40, 114, 115) 182 14.1.4 Alternate RSTV support 182 14.1.5 Trap Handling (Impdep #16, 32, 33, 35, 36, 44) 183 14.1.6 SIGM Support (Impdep #116) 183 14.1.7 44-bit Virtual Address Space 184 14.1.8 TICK Register 185 14.1.9 Population Count Instruction (POPC) 186 14.1.10 Secure Software 186 14.1.11 Address Masking (Impdep #125) 186 14.2 SPARC-V9 Integer Operations 187 14.2.1 Integer Register File and Window Control Registers (Impdep #2) 187 14.2.2 Clean Window Handling (Impdep #102) 187 14.2.3 Integer Multiply and Divide 187 14.2.4 Version Register (Impdep #2, 13, 101, 104) 188 14.3 SPARC-V9 Floating-Point Operations 189 14.3.1 Subnormal Operands & Results; Non-standard Operation 189 14.3.2 Overflow, Underflow, and Inexact Traps (Impdep #3, 55) 190 14.3.3 Quad-Precision Floating-Point Operations (Impdep #3) 191 14.3.4 Floating Point Upper and Lower Dirty Bits in FPRS Register 192 14.3.5 Floating-Point Status Register (FSR) (Impdep #13, 19, 22, 23, 24) 193 14.4 SPARC-V9 Memory-Related Operations 196 14.4.1 Load/Store Alternate Address Space (Impdep #5, 29, 30) 196 14.4.2 Load/Store ASR (Impdep #6,7,8,9, 47, 48) 196 14.4.3 MMU Implementation (Impdep #41) 196 14.4.4 FLUSH and Self-Modifying Code (Impdep #122) 196 14.4.5 PREFETCH{A} (Impdep #103, 117) 197 14.4.6 Non-faulting Load and MMU Disable (Impdep #117) 197 14.4.7 LDD/STD Handling (Impdep #107, 108) 198 14.4.8 FP mem_address_not_aligned (Impdep #109, 110, 111, 112) 198 x UltraSPARC-IIi User’s Manual • October 1997 14.4.9 Supported Memory Models (Impdep #113, 121) 198 14.4.10 I/O Operations (Impdep #118, 123) 198 14.5 Non-SPARC-V9 Extensions 199 14.5.1 Per-Processor TICK Compare Field of TICK Register 199 14.5.2 Cache Sub-system 199 14.5.3 Memory Management Unit 199 14.5.4 Error Handling 200 14.5.5 Block Memory Operations 200 14.5.6 Partial Stores 200 14.5.7 Short Floating-Point Loads and Stores 200 14.5.8 Atomic Quad-load 200 14.5.9 PSTATE Extensions: Trap Globals 200 14.5.10 Interrupt Vector Handling 202 14.5.11 Power Down Support and the SHUTDOWN Instruction 203 14.5.12 UltraSPARC-IIi Instruction Set Extensions (Impdep #106) 203 14.5.13 Performance Instrumentation 203 14.5.14 Debug and Diagnostics Support 203 15.
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