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2005 Synthesis of Ternary Quantum Logic Circuits by Decomposition

Marek Perkowski Portland State University, [email protected]

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Citation Details Perkowski, Marek, "Synthesis of Ternary Quantum Logic Circuits by Decomposition" (2005). Electrical and Computer Engineering Faculty Publications and Presentations. 220. https://pdxscholar.library.pdx.edu/ece_fac/220

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THE COSINE-SINE DECOMPOSITION (CSD) The Cosine-Sine decomposition has been used recently [8, 7] in the synthesis of binary quantum gates, which are 2n × 2n unitary matrices for n qubit gates. When used in conjunction with local optimization techniques, the CSD provides a recursive synthesis method with a lower number of elementary gates compared to other methods [7]. Cosine-Sine Decomposition: [9, 7] Let the unitary matrix W ∈ Cm×m be partitioned in 2 × 2 block form as r m − r r W11 W12 W = (1) m − r W21 W22  with 2r ≤ m. Then there exist r × r unitary matrices U1, V1, r × r real diagonal matrices C and S, and (m − r) × (m − r) unitary matrices U2, V2 such that

C −S 0 U1 0   V1 0 W =   S C 0   (2) 0 U2   0 V2      0 0 Im−2r     

The matrices C and S are the so-called cosine-sine matrices and are of the form C=diag(cos θ1, cos θ2,..., cos θr), 2 2 S=diag(sin θ1, sin θ2,..., sin θr), such that sin θi + cos θi =1 for 1 ≤ i ≤ r. CSD for Binary Quantum Logic Synthesis: In case of binary quantum logic, all matrices are even dimensional as powers of two. Hence, a given m×m unitary W can be always partitioned into m/2×m/2 square blocks, giving m/2 × m/2 square matrices U1,U2, V1, V2,C,S upon application of the CSD. The decomposition for this case is given in equation (3),

U1 0 C −S V1 0 W =       (3) 0 U2 S C 0 V2       The CSD can be applied to the 2 × 2 block diagonal factors that occur at each iteration until one reaches the qubit level which involves only 2 × 2 matrices [8]. At each iteration level the block diagonal matrices in the decomposition are realized as quantum multiplexers [7]. A quantum multiplexer is a gate acting on k+1 of which one is designated as the control qubit. If the control qubit is the highest order qubit, the multiplexer matrix is block diagonal. Depending on whether the control qubit carries |0i or |1i, the gate then performs either the top left block or the bottom right block of the (k + 1) × (k + 1) block diagonal matrix on the remaining k bits. •

M ≡ / F M / G

Figure 1. A 3-qubit quantum multiplexer. The / represents two wires, one for each lower qubit. Depending on the value of the controlling qubit, F or G is applied to the lower two qubits.

For instance, a quantum multiplexer matrix for 3 qubits will bea2 × 2 block diagonal matrix with each block matrix of size 4 × 4 given in equation (4). The value of the first qubit is |0i in the location of the block matrix

2 F and |1i in the location of the block matrix G. Therefore, depending on whether the control bit carries |0i or |1i, the gate then performs either F or G on the remaining 2 qubits respectively.

F 0   (4) 0 G  

The cosine-sine matrices in the CSD are realized as uniformly k-controlled Ry rotations [7, 8]. Such gates operate on k + 1 qubits, of which the lower k are controls and the top one is the target. A different Ry is applied to the target for each control bit-string. The circuit for a uniformly 2-controlled Ry rotation is given in figure 2.

θ0 θ1 θ2 θ3 Ry Ry Ry Ry Ry

• ≡  ØÙ •  ØÙ • •  ØÙ  ØÙ • •

Figure 2. A uniformly 2-controlled Ry rotation: the lower two bits are the control bits, and the top bit is the target bit. In general, it requires 2k one qubit controlled gates to implement a uniformly k-controlled rotation. The open circles represent the value |0i and the closed circles the value |1i.

For three qubits |ai , |bi, and |ci, the matrix formulation of a uniformly 2-controlled Ry rotation gate is given in equation (5).

cos θi − sin θi a0 b0 c0     ⊗   ⊗   (5) sin θi cos θi a1 b1 c1        

As |bi and |ci in equation (5) take on the values |0i and |1i in four possible combinations, θi takes on the values from the set {θ0,θ1,θ2,θ3}, resulting in different Ry gates being applied to the top most qubit. Each θi is an arbitrary angle.

3. CSD FOR TERNARY QUANTUM LOGIC SYNTHESIS For ternary quantum logic synthesis, an n-qutrit gate will be a unitary matrix W of size 3n × 3n. Partition W as in (1) with m =3n and r =3n−1, so that m − r =3n − 3n−1 =3n−1(3 − 1)=3n−1 · 2. After the application of n−1 n−1 the CSD, W will take the form in equation (2). The matrix blocks U2, V2 will be of size 3 · 2 × 3 · 2; hence an application of the CSD only on these two blocks will decompose each block into the form in equation (3). After these two application of the CSD and some matrix factoring, W will take the form

C −S 0   W =Σ S C 0 Γ (6)      0 0 I    with X1 0 0 I 0 0 I 0 0       Σ= 0 X2 0 0 C1 −S1 0 Z1 0 (7)              0 0 X3   0 S1 C1   0 0 Z2       

3 and Y1 0 0 I 0 0 I 0 0       Γ= 0 Y2 0 0 C2 −S2 0 W1 0 (8)              0 0 Y3   0 S2 C2   0 0 W2        Each block matrix in the decomposition given in equations (6) - (8) above is of size 3n−1 × 3n−1. We realize each block diagonal matrix as a ternary quantum multiplexer acting on n qutrits of which the highest order qutrit is designated as the control qutrit. Depending on which of the values |0i, |1i, or |2i the control qutrit carries, the gate then performs either the top left block, the middle block, or the bottom right block respectively on the remaining n − 1 qutrits. The cosine-sine matrices with identity in top-left/bottom-right block corner are realized as uniformly (n−1)-controlled Rx/Rz rotations. These matrices can be realized as Rx or Rz rotation [6] 3 matrices in R applied to the top most qutrit, controlled by the lower qutrits as they range over {|0i , |1i , |2i}. Each configuration of the lower qutrits leads to a different Rx or Rz gate. EXAMPLE Consider two qutrits being acted upon by an arbitrary gate Q. The CSD synthesis of Q is given in figure 3. ≡ Q M1 (CS)x M2 (CS)z M3 (CS)x M4

Figure 3. The decomposition of an arbitrary 2-qutrit gate Q using the CSD. Each Mi is a ternary quantum multiplexer. The gates (CS)x and (CS)z are uniformly 1-controlled rotations

For 1 ≤ i ≤ 4, each Mi gate in figure 3 is a quantum multiplexer controlled by the top qutrit and can be decomposed to the level of elementary gates as shown in figure 4.

≡ • ≡ +2 • +1 +1 • +2 • Mi X0i X0i X1i X2i

X1i Mi

X2i

Figure 4. Quantum Ternary Multiplexer for second qutrit and its realization in terms of Muthukrishan-Stroud gates. The gates labled +1 and +2 are bit shifts increasing the value of the bit by 1 and 2 mod 3 respectively. Depending on the value of the top control qutrit a, one of Xai is applied to the second qutrit, for a ∈ {0, 1, 2}.

For two qutrits, the matrix for a ternary quantum multiplexer will be a 3 × 3 block diagonal matrix given in equation (9). The value of the first qutrit is |0i in the location of the block matrix F, |1i in the location of the block matrix G, and |2i in the location of the block matrix H. Therefore, depending on whether the control bit carries |0i, |1i, or |2i, the gate then performs either F, G, or H on the remaining qutrit respectively. All blocks in the matrix in equation (9)are of size 3 × 3.

F 0 0   0 G 0 (9)      0 0 H   

The gates (CS)x and (CS)z in figure 3 are uniformly 1-controlled Rx and Rz rotations respectively. In either case, the top qutrit is controlled by the lower one, as shown in figure 5. The gate (CS)z corresponds to the middle matrix in equation (6). The matrix formulation of this gate as a uniformly 1-controlled Rz rotation is given in equation (10).

4 θ0 θ1 θ2 ≡ Rz Rz Rz (CS)z +2 • +1 +1 • +2 •

Figure 5. Uniformly 1-controlled rotations for 2-qutrits, realized as multiplexers via Muthukrishan-Stroud gates. The gates labeled +1 and +2 are bit shifts modulo 3.

cos θi − sin θi 0 a0 b0       sin θi cos θi 0 a1 ⊗ b1 (10)              0 0 1   a2   b2       

Depending on the three possible binary configurations of |bi, θi takes on the values from the set {θ0,θ1,θ2}, resulting in different Rz gates being applied to the top qutrit. If the lower qutrit is |0i, equation (10) reduces to

cos θ1 − sin θ1 0 a1 1       sin θ1 cos θ1 0 a2 ⊗ 0 (11)              0 0 1   a3   0        If the lower qutrit is |1i or |2i, equation (10) reduces to equations (12) and (13) respectively.

cos θ2 − sin θ2 0 a1 0       sin θ2 cos θ2 0 a2 ⊗ 1 (12)              0 0 1   a3   0       

cos θ3 − sin θ3 0 a1 0       sin θ3 cos θ3 0 a2 ⊗ 0 (13)              0 0 1   a3   1        Hence, a 2-qutrit quantum gate can be synthesized via four 1 qutrit quantum multiplexers and three 1-qutrit uniformly controlled rotations on the first qutrit. In general, an n-qutrit quantum gate can be synthesized via four n − 1 qutrit quantum multiplexers and three uniformly n − 1 controlled rotations on the top qutrit.

4. CONCLUSIONS AND FUTURE WORK We give a recursive procedure for ternary quantum logic synthesis by realizing n qutrit logic gates as 3n × 3n unitary matrices and applying the Cosine-Sine Decomposition. We conclude that this method can synthesize a n qutrit gate with four multiplexers acting on n − 1 qutrits and three uniformly n − 1-controlled rotations. A two qutrit example is given. It is our future goal to do a gate count by investigating local optimizations at each level of recursion. We also intend to write a CAD tool for this decomposition and get a gate count for a higher number of qutrits, and extend the decomposition to odd radix multi-valued quantum logic synthesis.

5. ACKNOWLEDGMENTS F. S. Khan is grateful to Jacob Biamonte for discussions, advice, and help in the layout of this paper. The Quan- A tum Circuit diagrams were all drawn in LTEX using Q-circuit available at http://info.phys.unm.edu/Qcircuit/.

5 REFERENCES 1. A. Muthukrishnan, C. R. Stroud Jr, Multi-Valued Logic Gates for Quantum Computation, Revised version to appear in Physical Review A. quant-ph/0002033 v2 2. M. H. A. Khan, M. A. Perkowski Evolutionary Algorithm Based Synthesis of Multi-Output Ternary Functions Using Quantum Cascade of Generalized Ternary Gates 3. S. Bullock, Dianne P. OLeary, Gavin K. Brennen Asymptotically Optimal Quantum Circuits for d-level Systems, quant-ph/0410116 v2 4. H. B. Pasquinucci, A. Peres, with 3-state Systems quant-ph/0001083 v1 5. D. L. Zhou, B. Zeng, Z. Xu, C. P. Sun, Quantum Computation Based on d-Level quant-ph/0304054 v2 6. K. Fuji, Quantum Optical Construction of Generalized Pauli and Walsh-Hadamard Matrices in Three Level Systems quant-ph/0309132 v1 7. V. Shende, S. Bullock, I. Markov, Synthesis of Quantum Logic Circuits, To appear,IEEE Transactions on Computer Aided Design. quant-ph/0406176 8. M. Mottonen, J. J. Vartiainen, V. Bergholm, M. M. Salomaa, Quantum circuits for general multiqubit gates, Phys. Rev. Lett. 93, 130502 (2004). quant-ph/0404089 9. G. W. Stewart, On the Perturbation of Pseudo-Inverses, Projections and Linear Least Square Prob- lems,SIAM Review, Vol. 19, N0 4 (Oct. 1977), 634-662, Appendix. 10. R. K. Brylinski, G. Chen, Mathematics of Quantum Computation Chapman Hall/CRC, 2002, ISBN: 1584882824. 11. G. H. Golub, Charles F. Van Loan, Matrix Computations John Hopkins University Press, 1989, ISBN: 0- 8018-3772-3. 12. S. D. Bartlett, H. D. Guise, B. Sanders, Quantum encodings in systems and harmonic oscillators, Physical Review A, Vol. 65, 052316. 13. M. Miller, D. Maslov, G. Dueck, Synthesis of Quantum Multiple-Valued Circuits, Journal of Multiple-Valued Logic and Soft Computing, special issue on Nano MVL Structures (24 journal pages, accepted). 14. M H. A. Khan, M. A. Perkowski, M. Khan, P. Kerntopf, Ternary GFSOP Minimization using Kronecker Decision Diagrams and Their Synthesis with Quantum Cascades, submitted to special issue of International Journal on Multiple-Valued Logic and Soft Computing, T. Hanyu, editor, 2004. 15. W. N. N. Hung, X. Song, G. Yang, J. Yang, M. A. Perkowski, Quantum logic synthesis by symbolic reacha- bility analysis, In Proceedings of the 41st Design Automation Conference, San Diego, CA, June 2004. 16. A. Barenco, C. Bennet, R. Cleve, D. P. DiVincenzo, N. Margolus, P. Shor, T. Sleator, J. Smolin, H. Wein- furter, Elementary gates for quantum computation, Physical Review A, 52:3457, 1995. quant-ph/9503016 v1 17. A. N. Al-Rabadi, Reversible Logic Synthesis: From Fundamental to , Springer-Verlag, Berlin, Heidelberg 2004, ISBN: 3-540-00935-3 18. D. C. Marinescu,G. M. Marinescu, Approaching Quantum Computing, Pearson Education, Inc. 2005, New Jersey, ISBN: 0-13-145224-X

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