Step 1: Boron Deposition

Final Lab Report Group #7 EE 432 Hunt, Mitch Due: 5-3-07 Jorgensen, Danny Yong, Ket-Bing Brown, Jonathon

Overview: Over the course of the semester, semiconductor chips were created from bare silicon wafers to learn the complex processing path necessary to produce useful devices. The bare wafers were initially cleaned to remove organic materials and unwanted oxides, then oxidized specifically to prepare for the first photolithography. The first photolithography was conducted to pattern the p-wells. A boron deposition and drive were performed to create the p-wells where the photoresist had been removed. Next, a photolithography to pattern the sources and drains of the PMOS transistors was conducted. Another boron deposition and drive were performed to create the sources and drains, and a protective oxide layer was concurrently grown over the entire surface. The third photolithography was conducted to pattern the sources and drains for the NMOS transistors. Into these patterns, phosphorous was deposited and driven, again concurrent to a protective oxide being grown. Another photolithography patterned the gate oxides, with a short oxidation to grow the gate oxides. By placing the oxide in bias to the substrate, charge movement across the device can be manipulated. The contact vias (aluminum) were then patterned by photolithography and deposited by evaporation. These vias allow charge carriers to flow to an external source from the device and allow for device property testing. Lastly, the metal contacts were patterned and sintered. The lithography was performed to isolate the metal contacts from one another and the sintering was performed to create a continuous homogeneous contact from what had previously been a relatively loose pile of aluminum atoms. After all of the processing, the devices were tested and compared to expected performance.

Process Summary: 1. Field Oxide – 1/25/07 Standard Clean: A standard clean is performed whenever a wafer is going to be oxidized or doped. The clean removes any organic material, as well as removing any preexisting oxide layers that are not desired. The clean was conducted as laid out in the Standard Operating Procedure on Standard Clean for Silicon. The heater N2 purge valve was turned on and both SC tubs 1/55 Final Lab Report Group #7 EE 432 Hunt, Mitch Due: 5-3-07 Jorgensen, Danny Yong, Ket-Bing Brown, Jonathon were rinsed with deionized water and allowed to drain. 2500mL of DI water and 500mL of ammonium hydroxide (NH4OH) were added to the left tub, while 3000mL of DI water and 500mL of hydrochloric acid (HCL) were added to the right tub. The graduated cylinder was rinsed between each change in liquid. The temperature controllers for each tub were set at 80°C. When both tubs reached temperature, 500mL of hydrogen peroxide

(H2O2) were added, allowing time for the solution to reach temperature again.

The wafer carrier was rinsed in SC-1 (left tub) for 15 minutes, then moved to the cascade rinse for 5 minutes, where nitrogen was gently bubbled through to “scrub” the wafers. After the cascade rinse, the carrier was transferred to the dilute (50:1) HF tub for 15 seconds and returned to the cascade rinse for 1 minute. The carrier then moved to the SC- 2 (right tub) for 15 minutes, then the cascade rinse for 3 minutes. Both heaters were turned off. After the cascade rinse, the wafers were subjected to one SRD cycle. While this cycle was occurring, 400mL of ammonium hydroxide (NH4OH) was added to the left tub to neutralize both solutions when they were subsequently drained. Each standard clean tub was then thoroughly rinsed with DI water and the wafers were removed from the SRD.

Wet Oxidation: The oxidation was performed to produce an etchable oxide that was eventually patterned to form the p-wells for the devices. Wet oxidation was used because of the much higher growth rate, though the quality of the oxide is lower than dry oxidation. The oxidation furnace (Tube #3) was set to load temperature of 800°C with an atmosphere of 0.3 slpm dry N2.The wafers were loaded into the furnace at a rate of one inch per 15 seconds. This slow rate was used because the thermal expansion of the silicon and the oxide were different. A rapid increase in temperature would cause the metallic silicon to stretch much more quickly than the oxide, causing internal stresses and potentially distorting the wafers. The furnace was then ramped up to 1055°C (30° higher due to furnace variation), which took 15 min, 30s. When the furnace reached temperature, oxidation was performed by switching the atmosphere to 200sccm N2 through the bubbler for 22 min, 40s. After 2/55 Final Lab Report Group #7 EE 432 Hunt, Mitch Due: 5-3-07 Jorgensen, Danny Yong, Ket-Bing Brown, Jonathon the oxidation, the furnace atmosphere was switched back to 0.3 slpm dry N2 and was ramped down to 800°C in 51 min. The wafers were then removed at the same slow rate of insertion.

2. Pattern for p-well – 2/1/07 Pattern Photoresist: Photolithography is a method of chemically imprinting patterns onto silicon to produce transistors. The use of photolithography allows complicated designs to be put on one wafer. The photolithography steps were conducted as laid out in the Standard Operating Procedure on photolithography, with a spin rate of 4000 rpm, spin time of 40 seconds, hexamethyldisilazane used as the adhesive, and AZ5214 used as the photo resist. The wafers were pre-baked at 90°C for 25 minutes to adhere the photoresist and aligned using the Karl-Suss Mask Aligner. The alignment was the most difficult portion of the lab, taking an extended period of time. First, one wafer was loaded onto the aligner platform and inserted into the main body of the aligner. The platform was slowly raised to put the wafer into contact with the photolithography mask (Mask 1 for this lab). The wafer was then slightly separated from the mask to allow for alignment. The external edges of the alignment box were lined up first (coarse alignment) before focusing on the alignment marks in the lower left corner for fine alignment. Once the wafer was satisfactory in its placement, the wafer was raised back into contact with the mask. A final alignment check was performed to maintain that the wafer had not shifted due to mask contact. This alignment procedure was followed for each wafer. The wafers were then exposed for 90 seconds to UV light to set the photoresist, developed for 60 seconds, rinsed for 3 minutes, and post baked for 15 minutes at 120°C.

SiO2 Etch & Photoresist Strip: The wafers were etched in the buffered oxide etch for 6.5 minutes. The oxide etch was determined to be complete when the wafers went from hydrophilic (“catches” water, a property of SiO2) to hydrophobic (water cascades off, a property of Si). The etch was

3/55 Final Lab Report Group #7 EE 432 Hunt, Mitch Due: 5-3-07 Jorgensen, Danny Yong, Ket-Bing Brown, Jonathon followed by 3 minutes of rinsing in “dirty” acetone, 3 minutes in “clean” acetone, 1 minute in methanol, 3 minutes in the cascade rinse, and subjected to one SRD cycle.

3. Boron deposition for p-well – 2/8/07 Standard Clean: The same standard clean procedure from Step 1 was used.

Boron Deposition: The boron deposition was conducted to produce the p-wells for the n-mos transistors and the p-mos transistors. The deposition was carried out in accordance with the Standard Operating Procedure for Boron Diffusion, beginning with a standard clean to remove all oxidation and other impurities from the surface of the device wafers. The boron deposition furnace (Tube #2) was set to 850 °C for the duration of the deposition, and the device side of each wafer faced a boron wafer as shown in Figure 1 (thin lines are device wafers, arrows show device direction).

Figure 1: Schematic for boron deposition in furnace. The wafers were situated in this manner so the boron that was removed from the source wafer would land directly on the device wafer. The wafers were inserted into the furnace at a rate of one inch per 15 seconds, for the same thermal expansion reasons. Once loaded, a recover time of 20 minutes was run to pull the wafers up to deposition temperature, and the boron source wafers were activated by maintaining an atmosphere of 1 lpm N2 + 1 lpm O2 + 40 sccm H2. After 2 minutes, the wafers were soaked at temperature for 36 minutes and 38 seconds. This was five minutes less than the calculated soak time because during the pull from the furnace, the wafers remain at a high

4/55 Final Lab Report Group #7 EE 432 Hunt, Mitch Due: 5-3-07 Jorgensen, Danny Yong, Ket-Bing Brown, Jonathon temperature and the boron continues to deposit on the device wafers. The furnace was returned to its standard state at 400°C AND 0.3 slpm N2.

Deglaze: The wafers were etched in the BOE tub for 2 minutes, rinsed in the cascade rinse for 3 minutes, and put through one SRD cycle.

4. P-well drive (Performed by lab instructors after week of Step 3) Standard Clean: The same standard clean procedure from Step 1 was used.

P-Well Low-Temperature Oxidation (LTO) and Boron Drive: The wet oxidation furnace (tube #3) was set to 800°C and the wafers were loaded into the quartz boat, spaced equally, with a guard wafer on each end so the wafers all saw the same environment.

The bubbler was refilled with DI water then powered up. The N2 gas flow was set to 200 sccm and, after a short self-check and warm up, the bubbler reached 98°C. The boat was then loaded into the furnace at a rate of one inch per 15 seconds. Once loaded and up to temperature, the bubbler switch was set to “Tube” to flow water vapor into the furnace to perform a low temperature oxidation (LTO) for 30 minutes. The LTO was performed to remove the “boron skin” that forms at the surface of the wafer. After 30 minutes, the bubbler was switched off, replaced by 0.3 slpm N2, and the boat was pulled out of the furnace at a rate of one inch per 15 seconds. After removal and cool down, the wafers were etched in the BOE tub for 2 minutes to remove the oxide layer, rinsed in the cascade rinse for 3 minutes, and then subjected to one SRD cycle.

After cleaning, the boat was loaded again at an equal spacing and pushed into the tube at the same slow rate. Once loaded, the furnace temperature was ramped up to the drive temperature (1150°C). The bubbler was then switched to put water vapor into the tube to 5/55 Final Lab Report Group #7 EE 432 Hunt, Mitch Due: 5-3-07 Jorgensen, Danny Yong, Ket-Bing Brown, Jonathon grow a protective oxide during the drive stage. After the desired oxide thickness was achieved (8.5 minutes according to calculations), the bubbler was switched off, the furnace atmosphere was set to 0.3 slpm N2, and the remainder of the 5-hour drive was completed. After 5 hours, the furnace was ramped down to 800°C (approximately 55 minutes) and the wafers were pulled at the same slow rate. Finally, the furnace was set to its standard 600°C condition and the wafers were put in the dry box.

5. Pattern for PMOS source/drain – 2/15/07 Pattern Photoresist: The same patterning procedure from Step 2 was used, this time using Mask 2.

SiO2 Etch & Photoresist Strip: The same etch & strip procedure from Step 2 was used, this time for 10 minutes.

6. Boron deposition for PMOS source/drain (Performed by lab instructors after week of Step 5) Standard Clean: The same standard clean procedure from Step 1 was used.

Boron Deposition: The same boron deposition procedure from Step 3 was used, this time for a 50-minute soak.

Deglaze: The same deglaze procedure from Step 3 was used.

7. Boron drive – 2/22/07 Standard Clean: The same standard clean procedure from Step 1 was used.

6/55 Final Lab Report Group #7 EE 432 Hunt, Mitch Due: 5-3-07 Jorgensen, Danny Yong, Ket-Bing Brown, Jonathon

P-Well Low-Temperature Oxidation (LTO) and Boron Drive: The same LTO and Boron Drive procedures from Step 4 were used.

8. Pattern from NMOS source/drain (Performed by lab instructors after week of Step 7) Pattern Photoresist: The same patterning procedure from Step 2 was used, this time using Mask 3.

9. Phosphorous deposition – 3/2/07 Standard Clean: The same standard clean procedure from Step 1 was used.

Phosphorous Deposition: The phosphorous deposition was conducted to produce the NMOS sources and drains. The deposition was carried out in accordance with the Standard Operating Procedure for Phosphorous Diffusion. The phosphorous deposition furnace (Tube #1) was set to 900°C and remained at that temperature for the duration of the deposition. The device side of each wafer was placed to face a phosphorous wafer as shown below (Figure 2 - thin lines are device wafers, arrows show device direction).

Figure 2: Schematic for phosphorous deposition in furnace.

The wafers were situated in this manner so that the phosphorous that vaporized from the source wafer would land directly on the device wafer. The wafers were inserted into the furnace at a quick rate of one inch per 2 seconds, because the phosphorous begins to deposit immediately, as compared to the boron which had to be activated by the atmosphere to deposit. The wafers were soaked at temperature for 14 minutes and quickly pulled and removed.

Deglaze: The same deglaze procedure from Step 3 was used.

10. Phosphorous Drive – 3/2/07 Standard Clean: The same standard clean procedure from Step 1 was used.

Phosphorous Drive: Once the deposition was complete, the phosphorous drive was conducted in accordance to the Standard Operating Procedure on Phosphorous Diffusion. The wet oxidation furnace (tube #3) was set to 800°C and the wafers were loaded into the quartz boat, spaced equally, with a guard wafer on each end of the quartz boat so the wafers were exposed to the same environment.

The bubbler was refilled with DI water then powered up. The N2 gas flow was set to 200 sccm and, after a short self-check and warm up, the bubbler reached 98°C. The boat was then loaded into the furnace at a rate of one inch per 15 seconds to prevent thermal shock and thermal expansion mismatch. Once loaded, the furnace was ramped up to the drive temperature of 1050°C (ramp time was 18 minutes) in an atmosphere of 0.3slpm dry N2. Once the furnace reached the drive temperature, the bubbler switch was set to “Tube” to flow water vapor into the furnace to produce a protective oxide. The oxidation step was performed for 16 minutes (see Calculations) and the bubbler was turned off for the final 2 minutes of the phosphorous drive (total drive time was 18 minutes, see Calculations) and

8/55 Final Lab Report Group #7 EE 432 Hunt, Mitch Due: 5-3-07 Jorgensen, Danny Yong, Ket-Bing Brown, Jonathon the atmosphere switched to 1.0slpm dry N2. No low-temperature oxidation was performed because no silicon-phosphide “skin” was formed during deposition as in the boron deposition. After the drive time had completed, the furnace was ramped down to

800°C at 0.3 slpm N2 (approximately 60 minutes). The boat was then pulled out of the furnace at a rate of one inch per 15 seconds. The furnace was then set to its standard 600°C condition and the wafers were placed in the dry box.

11. Pattern for gate oxide – 3/22/07 Pattern Photoresist: The same patterning procedure from Step 2 was used, this time using Mask 4.

12. Gate Oxide – 3/22/07 Standard Clean: The same standard clean procedure from Step 1 was used.

Dry Oxidation: The wafers were slowly inserted into an oxidation furnace to prevent thermal shock associated with rapid heating. During the push, the atmosphere was 0.3 slpm dry N2 at 800°C. The furnace was then ramped up to 1080°C in 17 minutes in the same 0.3 slpm dry N2 atmosphere. The temperature was set 30 °C higher than the desired temperature (1050°C) for furnace calibration reasons. Once the samples were inserted, the oxidation cycle was set to 20 minutes under 1 slpm O2, which corresponded to the Deal-Grove dry oxidation calculations done at the start of the lab. These calculations were performed even though the Deal-Grove model does not fit well with thin films. The error produced a thicker-than-expected oxide layer. When the cycle completed, the furnace atmosphere was switched back to 0.3 slpm dry N2 and ramped down to 800°C in 55 minutes. The samples were removed slowly, again to prevent thermal shock. 9/55 Final Lab Report Group #7 EE 432 Hunt, Mitch Due: 5-3-07 Jorgensen, Danny Yong, Ket-Bing Brown, Jonathon

13. Pattern for contact vias – 3/29/07 Pattern Photoresist: The same patterning procedure from Step 2 was used, this time using Mask 5.

SiO2 Etch & Photoresist Strip: The same etch & strip procedure from Step 2 was used, this time for 8.5 minutes.

14. Contact Metallization – 3/29/07 Metallization: The contact vias are metal pads to which the probes connect to access the devices on the wafer’s surface. The wafers were moved quickly from the SRD cycle into the evaporator and were situated as shown in Figure 3.

Figure 3: Evaporator schematic.

The wafers were arranged in such a manner that they all received as similar a metallic layer thickness as possible. The entire holding assembly rotated inside the evaporator to

10/55 Final Lab Report Group #7 EE 432 Hunt, Mitch Due: 5-3-07 Jorgensen, Danny Yong, Ket-Bing Brown, Jonathon evenly coat each wafer. The evaporator, a BJD-1800 system, deposited 2500Å of aluminum across the surface of the wafer. After the evaporation was completed, the wafer had a continuous layer of aluminum across the surface, so needed to be etched to isolate the devices.

15. Metal contact pattern – 4/5/07 Pattern Photoresist: The same patterning procedure from Step 2 was used, this time using Mask 6.

Aluminum etch & Photoresist Strip: Once the evaporation was complete, the devices needed to be isolated by etching certain sections of aluminum away. If the aluminum had not been etched, every device would have been electrically connected and the testing of the devices would have yielded no results. The same photolithography patterning was performed as in the previous steps, but a different etching mechanism was used. A PAN etch was concocted by adding 40 ml

H3PO4 (Phosphoric Acid), 40 ml Ch3COOH (Acetic Acid), and 10 ml HNO3 (Nitric Acid) to 10 ml of distilled water. The wafers were etched one at a time for an average of 9 minutes to remove the patterned aluminum. The etch was determined to be complete after the green layer on the surface was removed. The wafers were then subjected to a cascade rinse for 3 minutes, “dirty” acetone for 3 minutes, “clean” acetone for 3 minutes, and methanol for 1 minute to remove the remaining photoresist. They were then inserted into the cascade rinse for 3 minutes and placed in the SRD machine for one cycle.

Sintering: Sintering is performed to agglomerate the aluminum particles into much higher quality contacts. Prior to sintering, the aluminum atoms form a “pile” instead of one continuous layer. The wafers were loaded into a quartz boat and inserted into the smaller sintering tube at an atmosphere of 1 lpm dry N2, a temperature of 425°C, and a rate of 1 inch per second. A rapid rate could be used because of the lower temperature of the furnace. The

11/55 Final Lab Report Group #7 EE 432 Hunt, Mitch Due: 5-3-07 Jorgensen, Danny Yong, Ket-Bing Brown, Jonathon sintering was performed for 12 minutes at this temperature and was pulled at the same fast rate. Calculations: Lab 1 Calculations – Step 1: The Deal-Grove equations for wet oxide growth were used to determine the amount of time necessary to form an oxide layer of thickness tox = 0.275μm. A temperature of 1025°C was selected to perform the oxidation because that value had not been accounted for, and τ was 0 because the oxide was to be grown on a bare silicon wafer.

T=1025� C 1298 K 骣骣B7 骣-1.93 eV 7 - 1.93 eV 琪=(5.8x 10m m / hr) exp 琪 = ( 5.8 x 10 m m / hr) exp琪 A kT 琪 -5 桫wet 桫桫(8.617x 10 eV / K)( 1298 K )

骣B 琪 =1.8599mm / hr 桫A wet

骣 2骣-0.71eV 2 - 0.71 eV B=188m m / hr exp = 188 m m / hr exp琪 wet ( ) 琪 ( ) 琪 -5 桫 kT 桫(8.617x 10 eV / K)( 1298 K )

2 Bwet = 0.3291m m / hr

2 t t 2 0.275mm (0.275mm) t =ox + ox -t = + - 0 B/ A B 1.8599m m / hr 0.3291 m m2 / hr

骣60min t=0.37766 hr 琪 = 22.6597 min 桫 1hr t= 22 min, 40 s

Lab 2 Calculations – Steps 2-4: Step 3: Boron Deposition

The constant-source diffusion equations were used to find the time required for a dose of Q = 7.5x1013cm-2 12/55 Final Lab Report Group #7 EE 432 Hunt, Mitch Due: 5-3-07 Jorgensen, Danny Yong, Ket-Bing Brown, Jonathon

2 2N0 Q p Q= Dt , solving for t gives t = 2 , p 4DN0

19 -3 Where N0 is the solid solubility limit of boron in silicon at 850°C (9.5x10 cm ), and

骣-EA D= D0 exp琪 . 桫kB T T = 850°C = 1123K

13- 2 2 Q2p (7.5x 10 cm ) p t = = 骣-E 2 骣 -3.5eV 19- 3 4D exp A N 2 4*1cm / s *exp琪 *9.5 x 10 cm 0琪 0 8.617x 10-5 eV / K *1123 K 桫kB T 桫 t=2498 s = 41min,38 s

Step 4: Oxidation (Performed by supervisors)

The Deal-Grove equations for wet oxide growth were used to determine the amount of time necessary to form an oxide layer of thickness tox = 0.25μm. A temperature of 1150°C was selected to perform the oxidation, and τ was 0 because the oxide was to be grown on a bare silicon wafer. T=1150� C 1423 K 骣骣B7 骣-1.93 eV 7 - 1.93 eV 琪=(5.8x 10m m / hr) exp 琪 = ( 5.8 x 10 m m / hr) exp琪 A kT 琪 -5 桫wet 桫桫(8.617x 10 eV / K)( 1423 K )

骣B 琪 = 8.4677mm / hr 桫A wet

骣 2骣-0.71eV 2 - 0.71 eV B=188m m / hr exp = 188 m m / hr exp琪 wet ( ) 琪 ( ) 琪 -5 桫 kT 桫(8.617x 10 eV / K)( 1423 K )

2 Bwet = 0.5748m m / hr

2 t t 2 0.25mm (0.25mm) t =ox + ox -t = + - 0 B/ A B 8.4677m m / hr 0.5748 m m2 / hr

骣60min t=0.13826 hr 琪 = 8.29min 桫 1hr t= 8min,18 s Step 4: Boron Drive (Performed by supervisors)

The Gaussian equation was used to find the surface concentration [N(0)] after the drive and the junction depth. Q N(0, t) = p Dt The drive was performed at 1150°C for 5 hours.

2骣-3.5eV 骣 3600 s - 9 2 Dt=1 cm / s exp琪 *5 hr 琪 = 7.228 x 10 cm 桫8.617x 10-5 eV / K *1423 K 桫 1 hr

7.5x 1013 cm- 2 N(0,3600 s) = N(0,3600 s) = 4.977 x 1017 cm- 3 p *7.228x 10-9 cm 2

1/ 2 骣骣N (0) x= 2 Dt ln j 琪琪桫桫NB

15 -3 From the resistivity chart posted on the wall, NB = 10 cm .

17- 3 -9 2骣骣4.977x 10 cm - 4 xj =2 7.228 x 10 cm琪 ln琪 15- 3 = 4.237 x 10 cm 桫桫 10 cm

xj = 4.237m m

Lab 3 Calculations – Steps 5-7 A temperature of 850°C and deposition time of 50 minutes were selected to perform deposition. The constant-source diffusion portion of the two-step diffusion equations was used to find the total dose from the deposition. The Deal-Grove equations for wet oxide

14/55 Final Lab Report Group #7 EE 432 Hunt, Mitch Due: 5-3-07 Jorgensen, Danny Yong, Ket-Bing Brown, Jonathon growth were used to determine the amount of time necessary to form an oxide layer of thickness tox = 0.25μm. A temperature of 1085°C was selected to perform the oxidation and τ was 0 because the oxide was to be grown on a bare silicon wafer. The constant-dose diffusion portion from the two-step diffusion equation and the dose determined from the deposition step were used to determine the time for the boron drive.

Step 6: Boron Deposition (performed by lab supervisor, find total dose):

骣-EA D= D0 exp琪桫kB T

2 骣 2 cm-3.5 ev 16 cm D1 = 1.0 exp琪 = 1.96 10 琪 -5 s 桫(8.617� 10eV / K)( 850 273 K ) s  cm2   16  13 2 D1t1 = 1.96 10 50 * 60s = 5.786810 cm  s  2N Total dose, Q= 0 D t , where N is the solid solubility limit of boron in silicon at p 1 1 0 850°C (9.5x1019cm-3)

2创 9.5 1020 Q= 5.7868� 10-13 8.217 10 19 cm - 3 p

Step 7: Oxidation (goal of 0.25μm): 骣琪骣B 骣 7 m m-1.93 eV m m 琪= 琪5.8� 10 exp琪 3.98639 桫A 桫 hr琪骣 -5 eV hr wet 琪琪8.617� 10( 1085 273K ) 桫桫 K

骣 2琪 2 骣 mm琪 -0.71 eV m m Bwet =琪188 exp = 0.4356 桫 hr琪骣 -5 eV hr 琪琪8.617� 10( 1085 273K ) 桫桫 K

2 0.25mm (0.25mm) t= + =0.2016 hr = 12.37 min = 12 min,22 s mm mm2 3.9864 0.4356 hr hr

Step 7: Boron drive (30 min at 1085°C, goal of 0.5 – 1.0 μm junction depth): 2 骣 2 cm-3.5 eV 13 cm D2 = 1.0 exp琪 = 1.024 10 琪 -5 s 桫(8.617� 10eV / K )( 273 1085) s 2 骣 -13 cm骣 s 13 2 D2t2 = 琪1.024 10琪 30min*60 = 1.8435310 cm 桫 s 桫 min Q8.217 1019 cm- 2 N(0)= = = 3.415 1019 cm- 3 Surface concentration, -13 2 p D2 t 2 p 创1.84353 10 cm

1/ 2 骣轾N(0) x= 2 D t ln j 2 2 琪犏桫臌NB

15 -3 From the resistivity chart posted on the wall, NB = 10 cm .

1 19- 3 2 -13 2 轾骣3.415 10 cm xj = 2 1.84353� 10 cm 犏 ln琪 15- 3 0.877 m m 臌桫1.00 10 cm

N(0) = 3.42 x 1019 cm- 3

xj = 0.877m m

Lab 4 Calculations – Steps 8-10: A temperature of 900°C and deposition time of 14.03 minutes were selected to perform deposition. The constant-source diffusion portion of the two-step diffusion equations was used to find the total dose from the deposition. The Deal-Grove equations for wet oxide growth were used to determine the amount of time necessary to form an oxide layer of thickness tox = 0.25μm. After much fiddling with the diffusion spreadsheet, a temperature of 1050°C was selected to perform the oxidation and τ was 0 because the oxide was to be grown on a bare silicon wafer. The constant-dose diffusion portion from the two-step diffusion equation and the dose determined from the deposition step were used to determine the time for the phosphorous drive.

Step 9: Phosphorous Deposition (find total dose):

骣-EA D= D0 exp琪桫kB T

2 骣 2 cm-3.68 ev -16 cm D1 = 4.7 exp琪 = 7.251 10 琪 -5 s 桫(8.617� 10eV / K)( 900 273 K ) s 2 骣 -16 cm -13 2 D1t1 = 琪7.251 10( 14.03min*60s / min) = 6.10417 10 cm 桫 s 2N Total dose, Q= 0 D t , where N is the solid solubility limit of boron in silicon at p 1 1 0 900°C (9.5x1019cm-3)

2创 7 1020 Q= 6.1042� 10-13 6.171 10 14 cm - 2 p

Step 10: Oxidation (goal of 0.25μm): 骣琪骣B 骣 7 m m-1.93 eV m m 琪= 琪5.8� 10 exp琪 2.57683 桫A 桫 hr琪骣 -5 eV hr wet 琪琪8.617� 10( 1050 273K ) 桫桫 K

骣 2琪 2 骣 mm琪 -0.71 eV m m Bwet =琪188 exp = 0.371 桫 hr琪骣 -5 eV hr 琪琪8.617� 10( 1050 273K ) 桫桫 K

2 0.25mm (0.25mm) t= + =0.2655 hr = 15.93min 16min mm mm2 2.57683 0.371 hr hr

Step 10: Phosphorous Drive (18 min at 1050°C, goal of 0.3-0.5 μm junction depth and surface concentration of 5x1019cm-3):

Q 6.1711014 N(0)    4.9951019 cm 3 Surface concentration, 11 Dt2   4.85910

1/ 2 1   N(0)   4.9951019  2 x  2 Dt ln   2 4.8591011 ln   0.407 m j 2      16    N B    1.0010 

2 骣 2 cm-3.68 eV -14 cm D2 = 4.7 exp琪 = 4.4991 10 琪 -5 s 桫(8.617� 10eV / K )( 273 1050) s 2 骣 -14 cm骣 s -11 2 D2t2 = 琪4.4991 10琪 18min*60 = 4.859 10 cm 桫 s 桫 min Q6.171 1014 cm- 2 N(0)= = = 4.995 1019 cm- 3 Surface concentration, -11 2 p D2 t 2 p 创4.859 10 cm

1/ 2 骣轾N(0) x= 2 D t ln j 2 2 琪犏桫臌NB

16 -3 NB = 10 cm (assumed constant).

1 19- 3 2 -11 2 轾骣4.995 10 cm xj = 2 4.859� 10 cm 犏 ln琪 16- 3 0.407 m m 臌桫1.00 10 cm

N(0) = 4.995 x 1019 cm- 3

xj = 0.407m m

Lab 5 Calculations – Steps 11-15: A temperature of 1050°C and deposition time of 19.8 minutes were selected to perform the gate oxidation. The Deal-Grove model for dry oxide growth (higher quality) was used to determine the necessary time from the desired thickness, tox = 40nm, and temperature. τ was 0 because the gate oxide was to be grown on a bare silicon wafer.

Step 12: Oxidation (goal of 0.040μm):      B   m   2.01eV m  7.8106 exp   0.17179        A   hr   5 eV  hr dry  8.617 10 T 1050  273K    K  

     m2  1.21eV m 2 B  665 exp   0.01634 dry  hr    eV   hr    8.617 105 1050  273K    K  

0.04m 0.04m2 t    0.3307hr  19.8min  19 min,51s m m 2 0.17179 0.01634 hr hr

Step 12: Capacitance of oxide layer: A C   , where C = capacitance, A = surface area of capacitor, t = thickness of t

-12 dielectric, ε = εrε 0 = permittivity, and ε0 = 8.854x10 F/m. For SiO2, εr = 4.5.

12 2 6 C  4.58.854 10 F / m 4 F  1m  10 F  2 F    9.96 10    9.96 10 9 2     2 A t 40 10 m m 100cm   1F  cm

Step 15: Device Testing Diodes By taking the logarithm of the diode equation (in the forward bias region, so that the -1 term can be neglected), the equation becomes

v / nV i  I s e v ln(i)   ln(I s ) nVT

Where VT = 25.2mV at room temperature. Solving simultaneous equations for two I-V curves can provide the values for n and IS. Figures 4, 5, and 6 show the I-V characteristics for the diodes.

BJT2,1 Diode I-V Characteristics

) 0.01 A (

t n e r r u 0.005 C

0 -25 -20 -15 -10 -5 0 5 10

-0.005 Voltage (V)

Figure 4: BJT Diode Characteristics.

NMOS 40x80 Row 1 Col 2 Diode I-V Characteristics

0.03 ) A

( 0.02

t n e r r

u 0.01 C

0 -25 -20 -15 -10 -5 0 5 10 15

-0.02 Voltage (mV)

Figure 5: NMOS 40x80 Diode Characteristics.

NMOS 5x10 Row 1 Col 2 Diode I-V Characteristics

0.01 ) A (

n 0.005 e r r u C 0 -25 -20 -15 -10 -5 0 5 10 15

-0.005

-0.01 Voltage (mV)

Figure 6: NMOS 5x10 Diode Characteristics.

An example calculation is shown below, that of the BJT2,1 diode, with values taken from the graph: 5 ln(0.01437)   ln(I )      (1) n  0.0252 S 4 ln(0.002505)   ln(I )    (2) n  0.0252 S n  22.72

Substituting n=104.5 into equation (1): 5 ln(0.01437)   ln(I ) 22.72 0.0252 S 6 I S  2.3210 A The other two diodes were solved in the same manner. The breakdown voltage of the reverse-biased diodes is the point in the graph where the curve’s slope changes in negative bias. The results for all diodes are shown in Table 1.

Table 1: Diode device characteristics. BJT2,1 Row1 Col2 NMOS 40x80 Row1Col2 NMOS 5x10 Row1Col2 n 22.72 n 83.89 n 52.16 -6 -4 -6 IS 2.32x10 A IS 5.16x10 A IS 7.44x10 A

Vbr -17mV Vbr -16.2mV Vbr -16.7mV

TLM Measurement i) The slope of the Voltage versus Current graph for each length of the TLM gives the resistance (Figure 7).

TLM3 Row 2 Col 2 - 160um Post-Anneal

y = 594.42x - 0.0357 15 R2 = 0.9999

5 ) V (

g 0 a t l -0.03 -0.02 -0.01 0 0.01 0.02 0.03 o V -5

-20 Current (A)

Figure 7: Sample of Resistance Calculation for Post-Annealed TLM.

V=IR, so R = slope = 594.42Ω

ii) When all of the resistance values for the different lengths of TLM are plotted against the ratio of L/W, the slope of the graph becomes sheet resistance as seen in Figure 8 below.

Figure 8: Schematic of resistance properties discoverable by TLM.

With a width W = 100μm, the L/W values could be found to create this type of graph (Table 2). Table 2: Data used for Resistance Properties Chart of Post-Annealed TLM3. Length # L (microns) R (Ohms) L/W 1 10 72.729332 0.1 2 20 104.101532 0.2 3 40 169.87207 0.4 4 80 302.090881 0.8 5 160 594.421143 1.6

This information is used in Figure 9 to determine more resistance characteristics.

Resistance Properties Chart - TLM3 Post-Anneal

600 y = 348.12x + 32.812 R2 = 0.9992 500 )

s 400 m h O ( 300 R

0 -0.5 0 0.5 1 1.5 2 L/W (unitless)

Figure 9: Sample of Resistance Properties Chart for Post-Annealed TLM3.

RS = Sheet Resistance = Slope = 348.12Ω/square

(iii) The contact resistance can be found by finding the y-intercept of the line. y  348.12x  32.812  348.12(0)  32.812  32.812  2RC

RC  16.406 iv) To find the contact resistivity, the following equation can be used:

C RC  , so C  RC LTW LTW

As shown in Figure 8, the transfer length, LT can be found by solving for the x-intercept.  2L y  0  348.12x  32.812 , solving for x gives x  T  0.09425 , so L  4.71m W T

4 4 2 Thus, C  RC LTW  16.4064.7110 cm10010 cm  0.000077cm

This same process was used to find the resistance properties for all of the TLMs after annealing (Table 3). Table 3: Resistance Properties of TLMs after annealing. TLM1 (NMOS TLM2 (PMOS TLM3 (P-well) source/drain) source/drain) length Resistance Length Resistance Length resistance 10μm 471.43Ω 10μm 381.78Ω 10μm 264.79Ω 20μm 690.90Ω 20μm 406.60Ω 20μm 349.21Ω 40μm 1170.20Ω 40μm 494.18Ω 40μm 449.22Ω 80μm 2192.62Ω 80μm 812.74Ω 80μm 841.11Ω 160μm 4260.17Ω 160μm 1627.44Ω 160μm 1615.54Ω

Sheet Resistance, RS 699.14 Ω/square 957.39 Ω/square 348.12 Ω/square

Contact Resistance, RC 104.68Ω 49.68104.68Ω 16.406Ω

Contact Resistivity, ρC 0.001561 Ω-cm2 0.000258 Ω-cm2 0.000077 Ω-cm2

NMOS and PMOS Transistors In NMOS and PMOS Transistors, the I-V characteristics follow the equation 1 W I=m C轾2( V - V) V - V 2 , D2 oxL 臌 GS T DS DS

Where ID = current, μ = carrier mobility, Cox = oxide capacitance, W and L = geometric

properties, VGS = gate voltage, VT = threshold voltage, and VDS = applied voltage across

transistor. These curves (ID vs. VDS for differing VGS) can be seen in the summary section. This equation can be rearranged to:

1 1 骣1 W 2 1 W 2 and setting K= m C . (ID) =琪 m C ox[ V GS - V T ] ox 桫2 L 2 L

1/2 1/2 By plotting ID vs. VGS, the slope of the curve can be calculated as K , which can be

used to determine the value of μCox. An example can be seen in Figure 10.

ID1/2 vs. VGS for PMOS 10x40, Row 3 Col 3

0 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 -0.005 ) 2 /

1 y = 0.0043x + 0.0053

A 2 -0.01 (

R = 0.9965 2 / 1

t -0.015 n e r

r -0.02 u

C -0.025

-0.03 Gate Voltage (V)

ID Curve K determination Linear (K determination)

Figure 10: ID1/2 vs. VGS for PMOS 10x40, Row 3 Col 3.

The slope of this curve is K1/2 = 0.0043A1/2/V, therefore

2 L  A1/ 2  40m S   4 Cox  2K  20.0043   1.4810 W  V  10m V The threshold voltage can also be found by finding the x-intercept of this equation:

1 1 骣1 W 2 2 , since ID = 0, VT = VGS (ID) =琪 m C ox[ V GS - V T ] 桫2 L y  0  0.0043x  0.0053 x  VT  1.23V The same process was used to find the values for the other PMOS transistors and the NMOS transistors, though the NMOS transistor data could not be trusted, just like all other n-type devices (Figure 11).

ID1/2 vs. VGS for NMOS 10x80 Row 2 Col 2

0.122 y = 1.041E-03x + 1.065E-01 R2 = 9.962E-01 0.121 ) A

( 0.12

n 0.119 e r r 0.118 u C 0.117

0.115 0 2 4 6 8 10 12 14 16 Gate Voltage (V)

ID Characteristics K Determination Linear (K Determination)

Figure 11: ID1/2 vs. VGS for NMOS 10x80, Row 2 Col 2. -5 According to the same calculation process, μCox = 1.734x10 S/V and VT = -102.3V. This is obviously wrong because the threshold voltage should be positive and should be between 9-12V. However, the data is worthless for the NMOS transistors, so this result should have been expected. Table 4 shows the calculated values for μCox and VT that were produced by the computer program. Don’t trust the NMOS values.

Table 4: Transistor Characteristics.

Width (microns) Length (microns) K (S/V) VT (V) μCox (S/V) PMOS 5 10 -0.00405 -1.54 -0.0162 5 20 -0.005 -1.17 -0.04 5 40 -0.00838 -1.53 -0.13408 10 20 -0.00388 -1.57 -0.01552 10 40 -0.0054 -1.58 -0.0432 10 80 -0.00778 -1.58 -0.12448 20 80 -0.00486 -1.43 -0.03888 40 80 -0.00337 -1.45 -0.01348

NMOS 5 10 0.000529 0.0000258 0.002116 5 20 0.000155 0.0149 0.00124 5 40 0.000255 0.1588 0.00408 10 20 0.000694 -0.00313 0.002776 10 40 0.000237 0.0133 0.001896 10 80 0 0 0

20 80 0 0 0 40 80 0.000112 0.031 0.000448

As the table shows, the PMOS threshold voltages and μCox values stay relatively consistent, whereas the NMOS values are all over the place. Where the computer couldn’t calculate the correct values (as in 10x80, the example calculation) it printed a 0. The averages for each can be seen in Table 5. Table 5: Average transistor characteristics.

VT Avg. μCox Avg. (V) (S/V) PMOS -1.48125 -0.05323 NMOS 0.026862 0.0015695

MOS capacitors The formula for the capacitance of MOS capacitors is as below:   A A 0 rSiO2 Cox   tox tox

Where A = contact area and tox = oxide thickness

The relative permittivity of silicon dioxide = 4.5. The desired gate oxide thickness is tox = 40x10-9m, but the measured oxide thickness was 507Å=5.07x10-8m. The capacitance based on measured oxide thickness:

12 2 C  4.58.85410 F / m 4 F  1m  8 F    7.8610    7.86 10 A t 5.07 10 8 m m 2 100cm  cm 2

Collected Data and Process Specifics: Below are the material specifics and the process specifics for lab work this semester (Underlined information was blank in the process traveler and has been filled in with the

28/55 Final Lab Report Group #7 EE 432 Hunt, Mitch Due: 5-3-07 Jorgensen, Danny Yong, Ket-Bing Brown, Jonathon specific process information). This section also contains the charts needed when oxide thicknesses and sheet resistances were measured.

Starting Material: Orientation: <100> Dopant: n-TYPE, Phosphorous Resistivity: 2.654 ohm*cm Diameter: 3 inches Thickness: 350 microns Lot ID: 032110 Wafer Count: Device Wafers: 5 Test Wafers: 3

1. Field Oxide – 1/25/07 Standard Clean: See Traveler Wet Oxidation:

Push: Ambient: 0.3 slpm dry N2 Temp: 800°C Rate: 1 inch every 15 seconds

Ramp Up: Ambient: 0.3 slpm dry N2 Final Temperature: 1025°C Elapsed Time: 15 min 30s Bubbler On: Temperature: 1025 °C

Bubbler N2: 200 sccm - switch to vent

Oxidation: Ambient: 200 sccm bubbler N2 – switch to tube Temperature: 1025°C Time: 22 min 40s Bubbler Off: Power: off 29/55 Final Lab Report Group #7 EE 432 Hunt, Mitch Due: 5-3-07 Jorgensen, Danny Yong, Ket-Bing Brown, Jonathon

Bubbler N2: off – switch to vent

Ramp Down: Ambient: 0.3 slpm dry N2 Temp: 800°C Elapsed Time: 51 min

Pull: Ambient: 0.3 slpm dry N2 Temp: 800°C Rate: 1 inch every 15 seconds

2. Pattern for P-Well – Mask 1 – 2/1/07 Pattern Photoresist Spin HMDS: 4000 rpm for 40 seconds Spin photoresist: AZ5214 photoresist: 4000 rpm for 40 seconds Prebake: 90 °C for 25 minutes Expose: 90 seconds Develop: MIF-300 developer for 60 seconds Cascade rinse: 3 minutes Dry: Inspect: Postbake: 120 °C for 15 minutes SiO2 Etch & Photoresist Strip BOE: 6.5 minutes Cascade rinse: 3 minutes Acetone #1: 3 minutes Acetone #2: 3 minutes Methanol: 1 minute Cascade rinse: 3 minutes Spin rinse/dry:

3. Boron Deposition for P-Well – 2/8/07 Standard Clean: 30/55 Final Lab Report Group #7 EE 432 Hunt, Mitch Due: 5-3-07 Jorgensen, Danny Yong, Ket-Bing Brown, Jonathon

See Traveler Boron Deposition

Push Ambient: 0.3 slpm dry N2 Temperature: 850°C Rate: 1 inch every 15 seconds

Recovery Ambient: 1 lpm N2 + 1 lpm O2 Temperature: 850°C Time: 20 minutes

Source Ambient: 1 lpm N2 + 1 lpm O2 + 40 sccm H2 Temperature: 850°C Time: 2 minutes

Soak Ambient: 2 lpm N2 Temperature: 850 °C Time: 36 minutes, 40 seconds

Pull Ambient: 2 lpm N2 Temperature: 850°C Rate: 1 inch every 15 second Deglaze: BOE 2 minutes Cascade rinse: 3 minutes Spin rinse/dry

4. P-Well Drive (Performed by lab instructors after week of Step 3) P-Well Low-Temperature Oxidation (LTO) and Boron Drive Bubbler on: Temperature: 98°C

Bubbler N2: 200 sccm—switch to vent

Push: Ambient: 0.3 slpm dry N2 Temperature: 800°C Rate: 1 inch every 15 seconds

LTO: Ambient: 200 sccm bubbler N2 Bubbler switch to tube 31/55 Final Lab Report Group #7 EE 432 Hunt, Mitch Due: 5-3-07 Jorgensen, Danny Yong, Ket-Bing Brown, Jonathon

Temperature: 800°C Time: 30 minutes Bubbler off: Power: off

(If not used further) Bubbler N2: off — switch to vent

Pull: Ambient: 0.3 slpm dry N2 Temperature: 800°C Rate: 1 inch every 15 seconds Deglaze: BOE 2 minutes Cascade rinse: 3 minutes Spin rinse/dry

Push: Ambient: 0.3 slpm dry N2 Temperature: 800°C

Ramp up: Ambient: 0.3 slpm dry N2 Final temperature: 1150 °C Elapsed time: 26 minutes

Oxidation: Ambient: 200 sccm bubbler N2 switch to tube Temperature: 1150 °C Time: 8.5 minutes

Drive: Ambient: 0.3 slpm dry N2 Temperature: 1150 °C Time: 5 Hours

Ramp down: Ambient: 0.3 slpm dry N2 Final temperature: 800°C Elapsed time: 83 minutes

Pull: Ambient: 0.3 slpm dry N2 Temperature: 800°C Rate: 1 inch every 15 seconds Measured oxide thickness Table 6: Oxide thicknesses after p-well deposition and drive. Wafer Avg. oxide thickness St. Dev. of oxide thickness

TW1 2622 Å  = 16 Å TW2 3445 Å  = 10 Å TW3 3394 Å  = 19 Å

5. Pattern for P-MOS Source/Drain – Mask 2 – 2/15/07 Pattern Photoresist Spin HMDS: 4000 rpm for 40s Spin photoresist: AZ5214 photoresist: 4000 rpm for 40s Prebake: 90 °C for 25 min Expose: 90s Develop: MIF-300 developer for 60s Cascade rinse: 3 min Dry: Inspect: Postbake: 120 °C for 15 min SiO2 Etch & Photoresist Strip BOE: 10 min Cascade rinse: 3 min Acetone #1: 3 min Acetone #2: 3 min Methanol: 1 min Cascade rinse: 3 min Spin rinse/dry:

6. Boron Dep. For PMOS Source/Drain (Performed by lab instructors after week of Step 5) Standard Clean: See Traveler Boron Deposition

Push Ambient: 0.3 slpm dry N2

Temperature: 850°C Rate: 1 inch every 15s

Recovery Ambient: 1 lpm N2 + 1 lpm O2 Temperature: 850°C Time: 20 min

Source Ambient: 1 lpm N2 + 1 lpm O2 + 40 sccm H2 Temperature: 850°C Time: 2 min

Soak Ambient: 2 lpm N2 Temperature: 850 °C Time: 50 minutes

Pull Ambient: 2 lpm N2 Temperature: 850°C Rate: 1 inch every 15s Deglaze: BOE 2 min Cascade rinse: 3 min Spin rinse/dry:

7. Boron Drive – 2/22/07 P-Well Low-Temperature Oxidation (LTO) and Boron Drive Bubbler on: Temperature: 98°C

Push: Ambient: 0.3 slpm dry N2 Temperature: 800°C Rate: 1 inch every 15s

LTO: Ambient: 200 sccm N2 through bubbler Temperature: 800°C Time: 30 min Bubbler off: Power: off 34/55 Final Lab Report Group #7 EE 432 Hunt, Mitch Due: 5-3-07 Jorgensen, Danny Yong, Ket-Bing Brown, Jonathon

(If not used further) Bubbler N2: off — switch to vent

Pull: Ambient: 0.3 slpm dry N2 Temperature: 800°C Rate: 1 inch every 15s Deglaze: BOE 2 minutes Cascade rinse: 3 minutes Spin rinse/dry

Push: Ambient: 0.3 slpm dry N2 Temperature: 800°C

Ramp up: Ambient: 0.3 slpm dry N2 Final temperature: 1085 °C Elapsed time: 20 min, 17s

Oxidation: Ambient: 200 sccm N2 through bubbler Temperature: 1085 °C Time: 12 min, 22s

Drive: Ambient: 0.3 slpm dry N2 Temperature: 1085°C Time: 30 min

Ramp down: Ambient: 0.3 slpm dry N2 Final temperature: 800°C Elapsed time: 63 min

Pull: Ambient: 0.3 slpm dry N2 Temperature: 800°C Rate: 1 inch every 15s

Measured oxide thickness Table 7: Measured oxide thicknesses after PMOS drive. Wafer Avg. oxide thickness St. Dev. of oxide thickness Color

TW1 3098 Å  = 23 Å Blue-violet TW2 2848 Å  = 16 Å Purple TW3 3501 Å  = 14 Å Blue-green

8. Pattern For NMOS Source/Drain – Mask 3 (Performed by lab instructors week after Step 7) Pattern Photoresist Spin HMDS: 4000 rpm for 40 seconds Spin photoresist: AZ5214 photoresist: 4000 rpm for 40 seconds Prebake: 90 °C for 25 minutes Expose: 90 seconds Develop: MIF-300 developer for 60 seconds Cascade rinse: 3 minutes Dry: Inspect: Postbake: 120 °C for 15 minutes SiO2 Etch & Photoresist Strip BOE: 10 minutes Cascade rinse: 3 minutes Acetone #1: 3 minutes Acetone #2: 3 minutes Methanol: 1 minute Cascade rinse: 3 minutes Spin rinse/dry:

9. Phosphorous Deposition – 3/2/07 Standard Clean: See Traveler Phosphorus Deposition

Push Ambient: 1 lpm N2

Temperature: 900°C Rate: 0.5 inch every 1 second

Source Ambient: 1 lpm N2 Temperature: 900°C Time: 14 minutes

Pull Ambient: 1 lpm N2 Temperature: 900°C Rate: 1 inch every 2 seconds Deglaze: BOE 2 minutes Cascade rinse: 3 minutes Spin rinse/dry

10. Phosphorus Drive – 3/2/07 Phosphorus Drive: Bubbler on: Temperature: 98°C

Oxidation: Ambient: 200 sccm N2 through bubbler Temperature: 1050 °C Time: 16 minutes

Drive: Ambient: 1.0 slpm dry N2 Temperature: 1050 °C Time: 18 minutes

Ramp down: Ambient: 0.3 slpm dry N2 37/55 Final Lab Report Group #7 EE 432 Hunt, Mitch Due: 5-3-07 Jorgensen, Danny Yong, Ket-Bing Brown, Jonathon

Final temperature: 800°C Elapsed time: 60 minutes

Pull: Ambient: 0.3 slpm dry N2 Temperature: 800°C Rate: 1 inch every 15 seconds Measure oxide thickness Table 8: Oxide thicknesses after NMOS source/drain drive. Wafer Avg. oxide thickness St. Dev. of oxide thickness TW1 2560 Å  = 25 Å TW2 3538 Å  = 21 Å TW3 4030 Å  = 19 Å

11. Pattern for Gate Oxide - Mask 4 – 3/22/07 Pattern Photoresist: Spin HMDS: 4000 rpm for 40 seconds Spin photoresist: AZ5214 photoresist: 4000 rpm for 40 seconds Prebake: 90 °C for 25 minutes Expose: 90 seconds Develop: MIF-300 developer for 60 seconds Cascade rinse: 3 minutes Dry: Inspect: Postbake: 120 °C for 15 minutes SiO2 Etch & Photoresist Strip: BOE: 10 minutes Cascade rinse: 3 minutes Acetone #1: 3 minutes Acetone #2: 3 minutes Methanol: 1 minute Cascade rinse: 3 minutes

Spin rinse/dry:

12. Gate Oxide – 3/22/07 Standard Clean: See Traveler Dry Oxidation:

Drive: Ambient: 1 slpm dry N2 Temperature: 1050 °C Time: 20 minutes

Ramp down: Ambient: 0.3 slpm dry N2 Final temperature: 800°C Elapsed time: 55 minutes

Pull: Ambient: 0.3 slpm dry N2 Temperature: 800°C Rate: 1 inch every 15 seconds

Measured oxide thickness Table 9: Measured oxide thicknesses after gate oxidation. Wafer Avg. oxide thickness St. Dev. of oxide thickness Color TW1 2666 Å  = 24 Å Pinkish

TW2 3613 Å  = 26 Å Blue-green TW3 507 Å  = 7 Å Silver

13. Pattern for contact vias – Mask 5 – 3/29/07 Pattern Photoresist: Spin HMDS: 4000 rpm for 40 seconds Spin photoresist: AZ5214 photoresist: 4000 rpm for 40 seconds Prebake: 90 °C for 25 minutes Expose: 90 seconds Develop: MIF-300 developer for 60 seconds Cascade rinse: 3 minutes Dry: Inspect: Postbake: 120 °C for 15 minutes SiO2 Etch & Photoresist Strip: BOE: 8.5 minutes Cascade rinse: 3 minutes Acetone #1: 3 minutes Acetone #2: 3 minutes Methanol: 1 minute Cascade rinse: 3 minutes Spin rinse/dry:

Measured resistance properties Table 10: Resistance measurements of wafers after contact via lithography. Wafer Sheet Resistance Resistance Resistivity

TW1 RS ~ 600 Ω/□ R = 127 Ω ρ = 0.023 Ω-cm

TW2 RS ~ 825 Ω/□ R = 184 Ω ρ = 0.0627 Ω-cm

14. Contact Metallization – 3/29/07 Metallization: System Used: BJD-1800 Metal Deposited: Aluminum Total thickness: 2500 Å

15. Metal contact pattern – Mask 6 – 4/5/07 Pattern Photoresist Spin HMDS: 4000 rpm for 40 seconds Spin photoresist: AZ5214 photoresist: 4000 rpm for 40 seconds Prebake: 90 °C for 25 minutes Expose: 90 seconds Develop: MIF-300 developer for 60 seconds Cascade rinse: 3 minutes Dry: Inspect: Postbake: 120 °C for 15 minutes Aluminum Etch & Photoresist Strip

PAN etch: 40 ml H3PO4 + 40 ml CH3COOH + 10 ml HNO3 + 10 ml H2O Etch Time: 9 minutes Cascade rinse: 3 minutes Acetone #1: 3 minutes Acetone #2: 3 minutes Methanol: 1 minute Cascade rinse: 3 minutes Spin rinse/dry: Sintering

Push: Ambient: 1 lpm dry N2 Temperature: 425°C 41/55 Final Lab Report Group #7 EE 432 Hunt, Mitch Due: 5-3-07 Jorgensen, Danny Yong, Ket-Bing Brown, Jonathon

Rate: 1 inch per second

Sinter: Ambient: 1 lpm dry N2 Temperature 425°C Elapsed time: 12 min

Pull Ambient: 1 lpm dry N2 Temperature: 425°C Rate: 1 inch per second

Summary and Discussion: (New information is slightly farther down) Past Summary Info When wet oxidation was done, it was done to conserve time, even though the quality of the oxide was much lower. For the gate oxidation, when a high-quality thin oxide needed to be grown, dry oxidation was used for its slower rate and better properties. The Deal- Grove model for dry oxidation was used to determine the oxidation time, though this model is not very accurate for thin films. The model underpredicts the time required to produce an oxide of a certain thickness. Thus, the oxide produced was thicker than predicted (Table 9 shows that the oxide on TW3 was 507 Å instead of 400 Å). No oxide was exactly the thickness that was predicted. This was due to furnace variation and the not-exact values of the coefficients in the Deal-Grove model.

Temperature control is always important for these labs. The wafers are pushed and pulled slowly when possible because oxide-silicon thermal expansion mismatch could cause wafer deformation as well as thermal shock. Another indication of the importance of temperature control was pulling the wafers out of the furnace before the deposition time had completed. This was done because while the wafers were being pulled, they were at a high enough temperature to still cause boron and phosphorous deposition. If the pull had been started after the deposition time, too much dopant would have been deposited.

In order to save time, the oxide growth and dopant drive were usually coupled. The drive required a high temperature, while the oxide growth required a high temperature and certain atmosphere. The water vapor atmosphere did not greatly affect the drive, so both processes were able to be performed together.

During the boron depositions and drives, more concerns arose in the form of potential damage to the silicon crystal. This was a concern because a layer of silicon boride forms during deposition. This layer has defects that can propagate into the silicon crystal during the boron drive if not addressed. This potential problem was eliminated by doing a low temperature oxidation. By oxidizing the silicon boride layer and the silicon-silicon boride interface these defects are eliminated.

No extreme processing problems were encountered in any step, though lining up the mask in the lithography step was very time-consuming. Most difficulties occurred due to the fine-tuning of the alignment marks. The rough alignment of the corners of the box was simple, but frustrating issues arose while trying to line up the cross inside the square. The biggest frustration was dealing with the slight shift due to air interference when bringing the aligned wafer into contact with the mask. The wafer had to be taken out of contact, re-aligned, and put into contact again.

New Summary Info Sintering was performed for 15 minutes at 425°C to create much better contacts of the aluminum. Prior to sintering, the atoms simply sit as a pile on top of the wafer. By heating the wafer, the atoms diffuse into each other and form a continuous contact. The quality of the contact increases greatly, as can be seen in Figures 12 and 13.

TLM3 Row 2 Col 2 - 160um Post-Anneal TLM3 Row 2 Col 2 - 160um Preanneal 20 20 15 15 10 10 ) ) 5 V V

0 a t a l -0.03 -0.02 -0.01 0 0.01 0.02 0.03 t o

l -0.015 -0.01 -0.005 0 0.005 0.01 0.015

V -5 o -5 V -10 -10

-15 -15

-20 -20 Current (A) Current (A)

Figure 12: TLM 3 (p-type diffusion) before (left) and after (right) anneal. A straight line indicates ohmic contacts.

TLM1 Row 2 Col 2 - 160um Pre-Anneal TLM 1 Row 2 Col 2 - 160um Post-Anneal

0.015 0.015

0.01 0.01 ) 0.005 ) 0.005 A A ( (

t t n 0 n

e 0 e r r r -20 -15 -10 -5 0 5 10 15 20 r -20 -15 -10 -5 0 5 10 15 20 u u

C -0.005

-0.01 -0.01

-0.015 -0.015 Voltage (V) Voltage (V)

Figure 13: TLM 1 (n-type diffusion) before (left) and after (right) anneal. A straight line indicates ohmic contacts. As can be seen in the Figures above, the n-type diffusions produced much lower quality devices than the p-type diffusions. This phenomenon held true for all devices, and was probably due to difficulties with the phosphorous deposition and drive.

The diodes tested were between the B-C junction of a BJT in the Row 1 Column 2 die, the D-S junction of the 40x80 NMOS in the same die, and the D-S junction of the 5x10 NMOS in the same die. I-V curves can be found on pages 19 and 20 in the calculations section, as well as the determination of Is, n, and Vbr. The diode curves show exponentially increasing current under forward bias (right side of graph) and a limited current until breakdown under reverse bias (left side of graph). The limited current in the

44/55 Final Lab Report Group #7 EE 432 Hunt, Mitch Due: 5-3-07 Jorgensen, Danny Yong, Ket-Bing Brown, Jonathon two NMOS transistors does not approach a steady value, this is most likely due to phosphorous diffusion problems experienced in the processing of the device.

The resistance characteristics (Sheet resistance, RS, and contact resistivity, ρC) of the TLMs can be found on in Table 4 on page 26 in the calculations section. Figure 14 shows the complete set of IV curves for all the resistors on TLM3 after annealing.

IV Curves for all Resistors in TLM3

n 0 e r

r -0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 0.05 u -5 C -10

-20 Voltage (V)

10um Resistor 20um Resistor 40um Resistor 80um Resistor 160um Resistor

Figure 14: IV Curves for TLM3.

As can be seen, by increasing the resistance length, the slope of the IV curve (Resistance) L decreased. This makes sense as R = r , so increasing L increases R. W

Figures 15, 16, and 17 show the resistance vs. L/W curves for TLM1, TLM2, and TLM3 respectively.

1600 y = 699.14x + 209.35

) 1400 2 s R = 0.997

m 1200 h

O 1000 (

c 800 n a

t 600 s i

s 400 e

0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 L/W (Unitless)

Figure 15: Resistance Properties Chart - TLM1 Post-Anneal, Row 2 Col 2.

1600 y = 957.39x + 99.366 R2 = 0.9998 )

s 1400 m

h 1200 O ( 1000 e c

n 800 a t s

i 600 s

e 400 R

0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 L/W (Unitless)

Figure 16: Resistance Properties Chart - TLM2 Post-Anneal, Row 2 Col 2.

600 y = 348.12x + 32.812 R2 = 0.9992 500 ) s 400 m h

O 300 (

0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 L/W (unitless)

Figure 17: Resistance Properties Chart - TLM3 Post-Anneal, Row 2 Col 2. Each TLM has different properties due to the doping type and profile of each device (TLM1 is n-type with contacts in the NMOS source/drain, TLM2 is p-type with contacts in the PMOS source/drain, and TLM3 is p-type with contacts in the p-well).

Figures 18-23 show ID vs. VDS characteristics for NMOS and PMOS transistors of gate length 5, 10, and 20 μm, respectively.

ID vs VDS Curves for NMOS 5x10

0.00003

0.000025

0.00002 ) A (

0.000015 D I 0.00001

0.000005

0 0 2 4 6 8 10 12 VDS (V)

VGS = 5V VGS = 6V VGS = 7V VGS = 8V VGS = 9V

Figure 18: IV Curves for NMOS 5x10, Row 3 Col 3.

ID vs. VDS Curves for NMOS 10x20

0.000016

0.000014

0.000012

0.00001 ) A (

0.000008 D I 0.000006

0.000004

0.000002

0 0 2 4 6 8 10 12 VDS (V)

ID vs. VDS Curves for NMOS 20x80

0.0006

0.0005

0.0004 ) A (

0.0003 D I 0.0002

0.0001

0 0 2 4 6 8 10 12 VDS (V)

ID vs. VDS Curves for PMOS 5x40

0 -12 -10 -8 -6 -4 -2 0 -0.0002

-0.0004

) -0.0006 A (

D I -0.0008

-0.001

-0.0012

-0.0014 VDS (V)

VGS = -8.00E+00 VGS = -7.00E+00 VGS = -6.00E+00 VGS = -5.00E+00 VGS = -4.00E+00

Figure 21: IV Curves form PMOS 5x40, Row 1 Col 2.

0 -12 -10 -8 -6 -4 -2 0 -0.00005

-0.0001

) -0.00015 A (

D I -0.0002

-0.00025

-0.0003

-0.00035 VDS (V)

Figure 22: IV Curves for PMOS 10x20, Row 1 Col 2.

0 -12 -10 -8 -6 -4 -2 0 -0.0001

-0.0002

-0.0003 ) A (

-0.0004 D I -0.0005

-0.0006

-0.0007

-0.0008 VDS (V)

Figure 23: IV Curves for PMOS 20x80, Row 1 Col 2.

The gate thickness and gate length control the magnitude of each I-V curve in this section. As all thicknesses are relatively the same for these labs, the gate length has the most important control of the curve. As shown in the PMOS figures (5, 10, 20 microns), all of the curves have the same general shape, but saturate at different levels based on the gate length. The 5-micron curves don’t saturate as clearly, most likely due to leaking currents through the gate. The NMOS transistors show that increasing the gate length decreases the saturation level for the I-V curve. Both the 5 and 10 micron gates are of the same basic shape, but the 20-micron gate is an anomaly. The curves are much smoother, there is only slight differentiation between the curves based on gate voltage, and there doesn’t seem to be a saturation current. In fact, this transistor seems to show more of a forward-biased diode behavior. This deviation is most likely due to the same phosphorous diffusion issues that plagued all of the n-type devices.

1/2 It was not realized that ID vs. VGS curves were supposed to be produced for each size of transistor, so only one was produced for each. They can be found in Figures 24 and 25.

ID1/2 vs. VGS for NMOS 10x80 Row 2 Col 2

0.122 y = 1.041E-03x + 1.065E-01 R2 = 9.962E-01 0.121 ) A

( 0.12

n 0.119 e r r 0.118 u C 0.117

0.115 0 2 4 6 8 10 12 14 16 Gate Voltage (V)

ID Characteristics K Determination Linear (K Determination)

Figure 24: ID1/2 vs. VGS for NMOS 10x80 Row 2 Col 2.

ID1/2 vs. VGS for PMOS 10x40, Row 3 Col 3

0 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 -0.005 ) 2 /

1 y = 0.0043x + 0.0053

A 2 -0.01 (

R = 0.9965 2 / 1

t -0.015 n e r

r -0.02 u

C -0.025

-0.03 Gate Voltage (V)

ID Curve K determination Linear (K determination)

Figure 25: ID1/2 vs. VGS for PMOS 10x40, Row 3 Col 3.

Once again, the n-type devices (NMOS) show awful properties when compared to the

PMOS devices. This is due to difficulties in the phosphorous deposition and drive. VT and μCox for each transistor and average values of VT and μCox can be found in Tables 4 and 5 on pages 26 and 27 in the calculations section. Figure 26 shows a die map with the correlating transistor dimensions (width x length in microns). 51/55 Final Lab Report Group #7 EE 432 Hunt, Mitch Due: 5-3-07 Jorgensen, Danny Yong, Ket-Bing Brown, Jonathon

Figure 26: Die map of transistor dimensions. Transistor characteristics can be found in Table 4 on page 26.

The PMOS transistors work well as they follow the characteristics they are supposed to. The NMOS transistors are awful and don’t approach any of the properties they are supposed to have. Information from Intel (http://www.eas.asu.edu/~vasilesk/EEE531/TeraHertzlong.pdf) points to threshold

52/55 Final Lab Report Group #7 EE 432 Hunt, Mitch Due: 5-3-07 Jorgensen, Danny Yong, Ket-Bing Brown, Jonathon voltages of 0.75V on the newest transistors and gate thicknesses of as low as 15nm. Obviously, these advances are vastly different than the 50.7nm gate oxide grown in lab and the ~1.5V threshold voltage of the devices. No information on μCox values could be found.

Cox was determined from C-V measurements of the n-type capacitors and p-type capacitors. The lab images are shown in Figures 27 and 28.

C-V Curve for P-Capacitor 1, Row 3 Col 4

1.40E-08 )

2 1.20E-08 m c / 1.00E-08 F (

e 8.00E-09 c n

a 6.00E-09 t i c

a 4.00E-09 p a 2.00E-09 C 0.00E+00 -15 -10 -5 0 5 10 15 Voltage (V)

Figure 27: C-V Curve for P-type capacitor 1 in the Row 3 Col 4 die.

C-V Curve for N-Capacitor 1, Row 3 Col 4

1.20E-07 ) 2 1.00E-07 m c /

F 8.00E-08 (

c 6.00E-08 n a t i

c 4.00E-08 a p

a 2.00E-08 C 0.00E+00 -15 -10 -5 0 5 10 15 Voltage (V)

Figure 28: C-V Curve for N-type capacitor 1 in the Row 3 Col 4 die.

According to the notes, the oxide capacitance (Cox) should be the maximum value in each capacitor (Table 11). Table 11: Measured capacitance by C-V curves. PC1Row3Col4 NC1Row3Col4 Capacitance: 1.25x10-8 Fcm-2 9.44x10-8 Fcm-2

Both values come relatively close (within an order of magnitude) to the predicted value

-8 2 of Cox (7.86x10 F/cm , see page 27 in calculation section). The predicted capacitance of the gate oxide was not expected to be exactly correct. The oxide, though slow-grown, is most likely not fully-dense and therefore didn’t have the exact characteristics of pure

1/2 In order to produce a wafer map, the K values (slope of ID vs. VGS curves) were recorded from the 10x80 PMOS transistor on every other die (Figure 29).

Figure 29: Wafer map of K values for 10x80 PMOS. These values, except for those in the second column, agree very well with the K values produced in Table 4 of the transistor section of the calculations on page 26 and are consistent across the wafer. The deviation in Column 2 is likely due to a defect in that area of the mask set as it only affects one portion of the wafer.

Images of the devices can be found in Appendix A.