First Individual Test. Grades Will Be Available on Friday , 11Th April

BACHELOR DEGREE IN Digital Circuits and Systems (CSD) TELECOMMUNICATIONS 3GM11 / 3GM12 4 April 2013 Josep Jordana Barnils - First individual test. Grades will be available on Friday , 11th April. - Questions about the exam: Tuesday 10:00-13:00; Friday 12:00-13:00, 15:00-17:00 - Part A: [3P]

1- Obtain the truth table of Z(A,B,C). 2- Obtain the Boolean expression of Z(A,B,C), as a product of maxterms. 3- Write the VHDL code of this circuit , in a behavioral way. 4- Explain the meaning of the noise margin of a standard TTL digital gate. What happens

if the output voltage (Vo) of a digital gate is in this range (VoLmax < Vo < VoHmin?)

Fig. 1 A simple combinational circuit

Part B: [3P]

5- Simplify the following logic equation: F(x,y,z) = x’y’z + xy’z’ + xy’z + xyz’ + xyz as a SOP. Indicate the different steps that you follow. 6- Express the following equation as a product of maxterms. F(x,y,z) = xy + x’z. 7- Draw the logic circuit corresponding to the Boolean function F(x,y,x) = xy + x’z by means of only NAND gates.

Part C: [3P]

8- Draw the block diagram of a comparator of 4 bits (COMP-4). Indicate the way the comparators of 1 bit (COMP-1) are instantiated. 9- Explain the different steps you have to do in order to do a gate level simulation of a combinational circuit with Quartus II. Which is the difference between a functional simulation and a gate-level simulation?

Part D: [1P] 10- a) Add the following 8 bit unsigned numbers: A = 0x7F, B = 0x01. Indicate the result in hexadecimal format and in decimal format. 11- b) Add the following 8 bit signed numbers: A = 0x80, B = 0x20. Indicate the result in hexadecimal format and in decimal format.