Verilog Blif T- Vpack VPR EXAMPLE at END of DOCUMENT

TOOL FLOW

Verilog – Blif – T- Vpack – VPR **EXAMPLE AT END OF DOCUMENT**

The description of the circuit can be written in Verilog and converted to BLIF, the file format which VPR accepts.

CONVERSION FROM VERILOG TO BLIF 1. Press START/Windows Key and select Run. Type in “cmd” in the 'Open:' slot and press OK. 2. In the directory where the verilog file is located, type “quartus_map .v” and press ENTER. 3. Quartus will make project files for the verilog file in the same directory where the verilog file is located. 4. Open “.qsf” in Wordpad and add the following text in bold as a single line at the end of the file:

set_global_assignment -name INI_VARS "no_add_ops=on;opt_dont_use_mac=on;dump_blif_after_lut_map =on"

These options will convert the verilog file into blif with LUT mapping.

5. Save and exit. 6. Back in command prompt (cmd) in the directory where the project files and the verilog file are located, type “quartus_map ” (without the “.v”). 7. A BLIF file should have been created in the same directory as where your verilog and project files are.

USING SIS 1.2 IN WINDOWS SIS gets rid of null errors. Run the SIS binary then type “read_blif ” “write_blif ”

ERRORS TO WATCH OUT FOR Null Error : This occurs when trying to use BLIF file directly from quartus. To correct, re write file through SIS as directed above.

Ground and Voltage (VCC) error: Delete ground and voltage lines in BLIF file.

WRITING OWN BLIF FILE If you write your own BLIF file, convert the text file to UNIX version before running T- V pack if using T-V pack on a UNIX machine. To do this,

1. Go to directory containing BLIF file 2. Type “pico .blif” 3. Press CTRL + O 4. Press ENTER 5. Press CTRL + X

BLIF file is ready to be used in T-V pack on UNIX machine.

RUNNING T-VPACK Get into the T-V pack directory and run the following code

“t-vpack .blif .net -no_clustering” For an FPGA with logic blocks containing 1 LUT and 1 Flip flop. n :- Name of BLIF file m :- Name that you wish to call output NETLIST file.

“t-vpack .blif .net -lut_size -cluster_size -inputs_per_cluster -clocks_per_cluster ” For an FPGA with a user specified number of LUTs. n :- Name of BLIF file m :- Name that you wish to call output NETLIST file. a :- number of inputs per LUT b :- Number of LUTs c :- Total Number of inputs d :- Number of different clocks that can be used by each logic block

ARCHITECTURE FILE FOR VPR See VPR manual

Things to note about architecture file: - There must be an adequate number of input and output pins to accommodate all inputs and outputs - There must be as many T_subblock lines as there are LUTs. - If the ARCH file is written in another operating system, not UNIX and VPR is being run on UNIX, convert the text file to UNIX version before running VPR. To do this, Go to directory containing ARCH file, Type “pico .arch” Press CTRL + O Press ENTER Press CTRL + X

ARCH file is ready to be used in VPR.

RUNNING VPR Get into the VPR directory and run the following code “vpr .net .arch .p .r”

Other parameters can be specified as directed by the manual. m :- Name of net list file n :- Name of architecture file a :- Name user wishes to call placement file to be produced b :- Name user wishes to call routing file to be produced

SAMPLE TOOL FLOW 1) Run the attached Verilog file “adder.v” through quartus as directed above 2) Run the project file produced “adder.qsf” through quartus again after making the changes as directed above to produce BLIF file, “adder.blif”. 3) The generated BLIF file needs to be edited for null errors to be accepted by T- Vpack. Put the file in the same directory as SIS and run SIS as directed above. To be totally confident, manually check for and delete all “null” lines left in the BLIF file after running SIS. 4) Delete ground and Voltage lines from edited BLIF file and save. (edited file attached as “adderedit.blif” 5) Run the edited BLIF file through T-Vpack specifying desired parameters. (do not forget to copy to UNIX version if T-Vpack is on a UNIX machine) 6) Run VPR as directed above with the output NETLIST file and an architecture file.