Tutorial #2

The objectives of this tutorial are for you to:

 Become familiar with the Digilent Spartan-3 Starter Board.  Specify the connections between your design's inputs and outputs and the pins on the Spartan-3 FPGA using a user-constraints file (a .ucf file).  Implement a schematic-entry design using the Xilinx ISE 8.2 tools.  Download the implemented design to the Digilent Spartan-3 Starter Board.

This tutorial uses the design created in Tutorial #1.

This tutorial has the following sections:

 Setting up the Digilent Spartan-3 Starter Board.  Identifying the Spartan-3 pin names associated with the Digilent Spartan-3 Starter Board I/O devices and connectors.  Specifying I/O pin connections using a .ucf file.  Implementing a schematic-entry design with the Xilinx ISE 8.2 tools.  Downloading a design to the Digilent Spartan-3 Starter Board.

Setting up the Digilent Spartan-3 Starter Board.

Your Digilent Spartan-3 Starter Board comes with an FPGA board, PC parallel port cable, and a power supply. Below is a picture of the Digilent Spartan-3 Starter Board that you will be using. It shows where the power supply and parallel port cables should be attached. To setup your Spartan-3 board, connect the cables as shown above, plug in the power supply, and connect the PC parallel port cable to the parallel port connector on the back of the PC. When connecting the PC parallel port to the Spartan-3 board, be sure to connect it to Jumper J7 using the orientation shown above with the 2.8V label facing toward the middle of the Spartan-3 board. You should also confirm that the board's jumpers are installed in their original, shipped configurations as shown in the yellow circles above.

For more information about the Digilent Spartan-3 Starter Board, see the following:

 Digilent Spartan3 Starter Kit Board Reference Manual  Digilent Spartan3 Starter Kit Board Schematics

By default, the Spartan-3 board should behave as described below when the power supply cable is connected. If you ever suspect that some of these FPGA pins, switches, push-buttons, LEDs, or 7- segment LED displays are not functioning properly, you can simply power down and then power up the board and check to see if the board is working well.

 When rightmost switch (SW0) on the board is in the "down" position, the four 7-segment displays right above the switches should display the numbers 0 through 9 repeatedly.  When rightmost switch (SW0) on the board is in the "down" position, each time a push-button switch on the lower left of the board is depressed, one of the 7-segment displays should go blank.  As each of the switches on the lower right of the board is moved to the "up" position, the corresponding LED above the push-button switches on the lower left of the board should be lit. For all the switches except the right-most switch, the 7-segment LED displays should continue to display the numbers 0 through 9 repeatedly. Identifying the Spartan-3 pin names associated with the Digilent Spartan-3 Starter Board I/O devices and connectors.

When you are specifying the connections between your schematic design's I/O markers and the pins of the Spartan-3 FPGA, you need to know the name of the FPGA pin and what the FPGA pin is connected to. As you can see on the Spartan-3 board, there are many devices and connectors (LEDs, switches, push-buttons, 7-segment displays, VGA, RS-232, PS/2, expansion connectors, etc.). All of these devices and their connections to the Spartan-3 FPGA are documented in the Digilent Spartan3 Starter Kit Board Reference Manual. However, many of the pin names for various devices can be read directly from the board itself. Refer to your board and look at the circled sections shown below.

For example, the right-most slider switch is labeled SW0 (F12) and the left-most push-button switch is labeled BTN3 (L14). The first token in these labels is the name typically used in schematics to refer to these pins. The second token in parenthesis is the name of the FPGA pin that is connected to this device. For example, the right-most slider switch typically called SW0 in a schematic and its FPGA pin name is F12. The FPGA pin names are used when associating I/O markers in a schematic design with a particular FPGA pin. This association is usually done using a user-constraints (.ucf) file as described in the next section.

Specifying I/O pin connections using a .ucf file.

In this section, you will add a user-constraints (.ucf) file to the two-input AND project you created in Tutorial #1. The .ucf file will specify which FPGA pins to connect to the "A", "B", and "C" I/O markers.

In general, it seems to be a good idea to copy the directory of a previous part to a new directory and continue with the copy. This can be important if you mess something up in the new part of the experiment, and need to revert to the beginning without redoing the previous experiment. Accordingly, create a copy of the tutorial_1 directory and name it tutorial_2. Start up the Xilinx ISE 8.2 project manager and open the my_and project you copied into the tutorial_2 directory. Select the "Processes" and "Sources" panes on the left side of the project manager window and highlight (click once) "my_and_top (my_and_top.sch)" in the "Sources" pane as shown below. If the "Synthesize- XST" isn't green, double click it to make sure the synthesis files are up-to-date.

In the "Processes" pane, under "User Constraints", double-click upon the "Edit Constraints (Text)" option. This will bring up the following window.

Click "Yes" and the "my_and_top.ucf" file will be added to your project and you can enter your UCF directives into this file using the right side of the project manager window. Enter the contents of the UCF file shown below into your project's UCF file and then click on the save icon ( ) to save your UCF file.

Proceed to the next section to implement your project.

Implementing a schematic-entry design with the Xilinx ISE 8.2 tools.

Select the "Processes" and "Sources" panes on the left side of the project manager window and highlight (click once) "my_and_top (my_and_top.sch)" in the "Sources" pane as shown below.

Double-click on the "Implement Design" option in the "Processes" pane. This will take your synthesized design and implement it for the Spartan-3 FPGA using the user constraints you just entered into the UCF file. If all goes well, green checks should appear in the "Processes" pane after the "Translate", "Map", and "Place and Route" entries as shown below.

If the green checks do not appear, then either a warning or an error occurred during the implementation process. When this happens, check the information available in the "Console", "Errors", and "Warnings" views available by clicking on the appropriate tab near the bottom left of the project manager window as shown below.

Sometimes Xilinx gets confused and produces errors that seem to be incorrect and/or does not rebuild a design properly. When you suspect this has happened, I suggest selecting {Project} {Cleanup Project Files} from the project manager window. This option deletes the temporary and output files that are created during the synthesis and implementation processes, forcing Xilinx to start from the beginning. After cleaning up the project files, re-synthesize (and/or re-implement) your design.

Once your project implementation is successful, proceed to the next section to download your project to the Spartan-3 board.

Downloading a design to the Digilent Spartan-3 Starter Board.

In the "Processes" pane, double-click on the "Generate Programming File" option to generate a down-loadable version of your project for the Spartan-3 board. When the programming file has been successfully generated, green checks will appear in the "Processes" pane next to "Generate Programming File" and "Programming File Generation Report" as shown below. For some reason, there may be no indication that the program is running, but you can watch the "Transcript" pane to see what is going on.

Once the programming file has been generated successfully, you are ready to program the device. However, one parameter needs to be set in order to avoid an annoying warning later. Right click on "Generate Programming File" and select "Properties". The window below should appear:

Select "Startup Options" and set "FPGA Start-Up Clock" to "JTAG Clock" as shown below:

Click "OK" to confirm your choice.

Now double-click on the "Configure Device (iMPACT)" option under "Generate Programming File" in the "Processes" pane. This will start the iMPACT program, which will be used to set the design into the FPGA.

Once iMPACT starts, you will see the following: Select the "Configure devices using Boundary-Scan (JTAG)" option and select "Automatically connect to a cable and indentify Boundary-Scan Chain". Click "Finish". iMPACT will find two devices on the Spartan 3 board: the xc3s200 FPGA and the xcf02s serial ROM. The program automatically asks for a programming file for each device, and, unfortunately, may drop the file selection window right over the top of the schematic for the chain. Move the window so that you can see the chain of devices to be programmed.

The first device, the xc3s200, should use my_and_top.blt as shown below: In the automatic mode, another file selection window will pop up: You do not want to program the second device at this time, so click "Cancel" which should bring you back to the main iMPACT window similar to the one below.

Right-click on the on the Xilinx chip on the left (it should turn green if it isn't already). Double-click "Program" from the "iMPACT Processes" window shown above.

Click "OK" in the "Programming Properties" window to accept the defaults, and wait while your project design is downloaded to the Spartan-3 board. If the programming is successful, a window similar to the one below should appear.

If for some reason programming was not successful, try programming the board a few more times.

Once you have successfully programmed your board, try the push-buttons and check the LED to verify that your AND gate and its connections to the push-buttons and LED are working as expected.