University of California s14

EECS 140 FINAL EXAM Spring 01 NAME and SID

Note: Use the device parameters given in the class handout “Device Parameters & SPICE Models”.

1) Your friend has designed a two stage Miller-compensated CMOS op-amp. She has already added a compensation capacitor Cc that works for her application. The compensated op-amp has a low frequency pole at 1Mrad/sec, a low frequency gain of 1000, and a second pole at 100Mrad/sec. There are several other poles at frequencies around 3Grad/sec. a. Draw a Bode plot (magnitude and phase) of the compensated open-loop amplifier b. Is this amplifier stable in unity gain feedback? If yes, estimate the phase margin. c. Is this amplifier stable with a feedback factor of 0.1 (gain of 10)? If yes, estimate the phase margin. d. If you want to use the amplifier in unity gain feedback with a phase margin of at least 45 degrees, which capacitor would you change (C1, C2, or Cc), and roughly how much would you need to change it? 2) If you had a telescopic cascode amplifier with the same open loop poles and gain as described above, and you wanted a phase margin of 45 degrees in unity gain feedback, where would you add capacitance to achieve it, and how much would you need to add? What would your new unity gain frequency be?

of 6 3) For the amplifiers below, a. Calculate Gm in terms of gm, Rs, and ro for the amplifier on the left b. Assume that gm ro is large (i.e. gm is large compared to 1/ro) and write Gm in terms of gm and Rs only c. If we put a capacitor Cs in parallel with Rs (right figure), write down the impedance of the parallel combination, Zs d. Calculate Gm(s). You should find a pole and a zero. e. Plot the magnitude of Gm, clearly labeling the low and high-frequency values and the pole/zero location V V DD DD

V V BP BP V V o o V V i i C R S S R S

of 6 For the current-mirror amplifier on the left below, calculate the transfer function in terms of gm, ro, CL and Cgs. Show that there are two poles. For the differential pair, calculate the transfer function, showing that there are two poles and a zero. You may ignore all capacitances except CL and Cgs.

V V DD DD

M2 M3 M2 M3 V V o o

V V V V i M1 BN M4 C i+ M1 i- M4 C L L

of 6 4) For the following questions, state which amplifiers would NOT be appropriate, and give a very brief explanation of why.

a. An audio amplifier driving a fairly low resistance load. b. An amplifier with inputs near the top rail, and outputs near ground c. An amplifier with outputs that need to swing close to both rails

Amplifier choices: i) NMOS input folded cascode ii) PMOS input folded cascode iii) NMOS input 2 stage Miller compensated iv) PMOS input 2 stage Miller compensated v) NMOS input telescopic cascode vi) PMOS input telescopic cascode

of 6 5) For the following switched-capacitor circuit, assume that all switches are ideal unless otherwise stated, that the digital inverters are ideal, and that phi1 transitions slightly before phi1a. a. Calculate the value of Vx and Vy when phi1 and phi1a and Va and Vb are high, and phi2 is low (time t1). b. Calculate the value of Vx and Vy after phi1 and phi1a and Va and Vb have been brought low (everything low, time t2) c. Calculate the value of Vx and Vy after phi2 and Vb have gone high (time t3) d. Draw the waveforms for Vx and Vy below, assuming Vin = 0.5 volts. Use RC charging time constants of roughly 1 microsecond for all analog values

Vx 2 V

1pF 3pF V b V a

Phi1a Phi2

Vin 1 V

5 us t1 t2 t3

of 6 7) Consider the Folded Cascode Amplifier shown below.  Neglect extrinsic parasitic capacitances in parts a) through h)  Neglect body effect a) Determine the minimum and maximum output voltages, Vomin and Vomax, that are required to operate the amplifier in its high gain regime. b) Change W of M17 to maximize the output range while keeping all devices in the forward active region (assume maximum output current). Calculate the corresponding maximum output voltage Vomax’. Verify that M13 and M15 are indeed in saturation c) Calculate the amplifier’s differential mode transconductance Gm. d) Calculate the amplifier’s output resistance Ro. e) Calculate the low frequency differential gain Adm in dB. f) Calculate the unity gain frequency fu of the circuit for CL=5pF. Assume that all non-dominant poles are at higher frequencies than fu. g) Estimate the pole frequency fp2 caused by the cascode device M11 (node V1). h) Estimate the pole frequency fpm and the zero frequency fzm caused by the current mirror M13-M16. i) Estimate the low frequency input capacitance Ci2 looking into node Vi2. Include the gate to drain overlap capacitance of M2 in your analysis – neglect the parasitic junction capacitances. Hint: Include the Miller effect at node V2 and assume that CL is an open circuit for the frequencies of interest.

M5 M4 M3 M15 M16

W=200u W=200u W=200u W=100u W=100u L= 2u L= 2u L= 2u L= 2u L= 2u

M17 M13 M14

M1 M2 W=10u W=100u W=100u L= 2u L= 2u L= 2u Vi1 Vi2 + VDD W=100u W=100u Vo 5V + 200uA L= 2u L= 2u - - CL M6 M11 M12 W=5u W=50u W=50u L= 2u L= 2u L= 2u

M7 M8 M9 M10 W=100u W=100u W=100u W=100u L= 2u L= 2u L= 2u L= 2u