Mietec Design Kit User's Guide Page 1

* * _____ * / # # \ * / \ * | # # # # | * | | * | # # # # | * \ / * \_#_#_/ * * *

E U R O P R A C T I C E

M I E T E C D E S I G N K I T

U S E R ' S G U I D E

for Mentor Graphics version 8.2

Date: 30-JUN-1993

Author: Herman Witters, IMEC div INVOMEC

I N T R O D U C T I O N ======

The purpose of this text is not to teach the user to work with the Mentor Graphics version 8 software, but it is a guide to use the Mietec design kit.

The following topics are covered :

The Mietec Design Environment

Design Creation and Configuration

Digital Simulation

Analog Simulation

Physical Layout

The Mietec Library Tree

Creating Design Viewpoints

Creating a Standard Cell Layout

Layout Guidelines

Preparing for Processing Mietec Design Kit User's Guide Page 2

"Design Creation and Configuration", "Digital Simulation" and "Analog Simulation" are not discussed in depth because the symbols and simulation models in the Mietec design kit are completely compatible with the Mentor Graphics design flow.

"Physical Layout" is discussed in terms of "How to do it ?" in the sections "Creating a Standard Cell Layout".

Section "The Mietec Library Tree" is a little bit lost in the middle of this. Nevertheless it is important that a designer understands what is behind all the files and models he is using.

Section "Creating Design Viewpoints" is an important section because it explains how to configure your design made with de Mietec design kit for use with QuickSim, AccuSim and ICgraph.

"Layout Guidelines" discusses some important items that help you generate layouts succesfully.

"Preparing for Processing" discusses the generation of the gds file that has to be sent to your service centre so the design can be processed.

If you are not familiar with the Mentor Graphics Falcon Framework, do not hesitate reading the "Getting Started" training workbooks on the INFORM system. Throughout this text you will find references to the most useful Mentor Graphics manuals. Mietec Design Kit User's Guide Page 3

T H E M I E T E C D E S I G N E N V I R O N M E N T ======

______| | | Mieted Design Kit | | ______| _____ | | | | | | | | | | |<===| Design Creation |===>| | | | |===>| and Configuration | | | | | | B | |______| | | | | | a | || /\ | | | | | c | ______\/__||______| | D | | | k | | | | | o | | | - |<===| Digital or Analog |===>| c | | | A |===>| Simulation | | | u | | | n | |______| | | m | | | n | || /\ | | e | | | o | ______\/__||______| | n | | | t | | | | | t | | | a |<===| Physical Layout |===>| a | | | t |===>| IC | | | t | | | i | |______| | | i | |_| o |______||__/\______| | o | | n | ______\/__||______| n | | | | | | | | | | Packaging |===>| | | | | and Test | | | |_____| |______| |_____|

Figure 1: The Mietec Design Environment

The Mietec design kit lets you create and configure designs with Design Architect and DVE, using the Mietec 2.4 micron cmos standard cell library. Symbol models and a menu are provided for use in Design Architect.

Digital simulation of the design can be done with QuickSim. Analog simulation can be done with AccuSim. The Mietec design kit provides simulation models for QuickSim and AccuSim.

Physical layout is done in ICgraph. The process definition file, rules file and physical layout databases for the standard cells are provided for ICgraph. Mietec Design Kit User's Guide Page 4

D E S I G N C R E A T I O N A N D C O N F I G U R A T I O N ======

You can do design creation and configuration in Design Architect and in the Design Viewpoint Editor DVE.

When your $AMPLE_PATH variable in your login file contains the path to the "mietec_lib" directory, you will be able to use the Mietec library palette. The "Library" menu in Design Architect will contain an item "Mietec". Choose the menu item "Library > Mietec" to use the Mietec library palette. All the symbols available in the Mietec design kit can be activated from the Mietec library palette.

More information about design creation and configuration can be found in following manuals, available on the INFORM system:

Getting Started with Design Architect Training Workbook

Design Architect User's Manual

A Guide to Design Creation and Configuration Mietec Design Kit User's Guide Page 5

D I G I T A L S I M U L A T I O N ======

QuickSim (II) is the tool used for digital simulation.

______/ \ | |_ | Mietec | | Design Creation | | | Symbol |---->|======| | | Models | | Design Architect | | \______/ |______| | |______| || ______\/______/ \ | Component | |======| | Schematic Model | | VHDL Model | | Symbol Model | \______/ | ______Referenced | ______| |______|______/ \ | Design Configuration | | / \ | Back- | |======| |<--->| Viewpoint |---| Annotation | | DVE | | \______/ | Object | |______| | || \______/ |______| ______\/______Connected | |_ | Digital Simulation | | |======| | | QuickSim II | | |______| | |______| /\ ______||______|______|______/ \ / \ | Component | | Architectural | | Modeling | | and Component | |------| | Modeling | | QuickPart Models | |------| | Technology Files | | System-1076 | \______/ \______/

Figure 2: QuickSim II Design Flow

Before invoking QuickSim on a design, a viewpoint has to be created with the Design Viewpoint Editor. QuickSim uses this viewpoint, the QuickPart models and technology files when simulating the design. The QuickPart models and technology files are provided in the Mietec design kit.

With the Design Viewpoint Editor you can connect or disconnected a back-annotation object to a design viewpoint. The back-annotation object can be generated by ICgraph. This way you can back-annotate routing capacitance's to the simulation.

More information can be found in following manuals: Mietec Design Kit User's Guide Page 6

Getting Started with QuickSim II Training Workbook

QuickSim II User's Manual

Digital Modeling Guide Mietec Design Kit User's Guide Page 7

A N A L O G S I M U L A T I O N ======

AccuSim is the tool used for analog simulation.

______/ \ | |_ | Mietec | | Design Creation | | | Symbol |---->|======| | | Models | | Design Architect | | \______/ |______| | |______| || ______\/______/ \ | Component | |======| | Schematic Model | | Symbol Model | \______/ | ______Referenced | ______| |______|______/ \ | Design Configuration | | / \ | Back- | |======| |<--->| Viewpoint |---| Annotation | | DVE | | \______/ | Object | |______| | || \______/ |______| ______\/______Connected | |_ | Analog Simulation | | |======| | | AccuSim | | |______| | |______| /\ || ______||______/ \ | Component | | Modeling | |------| | Mietec Modelfile | | (SPICE subckts) | \______/

Figure 2: AccuSim Design Flow

Before invoking AccuSim on a design, a viewpoint has to be created and a modelfile has to be connected to that viewpoint. AccuSim uses this viewpoint and the Mietec modelfile.

More information can be found in following manuals:

Getting Started with AccuSim Training Workbook

Analog Simulators User's Manual Mietec Design Kit User's Guide Page 8

P H Y S I C A L L A Y O U T ======

______/ \ | |_ | Mietec | | Design Creation | | | Symbol |---->|======| | | Models | | Design Architect | | \______/ |______| | |______| || ______\/______/ \ | Component | |======| | Schematic Model | | Symbol Model | \______/ | ______Referenced | | |______|______| Design Configuration | | / \ |======| |<--->| IC Viewpoint | | DVE | | \______/ |______| | || |______| ______\/_____ | |_ | Physical | | | Layout | | ______|======| | / \ | ICgraph | |<--->| IC Design | |------| | | Database | | ICplan | | \______/ | ICblocks | | ______| ICcompact | | / \ | ICtrace | | | Back | | ICrules | |---->| Annotation | | ICextract | | | Object | |______| | \______/ |______|

Figure 3: IC Station Design Flow

In ICgraph you can do standard cell place and route, polygon layout editing, DRC, LVS and extraction. Polygon layout editing and extraction to netlist are not covered.

To do a standard cell place and route of a schematic design, you first have to create an IC viewpoint with DVE. The IC viewpoint is read by ICgraph during cell creation. ICgraph uses the process definition file, the rules file and the library file. These files are provided in the Mietec design kit. After layout and verification, you can create a back- annotation object to back-annotate the routing capacitance's to a simulator. When the design checking is completed, the IC design database can be translated to gdsii format using IClink.

More information can be found in following manuals: Mietec Design Kit User's Guide Page 9

Getting Started with IC Station Training Workbook

IC Station Automated Layout Procedures Manual

IC Station Floorplanning Manual

IC Station Full Custom Procedures Manual

IC Station Layout Verification Operations Manual

IC Station Layout Verification Procedures Manual

IC Station User Interface Manual

ICLink Manual Mietec Design Kit User's Guide Page 10

T H E M I E T E C L I B R A R Y T R E E ======

The mietec_lib directory is accessible from the Falcon Framework using the location map variable $MIETEC_LIB, if the library has been installed properly.

A brief description of the Mietec library tree follows:

$MIETEC_LIB The main directory.

$MIETEC_LIB/analog/cmos24 Contains the AccuSim modelfile(s).

$MIETEC_LIB/analog/parts Contains parts that have been modified for simulation in AccuSim.

$MIETEC_LIB/bin Contains scripts used for compilation of the QuickPart models and technology files

$MIETEC_LIB/demo A demo design directory.

$MIETEC_LIB/des_arch Contains userware for Design Architect.

$MIETEC_LIB/doc Contains this file.

$MIETEC_LIB/dve Contains userware for the Design Viewpoint Editor.

$MIETEC_LIB/func_models/schematics Contains QuickPart schematics.

$MIETEC_LIB/func_models/tables Contains QuickPart tables.

$MIETEC_LIB/layout/cmos24 Contains the physical design configuration files.

$MIETEC_LIB/parts Contains symbols, compiled QuickPart and timing models, and schematics.

$MIETEC_LIB/qcheck Contains the QuickCheck configuration files

$MIETEC_LIB/techfiles/cmos24 Contains the sources of the technology files.

$MIETEC_LIB/userware hwf A handy wave form pre-processor Mietec Design Kit User's Guide Page 11

conversion Contains a symbol map file for use with cvt_comp.

We will take a closer look at the model and configuration files used by Design Architect, QuickSim II, AccuSim and ICgraph.

Userware ------

The Mietec design kit contains userware for Design Architect (da) and the Design Viewpoint Editor (dve). You can use this userware only if you the AMPLE_PATH shell environment variable is set to the mietec_lib directory.

See the installation notes that come with the Mietec design kit media to set up your environment properly .

Symbol Model and Part Interface ------

The symbol models of the Mietec design kit reside in the $MIETEC_LIB/parts directory. The symbols are registered in the part interface with the name "mietec".

In Design Architect you can use these symbols when you are designing a schematic. The symbols are accessible from the Mietec library menu in Design Architect. Choose Library > Mietec to display the Mietec Library palette.

Example:

$MIETEC_LIB/parts/my_dffrl/mietec $MIETEC_LIB/parts/my_dffrl/part

Analog Models ------

Every component in the $MIETEC_LIB/parts directory that can be simulated with AccuSim has a schematic. This schematic contains a component that has been modyfied for the use with SPICE subcircuits in the Accusim modelfile. These modefied components are located in the $MIETEC_LIB/analog/parts directory.

Example:

$MIETEC_LIB/parts/and2/schematic $MIETEC_LIB/analog/parts/and2_analog

The Accusim modelfile is located at:

$MIETEC_LIB/analog/cmos24/mietec_cmos24_subcircuits.cir

You can use this file through the location map variable $MIETEC_CMOS24_ACCUSIM_MODFILE. This file has to be defined Mietec Design Kit User's Guide Page 12

in your design viewpoint for AccuSim. Section "Creating Design Viewpoints" contains a description of the steps needed to do this.

The file:

$MIETEC_LIB/analog/cmos24mietec_cmos24_l3_modelcards.cir

contains the SPICE level 3 models for simulation of MOS transistors. Other miscellaneous models, diodes and bipolar transistor, are also included. You can use this file through the location map variable $MIETEC_CMOS24_ACCUSIM_MODCARDS.

* IMPORTANT REMARK: * * Do not use level 2 models, they are * not as accurate as level 3 models.

QuickPart Table Model ------

All functional models in the Mietec design kit are modeled with QuickPart tables except the "mds*" cells. The source QuickPart tables reside in the $MIETEC_LIB/func_models/tables directory.

Example:

$MIETEC_LIB/func_models/tables/my_dffrl.table

> model my_dffrl: table= > > input d, rb; > edge_sense input ck; > output q, qb; > > state_table > > d, ck, rb :: q, qb; > ##------||------> ?, [?0], 1 :: N, N; > ?, [11], 1 :: N, N; > ?, [01], 1 :: (d), !(d); > ?, [??], 0 :: 0, 1; > > end;

The tables have been compiled using the script $MIETEC_LIB/bin/qpt_com. The binaries are placed in the component directory and registred with the label "cmos24". This means that the primitive "model: cmos24" has to be added to the design viewpoint, otherwise QuickSim can not find the appropriate simulation models.

Example:

$MIETEC_LIB/parts/my_dffrl/qpfile

Technology File Mietec Design Kit User's Guide Page 13

------

The technology files, also called timing models, reside in the $MIETEC_LIB/techfiles directory. For every supported technology of the Mietec foundry, you will find a directory. Present there is only one technology implemented, the 2.4 micron cmos process in the cmos24 directory. The $MIETEC_LIB/techfiles/cmos24 directory contains the sources and binaries of the technology files. The technology file contains the timing data for a cell. Note that there is also an include file. This include file mietec_cmos24.include contains the macros used in the "TIMING AND CONSTRAINT STATEMENT" section of the technology file.

Example:

$MIETEC_LIB/techfiles/cmos24/src/my_dfflr.ts

> model my_dffrl: technology = > > declare > > #include "mietec_cmos24.include" > > ###### TECHNOLOGY CONSTANTS ###### > > #define TP_CK_Q_R 6.0 > #define CL_CK_Q_Q_R 5.1 > ... > #define TP_RB_Q_F 8.4 > #define CL_RB_Q_Q_F 5.3 > #define CL_RB_Q_QB_F 6.0 > > #define TSETUP 7.5 > #define THOLD 6.5 > > #define TRELEASE 25.0 > #define TRECOVERY 25.0 > > ###### TECHNOLOGY PROPERTIES ###### > > property comp_size 19080; > > pin property d cap_pin 0.32; > pin property ck cap_pin 0.184; > pin property rb cap_pin 0.152; > pin property q max_drive 0.7; > pin property qb max_drive 0.6; > > ###### TIMING AND CONSTRAINT STATEMENTS ###### > > begin > > tp = prop_time("q", TP_CK_Q_R, CL_CK_Q_Q_R) > on ck (AH) to q (AH); > tp = prop_time("q", TP_CK_Q_F, CL_CK_Q_Q_F) > on ck (AH) to q (AL); > > tp = prop_time2("qb", TP_CK_QB_R, CL_CK_QB_QB_R, > "q", CL_CK_QB_Q_R) on ck (AH) to qb (AH); Mietec Design Kit User's Guide Page 14

> tp = prop_time2("qb", TP_CK_QB_F, CL_CK_QB_QB_F, > "q", CL_CK_QB_Q_F) on ck (AH) to qb (AL); > > tp = prop_time("qb", TP_RB_QB_R, CL_RB_QB_QB_R) > on rb (AL) to qb (AH); > tp = prop_time2("q", TP_RB_Q_F, CL_RB_Q_Q_F, > "qb", CL_RB_Q_QB_F) on rb (AL) to q (AL) > with ck (L); > tp = prop_time("q", TP_RB_Q_F, CL_RB_Q_Q_F) > on rb (AL) to q (AL) with ck (H); > > ts = scale(TSETUP) on d to ck (LH) do setup_message; > th = scale(THOLD) on d to ck (LH) do hold_message; > > ts = TRELEASE on rb (H) to ck (LH) do > release_message; > th = TRECOVERY on rb (H) to ck (LH) do > recovery_message; > > end;

The script $MIETEC_LIB/bin/tc_com compiles the timing file and links it with a library file. The binary is placed in the $MIETEC_LIB/techfiles/cmos24/bin directory.

Example:

$MIETEC_LIB/techfiles/cmos24/bin/my_dffrl $MIETEC_LIB/techfiles/cmos24/bin/mietec_cmos24

The functional and timing models are registered with the name "cmos24".

Physical Design Configuration ------

The physical design configuration files reside in the $MIETEC_LIB/layout/cmos24 directory. It contains the process definition file, the rules file, the library file and the physical layout databases of the standard cells.

o The Process Definition File

The process definition file process/mietec_cmos24 contains the layer and process variable settings for ICgraph in general and ICblocks. You can access the process definition file in ICgraph by using the location map variable: $MIETEC_CMOS24_IC_PROC.

o The Rules File

The ascii rules file process/mietec_cmos24_rules contains the design rule checks and extraction configuration. You can access the rules file in ICgraph by using the location map variable: $MIETEC_CMOS24_IC_RUL Mietec Design Kit User's Guide Page 15

You can find more information about the design rules in the file itself and in the "Mietec Standard Cell User Manual 2.4 micron CMOS".

o The Library File

The library file library/mietec_cmos24 contains the references to the physical layout information of the standard cells you can use in the Mietec design kit. You can access the process definition file in ICgraph by using the location map variable: $MIETEC_CMOS24_IC_LIB.

o The Physical Layout Database

The physical layout databases of the standard cells reside in the cells directory.

QuickCheck Configuration Files ------

The directory $MIETEC_LIB/qcheck contains the configuration file for QuickCheck in DVE. The two files needed are:

$MIETEC_LIB/qcheck/config_data/erc_rules.bin $MIETEC_LIB/qcheck/config_data/nc_rules.bin

The files can be used through the location map variables $MIETEC_QCHECK_ERC and $MIETEC_QCHECK_NC.

The electrical rule checks done with the $MIETEC_QCHECK_ERC file are:

- Shorted output pins - Undriven input pins - Unconnected input pins - Unconnected bidirectional pins - Unconnected output pins - Fanout - Statistics

See section "Creating Design Viewpoints" for more details on using these files. Mietec Design Kit User's Guide Page 16

C R E A T I N G D E S I G N V I E W P O I N T S ======

A design viewpoint is a special data object used for design configuration. You can create a design viewpoint with the Design Viewpoint Editor (DVE). DVE is used for custom design configuration, design checking and back-annotation management. After creating a component in Design Architect (or other source creation applications) you can invoke downstream applications such as QuickSim, AccuSim and ICgraph.

Each of these downstream tools needs a special design configuration. In the following is explained what you have to do to create a configuration file for QuickSim, AccuSim and ICgraph.

The Mietec design kit contains userware that defines an additional "Mietec" menu in DVE. You can use this menu to setup a viewpoint for QuickSim (and related simulators such as QuickFault, QuickPath and QuickGrade), AccuSim and ICgraph. The electrical rules check can also be performed.

More information can be found in:

Design Viewpoint Editor User's and Reference Manual

A Guide to Design Creation and Configuration

Creating a Viewpoint for QuickSim ------

All the QuickPart and timing models are registered with the label "cmos24". This means that the primitive level in the design viewpoint must be set to "model = cmos24" to be able to simulate the design with QuickSim.

1. Invoke the Design Viewpoint Editor on your design.

2. To create a design viewpoint, choose following menu item:

File > Open > Design Viewpoint...

Enter following items to the Open Design Viewpoint dialog box:

Component Name: your_design_name

Viewpoint Name: quicksim_vpt

Execute the dialog box.

3. Setup the configuration for the QuickSim family simulators:

Mietec > Setup (Quick)SIM, Fault, Path and Grade

Notice the changes in the Design Configuration window.

The setup for QuickSim, QuickFault, QuickPath and Mietec Design Kit User's Guide Page 17

QuickGrade is performed, and the following primitives and visible properties are added:

Primitive: model Value: cmos24

Visible properties: cap_net Owner: NET cap_pin Owner: PIN max_drive Owner: PIN

Primitives defines the lowest level data that is saved in the design viewpoint. In this case, the instance that has the property named "MODEL" attached to it with the value "cmos24", is also to be considered a primitive.

4. Save the design viewpoint and exit the Design Viewpoint Editor.

Within DVE it is possible to do ERC checks on your design with the QuickSim configuration. To do so you must execute the following menu:

Mietec > QuickCheck ERC

This starts up QuickCheck ERC with the file $MIETEC_QCHECK_ERC that contains the configuration for QuickCheck ERC. A report window appears with errors and warnings found in the design, also a statistics report is included.

Creating a Viewpoint for AccuSim ------

To prepare a design for simulation in AccuSim, you have to create a design viewpoint and connect a modelfile to that design viewpoint.

1. Invoke the Design Viewpoint Editor on your design.

File > Open > Design Viewpoint...

Viewpoint Name: accusim_vpt

3. Setup the configuration for the QuickSim family simulators:

Mietec > Setup AccuSim

A back-annotation object "accusim_modfile.ba" has been created and the accusim modelfile Mietec Design Kit User's Guide Page 18

$MIETEC_CMOS24_ACCUSIM_MODFILE has been connected to the design viewpoint.

4. Save the design viewpoint and exit the Design Viewpoint Editor.

Creating a Viewpoint for ICgraph ------

An IC viewpoint has to be created before you can perform automated placement and routing.

1. Invoke the Design Viewpoint Editor.

File > Open > Design Viewpoint

Viewpoint Name: icgraph_vpt

3. To add a primitive to the design viewpoint, choose the menu item:

Mietec > Setup ICgraph

Following primitives and visible properties are added:

Primitive: phy_comp

Visible properties: place Owner: INSTANCE phy_pin Owner: PIN pin Owner: PIN

Primitives defines the lowest level data that is saved in the design viewpoint. In this case, the instance that has the property named "MODEL" attached to it with the value "cmos24", is also to be considered a primitive.

4. Save the design viewpoint and exit the Design Viewpoint Editor. Mietec Design Kit User's Guide Page 19

C R E A T I N G A S T A N D A R D C E L L L A Y O U T ======

______| | | Design Architect | |------| | Pre-Placent IO-Cells | |______| || ______\/______| | | AccuSim or | | DVE | | QuickSim | |------|======>|------| | Viewpoint Creation | | Simulation | |______| |______| || | ______\/______| | | | | ICgraph Layout Editor | | | ______| | | | | | | | | Cell Creation |<--->| | | | |------| | | | | | Floorplanning |<--->| | | | |------| | | | | | Standard Cell/Block |<--->| | | | | Placement | | | | | |------| | | | | | Routing |<--->| | | | |------| | | | | | Optimization |<--->| | | | |------| | | | | | LVS Checking |<--->| | | | |------| | | | | | Design Rule Checking |<--->| | | | |------| | | | | | Extraction and | | | | | | Back-Annotation |<--->| | | | |______| | | |______| | | | |______| Back-Annotation

Figure 4: Simulation and Automated Layout Methodology

This section gives an overview of how to make the several design viewpoints, start simulations in QuickSim and AccuSim and how to place and route a standard cell design in ICgraph. It will not discuss all features. More information can be found in the manuals available on the INFORM system.

Pre-Placement of IO-Cells ------

Before you lay out your design, you have to pre-place the IO-cells in the design. The easiest way to do this is to add a PLACE property to the instances of Mietec Design Kit User's Guide Page 20

the IO-cells in the schematic.

1. Invoke Design Architect.

2. Open the schematic design containing the IO-cells by choosing the following menu item:

Open Sheet

The Open Sheet dialog box is displayed. Enter:

Component Name: your_sheet

Execute the Open Sheet dialog box.

3. Select the IO-cells one by one and add the PLACE property to the instance by choosing the menu item:

RMB: Properties > Add

The Add Property dialog box is displayed. Enter:

Property Name: PLACE Property Value: T1

Execute the Add Property dialog box and the place the PLACE property clicking the left mouse button.

The values to enter for the PLACE properties are discussed in the section "Guidelines".

4. Check to sheet by choosing the menu item:

Check > Sheet

If errors occur, correct them. Be aware that the values of the PLACE property are not being checked by Check Sheet. By sure that no instance has the same PLACE property value.

5. Save the sheet and exit Design Architect.

Viewpoint Creation ------

See the previous chapter, topic "Creating a Viewpoint for ICgraph".

Cell Creation ------

In this procedure you create an empty cell for your design in preparation for floorplanning, placement and routing of standard blocks.

1. Invoke ICgraph.

2. To create the cell, choose the following menu item:

Session Palette > Cell Create Mietec Design Kit User's Guide Page 21

The create cell dialog box is displayed. You retain the default settings for most of the items on this dialog box. Enter:

Cell Name:

Attach Library: $MIETEC_CMOS24_IC_LIB

Process: $MIETEC_CMOS24_IC_PROC

Operational Configuration: CBC

Logic Source:

Logic Loading: Flat

Execute the Create Cell dialog box.

3. To load the design rules required for standard cell creation, choose the following menu item:

File > Load Rules...

Enter on the Load Rules dialog box:

Rules File: $MIETEC_CMOS24_IC_RUL

Execute the Load Rules dialog box.

4. Check the status line and make sure you are working in CBC mode. If you are not in CBC mode, choose following menu item:

Context > Set Cell Config > Correct By Construction

Floorplanning ------

In this procedure, you create the floorplan. Choose the following menu items:

IC Palettes > Place/Route

Place & Route > Autofloorplan

The Autofloorplan Options dialog box pops up. You can change the settings or you can retain the default settings. Execute the dialog box.

If needed you can edit the floorplan.

Standard Cell/Block Placement ------

In this procedure, you automatically place and route the standard cells.

Place & Route > Autoplace Std Cells

The Standard Cell Placer Options fill form pops up. Mietec Design Kit User's Guide Page 22

When you are done changing the settings, execute the prompt bar to place the standard cells on the floorplan rows.

Routing ------

To automatically route the cell, choose the menu item:

Place & Route > Autoroute All

The Autoroute All prompt bar pops up. You can change the route method. Execute the prompt bar to route the design.

The cell should be completely routed.

Optimization ------

You can optimize your cell by minimizing the vias and compacting.

1. To minimize the vias, choose the following menu item:

Place & Route > Minimize Vias

On the Minimize Vias prompt bar, set the Route Levels, the Maximum Length and the Options. Execute the prompt bar.

2. To compact the cell, choose the following menu item:

Place & Route > Compact

In the Compact prompt bar, set the direction, the extent and other Options. Execute the prompt bar.

Repeat these steps until you are satisfied with the result.

Layout Versus Schematic Checking ------

In this procedure you will compare your layout to the design viewpoint you created.

To perform LVS on the design, choose the following menu item:

IC Palettes > ICtrace (D) > LVS

The LVS (Direct) dialog box is displayed.

On the LVS (Direct) dialog box, click the Setup LVS button. Mietec Design Kit User's Guide Page 23

On the Setup LVS dialog box, enter :

Type properties: phy_comp

Pin name properties: phy_pin

Power names: VDD VDD_IO_RING VDDA VDDA_IO_RING

Ground names: VSS VSS_IO_RING VSSA VSSA_IO_RING

Click the button: Ignore Ports

Execute the Setup LVS dialog box and the LVS (Direct) dialog box. The mux2 layout is compared to the design viewpoint that you created. A report is generated and placed in your working directory.

To view the report, choose the following menu item:

MGC > Notepad > Open > Read Only

Using the Navigator, locate and click on the file called lvs.rep. Execute the Navigator Scroll through and read the LVS report.

At this point you would correct any LVS errors and rerun the LVS checks.

Design Rule Checking ------

After you have ensured that the layout matches the schematic, you must determine whether the layout meets the design rules for the technology that you are using.

Choose the following menu item:

IC Palettes > ICrules

1. To select all DRC rules in the Rules file, choose the following menu item:

ICrules > Select > All

To display the selected DRC rules in the Rules File, choose the following menu item and execute the Display Selected Rules prompt bar:

ICrules > List > Selected:

A DRC Rule File report dialog box is displayed that shows the DRC related rules that are in the Rules file. Mietec Design Kit User's Guide Page 24

Close the DRC Rule File report dialog box.

To perform DRCs, complete the following tasks:

2. To select everything in the cell, choose the following menu item:

IC window popup > Select > All

To peek all instances in the mux2 cell, choose the following menu item:

Context > Hierarchy > Peek:

Execute the Peek prompt bar.

You can see the internal mask data for the peeked cells. You need to peek the cells in order to perform the design rule checks at all levels of the design hierarchy.

Unselect everything.

3. To run the DRCs, choose the following menu item:

ICrules > Check

Execute the Check DRC prompt bar.

The selected DRC rules in the Rules File are executed. In this procedure, you selected all the DRC rules. In other circumstances, you might choose to run only some checks in order to locate specific kinds of errors.

4. To view the errors found by the checks, choose the following menu item:

ICrules > Set Scan To First

The first DRC error is highlighted. To get a closer view of the error, choose the following menu item:

ICrules > View

ICgraph centers and zooms in on the DRC error in the IC window. The highlighting for the error flashes momentarily to let you locate the error.

To view of the next error, choose the following menu item:

ICrules > Set Scan To Next

ICgraph centers and zooms in on the next DRC error in the IC window.

5. A report can be generated choosing the following menu item:

ICrules > Report > All Mietec Design Kit User's Guide Page 25

Execute the prompt bar. The report pops up.

At this point you correct any DRC errors and rerun the DRCs.

Extraction and Back-Annotation ------

After you have ensured that the layout conforms to the design rules for the technology that you are using, you must extract parasitic data from the layout that you can use in later steps to simulate the design.

1. To perform parasitic extraction, choose the following menu item:

IC Palettes > ICextract (D) > Lumped

2. To generate the extraction database, and go on with:

IC Palettes > ICextract (D) > Bkannotate

The Backannotate Net Parameters dialog box is displayed. Enter following items:

BA Name: pex_ba

ASCII BA Name: layout_ba.ascii

Type: Lumped

Lumped Capacitance button: Yes

Name: cap_net

Exclude: VDD VDD_IO_RING VSS VSS_IO_RING

Execute the Backannotate Net Parameters dialog box

3. To view the results of the parasitic extraction, choose the following menu item:

ICtrace (D) > Report > All Nets...

Execute the Report Net Parameters dialog box.

A dialog box is displayed in which you can view the C values for the nets in your design.

Remove the dialog box.

Now you can resimulate your design by using the new C values to determine whether any changes are required in your layout.

Fanout Checking Mietec Design Kit User's Guide Page 26

------

You use QuickCheck to check the fanout of the cells.

1. Invoke the Design Viewpoint Editor on the QuickSim design viewpoint.

2. Connect the back-annation object pex_ba to the QuickSim design viewpoint:

File > Back Annotation > Connect

Enter the back annation name to the form:

Back Annotation Name: your_path/pex_ba

3. Select the menu option:

Mietec > QuickCheck ERC

or select:

Miscellaneous > Check Design > Check Options...

Click the Electrical Rule Checks Yes button in the fill form and add to the form:

ERC Binary File(s): $MIETEC_QCHECK_ERC

Execute the form. A report window appears with errors and warnings found in the design, also a statistics report is included.

Post Layout Simulation ------

If the back-annotation object is not yet connected to your QuickSim design viewpoint, you can use the ASCII back- annotation object generated above and back-annotate the C values to the simulator.

Invoke Quicksim and open your design sheet by choosing menu item:

File > Open Sheet

To import the ASCII back-annotation object, choose the following menu item:

File > Back Annotation > Import

The Import Back Annotation dialog box pops up. Enter:

ASCII BA File: your_path/pex_ba.ascii

You can see the cap_net properties on the nets in the schematic view. You can resimulate your design using the cap_net properties to calculate the delays of the output. Mietec Design Kit User's Guide Page 27

If the simulation runs correct, your design is ready for processing. Mietec Design Kit User's Guide Page 28

L A Y O U T G U I D E L I N E S ======

______| T1 | | T2 | | | | | ______| |__ __| |______| ______| |__ vssa_io_ring __| |______| | | ______| |__ vdda_io_ring __| |______| | | | | ______| |__ vdd_io_ring __| |______| | | | | | | ____| |__ vdd_io_ring __| |____ | | | | | | | | | |______| |______| | | | | | _____|_|_|_|_|_ _|_|_|_|_|_____ | L5 | ______| R5 | | | | |__ | | | | | ____| Digital cells | | | | | |______| | __|______| | | |______| _____|_|_|_|_|_ | | | | _|_|_|_|_|_____ | L4 iovss|_____| | ______| |_____|iovdd R4 | | | vss | | |__ vdd | | | |_____ |__| Sitetype 1 | |______| | |______| |____|______| |______| _____|_|_|_|_|_ _|_|_|_|_|_____ | L3 vddshort| ______|vddshort R3 | |______| | |__ | |______| _____|_|_|_|_|_ | Analog cells | | | _|_|_|_|_|_____ | L2 pfvdd|______| | | |_____|pfvdd R2 | | | vssa __|______| | vdda | | | |_____ | | _____| | |______| | | ______| | |______| _____|_|_|_|_|_ | | | |____| _|_|_|_|_|_____ | L1 | | | | Sitetype 2 | | R1 | | | | |__| | | | | | |____|______| | | |______| |______| | | | | | ______| | | | | | | | | |_____| B1 | B2 | B3 | B4 |____| | | | | | | | |______| | | | |______| | | | | | |______| | | | |______| | | | |______| | | | |______| | |______| | | | |______| | | Sitetype 3 | | | | | | | |______|______|______|______|

Figure 5: Mixed Analog and Digital Standard Cell Design

This section will discuss the following topics:

Power- and Groundnames Sitetypes PLACE Properties IO-Cells in the Schematic Mietec Macro Cells Design Rule Checks Tracks (Via Spacing) Spacings between Cells after Compaction Extraction of Devices.

Power- and Groundnames ------Mietec Design Kit User's Guide Page 29

As you can see in figure 5, there are four power- and four groundnames in a Mietec mixed analog and digital standard cell design:

| Internal External ------|------DIGITAL POWER | VDD VDD_IO_RING GROUND | VSS VSS_IO_RING ANALOG POWER | VDDA VDDA_IO_RING GROUND | VSSA VSSA_IO_RING

The configuration of the power and ground in a design is always:

Analog and digital ground at the LEFT side

Analog and digital power at the RIGHT side.

This forces the designer to pre-place the power and ground IO-cells on the IO-ring as follows:

IOVSS and PFVSS on the left side

IOVDD and PFVDD on the right side.

If you don't, the router will not be able to route the power and ground nets completely in most cases.

It is also good practive to group the analog IO-cells and digital IO-cells, for example the analog IO-cell at the bottom and the digital IO-cells at the top of the IO-ring.

Sitetypes ------

The sitetype defines in which floorplan shape a cell can be placed. For example, a digital core cells can be placed in the IO-ring floorplan shape because the sitetype don't match.

There are four different sitetypes used in the Mietec design kit:

Sitetype 0: for large blocks (ad081, da081, ...)

Sitetype 1: for digital core cells

Sitetype 2: for analog core cells

Sitetype 3: analog and digital IO-cells

As you can see, there is only one sitetype (3) for the analog and digital IO-cells, so it is possible that the analog and digital IO-cells are mixed, but it is better you do mix them.

PLACE Properties ------Mietec Design Kit User's Guide Page 30

The easiest way to pre-place the IO-cells is to add PLACE properties to the instances ot the IO-cells in your schematic. The topic "Operating Procedures" contains a section that tells you how to add a PLACE property to an instance.

In figure 5, the values of the PLACE properties are indicated in bold style. For example the IO-cell on the left side on the bottom has a PLACE property L1.

IO-Cells in the Schematic ------Be sure to place the IO-cell instances on the top schematic of your design hierarchy. This way it is easy to add the place properties to all instances of IO-cells.

Mietec Macro Cells ------Using the Mietec macro cells (m1d*, mxd*, mt*, mds* cells) you can reduce routing in the channels. Since today's routers are good, you don't gain much in area using these macro cells. It is recommended not to use these macro cells anymore. If you still want to use them. Be sure to add PLACE properties to the instances of the macro cells. See also the previous sections about pre-placement and PLACE properties.

Example:

A flipflop chain containing one m1drl cell and two mxdrl cells.

The m1drl cell has to be the first cell in the chain: PLACE property value: T1:L1

This is the most left cell in the top row.

The second cell which is a mxdrl cell: PLACE property value: T1:L2

This is the second cell in the top row from the left.

The third cell which is a mxdrl cell: PLACE property value: T1:L3

Design Rule Checks ------You can find the design rules file "mietec_cmos24_rules" in the "$MIETEC_LIB/layout/cmos24/process" directory. All the design rules are implemented with the names used in the document "Lay Out Rules 2.4 micron CMOS" of Mietec. You can always print out the rules file for additional information on the implemented design rule checks. Mietec Design Kit User's Guide Page 31

Tracks and Via Spacing ------The width of a track in the Mietec technology is 10 micron. Take a look in the document "Lay Out Rules 2.4 micron CMOS" of Mietec. Rule 12B and according note say that the metal2-metal2 spacing of 3 micron is allowed around vias, otherwise the spacing is 4 micron.

Spacing between Cells after Compaction ------

You have to be carefull when compacting the internal core cells. Consider the configuration of a design as in figure 5. Compacting in horizontal direction can cause the cells to slide to the left or to the right. This can insert little spacings between the cells. These spacings can be the cause of design rule errors in on the P-Window layer. To avoid this you can use check "ERROR CELL SPACING" in ICrules. This checks the spacing between the cell boundaries on the "fp" layer to be larger than 10 micron or abutting. The spacing of 10 micron equals the width and spacing of a metal2 wire routed between the cells.

Extraction of Devices ------Following devices can be extracted:

NMOS transistor PMOS transistor POLY1-POLY2 capacitor N+ Diffusion resistor P+ Diffusion resistor N-WELL resistor Poly1 resistor

To extract the resistor, you have to draw a RES-Layer polygon over the device. If you don't, the resistor will be extracted as a parasitic resistance and not as a resistor device. You do not need to draw additonial polygons to extract the transistor and capacitor devices. Mietec Design Kit User's Guide Page 32

P R E P A R I N G F O R P R O C E S S I N G ======

After your design passed the checks and resimulations is your ready for processing. You have to create a gds file, that can be sent to your service centre for processing.

Enter the following at the prompt:

$ iclink -convert -source -ics -destination -gds .gds

This generates a file .gds that can be put on tape and sent to the service centre.

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