Laboratory Experiment #6

Laboratory Experiment #6: Carry Select Adder

Ari Mahpour ECE 526 Lab Student ID #: 101146706 Table of Contents Purpose The purpose of this lab is to implement and view the behavior of a six bit carry select adder. As opposed to other adders, such as ripple carry adders, the carry select adder will evaluate in a parallel fashion, running much faster than any other conventional adder. In the final test bench, the student was instructed to implement a carry select adder and a normal adder that was coded behaviorally. The test benches and results will be discussed later.

When implementing the carry select adder, the student had to consider a bottom up design, as instructed by the laboratory manual. The first level consisted of a full adder, the second, a two bit summer, and the third, the carry select adder itself (top module). The design of the full adder was a simple assign statement but the two bit summer required a combination of parts. The two bit summer consisted of two pairs of full adders, and two multiplexers. One pair of full adders would take in a ‘0’ carry in bit and a ‘1’ carry in bit. The second set would evaluate those previous full adders. The multiplexers would be controlled by the carry out bits and would determine which would be the appropriate outputted sum (i.e. the ‘0’ or ‘1’ carry in full adders). The top level module, the carry select adder itself, would consist of two, two bit summers, the first two full adders, and two multiplexers. As the one two bit summer was performing a set of sums, the second one would also be performing calculations in parallel timing. To be discussed in the test strategy are the potential problems or gains with the carry select adder versus a normal adder which was coded behaviorally. Test Strategy This experiment consisted of two separated test benches. The first test bench was a non-exhaustive test bench, plugging in specific vectors to test the circuit itself for proper functionality. The vectors that were chosen were to test functions such as normal adding performances, overflow, carry bits, ‘x’ values, and ‘z’ values.

The second test bench was an exhaustive test bench which consisted of for loops and other functions specified by the laboratory manual. The “for” loops directed the test bench to traverse through all the possible input vectors and perform a proper summation processes.

Should something not work, it would output that there were certain mismatches. If the test found that there were no mismatches, comparing the implemented 6-bit carry select adder and the behaviorally coded 6-bit adder, then there were be an outputted message stating that all worked fine.

Another test that was included in the test bench was implementing a “force” assignment to override the behavioral adder’s sum. The last twelve vectors were forced to ensure that mistakes would show up in the test vectors. It was important to use the last twelve vectors because only the first 12 and last twelve were monitored using the “$monitoron” and

“$monitoroff” functions. Had they been off, it would have been difficult to determine what the error is (if reading the log file) and not being able to see the inputs, carries, and sum values. Results For the non-exhaustive test, all the values had added up properly. Simply by adding up the values by hand or in a binary calculator would show that everything had been calculated perfectly.

Though there were no statements to verify this by the computer automatically, all processes were manually verified.

The exhaustive test also proved to be a success. When omitting the “force” function, all values had come out to be equal to each other. Thus, the implemented 6-bit adder and behaviorally coded adder had worked exactly the same (just as predicted). For the force function, it was quite clear from the beginning that errors would show up for those forced values. Exactly as predicted, the last twelve vectors had been triggered by the error checker and indicated that there was a mismatch between the implemented adder’s sums and the behaviorally coded adder’s sums. This, once again, was forced and since the exhaustive, error-free, test bench had been performed previously, it was quite evident that both adders worked perfectly well. The attached waveform and log files depict how all the modules worked perfectly. Naturally, all test benches for the lower level modules were successful (considering that the top design was a success). Conclusion In the laboratory experiment we explored many different functions that we had learned in the corresponding lecture course. All of these were very important to not only learn but to be put into practice. Though we had used functions such as “$monitor” it wasn’t so clear when we would be turning it on and off. For this test bench it was very clear how useful the ON and

OFF parts of the “$monitor” function was. More than just implementing code, it was important to understand why the carry select adder is known as one of the fastest adders out there. In order to fully understand a concept such as this, it is important to run accurate tests (such as this laboratory experiment) to fully comprehend the behavior of a logic circuit. Waveform DiagramI hereby attest that this lab report is entirely my own work. I have not copied either code or text from anyone, nor have I allowed or will allow anyone to copy my work.

Name (printed): ______

Name (signed): ______

Date: ______