ECE 4480/5480 Computer Architecture and Design s1

ECE 4480/5480 Computer Architecture and Design spring 2013

Exam I open textbook and lecture notes only

Name: ______solution______(print) Problem 1 (MIPS instruction encoding) assuming registers 1 – 30 have the following contents register number contents (in decimal) $1 0 $2 400 $3 80 $4 120 $5 16

memory, MIPS addresses each byte, word addresses are multiples of 4; 4 bytes in a word word address data; (address and data are in decimal) 0 1 4 101 8 10 12 100 16 200 20 300 24 400

(a) encoding lw $1, 4($5) (you can write your answer in hex) 8CA100004 1000 11 00 101 0 0001 0000 0000 0000 0100

31 0

(b) what are the contents (in hex) of $1 and $5 after executing the instruction in (a) $1 = 300 (decimal) = 0000012C 0000 0000 0000 0000 0000 0001 0010 1100

$5 = 16 (decimal) = 0x10 (hex) 0000 0000 0000 0000 0000 0000 0001 0000

(d) What are the final contents of $3 and $2 after executing instruction in (c) $3 = 80 (decimal) = 0x50 (hex) 0000 0000 0000 0000 0000 0000 0101 0000

$2 = 400 (decimal) = 0x190 (hex) 0000 0000 0000 0000 0000 0001 1001 0000 Problem 2 There is a five-stage pipeline processor as studied in Chapter 4. inst. no. (1) add $12, $11, $10 (2) sub $11, $10, $9 (3) lw $11, 100($1) (4) andi $1, $2, 100 (5) add $1, $2, $11 (6) and $2, $1, $6 (7) sub $22, $2, $1 (8) sw $22, 2003($1) (9) sw $2, 2003($22)

(a) Identify all possible data hazards in the code above without any forwarding paths. instruction no. register causing (3, 5) $11 (4, 6) $1 (5, 6) $1 (5, 7) $1 (6, 7) $2 (7, 8) $22 (7, 9) $22

(b) Assuming the hazard detection unit works properly and stalls the processor properly, How many clock cycles are needed to finish the above 9 instructions on the pipelined processor without any forwarding paths.

Ins Ck1 Ck2 Ck3 Ck4 Ck5 6 7 8 9 10 11 12 13 14 15 Ck16 (1) F D E M W (2) F D E M W (3) F D E M W (4) F D E M W (5) F S D E M W (6) F S S D E M W (7) F S S D E M W (8) F S S D (9) F

table extended to accommodate instruction (9). Ins Ck17 Ck18 Ck19 Ck20 (8) E M W (9) D E M W (c) Show forwarding paths and identify all possible data hazards after adding forwarding paths. Forwarding path: from EX/MEM pipeline register to ALU input MUX Forwarding path: from MEM/WB pipeline register to ALU input MUX

(d) How many clock cycles are needed to finish above 9 instructions on a pipelined processor as shown in Figure 4.60 Ins Ck1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 (1) F D E M W (2) F D E M W (3) F D E M W (4) F D E M W (5) F D E M W (6) F D E M W (7) F D E M W (8) F D E M W (9) F D E M W extend the table as needed Problem 3. The following three figures show the state diagram, processor and the control logic implementation. Now we like to add another instruction ori

(1) Modify the following state diagram to include the instruction ori and list the control signals used by ori instruction The Multicycle Datapath with Control Signals

PCWriteCond PCWrite PCSource IorD ALUOp MemRead Control ALUSrcB MemWrite ALUSrcA MemtoReg RegWrite IRWrite RegDst

PC[31-28] Shift Instr[25-0] 28 left 2 2 0 1

C Memory 0

P 0 Read Addr 1 A

Address R

I Read 1 Register 1 zero Read Addr 2 Data 1 t Read Data u 0 File o (Instr. or Data) ALU U Write Addr L 1 Read A

Write Data Data 2 B 1 Write Data 0 R 4 1 D

M 0 2 Instr[15-0] Sign Shift 3 Extend 32 left 2 ALU Instr[5-0] control

(2). Highlight the data path and control signals required by your design of instruction ori (3) Derive the logic equation for NS2 after including the new instruction ori. Problem 4. (1) Highlight the data path and set control signals used by sw $4, 100($5) (2) Highlight/modify the data path and set control signals required by sll $12, $10, 2