NOTE TO REVIEWERS: This Paper is currently slightly larger than 7 pages. If accepted we plan to pay for an extra page. If this is not possible, we plan to reduce the paper in sections with red font, and also to remove Figures 7 and 8 and also to reduce the number of citations. A Quantum CAD Accelerator Based on Grover’s Algorithm for Finding the Minimum Fixed Polarity Reed-Muller Form

Lun Li1*, Mitch Thornton*, and Marek Perkowski**

*CAD Methods Lab, Southern Methodist University, Dallas, TX 75206, USA, {lli,mitch}@engr.smu.edu ** Portland Quantum Logic Group, Electrical & Computer Engineering Department, Portland State University, Portland, OR 97207-0751, USA, [email protected]

Abstract . From this aspect, this research is only of theoretical value since it is unlikely that a quantum computer with A quantum algorithm for searching unstructured databases 2n qubits will be built in the near future; however, it is of invented by Grover finds a number (or a set of numbers) that interest that classical EDA problems can be sped-up using satisfy a certain constraint expressed by an “oracle”. Here we quantum computing principles. describe a generalization of Grover’s algorithm that finds the A classic problem in binary logic minimization is that simplest expression of a certain form that describes all of minimizing a single-output Boolean function using a solutions. Our particular application here is to a Fixed Polarity Reed-Muller form that satisfies a threshold value constraint, two-level structure consisting of the exclusive-OR of an thus we find a particular FPRM form among all 2n FPRM forms array of ANDs of literals. If there is no constraint on the that has a minimal number of terms. Grover’s algorithm is literals, the expression is called Exclusive Sum of Product implemented in a quantum logic circuit that also contains a expression or ESOP. When all literals are not negated, the subcircuit that expresses all possible FPRM solutions of a given problem is that of finding the Positive Polarity Reed- function. This approach illustrates how fast transforms as Muller form (PPRM). A generalization of PPRM is called known from spectral theory can be combined with quantum the Fixed Polarity Reed-Muller (FPRM) form where computing as a part of an oracle. every variable is either negated or not consistently in the same polarity in every term of the expression. Thus, 1. Introduction FPRM F= a' b ' has the polarity number 3 ( a=0, b = 0 ) The original quantum search algorithm of Grover finds and the equivalent PPRM F= 1排 a b ab has the a single solution, a number that satisfies the quantum oracle F . A quantum oracle can be considered as a polarity number 0 ( a=1, b = 1 ). In binary form, FPRMs represent a two-level circuit Boolean function F with a solution minterm mi that satisfies F (i.e. F( m )= 1 ). Finding a solution can be thus consisting of a set of conjunctions of literals (AND i operations) followed by a multi-input addition modulo-2 visualized as finding a single number with value “1” (a (XOR operation). Such circuits have desirable properties true minterm) in a Karnaugh Map of function F in which including requiring fewer product terms for many classes all other cells have values 0. Obviously, if no additional of functions [8] and desirable testing properties [17,18]. information is available, classical SAT algorithms can be Several heuristic methods have been formulated in the employed that have worst-case exponential behavior. past for both ESOP minimization [22, 23] and for FPRM M When there are >1 solutions, a variant of Grover’s minimization [7,9]. In this work, we present a algorithm can be employed to find all solutions (SAT- fundamentally new approach to FPRM minimization that ALL). is based on quantum logic and the use of Grover’s A generic machine-learning problem can be formulated algorithm. This approach can be extended to several as finding the simplest rule describing a Boolean function canonical XOR forms [7] as well as to the non-canonical representing the set of all solutions. In this work, the rule ESOPs; however, here only the FPRM case is discussed. is expressed as a Fixed Polarity Reed-Muller expression; It can be observed that the method is based on controlling however, variations for other types of expressions such as stages of butterfly diagrams and thus similar approaches Exclusive-OR Sum of Products (ESOP) are also possible. can be applied to any transform that can be described by a In the case of a single solution, our algorithm reduces to butterfly diagram. We present the binary case here, but the classical algorithm of Grover with the “database” being searched that of a binary-valued vector of length 2n

1 This work was supported in part by the Advanced Technology Program (ATP) of Texas under grant 003613-0029-2003. the ternary case [25] is very similar and will be presented characterized by a linear transformation matrix as the in slides. fixed-polarity Reed-Muller transform [19,20,21]. The This paper is organized as follows. Section 2 will structure of this transformation matrix can be expressed as describe the preliminary background for FPRMs and for a Kronecker (or tensor) matrix product where each the quantum logic circuits we use. Section 3 contains a dependent variable is represented by a matrix representing description of the architecture of the quantum circuit used a given polarity. As an example, the transformation to determine FPRM polarity value below some threshold. matrix for the PPRM transformation is given as Section 4 contains details of the quantum circuit designs 轾1 0 n MP1=犏 M Pn = M Pi . used in the architecture of the FPRM processor. Section 5 臌1 1 i=1 contains discussions of applications of the FPRM For an FPRM, the negative polarity matrix used in processor and conclusions and future work are presented forming the transformation matrix M is used to in Section 6. N1 represent complemented variables and that of M P1 is 2. FPRM and Quantum Logic Background used for positive-polarity variables. As an example the This section contains preliminary background transformation matrix for an FPRM of polarity 5 is discussion of two basic topics; the theory of FPRM forms formed as M哪 M M and the basics of quantum logic circuits. N1 P 1 N 1 轾1 1 轾 1 0 轾 1 1 = 犏哪 犏 犏 . 2.1 FPRM Theory 臌0 1 臌 1 1 臌 0 1 A switching function is commonly described in a sum- Due to the Kronecker product decomposition of an of-minterms form that is canonic and in the binary case FPRM transformation matrix, the techniques first represents a collection of conjunctive terms joined by a attributed to [24] may be used to represent the disjunctive operator. As an example, all binary functions transformation in a so-called “butterfly” signal flow-graph of three variables may be expressed in the form (also known as a “fast transform”) where edges represent

F= m0 x 1 x 2 x 3 + m 1 x 1 x 2 x 3 + m 2 x 1 x 2 x 3 + m 3 x 1 x 2 x 3 multiplicative weights (in this case all weights are unity) and vertices represent additions modulo-2, shown in +m4 x 1 x 2 x 3 + m 5 x 1 x 2 x 3 + m 6 x 1 x 2 x 3 + m 7 x 1 x 2 x 3 Figure 1. where mi{0,1} are commonly referred to as the RM Polarity 0 Polarity 1 RM minterms of the function f. Alternatively, such functions coefficient coefficient x3 x2 x1 x3 x2 x1 may also be represented as a Reed-Muller expansion of a 0 0 0 0 a0 0 1 1 1 a0 1 1 1 1 a 1 1 a given polarity using a collection of conjunctive terms 3 1 1 13 1 1 1 1 a2 1 1 0 0 a12 joined by the modulo-additive operator as 0 1 0 0 a23 0 0 1 1 a123 0 0 0 0 a 0 a F= a1排 a x˙ ax ˙ 排 ax ˙ ax ˙x ˙ 1 0 0 1 0 0 1 1 2 2 3 3 12 1 2 0 0 0 1 a 0 a 13 0 0 1 3 0 排a13 x˙ 1x ˙ 3 a 23x ˙ 2x ˙ 3 a 123x ˙ 1x ˙ 2x ˙ 3 0 0 1 a12 0 1 1 1 a2 1 1 1 1 a123 1 1 1 0 a23 where ai{0,1} are commonly referred to as the FPRM Figure 1: Butterfly signal flow-graph x˙ spectral coefficients and i represents a literal in either As is described in detail in [10] butterfly diagrams may complemented or uncomplemented form consistent for all be devised for any given polarity number for the FPRM values of i. The particular assignment of polarities of the expansion. Unfortunately, finding the “best” polarity dependent variables x˙i leads to the polarity number. For number and corresponding maximal number of zero- example, x1 x 2 x 3 0 , x1 x 2 x 3 3 , x1 x 2 x 3 4 , etc. valued Reed-Muller coefficients resulting in the “best” The problem we address here is that of finding a butterfly structure is very challenging. In this work, we polarity number P T such that a Reed-Muller show how the use of quantum logic circuits can give an expansion can be formed where at least T spectral optimal polarity number. coefficients are zero-valued. The solution of this problem allows for the realization of a FPRM expansion that 2.2 Quantum Logic Circuits utilizes no more than T conjunctive operations and is a Quantum logic circuits utilize quantum-bits (or qubits) problem of interest for the logic synthesis and verification that may be implemented as the state of electron spin, community. photon polarization, or some other quantum phenomena The two expressions shown previously are both affine [12]. A qubit is denoted in Dirac notation by |0> +  |1> functions that are related by a linear transformation. This where  and  are complex numbers such that || 2 + || 2 transformation is well-known and commonly =1, |a|2 = a a* and a* is the complex conjugate of a. Here ||2 is the probability of measuring state |0> and ||2 is the a b >. It is noted that this gate operates over arbitrary probability of measuring state |1>. Quantum circuits are complex-valued states as well as basis states. By represented as a cascade of qubit operators and have some multiplying the matrix of CNOT by the input state [   similarity to classical circuits although the underlying ] T we obtain vector [   ] T, illustrating operation of a physical interpretation is different. In a quantum logic permutation gate on arbitrary states. When this (or any circuit each horizontal line represents an instance of a other permutation gate) operates inside a quantum oracle, qubit and the progression from left to right along the line it operates on arbitrary quantum states not only basic represents the passage of time. states. A gate operation encountered while traversing a qubit It is a significant fact that the unitary quantum gates line from left to right represents a transformation for that such as the one described by Equation (1) can realize any particular qubit. Such transformations are characterized quantum logic function (including standard binary). as gates and they are traditionally named after their Every non-reversible Boolean or multiple-valued circuit inventor. In the architecture described in Section 3, we C1 (with arbitrary numbers of inputs and outputs) can be utilize the CNOT or Toffoli gate and a generalized transformed to a reversible circuit C2 (described by a version of the Toffoli gate. permutation matrix). This generally requires adding bits

Here, we use the symbol  to denote the Kronecker to both the input and output of C2. Circuit C2 is equivalent product (Kronecker multiplication) operation. One of the to C1 in the sense that over the original input/output bits, most important quantum gates is the quantum XOR gate C2 produces the same input-output mapping as C1. Bits (also called the Feynman gate or Controlled-Not gate - added to the inputs of circuit C2 are the so-called ancilla CNOT). This gate allows input states of |0>  |0> = |0>| bits and are initialized to constants. Ancilla bits are 0> = |00> and |01> to appear unchanged at the outputs, always necessary to convert a non-reversible logic but interchanges the states |10> and |11>. This is function to a reversible function over more variables, commonly represented through the use of the 4 4 however we strive to add as few of them as possible. C2 permutation matrix in equation (1) below. Columns (from has also non-used output bits, called garbage bits. left to right) correspond to the input states of the gate, and A P  A rows (from top to bottom) correspond to the output states B Q  B each in the order of |00>, |01>, |10>, and |11>. Thus the C R  AB  C transition from a basis input state of |11> to a corresponding basis output state of |10> is represented as Figure 2: A 3*3 Generalized Toffoli Gate. Symbol + stands a “1” at the intersection of the fourth column and third for GF(2) addition for binary quantum and modulo-3 row of the matrix. The basis state vector of state |10> = [0 addition (GF(3) addition) for ternary quantum case. 0 1 0] T, is a Kronecker product of states |1> = [0 1] T and T Observe in the unitary matrix for the CNOT gate (Eqn. |0> = [1 0] . (T stands for vector transpose). When only 1) that when the control bit a=P (the first one from top) basis states are used we remain in the realm of classical has value |0> the gate does nothing, the controlled bit b reversible logic. When vectors represent arbitrary (the lower bit) has the same value on input and on output. superpositions of basis states, we are in the quantum However, when the first bit a has value |1>, the controlled domain. Let us analyze the operation of this gate with a bit b is inverted (since1�b b ' ). Therefore this gate is basis input state |10>. By multiplying the matrix of the called Controlled-NOT, which means that the controlling CNOT gate by the input state |10> = [0 0 1 0] T we obtain vector [0 0 0 1] T, as follows: bit controls the NOT operation. Similarly a 3-qubit 轾1 0 0 0 轾 0 轾 0 (universal) Fredkin gate is called a Controlled-Swap, 犏 犏 犏 0 1 0 0 0 0 because when the first bit P = a (control) is |0> the gate 犏 犏= 犏 犏0 0 0 1 犏 1 犏 0 (1) 犏 犏 犏 does nothing, which means that the lower two bits just 臌0 0 1 0 臌 0 臌 1 transfer input values; Q = b, R = c, and when the control bit is |1>, these bits are swapped; Q = c, R = b. Thus the In this example, the input qubit pair is |10> = [(0)| Fredkin gate realizes functions over the basis states as the 0>+(1)|1>] [(1)|0>+(0)|1>] and the corresponding input following reversible function, P= a , vector is represented by the coefficients shown in Q= ( a '仝 b ) ( a c ) R= ( a '仝 c ) ( a b ) parentheses. Logically, the CNOT gate can be described , . A binary by two equations: P= a , Q= a b , where bit a is Toffoli gate (Figure 2) is described by equations: P= a , Q= b R= ( a倥 b ) c referred to as the control bit and b is the controlled or data , . Symbol  denotes Boolean AND, bit. Input variables are a and b, output variables are P and symbol  Boolean OR and symbol  Boolean XOR. This Q. In Dirac notation this operation is expressed as |a, gate can be extended to ternary Toffoli gate with GF(3) operations replacing GF(2) operations and used to build spectral coefficients corresponding to the function and ternary butterflies for ternary Reed-Muller expansions and polarity vector. Two tasks are accomplished in the Cost transforms. A generalized Toffoli gate can be built (in Function and Comparator block. First, the number of binary or MV logic) where the number of control inputs is ones in the vector of spectral coefficients is counted. arbitrary. The Toffoli gate is also called the Controlled- Second, a comparison of the number of ones with the Controlled-NOT, since the NOT operation is controlled threshold value is accomplished. If the number of ones in by a product of inputs a and b. Feynman, Fredkin and the coefficients is less than the threshold value, the Cost Toffoli gates, named after their early inventors, are Function and Comparator block will output a one, examples of controlled gates. Controlled gates are also otherwise zero. The corresponding inverse blocks, created for multi-valued and hybrid quantum circuits. In Inverse FPRM processor, Inverse Cost Function and hybrid logic, a ternary bit A may control a binary bit B or Comparator, accomplish the inverse of these functions. a binary bit may control a quaternary bit, but every wire is for one radix logic only, binary, ternary or quaternary 3.2 Grover’s Algorithm throughout the entire circuit. We have designed quantum In the architecture of Figure 3, we use Grover’s oracles for all these types of gates. algorithm to evaluate the condition that the number of one-values in the spectral coefficients is less than the 3. Proposed Architecture threshold value. In the following, we gave a brief In this section, we introduce the proposed architecture introduction to Grover’s algorithm. Assume you have a n n for finding minimum FPRM system with states N = 2 labeled S1, S 2 ,..., SN . These 2 states are represented by n -bit strings. Assume there is a 3.1 Architecture unique marked element Sm that satisfies a condition The proposed architecture is shown in Figure 3. There C( S )= 1, and for all other states C( S )= 0 . Assuming are 4 blocks in the architecture, FPRM processor, Cost m Function and Comparator, and corresponding inverse that C can be evaluated in unit time. Grover’s algorithm blocks Inverse FPRM processor, Inverse Cost Function can minimize the number of evaluations for C [3]. A and Comparator. quantum register is just a group of qubits, all part of the Polarity same quantum mechanical system. Just as an n -bit vector p p n pa a register is capable of representing 2 distinct values, so b pb p p c c n n |0> Yes/No too will an -bit quantum register assume one of the 2

b0 b0 basis states when measured [1]. Threshold b Inverse b 1 Cost Counter 1 value b Cost Counter b b2 and b2 The idea of Grover's algorithm is to place a register in 3 and 3 |0> Comparator |0> Working Comparator an equal superposition of all states, and then selectively qubits |0> |0> d e0 invert the phase of the marked state, followed by 0 d0 e1 d1 d1 inversion about the mean operation a number of times. e2 d2 d2 e Inverse Selective inversion of the marked state, followed by the d FPRM 3 d 3 FPRM 3 Processor e d 4 Processor d inversion about the mean is also referred to as the Grover 4 e 4 d 5 d 5 5 Operator. The Grover Operator has the effect of e6 d6 d6 e7 d7 d7 increasing the amplitude of the marked state by O(1 N ) function spectrum Figure 3: Quantum Architecture for FPRM Oracle for . Therefore, after O( N ) operations, the probability of Grover’s Method measuring the marked state approaches one [2]. Observe The input of the FPRM processor is the vector of that we did not modify Grover’s algorithm at all in this minterms (true for false) for a given Boolean function and work, we just showed that it can be extended by a special the polarity vector. The output of the FPRM processor is way of building the oracle. This is true for many other the RM spectrum coefficients for the given Boolean applications as well. function and polarity specified by (pa, pb, pc). The detailed Placing the register in an equal superposition of all architecture for the FPRM processor is presented in next states can be accomplished by applying the Walsh- section. Hadamard operator [3]. Selective inversion of the marked There are two input busses for the Cost Function and state in the Grover Operator means if the system is in any Comparator block, the threshold value and the polarity state S and C( S )= 1 , we rotate the phase by p radians, n vector. The FPRM processor requires the 2 truth vector otherwise we leave the system unaltered. This operation n of the Boolean function and produces the 2 FPRM can be accomplished with the Oracle as described in [4]. Applying the inversion about the mean is equivalent to The FPRM processor accepts a vector corresponding to applying an operation whose matrix representation is: the Boolean function and a polarity vector and outputs

Aij = 2 N if i j and Aii = -1 + 2 N to the quantum FPRM spectral coefficients. The core part of the FPRM register [3]. A block diagram for quantum circuit of processor is the “butterfly” quantum circuit. The polarity Grover’s algorithm is shown In Figure 4. of the “butterfly” is controlled by the polarity bits. Figure O(N1/2) 5 shows the 1-variable FPRM processor which has a 2-bit Measured Input Walsh- function input ([d , d ]) and a 1-bit polarity input (p). If Hadamard polarity for 1 2 which satisfied oracle workspace G G G p = 0 , the output is positive polarity coefficients, |q> Grover Operator otherwise, it is negative polarity coefficients. o Inversion Figure 6 shows the 3-variable FPRM processor. There r about mean a are 3 polarity bits and 8 input lines for 3-variable c l processor. There are 3-levels in the processor that e correspond to a 3-level “butterfly” diagram such as those Figure 4: Grover’s Algorithm Block Diagram shown in Figure 1. 4. Circuit Design 3 bit for polarity In this section, we present the detailed implementation pa for blocks described in the overall architecture. pb pc d e 4.1 FPRM Processor 0 0 d e The butterfly diagrams described previously for the 1 1 d2 e2 “fast” calculation of the FPRM spectral coefficients may d 3 e3 be represented as quantum logic circuits comprised of d4 e4 d cascades of generalized Toffoli gates. Furthermore, all 5 e5 d e possible butterfly diagrams for any given polarity may be 6 6 d e described as a single quantum logic circuit with the 7 7 polarity number provided as an input to the circuit. 23 bit for data - 23 bit for spectrum of Figure 5 contains the butterfly diagrams for all functions Boolean Function this Boolean function of one. The diagram on the left represents the polarity-0 for given polarity transform while that on the right represents the polarity-1 Figure 6: 3-variable FPRM Processor transform. Values d1 and d2 represent binary truth 4.2 Cost Counter and Comparator vectors for all possible functions of 1-variable. The right There are two tasks to be accomplished in this block. side of each butterfly expresses the RM spectral The first task is to count the number of ones in the coefficients in terms of the original function values. The spectral coefficients and secondly, to compare the number quantum logic circuit is a realization of the composite of ones with the threshold value. If the number of ones in function formed using the polarity value p to select which the coefficients is less than the threshold value, the circuit of the two sets of coefficients are requested as shown in will output one, otherwise zero. the expressions on the right side of the quantum logic The “count ones” function can be accomplished using a circuit. tree of half-adders and full-adders and is also known in Just as butterfly diagrams representing RM transforms the arithmetic community as an 8:4 compressor. The of more than 1-variable can be formulated based on the quantum implementation for the half-adder is shown in Kronecker product, so can the quantum logic circuit also Figure 7 and the full-adder is shown in Figure 8. be expanded for larger functions. Figure 6 depicts an x x y expanded FPRM processor for 3-variable functions. y s p=1 p=0 d z s d d d d 1 1 1 2 1 0 c 0 c d d d d2 d2 2 1 2 p Figure 7: Half-adder Figure 8: Full-adder d 1 p'd1+p(d1 d2) The 8:4 compressor based on a tree of full-adders and d p'(d d )+pd 2 1 2 2 half adders is shown in Figure 9. The compressor circuit Figure 5: RM Transformation Butterflies and has two-levels with the first level consisting of two full- Corresponding Quantum Logic Circuit adders and one half-adder which add two 3-bit values and one 2-bit value parallel and form three 2-bit numbers. The second level is an adder tree that compresses the 6-bit value from the first stage into a 3-bit value. The detailed As described in the previous section, this circuit quantum implementation is shown in Figure 10 (in the consists of a compressor and a comparator. The leftmost box). This result along with the threshold value compressor will have a delay and cost proportional to the then serves as input to the comparator. number of stages in the compressor tree. In the small 3- e 0 ss0 sss variable example described previously, 3:2 and 2:2 binary 0 s0 e1 A F cc compressors are used. For larger functions, the 0 A

e F 2 ccc 0 compressor tree can be optimized by using larger

e ss1 A 3 s1 compressors and compressors that are based on the signed H

e4 A F cc1 binary digit set. e5 cccc s2 1 The signed binary number system still uses a radix- ss sss1 A 2 H e6 A A value of 2 but allows for a digit set of {1,0,1} , where 1 F H cc ccc e 2 1 s3 7 represents the value of -1 (negative unity). This is Figure 9: Block diagram of 8:4 Compressor Tree redundant in that some values may be expressed with To build the comparator, we first derive the Boolean two-different digit strings (eg. +1=01=11 ). Efficient function for a comparator that compares two unsigned 4- compressors may be designed using the signed binary bit numbers ( S= s3 s 2 s 1 s 0 and B= b3 b 2 b 1 b 0 ). We first compare adder as a component. Because three distinct digits are used, it is convenient to implement the signed digit adder the Most Significant bit (MSb), if s3 and b3 has different as a quantum-ternary-valued circuit. We also note that s� b 1 b = 1 B> S s value ( 3 3 ) and 3 , then we know . If 3 these types of adders have the desirable property of and b3 are the same ( s3� b 3 0 ), then we check the next constant delay regardless of wordlength and can be used significant digit. This can be carried out until the Least as the basis for other high-speed arithmetic circuits. Significant bit (LSb) is reached. Based on that, we can Table 1 first appeared in [26] and illustrates how the write the Boolean function as the following: redundant digit set is exploited to prevent long carry

out= ( s3排 b 3 ) b 3 ( s 3 排 b 3 )( s 2 b 2 ) b 2 排 ( s 3 b 3 )( s 2 欧 b2 ) ripples.

(s1排 b 1 ) b 1 ( s 3 欧 b 3 ) ( s 2 排 b2 )( s 1 b 1 )( s 0 b 0 ) b 0 Based on the formula, we design the quantum circuit as shown in Figure 10 (in the rightmost box). The inverse circuits are just mirror reflections of their basic circuits, and thus the inverse butterfly is drawn by mirroring in inverse order all gates from the butterfly. This is because in binary reversible logic the generalized Toffoli gates, Toffoli, Feynman and NOT gates are its own inverses. This is not true in ternary logic, but designing inverse In Table 1, the values s1 and c1 occur when either of circuits is also straightforward in this logic [5]. the digits at next position to the right are negative while Count ones e 0 s2 and c2 occur when neither of the digits to the right e 1 ss e 0 2 are negative. The portion of the circuit that performs this cc |0> 0 computation is called the pre-condition. e3 e4 ss1 Our implementation of this adder as a ternary-quantum e5 cc |0> 1 circuit is shown in Figure 11 where we use the following e 6 ss 2 sss0 s e7 0 encoding scheme: 0 0, 1 1, 1 2 . To build the cc sss |0> 2 1 ccc s s |0> 0 1 signed-digit adder, logic to differentiate between 1 and ccc |0> 1 s s |0> 2 2 is necessary. The subcircuit for computing the pre- cccc1 s |0> 3 condition that “either input is negative” is based on the |0> generalized Toffoli gates as shown in upper-left box in b3

b2 Figure 11.

b1 Based on above table, the sum and carry values are: (0) (0) (0) (0) (2) b0 A+ B + A B = s2 Comparator 2 �s2 s 1 Figure 10: Quantum Implementation of 8:4 Compressor and C= S(2放 ( A B )) = S 欧 (2 ( A B )) Comparator i i i i 欧 5. MVL Compressor Tree Implementation where , are GF add and multiplication respectively. From the formulas, the entire adder can be problems for both binary, ternary and hybrid implemented as shown in Figure 11. The lower-left box binary/ternary algorithms/circuits. One of the aims of our shows the implementation for the sum digit and the work is to discover practical and efficient methods of lower-right box indicates the portion for the for the carry designing and laying out binary, multi-valued and hybrid digit. quantum circuits not for random benchmarks but for Pre-condition practical blocks and architectures.

Ai-1 2 2 Ai-1

B 2 2 B i-1 i-1 8. References 0 +2 +2 +1 [1] C. Williams, S. Clearwater, Explorations in Quantum Computing,

Ai 0 0 Ai Springer-Verlag, New York, Inc.

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