Study guide of Final Exam CS 147Fall 2007
Exam Time: Cs147 – Wednesday Dec 12 2007 09:45AM to 12:00AM Cs157 – Tuesday, Dec 18 2007 07:15AM-09:30AM Note: Please bring 882E Scantron!
TYPES OF QUESTIONS:
- Multiple Choice (4-6 answers possible, enter one response only)
- Short Answer (1-2 sentences - no dissertations, please)
- Computation (e.g., convert a binary number to its decimal value, do signed or unsigned addition, subtraction, multiplication, or division) - Diagram (timing diagrams, show how the stages are arranged in a pipeline)
1. Define the terms: Pipelining, control bus, ALU, CPU, Computer instructions, decoder, multiplexer, MMU.
2. Give the following boolean function F=A*BC*+A*BC+AB*C a) Develop an equivalent expression using only NAND operations, and draw the logic diagram. b) Develop an equivalent expression using only NOR operations, and draw the logic diagram.
3. For the logic function of F(A, B, C, D)=(0, 1, 3, 4, 5, 7, 8, 10, 12, 14, 15) a) Show the truth table. b) Write the SOP form. c) Write the POS form. d) Simplify by K-map.
4. Is there a Boolean function that cannot be realized using only NAND of OR gates? If so, give a simple example; If not, explain.
5.(a)Implement the following Boolean expression using only NAND gates.
F A B C A BA C
(b) Construct a NOR function by only NAND gates.
6. True or False
(T/F)(a)A larger block size increases the hit rate for accesses that display spacial locality. (T/F)(b) Including registers would probably reduce the number of loads/stores, but would not affect the instruction fetches, which comprise the majority of memory accesses. (T/F)(c) The miss ratio varies from program to program. (T/F)(d) For a high hit ratio, average memory access time is closer to the access time of the slower memory. (T/F)(e) To meet the cost goal of the two level memory organization, since the faster memory is much more expensive than the slower, the size of faster must be much larger than size of slower memory.
7. Describe the function and the operation of a bus in a microcomputer.
8. What are the advantages and disadvantages of a single-bus structure?
9. Implement the function, F, shown in the Karnaugh map below using only an 8-to-1 MUX and using A, C, and D as control inputs. Assume compliments are available.
10. How is the main memory organized?
11. Describe the operation of the CPU when writing a word of data into the main memory.
12. What are the functions and the structure of the CPU?
13. What is the purpose of the program counter?
14. Give the Karnaugh map of the following functions: a) f=x*y*z*+xy*z+xyz+x*yz*+x*yz b) f=a*b*cd*+bd+acd*+a+d
15. What are the cache memory? Define the term hit ratio. 16.(a) Determine the inputs I0, I1, I2, I3 of an 4-input multiplexer to implement f(x, y, z)=x*yz+xy*z*+xz (b) Implement the following Boolean function using an 8:1 multiplexer.
F ACD BCD BCD ACD 17. Determine the inputs I0,...,I7 of an 8-input multiplexer to implement f(w, x, y, z)=(2, 3, 5, 6, 8, 10, 11, 12, 13, 14)
18. Design a ROM to convert binary inputs to gray code output (4-bit)
19. You are required to design a logic network that can display the characters in “HELLO” on a seven-segment display unit. Write the truth table for the output functions C0-C6, and implement them using a ROM of appropriate size (clearly specify the size). (Hint: you only need two inputs, e.g. A and B. Use input combination 00 for H, 01 for E, 10 for L and 11 for O, and of course you have seven outputs.)
H: E: L: O: C0 C0 C0 C0
C5 C6 C1 C5 C6 C1 C5 C6 C1 C5 C6 C1
C4 C2 C4 C2 C4 C2 C4 C2
C3 C3 C3 C3 20. Implement a converter to convert six-bit binary numbers into BCD, using a ROM of the appropriate size.
21. Implement the following using a)ROM, b) a PLA. i) A 4*4 multiplier. ii) A circuit that squares that three-bit number input to it.
22. A divide-by-three circuit is needed to divide the input four-bit binary number to generate the quotient and the remainder. Draw the truth table for the circuit and implement the circult with the PLA of minimum size.
23. Implement the following multiple-output function using the minimum PLA: F(A, B, C, D)= m(0, 2, 8, 10)+d(1, 3, 9, 15) F(A, B, C, D)= m(3, 6, 7, 14)+d(0, 8, 11) F(A, B, C, D)= m(1, 5, 11, 13)+d(2, 7, 12)
24. Simplify the following functions: F(A, B, C, D)= m(3, 6, 7, 14)+d(0, 8, 11) F(A, B, C, D)= m(1, 5, 11, 13)+d(2, 7, 12)
25. Given a JK flip-flop packaged in a chip, is it possible to convert it to a D flip-flop using external logic? If not, why not? What about the reverse, that is, converting a D flip-flop into a JK one?
26. A machine has a 32-bit byte-addressable virtual address space. The page size is 8 KB. How many pages of virtual address space exist?
27. A computer has 16 pages of virtual address space but only four page frames. Initially, the memory is empty. A program references the virtual pages in the order 0, 7, 2, 7, 5, 8, 9, 2, 4 a. which references cause a page fault with LRU? b. Which references cause a page fault with FIFO?
28. Compare internal fragmentation to external fragmentation. What can be done to alleviate each?
29. (a) Convert -1234 base 10 to its sixteen-bit one's complement binary equivalent.
(b) Convert -2345 base 10 to its sixteen-bit two's complement binary equivalent.
30. What is meant by the term "duality" in Boolean algebra? What is the dual of the theorem X+X'Y=X+Y?
31. You run two different programs, and the miss ratio comes out different. Is this OK, or should you re-run your program to try again? (Briefly) justify your answer.
32. 33. You are designing a multiprocessor network with 1024 nodes using a hypercube interconnection scheme. Of what degree is the hypercube?
34. Using only full adders and half adders, show how you would build a circuit which will accept three 3-bit binary numbers A, B, and C (bits A2, A1, A0, B2, B1, B0, C2, C1, C0), and produce their sum S (a 5-bit binary number with bits S4, S3, S2, S1, S0). 35. MIMD occurs as an acronym in Flynn's taxonomy. What does it stand for? Give a brief description and an example. 36. Complete the timing diagram for the circuit shown below. Delays need not be shown.
37. A state diagram and a state assignment for a synchronous sequential circuit are shown below. Complete the design of this circuit using JK flipflops, and draw a circuit diagram. Show your work. The circuit should have a negative edge sensitive clock and an asynchronous active-low clear input which will place it in state A. Call the input X and call the output Q.
State | Q1 Q0 ------+------A | 0 0 B | 0 1 C | 1 0 D | 1 1 38. A program with five virtual pages numbered from 0 to 4 references its pages in the order: 0 1 2 3 0 1 4 0 1 2 3 4 1. Using FIFO replacement, compute the number of page faults with 3 frames. Repeat for 4 frames. 2. Compute the number of page faults under LRU, and the optimal algorithm.
Solution:
1. The number of page faults is 9 with 3 frames, 10 with 4.
The point of the exercise is to see that the performance of LRU, NRU, clock algorithm and optimal all offer better performance with larger number of frames
39. Draw the shape of the memory hierarchy. Fill in as much detail as you are able.
40.What is the difference between first-fit and best-fit, in the context of dynamic memory management?
41. Assume that you have free memory partitions of size 100KB, 500KB, 200KB, 300KB, and 600KB (in this order) and that memory requests for 212KB, 417KB, 112KB, and 426KB arrive. a) Show how a First-Fit allocation algorithm would assign the requests to free memory. Clearly show the size of each piece of memory after each request arrives. b) Show how a Best-Fit allocation algorithm would assign the same requests. Clearly show the size of each piece of memory after each request arrives. c) Show how a Worst-Fit allocation algorithm would assign the same requests. Clearly show the size of each piece of memory after each request arrives.
42.How does pipelining improve processor performance?
Answer: It increases throughput. Pipelined designs exploit parallelism -- it makes the throughput of instruction fetch and execute faster.