ECE 591 E - ASIC Verification Fall 2002 Course Syllabus

Introduction

Welcome to ASIC Verification, I am pleased to be working with Dr. Paul Franzon on bringing this class to NCSU. To let everyone know a little about myself, I am a verification engineer for IBM Corp. I have a background in ASIC verification, ASIC design, and tools. I have worked for IBM Corp. for approximately 9 years. My latest responsibilities include being the verification lead for a multimillion gate (approximately 40 million) next generation Network Processor.

My e-mail is: [email protected]

My phone number is: (919) 254-0820

I tend to not be at my desk throughout the day, so I would prefer that you send questions and correspondence via e-mail.

Office hours will be before class (6:30 – 7:30 PM, Mon/Wed).

Course Layout

There will be at least 3 homework assignments (maybe more), these homework assignments will consist of 15% of a students overall grade. The homework will be handed out, and you will have 1 week to complete the assignment. Late homework will not be accepted unless prior approval and arrangements are made.

There will be 3 working labs. These labs will consist of 40% of a students overall grade. Each lab will be different in duration based on its complexity. Each lab is constructed so that each student must find all the bugs in the design in order to achieve a 100%. But because all bugs are found, does not necessarily deem the student achieves a 100%. Each student is required to hand in an analysis of the bugs and how they were found.

There will be 2 exams – a midterm and a final. Each exam will consist of 20% of a student’s grade.

Cheating will not be tolerated. Anyone found cheating will result in a zero for that lab and be turned in to the Academic Review Committee. Course Syllabus

Class Topic Chapters HW/Labs in Book 1 Course Introduction Chapter 1 2 What is Verification Chapter 1 3 Verification Tools Chapter 2 HW 1 Assigned 4 Verification Plan – Strategies Chapter 3 5 Verification Plan – Testcases Chapter 3 HW 1 Due/HW 2 Assigned 6 Verification Plan – Testbenches Chapter 3 7 Architecting Testbenches Chapter 6 HW 2 Due/HW 3 Assigned 8 Architecting Testbenches Chapter 6 9 Architecting Testbenches Chapter 6 HW 3 Due/Lab 1 Assigned 10 Architecting Testbenches Chapter 6 11 Lab 1 Solution Discussion / Chapter 6 Lab 1 Due Architecting Testbenches 12 Architecting Testbenches Chapter 6 13 EXAM #1 – Chapters 1,2,3,6 14 Lab 2 Overview / Stimulus and Chapter 5 Lab 2 Assigned Response 15 Review EXAM #1 16 Stimulus and Response Chapter 5 17 Lab 1 Due/Lab 2 Assigned 18 Stimulus and Response Chapter 5 19 Stimulus and Response Chapter 5 20 Special Topic Day Online NetSeminar on new verification technologies 21 Lab 2 Solution Discussion / Chapter 5 Lab 2 Due Stimulus and Response 22 Behavioral HDL Chapter 4 23 Behavioral HDL Chapter 4 24 Lab 3 Overview / Behavioral HDL Chapter 4 Lab 3 Assigned 25 Simulation Management Chapter 7 26 Special Topic Day Online NetSeminar on new verification technologies 27 EXAM #2 – Chapters 5,4,7 Chapter 6 28 Lab Day 29 Review Exam #2 Exam Week Lab 3 Presentation/Escape Analysis