Winter 2006
To: SECS Faculty and CSE 378 students From: R. E. Haskell, Professor of Engineering Subject: CSE 378 – Computer Hardware Design
Course Title Computer Hardware Design
Prerequisites CSE 171 and either major standing or conditional major standing
Text and Materials Required: Digital Logic and Microprocessor Design with VHDL, by Enoch O. Hwang, Thomson, 2006. Required: A USB portable storage device with capacity of 64 MB or more. Optional: Spartan-3 board available from www.digilentinc.com Enter OU378 in the Value code field References: . VHDL Tutorial: Learn by Example http://www.cs.ucr.edu/content/esd/labs/tutorial/ . VHDL Tutorial http://www.aldec.com/Downloads/ . Xilinx Spartan-3 FPGA Family: Data Sheet (available on class website) . S3 Board Reference Manual http://www.digilentinc.com/Materials/BoardProducts.html . The FPGA Journal: www.fpgajournal.com . www.google.com
Class Time Classes will be held on Tuesday and Thursday from 5:30 p.m. to 7:17 p.m. The labs will be held in Room 133, Science and Engineering Building (SEB). Labs will start on Tuesday, January 17, 2006.
Course Objectives By the end or this course a successful student will be able to:
Design combinational logic circuits using VHDL Design sequential logic circuits using VHDL Describe how combinational and sequential components can be used to design a datapath and control unit for performing logic operations Describe how memory operates and is addressed Synthesize VHDL designs to FPGAs Simulate VHDL designs using a modern simulator Design dedicated microprocessors using VHDL and synthesize them to an FPGA
1 Course Emphasis This class will emphasize the use of VHDL in the design of digital systems. VHDL (VHSIC Hardware Description Language) had its origin in the U. S. Government's Very High Speed Integrated Circuits (VHSIC) program. It has since become an IEEE standard. It is widely used in industry to design complex digital circuits that will be implemented in either Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs), or Complex Programmable Logic Devices (CPLDs).
List of Topics: Digital Logic Circuits Combinational Logic Latches and Flip-Flops Circuits Sequential Logic Circuits Standard Combinational Standard Sequential Components Components and RAM Timing Datapaths Implementation Control Units Technologies Dedicated Microprocessors
In addition to the lectures the class will include a hands-on laboratory in which students will design digital circuits using VHDL and synthesize them to Xilinx FPGAs. Each of the labs will involve a digital design using VHDL.
Design Project
In addition to the eight labs each student will participate in a group project and demonstrate an original VHDL design by means of a PowerPoint presentation given to the class, a presentation poster that may be displayed publicly, and a project report.
Exams There will be two exams during the semester.
Grading
Grading will be based of the following:
Labs 25% (8 labs) Homework 10% Exam 1 20% Exam 2 20% Design Project 25% 100%
To pass the course a student must earn a passing grade (60% or higher) in the laboratory and on the Design Project, as well as in the course.
Office Hours: 4:00 – 5:15 p.m. Tues. and Thurs.
2 115 Dodge Hall Tel: 248-370-2861 email: [email protected] Class Web Site: http://www.cse.secs.oakland.edu/haskell/ Click on CSE 378 and CSE 378
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