Week 7: Common-Collector Amplifier, MOS Field Effect Transistor

ELE 2110A Electronic Circuits

ELE2110A © 2008 Lecture 07 - 1 Topics to cover … z Common-Collector Amplifier z MOS Field Effect Transistor – Physical Operation and I-V Characteristics of n-channel devices – Non-ideal effects – P-channel devices and other types z Reading Assignment: Chap 14.1 – 14.5 of Jaeger and Blalock , or Chap 5.7 of Sedra & Smith And Chap 4.1 – 4.4 of Jaeger and Blalock or Chap 5.1-5.2 of Sedra & Smith

AC ground Input Output

Source

Load AC/Small signal equivalent

RL = R4 || R7

Also called “Emitter follower” RB = R1 || R2

g R >>1 v (β +1)R In most C-C amplifiers, m L CC o L Avt = = CC v rπ +(β +1)R ∴A ≅1 b L vt g R CC m L Output voltage at emitter follows ∴ Avt ≅ for β >>1 1+ g R input voltage, hence the circuit is m L named Emitter Followers.

Input resistance looking into the Overall voltage gain is base terminal is given by ⎛ ⎞⎛ ⎞ ⎛ ⎞ v ⎜ v ⎟⎜ v ⎟ ⎜ v ⎟ CC o ⎜ o ⎟⎜ b ⎟ ⎜ b ⎟ v Av = = ⎜ ⎟⎜ ⎟ = Avt ⎜ ⎟ CC b π v ⎜ v ⎟⎜ v ⎟ ⎜ v ⎟ R = =r +(β +1)R ⎜ ⎟⎜ ⎟ ⎜ ⎟ in L i ⎝ b ⎠⎝ i ⎠ ⎝ i ⎠ i ⎡ ⎤ ⎢ R CC ⎥ ⎢ Rin ⎥ = CC ⎢ B ⎥ Avt ⎛ ⎞ ⎢ ⎜ CC ⎟ ⎥ ⎢ R + ⎜ R R ⎟ ⎥ ⎣⎢ I ⎝ B in ⎠ ⎦⎥

ELE2110A © 2008 Lecture 07 - 5 Example 1 z Problem: Find overall voltage gain. z Given data: β=100, Q-point values: IC=245uA, AC ground −1 VCE=3.64V, gm=9.8mΩ , rπ=10.2kΩ. z Assumptions: Small-signal operating conditions. z Analysis:

R = R R =104kΩ B 1 2 R = R R =11.5kΩ L 4 7 R =r +(β +1)R =10.2kΩ+101(10.2kΩ)=1.17MΩ in π L

⎡ ⎤ gmR ⎢ R RCC ⎥ L ⎢ B in ⎥ A = =0.991 A = A ⎢ ⎥ =0.956 vt v vt ⎛ ⎞ 1+ g R ⎢ R + ⎜ R CC ⎟ ⎥ m L ⎢ ⎜ R ⎟ ⎥ ⎣⎢ I ⎝ B in ⎠ ⎦⎥

For small-signal operation, magnitude of vbe < 5 mV. ⎛ ⎛ ⎞⎞ v r v ⎜ ⎜ R ⎟⎟ b π b v ≤0.005⎜1+ g ⎜ R + L ⎟⎟ v =irπ = = b ⎜ m ⎜ L ⎟⎟ be r +(β +1)R R ⎜ ⎜ β ⎟⎟ π L 1+ g R + L ⎝ ⎝ ⎠⎠ m L ≅0.005(1+ g R )V rπ m L

If g R >> 1 , v can be increased beyond 5 mV limit. m L b Emitter followers can be used with relatively large input signals!

⎛ ⎞ v ⎜ v ⎟ x ⎜ x ⎟ i =−i− βi = − β⎜− ⎟ x ⎜ ⎟ R +r ⎜ R +r ⎟ th π ⎝ th π ⎠ R +r R CC π r ∴R ≅ th = π + th out β +1 β +1 β +1 α

βR R CC th 1 th Rout = + ≅ + gm +1 gm β +1

CC 1 R connected to base R ≅ + out g β +1 m

Rth = RI || RB Small output resistance!

ELE2110A © 2008 Lecture 07 - 8 Example 2 z Problem: Find output resistance. z Given data: β=100, Q-point values: IC=245uA, VCE=3.64V, gm=9.8mS, rπ=10.2kΩ, rο=219kΩ. z Assumptions: Small-signal operating conditions. z Analysis:

α R CC th 0.990 1.96kΩ Rout = + = + =120Ω gm β +1 9.80mS 101

i CC z Terminal current gain A = 1 = β +1 it i

ELE2110A © 2008 Lecture 07 - 10 Summary of Emitter Follower z Voltage gain: Close to unity. z Input resistance: Large z Output resistance: Small z Input signal range: relatively large z Terminal current gain: Large (β+1) z Excellent for use as a voltage buffer

Without buffer: Rs RL Vs Vo v = v << v RL o s s if RL << Rs Rs + RL With buffer: ⎛ R ⎞ R ⎜ i ⎟ L vo = ⎜ vs ⎟A ⎝ RS + Ri ⎠ RL + RO

≅ Avs = vs for Ri >> RS and RO << RL

Requirement of voltage buffer: - High input resistance - Low output resistance - Unity voltage gain

C-E Emitter Degenerated C-C C-B

(RE=0) C-E Terminal Inverting Inverting & 1 Non-inverting & Voltage Gain & large moderate Large Input Moderate Large Large Low Resistance

Output Moderate Large Low Large Resistance

Input Voltage Small Moderate Large Moderate Range

Terminal Inverting Inverting & Large Non- 1 Current Gain & Large inverting & Large

741 Op-amp - Built from single stage amplifiers

ELE2110A © 2008 Lecture 07 - 14 Topics to cover … z Common-Collector Amplifier z MOS Field Effect Transistor – Physical Operation and I-V Characteristics of n-channel devices – Non-ideal effects – P-channel devices and other types

ELE2110A © 2008 Lecture 07 - 15 Introduction z Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET) is the primary component in high-density chips such as memories and microprocessors z Compared with BJT, MOSFET has – Higher integration scale – Lower manufacturing cost – Simpler circuitry for digital logic and memory – Inferior analog circuit performance in general z Recent trend: more and more analog circuits are implemented in MOS technology for –lower cost – integration with digital circuits in a same chip (mixed-signal IC)

z Four terminals: – Gate, Source, Drain and body

z Two types – n-Channel (NMOS) – p-Channel (PMOS)

z The minimum value of L is referred as the feature size of the fabrication technology. – E.g., 45nm is used for Intel’s Core 2 processors.

symbol

z Body is commonly tied to ground z When the gate is at a low voltage (VGS ~ 0): – P-type body is at low voltage – Source-body and drain-body diodes are OFF (reverse bias)

–iG=0 (always), iDS = 0 z Depletion region between n+ and p-type bulk – No current can flow, transistor is said in “Cutoff” mode

z Vertical electric field established z Under the gate-oxide: – Holes (positive charges) repelled – Depletion region under gate oxide formed

z Electrons (minorities in the p region) attracted by the electric field towards the gate, and stopped by the gate oxide z A n-type inversion layer formed underneath the gate oxide when VGS reaches a certain value, called threshold voltage (Vt, or VTN for NMOS) z The channel connects the S and D and now currents can flow between them

–iDS ∝ vDS z Increasing vGS above Vt increases the electron density in the channel, and in turn increases the conductivity between D & S z Such devices are called enhancement-type MOSFET z In this mode, transistor = a voltage controlled resistor

z Increase vDS Æ Decrease vGD Æ less electrons at the drain side of the channel z When vDS ≥ vGS –Vt Æ VGD ≤ Vt Æ no channel exists at the drain side. The channel “pinches-off”

z When channel pinches off, electrons still flows from S to D – Electrons are diffused from the channel to the depletion region near D, where they are drifted by the lateral E-field to the D – Similar to a reverse-biased B-C junction in a BJT z Further increase of vDS Æ no effect on the channel Æ current is “saturated” and the transistor is in “Saturation Mode” z In this mode, transistor = a voltage controlled current source

Pinch Off

dQ amount of charge in the channel I ≡ = dt time it takes the carriers to get across the channel

ELE2110A © 2008 Lecture 07 - 26 Amount of Channelε Charge z MOS structure looks like a Q = CV parallel plate capacitor channel WL z V is composed of two GC C = ox = CoxWL where Cox = ε ox / tox components tox –Vt to form the channel V = VGC −Vt = ()vGS − vDS / 2 −Vt –(VGC-Vt) to accumulate negative 1424 434 charges in the channel Average gate-channel voltage

Ref: G.-Y. Wei, notes ES154, Harvard University

v = µn E where µn is the mobility

E = vDS / L z Time for carriers to cross the channel is L L2 t = L / v = µ = n E µnvDS

ELE2110A © 2008 Lecture 07 - 28 I-V Behavior: Linear Mode z Combine the channel charge and velocity to find the current flow – Current =µ amount of charge in the channel / time it takes the carriers to get across the channel µ Q v i = channel = C WL(v −V − v / 2) n DS D t ox GS t DS L2 W = C (v −V − v / 2)v n ox L GS t DS DS W = K (v −V − v / 2)v where K = µ C n GS t DS DS n n ox L

W ⎡ 1 ⎤ i = (µ C ) (v −V )v − v 2 D n ox ⎢ GS t DS DS ⎥ L ⎣ 2 ⎦ z (µnCox ) is a constant determined by the processing technology, and is denoted by K’n z W/L is a main design parameter in integrated circuit design.

– When vDS ≥ Vdsat = vGS –Vt z Now, drain voltage no longer increases with vDS z Putting vDS = vGS –Vt to the equation:

W ⎡ 1 ⎤ i = (µ C ) (v −V )v − v 2 D n ox ⎢ GS t DS DS ⎥ L ⎣ 2 ⎦

1 W 2 for VGS > Vt and iD = (µnCox) (vGS −Vt ) 2 L VDS ≥ vGS -Vt z iD independent of vDS.

Region Cutoff Triode Saturation

vGS ≥ Vt Conditions vGS < Vt v ≥ v − V v DS < vGS − Vt DS GS t

W ⎡ 1 ⎤ 1 W 2 I-V relation i = K ' (v −V )v − v 2 i = K ' (v −V ) iD = 0 D n ⎢ GS t DS DS ⎥ D n GS t L ⎣ 2 ⎦ 2 L

Kn '= µnCox Cutoff region vGS < Vt Triode region

vGS ≥ Vt and

v DS < vGS − Vt Saturation region

vGS ≥ Vt and

v DS ≥ vGS − Vt

In saturation mode: 1 W i = (µ C ) (v −V )2 D 2 n ox L GS t

z MOS vs. BJT – Current is quadratic with voltage in MOS vs. – exponential relationship in BJT z Saturation mode of MOS corresponds to active mode of BJT

NMOS

ELE2110A © 2008 Lecture 07 - 33 Topics to cover … z Common-Collector Amplifier z MOS Field Effect Transistor – Physical Operation and I-V Characteristics of n-channel devices – Non-ideal effects – P-channel devices and other types

z At vDS=vGS-VTN=VDSsat, – Channel pinch-off

z As vDS increases beyond vDSsat, the pinch off point moves away from D towards S

where gate-to-channel voltage = VTN – The effective channel length L is reduced by ∆L

–ID increases – An effect similar to Early effect in BJT

' K 2 n W ⎛ ⎞ i = ⎜v −V ⎟ D ⎝ TN ⎠ 2 L GS

z This effect is modeled by adding

a term (1+λvDS) to the I-V equation:

' K W 2⎛ ⎞ n ⎛ ⎞ ⎜ ⎟ i = ⎜v −V ⎟ 1+ λv D ⎝ GS TN ⎠ ⎜ ⎟ 2 L ⎝ DS ⎠

λ = channel length modulation parameter

z Channel-body can be regarded as a pn junction z If channel-body junction is reverse-biased, – Depletion layer beneath the gate oxide becomes wider – Since the amount of negative charges in the ( channel + depletion ) layer = amount of positive charges in the gate (Constant for a fixed gate-source voltage) Æ Channel depth is reduced – This is equivalent to an increase in the threshold voltage

z Non-zero vSB changes threshold voltage: γ φ ⎛ ⎞ ⎜ ⎟ V =V + ⎜ v +2 − 2φ ⎟ TN TO ⎝ SB F F ⎠

where

VTO= zero substrate bias for VTN (V) γ= body-effect parameter ( V )

2ΦF= surface potential parameter (V)

(source-body voltage)

It follows that the body voltage controls iD. This phenomenon is known as the body effect.

–Vt decreases by 2mV for every 1ºC rise in temperature – mobility µ decreases with temperature z Overall, increase in temperature results in lower drain currents

z As VD is increased, the drain-body junction becomes reversed biased Æ Breakdown occurs at voltages of 20 to 150V Æ Rapid increase in the drain current z Normally, no permanent damage to the device

z Whe VD is increased to a point, Æ the depletion region surrounding D extends to the S Æ Punch-through breakdown (about 20 V) z Occurs in devices with short channels z Normally, no permanent damage to the device

z When VGS exceeds about 30 V (or lower in modern IC technology) Æ Gate oxide breaks down like in the case of a capacitor z Results in permanent damage to the device

Input Pin to gates

z Since the MOSFET has a very small input capacitance and a very high input resistance, a small amount of static charges accumulating on the gate can cause the gate voltage to exceed the breakdown level – e.g., Electrostatic Discharge (ESD) from human body z Clamping diodes can be used in the I/O pins to protect the circuit from gate-oxide breakdown

ELE2110A © 2008 Lecture 07 - 44 Topics to cover … z Common-Collector Amplifier z MOS Field Effect Transistor – Physical Operation and I-V Characteristics of n-channel devices – Non-ideal effects – P-channel devices and other types

ELE2110A © 2008 Lecture 07 - 45 P-channel MOSFET (PMOS) z Similar to NMOS, but doping and voltages reversed – Body tied to highest voltage (Vdd) to prevent forward-biasing pn junctions – Source typically tied to Vdd too – Gate voltage high: transistor is OFF

– Gate voltage low: transistor is ON when VGS < Vt (threshold voltage) z Inverted channel of positively charged holes

–vGS and vDS are negative and Vt is also negative

Symbols

Cutoff region | vGS |<|Vt | Triode region

| vGS |≥| Vt | and

| v DS |<| vGS − Vt | Saturation region

| vGS |≥| Vt | and Vt, vGS and vDS are negative. | v DS |≥| vGS − Vt |

Cutoff Triode/Linear Saturation

⎡ 1 2 ⎤ 1 2 iD = 0 iD = K p (vGS −Vt )vDS − vDS i = K (v −V ) ⎣⎢ 2 ⎦⎥ D 2 p GS t W where K p = K p ' , K p '= µ pCox L µp is 2 or 3-times lower than µn

PMOS transistor is fabricated in the n well

Complementary MOS or CMOS integrated-circuit technologies provide both NMOS and PMOS on a same IC

– Must apply a negative vGS to turn off device z Vt is negative for NMOS

enhancement

depletion

z (g) and(i) are the most commonly used symbols in VLSI logic design.

z MOS devices are symmetric.

z In NMOS, n+ region at higher voltage is the drain.

z In PMOS p+ region at lower voltage is the drain