UNIVERSITY of CALIFORNIA, SAN DIEGO Sige HBT Linear-In-Db High

UNIVERSITY OF CALIFORNIA, SAN DIEGO

SiGe HBT Linear-in-dB High Dynamic Range RF Envelope Detectors and Wideband High Linearity Ampliﬁers

A dissertation submitted in partial satisfaction of the requirements for the degree Doctor of Philosophy

Electrical Engineering (Electronic Circuits and Systems)

Hsuan-yu Pan

Committee in charge:

Professor Lawrence E. Larson, Chair Professor Peter Asbeck Professor Robert Bitmead Professor James Buckwalter Professor Andrew Kummel

Chair

University of California, San Diego

2010

iii DEDICATION

To my family, especially my mother Yen-shia Hung – who is now smiling in the heaven.

iv EPIGRAPH

Be sure to have fun in your work, at all times. —Barrie Gilbert

v TABLE OF CONTENTS

Signature Page ...... iii

Dedication ...... iv

Epigraph ...... v

Table of Contents ...... vi

List of Figures ...... ix

List of Tables ...... xiii

Acknowledgements ...... xiv

Vita ...... xvi

Abstract of the Dissertation ...... xvii

Chapter 1 Introduction ...... 1 1.1 SiGe BiCMOS Technology ...... 1 1.1.1 SiGe HBT Fundamentals ...... 1 1.1.2 TowerJazz SBC18 SiGe HBT BiCMOS Process . . . 5 1.2 Broadband Differential Linear Amplifier Overview . . . . . 6 1.2.1 Emitter Resistor Degeneration ...... 8 1.2.2 Caprio’s Quad ...... 9 1.2.3 Cascomp Quad ...... 10 1.2.4 Series-and-Shunt Feedback ...... 11 1.2.5 Feedback with Operational Amplifiers ...... 13 1.3 Linear-in-dB RF Envelope Detector Overview ...... 14 1.3.1 Logarithmic Amplifier Operation ...... 15 1.3.2 AGC-based Linear-in-dB Detector Operation . . . . 18 1.4 Linear-in-dB Control for RF VGAs ...... 20 1.4.1 Using BJT’s IC vs. VBE Dependence ...... 20 1.4.2 Biasing MOS Transistors in the Weak-inversion Re- gion for Linear-in-dB Control ...... 22 1.4.3 Pseudo-Exponential Polynomial Approximation . . 23 1.4.4 Digital Control by DAC ...... 25 1.5 Dissertation Objective and Organization ...... 27

vi Chapter 2 An Improved Broadband High Linearity SiGe HBT Differential Amplifier ...... 29 2.1 Introduction ...... 29 2.2 Improved Linear Amplifier Design ...... 30 2.2.1 Linearity of Improved Cell ...... 30 2.2.2 Comparison of Improved Cell to Other Linearization Schemes ...... 35 2.3 Impedance Matching and Stability ...... 39 2.3.1 Input Impedance of the Improved Cell ...... 39 2.3.2 The Closed-Loop Input Impedance of Shunt-Shunt Feedback Amplifier ...... 40 2.3.3 Improved Matching Circuits for Broadband Shunt- shunt Feedback Amplifier Based on the Improved Cell . . 43 2.4 Experimental Setup ...... 46 2.5 Measurement Results ...... 47 2.6 Conclusion ...... 51

Chapter 3 Improved Dynamic Model of Fast-Settling Linear-in-dB Automatic Gain Control Circuit ...... 52 3.1 Introduction ...... 52 3.2 AGC Circuit Operation and First-order Steady -State Large-Signal Modeling ...... 53 3.2.1 First-order Steady-State Large-signal Model . . . . . 53 3.2.2 First-order Steady-State Behavior ...... 55 3.3 AGC Circuit Second-order Large-Signal Model ...... 56 3.3.1 Peak Detector Delay Model ...... 56 3.3.2 Second-order Steady-State Behavior ...... 56 3.4 AGC Loop Settling Time ...... 58 3.4.1 First-order AGC Circuit Settling Time Calculation . 58 3.4.2 Second-order AGC Circuit Settling Time Calculation 59 3.5 AGC Simulations and Veriﬁcation of Analysis ...... 61 3.6 Conclusion ...... 61

Chapter 4 A Linear-in-dB SiGe HBT Wideband High Dynamic Range RF Envelope Detector ...... 62 4.1 Introduction ...... 62 4.2 AGC-based Linear-in-dB Envelope Detector Operation . . . 63 4.3 Circuit Design ...... 64 4.3.1 Gilbert Multiplier Type VGA ...... 64 4.3.2 Gain Stages with Bandwidth Broadening ...... 66 4.3.3 Linear-in-dB Controller for Gilbert Multiplier Type VGA ...... 67

vii 4.3.4 V-I Converter ...... 68 4.3.5 Adaptive Biasing Peak Detector ...... 68 4.3.6 Multi-tanh Differential gm-C Filter ...... 69 4.4 Experimental Setup ...... 69 4.5 Measurement Results ...... 72 4.6 Conclusion ...... 74

Chapter 5 Conclusions ...... 76 5.1 Key Research Results ...... 76 5.1.1 Key Research Results of Broadband High Linearity SiGe HBT Differential Ampliﬁers ...... 76 5.1.2 Key Research Results of Linear-in-dB SiGe HBT Wideband High Dynamic Range RF Envelope De- tectors ...... 77 5.2 Directions for Future Research ...... 79

Appendix A Volterra Series Kernel Analysis of Emitter Resistor Degeneration and Caprio’s Quad ...... 81 A.0.1 Volterra Series Analysis of Differential Pair with De- generation Resistors ...... 81 A.0.2 Volterra Series Analysis of Caprio’s Quad ...... 86

Bibliography ...... 90

viii LIST OF FIGURES

Figure 1.1: SiGe HBT: (a) schematic device cross section (b) the microphotographic view [1][2]...... 2 Figure 1.2: Energy band diagram of a graded-base SiGe HBT compared to a Si BJT [3]...... 3 Figure 1.3: Comparison of cut-off frequencies between Si BJT and SiGe HBTs with different Ge profile [3]...... 4 Figure 1.4: The speed-power dissapation trade-off between Si BJTs and SiGe HBTs [3]...... 4 Figure 1.5: A differential amplifier with a differential input and a differential output...... 6 Figure 1.6: Cable TV networks with linear distibution amplifiers [4]...... 7 Figure 1.7: A differential pair with emitter resistor degeneration...... 8 Figure 1.8: Caprio’s Quad...... 10 Figure 1.9: Cascomp Quad [5][6]...... 11 Figure 1.10: Series-and-shunt feedback circuits: (a) )Two stage shunt and series feedback circuit [7] (b) Complete schematic of the series-and-shunt amplifier [7] [8]...... 12 Figure 1.11: Improve linearity by feedback with operational amplifiers [9]. . . . 14 Figure 1.12: Two RF envelope detector example applications: (a) Polar transmitter (b) RSSI [10][11]...... 16 Figure 1.13: A typical linear-in-dB detector input–output characteristic [12] [13] . 17 Figure 1.14: Basic logarithmic amplifier operation [12]...... 17 Figure 1.15: Logarithmic amplifier’s characteristics: (a) Simplified nonlinear saturated amplifier model (b) Linear-in-dB characterisitc of logarithmic amplifier based (a)...... 19 Figure 1.16: AGC-based linear-in-dB envelope detector [12]...... 19 Figure 1.17: Current steering RF BJT VGA with linear-in-dB controller [14]. . . 20 Figure 1.18: Current steering RF CMOS VGA with linear-in-dB controller [15]. 23 Figure 1.19: Pseudo-exponential CMOS VGA with linear-in-dB controller [16]. 24 Figure 1.20: (a) Digitally controlled linear-in-dB VGA (b) its DAC [17]. . . . . 26

Figure 2.1: Different linearity enhancement techniques: (a) Caprio’s Quad and (b) improved Gm cell...... 31 Figure 2.2: Equivalent odd-mode half-circuit ...... 34 Figure 2.3: IIP3 vs cut-off frequency ( fT ) of Caprio’s Quad, improved Gm cell and differential pair with emitter degeneration at 20MHz. Simula- tion parameters: Ree = 250Ω, RL = 50Ω, K=2.8. Overall current consumption IT =2mA ...... 37

ix Figure 2.4: Simulated normalized Gm vs. input voltage at 20MHz of Caprio’s Quad, improved Gm cell and differnenail pair with emitter degeneration. The improved Gm cell has nearly a doubled input dynamic range compared with Caprio’s Quad...... 38 Figure 2.5: Real part of input impedance of the improved cell and Caprio’s Quad. Ree = 14Ω, fT =100GHz, β = 100 and IT =2mA...... 40 Figure 2.6: Gain and phase of the proposed cell with shunt-shunt feedback resistor RF and different K values. Simulation parameters: Ree = 14Ω, RF = 310Ω, RL = 50Ω, fT =100GHz, β = 100, IT =120mA. . 41 Figure 2.7: Input admittance magnitude of the improved cell using shunt-shunt feedback resistor RF with different K values. Ree = 14Ω, RF = 310Ω, RL = 50Ω, fT =100GHz, β = 100, IT =120mA...... 43 Figure 2.8: Improved input matching techniques: 1)RFH-CFH feedback, 2) Rin- Cin termination...... 44 Figure 2.9: Magnitude of input reflection coefficient S11 after adding auxiliary RFH-CFH feedbacks. Ree = 14Ω, RF = 310Ω, RL = 50Ω, β = 100, RFH = 15kΩ, RBB = 1.5k, fT =100GHz, and IT =120mA...... 44 Figure 2.10: Magnitude of input reflection coefficient S11 after adding Rin-Cin terminations. Ree = 14Ω, RF = 310Ω, RL = 50Ω, fT =100GHz, β = 100, RFH = 15kΩ, CFH = 0.1pF, RBB = 1.5k, Rin = 5Ω. and IT =120mA...... 45 Figure 2.11: Simulated K-factor after adding Rin-Cin terminations. Ree = 14Ω, RF = 310Ω, RL = 50Ω, fT =100GHz, β = 100, RFH = 15kΩ, CFH = 0.1pF, RBB = 1.5k, Rin = 5Ω. and IT =120mA...... 46 Figure 2.12: Chip microphotograph...... 47 Figure 2.13: Experimental setup ...... 48 Figure 2.14: Laboratory bench for broadband linear amplifier IC evaluation . . . 48 Figure 2.15: Measured/Simlulated S-parameters...... 49 Figure 2.16: Measured/Simulated noise figure...... 50 Figure 2.17: Simulated and measured P1dB, IIP3, OIP3...... 50 Figure 3.1: Basic AGC circuit block diagram. The gain of VGA is adjusted according to the amplitude of V to hold V at constant-amplitude . . 54 Figure 3.2: Peak detector delay block diagram...... 56 Figure 3.3: Second-order AGC circuit block diagram. The dotted area represents the new peak detector model including the delay of peak detector...... 57 Figure 3.4: Second-order AGC circuit root mean square error percentage vs. (ωe/ωp) from SPICE simulation and theory . The error percentage increases when ωe increases. Simulation parameters: VT =0.6V, ωc=2GHz, Vre f =0.24V,A=1mV, gm=0.5mS and 1mS, C=2pF, α=0.1, m=0.9...... 58

x Figure 3.5: Comparison of ﬁrst-order and second-order AGC circuit settling time simulation and calculation results for (ωe/ωp)=1/20 and 1/100. Settling time Ts is a function of input amplitude variation ratio k. Simulation parameters: V=0.6V, ω=2GHz, V=0.24V, A=1mV, C= 2pF, α=0.1, m=0.9, g=1mS...... 60

Figure 4.1: Block diagram of linear-in-dB envelope detector...... 63 Figure 4.2: Variable gain stage. The control voltage is provided by the linear- in-dB controller...... 65 Figure 4.3: Fixed gain stages with gain broadening. The second gain stage’s input is in parallel with a differential pair with a degenerated capacitor CEE/2 to cancel out the dominant pole due to the load...... 65 Figure 4.4: Bandwidth broadening simulation/calculation results. IEE1−4= 1mA, VCC=3V, RL1=RL2=0.5K, REE1=REE2=0.125K, Cc=10pF, CL=0.1pF. 66 Figure 4.5: Linear-in-dB controller for Gilbert multiplier VGA. The difference −IconRcon/VT between IC4 and IC5 will be proportional to e ...... 67 Figure 4.6: V-I converter to generate Icon. The output current Iconis proportional to the differential voltage Vctrl and IPTAT ...... 68 Figure 4.7: Adaptive biasing peak detector. IC6 adjusts to the input signal to speed charging/discharging...... 69 Figure 4.8: Simulation results of Vpd −Vre f with/without adaptive biasing techniques where K is the current mirror ratio. Input carrier frequency equals to 1.7GHz...... 70 Figure 4.9: Multi-tanh differential gm-C filter. The differential pairs are asymmetric to improve the AGC loop settling time without sacrificing stability...... 70 Figure 4.10: Multi-tanh simulated gm profile. The transconductance is offset to speed the AGC loop without sacrificing stability...... 71 Figure 4.11: AGC-based envelope detector chip microphotograph. The chip occupies 1.8 × 1 mm2 die area including the pads...... 71 Figure 4.12: Laboratory bench of SiGe HBT linear-in-dB AGC-based envelope detector IC evaluation...... 72 Figure 4.13: Linear-in-dB measurement results (a) Venv vs. input power of the envelope detector. (b)linear-in-dB error vs. input power of the envelope detector...... 73 Figure 4.14: Envelope settling time for different input frequencies. Input power varies from -10dBm to -60dBm...... 74

Figure A.1: Small-signal half circuits of differential Pair with resistive degeneration resistors for Volterra series analysis: (a) ﬁrst-order kernel analysis (b) third-order kernel analysis...... 82

xi Figure A.2: Caprio’s Quad half circuit simpliﬁed steps: (a) applying VCVS VX and −VX and (b) resultant small-signal half circuit for calculating ﬁrst and third kernels...... 87

xii LIST OF TABLES

Table 1.1: TowerJazz SBC18 SiGe BiCMOS Process Parameters...... 5 Table 1.2: Commercial SiGe HBT BiCMOS Technologies Comparison. . . . . 6 Table 1.3: Commercial Ampliﬁer Speciﬁcations...... 7

Table 2.1: Table of Comparison for Different Transconductors ...... 39 Table 2.2: Wideband Linear Ampliﬁer Comparison ...... 51

Table 4.1: Table of Comparison: AGC-based Linear-in-dB RF Power Detec- tors...... 75

xiii ACKNOWLEDGEMENTS

The author is indebted to Professor Larry Larson for his continuous support during these years. His unique, extraordinary guidance keeps leading us into various circuit design fields. From basic DC biasing of transistors to complicated transceiver architectures, Professor Larson is always an excellent mentor to discuss with. It is impossible for me to complete the degree without his unselfish direction. The author sincerely thanks the members of my committee, Professor Peter As- beck, Professor James Buckwalter, Professor Robert Bitmead and Professor Andrew Kummel, for their invaluable recommendations and suggestions to this dissertation. The author is grateful to MaXentric’s working experience during the final phase of degree’s completion. The author wants to thank Mr. Houman Ghajari and Mr. Kam- ran Mahbobi to provide this great internship to cooperate with UCSD. The author also sincerely acknowledge Mr. Donald Kimball for the great ongoing support, the Center for Wireless Communications for the financial aid, and Mr. Cuong Vu’s patience on fabricating the PCBs. The author is thankful for Mr. Anton Arriagada’s kindly assistance on finishing up JTRS wideband high dynamic range frequency hopping transceiver project. He is definitely an open-minded and respectable partner. I learned a lot. The author is deeply appreciative of unforgettable journey to Northwest Lab in Analog Devices Inc.. Having innovative discussions with Mr. Multiplier – Dr. Barrie Gilbert, Dr. John Cowles, Dr. Todd Weigandt, Mr. Benjamin Sam, Mr. Daryl Carbonari and Mr. Richard Soenneker gives me numerous insights and strength to fulfill the design tasks after coming back to the campus. The author is much obliged to the internship experience on Jones Farm Campus of Intel Corporation. During the beginning phase of my Ph.D career, Dr. Ashoke Ravi, Dr. Jing-hong Conan Zhan, Dr. Javier Alvarado, Mr. Jack Peng, Dr. Stewart Taylor, Dr. Hasnain Lakdawala, Dr. Mostafa Elmala, and Dr. Krishnamurthy Soumyanath had been generously teaching me how to lead research to the right directions. The author thank them. The author heartily thanks Professor Donald Y. C. Lie’s guidance during the beginning study at UCSD.

xiv The author wants to thank all my colleagues at UCSD for their inspiring discussions and suggestions, especially to Miss Jonmei Yan, Mr. Chin Hsia, Dr. Rahul Kodkani, Dr. Junxiong Deng , Dr. Vincent Leung, Dr. Joe Jamp, Mr. Yiping Han, Dr. Mohammad Farazian, Dr. Sanghoon Park, Mr. Pavel Kolinko, Dr. Sean Kim, Dr. Himanshu Khatri, Mr. Alireza Kheirkhani, Dr. Feipang Wang, Dr. John Fairbanks, Mr. Paul Theilmann, Mr. Paul Draxler, Dr. Tsaipi Hung, Mr. Mingyan Li, Dr. Tomas O’sullian, Mr. Sataporn Pornpromlikit, Dr. Calogero Presti, Mr. Toshifumi Nakatani and Mr. Chris Thomas. Friends are indispensable. For many years, the author appreciates keeping the company with Mr. Ning Wang, Dr. Tzu-chien Hsueh, Dr. Wei-jung Chien, Mr. Yu-tien Lin, Miss Yiling Hu, Mr. Shiou-hung Chen, Mr. O-cheng Chang, Mr. Phil Talatala, Mr. Patrick Lai, Mr. Ting-fan Wu, Dr. Wendy Chi, Mr. Weilun Tsao, Dr. Jin-wei Shi, Mr. Cheng-han Wang, Mr. Derek Chau, Mr. Chih-de Hung, Mr. Hung-chi Lai, Dr. Jiasheu Huang, Mr. Pin-chou Chaing, Dr. Rick Ni, Mr. Sean Peng, Mr. Steve Fang, Mr. Taihong Chih, Dr. Tiku Yu, Dr. Wei-hsin Wade Chang, Dr. Yen-lin Lee and Dr. Yun-shiang Shu. Thanks for their effort on helping me during difficulties and frustrations. Family always comes first. I want to make a bow to my father, Mr. Chun-hua Pan and my mother, Mrs. Yen-shia Hung –even though she will miss my graduation. I thank my brother Dr. Hsuan-I Pan’s assistance in managing my family issues, especially in recent years. Finally, I am grateful to Miss Chih-chieh Cheng in her fantastic cooking and immense love. The text of Chapter Two, Three, and Four, in part of in full, is a reprint of the material as it appears in the author’s published papers or as it has been submitted for publication in IEEE International Symposium on Circuits and Systems (ISCAS), IEEE Radio Frequency Integrated Circuits (RFIC) Symposium and IEEE Transactions on Cir- cuits and Systems I (TCAS-I). The dissertation author was the primary researcher and the first author with co-author Prof. Lawrence E. Larson listed in these publications. He directed and supervised the research which forms the basis for these chapters.

xv VITA

1999 B. S. in Electrical Engineering, National Taiwan University, Tai- wan (R.O.C.)

2001 M. S. in Electrical Engineering, National Taiwan University, Tai- wan (R.O.C.)

2010 Ph. D. in Electrical Engineering (Electronic Circuits and Sys- tems), University of California, San Diego

PUBLICATIONS

H-Y. M. Pan and L. E. Larson, "Improved Dynamic Model of Fast-Settling Linear-in- dB Automatic Gain Control Circuits," IEEE International Symposium on Circuits and Systems (ISCAS), pp. 681-684, May 2007.

H-Y. M. Pan and L. E. Larson, "Highly Linear Bipolar Transconductor For Broadband High-Frequency Applications with Improved Input Voltage Swing," IEEE International Symposium on Circuits and Systems (ISCAS), pp. 713-716, May 2007.

H-Y. M. Pan and L. E. Larson, "A Linear-in-dB SiGe HBT Wideband High Dynamic Range RF Envelope Detector," IEEE Radio Frequency Integrated Circuits (RFIC) Sym- posium," pp. 267-270, May 2010.

H-Y. M. Pan and L. E. Larson, "An Improved Broadband High Linearity SiGe HBT Differential Ampliﬁer," IEEE Transaction of Circuit System I (TCAS-I), submitted.

A. Arriagada, H-Y. M. Pan, J. Yan, D. F. Kimball and L. E. Larson, "A Wideband High Dynamic Range Frequency Hopping Transceiver for the Joint Tactical Radio System," IEEE Military Communication Conference (MILCOM) 2010, accepted.

H-Y. M. Pan and L. E. Larson, "An Improved Linear-in-dB SiGe HBT Wideband High Dynamic Range RF Envelope Detector," IEEE Journal of Solid-State Circuits (JSSC)," in preparation.

xvi ABSTRACT OF THE DISSERTATION

SiGe HBT Linear-in-dB High Dynamic Range RF Envelope Detectors and Wideband High Linearity Ampliﬁers

Hsuan-yu Pan

Doctor of Philosophy in Electrical Engineering (Electronic Circuits and Systems)

University of California, San Diego, 2010

Professor Lawrence E. Larson, Chair

This research work aims on exploiting SiGe HBT technologies in high dynamic range wideband RF linear-in-dB envelope detectors and linear amplifiers. First, an improved all-npn broadband highly linear SiGe HBT differential amplifier is presented based on a variation of Caprio’s Quad. A broadband linear amplifier with 46dBm OIP3 at 20MHz, 34dBm OIP3 at 1GHz, 6dB noise figure and 10.3dBm P1dB is demonstrated. Second, an improved exact dynamic model of a fast-settling linear-in-dB Automatic Gain Control (AGC) circuit is developed. Based on this, a wideband linear-in-dB RF envelope detector is implemented in TowerJazz Semiconductor 0.18 µm SBC BiCMOS process with 2.5GHz bandwidth and 50dB dynamic range.

xvii Chapter 1

Introduction

1.1 SiGe BiCMOS Technology

In recent years, Silicon-Germanium (SiGe) BiCMOS technology has become a unique candidate for the next generation communication market by providing not only the superior performance of a heterojunction bipolar transistors (HBT), but also the good integration/low-cost advantages of the traditional silicon process [18][19]. Starting from 1996, the ﬁrst standard high-volume SiGe process was initiated by IBM Microelectroncs and later adopted by many companies for various applications [3]. Because of its out- standing performance and good compatibility with complementary metal oxide semiconductor (CMOS), SiGe BiCMOS processes are widely used today in demonstrating ﬁrst-generation silicon IC experimental prototypes, and implementing heavily demand- ing applications where performances have to be comparable to III-V compound based IC’s.

1.1.1 SiGe HBT Fundamentals

The SiGe HBT utilizes heterojunction bandgap engineering to drastically improve silicon bipolar junction transistor’s speed. A SiGe alloy is generated by combining germanium (Ge) – which has a smaller bandgap (0.66eV) – and silicon (Si) – which has a 1.12 eV bandgap energy [3] – together. The SiGe alloy is deposited as the base region of a bipolar junction transistor (BJT), as shown in Fig. 1.1. The p-SiGe base cre-

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" # τb,SiGe kT kT ∝ × 1 − × 1 − e−∆Eg,Ge(grade)/kT (1.1) τb,Si ∆Eg,Ge(grade) ∆Eg,Ge(grade)

where τb,Si is the base transit time of silicon bipolar transistors [3]. With proper Ge grading, τb,SiGe can be signiﬁcantly reduced. For high-frequency applications, an important ﬁgure of merit for transistor speed is the cutoff frequency ( fT ), which is given by [20][21]

! −1 Figure 1.12 Energy1 band1 diagram of a graded-base SiGe HBT compared to a Si BJT. fT ≈ (Cbe +Cbc) + τb (1.2) 2π gm

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Figure 1.11 (a) Schematic device cross section of a SiGe HBT, and (b) the microphotographic view [48].

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Figure 1.12 EnergyFigure 1.2 band: Energy diagram band diagram of a graded-base of a graded-base SiGe SiGe HBTHBT compared compared to a Si to BJT a Si BJT. [3].

where gm is the transconductance (IC/VT ). Cbe, Cbc are the base-emitter, base-collector junction capacitances, respectively. As shown! in Equation (1.2), the smaller transit time τb implies a larger cut-off frequency fT . Hence, the SiGe HBT’s fT can be improved

signiﬁcantly when compared with a Si BJT. Fig. 1.3 shows the comparison of fT between the Si BJT and SiGe BJTs under the same bias conditions – the SiGe BJTs have

larger peak fT , as expected.

Because of the improved fT , the SiGe HBT also has an advantage for low power consumption applications. Compared with conventional Si BJTs, the required bias current for operation at the same frequency can be signiﬁcantly reduced. This speed-power dissipation tradeoff is illustrated in Fig. 1.4. Other advantages of SiGe HBTs are sum-

marized in [3] such as enhancement in the maximum oscillation frequency ( fmax) and

Early voltage (VA), reduction in low frequency 1/f and high frequency (broadband) noise, and improved low-temperature performance. the Ge gradient induced drift ﬁeld across the neutral base is determined by the amount of

Ge grading. The resulting reduction in b of a SiGe HBT over an identically constructed Si BJT is [35]

b,SiGe kT kT E (grade)/kT 1 1 e−" g,Ge . (7) b,Si ∝ Eg,Ge(grade) · − Eg,Ge(grade) − " ! " " #$ As expected, the improvement is reciprocally dependent on the Ge induced bandgap grad-

ing factor. Figure 11 conﬁrms this reduction in b with measured fT . Other advantages, 4 such as increases in Early voltage (VA) and maximum oscillation frequency (fmax), reductions in low-frequency (1/f) and high-frequency (broadband) noise, and improved low-

temperature performance of SiGe HBTs over traditional Si BJTs are described in [35].

FigureFigure 1.3: Comparison 11: Comparison ofof cut-offmeasured frequenciescutoff frequenc betweenies of comp Siara BJTbly co andnstruc SiGeted Si B HBTsJT with differentan Ged SiG profilee HBTs [3].with different Ge profiles (after [35]). ! ! "#!! SiGe HBT BiCMOS technology is relatively new, even though the concept of HBTs

Figure Figure1.13 SiGe 1.4: HBT, The speed-power whose fT is dissapation inherently trade-off higher betweenthan that Si of BJTs silicon and SiGefor the HBTs same bias current,[3]. can trade off the excess speed to achieve a low-power solution.

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Table 1.1: TowerJazz SBC18 SiGe BiCMOS Process Parameters. SiGe HBT NPN Low-voltage Device High-voltage Device Max. β 116 105 Max. ft 78 GHz 38 GHz Max. fmax 160 GHz 100 GHz Early Voltage 75 V 220 V BVCEO 1.99 V 3.18 V NMOS Thin-Oxide Device Thick-oxide Device tox 3.85 nm 6.71 nm Le f f 0.18 µm 0.36 µm Idsat 599 µA/µm 560 µA/µm PMOS Thin-Oxide Device Thick-oxide Device tox 3.79nm 6.71nm Le f f 0.18 µm 0.36 µm Idsat 254 µA/µm 290 µA/µm Capacitor MiM Capacitor Poly Capacitor Density 5.6 fF/µm2 8.7 fF/µm2 Resistor TiN Metal Resistor Poly Resistor Resistivity 24.5 Ω/square 1000 & 235 Ω/square

1.1.2 TowerJazz SBC18 SiGe HBT BiCMOS Process

Besides the high-performance SiGe HBTs, high-quality passive elements and CMOS transistors are also indispensable to implement circuits for different applications. TowerJazz Semiconductor’s SBC18 SiGe HBT BiCMOS process [2] integrates a 78 GHz fT low-voltage SiGe HBT with a 3.3 V supply voltage. A high breakdown voltage HBT with a modified collector is also provided with a 38 GHz fT and a 6 V supply voltage for high power amplification. To be compatible with CMOS, two kinds of complementary MOSFET devices are provided: a standard 1.8 V 0.18 µm FET, and a high-voltage 3.3 V FET for use in I/O circuit designs. It offers six metal layers for layout flexibility. In addition, this process features MiM capacitors with high qualify factors, poly capacitors for high capacitance-to-area ratio. It also offers high-Q spiral inductors with thick top metals. To reject the undesired spurs, a deep trench structure is provided to improve isolation [22]. A summary of TowerJazz SBC18 process parameters is given in Table 1.1 [2]. To glance the advancement of the existing SiGe BiCMOS processes, a table of comparison 6

Table 1.2: Commercial SiGe HBT BiCMOS Technologies Comparison. Technology IBM IBM IBM TowerJazz 6HP 7HP 8HP SBC18HX Max. fT 47 GHz 120 GHz 200 GHz 78 GHz Max fmax 65 GHz 100 GHz 280 GHz 160 GHz BVCEO 3.3 V 1.8 V 1.7 V 3.18 V WE,e f f 0.42 µm 0.18 µm 0.13 µm 0.18 µm CMOS Le f f 0.35 µm 0.14 µm 0.092 µm 0.18 µm CMOS Supply 3.3 V 1.8 V 1.5 V 1.8 V

Figure 1.5: A differential amplifier with a differential input and a differential output. of different SiGe BiCMOS processes is provided in Table 1.2. The excellence of SiGe BiCMOS technologies clearly demonstrates that SiGe HBT is a promising technology for RF circuit designs. In the next sections, two important applications of SiGe HBTs will be covered: the first is the broadband linear differential amplifier, and the second is the Automatic Gain Control Circuit (AGC)-based linear-in-dB RF envelope detector.

1.2 Broadband Differential Linear Ampliﬁer Overview

The concept of "differential" signals and amplifiers was invented in 1940s and originally utilized in vacuum-tube circuits [23]. In order to provide immunity to common mode interference, fully differential topologies are extensively utilized [24] and became robust, highly reliable building blocks in today’s systems. Fig. 1.5 shows an illustrated differential amplifier with a differential input and a differential output [25]. In order to provide undistorted amplification, "linearity" is usually an important requirement for differential amplifiers in most commercial applications, such as RF 5 Digital TV by Cable 124 THE MATV (MASTER ANTENNA TV) NETWORK

In many European countries, cable TV was based on the fact that there were lots of MATV systems that easily could be hooked up the larger cable TV networks. However the quality of MATV networks varies. Most of these networks are cascaded networks (see Figure 5.6). In order to save some cabling, one cable can go from one apartment to the next passing through several outlets. But saving cable comes at a price. The signal level will get lower as the signal pass from one outlet to the next. If you are at the end outlet, your signal might be a lot worse than at the first outlet. The alternative to the cascaded network is the star-shaped network. Each apartment has its own cable direct from the divider and each unit’s signal level is not affected by other outlets. Another advantage is that there is an alternative to encryption of pay TV channels. Instead, the pay-TV content can be filtered so that only people paying would get those channels distributed on their cable. In the beginning of cable TV, there were some high ambitions about using only star-shaped networks to benefit from these advantages. Economical reali- ties, however, showed that this was not possible. The antenna outlets had to be exchanged and new amplifiers had to replace the old ones. However in many cases old cables were used. And in many cases there was not room for any new cables necessary to get a star-shaped structure in the old tubes and conduits. It 7 was much easier to renovate the old cascaded networks that already existed.

FIGURE Cable TV networks with several branches, in this case in star-shaped (left) and cascaded structures (right). 5.6 Figure 1.6: Cable TV networks with linear distibution ampliﬁers [4].

Table 1.3: Commercial Amplifier Specifications. Application RF Gain Block CATV Signal Distribution Supply Voltage 3–6V 3.3–9V Supply Current 41–160mA 104–450mA Bandwidth 1MHz–4.5GHz 5MHz–1.3GHz P1dB 9.1–21dBm 25.7–29dBm OIP3 19–42.3dBm 42–45.3dBm NF 1.1–7.5dB 4.4–6.5dB Gain 13.3–20dB 4.6–13dB Gain flatness 0.5dB 0.2dB ZO 50 Ω 75 Ω

transceivers [26], Cable Television (CATV) signal distribution [27][4][28], instrument interfaces [29][30] and Digital Subscriber Line (DSL) drivers [31][32]. Fig. 1.6 shows Cable TV networks with linear distibution ampliﬁers. These linear differential ampli- ﬁers are typically realized in commercial GaAs technology. However, the improved silicon-based circuit approach, like the SiGe HBT, provides a great opportunity to lower the cost of these key building blocks – the wide bandwidth can be possibly achieved

by its inherent high fT , and the required linearity could be met by appropriate circuit designs. The speciﬁcations of the commercial ampliﬁers are summarized in able 1.3. The RF gain blocks are widely used in instrument interfaces and RF transceivers to meet 8

Figure 1.7: A differential pair with emitter resistor degeneration. various gain and linearity requirements. On the other hand, the CATV signal distribution amplifiers are often designed to provide output power up to at least 25 dBm, with high linearity and moderate noise figure. Both of them require high linearity, wide bandwidth amplifications with good noise performance. In recent years, various linearity enhancement techniques were developed to meet the required linearity and noise specifications, such as resistor degeneration [25], Caprio’s Quad [33], series-and-shunt feedback [7] [8], feedback with operational amplifiers [34] and the Cascomp [5]. However, these techniques still have a variety of noise, linearity and dynamic range limitations [35].

1.2.1 Emitter Resistor Degeneration

The most popular linearization scheme of bipolar differential pairs is with an emitter degeneration resistor [20][25], which is shown in Fig. 1.7. The output current is the well-known v + ∆v ∆I = IN BE (1.3) 2Ree 9

where ∆vBE represents the base-emitter voltage difference of Q1 and Q2. Equation 1.3 shows that the imperfect linearity of ∆I vs. vIN results from the incomplete cancellation of base-emitter voltages of Q1 and Q2, i.e. vBE1 is not exactly equal to vBE2. In communication applications, the linearity is usually characterized by intermodulation distortion (IM) and third-order input referred intercept point (IIP3) [36]. Suppose a two-tone signal with frequency components ∆ f + f and f is fed into a differential pair with degeneration resistor, then the third-order input referred intercept point voltage (VIIP3) at frequency f + 2∆ f is [25]

3/2 IT Ree VIIP3Deg ≈ 4VT 1 + (1.4) 2VT

where VT is the thermal voltage, Ree is the emitter degeneration resistor and IT = 2Iee is the overall current consumption of the differential pair. Equation (1.4) shows the well- known result that the VIIP3Deg relies on the product IT Ree. This technique is widely used because of its simplicity and broadband improvement with moderate linearity.

1.2.2 Caprio’s Quad

To obtain improved cancellation of the base-emitter voltages, Caprio’s Quad [33] added one cross-coupled pair Q3 −Q4 to the original differential pair Q1 −Q2, as shown in Fig. 1.8. The loop voltage can be written as

vIN − vBE1 − vBE4 + 2Ree∆I + vBE3 + vBE2 = 0. (1.5)

Because of the cancellation of the base-emitter voltages of Q1 −Q4 (vBE1 = vBE3, vBE2 = vBE4), Caprio’s Quad is very linear. Nevertheless, the input voltage swing range of

Caprio’s Quad is limited due to the cross-coupled base-collector junctions of Q3 and

Q4. When vIN exceeds one junction turn-on voltage – roughly 0.8V – the base-collector 10

Figure 1.8: Caprio’s Quad.

junction of Q3 will become forward-biased and high linearity operation will not be preserved. The other problem, noted by B. Gilbert in [37], is the high frequency instability due to its negative impedance at the input.

1.2.3 Cascomp Quad

As shown in Fig. 1.9, the cascode compensation circuit (Cascomp) [5][6] reduces the distortion using feedfoward linearization [38]. The Cascomp quad includes one main quad and one auxiliary quad. The main quad is composed of a bipolar differential pair Q1 − Q2 with emitter degeneration resistors R1 − R2. The auxiliary quad comprises the other bipolar differential pair Q5 −Q6 with emitter degeneration resistors

R5 − R6, which is designed to correct the distortion generated by the main quad. The principle of operation can be explained as follows: ﬁrst, the distortion produced by the base-emitter junctions of input pair Q1 − Q2 is replicated across the base- emitter junctions of Q3 − Q4. Compensating transistor pair Q5 − Q6 senses the signal across Q3 − Q4, ampliﬁes it, and then adds a compensating anti-phase signal to the col- Distortion produced by the base-emitter junctions of input transistor, depend upon the product of degeneration pair Q1-Q2 is replicated across the base-emitter junctions resistance and transistor transconductance. Consequently, of Q3-Q4. Compensating transistor pair Q5-Q6 sense the the differential common-base and common-emitter signal across Q3-Q4, amplify it, and then add a amplifiers of Fig. 3 are designed so that the fundamental compensating anti-phase signal to the collector currents of components of their respective output currents add in- Q3-Q4. However, the phase shift in the signal paths of the phase, while the third-order distortion components (both cascode and compensation amplifiers differ, and this harmonic and intermodulation products) are anti-phase and imperfection increases with operating frequency. Hence, cancel each other. the operating bandwidth is limited, as distortion is no longer cancelled by the addition of collector currents from 2. ANALYSIS Q3-Q4 and Q5-Q6 at frequencies above approximately one- Coefficients for the power series were determined by first 11 fifth of fT [3]. summing the voltages at the input using Kirchhoff’s

+ - voltage law, followed by the substitution for the nonlinear Iout Iout base-emitter junction voltage by a power series expansion. A harmonic balance is then used to express the harmonics of collector current generated by a sinusoidal input signal V Q Q V b 3 4 b [4]. Using one-half of the differential-excited common-base Q5 Q6 transistors in Fig. 3 as example, the voltage drop across R3, R R 5 6 the base-emitter junction of Q3, and the input voltage are + - Vin Q1 2I5 Q2 Vin related by R =R 1 2 V in= – ie3 R3 – vbe3 (2) R1 R2 R =R 5 6 with 2I1 i v = V ln §·1 + -----e3 be3 T ©¹ . (3) Figure 2: CascodeFigure Compensation 1.9: Cascomp Quad (Quinn’s [5][6]. CasComp). I3 The transconductor of Fig. 3 offers improvement in Replacing the ln function in (3) by its series expansion linearitylector currents comparable of Q3 − Q4. However, to the phase CasComp, shift in the signal while paths of offering the cascode a and substituting (3) into (2), results in an expression and compensation amplifiers differ, and this imperfection increases with operating fre- relating the input voltage to the emitter/collector current widerquency. Hence,operating the usable bandwidth bandwidth is limited. and Thea low main quad’sinput distortion impedance is no longer as (ie≈ic). Then, it is assumed that the single input tone requiredcancelled when for the RF input frequencies and many is above high-speed approximately one–fifth applications. of fT [5]. The circuit consists of two differential-excited common-base V in() t = V1A cos ω1 t (4) transistors1.2.4 Series-and-Shunt (Q3-Q4) and Feedback a feedforward emitter-coupled pair generates a collector current (Q -Q ). i ()t = c cos ()ωt +c cos ()2ωt +c cos ()3ω t + … (5) 1 When2 the input frequency is relatively low, many analog feedback techniques c 1 2 3 can be exploited because of the large loop gain [8]. A two stage feedback amplifier encompassing all the generated harmonics. After Iout+ Iout- is proposed by Prof. Meyer in [7] and is shown in Fig. 1.10 (a), which incorporates substituting and replacing the input voltage and emitter

both series and shunt feedback. If feedback resistor RF1 and RF2 are large, the overall current in (2) with the expressions from (4) and (5), feedback loop gain can be approximated as Q3 Vb Vb Q4 coefficients ci , are determined from a harmonic balance

analysis. Coefficients for the first three harmonics of R3 RL RE2 RER1 4 A(s) ≈ β (s) × × + (1.6) 2 R R R common-base and common-emitter differential currents Q1 E1 Q2 F2 F1 Vin+ Vin- are listed in Table 1.

Because of the high β of Q2, theR resultant1 loop gainR2 A(s) can be very large. Conse- Table 1: Coefficients for the Differential Currents. R =R 1 2 i = i – i i = i – i I3 2I I3 Out,CE ()c1 c2 Out,CB c3 c4 1 R3=R4 Figure 3: Feedforward Compensated Differential Pair. gm1 gm 3 c1 ------V1 A – ------V1 A 1 + R g 1 + R g Distortion compensation for weakly nonlinear behavior 1 m 1 3 m 3 in the transistors is achieved using the effect of emitter c2 00 degeneration on the third-order distortion products produced by each stage. This is possible because the phase gm1 3 gm 3 ()12– R3 gm 3 3 c3 ------V1A ------V1 A relationship between fundamental and distortion 2 4 2 5 48VT ()1 + R1 gm 1 96 VT ()1 + R3 gm 3 components (i.e., either in-phase or anti-phase) produced by a degenerated common-base or common-emitter

Authorized licensed use limited to: Univ of Calif San Diego. Downloaded on June 19,2010 at 17:41:49 UTC from IEEE Xplore. Restrictions apply. MEYERet al.: UL~LINEAR AMPLI~IER 12 171

IC2 (mA) =8=31

-40~~0

MEYER et al.: ULTS-4LINEAR AMPLIFIER 169

.=z These equations are extremely useful in determining & .-% 0 first-order dependence of circuit parameters on element -t30- ‘-\. Measured IM3values.at 200M’HzHowever, they are approximate expressions [espe- =-. / +---x-————- *- —cially-.--- *-----(16) ] and final design values are generally refined \alculated IM3by computer analysis. -1oo- Frequency (MHz) As in the previous examples, the terminal impedances Fig. 9. Calculated and measured intermodulation distortion of a Fig. 8. Computed feedback loop gain of the Darlington pairRF~as a Darlington pair. Output signal levels andare O gaindBm. Sourcedependand on resistor values only (to first order) function of frequency. load impedances are 500, and are quite broad band due to the negative feedback Fig. 3. Two stage shunt (a)and series feedback circuit. of the circuit. Note that (16) shows a substantial feed- y+22v back loop gain in the circuit. The appropriate value of ever, the high end of the band at 300 MHz was quite 82 (s) is the current gain of Q2 in Fig. 3 including the sensitive to loop phase shift and had a tendency to peak effects of parasitic and Miller capacitance. Another sig- excessively. As a consequence, it was decided that feed- nificant aspect of (16) is that the frequence dependence back over three stages at these frequencies may give of the loop gain is ideally that of a single pole, and thus problems on a production basis and was not pursued. the high-frequency phase shift of Al should approach 90°. IN PUT However, at lower frequencies (say below 100 MHz) this This has important implications for CM reduction [6]. circuit may be useable in these applications. It should be noted that, in general, due to losses caused The final circuit configuration to be considered is the by nonideal feedback elements, maximum gain-band- two stage version of this technique shown in Fig. 3. The width in a feedback amplifier is achieved using only one operation of this circuit is not as obvious as that of feedback loop. The use of two loops in these circuits is Figs. 1 and 2, but the incorporation of both shunt and followed because of the need for wide-band resistive series feedback at input and output is apparent. Since matches. Fig. 10.thisCompletecircuit schematicconfigurationof the final amplifier.was(b) theResistorsone in finallyohms, capacitorsused, in themicrof arads.Finally, the noise figure of the circuit of Fig. 3 can be analysis of this circuit will be done in greater detail than shown to be the elimination of the null between Cjn and C’jc. This is cellation. Inductors L4 and L5 are high-frequency match- Figurefor 1.10the: Series-and-shuntfirst three. feedbackAlthough circuits:a similar (a) )Two stagecircuit shunthas and seriesbeen feed- of little consequence however, because of the decision to ing elements. backproposed circuit [7] (b)before Complete[10] schematicthe ofbandwidth the series-and-shuntand distortion ampliﬁer [7] [8].per- use a balanced push–pull configuration which cancels Initial values of Rrl, REI, R~z, R~2 and R~ were chosen even-order distortion. IM2formanceis now alsoachieveddeterminedherelargelyis believedusing to(13 )beto unique.(16), They represent a compromise be- by C’jc of Ql, as can be seenIn orderfrom tothe obtaincalculatedequalcurveresistivetween impedancesoverall gain andR, andminimizationRO of signal loss due which assumes this is theit wasonly foundsource necessaryof distortion. to Theincludeto thea small-seriesshunting effectsbaseof Rr,pad-and RF,. Final values were use of a Darlington output connection improved IMS of chosen by computer optimization and are+ shown[1+in(%31’’%?+%3$’the ding resistor R~. Although this causes some noise figure the circuit by 3 to 4 dB at the high frequency end of circuit diagram. Using these values in (13) to (17) gives: degradation, the specification of 9 dB could still be met. + ~ , (R, + R,)’ the band. . (17) In Appendix I, it is shown that approximateR, = 34 L?, expressionR, = 33 Q /S,, = 19.5 dB, 2R. -[k+ (k)’] B. Final Circuit NF = 7.0 dB (/3 = 90) for the parameters of the circuit of Fig. 3 are where gn,l, /31, ~B, and j~l are parameters of transistor Q1. The complete circuit is shown in Fig. 10. As mentioned for the differential half circuit. The impedancesThe feedbackare dou- resistors REI and RFZ and the series re- above, a balanced circuit was used toR,,reduce+ Rmsecond- R,,Rbled for the full circuit. These values are close to the de- sistor RB all cause noise figure degradation. For minimum R,=R~+ R sired performance (Rand,2 agree+ REZ),with experimental measure- order distortion, and in practice reductions( Ezin IM2R,,of + Rm + R ) 25 to 30 dB were obtained. This degree of balance at 300 ments. The output shunt feedback noiseresistorsfigure,RFIA Rnland and RB should be minimized and RPZ MHz requires careful circuiti.e., design and layout, and the RFIB are 135 ~ and each shunts 37.5maximized.Q of load resistance. use of balun transformers T1 and T2 with complementary The output power loss due to the feedback resistors is chokes L1 and L2 [12]. The chokes serve both(E,%as balanc-+ RJRE,Rthus only about 1 dB. III. CIRCUIT REALIZATION A computer simulation of (13)the high-frequency loop gain ing elements and a path‘i for= dc‘Bbias+ inREIRthe circuit.+ R.,(R.,Choke + RE1 + R) L3 forces the bias voltage at the bases of Q3 and Q4 to be of the circuit was made by breaking theThelooptransistorsat the base for use in an amplifier such as this are equal and thus improves the dc balance in the two halves of Q5 inserting a test signal and obviouslycomputing theof loopcritical importance. Special devices were R, = (RF, + Rm)REz(R i- R,) of the circuit and consequently improves the IM2 can- transmission.(R,, +TheREJ,loop gain showed developeda single poleforrolloffthis application and their properties are RB,(RF~ + R~, + R, + R) listed below. i.e., Common-emitter cutoff frequency: j* = 5 GHz. Authorized licensed use limited to: Univ of Calif San Diego. Downloaded on June 20,2010 at 02:49:15 UTC from IEEE Xplore. Base Restrictionsresistance: apply. r~ = 150. (R,, + Rm)Rm(R+ R.)__ (14) ‘0 = Rm(Rm + R,, + R + R,) + Rm(R, + R) collector-base capacitance at VO~ = – 10 V: CiO = 2 pF. ~ =R~l+REIRi–R~ 21 (15) Emitter-base junction capacitance at 1,, = 100 mA: R R, ‘ El cj~ = 25 pF.

where, R~ = RL = R, R6 is given by (13) and input and Typical distortion characteristics of these devices are output are assumed matched. The feedback loop gain shown in Fig,s. 4 and 5. Also shown is predicted distor- due to both loops is tion using the simple formulas developed in Appendix II and neglecting Kirk effect [11 ]. The measured and cal- 1 At = 82(5) E,l II (R., + R) culated data agree well at low and moderate currents, but deviate at high currents due to f~ fall-off which was not modeled. The null in IMZ is due to cancellation between Cin and C;c as seen in (31) of Appendix II.

Authorized licensed use limited to: Univ of Calif San Diego. Downloaded on June 20,2010 at 02:49:15 UTC from IEEE Xplore. Restrictions apply. 13 quently, the input/output impedance is well-defined and the nonlinearity of BJTs is also suppressed. Hence the resultant amplifier’s input/output impedance can be matched precisely at moderate frequencies and preserve good linearity. Fig. 1.10 (b) shows the complete circuit implementation of the series-and-shunt amplifier. Notice the second stage is replaced with a Darlington pair rather than a emitter degenerated BJT. However, when input frequency becomes higher, the transistor’s β rolls off and creates extra poles, which worsen the entire amplifier’s impedance matching. The β dependence also implies that the loop gain is susceptible to the BJT’s process variations. Moreover, the two-stage feedback amplifier’s stability has to be examined carefully when applying this technique for RF applications [21].

1.2.5 Feedback with Operational Ampliﬁers

A promising linearization solution is to improve the transconductor’s linearity by the use of operational ampliﬁers (Opamps), which is shown in Fig. 1.11 [34][9][39].

Assuming the Opamp’s gain A0 is very large and the "virtual gound" property is preserved, the Opamps replicate the input differential voltage and force it to appear cross the degeneration resistor R, hence the overall transconductor is very linear. Neverthe- less, this approach’s achievable bandwidth is mainly set by the input Opamp’s maximum operating frequency. At RF frequencies, because of the roll-off of the Opamps’ gain, the resultant linearity improvement is limited.

To sum up, the SiGe HBT process provides a great opportunity to lower cost implementation of broadband differential linear ampliﬁers. The HBT’s inherent high fT is capble of covering the linear ampliﬁer’s wide bandwidth. As compared with traditional III-V compound transistors, the fabrication cost is greatly reduced with comparable RF performances. SiGe HBT also has supplied good integration with the existing CMOS technologies. As to bipolar linear transconductor circuit design, various linearization techniques have bee reported in recent years, but with different linearity enchancement, bandwidth and input swing limitations. The emitter resistor degeneration approach has the simplest topology, but with only moderate linearity. Caprio’s Quad is very linear but 424 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-10, NO. 6, DECEMBER 197S

A Wide-Band Monolithic Instrumentation Amplifier

RUDY J. VAN DE PLASSCHE 14

Abstract–A new voltage-to-current converter has been designed. $fOut Outp This converter combines accuracy with differential signal handling and a high common-mode rejection ratio (CMRR). An application in an v(”@--- V(n instrumentation amplifier consisting of two voltage-to-current converters in a batancing circuit shows the versatility of these units in analog circuit design. A remarkable point of the instrumentation amplifier is that the bandwidth (800 kHz) remains constant although the voltage gain varies from 1 to 104.

~- ODAY the operational amplifier, especially in the form Fig. 1. General form of a voltage-to-current converter. of an integrated circuit, has become the general purpose Figure 1.11: Improve linearity by feedback with operational ampliﬁers [9]. T work horse for the analog system designer. In some applications, however, this amplifier type limits the overall cir- with limited input voltage swing range due to the cross-coupled nature. The Cascomp cuit performance. A well-known problem in this field is the Quad’s auxiliary quad linearizes the main quad’s linearity in a feedforward manner, but amplification of low-level signals superimposed on large inter- with limited achievable bandwidth. The series-shunt ampliﬁer feedback loop gain is fering common-mode voltages. With three operational ampli- proportional to the transistor’s β – which is susceptible to process variation, and rolls fiers and a few externally connected feedback elements this off at higher frequencies. Its two-stage oriented stability has to be considered carefully problem can be solved, but an optimum in circuit. perfor- as well. Feedback with Opamps’ lowers the operating frequency, but works well for low- mance is not obta~ed. In particular the common-mode be- frequency applications. Therefore, the implementation of wide bandwidth highly-linear havior is poor. bipolar transconductors with moderate input voltage swing range is still an ongoing re- Analysis shows that there are two basic solutions to solve the search area and has numerous commercial possibilities. instrumentation amplifier problem. The next Section covers the other important application of the SiGe HBT – the 1) The use of current feedback instead of resistive feedback AGC-based linear-in-dB RF envelope detector. It also requires high performance SiGe to isolate the input part from the output p~~~of the amplifier HBTs to achieveFig. 2. accuratePractical RF linear-in-dBconverter envelopeshowing detection.stability problems. and so the common-mode voltage is removed from the signal volt age. ~) The use of a floating and accurate vohage-to-current cOn- 1.3 Linear-in-dB RF Envelope Detector Overview the current sources 10. Via TI and T~ the converted current verter; due to the current source character of the converter flowsRFto envelopethe output detectorsterminals. [40] are used(In ina manyfirst applications,approximation such as instrumentignore output circuitry the common-mode voltage is removed with- interfaces,the base polarcurrents and envelopeof TI trackingand transmittersTz.) Due [26][10],to the receivecurrent signalsource strength out any problem from the voltage. indicationbehavior (RSSI)of [41][11],transistors powerT, controland [42],T2, voltagewhich standing-waveform the ratiolink (VSWR)be- On current feedback a few designs [1], [2] have recently measurementstween the andfloating automaticinput gain controlpart and (AGC)the circuits.grounded Fig. 1.12output shows twopart exampleof been published. These designs have the drawback of low flex- the circuit, the common-mode voltage is removed from the in- applications of RF envelope detectors: they can be used to extract the down-conversion ibility, stringent requirements for the current gain tracking of put signal. The amplifiers AO give the circuit a high-input the feedback transistors, and a limitation in high-frequency impedance and an accurately adjustable conversion factor common-mode behavior. which is determined by the resistor R. Now two design prob- A design of an instrumentation amplifier which uses a new lems arise. The first is due to the stability of the improved type of a voltage-to-current converter will be described. Fur- emitter followers TI and Tz when a common-mode input thermore, such a converter is very suitable for signal handling voltage is applied. The high open-loop gain of the amplifiers in bipolar integrated circuits and can be seen as a basic circuit A ~ decreases the stability margin, particularly where capaci- element for medium scale integrated circuits. tive loading is introduced by the parasitic capacitances of the current sources 10. GENERAL FORM OF A VOLTAGE-TO-CURRENT CONVERTER The second problem is introduced by the parasitic capaci- The general form of a voltage-to-current converter is shown tances CP, which express the total stray capacitances between in Fig. 1. The two floating operational amplifiers AO perform the floating input part and the grounded output part of the an exact reproduction of the input voltage Vin across the con- circuit. These capacitances are multiplied by the Miller effect version resistor R. DC biasing of the circuit is performed by in the amplifiers AO and can now be seen connected in parallel to the current sources 10. At high frequencies the maximum Manuscript received May 28, 1975; revised August 4, 1975. This allowable common-mode voltage which can be applied at the paper was presented at the International Solid-State Circuits Confer- input terminals is now reduced because of the limited value of ence, Philadelphia, Pa., February 1975. The author is with Philips Research Laboratories, Eindhoven, The 10. In Fig. 2 a general circuit into which nearly every instru- Netherlands. mentation ~mplifier circuit, based on the principle of current

Authorized licensed use limited to: Univ of Calif San Diego. Downloaded on June 20,2010 at 18:44:26 UTC from IEEE Xplore. Restrictions apply. 15 path’s envelope information in the polar transmitter, or they can be utilized to sense the received signal’s strength in the receiver. Therefore, accurate RF envelope detection, either in transmitters or in receivers, is indispensable. When detecting wide dynamic range RF signals, a "linear-in-dB" detector generates an output proportional to the logarithm of the input envelope [12], as shown in Fig. 1.13. According to their operation, linear-in-dB detectors can be classiﬁed into two different types: logarithmic ampliﬁers and AGC-based detectors [42]. They are explained as follows:

1.3.1 Logarithmic Ampliﬁer Operation

Logarithmic amplifiers rely on the progressive compression of cascading gain cells, with summing/filtering each stage to produce a rectified voltage [43][44]. Fig. 1.14 shows the basic logarithmic amplifier operation, which is composed of a chain of amplifiers and detectors to measure the output signals of each amplifier and a summer to generate an output voltage called Venv [45][46]. These amplifiers have linear gain A. As the signal progresses down the gain chain, it begins to clip when the last amplifier’s output amplitude reaches the next amplifier’s input threshold voltage. As an example, the clipping level is set at 1 Volt. After the signal begins to be clipped in one of the stages, the clipped signal continues to propagate to the following signal chain, and be clipped in the next stages, maintaining its 1 Volt peak amplitude. The signal at the output of each amplifier is also fed into a full wave rectifier. The outputs of these rectifiers are summed together and applied to a low-pass filter, which removes the ripple of the full-wave rectified signal. This yields the detector’s output

Venv, which is linear-in-dB to the input signal envelope. To examine the linear-in-dB characteristic, a simplified nonlinear amplifier model is shown in Fig. 1.15(a). The simplified amplifier has linear gain A, and output is saturated at Vclip when the input amplitude reaches Vclip/A. Consider the basic logarithmic amplifier operation in Fig. 1.14. If the input signal envelope is Vin,env and the amplifier’s gain A >> 1, then the output voltage Venv can be approximated as 16

2182 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 12, DECEMBER 2004

WUFig. AND 6. TSAO: Proposed A 110-MHz polar loop 84-dB transmitter. CMOS PROGRAMMABLE GAIN AMPLIFIER WITH INTEGRATED RSSI FUNCTION 1255 (a)

(a) (b)

Fig. 7. (a) Spectrum of amplitude component. (b) Spectrum of phase component in EDGE.

TheFigure amplitude 1.12 loop has: Two a wide RF dynamic envelope range with detector wide band- exampleTo ensure applications: stability and system (a) Polar performance, transmitter the combined (b) gain widthRSSI and low [10][11].noise. It is designed to have a loop gain of 40 dB so of IFVGA and BBVGA is kept constant within a55-dB PAoutput that the signal levels at the two detectors D1 and D2 are the same power range, from 35 to 20 dBm. The loop maintains its func- with a typical amplitude error of 1%. To have the same ampli- tionality up to the level equivalent to 38 dBm at the PA output. tude accuracy at the output of the PA, the entire feedback chain Operation in multiband is achieved by using two different including mixer and IFVGA was designed to be highly linear RF VCOs, a low-band VCO which covers both GSM850 with an IM3 of less than 40 dBc. The average output power (824–849 MHz) and GSM900 (880–925 MHz) bands, and level is controlled by changing the feedback gain. Since the for- a high-band VCO that covers both DCS (1710–1785 MHz) ward-path BBVGA gain tracks with an opposite slope, the error and PCS (1850–1910 MHz) bands. Both VCOs are integrated signal is ampliﬁed, resulting in a variable bias of the PA. If the on-chip. While in high-band operation (DCS/PCS), the LO1 feedback gain is swept, the output power sweeps, and a desired signal will be multiplied by two before being applied to the ramp proﬁle is achieved. Dominant poles zeros have been used in mixer in the feedback path. This keeps the IF frequency similar the loop to achieve 65 phase margin and a 14-dB gain margin. between high-band and low-band operation.

Authorized licensed use limited to: Univ of Calif San Diego. Downloaded on(b) June 21,2010 at 01:58:25 UTC from IEEE Xplore. Restrictions apply. Fig. 7. (a) Architecture of the RSSI circuit. (b) One of the detector circuits of the RSSI.

The output of the fixed gain stage that is chosen to be the and still turn off the current of the saturated rectifiers, the offset input of the fine gain control stage has a swing ranging from 50 cancellation circuit still maintains its function. to 200 mV. Thus, a fixed gain stage is considered as saturated when its output exceeds 200 mV, and the rectifiers should be VI. EXPERIMENTAL RESULTS designed according to this operating range. However, the following saturated fixed gain stages will be used by the RSSI cir- The IF amplifier we proposed [7] has been fabricated in a cuit only, but not the whole PGA signal chain, so these saturated 0.35- m one-poly four–metal (1P4M) CMOS process. The ca- fixed gain stages can be turned off without affecting the inte- pacitors used for frequency compensation in the operational am- grated RSSI function only if we also turn off the current of the plifier for the bias circuit of the fixed gain stages are realized saturated rectifiers (this is not realized in this chip), because the using MOS capacitors. The gain programming logic circuit and rectifier output current goes to zero when its input saturates. So RSSI circuit are also integrated with the IF amplifier. The test in the presence of larger signals, we can prevent the last ampli- chip is directly bonded to a PCB surrounded with the required fier stages from clipping. However, this will break the loop of external components. The programmable power gain range of the offset cancellation circuit, so the offset cancellation circuit the whole PGA is from 7.78 to 79.79 dB in normal operation should be modified, for example, by turning on these saturated mode (at 110 MHz) and 7.79 to 80.03 dB in low-power oper- stages when the PGA is not in the operation mode in a TDMA ation mode (at 71 MHz), as shown in Fig. 9. It has been found system or using some feedback schemes like a dynamic mode that the peaks of gain step error occur every 12 dB because of the feedback circuit. In another way, if we just lower the gain of the 12-dB gain of the fixed gain stages. The gain step error is kept following saturated fixed gain stages, i.e., like unity gain buffers, within 0.4 dB when the test chip is operated in either normal

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Figure 17. VOUT Pulse Response Time; Pulsed RF Input 0.1 GHz, −10 dBm; Figure 20. Output Voltage Stability vs. Supply Voltage at 1.9 GHz CLPF = Open; RLOAD = 150 Ω Figure 1.13: A typical linear-in-dBWhen V detectorPOS Varies input–output by 10% characteristic [12] [13] .

Rev. B | Page 9 of 20

Figure 1.14: Basic logarithmic ampliﬁer operation [12]. 18

V V ≈ A4V when V ≤ clip env in,env in,env A4 V V V ≈ A3V +V when clip ≤ V ≤ clip env in,env clip A3 in,env A4 V V V ≈ A2V + 2V when clip ≤ V ≤ clip env in,env clip A2 in,env A3 V V V ≈ AV + 3V when clip ≤ V ≤ clip env in,env clip A in,env A2 V V ≈ 4V when clip ≤ V . (1.7) env clip A in,env

And the Venv vs. Vin,env is illustrated in Fig. 1.15(b). Notice that when Venv increases by a factor A in magnitude, the Venv will increase by the same amount "step" Vclip (1 Volt in the previous example), and the slope is changed by A as well. This is called a "linear-in-dB" response, and is very suitable to detect wide dynamic range signals with a low peak-to-average ratio (PAR). When the PAR of the input signal is large, the output low-pass filter design becomes challenging: it has to not only filter out the ripples from the summing output, but also leave the wideband high PAR envelope signal’s content unchanged. Moreover, the amplifier’s saturation response is never ideal in reality [47], and extra precaution is needed to "linearize" the linear-in-dB response.

1.3.2 AGC-based Linear-in-dB Detector Operation

For high peak-to-average ratio (PAR) signals, AGC-based detectors (also referred to as "true RMS" detectors) are preferable and operate in a closed-loop manner. The output of the VGA/attenuator is a constant when the loop is locked, and the envelope information is extracted from the VGA control voltage [48][49]. An AGC-based linear-in-dB detector is shown in Fig. 1.16 with illustrated wave- forms. First, an enveloped-modulated signal Vin is ampliﬁed by a linear-in-dB VGA with a control voltage Venv. The peak detector detects the VGA output voltage Vout and generates a peak-extraction signal Vpd. The Gm-C ﬁlter compares Vpd with a constant reference voltage Vre f , and creates a "correction" voltage Venv. When the loop is locked,

Venv is automatically adjusted according to the envelope of Vin to keep the linear-in-dB 19

(a) (b)

Figure 1.15: Logarithmic amplifier’s characteristics: (a) Simplified nonlinear saturated amplifier model (b) Linear-in-dB characterisitc of logarithmic amplifier based (a).

Figure 1.16: AGC-based linear-in-dB envelope detector [12]. 20 1944 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 12, DECEMBER 2000

Linear-in-dB Controller RF VGA

Fig. 2. Signal-summing VGA circuit with CSC. Figure 1.17: Current steering RF BJT VGA with linear-in-dB controller [14]. [5]. This configuration can operate at high frequency be- of the VGA stages must be increased so as to obtain the desired cause the gain is determinedVGA’s outputby the currentVout constant. ratio, As a, result, and theVenv gainis proportional range. to the logarithm of the en- range over which tail currents and change can be reduced By subtracting one from the denominator in (1), the signal- velope of V , which is "linear-in-dB" [12]. Because the AGC’s gain is changing with compared to that for the VGA shownin in Fig. 1(c). However, this summing VGA can have a complete linear-in-dB characteristic configuration dissipatesthe ainput large signal amount amplitude, of power the because overall detector two and input 20-dB dynamic wider range gain isrange. greatly This improved, realizes a gain range of 40 dB stages of the amplifierand are becomes required much in the higher signal than path. the traditionalusing peak detectorone gain approach. stage. Thus, only two cascaded stages of the The signal-summing VGA [Fig. 1(a)] and the differential signal-summing VGA are needed to obtain an 80-dB gain range, In order to achieve a good RF AGC-based linear-in-dB detector, the RF linear- pair VGA with an MOS resistor [Fig. 1(b)] are superior among which reduces the power dissipation of the VGA by approxi- the four types of VGAsin-dB from VGA the design viewpoint becomes of high-frequency extremely important.mately As one-half. to device technologies, the high and low-power operation.performance We adopted SiGe HBT the plays signal-summing an indispensable role in achieving an RF linear-in-dB VGA because, as outlined below, a linear-in-dB function can B. VGA with Accurate Linear-in-dB Gain Control be achieved over theVGA, complete because gain-range of the high byfT modifying, and its inherent the exponential dependence between collector The biggest issue in using the signal-summing VGA is the gain-control signal, whichcurrent does (I ) not and affect base-emitter signal path. voltage Hence, (V ). The next section reviews the linear-in-dB C BE large gain deviation from the linear-in-dB gain-control charac- there is no need to consider the frequency response of the gain control methods for published RF VGAs. teristic at high gain. We propose a gain compensation scheme compensation circuit. On the other hand, the differential pair in which the gain-control signal is applied to a pre-distortion VGA with an MOS resistor deviates from the linear-in-dB gain circuit. Fig. 2 shows the signal-summing VGA with the pro- characteristic at high frequency even if the gain-control signal posed pre-distortion circuit, which is referred to as a control is modified for linear-in-dB1.4 characteristic Linear-in-dB at some Control frequency. for RF VGAs signal converter (CSC). Signal currents ( ) are input to the VGA (emitters of , , and , ) and attenuated IV.1.4.1 CIRCUIT UsingDESIGN BJT’s IC vs. VBE Dependenceaccording to the gain-control signal . The CSC converts the gain-control signal into to obtain a linear-in-dB vari- A design consideration for low-power operation and the Because of the inherent exponentialable-gain dependence characteristic between its upIC toand theV maximumBE, i.e, gain of the VGA. VGA circuit implementation are described in this section. I ≈ I eVBE /VT [21], BJTs are widely used in theTo realizelinear-in-dB a linear-in-dB controllers characteristic of RF VGAs. based on (1), the transfer In particular, we focusC onS a proposed gain-compensation function of the CSC must satisfy scheme and temperature-compensation techniques for realizing an accurate linear-in-dB function up to the maximum gain. These techniques enable a low-power operation of the VGA. (2) Two temperature-compensation techniques are applied to the gain-compensation scheme and a differential amplifier of the where is a constant. The gain-control signal first stage of the VGA, which are explained in Sections IV-C generates a voltage drop of between the and IV-D, respectively. bases of and . Due to the exponential nature of bipolar transistors and , the collector cur- A. Design Consideration for Lower-Power Operation rents of and are and The signal-summing VGA has an unusable gain-control , respectively. The resulting range of about 20 dB below its maximum gain. Supposing that base voltage difference satisfies (2) for the minimum current gain is limited to 40 dB due to signal . Thus, the current gain is expressed as follows: feedthrough, the VGA will have a usable gain range of only 20 dB. This reduced gain range due to incomplete linear-in-dB (3) function causes high power consumption because the number

Authorized licensed use limited to: Univ of Calif San Diego. Downloaded on June 22,2010 at 22:41:16 UTC from IEEE Xplore. Restrictions apply. 21

A current steering bipolar RF VGA is proposed in [14] and shown in Fig. 1.17.

The RF VGA has one differential RF current input ±Iin. The differential RF current output ±Iout is determined by how much RF input current (±Iin) is steered to the resistive load RL by controlling the top differential pairs Q1 – Q2 and Q3 – Q4. A well-known relationship between VY , which represents the base voltage of differential pair Q1 – Q2, and the output current Iout, can be expressed as [20]:

eVY /VT Iout = Iin × . (1.8) 1 + eVY /VT

where VT is the thermal voltage of the BJT (=kT/q). As Equation (1.8) shows, Iout is not proportional to eVY /VT . Therefore, a linear-in-dB controller is required to control this RF current steering VGA. Suppose a linear transconductor faithfully transforms the VGA’s control voltage

VCNT to the control current ICNT , i.e. ICNT = VCNT /RC. Then, one way to achieve linear- in-dB control is to let ICNT ﬂow through resistor R between the bases of two transistors

Q21 and Q20, as shown in Fig. 1.17. If Q20 and Q21 have the same emitter area, based on the BJT’s IC–VBE exponential dependence, IC21 can be written as

−ICNT R/VT IC21 ≈ IC20 × e (1.9)

The next step is to mirror the current IC21 to Q10 using a 1:1 PNP-PMOS current mirror

Q25–Q26,(Q22–Q24 are used for β compensation). Hence IC10 ≈ IC21. Finally, with the assistance of translinear loop Q1 − Q10 − Q11 − Q2, the resultant RF output current Iout is

Iout ≈ Iin × exp(−ICNT R/VT ) (1.10)

Replacing ICNT with VCNT /RC, Iout becomes 22

−VCNT R Iout ≈ Iin × exp( ) (1.11) VT RC

−VCNT R which shows Iout is linear-in-dB to . Temperature compensation can be achieved VT RC by making VCNT as proportional-to-absolute-temperatue (PTAT) and maintaining the same temperature coefﬁcients between R and RC.

1.4.2 Biasing MOS Transistors in the Weak-inversion Region for Linear-in-dB Control

When the applied gate-source voltage (VGS) is less than the threshold voltage

(Vth), the MOSFET is operating in the "weak-inverison" (subthreshold) mode. The Boltzmann distribution of electron energies allows some energetic electrons at the source to enter the channel to travel to the drain, generating a subthreshold current that is an exponential function of gate–source voltage. This current can be approximated by [20]:

VGS −Vth ID ≈ ID0 × exp (1.12) nVth

where ID0 is the current when VGS = Vth, and n is a proportionality constant. Fig. 1.18 shows an example of a linear-in-dB controller using weak-inversion MOSFETs to generate the exponential current ID1. The CMOS VGA’s topology is similar to Fig. 1.17’s current steering RF BJT VGA, but generating the exponential current source from a weak-inversion NMOS M21. Notice that transistor M21, M10, M1 and M3 are all operating in the weak-inversion region. One bottleneck to apply this technique to control an RF VGA is the slow speed of the weak-inversion MOSFET. The transconductance of a weak-inversion MOSFET can be derived as

gm ≈ ID/nVth. (1.13) 11.1 A 380-MHz CMOS Linear-in-dB Signal-summing Variable Gain Amplifier with Gain Compensation Techniques for CDMA Systems Osamii Watanabe, Slioji Otaka, Mitsuyuki Ashida and Tetsuro Itakura

Corporate R&D Center, Toshiba Corporation, Kawasaki, .Japan 23 Abstract Linear-in-dBCSCl Controller Signal-summingRF VGA VGA A linear-in-dB signal-summing VGA is fabricated in 0.25 pm CMOS technology. Two gain compensation techniques are proposed in order to compensate the gain deviations due to a MOSFET characteristic which has a square-law characteristic or an exponential-law characteristic determined by its current density. Temperature conipensation techniques are also proposed. A gain range of 80 dB, a gain error of within i3dB, an NF of 11 dB are obtained at 380 MHz by measurement. Introduction CDMA systems require variable gain amplifiers (VGAs) with wide dynamic range in both transmitter(TX) and receiver(RX). Especially for a wide-band CDMA (W-CDMA) system, not only the wide dynamic ranae but also a hiah ~ frequency operation should be simultaneously satisfied in the FigureFigure 1.18: Current CMOS steering RFsignal-summing CMOS VGA with linear-in-dBV~~ with controller CsC [15]. VGA. Although CMOS linear-in-dB VGAs have been reported 11, 21, a linear-in-dB VGA with signal-summing technique suitable for wide dynamic range and high frequency operation has not been realized with CMOS technology, because gain com-Because of the low subthreshold current ID, the resultant gm is relatively small, which pensation seems complicated for ohtaining a linear-in-dB char-limits the maximum operating frequency of this approach. Moreover, the MOSFET sub- acteristic as described in the next section. This paper mainlythreshold characteristic depends heavily on the threshold voltage, which has a strong de- discusses gain compensation techniques suitable for a CMOSpendence on process variations [50]. As a result, designing a wide-bandwidth, process- linear-in-dB VGA with signal-summing technique. The mea- insensitive CMOS linear-in-dB RF VGA using weak-inversion MOSFETs is difﬁcult. sured results indicate that the VGAs with the proposed gain compensation techniques are applicable for W-CDMA system. 1.4.3 Pseudo-Exponential Polynomial Approximation Gain deviation in signal-summing VGA TheI exponential gain control function can be easily obtained in a BJT, but dif- A signal-summing VGA with control signal converter(CSC1) ﬁcult in a MOSFET4 [16] [51]. A pseudo-exponential- polynomial function [52] is often using bipolar transistors has been proposed for ohtaining a square-law region exponential-law region linear-in-dB characteristic. where CSCl~~ comeensat,rs a gainused to approximate the exponential function as follows: I ~~~~~ characteristic of the signai-summing VGA[3]. Fig. 1 shows a CMOS version of the signal-summing VGA with CsC1. Cur- Figure 2: Gain deviation from1 + X linear-in-dB1/2 characteristic ex ≈ (1.14) rent densities of MlO-M11 and M1-M4 are set to the same 1 − X value so as to have differential pairs of M1-M2, M3-M4 op- where gmMlo,gmM1l are transconductances of M10 and erate as a current mirror of a differential pair of MlO-M11 in NotM11, surprisingly, respectively, the approximation IDI,ID~ is validare only fordrain small currentsX. Even thoughof M10 the ap- order to determine a current gain GI,(=AIaut/AItn) by CSCl. and M11. Equation (2) indicates that the gain-slope is IDI(= Ioexp{-RIx/(aV~)}) is generated at M21 by a cun- exp{-RIx/(SnVT)} and the gain decreases 3 dB at IDI = trol signal current Ix, a resistor R, and M20, M21 operated Im(Vv = 0) from a linear-in-dB gain line(line A). in exponential-law region such bipolar transistors, where as In the case that M1, M3, M10 operate in exponential-law ID,, lo are drain currents of M21 and MZO, respectively. How- region; that is lower gain region, the current gain GI is ap- ever, a crucial deviation from linear-in-dB characteristic occurs proximately cxpressed by as shown in Fig. 2, because an operating region of M1, M3, M10 is changed from square-law region to exponential-law region as the current gain is decreased as described below. In the case that M1, M3, M10 operate in square-law region; that is, in higher gain region, the current gain of GI is expressed by where p = (l/Z)pCox(W/L),p is a mobility, Cox is gate oxide capacitance per unit area, n is a constant related on process parameters, and VT is the thermal voltage. Equation (3) indicates that the gain-slope is twice of that in square-law region.

136 0-7803-7310-3/02/$17.0002002 IEEE 2002 Symposium On VLSl Circuits Digest of Technical Papers

Authorized licensed use limited to: Univ of Calif San Diego. Downloaded on June 24,2010 at 21:20:25 UTC from IEEE Xplore. Restrictions apply. their Gain Cell 2 and 3, because of improving its noise figure (NF). The voltages V1 and V2 are supplied from the proposed gain control circuit in Fig.3. 3.Experimental Result This VGA is fabricated in a 0.18 µm CMOS process. The total current is 4 to 6mA under 1.8-V supply. The two output buffers consume 10mA. Fig.5 shows the layout of this VGA. Power-splitter with anti-phase outputs creates balanced signal-ended source, which is applied to input ports. The balanced output port is converted by power-combiner into a single-ended signal for measurements. Measurements are made at 380MHz,and the CMOS VGA with output buffers, when linearity (IP1dB) is measured, is used. The output buffers are used to gain the drive-ability, but they are no influence to the linearity of the VGA, which is revealed by the measurements. Fig.6 shows the measurement gain control characteristics at temperature of -30, 25 and 85 degree Celsius. The 73dB linearity controlled gain range within ±2dB error is achieved at 25 degree Celsius. The gain deviation within ±3dB achieve 32dB in the temperature range. From the measurement, the temperature stable gain isn’t achieved with the original ability of this VGA with the temperature stable technique. Because it’s the cause of pairing mismatches in the gain control circuit. Fig.7 shows the NF and IP1-dB, which indicates the linearity of this VGA. The NF is obtained 5dB at maximum gain. Fig.7 indicates that this CMOS VGA obtained a good performance for the NF. And the best IP1dB is -18.6dBm at the gain of 10dB, while the lowest is -45.6dBm.The measurement results are summarized in Table 1.

4.Conclusion All-CMOS VGA with independence of device parameter and temperature behavior, which is operating at 380MHz under low power dissipation, is proposed. This VGA is fabricated in 0.18-µm CMOS technology. This VGA has abilities that the linear-in-dB controlled range is 73dB at 25 degree Celsius, the NF is 5dB at maximum gain, and the best IP1dB is -18.6dBm at the gain of 10dB,while the lowest is -45.6dBm. From measurement results, this VGA is realizable for a highly integrated CMOS radio receiver.

5.Reference [1] T. Yamaji, N. Kanou, T. Itakura: “A Temperature Stable CMOS Variable Gain Amplifier with 80-dB Linearly Controlled Gain Range”, 2001 symposium on VLSI Circuit Design of Technical Papers, pp.77-80, 2001 [2] P-C.Huang, L-Y. Chiou, C-K. Wang: “A 3.3-V Wideband Exponential Control Variable-Gain-Amplifier,” IEEE International Symposium on Circuits and Systems, 1, pp. 285-288, 1998. [3] Kinya Hosoda, Akira Hyogo, Keitaro Sekine: “A Three MOSFET Pseudo-Exponential Function Circuit,” ICFS 2002 pp. S1-29-32, March 27-28, 2002. [4] Yasuhide Kuramoti, Akira Hyogo, Keitaro Sekine: “Current-Mode Pseudo-Exponential Function Generators,” IEEJ 2000 International Analog VLSI Work-shop, pp. 1318-1321, 47,2000. [5] C. -C. Chang, and.-I. Liu: “Pseudo-Exponential Function MOSFETs in Saturation,” IEEE Trans. Circuit Syst. II Analog Digit. Signal Process, pp.1318-1321, 47, 2000. [6] C.-H. Lin, T .Pimenta and M. Ismail: “Universal Exponential Function Implementation using Highly-CMOS V-I Converters for dB-Linear (AGC)Applications,” Mid-west Symposium on Circuits and Systems, pp.360- 363, 1998. [7] R. Harjani: “A Low -Power CMOS VGA for 50 Mb/s Disk Drive Read Channel,” IEEE Trans. on Circuits and System, pt II, vol. 42, no. 6, pp.370-376, June 1995.

Common Mode Pseudo-exponential CommonFeedback Mode Feedback Gain Cell Table 1: Performance summary M23 M24 M7 M8 Power Supply Voltage 1.8 V Current Consumption 4 to 6 mA Vcm M21 M22

Gain range 73 dB MR1 Cc MR2 vo- vo+ NFDSB at GMAX 5 dB Input P1dB at GMAX -18.6dBm@Gain=10dB v v Input P1dB at G -45.6dBm i+ i- MIN M11 M12 M3 M5 M6 M4

M1 M2 M13 M14 I i Il Linear-in-dBGain Control Gain Cell Gain Controller Fig.1 Conventional VGA Figure 1.19: Pseudo-exponential CMOS VGA with linear-in-dB controller [16].

proximation has a limited dynamic range, this method is still widely applied in CMOS linear-in-dB VGAs because of its simplicity. Fig. 1.19 shows an example of a pseudo-exponential CMOS VGA with linear-in- dB controller to implement the approximation in (1.14) [16]. The pseudo-exponential VGA is composed of a gain cell, a linear-in-dB gain controller, and a common-mode

feedback circuit. The gain cell is composed of an input source-coupled pair M3 –

M4 with diode-connected loads M5-M6. The DC biasing current sources M1–M2 are controlled by the linear-in-dB controller to adjust input source-coupled pair’s biasing

current. Mg1 and Mg2 are used for common-mode feedback to ensure the DC output voltages are properly deﬁned. Assume the long-channel square-law approximation is applied to all devices. Since the gain cell can be simply treated as a source -coupled pair loaded with diodes, the differential gain can be easily determined by the transconductance ratio between

input devices M3-M4, and output devices M5-M6: 25

g g Gain ≈ m,in = m,3−4 gm,out gm,5−6 s µC (W/L) × I = ox 3−4 3,4 µCox(W/L)5−6 × I5,6 s (W/L) × (I + I ) = 3−4 bias con (1.15) (W/L)5−6 × (Ibias − Icon)

where Ibias is the DC biasing current of M1’s and M2 when control voltage VC=0. Current

Icon is the control current adjusted by the control voltage Vc. Combining (1.14) and

(1.15), if M3, M4, M5 and M6 have the same size, (1.15) can be further simpliﬁed as

1/2 Icon Ibias + Icon Gain ≈ ≈ eIbias (1.16) Ibias − Icon

As a result, the linear-in-dB control can be accomplished in CMOS technology. Nev- ertheless, constrained by the pseudo-exponential polynomial in (1.14), this method has limited dynamic range with moderate linear-in-dB error. A compromise solution is to cascade more gain cell stages to mitigate the linear-in-dB errors, but this consumes more DC power [16] [51].

1.4.4 Digital Control by DAC

A digitally controlled scheme is proposed to overcome the non-idealites in the analog control linear-in-dB VGA [17] by the advanced digital signal processor (DSP). As shown in Fig. 1.20(a), a current steering VGA (similar to Fig. 1.17) is still used, but the base current of Q4 and Q5 are supplied by a digital-to-analog converter (DAC). Fig. 1.20(b) shows the linear-in-dB control DAC with ECL logic. The DAC has a four-bit digital word input and one current output IDAC, which is tied to the control port of Fig. 1.20(a). With a different DAC’s input word, the DAC generates the corresponding output current IDAC to adjust the base current of Q4 and Q5 (ICRTL) and varies the VGA gain. Because the DAC only has four bit, the minimum increment of the controlled gain cannot be too small. Nevertheless, the digitally controlled method still provides a Fig. 1 Transmitter block diagram 26

Fig. 4 Schematic of the DAC

neglect the base current of the Q3 –Q6 transistors in the Fig. 1 Transmitter block diagram VGA (see Fig. 2). The gain steps in dB (DG) for low gain levels can be derived from (1), neglecting the unit terms when compared Fig. 2 VGA schematic (a) with the exponential one. Therefore DG can be computed as The block diagram of the digital control circuit is shown 1 in Fig. 3. It uses three control bits (data, clock and reset) and DG (2) ¼ exp (R DI =V ) consists of a digital interface, a DAC, a decoder and a com- B2 Á DAC T pensator. In order to achieve a dB-linear behaviour, a non- where DIDAC is the resolution of the DAC. As a result, the linear variation of ICTRL is required. For this, the linear gain step is obtained by setting the value of resistor RB2 current IDAC is compensated by a predistortion component in the VGA (Fig. 2). In our design, DG is equal ICOMP. to 2 dB and the corresponding value for resistor RB2 is 60 V. The DAC is driven by four data bits (X1, X2, X3 and X4) The control current ICTRL, which guarantees a and sets the nominal ICTRL step, which is properly increased linear-in-dB gain control characteristic, is given by by the compensator at high(b) gain levels. The compensator is Fig. 4 Schematic of the DAC N DG=20 driven by six data bits (Y1, Y2, Y3, Y4, Y5 and Y6), which VT ln (2 10 Á 1) are provided by the decoder. The digital interface ICTRL(X1, X2, X3, X4) Á À (3) ¼ RB2 neglectperformsFigure the 1.20 both base: (a) Digitally complementary current controlled of the linear-in-dB metal–oxide–semiconduc-Q3 –Q VGA6 transistors (b) its DAC [17]. in the VGAtor to (see emitterFig. 2). coupled logic (CMOS-to-ECL) adaptation where andThe series-to-parallel gain steps in dB conversion (DG) for for low the gain input levels control can bits. be derivedFig. from 4 shows (1), neglecting the schematic the unit of terms the DAC. when The compared circuit (N)10 (X1, X2, X3, X4)2 (4) Fig. 2 VGA schematic ¼ withadopts the an exponential R–2R ladder one. Therefore topology withDG can switches be Therefore the compensator current I can be derived computedimplemented as in the ECL logic. The resolution of the DAC COMP from the following expression The block diagram of the digital control circuit is shown has been set equal to 100 mA. This represents the minimum value, which allows1 a robust design with in Fig. 3. It uses three control bits (data, clock and reset) and DG (2) ICOMP(X1, X2, X3, X4) ICTRL(X1, X2, X3, X4) respect to the fabrication¼ exp (R tolerancesDI =V to) be achieved. ¼ consists of a digital interface, a DAC, a decoder and a com- B2 Á DAC T N DI (5) Indeed, the DAC resolution must be sufﬁciently large to À Á DAC pensator. In order to achieve a dB-linear behaviour, a non- where DIDAC is the resolution of the DAC. As a result, the I , I and I as functions of the control word are linear variation of ICTRL is required. For this, the linear gain step is obtained by setting the value of resistor RB2 CTRL COMP DAC current IDAC is compensated by a predistortion component in the VGA (Fig. 2). In our design, DG is equal shown in Fig. 5, whereas Fig. 6 shows the compensated gain control characteristic and the uncompensated curve. The ICOMP. to 2 dB and the corresponding value for resistor RB2 is 60 V. ICOMP performs the compensation at the highest levels of The DAC is driven by four data bits (X1, X2, X3 and X4) The control current ICTRL, which guarantees a and sets the nominal ICTRL step, which is properly increased linear-in-dB gain control characteristic, is given by gain. At low levels of the gain, ICOMP tends to a constant by the compensator at high gain levels. The compensator is value and the actual step of ICTRL becomes equal to the N DG=20 driven by six data bits (Y1, Y2, Y3, Y4, Y5 and Y6), which V ln (2 10 Á 1) DIDAC. The number of gain levels to be compensated is I (X , X , X , X ) T Á À (3) related to both DG and maximum tolerable dB-linear gain are provided by the decoder. The digital interface CTRL 1 2 3 4 ¼ R performs both complementary metal–oxide–semiconduc- B2 error. In our circuit, the compensator adjusts six current tor to emitter coupled logic (CMOS-to-ECL) adaptation where steps corresponding to the highest seven gain levels. and series-to-parallel conversion for the input control bits. The schematic of the compensator is shown in Fig. 7. It (N) (X , X , X , X ) (4) adopts a simple binary-weighted current source topology Fig. 4 shows the schematic of the DAC. The circuit 10 ¼ 1 2 3 4 2 adopts an R–2R ladder topology with switches Fig. 3 Block diagram of the digital control circuit and is driven by six data bits (Y1, Y2, Y3, Y4, Y5 and Y6) Therefore the compensator current I can be derived implemented in the ECL logic. The resolution of the DAC COMP from410 the following expression IET Circuits Devices Syst., Vol. 1, No. 6, December 2007 has been set equal to 100 mA. This represents the minimum value, which allows a robust design with I (X , X , X , X ) I (X , X , X , X ) respect to the fabrication tolerances to be achieved. COMP 1 2 3 4 ¼ CTRL 1 2 3 4 N DI (5) Indeed, the DAC resolution must be sufﬁciently large to Authorized licensed use limited Àto: UnivÁ of DACCalif San Diego. Downloaded on June 24,2010 at 23:56:50 UTC from IEEE Xplore. Restrictions apply.

ICTRL, ICOMP and IDAC as functions of the control word are shown in Fig. 5, whereas Fig. 6 shows the compensated gain control characteristic and the uncompensated curve. The ICOMP performs the compensation at the highest levels of gain. At low levels of the gain, ICOMP tends to a constant value and the actual step of ICTRL becomes equal to the DIDAC. The number of gain levels to be compensated is related to both DG and maximum tolerable dB-linear gain error. In our circuit, the compensator adjusts six current steps corresponding to the highest seven gain levels. The schematic of the compensator is shown in Fig. 7. It adopts a simple binary-weighted current source topology Fig. 3 Block diagram of the digital control circuit and is driven by six data bits (Y1, Y2, Y3, Y4, Y5 and Y6)

410 IET Circuits Devices Syst., Vol. 1, No. 6, December 2007

Authorized licensed use limited to: Univ of Calif San Diego. Downloaded on June 24,2010 at 23:56:50 UTC from IEEE Xplore. Restrictions apply. 27 good opportunity to increase the control speed and resolution using a high performance DAC, especially since the digital technologies have improved drastically in recent years. This digitally-assisted technique has been also applied in different applications, such as DSP pre-distortion in power ampliﬁers [26][10].

To sum up, a good linear-in-dB RF VGA is the core circuit required to accom- plish a high performance AGC-based linear-in-dB RF envelope detector. Various techniques have been proposed to achieve linear-in-dB control for RF VGA, and each has its own advantages and disadvantages.

Using a BJT’s inherent IC –VBE is the most straightforward way. Because of the high fT , and its inherent exponential dependence between collector current (IC) and base-emitter voltage (VBE), the SiGe HBT has signiﬁcant advantages in designing high performance linear-in-dB RF VGAs. A weak-inversion MOSFET provides the other opportunity to implement linear-in-dB functions in CMOS technology,. Nevertheless, the resultant gm is small and this sets the limit of its maximum operating frequency. Moreover, the weak-inversion behavior is sensitive to process variations and affects the robustness of the entire linear-in-dB control. A pseudo-exponential polynomial function approximates the exponential function by the ratio of two polynomials. It has been widely used in CMOS RF linear- in-dB VGAs because its simplicity, but with moderate linear-in-dB errors owing to its approximation-oriented nature. A digitally controlled DAC offers a chance to overcome the control difﬁculties with an advanced DSP. Even though the minimum gain control increment is set by the DAC’s resolution, as the digital technology improves drastically, digitally-assisted linear-in-dB Control with a high resolution DAC is still promising and becomes an attractive research topic in future years.

1.5 Dissertation Objective and Organization

This dissertation can be divided into two broad sections. The first part of this dissertation focuses on the SiGe HBT broadband linear amplifiers. While bipolar linear amplifiers has been studied extensively for many years, a new improved broadband 28 highly-linear HBT amplifier is proposed based on the variation of Caprio’s quad. It improves the input swing range limitation of Caprio’s quad and maintains its highly-linear properties. The second part of this dissertation focuses on the design of linear-in-dB SiGe HBT wideband AGC-based envelope detectors. First, an improved dynamic model of fast-settling linear-in-dB AGC circuit is proposed to analyze its explicit transient behavior. Based on this, a linear-in-dB RF envelope detector was implemented in the Tower- Jazz Semiconductor 0.18 µm SBC BiCMOS process. Several circuit design techniques are also proposed to enhance the detector’s performance. The dissertation is organized as follows: Chapter 2 presents a highly linear SiGe HBT broadband differential amplifier. We will begin with a thorough review of the existing linearization schemes and discuss their pros and cons. We will then introduce the improved linear transconductor based on a variation of Caprio’s quad. Two key issues on utilizing the proposed quad in to amplifier applications (i.e input impedance matching and stability) will be addressed with their corresponding solutions. Measurement results will be presented to validate theoretical predictions and simulations. Chapter 3 describes an improved dynamic model of a fast-settling linear-in-dB AGC circuit. The traditional Taylor series approximation will be reviewed in the beginning, and an explicit model will be proposed by solving the closed-loop time-domain behavioral ordinary differential equations (O.D.E.). A second-order large-signal model of the AGC circuit will be also provided to predict the loop’s behavior with parasitics. For each case, calculation and simulation results will be both furnished to verify the proposed mathematical models. Chapter 4 provides an implemented wideband SiGe HBT linear-in-dB envelope detectors. Key circuit building blocks, such VGA, peak detector, gm-C filter, linear- in-dB controller, V-I converter will be presented with innovative circuit designs. The overall performance of this work will be compared to other state-of-the-art works. Chapter 5 concludes the dissertation. It summarizes the key research results of broadband amplifiers and linear-in-dB envelope detectors, and discusses the possibilities on improving the existing designs. Future research areas will also be suggested. Chapter 2

An Improved Broadband High Linearity SiGe HBT Differential Ampliﬁer

2.1 Introduction

Broadband baseband high-linearity amplifiers are widely used in many applications, such as Cable Television (CATV) signal distribution [27][4][28], instrument interfaces [29][30] and Digital Subscriber Line (DSL) drivers [31][32]. In order to provide immunity to common-mode interference, fully differential topologies are extensively utilized [24]. These amplifiers are typically realized in commercial GaAs technology, and improved silicon-based circuit approaches will result in lower cost implementation of these key building blocks. To meet the required linearity and noise specifications, various linearity enhancement techniques were developed, such as resistor degeneration [25][20], Caprio’s Quad [33], series-and-shunt feedback [7] [8], feedback with operational amplifiers [34] and the Cascomp [5]. However, these techniques still have a variety of noise, linearity and dynamic range limitations. Since loop gain is limited by transistor speed, linearity typically declines at higher frequencies [25]. Caprio’s Quad [33], shown in Fig. 2.1(a), demonstrates excellent linearity, but

29 30 has a limited input voltage range due to the forward-biasing of the base-collector junction under large-signal operation. The Cascomp [5] improves linearity by adding a second error correction amplifier, known as a “cascode differential pair”, but the circuit requires higher supply voltages. Resistive series and shunt feedback [7][8] are very effective in improving linearity, but at the expense of a relatively high noise figure. Caprio’s Quad [33] improves the linearity by adding a cross-coupled transistor pair in series with the emitters of the original differential pair. The cross-coupled pair corrects the incomplete cancellation of the original differential pair. Hence, its linearity is improved at high frequencies compared with traditional feedback approaches [35]. However, the base-collector junctions of the cross-coupled pair will become forward-biased if the input signal’s amplitude exceeds the p-n junction turn-on voltage — roughly 0.8V. Once the cross-coupled pair becomes forward-biased, the linearity degrades dramatically. The circuit is also prone to instability, due to the the negative resistance appearing in the emitter due to the cross-coupled pair [53]. In this chapter, a broadband linear SiGe differential topology is proposed based on a variation of Caprio’s Quad [33]. This variation has similar linearity response and power supply requirements as Caprio’s Quad, but an improved input voltage range. The stability of the circuit is analyzed, and an improved stabilization approach is proposed for this class of circuits. The resulting amplifier exhibits extremely broadband response, with high linearity across a wide bandwidth, as well as unconditional stability, excellent noise and low dc power consumption. The chapter is organized as follows: Section 2.2 describes the improved transconductance cell operation. Section 2.3 investigates its stability properties. Section 2.4 and 2.5 summarize implementation and measurement results. Section 2.6 compares the state-of-art linear amplifiers and provides conclusions.

2.2 Improved Linear Ampliﬁer Design

2.2.1 Linearity of Improved Cell

The large-signal loop voltage of Caprio’s Quad (Fig. 2.1(a)) can be written as 31

(a)

(b)

Figure 2.1: Different linearity enhancement techniques: (a) Caprio’s Quad and (b) improved Gm cell. 32

vIN − vBE1 − vBE4 + 2Ree∆I + vBE3 + vBE2 = 0. (2.1)

since vBE1 ≈ vBE3 and vBE2 ≈ vBE4, ∆I ≈ −vIN/2Ree — a very linear result. Never- theless, the input voltage swing range of Caprio’s Quad is limited by the cross-coupled base-collector junctions of Q3 and Q4. When vIN exceeds one junction turn-on voltage – roughly 0.8V – the base-collector junction of Q3 will become forward-biased and the linear operation will not be preserved.

To improve the input voltage swing range, a Gm cell, based on a variation of Caprio’s Quad, is shown in Fig. 2.1(b) [35]. The improved cell is composed of two translinear loops: Q1-Q4-Q8-Q5 and Q3-Q2-Q6-Q7. The input voltage loops can be expressed as

vIN − vBE1 − vBE4 − 2Ree∆I + vBE8 + vBE5 = 0. (2.2) and

vBE3 + vBE2 − vBE6 − vBE7 = 0. (2.3)

but vBE2 ≈ vBE4, vBE3 ≈ vBE1, vBE6 ≈ vBE8 and vBE5 ≈ vBE7, so ∆I ≈ vIN/2Ree. The resultant differential output current is (1+K)vIN/2Ree. The improved Gm cell preserves the linearity characteristics of Caprio’s Quad while doubling the input voltage range; the base-collector junctions of Q3-Q4 and Q7-Q8 will not become forward-biased until vIN exceeds 2vBE – roughly 1.6V. In communication applications, the linearity is usually characterized by intermodulation distortion (IM) and third- order input referred intercept point (IIP3) [36]. These weakly nonlinear HF characteristics can be calculated by the Volterra series method [54]. The nonlinear transfer function is given by

vout = H1(s1) ◦ vin(s1) 2 + H2(s1,s2) ◦ vin(s1 + s2) 3 + H3(s1,s2,s3) ◦ vin(s1 + s2 + s3) + ... (2.4) 33

To simplify the analysis, we assume that: 1) the current gain β is assumed to be >> 1, 2) the base-emitter capacitor Cbe is gmτF , where gm is the transconductance and τF is the forward transit time of the bipolar transistors [12], 3) the product gmRee is much greater than unity, 4) the ratio ∆ f / f is much less than unity, where f is the input frequency and ∆ f is the frequency spacing of the two-tone signal, 5) the source impedance RS is purely resistive, as it will be for broadband applications. The nonlinear transfer function of the improved cell is derived from the differential half-circuit of Fig. 2.2. By performing a nodal analysis and expressing the voltages vbe1,vbe2, vbe4 and vin, we have

vbe1 1 gee(s(1 + K)Cbe1 − Kgm1) H1,1(s) = = (2.5a) vin 2 K∆imp vbe2 1 geegm1 H2,1(s) = = (2.5b) vin 2 ∆imp vbe4 1 gee(sCbe1(K + 1) + gm1) H4,1(s) = = (2.5c) vin 2 ∆imp where gee = 1/Ree and

2 2 ∆imp ≈ s Cbe1(K + 1) 2 + sCbe1gm1(K + 2) + gm1 (2.6) if gm >> gs,gee, and K = Iee1/Iee2. The ﬁrst-order transfer function is

vout(s) 1 (1 + K)gm1gee(sCbe1 − gm1) H1(s) = = − (2.7) vin(s) 2 gL∆imp

At low frequencies, H1(s) is approximately

1 + K RL H1(s) ≈ , (2.8) 2 Ree 34

Figure 2.2: Equivalent odd-mode half-circuit

Because the proposed cell ideally has no even-mode response, the second-order Volterra kernel is roughly zero. The third-order distortion can be calculated by adding the nonlinear sources to each of the nonlinear components [54].

The nonlinear sources iNL3Cbe , iNL3gπ , iNL3gm are (for Q1) [54]

gm1 iNL3gm = 2 H1,1(s1)H1,1(s2)H1,1(s3) (2.9) 6VT (s + s + s )g τ i 1 2 3 m1 H s H s H s NL3Cbe = 2 1,1( 1) 1,1( 2) 1,1( 3) (2.10) 6VT gm1 iNL3gπ = 2 H1,1(s1)H1,1(s2)H1,1(s3) (2.11) 6βVT

By setting s1 and s2 to jω and s3 to − j(ω + ∆ω) , the third-order response is

− j(K + 1)3g4 ω H ( jω, jω,− j(ω + ∆ω)) ≈ ee (2.12) 3 5 3 2 48K gm1VT ωT if gmRee and β are both >> 1 and ∆ f << f . 35

The third-order intermodulation distortion (IM3) of the output voltage at frequency f + 2∆ f can be estimated by taking the ratio of (2.12) and the fundamental component (2.7). Therefore IM3 can be approximated as :

A2 f (K + 1)2 IM3 ≈ in (2.13) 3 3 2 5 32gm1ReeVT fT K where gm1 is the transconductance of Q1,Q3,Q5,Q7 and Ain is the amplitude of vin. The IIP3 can be solved from (2.13) by setting IM3 = 1.

s 3 3 5 IT Ree K fT VIIP3imp ≈ 5 . (2.14) VT (K + 1) f

where IT is the overall current consumption of the improved Gm cell. Equation (2.14) shows that VIIP3Imp can become very large with a high fT device.

The noise ﬁgure of the proposed Gm cell can also be derived assuming f << fT and β >> 1, as

2 2 K + 1 1 3Ree K Ree Fimp = 1 + + + 2 K gmRs Rs K + 1 RsRL K g R2 + 2K + m ee (2.15) 2(K + 1) Rs

2.2.2 Comparison of Improved Cell to Other Linearization Schemes

Resistive Degeneration

The linearity of a standard resistive degeneration differential pair can be calculated in a similar manner.

At low frequencies, where f << fT , the VIIP3Deg can be approximated as [25] [55] [56]

s 3/2 3 3 IT Ree 2IT Ree VIIP3Deg ≈ 4VT 1 + ≈ (2.16) 2VT VT 36

if IT Ree >> 2VT . The noise ﬁgure of the resistively degenerated ampliﬁer is:

2 1 Ree 1 1 + gmRee FDeg ≈ 1 + + + (2.17) 2gmRs Rs RsRL gm

Caprio’s Quad

Suppose a two-tone signal with frequency components ∆ f + f and f is fed into

Caprio’s Quad, its linearity can be calculated in a similar manner. If Ree, β are large, and

∆ f << f , the third-order intermodulation distortion (IM3) of the output voltage Vout at frequency f + 2∆ f can be estimated as :

A2 f IM3 ≈ in (2.18) cap 3 3 2 8gmReeVT fT

VIIP3 can be solved from (A.22) by setting IM3cap=1 as follows:

s 3 3 IT Ree fT VIIP3cap ≈ . (2.19) VT f

where IT is the overall current consumption. Compared with the differential pair with degeneration resistance, VIIP3cap is not only a function of the product IT Ree, but also a function of the frequency ratio f / fT . Equation (A.24) shows that the Caprio’s Quad has roughly the same VIIP3 as the proposed Gm cell in (2.14) with a large value of K. With a high fT device, VIIP3Imp can become very large, which is similar to Caprio’s Quad. Through a noise analysis, the noise ﬁgure of Caprio’s Quad can also be derived as follows:

2 2 4gmRee Ree 2Ree FCap ≈ 1 + 2 + + (2.20) Rs(1 + 2gmRee) Rs RLRs which is greater than the resistive degeneration cell’s case. To validate our theory, the calculated and simulation IIP3 of Caprio’s Quad, the improved Gm cell and differential pair with emitter degeneration at 20MHz is shown in 37

60 Caprio Sim. Caprio Cal. 50 Improved Sim. Improved Cal.

30 IIP3(dBm)

Resistor Degeneration Simulation/ Calculation 20

10 20 40 60 80 100 Frequency (GHz) T

Figure 2.3: IIP3 vs cut-off frequency ( fT ) of Caprio’s Quad, improved Gm cell and differential pair with emitter degeneration at 20MHz. Simulation parameters: Ree = 250Ω, RL = 50Ω, K=2.8. Overall current consumption IT =2mA .

Fig. 2.3. The volt-to-dBm conversion is based on a 50 Ω normalizing impedance [57]. For an ideal transconductor, a flat transconductance response with respect to input voltage is desired. To the improved input voltage swing range, the simulated normalized transconductance of the differential pair with emitter degeneration, Caprio’s Quad and the improved Gm cell is shown Fig. 2.4. To highlight the transconductance flatness, a 0.1 % Gm compression point is adopted to define the input voltage swing range. It can be seen that the input voltage swing range of the improved Gm cell is roughly doubled, and is superior to either Caprio’s Quad or the classic emitter degeneration transconductance cell. A figure-of-merit (FOM) for a high-frequency transconductor was defined as follows [58]:

IIP3(mW) 1 FOM1 = 10log (2.21) F − 1 Pdc(mW)

which normalizes the linearity, Noise Factor F and power consumption Pdc. However, 38 &'()!!" '''''''''''''''''''''''''''''''''''''''''''$%(&' *$$+!##≈ * !""# $!% # $()+ %&#

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Where Vswing, deﬁned by the 0.1% Gm compression point,# represents the input swing %%'&'!"% range for circuit normal operation,"" and V + is ! the "" minimum'''''''''''''''''''''''$%#&' required supply voltage. 2/"& =% + + + DD#$,min #&''''& The table of comparison! at 0 20 0MHz 0 and 1%& 200MHz ! for emitter degeneration, Caprio’s ,) ## Quad and the improved GW#&m!""""""cell''' is shown in Table'''''''''''''''''''''''''''''''''$%!&' 2.1 The improved Gm cell has a similar 6789:;71!67?@A 234% =% +# + + FOM to the Caprio’s'&''''0 Quad$%+ # but ! "" with & doubled 0 1 the 0 input voltage swing range, which is a 5) 6789:;B71!C:3A signiﬁcant improvement for high-frequency applications.# # !"!"((+%% !R+"' "" ' 2N< % =%# +# $ + + # $ .389;DE1!%3!67?@A %&%&(&''(''+% +) ! 0 0 0 1

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715 39

Table 2.1: Table of Comparison for Different Transconductors

Gm Performance at 20MHz Type IIP3(dBm) NF(dB) Pdc(mW) Vswing(Volt) VDD,min(Volt) FOM(dB) Degen. 20.9 4.9 6.0. 0.6 0.9 8.1 Cap. 50.0 4.4 6.0 0.4 1.6 33.8 Imp. 46.7 6.5 6.0 0.9 1.6 31.0 Gm Performance at 200MHz Type IIP3(dBm) NF(dB) Pdc(mW) Vswing(Volt) VDD,min(Volt) FOM(dB) Degen. 20.9 4.9 6.0. 0.6 0.9 8.1 Cap. 39.8 4.4 6.0 0.4 1.6 23.6 Imp. 33.7 6.5 6.0 0.9 1.6 18.0

2.3 Impedance Matching and Stability

Most broadband ampliﬁers require broadband impedance matching networks to maximize the power transfer at their inputs and outputs [59] [60]. A shunt-shunt resistive broadband feedback topology [20] was chosen to match ampliﬁers’ input/output impedance to the system characteristic impedance ZO with a wide bandwidth.

2.3.1 Input Impedance of the Improved Cell

The input impedance of the improved cell is (assuming negligible rb)

2 1 Ree(s + ωT ) (s + K+1 ωT ) Zin,imp ≈ (2.23) 2 K K 2 ωT (s + K+1 ωT s − K+1 ωT )(s + β )

The real part of (2.23) can be approximated by

ω2 −Reeβ(1 + β(K + 4) 2 ) ωT Re(Zin,imp) ≈ (2.24) 2 ω2 2 ω2 K(1 + β 2 )(1 + ( K + 3) 2 ) ωT ωT

The negative impedance results from the improved cell’s cross-coupled pair. Similarly, the input impedance of Caprio’s Quad is: 40

-0.5k

-1k

-1.5k

-2k Impedance (Ohm) Impedance

-2.5k

-3k 7 8 9 10 11 10 10 10 10 10 Frequency (Hz)

Figure 2.5: Real part of input impedance of the improved cell and Caprio’s Quad. Ree = 14Ω, fT =100GHz, β = 100 and IT =2mA.

R (s + ω )2 Z ≈ ee T in,cap ωT (2.25) (s + ωT )(s − β )

The real part of (2.25) can be approximated by

ω2 −Reeβ(1 + 3β 2 ) ωT Re(Zin,cap) ≈ (2.26) ω2 2 ω2 (1 + 2 )(1 + β 2 ) ωT ωT

The real part of simulated/calculated input impedance of the improved cell and Caprio’s Quad are shown in Fig. 2.5.

2.3.2 The Closed-Loop Input Impedance of Shunt-Shunt Feedback Ampliﬁer

A shunt-shunt feedback ampliﬁer is proposed, based on the improved cell, to realize an improved input match and linearity. The shunt-shunt feedback ampliﬁer’s 41

15 Gain (dB) Gain 10

0 7 8 9 10 11 10 10 10 10 10 Frequency (Hz)

200

150

100 Phase(Degree)

0 7 8 9 10 11 10 10 10 10 10 Frequency (Hz)

Figure 2.6: Gain and phase of the proposed cell with shunt-shunt feedback resistor RF and different K values. Simulation parameters: Ree = 14Ω, RF = 310Ω, RL = 50Ω, fT =100GHz, β = 100, IT =120mA. 42 input admittance is

(1 − Aamp) Yin,amp ≈Yin,imp + (2.27) RF

where Yin,imp = 1/Zin,imp, RF is the feedback resistor and Aamp is the voltage gain of the ampliﬁer. Through a small-signal analysis, the gain of shunt-shunt feedback ampliﬁer is calculated in (2.28), and the simulated/calculated Bode plots are shown in Fig. 2.6.

vout− − vout+ Aamp = vin+ − vin− 2 RF RF 2 R s + ( )ωT s − ( )ω ≈ L Ree Ree T ωT (2.28) RF + RL (s + ωT )(s + K+1 )

Equation (2.28) shows the gain transfer function has two poles/zeros, and their frequencies are

r r r RF 1 RF RF ωz ≈ −ωT + + 4 Ree 2 Ree Ree r r r RF 1 RF RF ,ωT − + + 4 (2.29) Ree 2 Ree Ree and

ω ω ≈ −ω ,− T (2.30) p T K + 1

Notice that the right-half plane zero adds extra phase shift in addition to the two poles. The simulated and calculated input admittance of the proposed shunt-shunt feedback ampliﬁer, with different K values are shown in Fig. 2.7. As expected, the low- frequency impedance is mainly determined by RF . However, at higher frequencies, the impedance is dominated by Yin,imp. The resulting mismatch limits the ampliﬁer’s bandwidth and degrades the stability factor [59][60]. An improved matching technique is required to mitigate the input mismatch at higher frequencies. 43

0.05 in,amp in,amp 0.04 amp F in,imp

0.03

0.02 Admittance(mS)

0.01

0 7 8 9 10 11 10 10 10 10 10 Frequency (Hz)

Figure 2.7: Input admittance magnitude of the improved cell using shunt-shunt feedback resistor RF with different K values. Ree = 14Ω, RF = 310Ω, RL = 50Ω, fT =100GHz, β = 100, IT =120mA.

2.3.3 Improved Matching Circuits for Broadband Shunt-shunt Feedback Ampliﬁer Based on the Improved Cell

As shown in Fig. 2.7, the amplifier’s admittance Yin,amp will be dominated by the original proposed cell’s input admittance Yin,imp at higher frequencies. Fig. 2.8 shows a shunt-shunt feedback amplifier based on the improved cell. The self-bias resistor RBB is used to set the DC base voltages of Q1 and Q5. If RFH >> RF , the input admittance of the amplifier becomes

0 (1 + Aamp) Yin,amp ≈ Yin,amp + (2.31) RFH + 1/sCFH

where Yin,amp is the original amplifier’s input admittance in (2.27), and Aamp is the gain of the amplifier. Combining (2.28) and (2.31), if |Aamp| >> 1, and ω << ωT , then (2.31) can be simplified to 44

Figure 2.8: Improved input matching techniques: 1)RFH-CFH feedback, 2) Rin-Cin termination.

-20

-22

-24

-26 FH FH

FH FH -28

Input Reflection Coefficient (dB) FH

-30 7 8 9 10 11 10 10 10 10 10 Frequency (Hz)

Figure 2.9: Magnitude of input reﬂection coefﬁcient S11 after adding auxiliary RFH- CFH feedbacks. Ree = 14Ω, RF = 310Ω, RL = 50Ω, β = 100, RFH = 15kΩ, RBB = 1.5k, fT =100GHz, and IT =120mA. 45

0 in

in -10 in in in -20 Input Reflection Coefficient (dB)

-30 7 8 9 10 11 10 10 10 10 10 Frequency (Hz)

Figure 2.10: Magnitude of input reﬂection coefﬁcient S11 after adding Rin-Cin terminations. Ree = 14Ω, RF = 310Ω, RL = 50Ω, fT =100GHz, β = 100, RFH = 15kΩ, CFH = 0.1pF, RBB = 1.5k, Rin = 5Ω. and IT =120mA.

0 RL s Yin,amp ≈ Yin,amp − (2.32) RF Ree s + ωFH

0 where ωFH = 1/RFHCFH. Equation (2.32) shows the magnitude of Yin,amp can be low- ered by amount of RL/(RF Ree) at higher frequencies, to compensate for the increase of the original amplifier’s input admittance Yin,amp. Fig. 2.9 shows the simulated input reflection coefficient S11 of the amplifier. With proper choice of RFH −CFH, S11 can be further minimized. However, because of the cross-coupld quad nature, the proposed amplifier’s input admittance is still dominated by the Yin,imp when the input frequency is comparable to the transistor’s cut-off frequency fT , and the real part of the input impedance is negative. To mitigate the negative real input impedance/admittance when the input frequency is close to fT , a series combination of Rin and Cin is added at the input as shown 46

3 in in in

1 K Factor K

in in -1 7 8 9 10 11 10 10 10 10 10 Frequency (Hz)

Figure 2.11: Simulated K-factor after adding Rin-Cin terminations. Ree = 14Ω, RF = 310Ω, RL = 50Ω, fT =100GHz, β = 100, RFH = 15kΩ, CFH = 0.1pF, RBB = 1.5k, Rin = 5Ω. and IT =120mA.

in Fig. 2.8. Figure 2.10 shows the simulated input reﬂection coefﬁcient S11. With the addition of Rin-Cin, S11 is always below 0dB when the operating frequency is close to fT . Figure 2.11 shows the simulated K-factor [57], which is always greater than unity with the proposed improvement to ensure stability.

2.4 Experimental Setup

The ampliﬁer is fabricated in Jazz Semiconductor’s 0.18µm SiGe SBC18 BiC- MOS process [61], and is shown in Fig. 2.12. The chip occupies 1.2 × 0.8 mm2 die area including the pads. The measurement setup is shown in Fig. 2.13. An Agilent PNA-X Series Mi- crowave Network Analyzer N5242A, with 4-port interface, is used to characterize the S-parameter broadband behavior. The chip’s input and output are probed by two GGB GSGSG 40GHz RF probes with 125 µm pitch-to-pitch distance. The circuit is biased by external DC supplies through DC probes. Two Bias Tees are put after the output RF 47

Bias Generation

Input Gm Output Match. Cell Match. 0.8mm

1.2mm

Figure 2.12: Chip microphotograph. probes to provide the DC bias current and couple the RF signals to the PNA-X. Noise ﬁgure was measured using the direct method [24] by an Agilent 8970B Noise Figure Meter. The linearity is characterized by generating the two-tone signals from Agilent N5181A MXG RF Analog Signal Generator with M/A COM H-183-4 30MHz-3GHz Microwave 180 degree Hybrid with 0.3dB loss. Fig. 2.14 shows the picture of the laboratory bench.

2.5 Measurement Results

The S-parameter simulation and the measurement results are shown in Fig. 2.15 with close agreement. The measured S21 has 10.4dB gain and 1.37GHz 3dB bandwidth, which is similar to the simulated S21 with 10.7dB gain and 1.56GHz 3dB bandwidth.

The measured/simulated S11 and S22 is less than -10dB when input frequency is less than 400MHz, and below 0dB when input frequency reaches to the GHz range. The S12 is approximately -16dB , which is mainly due to the reverse feedthrough of the shunt- 48

Figure 2.13: Experimental setup

DC Power Supplies

Tested Agilent PNA-X Chip Network Analyzer

GSGSG RF Probe

Figure 2.14: Laboratory bench for broadband linear ampliﬁer IC evaluation 49

15 21 10 21 5

0 11

-5 22 11

-10 22 Magnitude(dB) -15

-20

-25 12

-30 12 7 8 9 10 10 10 Frequency (Hz)

Figure 2.15: Measured/Simlulated S-parameters. shunt feedback. The noise figure was measured using the direct method [24] by an Agilent 8970B Noise Figure Meter. The noise figure performance is shown in Fig. 2.16 with good agreement with simulation result and has a 6dB minimum value. The linearity measurement results are shown in Fig. 2.17. The linearity performance is characterized by a two tone test with tone spacing 10KHz, with center frequencies from 20MHz to 1.5GHz. The amplifier has 46dBm OIP3 at 20MHz. As expected, the OIP3 drops to 30dBm at 1.5GHz because of it decreased gain and degraded 1/2 IIP3, which is proportional to the ( fT / f ) ratio in (2.14). The maximum output P1dB is 10.33dBm and drops when input frequency reaches to GHz range. Table 2.2 compares the performance of the circuit to existing wideband linear amplifiers. 50

4 Magnitude(dB)

0 7 8 9 10 10 10 Frequency (Hz)

Figure 2.16: Measured/Simulated noise ﬁgure.

20 Power (dBm) Power 1dB 10

0 7 8 9 10 10 10 Frequency (Hz)

Figure 2.17: Simulated and measured P1dB, IIP3, OIP3. 51

Table 2.2: Wideband Linear Ampliﬁer Comparison Sinderen[62] Lee[63] Kobayashi [64] This Work Device BiCMOS GaAs InP SiGe Technology pHEMT HBT HBT Min. Vcc 3.3V 5V 5V 4V Min. IDC 40mA 100mA 35mA 120mA RF BW. 0.1-0.86GHz 0.2-2.6GHz 0.5-3GHz 0.02-1GHz Max. P1dB N/A 22.5dBm 13.3dBm 10.3dBm Max. OIP3 24dBm 40dBm 40.5dBm 46dBm NF 7dB 3dB 5dB 6dB Gain 6dB 14.6dB 9.5dB 10dB

2.6 Conclusion

An improved all-npn broadband highly linear SiGe HBT amplifier based on a variation Caprio’s Quad is presented. The wideband linear amplifier has 46dBm OIP3 at 20MHz, 34dBm OIP3 at 1GHz, 6dB noise figure, and 10.3dBm output P1dB. The amplifier’s input/ouput reflection coefficients are less than 0dB for all frequencies thanks to the improved input matching techniques. The chip occupies 1.2mm×0.8mm die area. The proposed amplifier can be used as a general purpose gain block for medium power broadband linear amplification applications. This chapter, in part or in full, is a reprint of the material as it appears in Pro- ceedings of IEEE International Symposium on Circuits and Systems (ISCAS) 2007, and has been submitted to IEEE Transaction of Circuit System I (TCAS-I). The dissertation author was the primary researcher and the first author listed in these publications. Chapter 3

Improved Dynamic Model of Fast-Settling Linear-in-dB Automatic Gain Control Circuit

3.1 Introduction

Automatic Gain Control (AGC) circuits are used in many systems, where the input amplitude varies over a wide dynamic range and the output amplitude is designed to achieve a certain specified level. An AGC circuit is usually composed of a peak detector (PD), a variable gain amplifier (VGA), and a loop filter, as shown in Fig. 3.1 [65]. The output of the VGA is detected by the peak detector, and compared with a reference voltage Vre f . Since the gain of the VGA is adjusted according to the amplitude of the input, the resulting output amplitude is constant. AGC circuits can be categorized according to different gain characteristics of the VGA. One of the most popular types is the "Linear-in-dB" VGA, whose gain control has an exponential characteristic [14]. As a result of this characteristic, an exact analysis of the large-signal settling behavior of the Linear-in-dB circuit is very difficult. Previous authors have used a Taylor series expansion to approximate the exponential function in the overall loop analysis [65][66][67], which is only valid for small input level variations. One important use of this VGA is as a feedback control element for a wideband

52 53 polar transmitter [10][68]. These circuits require a very wide dynamic range for their operation and therefore an exact analysis of the settling behavior of the Linear-in-dB VGA is needed. In light of this, we present an exact dynamic large-signal model of a linear-in- dB AGC circuit. Our proposed model is capable of describing the entire loop large- signal behavior, and exactly predicts the overall loop settling time dependence on input amplitude variations. The chapter is organized as follows: Section 3.2 reviews the AGC loop operation and derives the ﬁrst-order exact steady-state large signal model. Section 3.3 generalizes the analysis to a second-order response. Section 3.4 derives the settling time of the overall loop. Section 3.5 compares the calculated settling time results with behavioral simulation results. Conclusions are provided in Section 3.6.

3.2 AGC Circuit Operation and First-order Steady -State Large-Signal Modeling

3.2.1 First-order Steady-State Large-signal Model

The ﬁrst-order basic AGC loop is shown in Fig. 3.1. According to the linear-in- dB operation of the VGA, the output of the VGA can be expressed as

V /VT Vout = Vin × α × e ctrl (3.1)

where α is the VGA gain when the control voltage Vctrl is zero, and VT is the constant representing the linear-in-dB slope. As an example, suppose an envelope-modulated signal is fed to the input of the

VGA, Vin can be written as

Vin = A × (1 + mcosωet) × cosωct (3.2)

where m is the modulation index of the envelope-modulated signal, ωe is the envelope @6>.3A95!BC:(6#*!D3592!3;!"()0?E9002#:$!F#:9(.?#:?5'!! +/036(0#*!,(#:!-3:0.32!-#.*/#0!!

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extraction operation, the output of the peak detector Vpd can be expressed as

Vpd = Peak(Vout) (3.3)

where Peak() is the peak extraction function. The output of the gm-C ﬁlter, which acts as a loop ﬁlter, can also be described as

where Vctrl is integrated from the error term Vre f -Vpd. Combining (3.1)-(3.4), we have

dV gm ctrl = × V − A × (1 + mcosω t) × α × eVctrl/VT (3.5) dt C re f e

Equation (3.5) describes the transient behavior of Vctrl of the first-order AGC circuit. It 55 is a nonlinear first-order differential equation and is difficult to solve directly. However, (3.5) can be simplified by substituting u = eVctrl/VT and then:

1 du gm Vre f 1 gm A × (1 + mcosωet) × α 2 − = − (3.6) u dt C VT u C VT

Equation (3.6) is known as the Bernoulli Equation [71] and can be solved as

 −1 −ω V gm re f t ωgmA × α mcos(ωet − φ) Aα V  u =  × r + + Pe T  (3.7)  VT ω V 2 Vre f  ω2 + gm re f e VT

−1 CωeVT gm where φ = tan , ωgm = and P is the integration constant. Finally, the control gmVre f C voltage Vctrl can be obtained by applying Vctrl = VT × ln(u) and solved explicitly as

  −ω V gm re f t ωgmA × α mcos(ωet − φ) Aα V  Vctrl = −VT × ln × r + + Pe T  (3.8)  VT ω V 2 Vre f  ω2 + gm re f e VT

3.2.2 First-order Steady-State Behavior

−ωgmVre f V t In steady state, the Pe T term in (3.8) can be neglected and Vout can also be solved explicitly by combining and substituting Vctrl of (3.8) into (3.1) and (3.8).

1 + mcosωet Vout,ss1 = ×Vre f × cosωct (3.9) mcos(ωet − φ) 1 + s ω V 2 1 + e T ωgmVre f

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ω31& /(2 . ω ω17 α / − % 31 ! & 0 0 H2#*+'->I#*+-+'<#+&'#'( 6 #+'(8#)2#!T"#0-2#='#2'7;'0+'>#-2># LL ##################!?L"# 0ω(& 6 ω (+ ω ! 7 α 0 & #0-2#-;*1#='#*1;A'>#'/,;)0)+;I#=I#018=)2)27#-2>#*4=*+)+4+)27# &&%= −−;2 01*!ωϕ " + #$% .%/0#!$"5# 0 ()ω31& /(2 0 0 *++? 0 0 ,-ω(6& 0 #########################################!P"# 34 56 !?+ 1% 01*ω " &&%= ( 01*ω #$%'+'0+1(#>';-I#=;10.#>)-7(-85## Figure 3.2: Peak detector delay block diagram.

within a very short time. If ωe is large, (3.9) implies that the AGC cannot keep the output amplitude constant.

3.3 AGC Circuit Second-order Large-Signal Model 682 3.3.1 Peak Detector Delay Model

The analysis in the previous section was concerned only with the ﬁrst-order

(single-pole) approximation, where the pole is only determined by the gm-C ﬁlter and there are no delays anywhere else in the circuit. However, as the input frequency increases, other poles in the circuit become more important [20]. Therefore, a second- order large-signal model is proposed here, which takes into account the other poles associated with the peak detector. Consider the peak detector delay model in Fig. 3.2, where the input signal is

Acos(ωt) and ωp is the angular frequency of the associated pole. In steady state, the out-

put of the peak detector delay block, Vdout(t), can be calculated by the Inverse Laplace

Transform of Vdout(s) as follows:

Aωp −1 ω Vdout(t) = q cos(ωt − φd), φd = tan (3.10) 2 2 ωp ω + ωp

3.3.2 Second-order Steady-State Behavior

If we insert the above delay block between the output of the PD and the input to

the gm-C ﬁlter to model the delay associated with the PD, as shown in Fig. 3.3, the input 57 ;;;," KLH%MNNG%=BFFM;OL%F;PB%%

01% 23&4#5*&,!&6078683&-+3#69!##.3:$6"3%!68;.-+.;#3*:6 Vin VGA Vout =:#[email protected]('.7)/% @7$% ()% KLH% 2.$21.'% 7@'#)% .)E7

ω$%) &!' I.3,A,%=#27)6Q7$6#$%KLH%2.$21.'%><72[%6.(3$(0,%F"#%67''#6%($#(%$#:$#/#)'/%'"#% ! −*+# " Figure 3.3: Second-order AGC circuit block diagram. The dotted area represents the )&!' < ) %%%%%%%%%%%%%%%%%%%%%%%*&J+% )#!%:#([%6#'#2'7$%076#<%.)2<16.)3%'"#%6#<(?%7@%'"#%:#([%6#'#2'7$,% ))!= #<)* +−− <)*& * +" +$ new peak detector model including the delay of peak detector. -#&.4& 4& " 0*& < + & < %# & ++α &$

&&ωω) ()66) %2()%>#%/7?%/1>/'.'1'.)3%*&J+%.)'7%*&+% !"#$#%g −−!"! ,% -"#)% ω ( ./% 012"% 3$#('#$% *+# of m-C ﬁlterϕ# can=+'() be calculated by combining '() * (3.2) + and (3.3), and be re-written as ωω$%) &!' ( )#&!'27/ω - %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%*&T+%   ) = *+#4& 4& ω$%) &!' '"()% 4%*&5+%$#612#/%'7%*8+%(/%#9:#2'#6,%%mωpcos(ωet − φd) −*+# ω! Vctrl/VT −ωpt < Vgmc = Aαe u(t) − e + q  (3.11) )" 2 2 &− * +! ωe + ωp & < ;)%(%/.0.<($%0())#$%'7%=#2'.7)%;;4%)*+#%()6%)(,%2()%(#% + #9:$#//#6% #9:<.2.'?% 270>.).)3%()6%/1>/'.'1'.)3%)-#&.% 7@% *&5+% F"#)%'"#%&U%/#''<.)3%'.0#6"46R&5S%7@%'"#%)*+#>4&?D/%#)E#<7:#%2()% In steady-state, the term can be ignored. By substituting Vpd with Vgmc and solving (3.1), .)'7%*&+%()6%*A+,%BC1('.7)%*&5+%(#%/7#%/#E#$#?%(%<7!% %*27$$#/:7)6.)3% )<" ! +&VV" %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%*&W+% ω! " = <) 4 )<# & $ '7% #92#//.E#% <77:% 6#<(?+,% F7% E(<.6('#% 71$% '"#7$?4% '"#%)(,% $77'% ω$% &!' % + & 0#()% /C1($#% #$$7$%ωgmωp :#$2#)'(3#%mAα 1 !.'"% $#/:#2'% '7% /ω!A"ωα #$!" @$70% O7'%/1$:$./.)3#% 2 2 ωgmV re f  (%@1)2'.7)%7@% ))X &%>1'%(#%2(<21<('#6%>?%(::#%/"7!)%(/%@7<<7!/Y%

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Figure 3.4: Second-order AGC circuit root mean square error percentage vs. (ωe/ωp) from SPICE simulation and theory . The error percentage increases when ωe increases. Simulation parameters: VT =0.6V, ωc=2GHz, Vre f =0.24V, A=1mV, gm=0.5mS and 1mS, C=2pF, α=0.1, m=0.9. shows that the loop’s overall response could be severely impeded by a low (corresponding to excessive loop delay). To validate our theory, the Vpd root mean square error percentage with respect to (ωe/ωp), from SPICE simulation and calculation, is shown in Fig. 3.4. It can be seen that the error percentage increases when(ωe/ωp) increases, and calculation and simulation results agree closely.

3.4 AGC Loop Settling Time

3.4.1 First-order AGC Circuit Settling Time Calculation

Speciﬁcations for an AGC circuit often involve certain requirements associated with the transient response, and one important ﬁgure-of-merit is the settling time [66]. A simple way of measuring this is to apply a unit step response to the system, i.e.

Vin = A1(1 + k × u(t))cosωct (3.13) 59

Where u(t) is the unit-step function and k is the input amplitude variation factor. The

ﬁrst-order Vctrl transient response with respect to the input unit-step response is

V k ωgmVre f re f − V t Vctrl,sr1 = VT ln − ln 1 − e T (3.14) A1(1 + k)α 1 + k

and Vout can be solved by substituting (3.14) into (3.1)

Vre f × cosωct Voutl,sr1 = (3.15) ωgmVre f − t − k e VT 1 1 + k

Then the 1% settling time Ts [72] of the Vout,sr1’s envelope can be solved as

VT k + 100 Ts = × ln (3.16) ωgmVre f k + 1

Not surprisingly, (3.16) shows that the settling time is not only a function of ωgmVre f /VT , but also a function of input amplitude variation ratio k.

3.4.2 Second-order AGC Circuit Settling Time Calculation

Similarly, the second-order AGC circuit settling time can also be calculated by applying a unit step response to the circuit in Fig. 3.3. The second-order Vctrl transient response with respect to input unit-step response can be shown as follows:

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Figure 3.5: Comparison of ﬁrst-order and second-order AGC circuit settling time sim- T.0>X>& G619<:.+6/& 63& 3.:+,W6:2*:& &L*,,-./0&,.1*&(s & tion of input amplitude variation ratio k.ω Simulation$ ω! parameters: V=0.6V, ω=2GHz,+ .+& <& 35/4,.6/& 63& ./95,& <19-.,52*& =<:.<,.6/& :<,.6& ,>& L.15-<,.6/& 9<:<1*,*:+f& V=0.24V, A=1mV, C= 2pF, α=0.1, m=0.9, g=1mS. *'kd>aK!&ω>k"F[_!&*!"#kd>"YK!&Ck%1K!&$%k%1L!&4k"9T!&αkd>%!&%kd>b>&

V V (t) = re f (3.18) ctrl,ssr2  ω V  p T Vre f ωgm −ωpt ω V − t 1 + e −  gm re f − 1 e VT ωpVT  ωpVT k + 1 − 1 − 1 ω V ωgmVre f gm re f

The settling time Ts is difﬁcult to be expressed explicitly from (3.18) but it can be solved iteratively. Equation (3.18) shows that the transient behavior is a function of the input amplitude variation ratio k and peak detector poleωp. If ωp is very low, the Vpd settling response is dominated by ωp rather than ωgm ×Vre f /VT . Therefore, to achieve a fast684 settling AGC circuit, it is important to increase ωp [73], ωgm, and the ratio Vre f /VT . 61

3.5 AGC Simulations and Veriﬁcation of Analysis

Behavioral level simulations are provided in this section to compare the ﬁrst- order/second-order settling time simulation results and theoretical results, where the second-order settling time is calculated iteratively. The response of the AGC circuit is shown in Fig. 3.5, where previous theories [65][66][67] did not describe the loop characteristics dependence on input amplitude variation ratio k. Note that the ﬁrst-order estimation is only valid for small (ωe/ωp) ratio .The theoretical calculation results predicted by our theory are close to SPICE behavioral level simulation results.

3.6 Conclusion

An exact dynamic model of linear-in-dB Automatic Gain Control (AGC) circuit is proposed and validated. The explicit steady-state behavior and the overall loop settling time are calculated for ﬁrst-order and second-order AGC loops. The analysis shows that the overall loop settling time depends on the input amplitude ratio, phase detector delay, and other loop parameters. This exact large-signal model can also be used for the design of wideband closed-loop polar transmitters.

This chapter, in part or in full, is a reprint of the material as it appears in Pro- ceedings of IEEE International Symposium on Circuits and Systems (ISCAS) 2007. The dissertation author was the primary researcher and the ﬁrst author listed in this publication. Chapter 4

A Linear-in-dB SiGe HBT Wideband High Dynamic Range RF Envelope Detector

4.1 Introduction

RF envelope detectors [40][74] are used in many applications, such as instrument interfaces [75], polar and envelope tracking transmitters [76]–[77], receive signal strength indication (RSSI) [78][41], power control [42][79], voltage standing-wave ratio (VSWR) measurements [80] and automatic gain control (AGC) circuits [81][82]. When detecting wide dynamic range RF signals, "linear-in-dB" detectors generate an output proportional to the logarithm of the input envelope [12][83] and can be classified into two types: logarithmic amplifiers and AGC-based detectors [42]. Log- arithmic amplifiers rely on the progressive compression of cascading gain cells, with summing/filtering at each stage to produce a rectified voltage [43]–[45]. For high peak- to-aveage ratio (PAR) signals, AGC-based detectors (also referred to as "true RMS" detectors) operate in a closed-loop manner – the input signal is detected by an AGC with linear-in-dB VGA/attenuator. The output of the VGA/attenautor is a constant when the loop is locked, and the envelope information is extracted from the control voltage [48][49][85].

62 63

Figure 4.1: Block diagram of linear-in-dB envelope detector.

In this chapter, an improved AGC-based linear-in-dB envelope detector is proposed. The chapter is organized as follows: Section 4.2 reviews the AGC-based power detector. Section 4.3 covers the implementation of sub-blocks. Section 4.4 and 4.5 show the measurement results.

4.2 AGC-based Linear-in-dB Envelope Detector Opera- tion

The basic AGC-based linear-in-dB envelope detector is shown in Fig. 4.1. The output of the VGA can be expressed as:

Venv(t)/VC Vout(t) = Vin(t) × α × 10 (4.1)

where α is the VGA gain constant and VC is the exponential slope. If Vin(t) is an envelope modulated signal: 64

Vin(t) = Vin,env(t) × cosωct (4.2)

where Vin,env(t) is the envelope and ωc is the carrier angular frequency.

An ideal peak detector will extract the envelope Vin,env(t) in (4.2). i.e.

Venv(t)/VC Vpd(t) = Vin,env(t) × α × 10 (4.3)

Vre f gm When the bandwidth of Vin,env(t) is relatively small compared with × [86], the VC C loop forces Vpd(t) to the reference voltage Vre f . Hence Venv(t) is

V V (t) ≈ − C × 20log(V (t)) +V (4.4) env 20 in,env K where VK = VC × log(Vre f /α).

4.3 Circuit Design

The linear-in-dB VGA function is realized by a chain of cascaded VGAs and gain stages, a V-I converter and a linear-in-dB controller.

4.3.1 Gilbert Multiplier Type VGA

Fig. 4.2 shows the variable gain stage, which keeps the output of the VGA constant when the input signal varies [53]–[88]. The voltage gain is approximately

I R 1 − eVctrl/VT A ≈ EE L × (4.5) VGA V /V IEEREE +VT 1 + e ctrl T

where VT is KT/q. Equation (4.5) shows that a linear-in-dB control is needed. 65

Figure 4.2: Variable gain stage. The control voltage is provided by the linear-in-dB controller.

Figure 4.3: Fixed gain stages with gain broadening. The second gain stage’s input is in parallel with a differential pair with a degenerated capacitor CEE/2 to cancel out the dominant pole due to the load. 66

7 8 9 10

Figure 4.4: Bandwidth broadening simulation/calculation results. IEE1−4= 1mA, VCC=3V, RL1=RL2=0.5K, REE1=REE2=0.125K, Cc=10pF, CL=0.1pF.

4.3.2 Gain Stages with Bandwidth Broadening

Fig. 4.3 shows the ﬁxed gain stages with bandwidth broadening. The second gain stage’s input is in parallel with a differential pair Q9 −Q10 with a capacitor CEE/2, which serves to broaden the bandwidth. The high frequency voltage gain of two gain stages can be approximated as

g0 g g0 g ( m1 m3 )(s + m2 m3 ) C2 C (g0 +g ) A ≈ L EE2 m2 m3 (4.6) (s + gm3 )(s + 1 )(s + 1 ) CEE2 RL1CL RL2CL

0 0 where gm1 ≈ 1/REE1, gm2 ≈ 1/REE2 and gm3 = IEE3/VT . The circuit generates a zero and mitigates the roll-off due to dominant pole 1/RL2CL and 1/RL3CL to extend the bandwidth. Fig. 4.4 shows the simulation/calculation results of the bandwidth broadening. 67

Figure 4.5: Linear-in-dB controller for Gilbert multiplier VGA. The difference between −IconRcon/VT IC4 and IC5 will be proportional to e .

4.3.3 Linear-in-dB Controller for Gilbert Multiplier Type VGA

Fig. 4.5 shows the linear-in-dB controller for a Gilbert multiplier type VGA, where Icon is the control current proportional to Venv from the output of V-I converter (in

Fig. 4.1). When Icon ﬂows through Rcon, IC1 will be

−IconRcon/VT IC1 = IC2,3 × e . (4.7)

Therefore the controller’s output voltage is

−IconRcon/VT Vctrl = VT × ln(1 + e ) (4.8)

Combining (4.5) and (4.8), AVGA is

−8.7 × IconRcon IEERL dB(AVGA) ≈ + dB (4.9) VT IEEREE +VT

Equation (4.9) shows the gain of the VGA is linear-in-dB to the control current. The 68

Figure 4.6: V-I converter to generate Icon. The output current Iconis proportional to the differential voltage Vctrl and IPTAT . temperature dependance of VT is cancelled by setting Icon proportional to absolute temperature (PTAT).

4.3.4 V-I Converter

Fig. 4.6 shows the V-I converter to transform Venv to Icon [89]. The differential input voltage Venv is linearized by a PMOS degenerated differential pair M1-M2. Based on the translinear loop Q1-Q4, the output current Icon can be approximated as

Venv IPTAT ISS1IPTAT Icon ≈ + (4.10) 2RSS IBG IBG

where IPTAT is a PTAT current source and IBG is a constant current source. The current mirror M3-M4 and Q5-Q6 are used to compensate the base current of Q4.

4.3.5 Adaptive Biasing Peak Detector

Fig. 4.7 shows the peak detector [90] with adaptive discharging current source

IC6. When the input Vin drops, IC6 will increase to speed up the discharging process of 69

Figure 4.7: Adaptive biasing peak detector. IC6 adjusts to the input signal to speed charging/discharging.

Cpd. When Vin increases, IC6 will become smaller to assist Cpd’s charging process.

Fig. 4.8 shows the Vpd −Vre f settling behavior with/without adaptive biasing techniques. The discharging time can be signiﬁcantly improved by selecting the appropriate K value.

4.3.6 Multi-tanh Differential gm-C Filter

Fig. 4.9 shows a multi-tanh differential gm-C filter composed of four asymmetric differential pairs. In order to speed the settling, a modified multi-tanh gm profile is applied as shown in Fig. 4.10 [91]. When |Vre f −Vpd| is large, the transconductance is enhanced to speed the charging/discharging process without sacrificing stability.

4.4 Experimental Setup

The detector chip is fabricated in TowerJazz Semiconductor’s 0.18µm SiGe SBC18 BiCMOS process [92], and is shown in Fig. 4.11. The chip occupies 1.8 × 1 mm2 die area including the pads. 70 ref pd

Without Adaptive Biasing

K=1 K=1.5

K=2

Figure 4.8: Simulation results of Vpd −Vre f with/without adaptive biasing techniques where K is the current mirror ratio. Input carrier frequency equals to 1.7GHz.

Figure 4.9: Multi-tanh differential gm-C ﬁlter. The differential pairs are asymmetric to improve the AGC loop settling time without sacriﬁcing stability. 71

Figure 4.10: Multi-tanh simulated gm proﬁle. The transconductance is offset to speed the AGC loop without sacriﬁcing stability.

Figure 4.11: AGC-based envelope detector chip microphotograph. The chip occupies 1.8 × 1 mm2 die area including the pads. . 72

Agilent MSO Oscilloscope

DC Power Agilent MSG Analog Supplies Tested Chip Signal Generator

Figure 4.12: Laboratory bench of SiGe HBT linear-in-dB AGC-based envelope detector IC evaluation. .

The linear-in-dB measurement is performed by direct on-chip probing. The input signal is generated from Agilent N5181A MXG RF Analog Signal Generator with M/A COM H-183-4 30MHz-3GHz Microwave 180 degree Hybrid with 0.3dB loss. The envelope output is connected to Agilent MSO6054A Mixed Signal Oscilloscope with 1MΩ input impedance with 14pF load capacitor. Fig. 4.12 shows the picture of the laboratory bench.

4.5 Measurement Results

The measurement results are shown in Fig. 4.13. Fig. 4.13(b) shows linear-in- dB error for different input power and frequencies. When the input frequency is close to 1GHz, the optimal dynamic range is 50dB with +-2dB error range. The error degrades at higher frequency – the dynamic range reduces to 30dB when the frequency increases to 2.2GHz. When the input signal is small, the linear-in-dB error is limited by the isolation between VGA and gain stages. When the input signal is large, the linear-in-dB error is mainly dominated by the mismatches of Gilbert type VGA devices [93]. The -10dBm to -60dBm transient impulse response is shown in Fig. 4.14 and a 10%-90% settling time is adopted here. The envelope detector’s rising/falling edge settling time is ranging from 60ns to 200ns and 100ns to 490ns, respectively. Table 4.1 compares existing linear-in-dB and linear envelope detectors. 73

0.95

0.9

0.85

0.8

0.75 Envelope Output Voltage(Volt)

0.7 -50 -45 -40 -35 -30 -25 -20 -15 Input Power(dBm)

(a)

-1 Linear-in-dB error(dB) Linear-in-dB

-2

-50 -45 -40 -35 -30 -25 -20 -15 Input Power(dBm)

(b)

Figure 4.13: Linear-in-dB measurement results (a) Venv vs. input power of the envelope detector. (b)linear-in-dB error vs. input power of the envelope detector. 74

500

400

300

200 Settling Time (ns) Time Settling

100

0 0 0.5 1 1.5 2 2.5 Input Signal Frequency (GHz)

Figure 4.14: Envelope settling time for different input frequencies. Input power varies from -10dBm to -60dBm.

4.6 Conclusion

A 2.5GHz 50dB dynamic range linear-in-dB envelope detector operating with 3V power supply is presented. The detector consumes 34mA supply current with 1.8 mm2 die area. This chapter, in part or in full, is a reprint of the material as it appears in Pro- ceedings of IEEE Radio Frequency Integrated Circuits (RFIC) Symposium 2010. The dissertation author was the primary researcher and the ﬁrst author listed in this publication. 75

Table 4.1: Table of Comparison: AGC-based Linear-in-dB RF Power Detectors. AD8362 HMC614LP4 Cha This Work Type Linear-in-dB Linear-in-dB Linear Linear-in-dB Min. Vcc 4.5V 5V 1.8V 3V Min. IDC 24mA 65mA 1mA 34mA RF BW. 0-3.8GHz 0.1-3.9GHz 1-2.4GHz 0.2-2.5GHz Max. DR. 65dB 70dB 35dB 50dB Slope 50mV/dB 40mV/dB 1V/V 5.7mV/dB Accuracy +-1dB +-1dB N/A +-2dB Min. TRise 45ns 34ns >200ns* 60ns Min. TFall 400ns 620ns >200ns* 100ns Reference [48] [49] [40] This work *:Estimate from 5MHz sine-wave envelope bandwidth. Chapter 5

Conclusions

The two important applications of high performance SiGe HBT technology, as stated in the Introduction, are broadband high linearity ampliﬁers and wideband linear- in-dB high dynamic range envelope detectors. They have been designed, simulated, fabriacted and veriﬁed through architectures to circuit implementations. In conclusion, the achieved key innovations are summarized and followed by the suggestions for future research directions.

5.1 Key Research Results

We have developed a broadband high linearity SiGe HBT differential ampliﬁer and a wideband linear-in-dB high dynamic range envelope detector in a 0.18 µm SiGe HBT BiCMOS process. The accomplished key research results are mentioned as follows:

5.1.1 Key Research Results of Broadband High Linearity SiGe HBT Differential Ampliﬁers

Improved Input Voltage Swing High Linearity Transcondcutor

The proposed transconductor features an improved input voltage swing by properly connecting two Caprio’s Quad with two translinear loops. Since the variation is

76 77 based on Caprio’s quad, the improved transconductor is inherently highly linear.

Volterra Series Derivations and Veriﬁcations of Caprio’s Quad and the Proposed

Gm Cell

A Volterra series analysis is performed to validate emitter resistor degeneration,

Caprio’s Quad and the proposed Gm cell’s linearity and compared with the simulation results. From the analysis, the proposed Gm Cell’s linearity can be further improved by using high fT bipolar transistors, such as SiGe HBTs.

Broadband Differential Ampliﬁer with Stabilized Input Matching Circuits

Based on the proposed transconductor, a broadband differential amplifier is designed using resistive shunt-shunt feedback network. To solve the high-frequency instability caused by the transcondcutor’s negative impedance, two improved stabilization approaches are proposed. The resulting amplifier exhibits extremely broadband response, with high linearity across a wide bandwidth. A broadband linear amplifier with 46dBm OIP3 at 20MHz, 34dBm OIP3 at 1GHz, 6dB noise figure and 10.3dBm

P1dB is demonstrated.

5.1.2 Key Research Results of Linear-in-dB SiGe HBT Wideband High Dynamic Range RF Envelope Detectors

Explicit Dynamic Model of Fast-settling AGC-based-Linear-in-dB Envelope Detec- tors

To fully understand AGC-based linear-in-dB envelope detector’s operation, and overcome the dynamic range limitations of the traditional Taylor series approximation, an explicit mathematical model is proposed by solving the closed-loop time-domain behavioral O.D.E.s. A second-order large signal model of AGC circuit will be also provided to predict the loop’s behavior with parasitics. The proposed models provide useful insights and precise settling time estimation of AGC-based linear-in-dB envelope detectors. 78

Wide Dynamic Range Linear-in-dB Controller for a Gilbert Multiplier-based RF VGA

A linear-in-dB controller is proposed to control the Gilbert-type Multiplier-based

RF VGA. Because of BJT’s IC-VBE dependence, the controller generates a current that is an exponential function of the input control voltage. Through a translinear loop, the Gilbert Multiplier-based VGA’s top differential pair’s biasing current is forced to vary with the control signal, and behaves in a linear-in-dB way.

Bandwidth Broadening Technique for Gain Stages

A bandwidth broadening technique is proposed by using a differential pair with emitter capacitor degeneration to generate a zero, and mitigate the gain roll-off due to output dominant pole. Different than traditional narrow bandwidth gain-peaking approaches, this technique provides ﬂat gain response from low frequencies up to its 3dB bandwidth.

Fast Adaptive Biasing Peak Detector

An adaptive biasing peak detector is proposed to perform fast peak detection with low DC power consumption. The proposed peak detector’s DC biasing current is changing with input signal’s envelope. The discharging time is signiﬁcantly improved when compared with the traditional peak detectors.

Multi-tanh Differential gm-C Filter

Unlike the traditional multi-tanh techniques, a multi-tanh differential gm-C ﬁlter composed of four asymmetric differential pairs is proposed, which has a local minimum at zero input, and two local maximum when input’s amplitude is large. It expedites the loop the settling time without sacriﬁcing stability.

Linear-in-dB Wideband High Dynamic Range RF Envelope Detector

Based on the above techniques, a linear-in-dB wideband, SiGe HBT high dynamic range RF envelope detector is presented. The detector operates from 200MHz 79 to 2.5GHz with 50dB maximum dynamic range. The detector consumes 34mA supply current from 3V supply and occupies 1.8 mm2 die area.

5.2 Directions for Future Research

Relentless Cost Reduction is one of the major trends in commercial communication ICs. Even though the SiGe HBT has superior performance, CMOS technology has taken over most of the commercial communication applications such as GSM, EDGE, WCDMA, GPS, 802.11a/b/g and Bluetooth, mainly due to its advantages of low fabrication cost and high integration. While the proposed broadband highly linear SiGe HBT ampliﬁer and high dynamic range RF envelope detector works well with a SiGe process, it would be beneﬁcial to investigate the possibilities to support CMOS processing using similar system architectures and circuit implementations.

Because of the cross-coupled topology, the proposed Gm cell suffers instability from high-frequency negative impedance. Although two proposed stabilization techniques mitigate the instability at high frequencies, they also limit the usable bandwidth of the achieved shunt-shunt feedback ampliﬁer. It will be beneﬁcial to come up with a better solution, in a more clever way, to push this highly- linear transconductor operating frequency up to the 10’s of GHz range.

The proposed Gm’s linearity can be improved signiﬁcantly, as derived from the

Volterra analysis, by higher fT bipolar transistors. To examine the ultimate linearization limits, it will be interesting to implement similar circuits in more advanced HBT processes with higher fT , and observe the resultant linearity. The practical issues over process and temperature variations should also be examined.

Besides the AGC-based wideband linear-in-dB SiGe HBT RF envelope detectors, the logarithmic ampli fier’s possibilities should be explored as well. A conspic- uous advantage of the logarithmic ampliﬁer is that the linear-in-dB operation relies on the entire system ( progressive compression of cascading gain cells ), rather than BJT’s 80

Ic-VBE dependence. It provides a good opportunity to realize wideband RF linear-in-dB envelope detectors in commercial CMOS processes and further reduce the cost. To the author’s knowledge, a wideband high dynamic range RF CMOS logarithmic ampliﬁer is still a popular ongoing research topic. Appendix A

Volterra Series Kernel Analysis of Emitter Resistor Degeneration and Caprio’s Quad

A.0.1 Volterra Series Analysis of Differential Pair with Degenera- tion Resistors

The Volterra series analysis of differential pair with degeneration resistors is shown here. The ﬁrst kernel is calculated from its half small-signal circuit, which is shown in Fig. A.1(a), where Vin/2 is the input signal which connects the base and the ground, rπ and Cπ are the base-emitter resistor and capacitor, Ree is the emitter degeneration resistor, gm is the transconductance of the bipolar transistor, RS is the source resistance and RL is the resistive load which connects the collector and the supply voltage VDD. By performing a nodal analysis, we have

−V1(gs + sCπ + gπ ) +V2(sCπ + gπ ) = −gsVin/2 (A.1)

V1(sCπ + gπ + gm) −V2(sCπ + gπ + gm + gee) = 0 (A.2)

gmV1 − gmV2 + gLVout = 0 (A.3)

81 82

Figure A.1: Small-signal half circuits of differential Pair with resistive degeneration resistors for Volterra series analysis: (a) ﬁrst-order kernel analysis (b) third-order kernel analysis. 83

Where gee, gπ , gS and gL are 1/Ree, 1/rπ , 1/RS and 1/RL respectively. Dividing (A.1) -

(A.3) by Vin and re-writing them in matrix form, the resultant matrix can be derived as   −gs − sCπ − gπ sCπ + gπ 0    sC + g + g −sC − g − g − g 0   π π m π π m ee  gm −gm gL | {z } ADegen(s)     H1,1st(s) −gs/2     × H (s)  =  0  (A.4)  2,1st    Hout,1st(s) 0 | {z } | {z } BDegen,1st (s) CDegen,1st (s)

Where ADegen(s) is the admittance matrix which describes the characteristic of the circuit. BDegen,1st(s) is the ﬁrst-order kernel matrix which is composed of H1,1st(s), H2,1st(s) and Hout,1st(s), which can be also treated as the ﬁrst-order transfer function from Vin to

V1, V2 and V3 respectively. CDegen,1st(s) represents the excitation input. After applying Cramer’s rule, we have

sC g + g (g + g + g ) H (s) = π s s π m ee (A.5) 1,1st 2det(s) sC g + g (g + g ) H (s) = π s s π m (A.6) 2,1st 2det(s) gm −geegs H (s) = gL (A.7) out,1st 2det(s)

Where det(s) = sCπ (gs + gee) + gπ gee + gs(gπ + gm + gee). If Ree and β are large, the differential output Hout,1st,di f f can be calculated as doubled Hout,1st, and can be approximated as

−gmRL Hout,1st,di f f (s)≈ (A.8) sCπ (RS + Ree) + (gmRee + 1)

When s=0, the Hout,1st,di f f (s) becomes gmRL/(1 + gmRee), which is the well-known small-signal gain at low frequencies. 84

The third-order kernel can also be derived by following the similar method. Fig. A.1(b) shows the third-order small-signal circuit for Volterra series analysis by connecting the original input Vin/2 into ground and adding three nonlinear current sources iNL3gm, iNL3Cπ and iNL3gπ . After applying Kirchoff’s current law, the following matrix can be derived

 0 0  −gs − s Cπ − gπ s Cπ + gπ 0    s0C + g + g −s0C − g − g − g 0  (A.9)  π π m π π m ee  gm −gm gL | {z } ADegen(s)     H1,3rd(s1,s2,s3) iNL3Cπ + iNL3gπ     × H (s ,s ,s )  = −i − i − i   2,3rd 1 2 3   NL3gm NL3Cπ NL3gπ  Hout,3rd(s1,s2,s3) −iNL3gm | {z } | {z } BDegen,3rd(s) CDegen,3rd(s)

0 Where s = s1 + s2 + s3. iNL3gm, iNL3Cπ , iNL3gπ can be written as

gm iNL3gm = 2 H12,1st(s1)H12,1st(s2)H12,1st(s3) (A.10) 6VT 0 s gmτ iNL3Cπ = 2 H12,1st(s1)H12,1st(s2)H12,1st(s3) (A.11) 6VT gm iNL3gπ = 2 H12,1st(s1)H12,1st(s2)H12,1st(s3) (A.12) 6βVT

Where H12,1st(s) = H1,1st(s)−H2,1st(s) represents the ﬁrst-order transfer function which controls the transconductance gm. After applying Cramer’s rule, the output third order kernel can be calculated as follows:

iNL3gm Hout,3rd(s1,s2,s3) = − gL

gm iNL3gmgs + (iNL3Cπ + iNL3gπ )(gee + gs) + 0 (A.13) gL det3rd(s ) 85

0 0 Where det3rd(s ) = s Cπ (gs + gee) + gπ gee + gs(gπ + gm + gee). Suppose a two-tone signal with frequency components ∆ f + f and f is fed into differential pair with degeneration resistor. The third-order intermodulation response at Hout,3rd can be calculated from equation (A.13) by setting its argument (s1,s2,s3) to ( j2π f , j2π f ,− j2π( f + j∆ f )). If Ree, β are large, and ∆ f << f , Hout,3rd can be approximated as

Hout,3rd( j2π f , j2π f ,− j2π( f +∆ f )) 3 gee −gm gee gm ≈ 2 f g f g (A.14) 24V gL (g + g )3(1 + j ) (1 + ee ) + j (1 + ee ) T m ee fT gm fT gs

Where the quantify fT is the cut-off frequency of the bipolar transistor, and is evaluated as gm/2πCπ . Combing equation (A.7) and (A.14), the third-order input referred intercept point voltage (VIIP3) at frequency f − 2∆ f can be calculated as

s 4 H out,1st( j2π f ) VIIP3Deg ≈ 3 Hout,3rd( j2π f , j2π f ,− j2π( f +∆ f )) s 3/2 2 gm + gee f = 4VT 1 + (A.15) gee fT

At low frequencies, where f << fT , the VIIP3Deg can be approximated as [25] [55] [56]

3/2 IT Ree VIIP3Deg ≈ 4VT 1 + . (A.16) 2VT

where VT is the thermal voltage, Ree is the emitter degeneration resistor and IT =2Iee is the overall current consumption of the differential pair. Equation (A.16) shows the well-known result that the VIIP3Deg strongly relies on the product IT Ree. 86

A.0.2 Volterra Series Analysis of Caprio’s Quad

The Volterra series analysis of Caprio’s Quad can also be derived in a similar way. Since the Caprio’s Quad has a cross-coupled pair at its tail, it is difﬁcult to draw its corresponding small-signal half circuit directly. Several approximations are used here to simplify the derivation of its half circuit to calculate the ﬁrst/third kernel: 1) The transconductance gm of all transistors are approximated equal. 2) As shown in Fig. A.2(a), two opposite voltage-controlled voltage sources(VCVS) with equal magnitude, which are labeled as VX and −VX , are introduced at the bases of Q3 and Q4 to break the cross-coupled base connections and remove transistor Q2. 3) Because the base of Q3 and Q4 are driven differentially by −VX and VX , the collector current of Q3 can be modeled as a voltage-controlled current source(VCCS) gmVπ4 with direction opposite to Q4 with the omission of Q3’s emitter degeneration resistor Ree. As shown in Fig. A.2(b). By performing a nodal analysis and express voltages into Vπ1, Vπ4 and Vin, we have

(sCπ + gπ )Vπ1 + gmVπ1 = −gmVπ4 + (sCπ + gπ )Vπ4 (A.17)

Vin (sCπ + gπ )Vπ1 − −Vπ1 −Vπ4 2 gs g V + (sC + g )V − m π4 π π π4 = 0 (A.18) gee

Dividing (A.17) - (A.18) by Vin and re-writing them in matrix form, the ﬁrst-kernel matrix can be derived as

" # sCπ + gπ + gm gm − sCπ − gπ

sCπ + gπ + gs gs + gs(gm + sCπ4 + gπ )/gee | {z } ACaprio(s) " # " # Hπ1,1st(s) 0 × = (A.19) Hπ4,1st(s) gs/2 | {z } | {z } BCaprio,1st (s) CCaprio,1st (s) 87

Figure A.2: Caprio’s Quad half circuit simpliﬁed steps: (a) applying VCVS VX and −VX and (b) resultant small-signal half circuit for calculating ﬁrst and third kernels. 88

Where Hπ1,ist(s) and Hπ4,ist(s) are the transfer function from Vin to Vπ1 and Vπ4. The

ﬁrst-order transfer function from Vin to Vout, Hout,1st, can be calculated as Hπ1(s)×gm/gL by applying Cramer’s rule on (A.20). The third-order distortion can also be calculated by adding the corresponding nonlinear sources iNL3gm, iNL3Cπ , iNL3gπ to Fig. A.2(b) and set the input voltage source

Vin/2 to zero. The third-order kernel matrix can be derived as follows:

" # Hπ1,3rd(s1,s2,s3) ACaprio(s) × Hπ4,3rd(s1,s2,s3) | {z } BCaprio,3st (s)   iNL3Cπ4 + iNL3gπ4 − iNL3gm4    −i − i − i   NL3Cπ1 NL3gπ1 NL3gm1  =  (A.20) −iNL3C − iNL3g   π1 π1  − gs (i + i + +i ) gee NL3gm4 NL3Cπ4 NL3gπ4 | {z } CCaprio,3st (s)

0 Where s = s1 + s2 + s3. iNL3Cπ4 .iNL3gπ4 ,iNL3gm4 are the third-order nonlinear VCVS sources of Hπ4,1st, and iNL3Cπ1 ,iNL3gπ1 ,iNL3gm1 are the third-order nonlinear VCCS current sources of Hπ1,1st. The values of nonlinear sources can be calculated by equation

(A.10) – (A.12) by replacing ﬁrst-order kernels with Hπ1,1st and Hπ4,1st . The third-order distortion Hout,3rd,(s1,s2,s3) at the output node can be estimated as

3 3 Hout,3rd,(s1,s2,s3) = Ain(Hπ1,3rd,(s1,s2,s3) × gm + Inlgm1) (A.21) 4gL

where Ain is the input amplitude (in Volt). Suppose a two-tone signal with frequency components ∆ f + f and f is fed into Caprio’s Quad, its third-order behavior can be estimated by setting its argument

(s1,s2,s3) to ( j2π f , j2π f ,− j2π( f + ∆ f )). If Ree, β are large, and ∆ f << f , the third-order intermodulation distortion (IM3) of the output voltage Vout at frequency 89 f − 2∆ f can be estimated by taking the ratio of (A.21) and the fundamental component

AinHout,1st( j2π f ). Therefore IM3 can be approximated as :

A2 f IM3 ≈ in (A.22) cap 3 3 2 8gmReeVT fT

VIIP3 can be solved from Equation (A.22) by setting IM3cap=1 as follows:

s √ f VIIP3 ≈ 2 2V g3 R3 T (A.23) cap T m ee f

where VIIP3cap represents the third-order input referred intercept point voltage of the quad. VIIP3cap can be further simpliﬁed as

s 3 3 IT Ree fT VIIP3cap ≈ . (A.24) VT f

where IT is the overall current consumption.

Compared with the differential pair with degeneration resistance, VIIP3cap is not only a function of the product IT Ree, but also a function of the frequency ratio f / fT . It can be seen that the linearity can be further improved by using high fT bipolar transistors. Bibliography

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