Tunneling Based Quantum Functional Devices and Circuits for Low Power Vlsi Design

TUNNELING BASED QUANTUM FUNCTIONAL DEVICES AND CIRCUITS FOR LOW POWER VLSI DESIGN

DISSERTATION

Presented in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy in the Graduate School of The Ohio State University

Anisha Ramesh

Graduate Program in Electrical and Computer Science

The Ohio State University

2012

Dissertation Committee:

Professor Paul R. Berger, Advisor

Professor Marvin H. White

Professor Patrick Roblin

Anisha Ramesh

2012

ABSTRACT

Handheld devices, such as cellphones, dominate consumer electronics market today and are foreseen to grow further in future years. One of the primary challenges with these devices is reducing the power consumption while keeping the operating frequencies high. Scaling of transistor dimensions has contributed to both increasing chip operating frequencies and greater functionality per unit area. However, as dimensions enter a few

10’s of nanometer, leakage currents have also increased, escalating the overall power consumption. Scaling of supply voltage is a key to keep both dynamic and static power consumption low. Tunneling-based devices are investigated to address this challenge.

Tunnel diodes in conjunction with conventional transistors can be used in novel circuit topologies to develop high speed circuits operating below 0.5V. However, large scale manufacture requires a Si-based device structure that can be fabricated with tools compatible with standard CMOS processing. In this dissertation, Si-based resonant interband tunnel diodes (RITD) are fabricated using chemical vapor deposition (CVD).

High peak to valley current ratio's (PVCR) of 5.2 are obtained through optimization of the boron δ-doping with peak current densities of 20 A/cm2. This is the largest PVCR for silicon based tunnel diodes fabricated using CVD.

Further, integration into a standard electronic design automation (EDA) tools is essential to enable development of very large scale integrated (VLSI) circuits. Tunnel

ii diodes have been integrated into the Cadence EDA tool and a 32 × 32 bit tunneling

SRAM (TSRAM) memory array has been designed with a standard 90 nm product development kit (PDK) obtained from MOSIS, for use as embedded memory. This provides a platform to compare TSRAM performance with the currently dominant

SRAM and embedded DRAM technologies. Its performance and robustness to process variation is evaluated for a supply voltage of 0.5V. Read access times of 1 ns and write access times of 0.5 ns are obtained with a standby power dissipation of 6×10-5 mW/cell and dynamic power dissipation of 1.8×10-7 mW/MHz per cell. These are comparable to the 90 nm SRAM specifications obtained from the international technology roadmap for semiconductors (ITRS).

Tunnel FETs are a promising alternate to MOSFETs for low power design due to the ability to scale threshold voltage and hence supply voltage, without increase in OFF currents. However, they suffer from low ON currents. Prior experience with tunnel diode optimization is used to investigate new TFET structures to improve tunneling ON currents. A 300 nm channel Si vertical p-TFET with an n δ-doping has an ON current of

4 0.05 µA/µm at a VDS of 2.5V with an ION-IOFF ratio of 10 . Addition of Ge in the channel, to form a for a 30 nm Si0.9Ge0.1 channel, enhances the ON current to 4.8 µA/µm at a VDS of 2V.

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DEDICATION

This work is dedicated in memory of my grandmother, Smt. Rukmani Kumari Jogi

ACKNOWLEDGMENTS

There are a number of people I would like to thank who have contributed to this work either professionally or personally.

First I would like to thank my advisor Prof. Paul R. Berger for his support and encouragement and allowing me to evolve as an independent researcher. He has shown more confidence in me than I have had in myself, which has helped me in coming a long way from where I started.

Next, I would like to thank my committee members Prof. Marvin H. White and

Prof. Patrick Roblin who have been an inspiration not just through their teaching but also through their achievements in life. Additionally I would like to thank Prof. Mohammed

Ismail and Prof. George J. Valco for serving on my candidacy committee and providing very valuable insights.

I acknowledge Dr. Phillip Thompson from Naval Research Laboratories (NRL) for providing us innumerable MBE samples over the years without which this research would not have been possible. I would also like to thank Dr. Richard Magno from NRL for providing the GaSb/InAs MBE samples.

I am indebted to Dr. Roger Loo at the Interuniversity Microelectronics Center

(IMEC), Leuven, Belgium for always being forthcoming in providing us with the CVD samples used in this work. I would also like to thank Dr. Wilfried Vandervorst and

Bastien Douhard from IMEC for providing the SIMS measurement data which was critical for our device analysis.

Thanks to Dr. Guy Brammertz at IMEC for serving as my mentor during my six month internship there and teaching me the conductance technique for interface state characterization. A special thanks to Dr. Philippe M. Vereecken also at IMEC, for allowing me to use his laboratory for the anodic oxidation work and for teaching me electrochemistry.

I would like to acknowledge Dr. Samit Gupta and Prof. Stephen Lee from the department of Biomedical Engineering for their help on the biosensor project.

I would specially like to thank my colleagues Dr. Si-Young Park and Dr. Woo-

Joon Yoon for being my mentors and friends and providing invaluable advice over the years. I would also like to thank all the members of the Berger group from the past and present including Dr. Ronghua Yu, Minjae Kim, Tyler Growden, Amritesh Rai, Hye Jin

Song, Fang Ren, Ying Ding, Dr. Xiaona Li, Ken Clive and Shang Wei.

A special thank you to Jim Jones for all the timely help provided by him in the cleanroom and teaching me a lot about cleanroom etiquette that I hope to always follow.

Thanks also to Mark Brenner for helping out in the cleanroom and providing III-V RTD samples. A huge thanks to the entire team at the Nanotech West facility, especially Dr.

John Carlin, Aimee Price, Derek Ditmer, Paul Steffen and Dr. Robert Davis for all the timely help and support.

Thanks to all the members of the IEEE graduate student body specially Pat

Wensing and Dr. John Hu for their initiative in starting this organization. It is a great

vi platform for graduate students to mingle and grow professionally and make the years of research life a lot more fun. I wish the organization grows even more in the years to come.

Finally I would like to thank my family. My grandmother, who, despite not being very educated herself, is singly responsible in ensuring all her children and grandchildren have a doctoral degree. She has truly been an inspiration. My parents for planting the research bug in my brain at an age when I actually had no idea what they were talking about but made me ever so curious to explore the life of a researcher. My brother, Dr.

Manish Ramesh, the person I have looked up to the most in my life and my sister-in-law

Dr. Yashodhara Dash, both of whom have always set the bar very high for me. Finally I would thank my nephew Sohum, who just turns one, for providing a lot of joy and the renewed inspiration to never let the child’s curiosity die within me. Wish him a lot of success in life and to quote from Star Trek “may all your desires be fulfilled except for one, so you will always have something to strive for”.

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VITA

February 18, 1981 ...... Born - Mysore, Karnataka, India 2002...... B.Tech., Instrumentation and Electronics, College of Engineering and Technology, Bhubaneswar, India 2006...... M.Tech., Electrical Engineering, Indian Institute of Technology, Bombay, India 2006 -2007 ...... University Fellow, The Ohio State University 2007-2010 ...... Graduate Teaching Associate, The Ohio State University 2010-2011 ...... Graduate Research Associate, The Ohio State University 2011-2012 ...... Presidential Fellow, The Ohio State University

PUBLICATIONS

Book Chapter

P. R. Berger and A. Ramesh, "Negative Differential Resistance Devices and Circuits," In Comprehensive Semiconductor Science and Technology, edited by Pallab Bhattacharya, Robert Fornari and Hiroshi Kamimura, Vol. 5, pp. 176-241, Amsterdam: Elsevier, 2011

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Research Publications

A. Ramesh, P. R. Berger and R. Loo, "High 5.2 peak-to-valley current ratio in Si/SiGe resonant interband tunnel diodes grown by chemical vapor deposition," Applied Physics Letters, Vol. 100, p. 092104, 2012

A. Ramesh, T. A. Growden, P. R. Berger, R. Loo, W. Vandervorst, B. Douhard and M. Caymax, "Boron delta-doping dependence on Si/SiGe resonant interband tunneling diodes grown by chemical vapor deposition," Transactions on Electron Devices, Vol. 59(3), p. 602, 2012

A. Ramesh, S-Y. Park and P. R. Berger, "90 nm 32 × 32 bit Tunneling SRAM Memory Array with 0.5 ns write access time, 1 ns read access time and 0.5 Voltage operation," Transactions on Circuits and Systems-I, Vol. 58(10), p. 2432, 2011.

S. K. Gupta, H-H. Wu, K. J. Kwak, P. Casal, T. R. Nicholson III, X. Wen, R. Anisha, B. Bhushan, P. R. Berger, W. Lu, L. J. Brillson and S. C. Lee, "Interfacial design and structure of protein/polymer films on oxidized AlGaN surfaces," Journal of Physics D: Applied Physics, Vol. 44, p. 034010, 2011.

T. R. Nicholson III, S. Gupta, X. Wen, H-H. Wu, R. Anisha, P. Casal, K. J. Kwak, B. Bhushan, P. R. Berger, W. Lu, L. J. Brillson, S. C. Lee, "Rational enhancement of nanobiotechnolgical device functions illustrated by partial optimization of a protein- sensing field effect transistor," Proceedings of the Institution of Mechanical Engineers Part N: Journal of Nanoengineering and Nanosystems, Vol. 223(3-4), pp. 149-161, 2010

S-Y. Park, S. J. Di Giacomo, R. Anisha, P. R. Berger, P. E. Thompson and I. Adesida,

"Fabrication of nanowires with high aspect ratio utilized by dry etching with SF6 :C 4F8 and self-limiting thermal oxidation on Si substrate", Journal of Vacuum Science and Technology B, Vol. 28(4) p. 763, 2010

S-Y. Park, R. Anisha, P. R. Berger, R. Loo, N. D. Nguyen, S. Takeuchi, and M. Caymax, "Si/SiGe Resonant Interband Tunneling Diodes incorporating delta-doping layers grown by chemical vapor deposition," IEEE Electron Device Letters, Vol. 30(11), p. 1173, 2009

R. Yu, R. Anisha, N. Jin, S-Y. Chung, P. R. Berger, T. J. Gramila and P. E. Thompson,

"Observation of strain in pseudomorphic Si1-xGex by tracking phono participation in Si/SiGe resonant interband tunnel diodes via electron tunneling spectroscopy," Journal of Applied Physics, Vol. 106, p. 034501, 2009

P. E. Thompson, G. G. Jernigan, S.-Y. Park, R. Yu, R. Anisha, P. R. Berger, D. Pawlik, R. Krom and S. L. Rommel, "P and B doped Si resonant interband tunnel diodes with as- grown negative differential resistance," Electronic Letters, Vol. 45(14), p. 759, 2009

R. Anisha, N. Jin, S-Y. Chung, R. Yu, P. R. Berger and P. E. Thompson, "Strain engineering Si/SiGe resonant interband tunneling diodes with outside barriers grown by

Si0.8Ge0.2 virtual substrates," Applied Physics Letters, Vol. 93, p. 102113, 2008

FIELDS OF STUDY

Major Field: Electrical and Computer Engineering

TABLE OF CONTENTS

Abstract ...... ii

Dedication ...... iv

Acknowledgments...... v

Vita...... viii

List of Tables ...... xv

List of Figures ...... xvi

Chapter 1 Introduction ...... 1

1.1 Motivation ...... 1

1.2 Objective...... 2

1.3 Overview of the dissertation...... 4

Chapter 2 Quantum Mechanical Tunneling - Physics and Devices...... 6

2.1 Rectangular Barrier - Intraband Tunneling ...... 7

2.2 Double Rectangular Barrier - Resonant Intraband Tunneling...... 11

2.3 Arbitrary Potential Variation - WKB Approximation ...... 20

2.5 Conclusion ...... 33

Chapter 3 Tunnel Diode Digital Circuits ...... 34

3.1 Tunnel Diode Device Model ...... 34

3.2 Tunnel Diode Device Performance Metrics ...... 36

3.3 MOnostable-BIstable Logic Element (MOBILE) ...... 38

3.4 Tunneling Static Random Access Memory (TSRAM) ...... 51

3.5 Conclusion ...... 55

Chapter 4 Tunneling Static Random Access Memory...... 56

4.1 Static Random Access Memory (SRAM) ...... 57

4.2 Embedded Dynamic Random Access Memory (eDRAM) ...... 62

4.3 Tunneling Static Random Access Memory (TSRAM) ...... 66

4.4 Performance Comparison ...... 92

4.5 Conclusion ...... 93

Chapter 5 Si/SiGe Heterostructure and Delta Doping ...... 95

5.1 Si/SiGe Heterostructure - Strain and Critical Thickness ...... 96

5.2 Electrical Properties of Si/SiGe Heterostructures ...... 98

5.3 Epitaxial Growth ...... 105

5.4 Delta Doping ...... 113

5.5 Conclusion ...... 122

Chapter 6 Si/SiGe Resonant Interband Tunnel Diode ...... 123

6.1 Structure of Si/SiGe Resonant Interband Tunnel Diode ...... 124

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6.2 Prior work using LT-MBE ...... 125

6.3 Device fabrication using CVD ...... 127

6.4 Boron flow rate optimization...... 128

6.5 Use of Arsenic instead of Phosphorus for n doping ...... 137

6.6 Tunneling barrier thickness variation study ...... 139

6.7 Variation of n cap doping ...... 143

6.8 Performance variation across the wafer ...... 145

6.9 Conclusion ...... 146

Chapter 7 High-K Dielectrics ...... 148

7.1 Properties of High-κ Dielectrics ...... 149

7.2 Requirements for a Gate Dielectric ...... 152

7.3 Passivation of III-V semiconductors ...... 155

7.4 Gate oxide characterization using a metal-oxide-semiconductor capacitor ...... 157

7.5 Anodic oxidation technique for stoichiometric control of GaAs native oxide...... 166

7.6 Atomic Layer Deposition ...... 183

7.7 High-κ dielectrics for ion impermeability in in-vivo Biosensors ...... 184

Chapter 8 Tunneling Field Effect Transistors...... 199

8.1 Device Structure ...... 202

8.2 Device Fabrication Process ...... 209

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8.3 Process Optimization ...... 210

8.4 Results ...... 217

8.5 Conclusion ...... 221

Chapter 9 Conclusion and Future Work ...... 222

9.1 Si/SiGe Resonant Interband Tunnel Diodes ...... 222

9.2 Tunnel Diode VLSI circuit design ...... 223

9.3 Anodic oxidation for III-V passivation ...... 223

9.4 High-κ dielectrics in bio-sensors ...... 224

9.5 Tunneling field effect transistors...... 225

Appendix A Tunnel Diode integration into Cadence ...... 226

Appendix B RITD Fabrication Process ...... 236

Appendix C TFET Fabrication Process ...... 242

Appendix D MATLAB code ...... 247

Appendix E SILVACO code ...... 250

BIBLIOGRAPHY ...... 253

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LIST OF TABLES

Table 3.1 Output of multi-threshold logic gate...... 50

Table 4.1 Quantitative comparison of various embedded memory cell performance ...... 91

Table 4.2 Qualitative comparison of voltage scalability prospects of embedded memories

...... 92

Table 5.1 Prefactor and activation energy in eV for bulk diffusion in Silicon ... 116

Table 7.1 Bandgap and conduction band offsets for high-κ dielectric materials...... 152

Table 7.2 Gibbs free energy of stable III-V oxides ...... 156

Table 7.3 XPS results for anodic oxide grown by cyclic voltammetry ...... 173

Table 7.4 Relationship between increased alkali ion concentration into thermal SiO 2 oxide (~100nm) and soak time in physiological buffer solution (PBS) ...... 196

LIST OF FIGURES

Figure 2.1 Rectangular tunneling barrier showing incident, reflected and transmitted wavefunctions ...... 7

Figure 2.2 Transmission Coefficient for a In0.53Ga0.47As/AlAs barrier with barrier width 4 nm and barrier height of 1 eV. The electron effective mass used for In0.53Ga0.47As is 0.041m0 and for AlAs is 0.11m0. Contradictory to classical predictions, the transmission coefficient is not 1 for electron energies greater than the potential barrier, but is oscillatory...... 10

Figure 2.3 Double barrier structure showing amplitudes of forward and backward wave functions in each region ...... 11

Figure 2.4 Transmission probability for a In0.53Ga0.47As/AlAs double barrier with barrier width of 2 nm, separated by a quantum well of 4 nm width. Barrier height is 1 eV, showing resonance energy levels. The electron effective mass used for In0.53Ga0.47As is 0.041m0 and for AlAs is 0.11m0. In contrast to the single barrier case, the transmission probability shows a sharp resonance peak below the barrier height with unity transmission probability...... 13

Figure 2.5 Evolution of RTD band diagram with application of voltage bias and corresponding current voltage-characteristics ...... 15

Figure 2.6 Use of undoped spacer regions adjacent to the tunneling barrier structure resulting in 2D-2D tunneling instead of 3D-2D, improving PVCR ...... 16

Figure 2.7 Slowly varying potential used in WKB approximation ...... 21

Figure 2.8 Evolution of Esaki diode band diagram with application of voltage bias and corresponding current voltage-characteristics ...... 24

Figure 2.9 Triangular barrier approximation for tunneling through the depletion region of a degenerately doped p-n junction ...... 27

Figure 2.10 Various routes for tunneling through the forbidden bandgap using impurity levels ...... 28

Figure 2.11 Various resonant interband tunnel diode designs proposed by Sweeny and Xu ...... 30 xvi

Figure 3.1 Typical current-voltage (I-V) characteristic for a tunnel diode...... 35

Figure 3.2 (a) Small signal equivalent circuit of a tunnel diode (b) unified model combining small and large signal models ...... 36

Figure 3.3 (a) Two serially connected tunnel diodes and (b) loadline illustrating the latching action ...... 38

Figure 3.4 Operating principle of monostable-bistable (MOBILE) logic ...... 39

Figure 3.5 (a) Generic MOBILE logic inverter and (b) its timing diagram ...... 40

Figure 3.6 Loadline for (a) resistor (b) transistor (c) tunnel diode load and tunnel diode driver. Tunnel diode allows maximum charging (ISO) and discharging current (ISI )...... 41

Figure 3.7 Peak current modulation of a GaAs/AlAs RTD by addition of control gate... 41

Figure 3.8 (a) Modulation of peak current by addition of transistor in parallel to a TD (b) implementation of an inverter ...... 42

Figure 3.9 (a) Modulation of peak current by addition of transistor in parallel to a TD and its implementation as an inverter (b) RTD-HFET integration to realize logic input stage and (c) its resultant I-V characteristics ...... 43

Figure 3.10 (a) Implementation of a NAND/NOR gate using the RTD-HFET integrated circuit and (b) its experimental results [49] ...... 44

Figure 3.11 Threshold logic gate using MOBILE logic ...... 45

Figure 3.12 Full adder circuit using threshold logic gates ...... 45

Figure 3.13 (a) Four stage clocking. Also showing the four phases in a clock cycle (b) nano-pipelining with a four stage clock and comparison to conventional pipelining ..... 46

Figure 3.14 (a) Vertically stacked tunnel diodes (b) the resultant current-voltage characteristics showing the multiple peaks and (c) 3 stable operating points for two such diodes serially connected ...... 48

Figure 3.15 (a) 3 input inverter and (b) its simulated result ...... 49

Figure 3.16 Multi-threshold threshold logic gate ...... 50

Figure 3.17 Three input programmable logic implementing all 256 functions. Also shown is the clocking scheme utilizing nanopipelining...... 50

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Figure 3.18 (a) basic TSRAM memory cell design and (b) the bistable latch voltages corresponding to stored logic '0' and '1' ...... 51

Figure 3.19 Gain cell modification to the TSRAM memory cell design which avoids use of external capacitor...... 52

Figure 3.20 (a) Schematic of RTD/HFET integrated TSRAM memory cell (b) loadline of RTD's and (c) measured waveforms ...... 53

Figure 3.21 (a) Cross-sectional schematic of RITD/NMOS integrated TSRAM memory cell (b) loadline of RITD's and (c) measured waveforms ...... 54

Figure 4.1 Core i7, 32 nm technology processor showing the area consumed by on-chip cache memory (source: Intel core i7 whitepaper) ...... 57

Figure 4.2 Memory cell of a static random access memory ...... 58

Figure 4.3 Butterfly plot showing the static noise margin (SNM) its reduction with noise and (b) noise source configuration to determine SNM ...... 60

Figure 4.4 VDD dependence of (a) write margin (b) static noise margin and (c) cell current at 0σ and 6σ points. Failure rate of all three parameters greatly increases with voltage scaling ...... 62

Figure 4.5 Memory cell of a dynamic random access memory ...... 63

Figure 4.6 TSRAM 3 transistor- 2 tunnel diode memory cell ...... 66

Figure 4.7 Schematic of TSRAM memory cell. All NFETs are sized with W=140 nm, L=80nm ...... 68

Figure 4.8 Layout of TSRAM memory cell...... 69

Figure 4.9 Memory architecture for a 32 × 32 bit array showing sense amplifier and writeback circuit for read-before-write operation ...... 70

Figure 4.10 Timing diagram for (a) read cycle (b) write cycle...... 72

Figure 4.11 (a) Effect of doubling the read access transistor gate width on storage node (b) memory cell with dummy transistor (c) simulated waveform with dummy transistor showing no glitch in storage node ...... 75

Figure 4.12 Current I0 charging the parasitic node capacitance after wordline is deactivated for (a) VDD = 0.5V and (b) VDD = 0.6V. The standby power consumption is given by IS ×VS ...... 76

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Figure 4.13 simulated waveforms of (a) storage node output voltage for peak currents of 700 nA, 500 nA, 400 nA and 100 nA and PVCR of 4.02 showing read '1' failure below 400 nA...... 77

Figure 4.14 (a) Simulated waveforms for (a) read/write '1' and (b) read/write '0' operation. rbw = read before write, w1 = write '1', pre = precharge, wb1 = writeback '1', rd = read cycle, w0 = write '0', wb0 = writeback '0' (Also overlapped are control signals generated during each clock cycle) ...... 77

Figure 4.15 Voltage stored at storage node for (a) read/write '1' and (b) read/write '0' operation. Also overlapped are the control signals generated during each clock cycle. FNFP: Fast NFET Fast PFET; SNSP: Slow NFET Slow PFET; FNSP: Fast NFET Slow PFET; SNFP: Slow NFET Fast PFET ...... 79

Figure 4.16 Output of sense amplifier for (a) read/write '1' and (b) read/write '0' operation. Also overlapped are the control signals generated during each clock cycle. FNFP: Fast NFET Fast PFET; SNSP: Slow NFET Slow PFET; FNSP: Fast NFET Slow PFET; SNFP: Slow NFET Fast PFET ...... 79

Figure 4.17 Cell read current (solid lines) and bitline voltage (dashed lines) during read '1' operation ...... 80

Figure 4.18 Selection of precharge voltage and sense amplifier voltage based on sense amplifier output for (a) read '1' and (b) read '0' operation for successful read operation 80

Figure 4.19 (a) Linear fit done to the NDR region for monte-carlo simulations and I-V characteristics obtained for devices with 400 and 600 nA peak current (b) Monte-carlo simulations showing PVCR variation with peak current (c) scatter in bistable latch points as a result of mismatch between the load and driver tunnel diode ...... 83

Figure 4.20 Monte-Carlo simulation results for read/write ‘1’ operation showing (a) variation in voltage written into storage node SN at the end of write cycle (b) variation in SN voltage 1 ns after wordline is pulled low, showing the restoring action of the RITDs (c) variation in output of sense amplifier at the end of read cycle...... 84

Figure 4.21 Monte-Carlo simulation results for read/write ‘0’ operation showing (a) variation in voltage written into storage node SN at the end of write cycle (b) variation in SN voltage 1 ns after wordline is pulled low, showing the restoring action of the RITDs (c) variation in output of sense amplifier at the end of read cycle...... 84

Figure 4.22 Threshold voltage variation for low threshold voltage (a) NFET (b) PFET obtained from Monte-Carlo simulations showing actual distribution and distribution with chip mean skewed to a process corner. ACV = across chip variation. RSS = root of sum of squares ...... 85

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Figure 4.23 Storage node voltage variation with across the chip variation for (a) Write ‘1’ operation skewed to slow-slow corner (b) Write ‘0’ operation skewed to slow NFET, fast PFET corner, showing no failure points...... 86

Figure 4.24 Scatter plot of sense amplifier output for (a) read ‘1’ operation skewed to slow-slow corner (b) read ‘0’ operation skewed to slow NFET, fast PFET corner with sense amplifier PFET and NFET and read transistor MN1 SA = Sense Amplifier...... 88

Figure 4.25 Fail boundary for (a) read ‘1’ operation skewed to slow-slow corner and (b) read ‘0’ operation skewed to slow NFET, fast PFET corner ...... 88

Figure 4.26 Standby power consumption of a memory cell and sense amplifier. The power consumption for a (a) PVCR of 4 and (b) PVCR of 144 is compared. SAMP: Sense amplifier PFET, SAMN: Sense amplifier NFET...... 90

Figure 5.1 Schematic representation of Ge epitaxial layer with larger lattice constant grown on a Si substrate and the two alternate growth modes. Below the critical thickness the lattice mismatch is accomodated as compressive strain in the growth plane. Above the critical thickness, strain relaxation gives rise to misfit dislocations ...... 96

Figure 5.2 Critical thickness of SiGe epilayers grown on Si substrate. comparison of data from Matthews-Blakeslee calculation, as calculated by Jain , experimental results by Bean and Houghton ...... 98

Figure 5.3 (a) Conduction band constant energy surfaces for silicon showing the Δ6 degenerate valleys and preferential filling of the Δ2 valley for a biaxial tensile stress (b) Energy bandgap difference Eg(SiGe) - Eg(Si) showing bandgap reduction in strained SiGe compared to unstrained SiGe and schematic illustration of the effect of (c) compressive and (d) tensile biaxial stress on Si energy bands ...... 100

Figure 5.4 Effect of strain and alloying on the valence band (a) unstrained Si (b) compressively strained Si (c) unstrained Si0.6Ge0.4 (d) compressively strained Si0.6Ge0.4 ...... 101

Figure 5.5 Schematic of the valence band structure for (a) unstrained direct-bandgap semiconductor (b) under biaxial tension (c) under biaxial compression...... 102

Figure 5.6 Band alignment for (a) strained SiGe on Si substrate and (b) strained Si on SiGe substrate ...... 103

Figure 5.7 (a) conduction and (b) valence band offsets for strained SiGe on relaxed SiGe and (c) conduction and (d) valence band offsets for strained Si on relaxed SiGe ...... 104

Figure 5.8 (a) Basic processes in vapor-phase growth (b) formation of a cluster ...... 106

Figure 5.9 Schematic of (a) SiGe MBE system and (b) Si electron-beam gun QMS: qaudropole mass spectrometer for monitoring flux, RGA: residual gas analyzer, RHEED: reglection high-energy electron diffraction...... 107

Figure 5.10 Si1-xGex film morphology vs growth temperature ...... 108

Figure 5.11 Schematic of steps involved in a CVD growth ...... 109

Figure 5.12 Schematic of a horizontal cold-wall CVD reactor ...... 110

Figure 5.13 Process adjustments for correcting thickness variations in (a) front half and (b) back half of horizontal reactor ...... 111

Figure 5.14 Potential energy for a 1014 cm-2 boron δ-doping ...... 113

Figure 5.15 (a) SIMS profile showing segregation at various growth temperatures of 1 ML Sb on Si(100) surface (b) segregation ratio in the dilute concentration regime as a function of growth temperature ...... 118

Figure 5.16 (a) SIMS profile for P δ-doping at various growth temperatures showing segregation suppression at low temperature and (b) corresponding segregation ratio's 119

Figure 5.17 SIMS profile and dose deposited for various growth temperatures of (a) Phosphorus and (b) Arsenic vapor phase doping using APCVD ...... 120

Figure 5.18 SIMS profile for vapor phase doping of boron for formation of ultra shallow junctions. Sub-melt laser annealing is used for electrical activation. Drive in after anneal at (a) 1300oC and (b) 1220oC are shown ...... 121

Figure 6.1 (a) Basic structure of a Si/SiGe resonant interband tunnel diode with a (x+y) nm tunneling barrier and (b) the calculated band diagram for a 6 nm tunneling barrier 124

Figure 6.2 Operating principle of a Si/SiGe RITD ...... 125

Figure 6.3 SIMS profile for samples A through D with boron flow of (a) 6 × baseline (b) 4 × baseline (c) 2 × baseline and (d) baseline flow (e) comparison of boron SIMS profile for the 4 samples ...... 128

Figure 6.4 Measured I-V characteristics for samples A through D. The average peak current and PVCR are: (a) 500 A/cm2, 1.38; (b) 175 A/cm2, 2.24; (c) 70 A/cm2, 2.7; and (d) 15 A/cm2, 1.3, respectively. The maximum PVCR of 2.95 is obtained for sample C. The multiple lines in each graph correspond to measurements from various representative diodes in each sample. All measurements presented were performed on 18 µm mesa diameter diodes ...... 130

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Figure 6.5 (a) Device structure (b) boron and phosphorus doping (c) band diagram and (d) net electron and hole concentration obtained from device simulation of the Si/SiGe RITD structure using the ATLAS device simulator ...... 132

Figure 6.6 Representative measured I-V for samples A through D along with simulated I- V with and without inclusion of trap-assisted tunneling showing reduction in peak current and defect density as the boron δ-doping is reduced. The resultant simulated PVCR initially increases and then decreases with values of (a) 2.05 (b) 6.2 (c) 7.5 and (d) 3.85 ...... 135

Figure 6.7 (a) Variation in valley current with location of traps within the SiGe bandgap, illustrating that midgap traps result in maximum valley current. simulator (b) Variation of electric field within the tunneling barrier region for samples A through D. The electric field increases while the effective tunneling distance reduces due to the broadened boron δ-doping profile as boron doping is increased...... 136

Figure 6.8 Device structure for study of arsenic doping instead of phosphorus doping 137

Figure 6.9 Comparison of results for arsenic and phosphorus n-doping with (a) 4 × baseline and (b) 2 × baseline flowrate for the boron δ-doping region ...... 138

Figure 6.10 Schematic diagram of the RITD structures grown for tunneling barrier thickness study. The barrier thickness is (x+y) nm where x = 1, y = 1 (sample A), x = 1, y = 3 (sample B), x = 2, y = 4 (sample C), and x = 4, y = 4 (sample D)...... 139

Figure 6.11 Room temperature measured current-voltage characteristics for a (a) 2 nm (Si = 1 nm, SiGe = 1 nm), (b) 4 nm (Si = 1nm, SiGe = 3 nm), (c) 6 nm (Si = 2 nm, SiGe = 4 nm), and (d) 8 nm (Si = 4 nm, SiGe = 4 nm) tunneling barrier thickness. The average peak current densities and PVCR are (a) 280 A/cm2, 3; (b) 110 A/cm2, 4.1; (c) 20 A/cm2, 5.2, (d) 0.11 A/cm2, 4.2 respectively ...... 140

Figure 6.12 (a) Current density versus spacer thickness obtained experimentally( ) superimposed with an exponential fitting curve, (b) maximum PVCR variation with tunneling barrier thickness ...... 141

Figure 6.13 Schematic of the device structure used to study effect of n-cap doping density on the peak current density of CVD grown RITDs ...... 143

Figure 6.14 Variation in current-voltage characteristics of four samples with different n cap doping close to the n δ-doping region...... 144

Figure 6.15 Across the wafer performance for (a) 2× baseline (b) baseline flowrate from boron flow rate optimization and (c) 6 nm barrier wafer from wafer thickness study ... 146

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Figure 7.1 Frequency dependence of real and imaginary parts of the dielectric permittivity...... 149

Figure 7.2 Molecular orbital energy level diagram for group IV transition metal in an octahedral bonding with six oxygen neighbors ...... 150

Figure 7.3 Dielectric constant variation with bandgap ...... 151

Figure 7.4 Energy level diagram showing electron affinities of various defects in monoclinic HfO2 ...... 154

Figure 7.5 Metal-oxide-semiconductor structure...... 157

Figure 7.6 Energy band diagram for MOS capacitor formed using a p-type and n-type semiconductor in (a) accumulation (b) depletion and (c) inversion ...... 158

Figure 7.7 (a) Equivalent circuit of an ideal MOS capacitor (b) C-V plot for low and igh frequencies and (c) non-ideal equivalent circuit for MOS capacitor ...... 159

Figure 7.8 Equivalent circuit for (a) measured admittance (b) calculation of series resistance (c) calculation of interface states...... 161

Figure 7.9 Equivalent circuit for (a) single interface trap level (b) distribution of interface traps (c) conductance as a function of gate bias showing the peak in conductance and its relation to the interface state density for a single interface trap level...... 163

Figure 7.10 Electrochemical setup used for GaAs anodic oxidation ...... 167

Figure 7.11 Semiconductor-electrolyte interface under various bias conditions...... 169

Figure 7.12 Cyclic voltammetry curves for (a) 0.2M citric acid buffered with NH4OH (b) buffered citric acid with 0.01M Ga2(SO4)3 and (c) buffered citric acid with 0.05M Ga2(SO4)3 showing no oxide formation in (c)...... 170

Figure 7.13 Cyclic voltammetry curves for (a) p-GaAs and (b) n-GaAs ...... 171

Figure 7.14Pourbaix diagram for (a) gallium and (b) arsenic showing pH and potential for stable oxide formation...... 172

Figure 7.15 Chronopotentiometry curves with various current densities to obtain different oxide thicknesses...... 172

Figure 7.16 Photographs of GaAs wafers aftera anodic oxidation. The oxide layer is the central 1" diameter region which was in contact with the cell. No color gradient is observed by visual inspection ...... 174

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Figure 7.17 (a) C-V plots measured at room temperature and 100oC (b) conductance as a functon of gate bias and energy level in bandgap (c) interface state density for anodic oxide of p-GaAs formed using buffered citric acid solution with thickness of 34 nm ... 176

Figure 7.18 (a) C-V plots measured at room temperature and 100oC (b) conductance as a functon of gate bias and energy level in bandgap (c) interface state density for anodic oxide of p-GaAs formed using buffered citric acid solution with Ga2(SO4)3 and thickness of 47 nm ...... 177

Figure 7.19 (a) C-V plots measured at room temperature and 100oC (b) conductance as a functon of gate bias and energy level in bandgap (c) interface state density for anodic oxide of p-GaAs formed using buffered citric acid solution with thickness of 11 nm ... 178

Figure 7.20 (a) C-V plots measured at room temperature and 100oC (b) conductance as a functon of gate bias and energy level in bandgap (c) interface state density for anodic oxide of p-GaAs formed using buffered citric acid solution with Ga2(SO4)3 and thickness of 10 nm ...... 179

Figure 7.21 (a) C-V plots measured at room temperature and 100oC (b) conductance as a functon of gate bias and energy level in bandgap (c) interface state density for anodic oxide of p-GaAs formed using buffered citric acid solution with Ga2(SO4)3 and thickness of 120 nm ...... 180

Figure 7.22 C-V plots measured at room temperature for n-GaAs using (a) buffered citric acid (b) buffered citric acid solution with Ga2(SO4)3 with thickness of 11 nm, showing Fermi level pinning in both cases...... 181

Figure 7.23 Leakage current and breakdown characteristics for p-GaAs wafers with anodic oxide grown in citric acid solution with Ga2(SO4)3 with oxide thickness of (a) 120 nm (b) 47 nm (c) 34 nm (d) 10 nm ...... 181

Figure 7.24 Hysteresis curves (a) without and (b) with Ga2(SO4)3 showing reduced hysteresis for oxides grown in Ga2(SO4)3 ...... 182

Figure 7.25 Schematic of one ALD reaction cycle ...... 183

Figure 7.26 A field effect transistor protein biosensor is presented. When a target protein binds to the receptor, it induces charges in the substrate (electrons as pictured here), causing a change in the current flow between the source and drain...... 185

Figure 7.27 (a) Debye length limitation for biosensing using an FET and (b) reduction in sensor output with increased physiological buffer solution (PBS) concentration ...... 187

Figure 7.28 Various methods to overcome the Debye length challenge in protein sensing using FETs ...... 188

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Figure 7.29 Drift in current of Si MOSFET with time when exposed to PBS solution . 189

Figure 7.30 Capacitance-voltage plots of MOS capacitor with Al2O3 as gate dielectric, heat treated at various temperatures with different ambients, including O2, N2 and forming gas anneals (FGA) showing (a) hysteresis, (b) multifrequency C-V of Al2O3, (c) multifrequency C-V for SiO2 as gate dielectric, and (d) comparison of C-V characteristics of 100 nm SiO2 and Al2O3 with varying thicknesses...... 191

Figure 7.31 (a) Triangular voltage ramp technique for detecting alkali ions (A+), and (b) illustration of the peak obtained with low frequency C-V measurements due to mobile ions and calculation of ion concentration...... 195

Figure 7.32 (a) Triangular voltage sweep measurements of a typical thermal SiO 2 MOS capacitor at 250oC, and (b) relationship between increases in alkali ions concentration with increasing soak times in PBS for the control SiO2 based capacitor. The line is joins of the measured data...... 196

Figure 7.33 Triangular voltage sweep measurements of MOS capacitors with Al2O3 dielectric at 250oC for (a) 100 nm, (b) 50 nm, (c) 25 nm, and (d) 10 nm oxide thicknesses. Note the absence of any time varying mobile ion peak superimposed on the baseline C-V waveform that instead shows a natural progression of depletion and inversion in the channel ...... 197

Figure 8.1(a) Increase in leakage current with voltage scaling for an MOS transistor due to the lower limit on sub-threshold slope (b) comparison of various candidate technologies to improve MOSFET performance ...... 199

Figure 8.2 (a) Basic structure of a tunneling field effect transistor and (b) simulated band diagram for a Si TFET with 100 nm channel length and p+ doping of 1×1020 cm-3, n+ doping of 5×1017 cm-3. The applied gate and drain bias is 1V...... 200

Figure 8.3 Structure for MBE grown p-TFETS (a) Sample M1 is an all Si TFET incorporating a n δ-doping region with a 300 nm channel (b) Sample M2 comprises of a 30 nm Si0.9Ge0.1 channel also with an n δ-doping region ...... 203

Figure 8.4 Band diagram for (a) sample M1 with all Si channel and (b) sample M2 with Si0.9Ge0.1 channel...... 203

Figure 8.5 Simulation results for (a) drain current-drain voltage and (b) drain current-gate voltage characteristics of all Si channel p-TFET (sample M1) ...... 204

Figure 8.6Simulation results for (a) drain current-drain voltage and (b) drain current-gate voltage characteristics of Si0.9Ge0.1 channel p-TFET (sample M2) ...... 205

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Figure 8.7 Structure for CVD grown TFETs (a) Sample CM is an n-TFET incorporating a p δ-doping region with a 100 nm Si/SiGe channel (b) Sample CP is a p-TFET incorporating a n δ-doping region with a 100 nm Si/SiGe channel ...... 206

Figure 8.8 Band diagram for (a) Sample CM, n-TFET incorporating a p δ-doping region with a 100 nm Si/SiGe channel (b) Sample CP, p-TFET incorporating a n δ-doping region with a 100 nm Si/SiGe channel ...... 206

Figure 8.9 n-TFET broken gap heterostructures investigated with (a) GaSb/InGaAs tunneling junction (b) AlSb included in GaSb to create a quasi-bound state ...... 207

Figure 8.10 Band diagram for n-TFET Broken gap heterostructures investigated with (a) GaSb/InGaAs tunneling junction (b) AlSb included in GaSb to create quasi-bound state ...... 207

Figure 8.11 p-TFET broken gap heterostructure with AlGaSb/InAs as tunneling junction (a) device structure schematic and (b) simulated banddiagram ...... 208

Figure 8.12 (a) schematic of fabriacted TFET and (b) photomicrograph showing final device ...... 210

Figure 8.13 (a) Wet etching effect on highly doped silicon surface (b) dry versus wet etching effect on tunnel diode performance...... 211

Figure 8.14 Effect of various GaSb etch chemistries (a) HCl/H2O2/H2O stripping the photoresist (b) H3PO4/H2O2/H2O resulting in Sb2O3 formation (c) oxide formed with addition of tartratic acid (d) dry etching using BCl3/Ar ...... 212

Figure 8.15 Oxide characterization of 100 nm Al2O3 deposited by ALD (a) multi- frequency C-V characteristics showing no frequency dispersion (b) multi-frequency G-V plots (c) interface state density calculated using conductance technique ...... 213

Figure 8.16 (a) C-V characteristics for various HfO2 runs showing the reduction in Cox with RTA anneal (b) multi-frequency C-V curves showing reduction in frequency o dispersion with 1 min RTA anneal at 450 C in N2 ...... 214

o Figure 8.17 (a) Effect of post metal anneal at 400 C for 1 min in N2 and (b) effect of post oxide deposition anneal on Al2O3/HfO2 gate stack with TiN/Al gate metal ...... 215

Figure 8.18 Oxide characterization of Al2O3/HfO2 gate dielectric stack with 5/5.5 nm thickness deposited by ALD (a) multi-frequency C-V characteristics showing no frequency dispersion (b) multi-frequency G-V plots (c) interface state density calculated using conductance technique ...... 216

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Figure 8.19 Experimental drain current-drain voltage (ID-VD) characteristics for MBE grown p-TFET devices with (a) 300 nm Si only channel and (b) 30 nm Si0.9Ge0.1 channel ...... 217

Figure 8.20 Experimental drain current-gate voltage (ID-VG) characteristics for MBE grown p-TFET devices with (a) 300 nm Si only channel and (b) 30 nm Si0.9Ge0.1 channel ...... 218

Figure 8.21Comparison of reverse leakage current for the two MBE grown p-TFET structures. Inset showing forward and reverse I-V characteristics for 300 nm channel device ...... 218

Figure 8.22 (a) Drain current-drain voltage and (b) drain current-gate voltage characteristics for CVD grown p-TFET with a composite Si0.6Ge0.4/Si channel...... 219

Figure 8.23 p-i-n diode leakage current characteristics for 100nm Si0.6Ge0.4/Si channel, CVD grown (a) pTFET and (b) n-TFET structures ...... 220

Figure 8.24 (a) Drain current-drain voltage and (b) drain current-gate voltage characteristics for CVD grown n-TFET with a composite Si0.6Ge0.4/Si channel showing gate modulation only with negative gate bias ...... 220

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CHAPTER 1 INTRODUCTION

1.1 Motivation

For more than four decades the semiconductor industry has seen an extremely rapid development, a feat unparalleled by any other industry. The primary reason has been the ability to exponentially decrease the size of the transistors, the key building block used to fabricate integrated circuits. This has led to rapid performance improvements in terms of speed, power and area. Remarkably, the improvement in performance has come with a reduction in cost, resulting in a proliferation of consumer electronics. This scaling trend, also expressed in terms of Moore's law (i.e. the doubling of the number of components per chip every 2 years) was largely possible due to ease of scalability of the silicon MOSFET (metal oxide semiconductor field effect transistor). In fact the basic device structure did not undergo significant modification since its introduction until the replacement of silicon oxide by high dielectric constant materials as the gate oxide in Intel's 45 nm technology node in 2008. This change also signaled the need for constant device innovation going forward, if this pace of progress needs to be maintained. The emphasis of the industry until a few years back had primarily been on improvement of speed, resulting in a rapid increase in processor frequency from 16 MHz in the 80386 system in 1985 to 1.5 GHz in the Pentium 4 processors introduced in 2000.

Unfortunately, with the scaling of transistors to sub 50 nm sizes, the power consumption has rapidly increased due to increase in leakage currents. Further, with the change from 1 desktop computing to mobile computing, the focus of the industry has shifted to low power design. Increase in clock speeds also contributes to an increase in the dynamic power dissipation. With the emphasis on low power, the processor clock speeds have not seen a significant increase in the last 5 years, in order to keep the total power consumption under control. Hence, it is prudent to search for new device and circuit architectures geared towards low power, high speed operation and accelerate working on them if the progress of the industry needs to be maintained. As Intel CEO Paul Otellini states [1] "Our business model is one of very high risk: We dig a very big hole in the ground, spend three billion dollars to build a factory in it, which takes three years, to produce technology we haven't invented yet, to run products we haven't designed yet, for markets which don't exist. We do that two or three times a year. Everything we do has an inherent belief in technology".

1.2 Objective

In this dissertation, two approaches that could serve as a replacement to the current complementary MOS (CMOS) technology have been investigated.

Tunnel diodes, invented in 1958 by Leo Esaki, and for which he shared the Nobel prize in 1973 with Ivar Giaever and Brian D. Josephson, showed a lot of promise in the

1960's and 1970's. This was due to its negative differential resistance characteristic which was very useful for the use in oscillators, amplifiers and detectors [2]. However, with the rise of the MOSFET and its integration and scalability advantages all other devices were relegated to niche markets. Work was done to develop logic and memory circuits using tunnel diodes during the 1990's and early 2000's [3], [4]. These involved the use of tunnel

2 diodes in conjunction with MOSFETs with novel circuit architectures. However, the absence of a silicon-based tunnel diode capable of large scale integration using the standard CMOS process line led to a decline in interest. Si/SiGe resonant interband tunnel diodes (RITD) were first reported in 1998 [5] and several modifications in the growth parameters resulted in steady performance improvements. However, these were developed using molecular beam epitaxy, a growth technique not suited for large scale manufacture. In our work, Si/SiGe RITDs are implemented on 200 mm wafers using chemical vapor deposition (CVD) with an ASM Epsilon 2000 reactor, which is widely used in large scale manufacture. Various growth optimizations were conducted to improve device performance.

Since tunnel diode based circuits do not follow the conventional MOS architecture, it is essential to assess the performance benefits and shortcomings in comparison with current state-of-the-art technology, which can serve as a guide to device designers for performance requirements. Very large scale integration (VLSI) design heavily depends on the use of automation tools for circuit design. In our work tunnel diodes have been integrated into a standard electronic design automation tool, Cadence, to allow detailed simulations using tunnel diode circuits. A memory array is then designed and its performance compared to SRAM and embedded DRAM memory technologies currently in use by the industry.

Another device gaining a lot of attention in recent years has been the tunneling field effect transistor (TFET). This is a modification to the conventional MOSFET which reduces the leakage current due to drain induced barrier lowering (DIBL), a huge concern

3 in MOS transistors today. Although the off-current characteristics of these devices are very good, they have poor ON-currents due to low tunneling probabilities. This problem has been addressed here by applying the techniques used in improving tunneling currents in RITDs to TFETs.

1.3 Overview of the dissertation

Chapter 2 covers the theory of quantum mechanical tunneling and a historical review of the tunnel diode topologies developed using this phenomenon, utilizing different material systems.

Chapter 3 provides a summary of the various logic and memory circuit architectures proposed in literature including designs for moving beyond conventional boolean logic, towards multivalue and threshold logic, and the possibility of reconfigurable circuits.

In Chapter 4, a 32 × 32 bit tunneling static random access memory (TSRAM) array is simulated using a 90 nm process technology. The speed, power and robustness to process variations is evaluated.

The Si/SiGe material system is key in the development of Si/SiGe RITDs. This material system is discussed in Chapter 5. The two epitaxial growth techniques used in this work, namely molecular beam epitaxy and chemical vapor deposition, are also introduced. Another key component of RITDs is the use of δ-doping. Realization of δ- doping using both these growth techniques is also discussed.

Chapter 6 addresses development of Si/SiGe RITDs using chemical vapor deposition. Various techniques used to improve device performance are discussed and results provided.

A major change in the semiconductor industry has been the introduction of high dielectric constant (κ) materials as gate oxide in transistors. The key to the success of the silicon material system has been the excellent interface between Si and its native oxide

(SiO2). With continual scaling, the thickness of SiO2 reached 1 nm which led to large gate leakage currents due to tunneling. However, finding a replacement for SiO2 has been extremely challenging. Chapter 7 discusses issues with high- κ dielectrics which are also central to this dissertation for the development of TFETs. Replacement of channel material is also being investigated for improved mobility and III-V semiconductors are key candidates. However, III-V passivation has been a 40 year old problem due to the poor III-V native oxide. Anodic oxidation technique is explored to control the stoichiometry of the native oxide, to improve interface quality. High- κ dielectrics can then be deposited on top to form a gate stack similar to silicon. Finally another interesting use of high- κ dielectrics in biosensors is investigated.

Chapter 8 discusses the development of vertical tunneling field effect transistors and the various process optimizations required to develop these devices.

Finally, Chapter 9 summarizes the work of this dissertation and discusses future work on the various topics studied.

CHAPTER 2 QUANTUM MECHANICAL TUNNELING - PHYSICS AND

DEVICES

Quantum mechanical tunneling is a phenomenon on the microscope scale wherein a particle can penetrate a potential barrier higher than its kinetic energy. It has no classical mechanics equivalent. Classically, if a particle is incident on a potential barrier it is transmitted only when it has higher energy than the barrier height. However, quantum mechanically, if the barrier is thin enough and has a finite height, the electron wave can penetrate through the barrier and emerge on the other side. This is a result of the wave nature of particles analogous to the evanescent waves observed in electromagnetic radiation. The tunneling phenomenon can be observed in semiconductor devices, where the potential barrier is created either by a difference in band alignment of semiconductors with different bandgaps or by abrupt doping variations as in a p-n junction structure. Semiconductor tunneling devices are broadly classified into intraband and interband tunneling devices. Intraband tunneling involves tunneling within the same electronic band i.e. from conduction to conduction band or valence to valence band.

These are unipolar and involve only one type of carrier i.e. either electrons or holes. In the case of interband tunneling, carriers tunnel from the conduction to the valence band or vice versa and hence, these are bipolar devices. In this chapter, the theory of both types

6 of devices will be developed here and a historical review of tunnel diodes will be presented.

2.1 Rectangular Barrier - Intraband Tunneling

The simplest barrier to analyze is a rectangular potential Epot(x), with barrier height E0, larger than the electron total energy E as illustrated in Fig. 2.1. The potential exists in the finite interval 0 < x < a and is zero outside. In the region external to the potential i.e. x < 0 and x > a, the electron is free. For practical tunneling devices implemented using semiconductor heterostructures, the effective mass of electrons may not be equal in the regions inside and outside the barrier. This is taken into consideration by assuming an electron effective mass of m1 outside the barrier and m2 inside the barrier.

Potential Energy

Incident E0 E Transmitted

Reflected

el a x 0

Figure 2.1 Rectangular tunneling barrier showing incident, reflected and transmitted wavefunctions

To calculate the tunneling probability, the wavefunction Ψ is determined using the general time-independent Schrödinger equation:

(2.1)

Reducing to a one-dimensional problem,

(2.2)

where, (2.3)

In the region outside the barrier i.e. for x < 0 and x > a, = 0 and k reduces to

The general solution of the Schrödinger's equation is given by:

(2.4)

Where, A, B, C, D are constants.

Inside the barrier, . Since E < E0, k is imaginary. The Schrödinger's

equation is now written as

where, (2.5)

and the general solution is given by , where F and G are constants.

Now, and should be continuous at x = 0 and x = a. At x = 0,

and (2.6)

(2.7)

(2.8)

While at x = a,

(2.9)

(2.10)

(2.11)

Combining equations (2.8) and (2.11)

(2.12)

where, and

Assuming incidence only at the left side of the barrier, D = 0

(2.13)

(2.14)

(2.15)

(2.16)

and the reflection (R) and transmission (T) coefficients are given by:

For m1 = m2 this reduces to: (2.17)

For m1 = m2 this reduces to: (2.18)

5 5

4 4

3 3

2 2 In Ga As AlAs In Ga As 0.53 0.47 0.53 0.47

1 PotentialEnergy (eV) Electron Energy(eV) 1

0 0 2 4 6 8 10 12 0.01 0.1 1 Barrier Thickness (nm) Transmission Probability (a) (b)

Figure 2.2 shows the transmission coefficient, T for a single potential barrier formed using an In0.53Ga0.43As/AlAs heterostructure. In contradiction to classical prediction, for E > E0 the transmission coefficient is not always 1 but is oscillatory and equal to one only for i.e. when the thickness of the barrier is a half-integral or integral number of the de-Broglie wavelength in the barrier region. This is due to destructive interference between reflections at x = 0 and x = a. As E >> E0, T asymptotically tends to unity.

A more complex but practical scenario is when the momentum on the two sides of the barrier is not constant. If the wave vector on the left and right side of the barrier are and respectively, then the transmission coefficient is given by [6]:

(2.19)

2.2 Double Rectangular Barrier - Resonant Intraband Tunneling

Incident Transmitted electrons A F A' F' electrons Reflected electrons B G B' G' x a a+b 2a+b Figure 2.3 Double barrier structure showing amplitudes of forward and backward wave functions in each region

Connecting two barrier separated by a quantum well of width b (Fig. 2.3), discrete energy levels are formed in the well due to quantum confinement. When the incident wave energy coincides with the energy level in the well, resonant tunneling occurs, and the transmission through the barrier equals unity. The wave amplitude F transmitted through the left barrier can be related to the wave incident on the right barrier A' by the relation:

. Similarly,

Thus, describes the matrix for the well region. ML and MR are

matrices representing the two barrier regions and are identical to that obtained in Eq.

(2.12). The composite transmission matrix can now be written as:

(2.20)

where,

For barrier's with equal width and height, the wave vector in the regions left and right of the structure is the same as the wave vector in the quantum well. Further the wave vectors

in the barriers is also the same. Hence, and .

where from Eq. (2.16),

Hence, (2.21)

From Eq. (2.19), transmission probability,

3.0 3.0

2.5 2.5

2.0 2.0

1.5 1.5

In Ga As AlAs 0.53 0.47

1.0 1.0 Electron Energy(eV) PotentialEnergy (eV) 0.5 0.5

0.0 0.0 0 2 4 6 8 10 12 14 16 0.01 0.1 1 Distance (nm) Transmission Probability (a) (b) Figure 2.4 Transmission probability for a In0.53Ga0.47As/AlAs double barrier with barrier width of 2 nm, separated by a quantum well of 4 nm width. Barrier height is 1 eV, showing resonance energy levels. The electron effective mass used for In0.53Ga0.47As is 0.041m0 and for AlAs is 0.11m0. In contrast to the single barrier case, the transmission probability shows a sharp resonance peak below the barrier height with unity transmission probability.

Thus, off resonance, the transmission probability for a double barrier structure is lower than that of a single barrier. However, at resonance, and the transmission probability is unity. Thus, the condition for resonance is

(2.22)

In practical tunneling devices, application of voltage bias results in reduction of device symmetry and hence reduced transmission probability.

Figure 2.4 shows the transmission probability for a double barrier structure formed using an In0.53Ga0.43As/AlAs heterostructure showing the unity transmission probability. From Fig. 2.4(b) it is apparent that the transmission probability exhibits a

13 sharp resonance at the resonant energy level. This is often approximated by a Lorentzian shape. Thus, the transmission probability as a function of energy is given by [6]:

(2.23)

where, is the resonance energy level and is the full-width at half-maximum.

Self-consistent Calculation

In the previous calculations for transmission probability, the electrostatic potential due to ionized donor and acceptors and free charge carrier distribution is neglected. In practice, the charge carriers injected into the well especially during resonance modifies the potential distribution in the well. Thus, the self-consistent Hartree potential is determined using the Poisson equation and added to the Schrödinger equation. These equations need to be solved iteratively to obtain self consistent solutions for the wave function and potential [7]. The electron charge in the well screens the applied bias and shifts the resonance peak to a higher energy.

2.2.1 Resonant Tunnel Diode

A resonant tunnel diode (RTD) consists of a double rectangular potential barrier formed by an undoped quantum well between two undoped barrier layers utilizing the conduction or valence band edge discontinuity between the two materials. The double barrier is sandwiched between heavily doped emitter and collector regions serving as contacts. Figure 2.5(a) shows the zero bias conduction band diagram. The emitter and collector are 3D systems with electron density of states which are continuously distributed in energy while the 2D well consists of quantized energy states. As a voltage

14 bias is applied to the device, the electron energy in the emitter is raised with respect to the well and the collector. The applied bias is primarily dropped across the undoped double- barrier structure. When the electron energy in the emitter coincides with the quasi-bound state energy in the well (EF > En), resonant tunneling occurs through the double-barrier, resulting in a tunneling current [Fig. 2.5(b)].

Undoped E

EF En En En EC EF En EF EF EC EC EC V Emitter Collector V V

I I I I peak

V V valley V (a) (b) (c) (d) Figure 2.5 Evolution of RTD band diagram with application of voltage bias and corresponding current voltage-characteristics

Energy and lateral momentum are conserved. The electron energy in the emitter is

given by: where, and denote perpendicular to and parallel to

the direction of tunneling respectively and is the electron effective mass. A parabolic, isotropic, conduction band minima is chosen. Energy of electrons in the quasi-bound state

is denoted by: . Hence, from conservation of energy and lateral

momentum , is the condition for tunneling. This is known as coherent

tunneling since the particle maintains phase coherence across the tunneling structure.

Undoped

Figure 2.6 Use of undoped spacer regions adjacent to the tunneling barrier structure resulting in 2D-2D tunneling instead of 3D-2D, improving PVCR

As the applied bias is increased further and the conduction band on the left side,

crosses , tunneling current seizes to flow and a negative differential resistance

(NDR) region is observed. Ideally, the current should fall to zero, however a valley current is observed as a result of off-peak transmission due to phonon and impurity scattering, tunneling via impurity states in the potential barrier, interface roughness scattering. Scattering also results in broadened transmission resonance. Further increase in bias results in thermionic emission of carriers over the tunneling barrier and an increase in current. The ratio of the peak to the valley current (PVCR) is a very important figure of merit for tunneling devices. A high peak current is desirable for achieving high

16 speed operation, while the valley current contributes to power dissipation and should be as low as possible. Hence, a high PVCR is a critical design goal for tunnel diodes.

PVCR can be further improved by adding an undoped spacer region on the emitter side. The applied bias now falls across this undoped region in addition to the double barrier structure forming a triangular quantum well as shown in Fig. 2.6.

Tunneling now occurs between 2D-to-2D instead of 3D-2D states resulting in sharper resonance and larger PVCR. Introduction of spacer layers also increases the depletion width, reducing the capacitance which is beneficial for high frequency applications.

2.2.2 Coherent Tunneling Current

Current density is given by the total particle flux, . Where, is the electron charge, is the total number of carriers and is the velocity of carriers. For tunneling through a barrier, the number of carrier is proportional to the tunneling probability and the number of available electrons which depends on the density of k-

states and their Fermi occupation probability . Hence,

where, the factor 2 is due to spin degeneracy, is the normalized volume occupied by a k-state, is the tunneling probability, is the Fermi-Dirac distribution function, is the electron velocity in the tunneling direction. Now the net tunneling current is the difference between current flow from left of the barrier to right and from the right of the barrier to left.

(2.24)

From time reversal symmetry,

Hence,

(2.25)

Velocity , substituting,

Number of k-states at energy E in the two-dimensional space transverse to the tunneling direction is given by

(2.26)

Using effective mass approximation, , or , where, is the

effective mass in the hence,

(2.27)

The total energy E can be split into the longitudinal and transverse components. Hence,

(2.28)

For an applied bias of V volt,

(2.29)

which is the same as the expression derived by Esaki and Tsu [8] and is the general expression for tunneling current.

2.2.2.1 Tunneling Current for a Resonant Tunnel Diode

Some simplifications can be made for a resonant tunnel diode. The contribution from the right can be ignored for a large bias, and the Fermi function can be

approximated as a step function. Hence,

From Eq. (2.23) the Lorentzian approximation for the tunneling probability is substituted:

(2.30)

The term is slowly varying and is evaluated at En and removed from the integral and the current density reduces to:

(2.31)

where, and gives the location of the resonance peak with applied bias.

Tunneling occurs for EC < En < EFL.

2.2.3 Practical Implementation of Resonant Tunnel Diodes

Resonant tunnel diodes (RTDs) are most commonly implemented using the III-V material system due to the large selection of binary, tertiary, and ternary compounds which can be combined to form a variety of heterostructures with varying conduction band offsets. Early RTDs were developed in the AlGaAs/GaAs material system [9], [10].

[11]. High peak current densities (Jp) were obtained with the use of AlGaAs as barrier, however the PVCR was reduced due to thermionic emission over the barrier and thermal- assisted tunneling through higher subbands. Use of AlAs as barrier could reduce this but also deteriorated the peak current. High PVCRs of 3.9 were obtained using undoped spacer regions [11]. A switch to InGaAs/InAlAs material system significantly improved 19

PVCRs and Jp with improved barrier height and increased subband separation [12], [13].

2 Use of In0.53Ga0.47As/AlAs system led to PVCRs of 24 and Jp of 15 kA/cm [14].

Reducing the barrier thickness from 2.4 nm to 1 nm resulted in the Jp boosted to 450

2 kA/cm [15]. Addition of strained InAs, sandwiched between In0.53Ga0.74As in the

2 quantum well, greatly increased the PVCR to as high as 50 with Jp of 5.8 kA/cm [16].

Higher current densities were obtained for the InAs/AlSb system, which also benefitted

2 from the lower contact resistance of InAs, with Jp of 490 kA/cm and PVCR of 2.2 [17].

Si-based RTDs did not meet with a lot of success due to the lack of lattice- matched heterostructure materials. The Si/SiGe system, with strained SiGe grown on Si substrates, allowed formation of heterostructures but were limited due to the very small conduction band offset. Almost all the bandgap difference is accommodated in the valence band resulting in a hole RTD. RTDs grown using both molecular beam epitaxy and chemical vapor deposition exhibited negative differential characteristics only when cooled down to 77K and no room temperature results were obtained [18], [19], [20].

Conduction band offset of ~ 150 meV can be obtained by growing a strained Si/relaxed

Si1-xGex structure on a relaxed Si1-yGey substrate [21]. Room temperature PVCRs up to

1.2 were obtained [22], [23].

2.3 Arbitrary Potential Variation - WKB Approximation

For more complex barrier variations, where the potential is a function of the position, computation of Schrödinger equation is complicated and several approximation techniques have been developed. The WKB (Wentzel-Kramers-Brillouin) approximation is a popular technique to find solutions to the Schrödinger equation provided the potential

20 is slowly varying spatially. Here 'slowly-varying' implies that Epot(x) changes slightly over the de-Broglie wavelength (λ=h/p) length scale, or the potential change is so slow that the momentum is constant over several wavelengths.

E Epot(x) Classical turning point Incident Transmitted wave wave Decaying wave x x1 x2 Figure 2.7 Slowly varying potential used in WKB approximation

Considering an arbitrary potential variation, for an incident electron with energy

E, the classical turning point is defined at E = Epot, where the electron enters and exits the potential barrier [Fig. 2.7]. For E > Epot(x) the wave function is propagating while for E <

Epot(x) the wave function changes to decaying. Since the variation in potential is assumed to be slow, the general form of wave function obtained for a constant potential can be applied and is given by:

(2.32)

Substituting into Schrödinger equation:

(2.33)

(2.34)

21 where, is the local wavenumber. Since the potential and the wave number are assumed to vary slowly, can be assumed to be very small. Hence,

(2.35) or

Now, and using Eq. (2.35),

Using binomial expansion,

Integrating,

Hence, (2.36)

Now the wavefunction of the particle incident at x = x1 is given by:

and the decaying wavefunction inside the barrier can be

written as .

At x = x2 and the probability density at the right hand

side of the barrier (2.37)

Thus transmission probability

Hence, (2.38)

A similar expression is obtained using the rectangular barrier for low tunneling probabilities. From Eq. (2.18) , the tunneling probability for a constant potential barrier

. For low tunneling probability, . Hence,

and (2.39)

The pre-factor in Eq. (2.39) is of the order of unity and the exponential term is dominating. Hence the equation reduces to

2.4 Interband Tunneling

Tunneling is also observed in a pn junction when the p and n side are degenerately doped. This was discovered by Leo Esaki in 1958 [24] and was the first observation of quantum tunneling. The high doping results in the Fermi level being located inside the conduction and valence band on the n and p side respectively. The depletion layer width is on the order of 10 nm allowing direct tunneling from the conduction band on the n-side to the valence band on the p-side. Since the potential barrier in this case is a function of position WKB approximation is generally applied to determine the tunneling probability and current through the device.

2.4.1 Esaki Diode

Figure 2.8 shows the band diagram for an Esaki diode. When a forward bias is applied, electrons tunnel from the occupied states in the conduction band to the empty states in the valence band. As the forward bias is increased, the tunneling current increases until the peak of electron and hole profiles line up. This is the peak voltage. As

23 the forward bias is further increased, the current starts reducing, producing a negative differential resistance region. With further increase in bias, the conduction band electrons on the n side now see the bandgap and the tunneling current should ideally reduce to zero. However, defect energy levels exist within the bandgap, which acts as the barrier, resulting in trap-assisted tunneling current. This is known as excess current and is responsible for the reduced PVCRs in tunnel diodes. As the forward bias is increased further, thermal diffusion over the barrier is now possible, and the diode behaves like a pn junction diode. In the reverse bias region, the depletion widths are further reduced resulting in a zener tunneling current.

E EFn EFn p(E) ECn EFn EVp EVp EVp EVp ECn EF EFp ECn EFp EFp EFp

n(E) E

ECn

I I I I

V V V V

Figure 2.8 Evolution of Esaki diode band diagram with application of voltage bias and corresponding current voltage-characteristics

2.4.2 Band-to-Band Tunneling Current - Non-Local Model

The general tunneling current equation derived in Eq. 2.27 can be used to determine the interband tunneling current.

Since the tunneling is from conduction to valence band, the two band model is used to determine the imaginary wave vector in the semiconductor bandgap. This ensures the energy dispersion relation to be electron like near the conduction band and hole like near the valence band.

where, and

Now, from WKB approximation,

(2.40)

where the integration limits for the transverse energy is from 0 to where, is the smaller of and and the integration limits for the longitudinal energy is now the overlap region between the valence and conduction bands. is replaced by

from the two band model. The Fermi levels used here are the quasi-Fermi levels of the majority carriers on the left and right side of the barrier.

Hence,

(2.38)

2.4.3 Band-to-Band Tunneling Current - Local Approximation

A simpler expression can be obtained by assuming the electric field to be constant in the depletion region. This is the local approximation. From Fig. 2.9, it can be deduced that the potential energy, is linearly varying and is given by . Thus, the tunneling barrier can now be approximated to be a triangular barrier.

Now, at is the bandgap of the semiconductor, .

Or, or,

The WKB approximation for tunneling probability in this case can be written as:

Hence , (2.41)

In evaluating this expression, it is assumed that all the kinetic energy of the electron is in the direction of tunneling. In reality, as discussed for resonant tunneling, the energy can be divided into the longitudinal and transverse components corresponding to the energy in the direction and perpendicular to the direction of tunneling. The tunneling probability equation is now modified to [25]:

(2.42)

26 and results in a reduction in transmission probability. Here the parabolic 1-band relation is used instead of the two-band model [26].

Potential Energy

E 0

Figure 2.9 Triangular barrier approximation for tunneling through the depletion region of a deg enerately doped p-n junction

Using this approximation for the tunneling probability in the non-local tunneling current equation,

the equation reduces to [25]

(2.43)

where, and is called the

overlap integral and and an average electric field

Most simulators implement local band-to-band tunneling models by incorporating them in the continuity equations as a generation/recombination term [27]. The generation rate is given by .

2.4.4 Excess Current

Figure 2.10 Various routes for tunneling through the forbidden bandgap using impurity levels [31]

As the forward bias applied on a tunnel diode is increased, such that the electrons in the degenerate level on the n side are raised above the degenerate levels on the p-side, ideally the current should drop to zero. However, a substantial current is observed experimentally. This was termed as excess current by Yajima and Esaki [28] since the current is in excess of the diffusion current expected from a pn junction. It was found that addition of defects by adding deep level dopants [29] or neutron bombardment [30] could alter these currents. Chynoweth et al. [31] proposed that the current is due to tunneling through localized states within the bandgap. A possible origin of these levels was a large

28 number of donor-acceptor pair formation with the high doping densities giving rise to electrically neutral impurities. A range in donor-acceptor separations could result in a distribution of energy levels through the bandgap. Figure 2.10 shows the various routes for an electron to tunnel from the conduction band on the n side to the valence band on the p side via an impurity level in the bandgap. Considering the route CBV, the tunneling probability from B to V can be given by an equation similar to Eq. (2.41)

(2.42)

where is the energy gap through which the electron has to tunnel and is given by:

and , are the potential difference between the Fermi level and the valence and conduction band respectively.

A closed form expression for the total tunneling current, more suitable for use in circuit simulators, is given by [25]:

(2.44)

which is the sum of the tunneling current, excess current and diffusion current components.

Here, , , are the peak current, valley current, peak voltage and valley voltage respectively, is the saturation current density for a diode and is the exponent prefactor and is a fitting parameter to experimental data.

2.4.5 Resonant Interband Tunnel Diodes

(b)

(a)

Figure 2.11 Various resonant interband tunnel diode designs proposed by Sweeny and Xu [32]

(c)

Sweeny and Xu [32] proposed the design of a hybrid between a resonant tunnel diode and an Esaki diode known as the resonant interband tunnel diode (RITDs).

Resonant tunnel diodes suffered from poor PVCRs due to various scattering mechanisms such as polar scattering, interface roughness scattering and alloy scattering [33] that lead to a broadening of the transmission peak and increased excess currents. Excess currents in interband tunneling are considerably lower since it involves tunneling through the forbidden energy gap. However, they suffer from low operating frequencies. RITDs could potentially have the advantage of both structures. Some of the highest PVCRs are reported using this structure and hence is also the focus of this dissertation. Three designs were proposed and are illustrated in Fig. 2.11. Instead of a double-barrier structure with 30 unipolar transport, a double-well structure with bipolar transport is advocated (Fig.

2.11(a)). Here electrons from an n-type two-dimensional quantum well (region II) resonantly tunnel through the barrier to a p-type quantum well (region III). Region I and

IV serve as the contacts and are heavily doped n and p regions respectively. However they need not be degenerately doped. The quantum wells allow a 2D electron/hole gas formation without the need for degenerate doping. This reduces the capacitance, allowing higher operating frequencies. Figure 2.11(b) utilizes the InAs/AlSb/GaSb material system which are lattice matched with a lattice constant of 6.1Å. InAs/GaSb has a unique band alignment known as the 'broken gap' lineup [34] with the conduction band of InAs below the valence band of GaSb. AlSb acts as a tunnel barrier. The p and n quantum wells can also be realized using δ-doping [Fig. 2.11(c)].

2.4.6 Practical Implementation of Interband Tunneling Devices

Early Esaki diodes were implemented using the alloying technique and were realized using a number of materials, Si [35], Ge [24], GaAs [36], InSb [37]. However, this fabrication technique is not compatible with the integrated circuit technology. Cohen et al. [38] reported In0.53Ga0.47As Esaki diodes using metal organic molecular beam epitaxy. They fabricated an n-p-n structure with two back to back tunnel diodes to reduce the contact resistance. High peak current densities of 93.2 kA/cm2 were obtained with

PVCR of 3.8. More recently, the proximity diffusion technique was used to develop Si

Esaki diodes [39]. This provides a more manufacturable route for Esaki diodes.

After the work by Sweeny and Xu [32], RITDs gained in popularity over the

RTDs. The structure in Fig. 2.11(a) was implemented using In0.53Ga0.47As as the quantum

31 well and In0.52Al0.48As as the tunneling barrier with 4 nm well thickness and 2 nm barrier thickness [40]. A high PVCR of 104 was obtained. A PVCR of 144 was later obtained

[41] using the same structure and the difference was attributed to difference in growth conditions. The current density in both cases was about 160 A/cm2. Sutar et al. [42] re- investigated this structure and studied the effect of barrier thickness and doping density.

They obtained much higher current densities of 3.1 kA/cm2 but the PVCR was reduced to 39. The PVCR is found to reduce with increased asymmetry in the degeneracy of the electron and hole quantum wells.

Soderstrom et al. [43] investigated structure 2 [Fig. 2.11(b)] and obtained a

2 PVCR of 20 with Jp of 600 A/cm . The AlSb barrier thickness were 1.5 nm and 2.5 nm

(thinner barrier closer to substrate) and the GaSb well width was 6.5 nm. A study of the peak current dependence on the AlSb barrier thickness demonstrated a Jp variation from

78 kA/cm2 to 3 kA/cm2 for barrier thickness varying from 0.6 to 2 nm [44]. The valley current is also found to have an exponential dependence. The PVCR increases from 5 to

14 as the barrier thickness is increased. This is due to the off-resonant tunneling currents being attenuated more strongly than resonant tunneling components with increase in tunneling barrier thickness.

Structure 3 [Fig. 2.11(c)] is ideal for a Si material system which does not have other lattice matched materials to form heterostructures with. Si/SiGe resonant interband tunnel diodes were realized utilizing δ-doped p and n quantum wells and a composite

Si/SiGe spacer [5]. This structure is studied in the dissertation and will be described in more detail in Chapter 6.

2.5 Conclusion

In this chapter the concept of quantum mechanical tunneling is introduced which forms the basis of this dissertation. Novel devices known as tunnel diodes, which exhibit a unique negative differential resistance characteristic are discussed. Three broad categories of these devices are the Esaki diodes, resonant tunnel diodes and resonant interband tunnel diodes. An overview of the literature is provided along with the motivation to investigate the interband tunnel diodes.

CHAPTER 3 TUNNEL DIODE DIGITAL CIRCUITS

After the discovery of tunneling by Esaki in 1958, there was considerable excitement to use this unique negative differential resistance behavior in circuits ranging from logic and memory to mixed signal and RF applications. This was due to the fast switching speed of these diodes, not limited by transit time. However, with the advent of

Silicon MOSFETs and their large scale integration and ease of scaling, tunnel diodes were relegated to niche applications. A primary shortcoming being the lack of integration into silicon. However with recent advancements in silicon tunnel diodes and the ability for III-V integration onto silicon, the interest in tunnel diode circuits has renewed.

Further, the possibilities of use beyond conventional boolean logic, in multi-value logic and neural networks has renewed its prospects as 'future' technology, almost half a century after its invention.

3.1 Tunnel Diode Device Model

3.1.1 Large Signal Model

The typical current-voltage characteristic for a tunnel junction in the foward bias is shown in Fig. 3.1. It has a N-shape characteristic with a negative resistance region. The band alignment in the device is engineered to allow quantum mechanical tunneling immediately upon the application of a bias either through intraband or interband tunneling. As the bias is increased further the current peaks at a voltage and then drops due to reduction in tunneling probability until it reaches a minima at the valley 34 voltage . Eventually thermal diffusion mechanism takes over resulting in a rise in current again. Thus there are three distinct regions in the characteristic commonly referred to as (1) first positive differential region (PDR1) for , (2) the negative differential resistance region (NDR) for and (3) second positive differential region (PDR2) for .

3.1.2 Small Signal Model

IV V Vp Vv Vs Figure 3.1 Typical current-voltage (I-V) characteristic for a tunnel diode

The small signal equivalent circuit is shown in Fig. 3.2(a). The tunnel diode is represented by a negative differential conductance and junction capacitance The junction conductance is the slope of the curve at any bias point. The capacitance

is the depletion capacitance across the junction, as a result of charging and discharging the depletion regions. and are the series parasitic resistance and inductance due to interconnects and packaging. A unified model combining the small and large signal models is shown in Fig. 3.2(b). Here is obtained from the large signal model and

35 represents the diode as a voltage-controlled current source. is the junction capacitance as function of bias voltage.

LS LS RS RS

Cd Cd(V) gd I(V)

(a) (b) Figure 3.2 (a) Small signal equivalent circuit of a tunnel diode (b) unified model combining small and large signal models

3.2 Tunnel Diode Device Performance Metrics

3.2.1 Peak-to-valley current ratio

This is the ratio of the current values at the peak and valley voltage biases and is defined by

(3.1)

It is a unit-less parameter and its value should be greater than unity. A large PVCR is desirable for digital applications.

3.2.2 Peak Current Density

It is defined by where A is the cross-sectional area of the device. A high

is desirable for RF and mixed signal applications while a low is preferred for digital applications where low-power is consumption is a primary requirement.

3.2.3 Voltage Span

This is given by and characterizes the width of the NDR region. A large voltage span is preferred for oscillator applications, since the maximum output power is proportional to the voltage span. Voltage span depends on the series resistance . At high currents, the voltage dropped across causes to be shifted to higher voltages. At very high , resulting in observation of hysteresis. This is due to incorrect valley current observation in the forward sweep as the peak voltage overshoots the valley.

On the reverse sweep, the true value of the valley voltage is revealed. This is commonly observed in high current density tunnel diodes.

3.2.4 Voltage Swing

This is defined by and characterizes the broadness of the valley region. It is an intrinsic property of the device and is not affected by series resistance since and

are measured at the same current [45]. A large voltage swing is desirable for digital applications since it results in larger separation between the two stable states and hence better noise margin. However, it also results in reduced switching speed.

3.2.5 Speed Index

The switching speed of a tunnel diode is determined by the current available to charge the parasitic junction capacitance and the average product. is the negative resistance and is inversely proportional to the peak current. Hence a figure of merit typically used is given by and is known as the speed index.

3.3 MOnostable-BIstable Logic Element (MOBILE)

Two serially connected tunnel diodes operate as a latch due to the 'N' shaped characteristic of their current-voltage curve. This can be easily appreciated from Fig. 3.3.

To preferentially latch to a logic '1' or '0', the diodes are designed with a small difference in the peak currents. This concept is the most widely adopted circuit topology and is known as MOBILE (monostable-bistable) logic and was proposed by Maezawa and

Mizutani in 1993 [3].

VBIAS

VOUT Current

TD VBIAS Voltage

(a) (b) Figure 3.3 (a) Two serially connected tunnel diodes and (b) loadline illustrating the latching action

As illustrated in Fig. 3.4, when the bias voltage is smaller than twice the peak voltage (2Vpeak) the number of stable points is one (monostable) and both the devices are in the low resistance or 'ON' state corresponding to the first positive differential region

(PDR1). As the bias voltage is increased beyond 2Vpeak, the number of stable points splits to two (bistable). The device with the lower peak current transits to the second positive differential region (PDR2). This is also known as controlled quenching where the tunnel 38 diode with the smallest peak current is quenched first. Realization of logic functions using this technique require modulation of diode current by the applied input.

Monostable Device with lower peak current - off Bistable state (low)

VOUT VOUT VOUT

VBIAS VBIAS VLOGIC,0 VBIAS

Monostable Device with lower peak current - off Bistable state (high)

VOUT VOUT VOUT

VBIAS VBIAS VLOGIC,1 VBIAS (a) (b) (c) Figure 3.4 Operating principle of monostable-bistable (MOBILE) logic

Peak current modulation can be achieved by the addition of a third control gate terminal, which also serves as the input for the specific binary logic gate function. Figure

3.5(a) shows an inverter implementation. The area of the load diode (TDL) and hence its peak current is chosen larger than that of the driver tunnel diode (TDD). When voltage applied to the control gate is '0', as the clock voltage VCLOCK goes high, the output VOUT goes to '1' as previously illustrated in Fig. 3.4(b). The output remains latched as long as 39

VCLOCK is high. If the control voltage is now switched to '1', the sum of the currents of the driver diode (TDD) is greater than the peak current of TDL. Hence, as VCLOCK switches from low to high, the output now switches to '0'. The clock voltage has to be higher than

2Vp to ensure proper circuit operation. Figure 3.5(b) shows the timing diagram for the circuit. This self-latching property enables gate-leveled pipelining also known as nanopipelining [46]. The rise time of the clock signal is critical for the switching operation and determines the operating frequency.

VCLOCK

VCLOCK Input stabilized Output change s with clock TDL before clock VOUT VIN Input needs to be applied VIN until output latched TDD VOUT Control gate (a) (b) Figure 3.5 (a) Generic MOBILE logic inverter and (b) its timing diagram

Combinational logic can also be realized using resistive and transistor load/driver devices in series with a tunnel diode. Figure 3.6 shows the difference between the load lines for various configurations. The speed of the capacitance charging and discharging depends on the source (ISO) and sink (ISI ) current. From the figure it is apparent that having a tunnel diode both as load and driver provides the maximum source and sink current, hence speed.

ITD ITD ITD

ISI ISI ISO ISI

ISO ISO

VL VH V VL VH V VL VH V (a) (b) (c) Figure 3.6 Loadline for (a) resistor (b) transistor (c) tunnel diode load and tunnel diode driver. Tunnel diode allows maximum charging (ISO) and discharging current (ISI )

The control gate can be added in several ways

(1) Adding a third control gate terminal to the tunnel diode [3] (Fig. 3.7).

Figure 3.7 Peak current modulation of a GaAs/AlAs RTD by addition of control gate [3]

Application of gate bias varies the cross-sectional area available for carrier flow and hence modulates the peak current. Inverter operation using this technique is also illustrated. Application of -0.5V corresponds to input '1' which results in the output going to 0V at the next positive clock edge.

(2) Connecting a transistor in parallel to a tunnel diode (Fig. 3.8) [47], [48]. The composite current is sum of the current through the transistor and the diode. The transistor current is gate controlled, hence the total current is modulated by the gate bias.

Figure 3.8(b) shows an inverter implementation using this method. Chen et al. [47] demonstrated current modulation using this technique with an InP based RTD-HEMT integrated device. The RTD was implemented using AlAs barriers and an

2 In0.53Ga0.47As/InAs well and achieved a Jp of A/cm with a PVCR of 5.5. Three gates with gate width 2.5, 5 and 10 µm result in current modulation of 0.39, 0.84 and 1.85 mA respectively as the gate voltage is modulated from 0 to 0.5V.

VCLOCK ITotal IFET ITD TD V V TDL

+ G G VOUT V V VIN V TDD

(a) (b) Figure 3.8 (a) Modulation of peak current by addition of transistor in parallel to a TD (b) implementation of an inverter

(3) A variant of the previous topology, and the most widely used, is the addition of a tunnel diode to the input branch containing the transistor as shown in Fig. 3.9 [49].

This is known as a linear threshold gate. The transistor in this case acts only as a switch making the gate operation independent of transistor current and hence threshold voltage

42 variations. Thus, robustness of circuit only to tunnel diode process variations needs to be considered. Pacha et al. [49] fabricated a monolithically integrated InP based RTD-HFET to implement the logic input stage as shown in Fig. 3.9(b) . The RTD is fabricated using

2 AlAs/InGaAs and has a Jp of A/cm . The transistor channel length is 1 µm. The

RTD area and HFET gate width are designed such that the RTD is the current limiting device for gate voltage greater than 0.2V. Hence, the I-V characteristics look like an RTD beyond this voltage and is gate voltage independent.

VCLOCK

TDL

VOUT

TD TDD VIN

(a) (b) (c)

Other logic gates can be implemented as an extension of the same concept. Figure

3.10(a) shows a circuit for implementing both a NAND and NOR gate depending on the value of VPRO being '0' (NAND) or '1' (NOR). The experimental results for a NAND gate is shown in Fig. 3.9(b), where VY is set to logic '1'. Reducing transistor channel

43 length to sub-micron and improving peak current density by an order of magnitude is expected to achieve GHz operation.

(a) (b) Figure 3.10 (a) Implementation of a NAND/NOR gate using the RTD-HFET integrated circuit and (b) its experimental results [49]

Matsuzaki et al. [50] developed a relationship for the operating speed of a

MOBILE logic element. The time required to change the output node Vout from initial

voltage Vi to final voltage of Vf is given by:

3.3.1 Threshold Logic

Threshold logic units are the basic building blocks for neural networks. Neurons in the human brain communicate through short electrical impulses. Each neuron receives a multitude of signals from other neurons. If the signal exceeds a threshold then the neuron 'fires' or generates a voltage impulse in response, which is transmitted to other neurons through the axon. An artificial neural network mimics this behavior by modeling

44 a neuron as a threshold logic unit. The basic property of a threshold logic unit is that the output is high (or '1' in boolean logic) when the weighted sum of the inputs exceeds a certain threshold value. Mathematically,

Output, where, are the input signals, are the weights attached to each input and is the threshold value.

positive

weights VCLOCK

TD TD w1 w2 TDL

x1 x2

VOUT

TD TD w3 w4

x3 x4 TDD

negative weights Figure 3.12 Full adder circuit using Figure 3.11 Threshold logic gate using threshold logic gates MOBILE logic

MOBILE logic easily lends itself to realization of logic gates and this possibility was first discussed by Maezawa et al. [51]. Figure 3.11 shows a typical threshold logic gate implementation using MOBILE logic. An advantage of MOBILE logic is that both positive and negative weight's can be realized. Inputs parallel to the upper tunnel diode

(load) act as positive weights and those parallel to the lower tunnel diode (driver) behave 45 like negative weights. The weights here are determined by the area and hence peak current density of the tunnel diodes in each branch. Synthesis tools for threshold logic networks has also been developed [52], [53].

A full adder circuit using threshold logic gates is illustrated if Fig. 3.12 [49]. The first stage has three gates with threshold values of 1, 2 and 3 and evaluates if the sum of the inputs is greater than 1, 2 or 3. Thus for inputs ai, bi and carry from previous stage of ci-1 four possible outcomes for sum (s) and carry to next stage (ci) are:

For a carry is generated. The final value of sum is determined by a second stage which generates a '1' if the sum is 1 or 3. Pacha et al. [49] also proposed a four stage clocking scheme.

(a) (b) Figure 3.13 (a) Four stage clocking. Also showing the four phases in a clock cycle (b) nano-pipelining with a four stage clock and comparison to conventional pipelining [54]

There are four phases in a clock cycle each with equal time interval of T/4 where

T is the clock pulse width; evaluation: the rising edge of the clock when the load capacitance is charged and the gate output is evaluated, hold: the gate holds the output.

The next stage in the pipeline should start during this phase, reset: the falling edge of the clock the load capacitance is discharged and the gate returns to monostable state, wait: the inactive phase of the gate when the clock is disabled. Now 4 pipelined stages can be active in each clock cycle as shown in Fig. 3.13(a). Figure 3.13(b) shows a comparison of a conventional pipeline and a nano-pipeline with a 4 stage clock. In a conventional pipeline latches need to be inserted between combinational logic blocks which increases the gate count. However, the self-latching of mobile gates results in no extra gate overhead. Here M represents a MOBILE gate. The maximum pipeline depth with this nano-pipeline scheme is 4. An algorithm to convert resister-transfer logic (RTL) to nanopipelined architecture has also been developed [54]. Pettengi et al. have proposed that use of negative weights instead of positive can lead to increased operation frequency [55].

3.3.2 Multivalue Logic

A natural extension for NDR-based logic is the possibility of multivalue logic.

Two or more NDR devices stacked on top of each other result in multiple peaks. Figure

3.14 shows an example of two Si/SiGe resonant interband tunnel diodes vertically stacked and connected by a backward diode and the resultant current-voltage characteristics exhibiting two NDR peaks [56].

(a) (b) (c) Figure 3.14 (a) Vertically stacked tunnel diodes (b) the resultant current-voltage characteristics showing the multiple peaks [56] and (c) 3 stable operating points for two such diodes serially connected [57]

Threshold logic design can be extended to now realize multiple-valued

monostable-to-multistable (MML) transistion logic. n diodes connected in series forms a

n-peaked NDR device with n+1 stable operating points (Fig. 3.15) [57]. The parallel

branches can be activated/de-activated by multi-value inputs by using transistors with (n-

1) different threshold voltages such that a transistor with a specific threshold switches on

when the input exceeds one of the logic levels. Now considering a simple 3 valued

inverter as depicted in Fig. 3.15. When the input is at logic '0', both the branches are de-

activated and the sizing of the load tunnel diode pair being sized larger than the driver

results in the output corresponding to logic level '2'. Now when an input of logic level '1'

(Vx1) is applied, transistor Sb1 turns on while Sb2 remains off and the output transitions to

logic level '1'. When the input level is '2' both the transistors are turned on and the output

is driven to logic level '0'. The numbers adjacent to the diodes in the figure represent the

48 normalized peak value for the diodes. The devices switch 'off' in the sequence of their peak ordering as per the principle of controlled quenching.

(a) (b) Figure 3.15 (a) 3 input inverter and (b) its simulated result [57]

3.3.3 Multi-Threshold Threshold Logic Gates

A generalization of the threshold logic gate is a multi-threshold threshold logic gate (MTTG) with k-threshold values and n input values [58]. The output is now determined by:

where, and is even

A three input two threshold gate implementation is shown Fig. 3.16. Here three series tunnel diodes are needed to obtain two thresholds. For example, for implementation of the function the tunnel diode sizing is chosen as

x1 x2,x3 Area RTD quenched y

0 0,0 A1

0 0,1/1,0 A1+AJ1

A1+AJ1

0 1,1 A2+2AJ2

1 0,0 A2+2AJ2

A2+2AJ2

1 0,1/1,0 A2+3AJ2

A2+3AJ2

1 1,1 A0

Table 3.1 Output of multi-threshold logic gate

Depending on the input values of the tunnel diode with the lowest peak current amongst RTD0,1,2 is quenched and output is determined as shown in table 3.1.

3.3.4 Reconfigurable Logic

Figure 3.17 Three input programmable logic implementing all 256 functions. Also shown is the clocking scheme utilizing nanopipelining.

Some of the inputs of an MTTG can be replaced by control bits to implement logic gates which can be programmed to realize different boolean functions depending on

50 the value of the control bits [59]. A block diagram for a 3 input programmable logic element implementing all 256 input logic functions is shown in Fig. 3.17 along with the nanopipelining stages and clocking scheme. Here a modification of the MTTG is used which reduces the gate count [60].

3.4 Tunneling Static Random Access Memory (TSRAM)

Bitline logic '0' logic '1'

Vdd

Wordline

TDL Current VSN Write access transistor TDD Parasitic Voltage capacitance

(a) (b) Figure 3.18 (a) basic TSRAM memory cell design and (b) the bistable latch voltages corresponding to stored logic '0' and '1'

The self latching action of serially connected tunnel diodes can also be exploited to develop compact static memory cells. It can be considered as a MOBILE latch with identical tunnel diodes. To write data at the storage node (SN), an access transistor is connected to the bitline [Fig. 3.18(a)]. The access transistor also facilitates addressability.

Data is stored on the parasitic capacitance at the storage node which is the sum of the capacitances due to the two tunnel diodes and the gate-drain capacitance of the transistor.

Once the data is written at the node, the self-restoring action of the tunnel diodes maintains the value. Hence this is a static volatile memory.

3.4.1 Write operation

The bitline is charged with the data to be written. The wordline is pulled high to select the specific cell to be written. The data is transferred from bitline onto the storage node. When the wordline is pulled low, the data remains latched at one of the bistable latch points [Fig. 3.18(b)].

3.4.2 Read operation

For read operation the bitline is precharged to VDD/2 and kept floating. The wordline is next pulled high. Charge sharing between the parasitic node capacitance and the bitline capacitance results in a small change in the bitline voltage which is sensed and amplified by a sense amplifier. This also results in change on the voltage stored and the read is hence destructive and the data needs to be written back to restore it to its original state.

Figure 3.19 Gain cell modification to the TSRAM memory cell design which avoids use of external capacitor

With device scaling, the node capacitance also scales and an external capacitor will be needed to develop sufficient voltage change on the bitline to be sensed. Hence a gain cell approach was proposed as an alternate [Fig. 3.19] [61]. Here the gate of a second transistor (read FET) is driven by the voltage stored on the storage node (SN).

3.4.3 Fabricated TSRAM Memory Cell

(a)

Word (b)

Bit

Vout (c) Figure 3.20 (a) Schematic of RTD/HFET integrated TSRAM memory cell (b) loadline of RTD's and (c) measured waveforms

A RTD-HFET implementation of TSRAM was demonstrated in an InP material system [62]. The RTD consists of AlAs barriers and an InAs well and an In0.52Al0.48As pre-barrier to further reduce the current resulting in low current densities of 0.16 A/cm2.

These were integrated on the source of an InGaAs/InAlAs HFET as shown in Fig.

3.20(a). The resultant RTD loadlines and waveforms for a 0.45V bias are also shown in 53

Fig. 3.20 (b) and (c). Logic '1' and '0' correspond to 0.36V and 0.08V respectively. A low standby power of 50 nW per cell was thus demonstrated.

A silicon implementation using Si/SiGe RITDs integrated with an NMOS process was also reported [63]. Here, the entire NMOS fabrication process prior to metallization is implemented. The RITDs are grown on p+ active area defined in the n-well region in openings through the field oxide. The material deposited on top of the oxide layers is polycrystalline and another mask layer is needed to define the RITD mesa. Finally metallization is completed. The peak current density of tunnel diodes used here is 52.7

A/cm2 with a PVCR of 1.87 and bias voltage of 0.57V. Logic '1' and '0' correspond to

0.47V and 0.13V respectively. Figure 3.21 shows the cross-sectional schematic and the timing diagram showing successful write operation.

(a)

(c)

(b) Figure 3.21 (a) Cross-sectional schematic of RITD/NMOS integrated TSRAM memory cell (b) loadline of RITD's and (c) measured waveforms

3.5 Conclusion

In this Chapter, the key performance metrics for a tunnel diode are defined. The monostable-bistable logic structure, which is most commonly used to implement boolean logic functionality, is described. Various combinational logic topologies proposed in literature for boolean, multivalue and threshold logic are detailed. Finally, the tunneling

SRAM volatile memory cell structure, utilizing the bistable latching property of serially stacked tunnel diodes, is introduced.

CHAPTER 4 TUNNELING STATIC RANDOM ACCESS MEMORY

Ultra-low power is a dominant issue for embedded memories with the ever- increasing memory density and its power consumption relative to the rest of the components on a chip. As technology is scaled to improve speed and area, voltage scaling has not followed the same trend. The physical lower limit on the subthreshold swing of

60 mV/decade, results in a drastic increase in leakage current with threshold voltage scaling. Hence, the threshold voltage is unlikely to scale below 0.25V, limiting supply voltage (VDD) scaling, to maintain sufficient drive currents. Further, process variations such as random dopant fluctuations (RDF) result in a distribution of threshold voltage's and hence speed and leakage power. For memories with megabytes of capacity, this results in a distribution in memory cell performance and ensuring failure probabilities of one cell in a billion cells has become the major challenge. This makes voltage scaling, while maintaining functional robustness, even more challenging. Voltage scaling of memories is essential not only from a low power requirement but also for compatibility with logic, where voltages are being scaled much more aggressively. The primary embedded or on-chip memory technology is the static random access memory (SRAM) due to the high speeds achievable. Embedded dynamic random access memory (eDRAM) are also being considered as an alternate due to the high memory density requirements for high end computing and graphics applications. In this chapter a tunnel diode based

56 memory, tunneling static random access memory (TSRAM), is designed and simulated and its prospects as a viable alternate to current embedded memory technologies is analyzed, primarily from a voltage scaling perspective. To date, simulation results for

TSRAM have been limited to single memory cell SPICE simulations [4], [64]. To fully evaluate TSRAM performance and robustness to process variations and make a fair comparison to current embedded memory solutions, a post layout simulation is essential.

This should also lower the barrier for commercial adoption. Hence, a platform for insertion of alternate tunnel diode models using different material systems into a standard electronic design automation (EDA) tool, Cadence, is created to allow VLSI design using tunnel diode based circuits.

4.1 Static Random Access Memory (SRAM)

Embedded memory

Figure 4.1 Core i7, 32 nm technology processor showing the area consumed by on-chip cache memory (source: Intel core i7 whitepaper)

SRAM's are used to implement on-chip cache memory as well as registers and buffer memories. They provide the highest random access speed as well as are

57 compatible with the CMOS process technology. With increasing demand for on-chip integrated memory, SRAMs now occupy more than 50% of the overall processor chip area (Fig. 4.1). Hence, its area and power consumption is a major factor in chip costs and power budgets.

4.1.1 Memory Cell

BL VDD BLB

WL WL M3 M6

QB M2 Q M5 M1 M4

Figure 4.2 Memory cell of a static random access memory

The SRAM memory cell consists of 6 transistors with two cross-coupled inverters and two access transistors as shown in Fig. 4.2. The cross-coupled inverters can hold data using the positive feedback mechanism as long as the power supply VDD is applied.

The write cycle starts by applying the data to be written to the bitline (BL) and its complementary value to BLB. Next the wordline (WL) is pulled high. For example assuming that initially Q was '1' and QB was '0' and a '0' is now being written onto Q.

Since an NMOS is strong at passing a '0' the bitline with '0' is considered. In this case, the

58 transistor M2 tries to pull the node Q low while competing with M3 which is pulling the node to VDD. Hence M2 (M5) has to be sized to have a driving ability stronger than

M3(M6) to flip the cell.

The read cycle starts by pre-charging the bitlines to VDD and allowing it to float.

The wordline is now pulled high. Now if Q(QB) is storing a '0', its voltage is increased by

'0'+ΔV with the transistors M2(M5) and M1(M4) acting as a voltage divider.

Simultaneously the bitline voltage BL(BLB) reduces to VDD - ΔV. Once the differential voltage between the two bitlines is sufficient to be sensed, the sense amplifier is activated

Now sizing of M2(M5) and M1(M4) should be such that the ΔV does not exceed the switching threshold of M4(M2) and M6(M3). The ratio of the transistor width of the pull down transistors M1, M4 to the access transistors M2, M5 is known as β ratio and determines how high the voltage at the node storing a '0' rises during a read access.

4.1.2 Functional Robustness Issues with Scaling

SRAM functional margins are determined by three primary parameters - write margin, static noise margin and the cell current. Process scaling and the resulting increase in process variations, increases the failure probability of each of these parameters.

Voltage scaling affects all three parameters and makes functional robustness further challenging.

4.1.2.1 Write margin

This is defined as the minimum bit voltage required to flip the state of the cell. To maintain robust operation with process variations, the pull up transistors may need to be designed weaker or the access transistor designed stronger for the worst case process

59 corner of fast PMOS slow NMOS. The ratio of transistor strengths of access transistors

M2, M5 to pull up transistors M3, M6 is known as γ ratio. As devices are scaled the variation in γ ratio makes it a critical design parameter

4.1.2.2 Static Noise Margin (SNM)

VDD QB(V)

M3 M6 +Vn SNM Vn Q + - Vn - + QB -Vn M1 M4

Q(V) (a) (b) Figure 4.3 Butterfly plot showing the static noise margin (SNM) its reduction with noise and (b) noise source configuration to determine SNM

This is the most common metric to characterize SRAM operation and is defined as shown in Fig. 4.3. It is the maximum noise that can be tolerated by the cell before it flips its state. The voltage transfer curves for the two inverters superimposed forms a butterfly plot (Fig. 4.3). The curves intersect at three points forming two lobes. The static noise margin is defined as the length of the side of the largest square that can fit in the smaller of the two lobes. Two noise sources Vn are applied to the input of each inverter with opposite polarity. As Vn is applied the transfer curves shift as shown by the dotted lines. The cell remains bistable as long as two lobes are present. Thus the cell is more likely to lose one of the two data value. The cell is more vulnerable to noise and SNM 60 degradation during read access. Careful design of the β ratio is needed to maintain the required SNM. Process scaling results in variation of β ratio and deterioration of SNM

[65].

4.1.2.3 Cell current (Icell)

The cell current determines the time to discharge the bitline. Due to the large bitline capacitance this is a slow operation and determines a large percentage of the total access time. The cell current is determined by the transistor strengths of the access transistors M2, M5 and the pull down transistors M1, M4 which connects the bitline to ground. With process scaling the bitline capacitance reduces. However, with voltage scaling and threshold voltage variations the gate overdrive is greatly reduced.

Additionally leakage current through unselected cells causes discharge of the complementary bitline acting as reference, reducing the differential voltage developed.

4.1.2.4 Voltage Scaling

Voltage scaling reduces power consumption in two primary ways.

(a) Reduction in standby power

(b) Reduction in leakage current: Both drain induced barrier lowering (DIBL) and gate induced drain leakage (GIDL) decrease with VDD.

Figure 4.4 shows the dependence of WRM, SNM and Icell on VDD [66]. It is clear that maintaining functional robustness becomes very challenging as voltages are scaled and hence limits low-power operation of SRAMs. Voltage scaling is thus limited to about

0.7V and 7T and 8T SRAM cells have been proposed to overcome these challenges [65].

(a) (b)

Figure 4.4 VDD dependence of (a) write margin (b) static noise margin and (c) cell current at 0σ and 6σ points. Failure rate of all three parameters greatly increases with voltage scaling [66]

(c)

4.2 Embedded Dynamic Random Access Memory (eDRAM)

DRAM's have been popular for low cost, high density, standalone memory.

However standalone and on-chip DRAM have different optimization criteria. While standalone memory is designed to primarily achieve high memory densities at the cost of speed, on-cache memory has to be designed for high-speed low power operation at the expense of increased area.

4.2.1 Memory Cell

A typical DRAM memory cell consists of 1 transistor-1 capacitor (Fig. 4.5). The capacitor passively stores the data while the transistor provides bit addressability through the wordline and bitline. Due to lack of a feedback mechanism, as in an SRAM, the charge stored on the capacitor reduces with time due to parasitic leakage, and a refresh operation is needed periodically to restore the charge.

BL WL

access Storage capacitor, C transistor, M

Figure 4.5 Memory cell of a dynamic random access memory

The write operation consists of the bitline being charged with the voltage to be written. The wordline is then activated by pulling it high and the data on the bitline is transferred onto the capacitor.

Read operation involves precharging the bitline to a value of VDD/2 and leaving it floating. The wordline is now activated. Since the bitline is shared by a number of cells

(typically 512 cells in a column), the length of the bitline and hence is capacitance CBL is substantially larger than the storage capacitor Ccell. Hence, charge sharing between the two capacitances results in a small voltage change on the bitline depending on a logic '1' or '0' being stored on the cell. This voltage is sensed and amplified by a differential sense 63 amplifier, typically a cross-coupled inverter pair. The differential signal developed on the

bitline is given by: . For a VDD/2 sensing this reduces to

. This is positive for a high stored and negative for a low stored

on the node. The read operation is destructive and the data amplified by the sense amplifier is written back onto the cells after the read.

Word-boosting or word-bootstrapping i.e. using wordline voltage greater than

is required for both read and write, to null the effect of the Vth drop across the

NFET access transistor. It also reduces the effect of Vth non-uniformity across the wafer.

4.2.2 Voltage Scaling Issues

As dimensions are scaled, the length of the bitline reduces, however the spacing between lines also reduces resulting in the net bitline capacitance remaining the same.

This presents the challenge of maintaining a constant storage cell capacitance with reducing dimensions. This is primarily achieved by use of higher dielectric permittivity materials in the capacitor and by innovative fabrication techniques. Reducing the number of cells per bitline can reduce the bitline capacitance at the cost of increased area overhead of the sensing circuit. This also helps improve the read/write access speed. A smaller array size also allows reducing the cell capacitance [67].

Wordline voltage is restricted by threshold voltage scaling. Wordline voltage has to be greater than the sum of VDD+Vth0+the threshold voltage increase due to body effect since the source voltage is non-zero. With reduced array size and hence bitline capacitance, the increased cycle speed allows shorter refresh rates. This in-turn allows using transistors with lower Vth despite the higher leakage currents. 64

Bitline voltage (VDD) scaling is more critical as it is the main contributor to power dissipation since during a memory access a single wordline is turned on while a large number of bitlines are activated. The minimum VDD is governed by the signal to noise ratio of the cells and the gate over-drive needed for the sense amplifiers.

Voltage at the storage node is reduced not only by leakage current but also alpha particle or cosmic-ray irradiation to the cell node. The signal generated during a read is given by:

(4.1)

where, is the initial charge = , is the charge due to noise, is the charge reduction due to leakage, is the charge due to irradiation. and hence S/N ratio a reduced with scaling of and . Thus, VDD should be large enough for reliable sensing. The minimum VDD is given by

(4.2) where, is the threshold voltage mismatch between the sense amplifer MOSFET pair and is the differential noise due to bitline-bitline coupling capacitance when voltage swings on the adjacent bitline.

The minimum VDD requirement set by sense amplifier gate overdrive can be shown to be [68]:

(4.3) where, is the common mode noise due to negatively coupled common-mode voltage to the bitlines from the precharger and equalizer when the precharge pulse goes low.

Thus noise and threshold voltage variations are critical to voltage scaling. 65

4.3 Tunneling Static Random Access Memory (TSRAM)

As discussed in the previous chapter, the unique negative differential resistance characteristic of tunnel diodes can be exploited to develop a memory cell. A modification of the gain cell [62] is developed here [69]. The cell structure is shown in Fig. 4.6.

Readline Bitline

Read access Vdd transistor, MN2 Wordline TDL VSN Read transistor, Write access MN1 transistor, MN0 TDD

Figure 4.6 TSRAM 3 transistor- 2 tunnel diode memory cell

4.3.1 Memory Cell Operation

The write cycle is similar to that of a DRAM. The bitline is charged with the data to be written on the cell. The wordline is activated to turn on the write access transistor

(MN0) and select the cell. Data on the bitline is now transferred onto the storage node and stored on the parasitic capacitor formed by the two tunnel diodes, the drain-bulk capacitance of the write access transistor and the gate capacitance of the read transistor.

For the read cycle, a read transistor(MN1) is added which is driven by the bit state stored on the cell. A '1' stored in the memory cell turns the transistor 'on' while a '0' 66 stored keeps the transistor in the 'off' state. A third read access transistor (MN2) provides addressability during a read operation by activating the readline. The read operation in this case is non-destructive and does not degrade the voltage stored on the bit cell. This is a growing concern with SRAM cells leading to consideration of 8T SRAM cells [70] as voltages are scaled. DRAMs on the other hand always have a destructive read operation and require a write-after-read operation to restore the data to the original level.

All transistors in the cell are chosen as NFETs due to their larger drive current for the same size as compared to PFETs. Including a mixture of NFET and PFET also increases the cell area due to the need for separate well's for both. Now an NFET is good at passing a '0' but drops a threshold voltage across itself when passing a '1'. Hence, the read transistor is connected to Ground rather than VDD to ensure maximum change on bitline when turned on. However, this results in an inverted logic being read out, i.e. when a '1' is stored, MN1 turns on, driving the bitline low while a '0' keeps MN1 off, keeping bitline voltage to the high precharged value.

4.3.2 Cadence Implementation

4.3.2.1 Cell Schematic

The IBM 90 nm product development kit (PDK) available from MOSIS was used to implement the TSRAM which was the smallest node PDK available when this work began. Minimum sized NFET transistors with W=140 nm and L = 80 nm are used. To implement the tunnel diode a model was created in VerilogA. This was linked to a tunnel diode symbol to facilitate use in a schematic as detailed in Appendix A. Low Vth transistors are used for the read transistor and read access transistor to ensure a large

67 drive current while regular Vth transistor is used for the write access transistor to minimize leakage current. The nominal Vdd is chosen as 0.5V. The control signals such as the wordline and readline voltage are set to 1V which is the nominal voltage for this technology kit. This takes care of the 1 Vth drop across the NFETs when passing logic '1' which is 0.5V in this case.

Figure 4.7 Schematic of TSRAM memory cell. All NFETs are sized with W=140 nm, L=80nm

4.3.2.2 Cell Layout

The CMOS-tunnel diode fabrication process is as follows. The CMOS process is completed prior to metallization. Then n+ active areas are defined where tunnel diodes will be grown. An extra mask level is needed to define the openings in the field oxide where the tunnel diode will be places. The tunnel diode can then be grown epitaxially using molecular beam epitaxy or chemical vapor deposition. Material deposited on top of

68 the oxide will be polycrystalline. Another mask level is needed to define the tunnel diode mesa. Finally, metallization is completed, taking care to stay within the tunnel diode thermal budget to maintain sharp doping profiles. Two contacts are needed, to the top of the mesa and bottom contact to the n+ active area.

TDL Bitline Via M1-M2 Vdd Low Vth Wordline MN0 Via Diffusion-M1 SN M2 Readline 1.585 µm M1 MN2 Poly TDD Diffusion TD Mesa MN1 Gnd Via RITD-M1

1.155 µm Figure 4.8 Layout of TSRAM memory cell

Two new layers are introduced, to define the mesa and the metal 1 contact to the top of the device by modifying the technology file (see appendix A). The tunnel diode mesa area is chosen to be 200 nm × 200 nm, which is the minimum area taking into account the via size and tolerance's for the chosen technology. The cell layout is shown in

Figure 4.8.

wordline

readline

bitline

Write

column Data in 32 Prechargeselect 0.45 V

read SE

colu lvt lvt mn write selec back lvt lvt t

SEb

Data 32 Figure 4.9 Memory architectureout for a 32 × 32 bit array showing sense amplifier and writeback circuit for read-before-write operation

4.3.3 Memory Array Architecture

The memory architecture for a 32 × 32 bit array is shown in Fig. 4.9. As discussed in section 4.3.1, the output read out from the cell is inverted to the data stored, i.e. the bitline is pulled below precharge voltage value for a logic '1' stored and remains at precharge voltage for a logic '0'. Hence, an intuitive and simple sense amplifier implementation would be an inverter. This is a single-ended sensing scheme.

Conventional differential sensing can also be used similar to a DRAM. However, with voltage scaling, differential scaling becomes more unreliable due to leakage currents from unaccessed cells causing variation on the reference bitline. Hence, there is some merit in exploring a single ended scheme. On the flip side, single ended sensing requires a much larger signal difference to be generated for sensing, hence the number of rows along a bitline is restricted. 32 rows along a bitline were found the maximum, yielding robust operation, with minimum sized inverters.

As mentioned earlier, all control signals such as wordline, readline, writeback and column select signals are chosen to be 1V. Since logic '1' is 0.5V this allows use of NFET only as pass transistors instead of complementary pass transistors or word bootstrapping for the wordline.

4.3.3.1 Read cycle

The timing diagram for read cycle is shown in Fig. 4.10(a). The bitline is precharged to 0.45 V. The choice of precharge voltage is critical. It should be high enough to be detected as '1' by the sense amplifier during a read '0' operation. However, an upper limit is set by the time required to discharge the bitline in a read '1' operation.

Clock address data precharge readline Sense enable (SE) SEb Read column select

(a)

Clock

address data precharge readline

Sense enable (SE)

Read column select

Writeback Write column select Wordline

(b)

Figure 4.10 Timing diagram for (a) read cycle (b) write cycle

Readline and read-select are activated to select the memory cell to be read. The read transistor is ON or OFF depending on a '1' or '0' stored in the cell. If a '1' is stored, the bitline is pulled low, else the bitline stays the precharge voltage. The bitline drives the sense amplifier. The sense amplifier is enabled by applying a 0.7V to SE and 0V to SEb.

Low threshold voltage (lvt) transistors are used to implement the sense amplifier to permit fast sensing.

4.3.3.2 Write Cycle

The timing diagram for a write cycle is shown in Fig. 4.10(b). The write operation is preceded by a read to prevent loss of data on selected rows but unselected columns.

The read operation ensures that these cells are written back with data previously stored on them. The writeback circuit consists of a buffer that drives the data read out from the sense amplifier onto the bitline. Next, data to be written is inputted from the I/O line by selecting the write column select and the wordline is activated to write data into the memory cell.

4.3.4 Results

4.3.4.1 Peak Current Requirement

The peak current of a tunnel diode is inversely proportional to the tunneling barrier thickness for a given device area. For silicon based resonant interband tunnel diodes, it has been shown that he tunneling barrier can be varied by tuning the spacer thickness allowing tailorability of peak current [71], [72]. A low peak current is desirable since it ensures a low valley current for a given peak to valley current ratio and the valley current primarily contributes to standby power consumption. However, a lower limit on

73 the peak current is set by the minimum current needed to re-charge the storage node capacitor due to any voltage fluctuation on the node. A particular case of concern is the phenomenon of charge injection [73], [74].

Figure 4.11(a) shows the voltage on the storage node during and after a write '1' operation. As is evident, a glitch occurs on the node when the wordline is deactivated at the end of the write cycle. This is due to charge injection. Two mechanisms contribute to charge injection: channel charge and the overlap capacitance between gate and junction.

The voltage change at the storage node, assuming channel charge flows equally to source and drain, is given by:

(4.4)

The storage node capacitance is given by:

(4.5) where, , are parasitic capacitances of driver and load tunnel diodes, is drain-bulk capacitance of write access transistor and is gate-source capacitance of the read transistor.

Thus, a larger storage node capacitance results in smaller voltage variation due to injected charge. For example, as illustrated in Fig. 4.11(a), if the read transistor width is doubled, doubling , the glitch at the storage node is reduced.

However, any parasitic capacitance increase comes at a cost of increased cell area and reduced node charging time, which offsets the benefit of a lower injected charge.

Another method to confirm charge injection is by adding a dummy transistor between the write access transistor and the storage node [Fig. 4.11(b)]. This is a standard 74 technique to absorb the channel charge. The dummy transistor is designed with area half

1.0 wordline bitline W =W g,read 0.8 glitch in storage W = 2W Vdd = 0.5V g,read node ______

0.6 wordline wordline

0.4 TDL

Voltage(V) SN 0.2 2W/L W/L

0.0 TDD Access Dummy 0 1 2 3 4 5 transistor transistor time (ns) (b) (a)

wordline wordlineb 1.0

0.8 Figure 4.11 (a) Effect of doubling the

0.6 read access transistor gate width on

SN storage node (b) memory cell with

0.4 dummy transistor (c) simulated waveform with dummy transistor Voltage (V) Voltage 0.2 showing no glitch in storage node 0.0

0.0 0.5 1.0 1.5 time (ns) (c) of the access transistor (assuming half of the channel charge moves to source end and half to drain end) with drain and source shorted. The dummy transistor is turned on when the wordline is pulled low using a non-overlapping second clock. This absorbs the channel charge preventing its effect on the storage node as demonstrated in Fig. 4.11(c).

The latch action of tunnel diodes naturally restores the voltage drop due to charge injection. The minimum peak current is set by the current needed to restore the node voltage within a clock interval to a voltage high enough for robust read operation. The current charging the parasitic node capacitance is the difference between the current through the load tunnel diode and driver tunnel diode I0, assuming the leakage current is negligible [Fig. 4.12(a)]. If the bias voltage is increased to 0.6V, I0 increases. However, the standby power also (~ IS ×VS) also increases [Fig. 4.12(b)].

(a) (b)

Figure 4.12 Current I0 charging the parasitic node capacitance after wordline is deactivated for (a) VDD = 0.5V and (b) VDD = 0.6V. The standby power consumption is given by IS ×VS

A peak current of 500 nA was found to be the minimum current for robust circuit operation including process variations. Figure 4.12 shows the stored voltage variation for different peak current values, evaluated at the worst case, slow NFET- slow PFET, corner. This corresponds to a peak current density of 1.2 kA/cm2 for a 200 nm × 200 nm device.

(a) (b) Figure 4.13 simulated waveforms of (a) storage node output voltage for peak currents of 700 nA, 500 nA, 400 nA and 100 nA and PVCR of 4.02 showing read '1' failure below 400 nA

(a) (b) Figure 4.14 (a) Simulated waveforms for (a) read/write '1' and (b) read/write '0' operation. rbw = read before write, w1 = write '1', pre = precharge, wb1 = writeback '1', rd = read cycle, w0 = write '0', wb0 = writeback '0' (Also overlapped are control signals generated during each clock cycle)

4.3.4.2 Performance at 'Typical' Corner

Read/Write operation results for a typical corner are shown in Fig. 4.14. The bitline is precharged to 0.45V. A read operation is performed prior to write, to facilitate writeback, by activating readline and column read select. Next the wordline and writeback signals are pulled high to writeback the data. The wordline is maintained high which the writeback signal is deactivated and the column write select is turned on to write data into the cell. A precharge-read-writeback operation is tested next. Figure

4.14(a) shows the case for a '1' stored while 4.14(b) depicts the case of a '0' stored in the cell. The read access time is 1 ns. The write access time, including read time is 2 ns. This can be reduced to 0.5 ns if a 32 bit write is performed, eliminating the need for a writeback operation.

4.3.4.3 Impact of Process Variation

Robustness to process variation has become extremely critical as device dimensions have entered the sub-nanometer region. The PDK from MOSIS includes models for process variation of transistor gate oxide thickness, threshold voltage and dimensions. STI stress and well edge-proximity effects are also included. Four corner simulations are performed for 32 bit read/write '1' and read/write '0' operation. Figure

4.15 shows the storage node voltage at each corner while Fig. 4.16 shows the sense amplifier output. The slow NFET fast PFET corner shows a slightly higher sense amplifier output for logic '0'. Ideally the NFET should be turned on while PFET should remain off when the sense amplifier input is equal to the precharge voltage. However, due to the low PFET Vth and high NFET Vth in this corner, both transistors are turned on,

78 resulting in the increase in voltage read out. A 65% drop in cell drive current is observed between the fast and slow NFET corners due to a threshold voltage variation of 120 mV as illustrated in Fig. 4.17. This limits the number of cells/bitline.

(a) (b) Figure 4.16 Voltage stored at storage node for (a) read/write '1' and (b) read/write '0' operation. Also overlapped are the control signals generated during each clock cycle. FNFP: Fast NFET Fast PFET; SNSP: Slow NFET Slow PFET; FNSP: Fast NFET Slow PFET; SNFP: Slow NFET Fast PFET

(a) (b) Figure 4.15 Output of sense amplifier for (a) read/write '1' and (b) read/write '0' operation. Also overlapped are the control signals generated during each clock cycle. FNFP: Fast NFET Fast PFET; SNSP: Slow NFET Slow PFET; FNSP: Fast NFET Slow PFET; SNFP: Slow NFET Fast PFET

Figure 4.18 Cell read current (solid lines) and bitline voltage (dashed lines) during read '1' operation

(a) (b) Figure 4.17 Selection of precharge voltage and sense amplifier voltage based on sense amplifier output for (a) read '1' and (b) read '0' operation for successful read operation

Choice of sense amplifier bias voltage (VDD,SE) and precharge voltage (VPRE) is also determined from limitations at process corners [Fig. 4.18]. Selection of the two voltages is based on the slow NFET, fast PFET (SNFP) corner for read '0' operation and slow NFET-slow PFET (SNSP) corner for read '1' operation. For a successful read the following conditions should be satisfied:

(4.6)

(4.7)

4.3.4.4 Monte Carlo Simulations

Monte-carlo simulations are further used to determine 6σ performance with process variations and geometric mismatch. Tunnel diode current variation due to non- uniform spacer thickness across a wafer is also modeled assuming a 0.5 monolayer thickness variation. For silicon, this is equal to ~0.25 nm (Δ). From experimental data on peak (JP) and valley (JV) current density dependence on spacer thickness, the following relations are obtained:

(4.8)

(4.9)

Hence Percentage change in JP :

or, (4.10)

Thus peak current is modeled as a Gaussian distribution about 500 nA with 3σ = 20% of

500 nA = 100 nA.

To model valley current density variation, the relation between peak current and valley current is determined as follows:

From Eq. (4.10):

(8)

(9)

where, IP is variation in peak current from its nominal value Inom.

(10)

(4.11)

In order to implement this variation in the veriloga model, a linear approximation is fit to the negative differential region (NDR) current. The peak current is chosen randomly from the monte carlo simulator with mean value of 500 nA and 3σ variation of 100 nA. The value of as calculated using equation (4.8) is added to the empirical . Since and

are unequal, the PVCR of the device is also varies with peak current. Figure 4.19(a) shows a comparison of the empirically fit current-voltage characteristics and that obtained as a result of linear fitting to the NDR region. Also shown are I-V characteristics for two diodes with peak currents of 400 and 600 nA with resultant PVCR obtained as

6.7 and 2.8 respectively. The PVCR variation with peak current obtained from Monte-

Carlo simulations is shown in Fig. 4.19(b). RITD capacitance variation with spacer thickness is included in the model by assuming the capacitance to be given by εA/d

where d is the spacer thickness. Hence, RITD capacitance = . Where, Cnom

= nominal capacitance for spacer thickness tnom (8 nm). 82

800 Fit to experimental data 6.5 700 Linear fit to NDR region 400 nA peak current device 6.0 600 nA peak current device 600 5.5

500 5.0 400

4.5

300 PVCR 4.0

Current (nA) 200 3.5 100 3.0 0 2.5 0.0 0.2 0.4 0.6 0.8 1.0 420 450 480 510 540 570 600 630 Voltage (V) Peak Current (nA) (a) (b)

480 50

475 45

470 40

465

35 460

30 Logic'1' (mV)

455 Logic'0' (mV) 25 450 20 440 480 520 560 600 440 480 520 560 600 Peak Current (nA) Peak Current (nA) (c) (d)

Figure 4.19 (a) Linear fit done to the NDR region for monte-carlo simulations and I- V characteristics obtained for devices with 400 and 600 nA peak current (b) Monte- carlo simulations showing PVCR variation with peak current (c) scatter in bistable latch points as a result of mismatch between the load and driver tunnel diode

(a) (b) (c) Figure 4.20 Monte-Carlo simulation results for read/write ‘1’ operation showing (a) variation in voltage written into storage node SN at the end of write cycle (b) variation in SN voltage 1 ns after wordline is pulled low, showing the restoring action of the RITDs (c) variation in output of sense amplifier at the end of read cycle

(a) (b) (c) Figure 4.21 Monte-Carlo simulation results for read/write ‘0’ operation showing (a) variation in voltage written into storage node SN at the end of write cycle (b) variation in SN voltage 1 ns after wordline is pulled low, showing the restoring action of the RITDs (c) variation in output of sense amplifier at the end of read cycle

A maximum mismatch of 20 percent between the two tunnel diodes in a memory cell is also incorporated. Hence the peak and valley currents for both the diodes vary resulting in a variation in the bistable latch points. The scatter in bistable latch points for logic ‘1’ and logic ‘0’for the memory cell is shown in Fig. 4.19(c) and (d).

To estimate robustness to process and mismatch variations 1500 Monte-Carlo

simulations are run with latin hypercube sampling to get a better spread in sample points.

The results are as shown in Fig. 4.20 and 4.21. Figure 4.20(a) and 4.21(a) shows the

voltage stored in the memory cell at the end of the write cycle for logic ‘1’ and ‘0’,

respectively. The restoring action of the RITDs pulls the stored voltage towards the

bistable latch point. Storage node voltage 1ns after the wordline is deactivated is shown

in Fig. 4.20(b) and 4.21(b). The corresponding sense amplifier output voltage at the end

of the read cycle is as shown in Fig. 4.20(c) and 4.21(c) showing successful read/write

operation with ± 3 sigma of chip mean and across the chip variation.

(a) (b) Figure 4.22 Threshold voltage variation for low threshold voltage (a) NFET (b) PFET obtained from Monte-Carlo simulations showing actual distribution and distribution with chip mean skewed to a process corner. ACV = across chip variation. RSS = root of sum of squares

The failure region corresponding to the worst case cell on the worst case chip is

evaluated using Monte-Carlo simulations run with the chip mean skewed to a 3 sigma (a) corner and across the chip variations enabled. From the four corner simulations, the slow 85

(a) (b)

NFET-slow PFET corner is found critical for write/read ‘1’ operation while the slow

NFET-fast PFET corner is critical to the write/read ‘0’ operation. The critical transistor

for write operation is MN0 while for read operation is MN1 and sense amplifier PFET

(SAMP) and NFET (SAMN). Figure 4.22 illustrates the threshold voltage variation for

the low Vth NFET and PFET along with the number of sigma from mean for the actual

and skewed distributions.

(a) (b) Figure 4.23 Storage node voltage variation with across the chip variation for (a) Write ‘1’ operation skewed to slow-slow corner (b) Write ‘0’ operation skewed to slow NFET, fast PFET corner, showing no failure points.

The scatter plots in Fig. 4.23 show the storage node voltage 1ns after the wordline is pulled low. No failure is observed for both write ‘1’ and ‘0’ operations.

A scatter plot of the sense amplifier output, 1ns after the readline is turned on,

with the three critical transistors involved in read operation is shown in Fig. 4.24. The

read ‘1’ operation has a linear `dependence on the read transistor (MN1) threshold

voltage, while the read ‘0’ operation has a linear variation with the sense amplifier NFET 86

(SAMN) threshold voltage. The fail boundary is determined from Fig. 4.24 where a fail for read ‘1’ operation is an output less than 0.3V and a fail for read ‘0’ operation is an output greater than 0.15V. The threshold voltage variation is modeled as a Gaussian distribution. From Fig. 4.25 the cell failure probability during a read ‘1’ operation, assuming the process parameters are uncorrelated, is

(4.12)

The read ‘0’ failure probability is

(4.13)

For small size memories of a few kB the cell failure probability is small enough to ensure good yield. However, for large arrays of 1MB, the read access time should be increased and a more judicious choice of precharge and sense amplifier VDD should be made, to improve the yield.

(a) (b) Figure 4.24 Scatter plot of sense amplifier output for (a) read ‘1’ operation skewed to slow-slow corner (b) read ‘0’ operation skewed to slow NFET, fast PFET corner with sense amplifier PFET and NFET and read transistor MN1 SA = Sense Amplifier

(a) (b) Figure 4.25 Fail boundary for (a) read ‘1’ operation skewed to slow-slow corner and (b) read ‘0’ operation skewed to slow NFET, fast PFET corner

4.3.4.5 Power Analysis

Both active and standby power are important when considering power consumption. As more and more functionality is added into mobile devices, the active power component is becoming dominant. For the TSRAM memory cell, the average power during a write ‘1’ operation is determined to be 0.45 µW/cell while the read ‘1’ power is 2.6 µW/cell. The read ‘0’ power is 0.15 µW/cell. The dynamic power consumption per cell is 1.8 × 10-7 mW/MHz which is much lower than that of an SRAM.

It is calculated using:

Where, ,

The standby power consumption of each device in the cell is shown in Fig.

4.26(a). The total standby power is 60 nW/cell. The dominant standby power component is the power due to valley current flowing through the tunnel diodes at the latch point.

For the same peak current a higher PVCR leads to lower static power consump tion.

Figure 4.26(b) illustrates the power consumption for a PVCR of 144 (The highest PVCR reported for any NDR device [41] ). An order of magnitude reduction in standby power is observed (standby power/cell = 7nW). Further lowering of standby power would require a lower peak current or higher PVCR device. The former would result in lower speed of operation as explained in section B thus resulting in a speed-power tradeoff. However, standby power consumption is becoming a lesser issue as memory architectures are

89 incorporating low-power idle states where the memory arrays are powered down during standby [75].

Active energy is obtained by integrating the power over the write/read cycle while the standby energy is obtained by integrating the standby power over a clock cycle (0.5 ns). The energy consumed by the 32 cells along a wordline is 2.62 fJ when a ‘1’ is written into all 32 bits, 71 fJ for a 32 bit all one read, and 3.9 fJ for a 32 bit all zero read. The standby energy is 1.3 fJ.

(a) (b)

4.3.5 Voltage scaling

Voltage scaling of TSRAM is limited only by limitations in transistor threshold voltage scaling (i.e. increased leakage current issues). For example in this design a 1V is used for wordline. However, a low Vth transistor could be used as the write access transistor and the wordline voltage can be reduced to Vlogic,1+Vth,low = 0.5+0.15 = 0.65 V.

However, a regular Vth transistor is used to keep the leakage current low. Alternate 90

transistor technologies such as Tunnel FETs, with lower subthreshold swing can be

considered to replace the MOSFET to overcome the leakage current issue with threshold

voltage scaling. The lower limit on Vlogic,1 is set by the peak voltage (Vpeak) of the

tunnel diode and is approximately equal to 2×Vpeak. Vpeak depends on the material system

and device structure used for the tunnel diode and can be as low as 0.1V. The memory

cell configuration itself is robust to voltage scaling.

ITRS (90nm 90 nm TSRAM ITRS (90 nm Embedded Technology SRAM) (PVCR =4) DRAM) HP/LSTP*

(wordline/SA/cell) Vdd 1.1/1.2 2.5 1/0.7/0.5

Wordlength 32 bit 32 bit 32 bit 1.13 1.83 Cell size µm2 (1.96 – logic 0.1-0.243 (logic DRC rules) DRC) Write cycle time 0.5 0.5/2 1 (ns) Read cycle time (ns) 1 0.4/2 1

Dynamic power per 1.8×10-7 7×10-7/8.5×10-7 1×10-7 cell (mW/MHz)

Static Power Dissipation per cell 6×10-5 1.5×10-4/6×10-7 1×10-11 (Standby) (mW)

Table 4.1 Quantitative comparison of various embedded memory cell performance

4.4 Performance Comparison

3T-2RITD TSRAM 6T-SRAM 1T-1C eDRAM Cell size (µm2), 1.83 90 nm 1.13 0.1-0.243 (logic design rules) technology Feedback action of Restoring action of tunnel Floating capacitor, requires Data storage cross-coupled diodes refresh operation inverters Destructive No No Yes readout Single-ended sensing utilized in this work. Sensing Differential sensing can Differential sensing Differential sensing be utilized, similar to DRAM 4-6 additional mask steps. Requires large cell capacitor; Compatibility 2 additional mask steps Compatible difficult to fabricate with scaling with logic dimensions since cell capacitance needs to be constant Small. Limited by Small. Limited by time to time for node storing Large. Limited by time to charge charge parasitic storage Delay ‘1’ to reduce below cell capacitor node capacitance trip point of inverter

V ~0.7V Limited by peak voltage DD V ~1.5V Limited by functional DD,WL Voltage scaling of tunnel diodes. V ~1V to maintain margins due to process DD,logic1 V > 2×V ~ 0.2V sufficient charge on capacitor DD,logic1 peak variations with [25] / V th,read dimensional scaling VDD,WL> VDD,logic1+Vth Table 4.2 Qualitative comparison of voltage scalability prospects of embedded memories

A quantitative comparison of the three embedded memory solutions discussed in this chapter is presented in table 4.1. The SRAM and eDRAM values are obtained from the International Technology roadmap of semiconductors (ITRS), 2007 for the 90 nm technology node. It should be noted that the static power for DRAM does not include the refresh power. A qualitative comparison of the memories with respect to voltage

92 scalability prospects is presented in table 4.2. It should be noted that the cell size is larger for TSRAM due to the use of logic design rules.

4.5 Conclusion

In summary, a 32 × 32 bit tunneling SRAM memory array was simulated by integrating an empirical tunnel diode model into a 90 nm PDK available from MOSIS.

This is the first in-depth analysis of TSRAMs taking into account process variations including transistor threshold voltage variance and transistor mismatch and tunnel diode spacer thickness variation across the wafer resulting in peak current and PVCR variation.

With growing mobile devices, low-power operation is given priority over speed and area considerations. Functional robustness is the most critical issue with scaling dimensions, as process variations become exceedingly dominant and are also the limiting factor for voltage scaling. Finally, a platform for inserting tunnel diode models into a standard EDA tool like Cadence is developed, to facilitate VLSI design.

The primary advantage of TSRAM over SRAM is its robustness to voltage scaling which is essential for reducing active power and maintaining compatibility with logic. In comparison to embedded DRAM, TSRAM does not require fabrication of a large external capacitor, can achieve high-speed operation due to the small storage node capacitance charge/discharge time as well as does not require periodic refresh cycles.

The choice of tunnel diode peak current and PVCR provide a speed/power tradeoff with a higher peak current needed for high speed operation which requires a higher PVCR to keep the standby power consumption low. For the technology node simulated, a 0.5ns write access time, 1 ns read access time is obtained with a standby

93 power consumption of 6×10-5 mW/cell and a dynamic power consumption of 1.8×10-7 mW/MHz per cell. Robustness to process variations has been shown upto ±6σ for the write operation and ±3σ for read operation. For high yield on larger memory array’s a larger read access time and a more judicious choice of precharge and sense amplifier voltage are required. Differential sensing should also be investigated. This study can be further extended to other NDR devices that can be integrated with CMOS technology.

CHAPTER 5 SI/SIGE HETEROSTRUCTURE AND DELTA DOPING

Silicon has been the mainstay for large scale integration, and over the last three decades, rapid scaling following the Moore's law, led to transistor gate lengths shrinking down to 130 nm. However, silicon being elemental in nature, could not exploit the benefits of band gap engineering common in compound semiconductors which had resulted in interesting devices based on semiconductor heterostructures. These include, tunneling devices, high-speed heterojunction bipolar transistors (HBT), modulation doped field effect transistors (MODFET) and optoelectronic devices. Germanium, being miscible with silicon over the entire compositional range, presented an exciting prospect to break this barrier and investigation into Si/SiGe heterostructures ensued. The strain in

Si/SiGe system also benefitted the traditional CMOS technology in terms of improved mobility, and SiGe was first introduced into VLSI production at the 90 nm technology node. The lower bandgap of SiGe is advantageous in tunneling devices as it reduces the tunneling barrier height, hence increasing the tunneling probability. This property is exploited in the development of Si/SiGe resonant interband tunnel diodes (RITDs) as will be elaborated upon in chapter 6. In this chapter an overview of the Si/SiGe material system is presented. Molecular beam epitaxy (MBE) and chemical vapor deposition

(CVD) are the two prominent epitaxial growth methods to form such structures. Both these techniques will be briefly discusses. Finally, another critical factor in the development of RITDs is the use of delta doping to create p and n quantum wells with

95 discrete energy levels and a resonant tunneling like effect in an interband structure as detailed in chapter 2. The realization of such highly doped regions using both MBE and

CVD will be discussed.

5.1 Si/SiGe Heterostructure - Strain and Critical Thickness

Germanium has an atomic spacing 4.2% larger than that of silicon. When grown on top of silicon, the first few layers of germanium accommodate the mismatch by modifying the in-plane lattice constant to match that of silicon. This results in a tetragonal distortion in the growth direction and an in-plane biaxial compressive strain is generated. As the thickness of germanium increases, so does the strain energy, and after a

96 certain thickness, known as the critical thickness, it becomes energetically more favorable to allow the strain to relax through the formation of misfit dislocations (Fig.

5.1). It is more desirable from a device perspective to stay within the regime of a strained epitaxial layer and avoid dislocation formation. The use of Si1-xGex alloy instead of pure germanium increases the critical thickness as the germanium content is reduced. The lattice constant for bulk SiGe can be calculated by Vegard's law

(nm) (5.1)

A more accurate equation is given by:

(nm) [76], [77] (5.2)

Strained SiGe (pseudomorphic) on silicon has in-plane and perpendicular lattice constant given by:

and (5.3) (5.3) where, [78] and

The equilibrium critical thickness is calculated by minimizing the sum of the dislocation energies and strain and allowing the spacing between dislocations to go to infinity. From the equilibrium theory the critical thickness is given by:

[79] (5.4)

Here, b is the Burgers vector, is the angle between the dislocation line and the Burgers vector, , q is the core cut-off parameter and is taken as equal to b, and is the core-energy parameter.

For the Si/Si1-xGex system the equation reduces to

[80] (nm) (5.5)

Figure 5.2 shows a comparison of theoretical and experimental critical thickness values for various compositons of SiGe.

Figure 5.2 Critical thickness of SiGe epilayers grown on Si substrate. comparison of data from Matthews-Blakeslee calculation, as calculated by Jain [175], experimental results by Bean [87] and Houghton [173]

5.2 Electrical Properties of Si/SiGe Heterostructures

An important outcome of the strain and tetragonal distortion in pseudomorphic

Si1-xGex grown on silicon or relaxed Si1-yGey, is the modification of the band structure.

Both silicon and germanium are indirect bandgap materials. The valence band in both cases is at k=0 and consists of degenerate light hole (LH) and heavy-hole (HH) bands with a split-off (SO) band at a lower energy. However, the conduction band minima in germanium occurs at the L-point of the Brillouin zone with eight equivalent valleys while the silicon conduction band minima is along the Δ-direction, at 0.85 of the X-point with 98 six equivalent minima. Unstrained (100) Si1-xGex shows an abrupt change between the silicon like Δ conduction band minima to the germanium like L conduction band minima at x=0.85. The experimentally observed bandgap can be fit to the following expression:

for 0 < x < 0.85 (5.6) and for 0.85 < x < 1 (5.7)

Strain results in lowering of symmetry from cubic to tetragonal. This causes a splitting of the band edges and modification of the bandgap. Biaxial strain consists of two components: hydrostatic strain, due to the change in volume of the material and uniaxial strain in the growth direction. The hydrostatic component results in an energy band shift and a change in bandgap while the uniaxial component causes a splitting in the conduction and valence band degeneracy.

The conduction band of Si1-xGex is Si-like till x = 0 and becomes Ge-like for higher x. Since, lower Ge contents are used practically, a Si-like conduction band structure is assumed here. Strain results in the six fold degenerate Δ6 conduction band splitting into a set of twofold Δ2 and fourfold Δ4 degenerate valleys. For a biaxial tensile stress (e.g. Strained Si grown on relaxed SiGe), the Δ2 valleys are preferentially occupied while for a compressive stress (e.g. Strained SiGe grown on Si substrate) the Δ4 valley have lower energy and the electrons transfer into them. The constant energy surfaces are ellipsoids as shown in Fig. 5.3(a), hence the effective mass is anisotropic. The longitudinal (ml) and transverse (mt) effective masses for silicon are 0.98m0 and 0.19m0.

With a 6 fold degeneracy, the average conductivity mass is given by

. Lifting of degeneracy due to strain increases the mobility by reducing the

intervalley scattering. Further, biaxial tensile stress is beneficial for in-plane conduction, e.g. in MOS transistors, since the Δ2 valleys are populated which have an effective mass mt in plane. A 30% mobility enhancement was experimentally obtained by Cheng et al.

[81] by fabricating MOSFETs with Si channel on Si0.75Ge0.25-on-insulator substrate.

(a) (b)

Biaxial compressive stress Biaxial tensile stress

(c) (d) Figure 5.3 (a) Conduction band constant energy surfaces for silicon showing the Δ6 degenerate valleys and preferential filling of the Δ2 valley for a biaxial tensile stress (b) Energy bandgap difference Eg(SiGe) - Eg(Si) showing bandgap reduction in strained SiGe compared to unstrained SiGe [85] and schematic illustration of the effect of (c) compressive and (d) tensile biaxial stress on Si energy bands [176]

100

(a) (b)

(c) (d) Figure 5.4 Effect of strain and alloying on the valence band (a) unstrained Si (b) compressively strained Si (c) unstrained Si0.6Ge0.4 (d) compressively strained Si0.6Ge0.4 [180]

Strain has a significant effect on the valence band, resulting in a change in effective mass and mobility. The reduced symmetry again leads to a reduction in energy.

The degeneracy of the light hole and heavy hole valence bands is also lifted by unixial stress. Effect of strain and alloying is shown in Fig. 5.4. In unstrained Si and Ge the valence band maxima consists of a degenerate heavy hole (HH) , light hole (LH) and split off (SO) bands. The split off band in Si is only 44 meV below the top of the valence band, presenting intervalley scattering opportunities and poor hole mobility. Ge SO band energy separation is 0.29 eV. Thus, the first benefit of forming a SiGe alloy is reduction in scattering into the SO band due to increased energy separation as can be observed by comparing Fig. 5.4(a) for unstrained Si and Fig. 5.4(c) for unstrained SiGe. Additionally,

101 uniaxial stress lifts the LH and HH degeneracy and further increases the split off band separation (Fig. 5.4(b), (d)). The valence band also becomes anisotropic between the growth direction versus in-plane, perpendicular to the growth direction (Fig. 5.5).

Compression in the plane results in the effective mass being higher in the growth direction and lower in plane. Biaxial tensile stress reduces the effective mass in the growth direction and increases it in-plane.

LH SO

(a) (b) (c) Figure 5.5 Schematic of the valence band structure for (a) unstrained direct-bandgap semiconductor (b) under biaxial tension (c) under biaxial compression. denotes in-plane and is perpendicular to plane, in the direction of growth [181]

Figure 5.3(b) shows the net effect on bandgap between strained and unstrained

SiGe. Van de Walle and Martin [82] and People [83] calculated the splitting of band edges for strained layers while Lang et al. [84] and King et al. [85] determined this experimentally for MBE-grown layers. It should be noted that the degeneracy of the L band is not lifted by tetragonal distortion.

102

(a) (b) Figure 5.6 Band alignment for (a) strained SiGe on Si substrate and (b) strained Si on SiGe substrate [78]

Band alignment for strained SiGe on Si and strained Si on relaxed SiGe are illustrated in Fig. 5.6. For compressively strained SiGe on Si the conduction band offset is very small and the majority of offset is in the valence band [86] and is suitable only as a p-type heterostructure device utilizing the valence band offset. Figure 5.7(a) and (b) shows the conduction and valence band discontinuities for strained Si1-xGex grown on relaxed Si1-yGey substrates for all compositions. Tensile strained Si on SiGe however can be used for n-type heterostructure devices. The calculated conduction and valence band offsets are shown in Fig. 5.7(c) and (d).

103

(a) (b)

(c) (d) Figure 5.7 (a) conduction and (b) valence band offsets for strained SiGe on relaxed SiGe and (c) conduction and (d) valence band offsets for strained Si on relaxed SiGe [78]

104

5.3 Epitaxial Growth

Epitaxy is the growth of a single-crystal film on top of a crystalline substrate. It is categorized into homoepitaxy and heteroepitaxy depending on whether the film and substrate are the same material or different materials. The two most popular techniques for epitaxial growth are molecular beam epitaxy (MBE) and chemical vapor deposition

(CVD). Both these techniques are vapor phase i.e. the constituent atoms or molecules of the material being grown are supplied in vapor phase and a phase transformation from vapor to solid phase occurs resulting in formation of a film with the desired composition and structure. The basic processes involved during film growth are [Fig. 5.8(a)]:

1. Adsorption: reactants impinging on the substrate, interact with the substrate surface.

Depending on the strength of the atomic interaction, the process can be classified as

physiosorption or chemisorption. In physiosorption, the molecules bond to the surface

with weak van der Waals forces while in chemisorption a stronger ionic or covalent

bonding occurs. The critical condition to facilitate adsorption is a reduction in energy

of the adsorbing species on the surface below their vapor phase energy, preventing

their escape.

2. Surface diffusion: The adsorbed atoms (adatoms) can diffuse across the surface if it

has enough energy, primarily determined by the substrate temperature. This is very

critical for crystalline growth. Too low temperatures result in amorphous film

formation.

3. Nucleation and Growth: The adatoms interact with one another to form clusters as

shown in Fig. 5.8(b). Nucleation occurs so as to minimize the free energy. If the

105

adatoms do not stick well to one another or do not stick to the substrate and are

desorbed more rapidly, formation of clusters and hence nucleation is slow.

4. Desorption of by-products and un-reacted material. Desorption of reactant species is

undesirable and for film growth the rate of adsorption should be faster than

desorption. However, in chemical vapor deposition, desorption of the byproducts of

the surface reaction is essential or it could inhibit film growth.

(a) (b)

Figure 5.8 (a) Basic processes in vapor-phase growth (b) formation of a cluster [177]

5.3.1 Molecular Beam Epitaxy

Molecular beam epitaxy (MBE) involves highly controlled evaporation in an ultra high vacuum (~10-10 torr) system. Ultra high vacuum (UHV) in the growth chamber is maintained through a cascade of vacuum pumps e.g. a sublimation pump, a turbo- molecular pump and a oil-free roughing pump. MBE is a far from equilibrium growth technique and is dominated by the kinetics of the surface processes. The constituent elements of the material being grown are heated in separate effusion cells or electron

106

beam guns (for high melting point materials such as Si and Ge) until they begin to

evaporate. The cell has a small opening from which the evaporated material escapes. The

flux from multiple sources (constituent elements or dopants) arrive at the substrate at the

same time. The final composition of the layer depends on the ratio of the fluxes and the

substrate temperature. Since the chamber is maintained under ultra high vacuum

conditions, the mean free path of the molecules in the beam is larger than the distance

between the effusion cell and the substrate resulting in a molecular flow regime. The

molecules travel line of sight and do not diffuse, preventing any interaction between the

(a) (b) Figure 5.9 Schematic of (a) SiGe MBE system and (b) Si electron-beam gun [78] QMS: qaudropole mass spectrometer for monitoring flux, RGA: residual gas analyzer, RHEED: reglection high-energy electron diffraction

constituent elements in the vapor phase. The substrate is mounted on a heated holder that

can rotate at a fixed rate to improve growth uniformity. The substrate temperature is

critical to provide enough thermal energy for the adatoms to diffuse until it arrives at a

step edge. The flux composition can be changed by abruptly opening and closing

107

mechanical shutters attached to the effusion cells. Figure 5.9 is a schematic view of the

growth chamber and the silicon electron beam evaporator gun.

Bean et al. [87] showed that planar growth of SiGe on Si requires lowering the

growth temperatures. Due to large interfacial energies between Ge and Si, the only way

to avoid islanding was to limit the surface atomic migration length. Growing higher

content Ge requires further reduction in temperature (Fig. 5.10) to attain sharp interfaces.

An added complication is due to Ge segregation to the surface through Si. This can also

be suppressed by lowering the growth temperature [88]. Since MBE is a physical

deposition process, the deposition rate and substrate temperature can be controlled

independently. Hence, it is well-suited for such low temperature growth compared to

other epitaxial growth techniques such as CVD.

Figure 5.10 Si1-xGex film morphology vs growth temperature [87]

108

5.3.2 Chemical Vapor Deposition (CVD)

Chemical vapor deposition is also a vapor phase epitaxy technique but in this case the constituent gases react in vapor phase on the surface of the substrate to form a solid.

The reaction also results in by-product formation which are desorbed and pumped out. A schematic showing the steps in a CVD process is shown in Fig. 5.11. The steps involved are: (a) mass transport of reactant gases to the reaction chamber, (b) diffusion of reactants through the boundary layer to the wafer surface, (c) reactants adsorbed onto surface followed by chemical decomposition and reactions on the surface to produce new species and by-products, (d) surface diffusion and nucleation, (e) desorption of volatile by- products and transport of by-products away from the deposition region.

Figure 5.11 Schematic of steps involved in a CVD growth [78]

The growth rate limiting steps are: the rate of arrival of reactants, the surface reaction and rate of removal of by-products. Pressure controls the thickness of the boundary layer and hence the rate limiting step. At low pressure, the boundary layer thickness is less, hence the diffusion process is minimized and surface kinetics is the rate limiting step. In typical systems, the process is optimized such that the arrival rate of

109 reactants controls the growth rate. The quality of the crystal grown depends on the substrate surface quality, arrival rate of the reactants relative to surface diffusion and crystal orientation. For growth in the diffusion limited regime, the temperature should be high enough so that the rate of arrival is commensurate to the surface diffusion rate.

A large variety of CVD reactor configurations exist such as horizontal, vertical, barrel, pancake and multi-wafer-in-tube LPCVD. The horizontal and vertical are the most common for atmospheric and reduced pressure growths. Further, reactors can be hot-wall or cold-walled. Hot-wall reactors are used for exothermic processes where the high wall temperature avoids deposition on reactor walls. Cold-wall reactors are used for endothermic processes such as deposition of silicon. A schematic of a simple horizontal flow, cold wall CVD reactor is shown in Fig. 5.12. In this work, a horizontal cold-wall atmospheric/reduced pressure CVD has been used and will be detailed below.

Figure 5.12 Schematic of a horizontal cold-wall CVD reactor

110

(a) (b) Figure 5.13 Process adjustments for correcting thickness variations in (a) front half and (b) back half of horizontal reactor [178]

Atmospheric pressure CVD (APCVD) is the most widely used system for silicon epitaxy. In this a gaseous silicon bearing species flows in at atmospheric pressure. The silicon wafer is placed on an inductively or radiatively heated susceptor. Uniformity of deposition is enhanced by rotation of the substrate. Significant unintentional doping was an issue in earlier systems. This was due to diffusion of dopants upwards from highly doped regions of the substrate and reincorporation of dopants evaporated from the surface. This is known as autodoping. Two methods were found to be effective in reducing this; lowering the growth temperature and reducing the process pressure to increase diffusion of dopants away from the growth interface. The former also led to increased defects hence the later was more suited. This led to a modification known as the reduced pressure CVD (RPCVD). This uses a pumping system to maintain a pressure of about 10 torr. Uniformity of thickness is controlled by dopant concentration and local temperature. Figure 5.13 illustrates possible thickness profiles (t) in a horizontal reactor

111 and possible corrective actions in terms of tilt angle, gas flow rate and temperature profile.

Silicon epitaxy was commonly done at high temperatures of around 1000oC using chlorinated compounds of silicon. The high temperature allowed oxygen desorption, the use of H2 also provided surface passivation. The reactions and temperatures with different precursors are [89]:

o SiCl4 + 2H2 → Si +4HCl (1150-1200 C)

o SiCl3H + H2 → Si + 3HCl (1080-1130 C)

o SiCl2H2 → Si + 2HCl (1030-1070 C) (pyrolysis in H2 atmosphere on wafer substrate)

With increased scaling, the issues of autodoping and interdiffusion became more acute and methods to reduce deposition temperature, while maintaining a high enough growth rate, to reduce the overall thermal budget were investigated. Lowering growth temperature in the 500 - 750oC range also enables growth of metastable layers of strained

SiGe in addition to sharper doping profiles. The use of load-locked systems with moisture and oxygen monitoring helped reduce water vapor and oxygen concentrations in the reactor chamber in APCVD systems. A change of precursors helped improve the growth rate at lower temperatures. Replacing chlorine with hydrogen in the precursor

(using silane, SiH4) and increasing the silane order from silane (SiH4) to disilane (Si2 H6) and trisilane (Si3H8) [90], [91] was found to increase the growth rate. Silane adsorbs dissociatively, consuming two active sites (2SiH4 + 2* → 2H* + 2SiH3). The SiHx fragments are subsequently dehydrogenated until a Si adatom is incorporated along with

H2 desporption. At low temperature the growth rate is controlled by the hydrogen atoms

112 present on the surface as a result of silane decomposition. A method to further increase growth rate at low temperature is the use of nitrogen as carrier gas instead of hydrogen, reducing the hydrogen partial pressure and enhancing hydrogen desorption and silane adsorption [92]. The use of silane however is problematic for high n doping levels. This is due to the preferentially dissociative adsorption of the group V hydrides, preventing the adsorption of silane and reducing the growth rate. The use of dichlorosilane precursor is preferable for high n doping at low temperatures [93].

In order to grow SiGe, germane (GeH4) is added to SiH4 or Si3H8 [94]. Germane is chemically similar to silane. Addition of GeH4 increases the growth rate [95] which is fortuitous since it allows further lowering of growth temperature. Ge segregation is reduced in APCVD due to surface hydrogen [96].

5.4 Delta Doping

Figure 5.14 Potential energy for a 1014 cm-2 boron δ-doping [179]

Delta (δ) doping is the fabrication of extremely narrow well-defined doping profiles. This results in high density two dimensional electron or hole gas in a V-shaped

113 quantum well. Reduction in spatial dimensions of dopant distribution has significant applications in electronic and optoelectronic devices [97], [98], [99], [100], [101]. In this work, δ-doping is used to form p and n quantum well structures which are key in the realization of resonant interband tunneling.

Since the dopant profile varies abruptly over a short distance, the free carrier distribution does not follow the doping profile but is more spread out. The wave function and energy levels in the quantum well formed as a result can be determined by solution of the coupled Poisson-Schrodinger equation. Figure 5.14 shows the calculated energy levels in a δ-doped potential well formed by a 1/10 monolayer boron sheet.

5.4.1 Growth Issues

δ-doping requires a large concentration of dopant atoms (upto 1014 cm-2) confined in a few atomic layers. A true δ-doping plane should have a full width at half maximum

(FWHM) of less than 2.5 nm. The key challenge in achieving this is the suppression of

(a) diffusion and (b) segregation. Both result in a redistribution of doping atoms particularly at growth temperature. Since both processes are kinetically mediated, lowering the growth temperature is essential.

5.4.1.1 Diffusion

Diffusion of dopants in silicon is mediated by point defects (vacancy or intersititals). Boron diffuse primarily through an interstitial type (I-type) mechanism whereas phosphorus, antimony and arsenic diffuse through a vacancy type (V-type) mechanism. Dopant diffusivity is proportional to the concentration of a particular point defect such as Si-self interstitials in the case of B and Si vacancies in the case of Sb.

114

Point defects can exist in various charge states, i. For a substitutional donor atom (P and

As) A(+1) and a negatively charged point defect, X(i-1):

A(+1) + X(i-1) → AXi similarly, for an acceptor atom (B), A(-1) + X(i+1) → AXi

From Fick's law, the total flux, summed over all charge states:

(5.8) where, is the proportionality constant, known as diffusivity and is the concentration of the dopant-impurity complex for a specific charge state.

The concentration of defects in various charge states can be taken to be proportional to

the ratio of where, N is the concentration of dopant atoms, is the intrinsic

carrier concentration and is the charge state where the (-) sign applies for n-type materials and (+) sign for p-type materials. The total diffusion coefficient from the vacancy model is then given by [102]:

(5.9)

where, the diffusivity for each pair is given by the Arrhenius form:

and, is the activation energy

For high dopant concentration, the resultant electric field enhances the movement of the impurity and

115 where, is the field enhancement factor and is 1 for N << ni and 2 for N >> ni and the diffusion coefficient becomes:

Typical activation energy and pre-exponential values are various dopants in Si are given in Table 5.1 [103]:

Table 5.1 Prefactor and activation energy in eV for bulk diffusion in Silicon [103]

Dopant B 0.037 3.46 0.76 3.46 Ga 0.374 3.39 28.5 3.92 Al 1.385 3.41 2480 4.2 In 0.785 3.63 415 4.28 P 3.85 3.66 4.44 4 44.2 4.37 As 0.066 3.44 12 4.05 Sb 0.214 3.65 15 4.08

The key to diffusion suppression is reduction in the thermal budget of the process. The characteristic diffusion length L is given by:

where, D is the diffusion constant of the dopant species and is the time the system is held at the elevated temperature. Thus, reduction of D or helps in minimizing diffusion.

5.4.1.2 Segregation

At typical growth temperatures of greater than 400oC surface segregation and low incorporation probabilities of dopants is observed for all common dopants (Sb, Ga, In, B) employed in Si MBE. The surface temperatures required to suppress segregation can be

116 too low for high quality epitaxy. Segregation can be observed by a tail in the dopant concentration-depth profile. Surface segregation could take place as a result of reduction in enthalpy of the system [104]. Columbic repulsion is another cause of segregation at very high concentration δ-doping where the dopant atoms are a few interatomic distance away from each other [105]. The columbic field of the charged dopants causes the atoms to repel each other. Fermi level pinning also adds to surface segregation. A charge flow to the empty surface states causes build up of a space charge of ionized donors. Thus, an internal field is setup that leads to drift of dopant atoms towards the surface [106].

The dopant segregation ratio is given by [107]:

(5.10)

where, is the dopant surface coverage, is the areal density of a

14 -2 monolayer of Si(100) = 6.78×10 cm , is the dopant concentration and is the atomic density of Si = 5×1022 cm-3.

If all the atoms are incorporated and none segregate, the relative surface

concentration is the same as bulk concentration, = and . If the dopant

atoms segregate, and .

5.4.2 δ -doping with Low Temperature MBE (LT-MBE)

LT-MBE is epitaxial growth at temperatures low enough to suppress dopant segregation. Conventional temperature measurement techniques such as infrared pyrometry and thermocouple measurements cannot be used and laser-interferometry is

117 preferred instead. A δ-doping plane is obtained by stopping epitaxial growth and only allowing the dopant flux to impinge on the semiconductor surface. After this the epitaxial growth is resumed. Figure 5.15 shows results from the deposition of a monolayer of Sb on a Si surface at various substrate temperatures followed by 500-800 nm Si overlayers at a growth rate of 0.1 nm/s [108]. Finally a 100 nm Si cap was deposited at 50oC to trap Sb remaining on the surface. The secondary ion mass spectroscopy (SIMS) profile for various temperatures is shown in Fig. 5.15(a). Segregation is observed as an asymmetric broadening of the dopant profile which becomes more severe with higher growth temperatures. The segregation ratio for low doping (NSb,surf < 0.1 ML) as a function of growth temperature (Fig. 5.15(b)) shows a sharp drop in segregation as temperature is lowered below 550oC. Theoretical results from the two-state exchange model [109] are also shown for comparison.

(a) (b) Figure 5.15 (a) SIMS profile showing segregation at various growth temperatures of 1 ML Sb on Si(100) surface (b) segregation ratio in the dilute concentration regime as a function of growth temperature [108]

118

A similar study was done for Phosphorus [110]. P has a higher solid solubility limit than Sb and hence can permit higher δ-doping concentrations. A P δ-doping spike was deposited with a sheet concentration of 1.2×1014 cm-2 on a Si substrate, at various growth temperatures. this was followed by a undoped Si cap deposition. Figure 5.16 shows the SIMS profile and segregation ratio's. Again, it is clear that low temperature growth at 380oC helps in suppression of segregation.

(a) (b) Figure 5.16 (a) SIMS profile for P δ-doping at various growth temperatures showing segregation suppression at low temperature and (b) corresponding segregation ratio's [110]

5.4.3 Vapor Phase Doping - δ-doping with CVD

Doping in CVD is done by the addition of dopant gases such as AsH3, PH3 and

B2H6. The abruptness of the doping profile is determined by the gas switching system and incorporation kinetics of the dopant species. Boron incorporation requires two active sites: B2H6 + 2* → 2BH3* followed by: BH3* → B* + 3H*. Meyerson et al. [111] 119

showed low-temperature (550oC) boron-doping using CVD with a linear boron

incorporation with gas concentration. In this experiment, the silane flow rate was fixed

and the B dopant flow rate was increased. Fully activated dopants with dopant level up to

20 -3 1.5×10 cm were reported. Adsorption of PH3 molecule on the other hand requires 4

surface atom sites PH3 + 4* → P* + 3H*. Desorption of P can occur at temperatures

higher than 550oC. As mentioned earlier, n-doping can reduce the growth rate when using

silane precursor due to preferential dissociative adsorption.

(a)

(b) Figure 5.17 SIMS profile and dose deposited for various growth temperatures of (a) Phosphorus and (b) Arsenic vapor phase doping using APCVD [112]

120

Vapor phase doping (VPD) is a technique to obtain δ-doping profiles with CVD.

In the case of VPD, the silane flow is stopped and only the dopant gas precursor flows, forming a sheet of dopant atoms deposited on the substrate surface through decomposition of the precursors. In a study of vapor phase doping of n-type dopants phosphorus and arsenic using APCVD, it was found that both exhibit self-limiting behavior on the silicon surface, similar to atomic layer deposition technique [112]. At

o temperatures below 450 C, hydrogen passivation of the Si surface prevents PH3 adsorption. This is improved with the use of N2 as a carrier gas instead, but the dose still

o remains low. However, at 600 C with N2 as a carrier gas, a 0.8ML coverage is achieved.

A self-limited deposition of 1ML is also obtained for AsH3 with N2 as a carrier gas.

Growth rate of silicon capping layer on top of the VPD layer shows significant reduction, which is attributed to autodoping from residual precursors in the chamber and dopant segregation.

(a) (b) Figure 5.18 SIMS profile for vapor phase doping of boron for formation of ultra shallow junctions. Sub-melt laser annealing is used for electrical activation. Drive in after anneal at (a) 1300oC and (b) 1220oC are shown [113]. 121

Increase in Si growth temperature reduces this but also reduces the P dose, and is considered to be due to desorption of P and As between 550oC-600oC. The dose with cap layer is also much lower than without the cap. Figure 5.17 shows the SIMS profile and dose with cap layer for P and As. Arsenic shows more segregation than P. A study of boron-VPD for ultra shallow junctions, conducted at 500oC and reduced pressure using

B2H6 with N2 as carrier gas also shows sharp dopant profiles (Fig. 5.18) [113].

5.5 Conclusion

This chapter provides a review of two important techniques to realize high tunneling currents in a silicon-based material system. Addition of SiGe reduces the bandgap and improves tunneling current. Issues with growth of SiGe material system and the important electronic properties of this system are discussed. MBE and CVD are two popular epitaxial techniques that can be used to grow tunneling devices. However, to obtain abrupt dopant junctions, as required for high tunneling currents, the use of low temperature processes along with δ-doping is essential and δ-doping using both these growth techniques is discussed.

122

CHAPTER 6 SI/SIGE RESONANT INTERBAND TUNNEL DIODE

Quantum mechanical tunneling based negative differential resistance devices are high speed devices that can be used to realize logic and memory circuits with fewer device components as detailed earlier in chapters 3 and 4. A major hurdle however has been the development of a manufacturable process that can be easily integrated into a standard CMOS process line. The development of Si/SiGe resonant interband tunnel diodes (RITD) helped overcome this shortcoming. Room temperature negative differential resistance along with current densities, which can be tailored to the application by varying the tunneling barrier thickness, has made these devices very promising, in the quest for extending functional scaling beyond the current CMOS technology. Prior development was limited to the use of molecular beam epitaxy (MBE), which provides the unique advantage of low temperature non-equilibrium growth modes, critical for forming the sharp highly doped profiles required in tunneling junctions.

However, translation into a standard CMOS process line requires high throughput growth methods such as chemical vapor deposition (CVD). In this chapter, Si/SiGe RITDs grown by CVD are addressed and optimizations to obtain record high peak to valley current ratio's are detailed.

123

6.1 Structure of Si/SiGe Resonant Interband Tunnel Diode

Figure 6.1(a) shows the basic structure of the Si/SiGe RITD and its calculated band diagram is shown in Fig. 6.1(b). It consists of n-type and p-type δ-doped layers which serve as quantum wells with a Si/SiGe tunneling barrier sandwiched in-between.

The SiGe with its lower bandgap serves to increase the tunneling probability. However, its thickness is limited by the critical thickness and hence thicker barriers require a composite Si/SiGe barrier. SiGe below the boron δ-doping layer acts as a diffusion barrier suppressing out-diffusion of boron. The operating principle is illustrated in Fig.

25 nm n+ Si

P δ-doping x nm undoped Si

y nm undoped Si0.6Ge0.4 B δ-doping

1 nm p+ Si0.6Ge0.4 100 nm p+ Si p+ Si Substrate (a) (b) Figure 6.1 (a) Basic structure of a Si/SiGe resonant interband tunnel diode with a (x+y) nm tunneling barrier and (b) the calculated band diagram for a 6 nm tunneling barrier

6.2. The quantum wells formed by the δ-doping layers result in quantization of energy levels. As the forward bias is increased, the energy levels in the two wells align resulting in resonant tunneling through the Si/SiGe barrier. Further increase in bias results in the

124 quantized energy levels now seeing the forbidden bandgap, preventing further tunneling and the current reduces. However due to defect levels within the bandgap defect assisted tunneling results in an excess current component. Further increase in forward bias results in reduction of the thermal barrier to diffusion and diffusion current akin to a regular pn junction flows.

6.2 Prior work using LT-MBE

The first report of Si/SiGe RITD was made by Rommel et al. [5] which exhibited a peak current density of 3.2 kA/cm2 and a PVCR of 1.54. The key features of this design were (1) intrinsic tunneling barrier which reduces carrier scattering (2) use of δ-doping injectors provides highly degenerate doping levels forming quantum wells (3) use of low- temperature molecular beam epitaxy to allow greater dopant incorporation and abrupt interfaces minimizing segregation and diffusion (4) short post growth rapid thermal

n δ-doping EC EC EC EC

EV EV EV EV

p δ-doping Tunneling Excess Thermal diffusion I I Current I Current I Current

V V V V Figure 6.2 Operating principle of a Si/SiGe RITD

125 annealing heat treatment to reduce point defect density associated with low temperature growth. Back-to-back diodes with a p-on-n structure grown on top of the n-on-p structure were also developed to obtain symmetric NDR regions in forward and reverse bias [114].

Due to the n-dopant segregation an issue, design of p-on-n is more challenging due to dopant incorporation into the tunneling spacer. Here the low temperature (320oC) growth of the Sb δ-doping layer was followed by a silicon spacer also grown at 320oC. The substrate temperature was then elevated to 550oC. From SIMS measurement the actual tunnel barrier for an 8 nm total Si spacer was 6 nm. The use of SiGe cladding layer around the B δ-doping further suppresses the boron out-diffusion improving the PVCR to

3.6 with peak current density of 0.3 kA/cm2 [115]. Stacked RITDs for multivalue logic were also developed [56]. Monolithic integration of RITDs with NMOS for memory application [63] and HBT for wireless applications [116] were demonstrated. Record high current densities of 218 kA/cm2 were achieved using 2.5 nm barrier thickness, which are useful for RF applications. Hydrogen passivation of the sidewall using an HBr dry etching chemistry instead of the conventional wet etching improved the PVCR upto 4.02

[117]. The use of Si0.8Ge0.2 virtual substrate allowed further increase in the Ge content in the tunneling barrier to Si0.4Ge0.6 and the ability to include tensilely strained Si cladding around the P δ-doping to deepen the δ-doping plane [118]. This was extended by adding tensilely strained Si 'outside' barriers to the B δ-doping plane and SiGe barrier to the P δ- doping to further deepen the quantum wells, block the nonresonant tunneling currents and improve the PVCR [119]. However the large surface roughness of the SiGe substrates resulted in inferior performance to conventional Si substrates.

126

6.3 Device fabrication using CVD

The epitaxial growth of RITDs using CVD is accomplished using a standard horizontal cold wall load-locked ASM Epsilon 2000 reactor with variable pressure ranging from atmospheric pressure (AP) to reduced pressure (RP). Si/SiGe RITDs were grown on a 200 mm diameter boron-doped Si substrate. Growth is initiated with a 100

o nm p+ Si buffer layer deposited at 650 C under RP using silane (SiH4) and intentionally

19 -3 doped at a nominal level of 5×10 cm using diborane (B2H6). The substrate temperature

o is then reduced to 575 C and a 1 nm Si0.6Ge0.4 boron diffusion barrier layer is grown, followed by a sheet of boron (at least 5×1013 cm-2) at AP. The undoped composite

Si0.6Ge0.4/Si tunneling spacer comprising is deposited at RP using silane (SiH4) and

13 -2 o germane (GeH4). Finally a phosphorus spike (at least 5×10 cm ) is grown at 600 C and a n+ cap layer is deposited at 675oC using dichlorosilane. As discussed earlier in section

5.3, dichlorosilane is preferred over silane for obtaining high n doping at low temperatures. Vapor phase doping technique is utilized to achieve the p and n δ-doping spike, wherein the dopant atoms are deposited on the wafer by thermal decomposition of diborane (B2H6) and phosphine (PH3) [112], [113], respectively as discussed in section

5.4.3. Nitrogen is used as carrier gas for the δ-doping spike.

For device fabrication the samples were cleaned in acetone, IPA followed by a dehydration bake. A first lithography step defines a series of dots with diameters of 10,

15, 30, 40, 50, and 75 µm followed by liftoff of Ti/Au (15/100 nm). Mesa isolation was performed using a self-aligned wet etch using HF/HNO3/H2O (2:100:100) solution.

127

Finally a second lithography step defines the anode and Pt/Au (15/100nm) was electron-

beam evaporated to form the anode ohmic contact.

6.4 Boron flow rate optimization

In this study, the boron flow rate for the δ-doping spike is varied and its effect on

(a) (b)

(e) Figure 6.3 SIMS profile for samples A through D with boron flow of (a) 6 × baseline (b) 4 × baseline (c) 2 × baseline and (d) baseline flow (e) comparison of boron SIMS profile for the 4 samples 128 the peak current density and PVCR is investigated. Figure 6.3 shows the secondary ion mass spectroscopy (SIMS) analysis of four wafers. An oxygen beam is used for measuring boron concentrations while a cesium beam is used for phosphorous concentration. An impact energy of 250 eV is selected for both the beams to reduce knock-on effects. The boron concentration is calculated in a Si0.7Ge0.3 matrix while phosphorus was calculated assuming a silicon matrix.

The boron peak doping is found to reduce as the boron flow rate is reduced with peak values of 5× 1021 cm-3, 2.9×1021 cm-3, 1.1×1021 cm-3 and 4.4×1020 cm-3 for flow rates of 6× (sample A), 4× (sample B), 2× (sample C) and baseline flow (sample D), respectively. The phosphorus limit remained unchanged for the four samples. In Fig.

6.3(e) the SIMS profiles are overlaid on top of each other for comparison.

Room temperature I-V characteristics measured at different locations for the as- grown samples are shown in Fig. 6.4. Prior studies have shown that post growth anneal leads to deterioration of performance and hence is not conducted. This is unlike MBE grown samples where post growth anneal is essential to reduce point defects and improve the PVCR. All measurements presented here are on 18 µm dots and are performed on pieces from the center for the 200 mm wafers. The peak current reduces with an average peak current density of 500, 175, 70, 15 A/cm2, respectively. The PVCR increases from an average value of 1.38 for sample A to 2.24 for sample B and 2.7 for sample C.

However it falls back to 1.3 for sample D. The highest PVCR of 2.95 is observed for sample C.

129

(a) (b)

(c) (d) Figure 6.4 Measured I-V characteristics for samples A through D. The average peak current and PVCR are: (a) 500 A/cm2, 1.38; (b) 175 A/cm2, 2.24; (c) 70 A/cm2, 2.7; and (d) 15 A/cm2, 1.3, respectively. The maximum PVCR of 2.95 is obtained for sample C. The multiple lines in each graph correspond to measurements from various representative diodes in each sample. All measurements presented were performed on 18 µm mesa diameter diodes

Device simulations of the CVD stack were performed using the ATLAS device

simulator (version 5.16.3.R) developed by SILVACO. The device structure model is

shown in Fig. 6.5(a). From the measured SIMS data in Fig. 6.3 it is apparent that the

doping concentration in the δ–doping region is much greater than the solid solubility limit

20 -3 for B in bulk Si0.6Ge0.4, assuming all electrically-active species, which is 2.5×10 cm .

130

The solid solubility limit of phosphorus is 1×1020 cm-3. Hence, the maximum active B doping level is assumed to be capped at 2.5×1020 cm-3 for all the samples in the simulations. There have been recent reports of enhanced boron solubility in compressive biaxially strained silicon [120]. In this structure, the boron δ-doping lies within a thin compressively strained SiGe. However, it is unclear if a similar effect manifests here. In fact, it is known that high boron doping can actually result in strain compensation in SiGe alloys allowing for larger critical thicknesses for a given Ge concentration [121], [122].

The δ-doping plane is modeled as a 1 nm nominal waist thickness and a Gaussian profile.

With the peak doping level fixed, the width of the Gaussian is then tuned in ATLAS to match the measured peak current data obtained experimentally. The corresponding slopes of the resulting Gaussians obtained for samples A to D are 1.4, 1.05, 0.85 and 0.3 nm/decade, respectively [Fig. 6.5(b)]. The corresponding values obtained from the SIMS profile are 1.9 nm/dec, 1.2 nm/dec., 1.2 nm/dec and 0.6 nm/dec, respectively. It is reasonable to expect that the measured SIMS profile will be broader than the actual dopant distribution due to knock-on effects and increasing surface roughness during depth profiling. However, there are several approximations in the tunneling model, the effective mass of electrons and holes used and inaccuracies in the doping density between the experimental and simulated device. Hence, the Gaussian slope fit obtained from simulation cannot be assumed to be quantitatively accurate. It should be noted that the simulated dopant distribution models the electrically active dopants alone while the SIMS data measures both substitutional and interstitial dopant density, regardless of electrical activation.

131

The band diagrams at equilibrium are obtained by self-consistent solutions of

Poisson and Schrödinger equations and are illustrated in Fig. 6.5(c). The large level of

Boron δ-doping results in quantum confinement, whereas no such confinement is

expected for the Phosphorus δ-doping plane obtained here due to its reduced doping

levels . Strain in the Si0.6Ge0.4 layer results in splitting of the heavy and light hole bands.

Three energy levels corresponding to two heavy hole and one light hole band are

100 nm n+ Si(1×1020 cm-3)

20 -3 P δ-doping (peak: 1.5×10 cm )

2 nm undoped Si

4 nm undoped Si 0.6Ge0.4 B δ-doping (variable) 19 -3 1 nm p+ Si0.6Ge0.4 (2×10 cm ) 100 nm p+ Si (2×1019 cm-3) p+ Si Substrate (a) (b)

(c) (d) Figure 6.5 (a) Device structure (b) boron and phosphorus doping (c) band diagram and (d) net electron and hole concentration obtained from device simulation of the Si/SiGe RITD structure using the ATLAS device simulator

132 obtained for samples A and B. The electron and hole concentrations are determined using

Fermi statistics, wave functions and Eigen energy values [Fig. 6.5(d)].

Figure 6.6 shows simulated I-V characteristics obtained using SILVACO for each sample along with a corresponding representative experimental I-V curve overlaid for comparison. The experimental I-V has been corrected for series resistance which includes ohmic contacts, bulk injector resistance and conductance through the substrate. Tunneling current is modeled by SILVACO using a non-local band-to- band tunneling model with a

Wentzel–Kramers–Brillouin (WKB) approximation. However, it does not account fully for indirect bandgap tunneling in Si and Ge where phonon assisted tunneling needs to be considered. The tunneling probability is calculated using a two-band approximation for the evanescent wave vector. The dotted lines in Fig. 6.6 are the resultant of currents due to tunneling and thermal diffusion components combined. However, normally a third current component, called excess current, due to tunneling through defect states within the forbidden gap of the tunneling barrier, is present [31]. In order to model the defect related current appropriately, trap levels were introduced into the band gap of the SiGe region with ATLAS modeling. Trap assisted tunneling is modeled by including field enhancement factors in the Shockley-Read-Hall equation, which is hence incorporated into the recombination term for the carrier continuity equation. The recombination term for donor-like (RD) and acceptor-like (RA) traps is given by:

(6.1)

(6.2)

133

Where,

= electron/hole lifetime

, = electron/hole capture cross section, = thermal velocity

calculated using electron/hole effective mass, = trap density

= degeneracy factor (set to 2 for the simulations)

= Field enhancement factor for electrons/holes

= energy range for which tunneling can occur for electrons /holes

(6.3)

The capture cross section is assumed to be 10-13 cm2 here. The trap density is then varied to fit the valley current obtained experimentally. However, it should be clarified that the capture cross-section and trap density cannot be determined independently and an assumption has to be made for one in order to determine the other. As long as the electron/hole lifetime, which depends on the product of the capture cross-section and the trap density, is constant, the valley current obtained from modeling is the same. For

-14 2 17 -3 example, for sample A, a of 10 cm and of 7×10 cm results in the same

-13 2 16 -3 valley current as determined alternatively with of 10 cm and of 7×10 cm . It should be noted that resonances in the measured NDR region may mask the true PVCR

[123]. Modeling suggests that PVCR of 2.05, 6.2, 7.5, 3.85, for samples A through D, are obtainable, respectively.

134

The effect of trap energy level position on the valley current is shown in Fig.

6.7(a). Doping levels commensurate to sample A are used for this study. The trap density is fixed to 7×1016 cm-3. The trap level is then varied throughout the bandgap and the I-V characteristics plotted in each case. Defects close to the conduction band have the minimum effect on valley current, while midgap acceptor/donor traps exhibit maximum

(a) (b)

(c) (d) Figure 6.6 Representative measured I-V for samples A through D along with simulated I- V with and without inclusion of trap-assisted tunneling showing reduction in peak current and defect density as the boron δ-doping is reduced. The resultant simulated PVCR initially increases and then decreases with values of (a) 2.05 (b) 6.2 (c) 7.5 and (d) 3.85

135 influence on valley current.

It is evident that as the Boron δ-doping is increased, the total trap density required to obtain a reasonable valley current fit to the experimental data increases too. The total trap densities used in the modeling are 7×1016 cm-3, 9×1015 cm-3, 5×1015 cm-3 and 3×1015 cm-3 for samples A to D, respectively. This trend indicates boron interstitials in the SiGe region contributing largely to the trap-assisted tunneling. Boron interstitials being highly reactive tend to form complexes with other impurities in silicon such as oxygen and carbon [124]. Higher doping can also lead to formation of boron clusters and precipitation [125]. Determination of the exact nature of the defect formed will require detailed deep level transient spectroscopy (DLTS) studies.

(a) (b) Figure 6.7 (a) Variation in valley current with location of traps within the SiGe bandgap, illustrating that midgap traps result in maximum valley current. simulator (b) Variation of electric field within the tunneling barrier region for samples A through D. The electric field increases while the effective tunneling distance reduces due to the broadened boron δ-doping profile as boron doping is increased.

136

The increase in peak current with boron δ-doping can be explained by the enhanced boron diffusion with boron concentrations and interstitial boron formation

[126]. From the electric field plot [Fig. 6.7(b)] it is evident that as the Gaussian profile for the δ-doping becomes broader the electric field in the intrinsic region increases and the net tunneling barrier width reduces, both leading to an increase in the tunneling current.

Thus, the boron δ-doping parameter needs to be carefully optimized to achieve high doping while keeping the defect formation to a minimum in order to obtain high peak currents concurrently with high PVCR.

6.5 Use of Arsenic instead of Phosphorus for n doping

o 25 nm n+ Si (SiH2Cl2, AsH3, 675 C)

o As δ-doping (AsH3, 600 C) o 2 nm undoped Si (SiH4, 575 C) o 4 nm undoped Si 0.6Ge0.4 (SiH4,GeH4, 575 C) B δ-doping (2×, 4× baseline, 575oC) o 1 nm p+ Si0.6Ge0.4 (SiH4,GeH4, 575 C) o 100 nm p+ Si (SiH4,650 C) p+ Si Substrate

Figure 6.8 Device structure for study of arsenic doping instead of phosphorus doping

In this study, arsenic is used instead of phosphorus as the n dopant. Arsenic has a higher solid solubility limit that phosphorus. In the earlier study no δ-doping plane was observed on the n side. A high doping of 1× 1020 cm-3 is maintained in the n cap region 137

in order to reduce the series resistance. However, the solid solubility limit of phosphorus

is also limited to 1× 1020 cm-3 hence the large degenerate doping required to obtain an n-

quantum well could not be obtained. This led to a 2D-3D tunneling instead of 2D-2D

tunneling. 2D-2D should improve PVCR further. Figure 6.8 shows the device structure

grown along with the growth temperature for each layer and precursor gases used.

(a) (b) Figure 6.9 Comparison of results for arsenic and phosphorus n-doping with (a) 4 × baseline and (b) 2 × baseline flowrate for the boron δ-doping region

Two structures are grown with boron flow rate in the p δ-doping region equivalent

to the 4 × baseline (sample A) and 2 × baseline flow (sample B). Figure 6.9 shows the

results. Also shown for comparison are results using phosphorus doping. Note that the

results from the arsenic doped samples have been corrected for series resistance to match

the prior phosphorus doped samples. The peak current variation with boron flow rate is

similar to that obtained in the previous study. However, the valley currents are

138 significantly enhanced with the use of arsenic doping. The PVCR reduces from 2.6 to

1.47 for sample A and from 2.9 to 1.5 for sample B. Further studies need to be conducted to investigate the reason for this deterioration in performance.

6.6 Tunneling barrier thickness variation study

o 25 nm n+ Si(SiH2Cl2, PH3, 675 C)

o P δ-doping PH3, 600 C) o x nm undoped Si (SiH4, 575 C) o y nm undoped Si 0.6Ge0.4 (SiH4, GeH4, 575 C) B δ-doping (2× baseline, 575oC) o 1 nm p+ Si0.6Ge0.4 (SiH4,GeH4, 575 C) o 100 nm p+ Si (SiH4, 650 C) p+ Si Substrate

In this study, the boron flow rate is fixed to the optimal flow for highest PVCR obtained from the previous study. This corresponds to the 2 × baseline flowrate. The details of growth and device fabrication are as described earlier in section 6.3. The structures used in this study are shown in Fig. 6.10. Four samples with varying spacer of x nm Si and y nm Si0.6Ge0.4 are grown to obtain tunneling barrier thicknesses of 2 nm (x =

1, y = 1), 4 nm (x = 1, y = 3), 6 nm (x = 2, y = 4), and 8 nm (x = 4, y = 4) respectively.

The measured room temperature current-voltage characteristics are shown in Fig. 6.11.

139

Figure 6.11 Room temperature measured current-voltage characteristics for a (a) 2 nm (Si = 1 nm, SiGe = 1 nm), (b) 4 nm (Si = 1nm, SiGe = 3 nm), (c) 6 nm (Si = 2 nm, SiGe = 4 nm), and (d) 8 nm (Si = 4 nm, SiGe = 4 nm) tunneling barrier thickness. The average peak current densities and PVCR are (a) 280 A/cm2, 3.0; (b) 110 A/cm2, 4.1; (c) 20 A/cm2, 5.2, (d) 0.11 A/cm2, 4.2 respectively

The current density is constant for devices of different mesa area, indicating no

significant leakage current contribution. A shift in the peak voltage with larger area for 2

and 4 nm barrier devices is expected and is due to significant contribution of series

resistance as the device current increases. This is primarily due to resistance emanating

from the p and n bulk regions. The peak current density exponentially varies with spacer

140 thickness with values of 280 A/cm2, 110 A/cm2, 20 A/cm2, 0.11 A/cm2 for thickness of 2,

4, 6 and 8 nm barrier respectively. The tunneling probability for a particle with energy E, incident on a single potential barrier of height E0 and width W, is given by:

(6.4)

where, is the wave vector inside the barrier.

Tunneling probability, and hence current density, thus reduces exponentially with increasing barrier thickness. For a p+-i-n+ diode, this is determined by the thickness of the intrinsic region combined with the depletion width contribution of the highly doped regions. For the RITDs studied here, the tunneling distance is assumed to be the nominally undoped region sandwiched between the two δ-doping spikes.

(a) (b)

Figure 6.12 (a) Current density versus spacer thickness obtained experimentally( ) superimposed with an exponential fitting curve, (b) maximum PVCR variation with tunneling barrier thickness

141

Figure 6.12(a) shows an exponential fit to the peak current density Jp versus spacer thickness W plot obtaining a relation

(6.5)

Results from low-temperature MBE grown devices have demonstrated significantly

higher current densities with . This can be attributed to much sharper dopant profiles from low-temperature growth. The lack of quantum well formation in the n+ regions in these samples could also lead to reduced current densities. p+-i-n+ Esaki diodes grown by LT-MBE but not utilizing δ-doping exhibit much lower current densities of 4.25 A/cm2 for a 5 nm barrier thickness, showing the benefit of both 2D-2D tunneling and the use of SiGe for maximizing tunneling current.

The highest room temperature PVCR of 5.2 is obtained for the 6 nm barrier RITD and reduces for both increasing and decreasing barrier thicknesses [Fig. 6.12(b)]. This is coincident with previous MBE results. The valley current is mainly due to excess current.

Both tunneling and excess current exponentially vary with barrier thickness. However, with increasing tunneling distance, excess current does not decay as rapidly as direct band-to-band tunneling current due to larger possible tunneling transitions via impurity states and shorter tunneling distances through intermediary defect sites within the barrier.

Hence, a reduction in PVCR is often observed as the spacer thickness is increased.

However, with reduction in barrier thickness below 6 nm, the barrier is too thin, and inter-diffusion of P and B dopants into the intrinsic tunneling barrier takes place,

142

resulting in dopant pair defect formation within the bandgap of the tunneling barrier, and

elevated excess currents, resulting in reduced PVCR. Hence the maximum PVCR is

obtained when these two competing factors are balanced. Since CVD growth is closer to

equilibrium compared to LT-MBE, it is expected to incorporate fewer point defects, and

hence lower valley currents are obtained. This is the highest PVCR reported for CVD

grown Si-based tunnel diodes.

6.7 Variation of n cap doping

o 15 nm n+ Si(SiH2Cl2, PH3, 675 C) o 10 nm Si variable doping (SiH2Cl2, PH3, 675 C) o P δ-doping (PH3, 600 C) o 2 nm undoped Si (SiH4, 575 C)

o 4 nm undoped Si 0.6Ge0.4 (SiH4, GeH4, 575 C)

B δ-doping (2× baseline, 575oC) o 1 nm p+ Si0.6Ge0.4 (SiH4,GeH4, 575 C) o 100 nm p+ Si (SiH4, 650 C)

p+ Si Substrate

Figure 6.13 Schematic of the device structure used to study effect of n-cap doping density on the peak current density of CVD grown RITDs

As discussed in the previous section, the lack of quantum well formation in the n+

region could be a reason for the low peak current densities in the CVD grown samples.

To investigate this, a study was done to reduce the n-cap doping density close to the δ-

doping layer to aid quantum well formation. Earlier work using LT-MBE showed much

sharper dopant profiles by using an undoped region close to the δ-doping layer [127]. 143

Here, after the growth of n+ doping spike using Sb as the dopant, the Sb shutter was closed and a 4 nm Si layer was grown at the low-temperature of 250oC. After this the temperature was raised to 350oC to increase the Sb segregation which served to sweep most of the Sb to the surface while lightly doping the injector. An n+ cap layer was grown on top of the undoped layer.

Figure 6.14 Variation in current-voltage characteristics of four samples with different n cap doping close to the n δ-doping region.

In this study, the n cap layer doping in close proximity to the δ-doping layer is varied and the effect on the device performance was investigated. Figure 6.13 shows a schematic of the structures grown. Four structures are grown. Sample A is the control sample and has the entire 25 nm cap nominally doped to 1×1020 cm-3. For the remaining 3 samples B, C and D the 10 nm Si cap layer close to the n δ-doping region are nominally doped to 1×1019 cm-3, 1×1018 cm-3 and undoped respectively. The device is fabricated as

144 described in Section 6.3. Figure 6.14 shows representative current-voltage characteristics for each of the samples. All data corresponds to pieces from the center of the wafer. Not much variation is observed in the peak currents and PVCRs indicating that the segregation effects are dominant and the expected result of a more pronounced n δ- doping spike is not obtained. However, SIMS analysis needs to be conducted to confirm this. Techniques to lower the cap growth temperature in order to reduce segregation can be investigated in the future to improve the current density.

6.8 Performance variation across the wafer

A critical issue of tunneling based devices is the difficulty in controlling performance variation across a wafer. This is due to the exponential dependence of current density on the barrier thickness. Very fine control of the thickness uniformity of the various layers, especially the tunneling barrier, is required to reduce process variations. Since this is the first study of tunnel diodes on a 200 mm wafers, it was deemed necessary to report data on across the wafer uniformity. However, no optimization has been performed to address uniformity issues in this work. Figure 6.15 shows the current-voltage characteristics from center to edge for three samples. Two samples are taken from the boron flow rate optimization study with 2× baseline and baseline flow rate and the third is the 6 nm barrier sample from the barrier thickness study. All samples show consistently an order of magnitude increase in current density from the center to edge of the wafer, with a reduction in peak to valley current ratio.

Good reproducibility and across the wafer uniformity are critical issues for manufacturability and will be examined in future studies.

145

(a) (b)

Figure 6.15 Across the wafer performance for (a) 2× baseline (b) baseline flowrate from boron flow rate optimization and (c) 6 nm barrier wafer from wafer thickness study

(c)

6.9 Conclusion

In this Chapter, optimization of Si/SiGe resonant interband tunnel diodes grown by chemical vapor deposition was performed. The doping of the boron δ-doped plane was found to be a critical knob to obtain high current densities versus high peak to valley current ratio's. SIMS measurements showed the lack of an n δ-doping spike. In the first study, arsenic doping was used, which has a higher solid solubility limit than phosphorus

146 to increase the peak doping of the δ-doping spike compared to the n-cap layer. However, no improvement in peak current density was obtained and deterioration in valley current was observed. A second technique to enhance the dopant spike is to reduce the doping in the cap region close to the δ-doped region. However, again not much variation in device performance was observed. It is plausible that the large segregation due to the high growth temperature of the n-cap layer is responsible for this. Further work needs to be done to investigate improvement of current densities in these structures. Finally a study of the effect of barrier thickness variation on the performance was performed. Record high PVCR of 5.2 was obtained for the 6 nm barrier. Across the wafer variation is also reported. Optimization of each layer is required to improve uniformity and will be investigated in future.

147

CHAPTER 7 HIGH-K DIELECTRICS

Gate length and gate oxide scaling have been key elements in the achievement of continual device scaling and increased functionality per unit area of integrated circuits.

However silicon oxide reached its scaling limit at ~ 2 nm, as several fundamental problems arose such as high gate leakage currents due to tunneling through the oxide, reduced oxide breakdown voltage and boron penetration from the polysilicon gate electrode. Thus, an intensive search ensued for an alternate dielectric with higher permittivity which would allow thicker physical thickness while maintaining the same drive current. This chapter discusses the requirements and issues with high- κ dielectrics.

The conductance method used for characterizing the oxide-semiconductor interface is also discussed. The search for higher mobility channel materials to boost ON-currents led to investigations of III-V semiconductors replacing silicon in the channel. However, the poor III-V native oxide had been the primary reason for silicon dominating the IC industry. The anodic oxidation technique is explored to tailor the native oxide and reduce the interface state density. Finally another interesting application of high- κ dielectrics in the field of biosensors will be discussed.

148

7.1 Properties of High-κ Dielectrics

Dielectric constant is a function of the material polarizability. Figure 7.1 shows the frequency dependence of dielectric permittivity. In the frequency range of interest for

CMOS ionic and electronic polarizability are the main contributors.

Figure 7.1 Frequency dependence of real and imaginary parts of the dielectric permittivity. [128]

The electronic polarizability is due to electron redistribution upon the application of an electric field resulting in separation of the electron distribution with respect to the nuclei. This is caused by electron transition to unoccupied electronic states with different spatial configuration. Atoms with larger atomic number have more electrons to respond to the field and hence higher polarizability. The ionic contribution to permittivity has a much larger effect. This is a result of the displacement of ions with an applied field.

Larger ion displacements are caused if the bond has a smaller force constant. Transition

149 metal ions, with empty d-electron states which have highly anisotropic spatial distribution, are strong candidates for both high ionic and electronic polarizability.

Figure 7.2 Molecular orbital energy level diagram for group IV transition metal in an octahedral bonding with six oxygen neighbors [182]

Figure 7.2 shows the transition metal-oxygen molecular orbital energy level diagram. Each oxygen atom provides one σ and two π 2p electrons. The transition metal atom provides 4d electrons. From crystal field theory, the octahedral bonding arrangement results in a splitting of the degenerate d-orbitals into ( , , ) and

( ) symmetry groups. The resultant molecular orbitals consist of the non- bonding π orbitals of oxygen 2p states forming the top of the valence band and the antibonding orbital formed by transition metal d-states with symmetry and oxygen p- states forming the conduction band. The overlap between the and p states is small forming weak π-type bonds. Hence the splitting between the bonding and antibonding orbitals is small and hence the bandgap is small. Thus, in all transition metal and rare-

150 earth oxides, the conduction band and hence the energy gap is determined by the d- orbitals. The electronic polarizability increases with smaller bandgap.

Figure 7.3 Dielectric constant variation with bandgap [128]

Ionic displacement of the metal ion with respect to the oxygen atom, upon application of an electric field gives rise to the ionic polarizability. This displacement results in increased overlap of the metal d and oxygen p states. This leads to a reduction of the force constant and an increase in the ionic polarizability. The ionic polarizability is

given by: , where, is the ionic charge, is the force constant

determined by the metal-oxygen σ bonds, is the vibronic constant and is the bandgap. Thus, both electronic and ionic polarizability increase with reducing bandgap.

Figure 7.3 shows the relation between dielectric constant and band gap.

Thus, the property that results in high dielectric constant also leads to low band gap and small conduction band offset to silicon which are detrimental for use as a gate

151

dielectric material due to the resulting large leakage currents. Table 7.1 lists the bandgap

and dielectric constant for some candidate high-κ dielectric materials.

Material Dielectric Constant Bandgap Conduction band offset to Si (eV) SiO2 3.9 8.9 3.2 Si3N4 7 5.1 2

Al2O3 9 8.7 2.1 Y2O3 15 5.6 2.3 ZrO2 25 5.8 1.2 HfO2 25 5.7 1.5 La2O3 30 4.3 2.3 Ta2O5 26 4.5 0.5 TiO2 80 3.5 1.2 Table 7.1 Bandgap and conduction band offsets for high-κ dielectric materials

7.2 Requirements for a Gate Dielectric

The key requirements for a new high-κ ma terial to be considered as a gate

dielectric are [128], [129]: 1) a high enough dielectric constant 2) Good thermodynamic

stability in contact with the semiconductor 3) have band offset of more than 1eV to the

semiconductor 4) form good electrical interface 5) have few bulk electrically active

defects 6) kinetically stable at typical source/drain anneal conditions of 1000oC for 5

seconds.

The dielectric constants should be over 10. As discussed earlier, the dielectric

constant and band gap have an inverse relation. Thus, too high values of κ could result in

very leaky oxides. High-κ also leads to strong fringe capacitances. Hence, a value of 25-

30 is preferred.

152

The oxide should not form SiO2 or silicide at the interface with silicon. SiO2 formation reduces the effective dielectric constant while silicides are metallic, shorting the field effect. This eliminates the use of Ta2O5 and TiO2. HfO2 and ZrO2 have high oxygen diffusivities [130]. Thus, annealing them in the presence of an oxygen ambient leads to oxygen diffusion and SiO2 formation at the interface.

Band offset to silicon should be symmetric and larger than 1 eV to prevent

Schottky emission of electrons or holes into the oxide bands. The leakage current through

an oxide due to thermionic emission is given by [25] ,

where is the barrier height, is the effective Richardson constant, is electric field across dielectric, is the temperature, is dielectric permittivity. Thus, the bandgap of the dielectric should be larger than 5 eV. Lanthanides have the highest conduction band offset. This reduces the candidate dielectrics to Al2O3, ZrO2, HfO2, La2O3 and Y2O3.

La2O3 has a higher κ than HfO2 but is more hygroscopic.

The reason for the success of the silicon industry has been the excellent interface

10 -2 between Si and SiO2 with interface defects of the order of 10 cm . Most high-κ materials have interface state densities in the range of 1010-1012 cm-2. Lucovsky et al.

[131] predicted using constraint theory that the large interface state density was a result of bonding constraints. The interface defect density increased proportionally to the average number of bonds per atom Nav. Metal oxides with a high coordination number have a high Nav (Nav > 3) and form an over-constrained interface with silicon in comparison to SiO2 with an Nav = 2.67, which is optimal since bond-bending forces are too weak to act as constraints at growth or annealing temperatures. 153

The rigid metal oxide structure also results in higher bulk defect density which are less likely to be reduced by high-temperature anneals since that would require a significant bond rearrangement. Typical defects include oxygen vacancies and interstitials in different charge states. Figure 7.4 shows the energy level of different defects in monoclinic HfO2. These serve as electron and hole traps which can lead to a shift in the threshold voltage of the transistor and a drift in threshold voltage with time.

These also act as scattering sites for carriers in the channel, reducing mobility.

Additionally, they increase the electrical failure probability and breakdown of the oxide.

Electrons are trapped in the delocalized d-states and the trapping/de-trapping is reversible and is observed as a hysteresis in the drain current-gate voltage characteristics.

Figure 7.4 Energy level diagram showing electron affinities of various defects in monoclinic HfO2 [183]

154

o Most metal oxides, except Al2O3, crystallize at low temperatures (~ 500 C). This is also a result of the rigid structure, resulting in long-range ordering. Crystallization leads to increased ion diffusion along the grain boundaries, affecting the threshold voltage. Oxygen vacancies also tend to precipitate along the grain boundaries serving as high leakage paths. Alloying with SiO2 [132] or Al2O3 [133] to form silicates and aluminates is found to improve thermal stability up to 900oC. Alloying also reduces the oxygen diffusion rate. Aluminates will result in higher κ but suffer from more defects.

Nitridation further improves the crystallization temperature to 1000oC [134].

7.3 Passivation of III-V semiconductors

III-V semiconductors have been known to have superior electron transport properties compared to silicon. However the absence of a good interface with its native oxide has been the biggest obstacle in realizing III-V MOSFETs. Fermi level pinning at the oxide semiconductor interface prevents effective gate modulation. Although there is still debate on the origin of the pinning [135] but it is generally believed to be due to an unstable arsenic oxide which decomposes to form metallic arsenic. This metallic arsenic is believed to pin the Fermi level [136]. The Fermi level remains invariant in the resulting

As metal/GaAs Schottky diode and the total capacitance of the oxide plus the depletion region does not change. It has also been found that preferential formation of Ga2O over

Ga2O3 can reduce the interface state related frequency dispersion in III-V MOS capacitors [137], [138]. Table 7.2 shows the Gibbs free energy for each of the native oxides. Arsenic oxides are the most unstable and are converted to gallium oxide at higher temperatures (> 500oC) along with the formation of metallic arsenic.

155

As2O3 + 2GaAs → Ga2O3 + 4As

Table 7.2 Gibbs free energy of stable III-V oxides [139]

Oxide Gibbs free energy ΔG (kcal/mol) Ga2O -75.3 Ga2O3 -238.6 GaAsO4 -212.8 GaSbO4 -218.4 GaPO4 -310.1 In2O3 -198.6

InAsO4 -209.4 InSbO -198.4 4 InPO4 -287 P2O3 -176 P2O5 -322.4 As2O3 -137.7 As2O5 -187 Sb2O3 -151.5

For InAs, InAsO4 is formed instead which is stable with minimal arsenic at the interface.

InxGa1-xAs forms a mixture of oxides of its constituent elements along with elemental As.

Annealing at high temperature again removes arsenic oxides and increases Ga oxide formation. InAsO4 does not form in this system. The oxides of InSb and GaSb behave similar to GaAs with formation of In/Ga and Sb oxides along with elemental Sb.

Various surface treatments prior to oxide deposition have been examined to reduce the interface state density. The most common wet chemical treatments are using ammonium hydroxide solution [140] to etch the native oxide, leaving elemental As behind, followed by the use of sulfur passivation ((NH4)2S, Na2S.9H2O) which etches away As and prevents further oxidation of the surface [141]. Sulfur also being a group VI element like oxygen, has the same electron number in its outer shell but is less chemically

156 reactive. Hence, it can passivate a clean III-V surface and prevent further oxide formation. The use of a thin amorphous Si layer, deposited using PECVD, as an interfacial layer, followed by high-k dielectric deposition also results in good oxide quality, which is believed to be due to the removal of the Ga 3+ oxidation state while leaving the Ga 1+ oxidation state [137]. Si getters the oxygen from the Ga 3+ species and serves as a barrier to further interface oxidation. Another effective way to reduce interface state densities is the 'self-cleaning' action by the trimethyl aluminum precursor which is widely used in the atomic layer deposition of Al2O3. This is believed to be due to Al also existing in a 3+ oxidation state, which effectively replaces the As in a 3+ oxidation state via a ligand exchange mechanism, thus removing arsenic oxide [142].

7.4 Gate oxide characterization using a metal-oxide-semiconductor capacitor

Gate Metal

Dielectric oxide Semiiconductor

Backside contact

Figure 7.5 Metal-oxide-semiconductor structure

The metal-oxide-semiconductor (MOS) capacitor structure is the most useful device to study the oxide quality and the oxide-semiconductor interface. The structure is shown in Fig. 7.5. Figure 7.6 shows the energy band diagram for both p and n type 157 semiconductors. Considering the case for a p-type semiconductor, application of a negative bias causes an accumulation of the majority carriers (holes in this case) at the semiconductor-oxide interface. The valence band edge near the surface moves upwards and is closer to the Fermi-level. Application of a small positive bias causes the bands to bend downward, the majority carriers are pushed away from the interface and a depletion region is formed. The Fermi level is close to midgap at the surface. Further increase in positive bias pulls the minority carriers (electrons) towards the surface with the bands bent further down and the intrinsic level crossing the Fermi level at the surface. This is

known as inversion. The total capacitance where, is charge on the gate and

is applied bias. Since, and where, is the surface potential and is the voltage across the oxide.

(a) (b) (c)

Figure 7.6 Energy band diagram for MOS capacitor formed using a p-type and n-type semiconductor in (a) accumulation (b) depletion and (c) inversion [25]

158

(7.1)

where, is the oxide capacitance and is the semiconductor capacitance.

The corresponding equivalent circuit for an ideal MOS capacitor is shown in Fig.

7.7(a) and capacitance-voltage plot is shown in Fig. 7.7(b) for the low (~100 Hz - 1 kHz) and high frequency (>100kHz) case. At high frequencies the minority carrier generation rate is too slow to respond to the ac signal.

Cox Cox

Cit CS CS Rit

(a) (b) (c) RS

Figure 7.7 (a) Equivalent circuit of an ideal MOS capacitor (b) C-V plot for low and igh frequencies and (c) non-ideal equivalent circuit for MOS capacitor

In reality, several non-idealities are present in the MOS capacitor structure. These include work function difference between the gate metal and semiconductor Φms, causing a band bending at equilibrium; fixed oxide charge due to charged defects in the oxide, also resulting in a shift in the flat-band voltage and hence the threshold voltage; interface trap charge at the oxide-semiconductor interface, these result in two effects – (1) the 159 charge on the interface states varies with applied dc bias, resulting in a stretch out in the

C-V. (2) Additionally, an interface state capacitance (Cit) is also added due to variation in

trapped charge with applied ac signal at the gate where, . The capture and

emission of carriers from interface traps is not instantaneous and this is included in the small signal equivalent as a resistance in series with the capacitance. It also indicates an energy loss associated with the process. Finally, a series resistance is present due to the contact resistance from the back contact, resistance of bulk semiconductor between back contact and depletion layer edge, resistance due to gate electrode material, probes and connecting cables. The final equivalent circuit for a practical MOS capacitor is shown in

Fig. 7.7(c).

For the work detailed in this dissertation, the Agilent 4284 LCR meter is used.

The measured admittance is modeled as a capacitance in parallel with a conductance as shown in Fig 7.8(a). Series resistance results in frequency dispersion primarily in the accumulation region. Considering the simplified case with no interface state defects (Fig.

7.8(b)), and equating the measured admittance to the actual MOS model (Cox in series with CS and RS), the measured capacitance and conductance (Cm and Gm) in terms of the actual model parameters are given by:

where,

(7.2)

160

(7.3)

The RsC time constant reduces as the voltage is swept from accumulation to depletion, hence in the case of a high frequency C-V (or measurements in the dark), where the minority carriers are unable to respond to the ac signal, the larger effect of the series resistance is seen in the accumulation and is observed as a drop in the accumulation capacitance with increasing frequency.

Cox Cox

Cm Gm

CS CD GD

(a) (b) (c)

Figure 7.8 Equivalent circuit for (a) measured admittance (b) calculation of series resistance (c) calculation of interface states

7.4.1 Conductance technique for interface state characterization

It is critical to eliminate the effect of series resistance for calculating the interface states using the conductance technique. This is done by measuring the admittance in accumulation. In accumulation, the semiconductor capacitance becomes infinite making the equivalent circuit a series combination of Cox and RS. Once the series resistance is

161 eliminated, the conductance is only due to interface states and this is utilized in the conductance technique for the measurement of interface state density.

7.4.1.1 Single-level interface traps

The equivalent circuit is shown in Fig. 7.9(a) where and are given by [143]:

(7.4)

For an n-type substrate, the electron capture and emission are dominant and

(7.5)

For a p-type substrate, the hole capture and emission are dominant and

(7.6)

The total admittance for electron capture and emission is given by:

(7.7)

The total admittance for hole capture and emission is:

(7.8)

Here, is the density of interface traps, and are the electron and hole density, and are the electron and hole capture probability and is the trap level

occupancy function , is the energy level of the trap and is

the Fermi level. An equivalent representation of Fig. 7.7(c) is illustrated in Fig. 7.8(c).

Here, Cd is the total bias dependent capacitance including semiconductor capacitance Cs and interface state capacitance Cit and Gd is the conductance due to interface states.

Using circuit analysis, Fig. 7.9(a) is equivalent to the circuit in Fig. 7.8(c) with: 162

and (7.9)

(7.10)

where,

The conductance shows a peak at or . At this value,

. Now the function peaks at . Hence, a plot of

versus gate bias (VG) shows a peak at the VG where . Thus, shows a peak

both as a function of frequency and bias.

Cox Cox

Cit Cit1 Citn CS CS

Git Git1 Gitn

(a) (b) (c)

7.4.1.2 Distribution of interface states

In reality, the interface states are distributed continuously in energy and the equivalent circuit is as shown in Fig. 7.9(b). Hence in equation (7.7) and (7.8) is 163 replaced by . Where is the interface state density per unit energy per unit area.

Considering a p-type substrate:

[144] (7.11)

Now, ,

(7.12)

Replacing Eq. (7.12) into Eq. (7.11)

Assuming is constant,

(7.13)

Evaluating using the boundary values of 0 and 1 for :

, (7.14)

And the total capacitance is given by:

(7.15)

A similar expression is obtained for an n-type substrate.

164

A peak in the conductance corresponds to , or ,

giving . Substituting into Eq. (7.14):

(7.16)

Hence, at the conductance peak,

or, (7.17)

This is the general formula used to determine the interface state density from the peak in the measured conductance.

Since there is no DC current flow in a MOS capacitor, the system is in thermal equilibrium. From the principle of detailed balance, the dc components of capture and emission rate are equal. Considering a p-type substrate with dominant hole capture and emission,

[145]

or, (7.18)

similarly, for an n-type material, (7.19)

Maximum energy loss, or peak in the conductance with bias is observed when the emission rate is comparable to the ac frequency [146]. Combining Eq. (7.18) and (7.19)

(7.20)

Where, is the hole/electron capture cross-section, is the thermal velocity, is the density of states for the majority carriers and is the energy difference between the majority carrier band edge and the trap energy. Thus, the applied frequency can be 165 correlated with the position in the bandgap at which the interface traps are measured and the peak in the conductance-gate bias plot gives the interface state density at that energy level.

7.5 Anodic oxidation technique for stoichiometric control of GaAs native oxide

Anodic oxidation is an alternate technique to thermal oxidation to grow native oxide. It is a room temperature process. It is particularly useful for III-V materials such as

GaAs since as discussed in Section 7.3, As2O3 is thermally unstable at higher temperatures and decomposes to form metallic As which pins the Fermi level. Since this is a room temperature process, it can reduce this As formation.

Anodic oxidation of GaAs was largely explored in the 1970s as an alternate to thermal oxidation to produce high quality native oxide [147], [148]. However all prior work was focused on thick oxides of the order of 100’s of nanometer’s involving application of very high voltages (~100V). The typical choice for electrolyte solution was

AGW solution (Acid-Glycol-Water). The acid chosen can be citric, tartaric or phosphoric acid and the glycol additive is typically used to improve uniformity. In this dissertation, modifications to the electrolyte solution are investigated to preferentially form the electrically preferred gallium oxide instead of a mixture of gallium and arsenic oxide.

Two buffer solutions are tested: citric acid with buffered ammonium hydroxide and the buffered citric acid with a gallium sulfate additive to saturate the solution with Ga.

7.5.1 Experimental Setup

An electrochemical cell consists of a working electrode, a counter electrode and a reference electrode. The current flows between the working electrode and the counter

166 electrode while the reference electrode provides a constant reference potential and the potential of the working electrode is measured with reference to this. Figure 7.10 shows the setup used in this work. The wafer is connected to an aluminum backplate to form the working electrode. A platinum wire is used as the counter electrode along with a n

Ag/AgCl reference electrode. The samples consist of a p-GaAs doped with Zn and an n-

GaAs doped with Si. Autolab with PGSTAT 100 is used for computer controlled electrochemical measurement.

Figure 7.10 Electrochemical setup used for GaAs anodic oxidation

The energy level of electrons in an electrolyte associated with ions is characterized by the redox potential EREDOX. It describes the tendency of each species in the electrolyte to give up or accept electrons and is equivalent to the Fermi level for a semiconductor. The most probable energy level of the reducing species is given by ERED

167 while the most probable energy level of the oxidizing species is given by EOX. The energy levels of the ions tend to fluctuate due to the solvent molecules surrounding the ions resulting in a Gaussian distribution of energies. When a semiconductor is brought in contact with an electrolyte, the Fermi levels align by transfer of charge across the interface. This results in a space charge region on the semiconductor side and a

Helmholtz potential on the solution side. Figure 7.11(a) and 7.11(b) show the equilibrium condition for a p-GaAs and an n-GaAs wafer in an electrolyte. In non-degenerate semiconductors, the applied bias primarily drops across the space charge region in the semiconductor. For p-GaAs, application of a positive bias (anodic current) results in majority hole injection from the valence band into the electrolyte [Fig. 7.11(c)]. The resultant reactions at the anode are:

GaAs + 6h+ → Ga3+ + As3+

+ - 3H2O ↔ 3H + 3(OH)

3+ - Ga + 3(OH) → Ga(OH)3

2Ga(OH)3 → Ga2O3 + 3H2O

3+ - + As + 2(OH) → AsO2 + 2H

- + 2AsO2 + 2H → As2O3 + H2O

Similar reactions occur for an n-GaAs. However, since holes are the minority carriers in this case, light is required to create electron-hole pairs and initiate the reaction (Fig.

7.11(d)). Due to the resultant oxide formation, the flow of current is inhibited and the oxide thickness is thus self-limited.

168

Helmholtz Helmholtz layer layer EC EOX + EC EREDOX EF - + EOX - ERED EF EREDOX - + EV ERED EV (a) (b)

EC EOX e EOX EC e EREDOX EREDOX EF ERED EF EHP ERED generation EV h h hole hole light injection injection (c) EV h h (d)

EC electron e injection e EHP electron EC e e generation injection EOX light EF EREDOX EOX 2H+ + 2e- → H2 EF ERED EREDOX EV h h ERED EV (e) (f)

Figure 7.11 Semiconductor-electrolyte interface under various bias conditions

169

In the reverse bias (cathodic current) electrons are injected from the conduction band. Now for p-GaAs light is required to initiate the reaction since electrons are the minority carriers in this case. Electron injection results in reduction of H+ ions to hydrogen and hydrogen bubbles can be observed near the wafer surface (Fig. 7.11(e) and

(f)). The resultant cyclic voltammetry curve are shown in Fig. 7.12.

14 30 Buffered citric acid + 0.01M Ga (SO ) Citric acid + NH OH 2 4 3 12 4 25 pH = 4.3 pH = 3.64 10 20

8 15

6 10

4 5

Current (mA) Current (mA) 2 0 0 -5 -4 -2 0 2 4 -6 -4 -2 0 2 4 6 Voltage (V) Voltage (V) (a) (b)

Buffered citric acid + 0.05M Ga (SO ) 80 2 4 3 pH = 2.03 Figure 7.12 Cyclic voltammetry curves for 60 (a) 0.2M citric acid buffered with NH4OH

(b) buffered citric acid with 0.01M

40 current compliance Ga2(SO4)3 and (c) buffered citric acid with limit

0.05M Ga2(SO4)3 showing no oxide Current (mA) 20 formation in (c) 0 0 1 2 3 4 5 Voltage (V) (c)

170

7.5.2 Results

The initial set of experiments targeted growing thin self-limited oxides by anodic oxidation and growing thicker high-k dielectrics on top using atomic layer deposition

(ALD). However, this was unsuccessful since the self-cleaning action of the ALD precursors removed the native oxide grown. Cyclic voltammetry is useful in analyzing the effect of various solvents. Figure 7.13 shows the influence of solvent on the curves.

Samples were cleaned with acetone and methanol followed by DI water rinse prior to oxidation. Sample 1 utilized a 0.2M citric acid solution buffered with NH4OH with a resultant pH of 4.02. For sample 2 0.01M Ga2(SO4)3 was added to the buffered citric acid solution to obtain a pH of 3.64. For sample 3 the concentration of Ga2(SO4)3 was increased to 0.05M with a resultant pH of 2.03. No self-limiting action is observed for

self-limiting action: oxide formation inhibits current flow 12 20 increasing light 15 10 intensity 10 8 increasing light 5

intensity 6

-5 4 Current (mA)

Current (mA) -10 2 -15 photocurrent 0 -20 -4 -2 0 2 4 -5 -4 -3 -2 -1 0 1 2 3 4 5 Voltage (V) Voltage (V) hydrogen bubbles at cathode (a) (b) dark (wafer) blocks reference electrode capillary causing current fluctuations Figure 7.13 Cyclic voltammetry curves for (a) p-GaAs and (b) n-GaAs

171 sample 3. This can be explained by referring to the Pourbaix diagram (Fig. 7.14) which shows the stable phases in a system for a given pH suitable for oxide formation. Both

Ga2O3 and As2O3 are soluble in highly acidic and alkaline solutions.

(a) Gallium (b) Arsenic

Potential Potential

pH pH Figure 7.15Pourbaix diagram for (a) gallium and (b) arsenic showing pH and potential for stable oxide formation

25 mA/cm2, 120 nm 10 19 mA/cm2, 47 nm

8 5.4 mA/cm2, 10 nm

5.7 mA/cm2, 34 nm

Voltage(V) 4

3.8 mA/cm2 1.9 mA/cm2 2 0.95 mA/cm2 0 2 4 6 8 10 12 14 16 18 20 time (sec) Figure 7.14 Chronopotentiometry curves with various current densities to obtain different oxide thicknesses

172

Table 7.3 shows the XPS data from samples grown in citric acid and those grown in citric acid + Ga2(SO4)3 using this method. A very small reduction in arsenic and arsenic oxide was observed but the data is not very conclusive when compared with the bare GaAs substrate data.

Table 7.3 XPS results for anodic oxide grown by cyclic voltammetry

Ga3d Ga3d As3d As3d5 As2O3/(As2O3+Ga2O3) As/(As+Ga) GaOx GaAs AsOx GaAs p-GaAs 6.8 31.2 5.7 34 0.46 0.52 citric acid p-GaAs substrate 9.6 19.1 9.4 22.5 0.5 0.54 p-GaAs 6.8 37.1 3.8 33.6 0.36 0.48 citric+Ga2(SO4)3 p-GaAs substrate 7.4 39.7 2.9 32 0.28 0.45

In order to grow thicker oxides, chronopotentiometry (CP) technique was used.

Here a constant current is applied between the working and counter electrode. As the oxide layer grows thicker, the voltage required to maintain the constant current increases until the voltage reaches a software defined limit of 10V. (This is the voltage between the working electrode and reference electrode. The compliance limit between the working and counter electrode, which is not measured, is 100V). A constant voltage technique

(chronoamperometry) can also be used, where the voltage is kept constant while the current drops as the oxide grows thicker. However, the CP technique produces more uniform oxide films [149], [150]. Oxides of thickness ranging from 10 nm to 120 nm were grown by varying the current density. Figure 7.15 shows the CP curves for various current densities. After oxidation, the samples were annealed in forming gas at 400oC for

5 minutes. This was followed by evaporation of 100 nm Ni metal dots through a shadow 173 mask. Finally Cr/Au was deposited to form the backside contact. Ellipsometry was used to measure the oxide thicknesses assuming a GaAs native oxide refractive index of 1.8.

The dielectric constant obtained is 9.4. Figure 7.16 shows the 2" wafers with oxide formed around the center, with a 1" diameter, corresponding to the part of wafer in contact with the electrochemical cell.

10 nm 34 nm

47 nm 120 nm

Capacitance-voltage and conductance-voltage measurements were made using

Agilent 4284 LCR meter for frequencies from 1 kHz to 1 MHz. Since GaAs has a wide bandgap, high temperature measurements (100oC) are also performed to probe interface states closer to midgap [151]. Figure 7.17-7.21 shows the results for oxides grown with and without addition of gallium sulfate solution. The conductance data is plotted as a

174 contour plot of the normalized conductance (G/Aωq) as a function of the gate bias and the energy level in the bandgap. The relationship between measurement frequency and location in the energy bandgap is obtained using the characteristic time for emission of a charge from a trap (Eq. 7.18, 7.19). Interface states are calculated using the conductance technique described in section 7.4. The addition of Ga2(SO4)3 clearly results in a reduction in interface state density, also observed in the C-V plot as a reduced frequency dispersion. A reduction in the peak due to arsenic dangling bonds can be observed. It should be noted that the absolute value of interface state density is not reliable due to leakage currents, especially in the thinner oxides, also adding to the conductance. Further, frequency dispersion makes extraction of Cox incorrect. Figure 7.22 shows the result for n-GaAs. Strong Fermi-level pinning is observed in this case. As discussed in section 7.3, metallic arsenic is not the only cause of Fermi level pinning and the phase of gallium oxide is also a possible reason. Enhancement of Ga2O over Ga2O3 could possibly improve this. Figure 7.23 shows leakage current and breakdown voltage characteristics.

The breakdown field is 1.8×106 V/cm. Figure 7.24 shows hysteresis characteristics.

Thinner oxides demonstrate smaller hysteresis.

175

0.35 0.34 o Room Temperature 100 C

0.32 )

) 2

2 0.30 0.30 1 kHz 1 kHz

0.28 F/cm

F/cm 0.25 

 0.26

0.24 0.20 0.22 0.20 0.15 1 MHz

0.18 1 MHz Capacitance ( Capacitance ( 0.16 0.10 -2 -1 0 1 2 -2 -1 0 1 2 3 4 5 Voltage (V) Voltage (V) (a)

0.55 0.32 2.1 1.4 0.43 0.097 0.54 1.7 /cm-eV 1.0 0.34 12 /cm-eV 0.21 1.0 0.42 12 0.21

0.51 1.4 0.69 10q) 

q) 10 q) 0.32 0.69 0.097 1.0  0.39 0.48 1.4 0.43

0.45 0.34 1.7 0.36 0.55 2.1 0.097 0.66

0.42 Conductance(G/A 2.4 0.33 0.32 Conductance(G/A 0.32 0.39 0.30 0.36

0.27 EnergyLevel in Bandgap (eV) EnergyLevel Bandgap in (eV) 0.33 -2 -1 0 1 2 3 4 5 -2 -1 0 1 2 Voltage (V) Voltage (V) (b)

) 2 7 Room Temperature 6 o

/eV-cm 100 C

12 5

4 Arsenic 3 dangling 2 bonds 1 0 0.24 0.28 0.32 0.36 0.40 0.44 0.48 0.52 0.56

IntefaceState Density (10 Energy Level in Bandgap (eV) (c) Figure 7.17 (a) C-V plots measured at room temperature and 100oC (b) conductance as a functon of gate bias and energy level in bandgap (c) interface state density for anodic oxide of p-GaAs formed using buffered citric acid solution with thickness of 34 nm

176

0.20 0.21 o

0.19 Room Temperature 0.20 1 KHz 100 C

)

) 2 2 0.18 1 KHz 0.19 0.18

0.17 F/cm

F/cm 0.17   0.16

0.16

0.15 1 MHz 0.15 1 MHz 0.14 0.14 0.13 0.13

0.12 0.12 Capacitance ( Capacitance ( 0.11 0.11 -4 -3 -2 -1 0 1 2 3 4 -4 -3 -2 -1 0 1 2 3 4 Voltage (V) (a) Voltage (V)

0.23 0.029 0.30 0.029 0.54

0.42 /cm-eV 0.024 12 1.1 /cm-eV 0.096 12 0.51 0.024 0.21

q) 10 q) 0.76  0.39 0.23 0.16 0.39 10 q) 0.029  0.029 0.48 0.94 0.57 0.16 0.23 0.024 1.1 0.39 0.76 0.36 0.029 0.16 0.30 0.45 0.57 0.21 0.94 0.36 1.1 0.33 0.16 0.42 Conductance(G/A 1.3 0.024 Conductance(G/A 0.39 0.21 0.30 0.029 0.16 0.36

0.27 EnergyLevel Bandgap in (eV)

EnergyLevel Bandgap in (eV) 0.33 -4 -3 -2 -1 0 1 2 3 4 -4 -3 -2 -1 0 1 2 3 4 Voltage (V) (b) Voltage (V)

-eV) 3.5 2 Room Temperature 3.0 o

/cm 100 C 12 2.5 Arsenic

2.0 dangling

1.5 bonds passivated 1.0

0.5 0.24 0.28 0.32 0.36 0.40 0.44 0.48 0.52 0.56

InterfaceState Density (x10 Energy Level in Bandgap (eV) (c) Figure 7.18 (a) C-V plots measured at room temperature and 100oC (b) conductance as a functon of gate bias and energy level in bandgap (c) interface state density for anodic oxide of p-GaAs formed using buffered citric acid solution with Ga2(SO4)3 and thickness of 47 nm 177

1.4 o

1.4 100 C

)

) 2 2 1 kHz

1.2 Room Temperature 1.2 F/cm F/cm 1.0

1 kHz  1.0



0.8 0.8

0.6 0.6 0.4 1 MHz

0.4 Capacitance ( Capacitance ( 0.2 1 MHz 0.2 -0.5 0.0 0.5 1.0 1.5 2.0 -0.5 0.0 0.5 1.0 1.5 2.0 Voltage (V) (a) Voltage (V)

0.49 2.8 3.8 0.49

1.1 0.55 /cm-eV /cm-eV 0.55 1.7 0.51 12 12 2.1 0.40 2.8 2.1

1.1 1.1

q) 10 q)

q) 10 q) 

 0.48 5.4 3.8 0.38 0.55 1.7 7.0 0.49 2.2 5.4 0.36 2.2 0.45 7.0 1.7 2.8 0.34 0.42 3.4 8.7

1.1 Conductance(G/A Conductance(G/A 0.32 0.39 0.30 0.36

0.28 EnergyLevel Bandgap in (eV) EnergyLevel Bandgap in (eV) 0.33 -0.5 0.0 0.5 1.0 1.5 2.0 -0.5 0.0 0.5 1.0 1.5 2.0 Voltage (V) Voltage (V) (b)

-eV) 2

/cm 20 12 Arsenic 15 dangling

bonds 10

0 0.28 0.32 0.36 0.40 0.44 0.48 0.52 0.56 Energy Level in Bandgap (eV) InterfaceState Density (x10 (c) Figure 7.19 (a) C-V plots measured at room temperature and 100oC (b) conductance as a functon of gate bias and energy level in bandgap (c) interface state density for anodic oxide of p-GaAs formed using buffered citric acid solution with thickness of 11 nm

178

0.8

0.8 100oC

)

) 2 2 0.7 0.7 Room Temperature 1KHz

0.6 0.6

F/cm

F/cm   1KHz

0.5 0.5

0.4 0.4

0.3 0.3 1MHz 1MHz

0.2 Capacitance ( Capacitance ( 0.2 0.1 -0.5 0.0 0.5 1.0 1.5 2.0 -0.5 0.0 0.5 1.0 1.5 2.0 Voltage (V) (a) Voltage (V)

0.44 0.54 8.9 4.8 1.2 0.61 0.79 7.5 0.52 2.1 /cm-eV 0.30 /cm-eV 0.42 2.1 12 0.30 12 0.61 0.50 6.2 3.5

0.40 0.61 10 q) q) 10 q) 3.5  0.92  0.48 4.8 0.38 0.92 6.2 0.46 0.79 7.5 0.36 1.2 0.44 8.9 0.42 0.34 1.5 10

0.40 Conductance(G/A 0.32 0.30 Conductance(G/A 0.38 0.30 0.30 0.36 EnergyLevel Bandgap in (eV) 0.28 0.34

EnergyLevel Bandgap in (eV) 0.79 -0.5 0.0 0.5 1.0 1.5 2.0 -0.5 0.0 0.5 1.0 1.5 2.0 Voltage (V) (b) Voltage (V)

-eV)

2 25 /cm 12 12 20 Arsenic 15 dangling

bonds 10 passivated 5

0 0.24 0.28 0.32 0.36 0.40 0.44 0.48 0.52 0.56

Energy Level in Bandgap (eV) InterfaceState Density (x10 (c) Figure 7.20 (a) C-V plots measured at room temperature and 100oC (b) conductance as a functon of gate bias and energy level in bandgap (c) interface state density for anodic oxide of p-GaAs formed using buffered citric acid solution with Ga2(SO4)3 and thickness of 10 nm

179

0.068 0.066 Room Temperature 0.066

) o ) 2 1 kHz

0.064 2 100 C 1 kHz 0.064

0.062 F/cm

F/cm 0.062 

0.060 

0.060

0.058 0.058 0.056 1 MHz 0.056 1 MHz 0.054

0.054 Capacitance (

0.052 Capacitance ( 0.052 -6 -4 -2 0 2 4 -6 -4 -2 0 2 4 6 Voltage (V) Voltage (V) (a)

0.44 0.54 0.15 /cm-eV 0.52 0.12 0.42 10 0.0067 0.96 0.50 /cm-eV 0.090 12 2.1 10 q) 0.035 0.40  0.063 0.96 0.48 0.0067 0.96 0.063 10 q)

0.035  0.38 2.1 0.96 0.46 0.0067 0.063 0.00670.0067 0.090 2.1 0.44 0.035 0.36 0.96 0.96 0.96 0.035 0.0067 0.12 3.2 0.42 0.0067 0.34 2.1 0.15

Conductance(G/A 0.40 0.32 0.17 0.38 0.0067 Conductance(G/A 0.30 0.36

0.96 EnergyLevel Bandgap in (eV)

EnergyLevel Bandgap in (eV) 0.28 0.34 2.1 -6 -4 -2 0 2 4 6 -6 -4 -2 0 2 4 (b) Voltage (V) Voltage (V)

-eV) 0.45 2

0.40 /cm

12 0.35 Arsenic 0.30 dangling bonds

0.25 0.20 passivated 0.15 0.10 0.05 0.25 0.30 0.35 0.40 0.45 0.50 0.55

InterfaceState Density (10 Energy level in bandgap (eV) (c)

180

Figure 7.23 C-V plots (measureda) at room temperature for n-GaAs( busing) (a) buffered citric acid (b) buffered citric acid solution with Ga2(SO4)3 with thickness of 11 nm, showing Fermi level pinning in both cases.

106 -5

10 4 )

120 nm ) 10 47 nm

2 2 102 10-6 100

-2

10 10-7 10-4 10-6 10-8 10-8

-10 Current Density(A/cm Current Density (A/cm 10 -1.5x106-1.0x106-5.0x105 0.0 5.0x105 1.0x106 1.5x106 -1.6x106 -8.0x105 0.0 8.0x105 1.6x106 (a) Electric Field (V/cm) (b) Electric Field (V/cm)

103

103 )

) 34 nm 1 10 nm 2 2 10 101 10-1 10-1 -3

-3

10 10

-5 10-5 10

-7 10-7 10

-9 -9

Current Density (A/cm Current Density (A/cm 10 10 6 6 6 6 6 6 6 -1.6x106 -8.0x105 0.0 8.0x105 1.6x106 -3x10 -2x10 -1x10 0 1x10 2x10 3x10 4x10 (c) Electric Field (V/cm) (d) Electric Field (V/cm) Figure 7.22 Leakage current and breakdown characteristics for p-GaAs wafers with anodic oxide grown in citric acid solution with Ga2(SO4)3 with oxide thickness of (a) 120 nm (b) 47 nm (c) 34 nm (d) 10 nm

181

0.40

1.2 )

34 nm ) 11 nm 2 0.35 2

1.0 F/cm

1.28 V F/cm 

0.30  0.8 80 mV

0.25 0.6

0.4

0.20 Capacitance ( Capacitance ( 0.2 0.15 -4 -2 0 2 4 -0.8 -0.4 0.0 0.4 0.8 Voltage (V) (a) Voltage (V)

0.17 0.8

) ) 2 0.16 47 nm 10 nm

2 0.7 0.15

F/cm 0.6 110 mV

F/cm 

0.14 0.88 V 

0.5 0.13 0.12 0.4

0.11 0.3

Capacitance ( Capacitance ( 0.10 0.2 -4 -2 0 2 4 -0.8 -0.4 0.0 0.4 0.8 Voltage (V) (b) Voltage (V)

Figure 7.24 Hysteresis curves (a) without and (b) with Ga2(SO4)3 showing reduced hysteresis for oxides grown in Ga2(SO4)3

In conclusion, electrochemistry provides a unique pathway to tailor native oxides on III-V semiconductors. First, the native oxide present on the wafer can be removed prior to anodic oxidation by applying a reverse bias before growth. The electrolyte solution composition can be modified to selectively form gallium oxide only and reduce midgap interface state density by reducing metallic arsenic formation. Further investigation can include increasing the concentration of Ga2(SO4)3 while adjusting the pH of the solution to still remain in the oxidation regime; reducing oxide thickness grown

182 and capping with a high-κ dielectric to reduce leakage currents and further improve dielectric constant.

7.6 Atomic Layer Deposition

Atomic layer deposition (ALD) is a layer-by-layer deposition method relying on self-limiting surface reactions to obtain atomic layer control of deposition. It is a modification to chemical vapor deposition (CVD) in which the precursors are pulsed sequentially with nitrogen purge cycles in between. The gas precursor decomposes and is chemisorbed on the surface and the reaction is limited to a maximum of one monolayer, resulting in a self-limiting reaction. The purge cycles in between the precursors ensures the chamber is cleaned of the previous precursor before the next is pulsed, preventing any

Figure 7.25 Schematic of one ALD reaction cycle [184]

183 gas phase reactions as in CVD. This ensures the atomic layer control and uniform deposition thickness. Figure 7.25 illustrates one ALD cycle.

One ALD cycle consists of: (A) self-terminating reaction of the first reactant (B) purge or removal of non-reacted reactants and reaction by-products (C) self-terminating reaction of the second reactant (D) purge of second reactant/by-products. This is known as one cycle. Growth rates are typically characterized in terms of growth per cycle

(Å/cycle). Typical parameters to optimize growth include pulse times for each precursor to ensure maximum surface coverage, indicated by saturation in the growth rate with any further increase in pulse time. The purge time in between pulses ensures complete removal of the unreacted precursor. Any CVD like growth can be detected by increased growth rate and non-uniform oxide thickness. The substrate temperature is also critical and typically an ALD window, or temperature range exists within which the growth is insensitive to temperature. Deposition should always be done in this window. Once the recipe is optimized, knowing the growth per cycle, the number of cycles gives an accurate estimate of the oxide thickness deposited. The primary benefit of ALD is conformal deposition with good thickness control and uniformity. In this dissertation, a

Picosun SunaleTM reactor ALD system is used.

7.7 High-κ dielectrics for ion impermeability in in-vivo Biosensors

An interesting application investigated in this dissertation is the use of high-κ dielectrics to improve stability of MOS transistors in the presence of high alkali ion environments as is typical for bio-sensing in bodily solutions. In this work the use of aluminum oxide (Al2O3) deposited using ALD is investigated as a replacement to

184 conventional thermally grown silicon oxide (SiO2). Metal-oxide-semiconductor (MOS) capacitors are used here as diagnostic test structures to detect and quantify the alkali ion concentration within the oxide.

7.7.1 FET based biosensor operating principle

A representative field effect transistor (FET) protein sensor is illustrated in Fig.

7.26. Conventional FET operation consists of a bias applied to the gate electrode resulting in a charge of opposite polarity induced in the semiconductor channel due to the capacitive action of the gate-oxide-semiconductor structure. The accumulation of charge in the channel significantly raises its conductivity. The application of a voltage between the drain and source electrodes thus results in a current flow through the channel.

For use as biosensors, the gate metal is replaced by a functionalized oxide surface

Positive VG Analyte S Receptor RE Metal S D

e e e e e e - e - e- e- - Functionalized n+ - n+ - - - surface p Sii-Substtratte

Dielectric oxide VD S Figure 7.26 A field effect transistor protein biosensor is presented. When a target protein binds to the receptor, it induces charges in the substrate (electrons as pictured here), causing a change in the current flow between the source and drain.

185 with analyte-specific affinity reagents (receptors such as antibody, enzyme, cell), leaving the gate effectively “floating” in direct contact with the solution being tested. Binding of charged analytes (protein to be detected) to these surface receptors results in a cha nge in the charge induced in the channel, which manifests as a change in the drain current. Since a gate metal is absent, a voltage can be applied to the electrolyte through a reference electrode (RE) to shift the baseline transistor bias condition and maximize transistor gain.

When the gate-source voltage (VGS) is greater than the drain-source voltage (VDS) the transistor operates in the linear region and the drain current-voltage relationship is given by:

(7.21)

As the drain-source voltage is increased and exceeds VGS-Vth , the device enters saturation and the drain current-voltage relation is given by:

(7.22)

Here, µ is the electron/hole mobility, Cox is the oxide capacitance given by , W

and L are the width and length of the gate, is the oxide permittivity, A is gate area, is oxide thickness and Vth is the threshold voltage.

The threshold voltage is the minimum gate voltage to turn on the transistor and is given by:

(7.23)

where, is the work function difference between the metal and semiconductor, is a potential energy controlled by the doping density, is the silicon permittivity, and is

186

the substrate doping concentration. is the fixed oxide charge introduced in the oxide

during growth and is constant for a device. is the mobile ion charge, which is of

primary concern in biosensor operation. It is clear that changes in results in changes

in device threshold voltage and hence output current of the device. This will conflict with

changes due to adsorbed protein analyte and result in erroneous operation.

7.7.2 Challenges with FET-based biosensing

A primary challenge for realization of FET based sensing has been the screening

of protein charges by the ions in the solution (Fig. 7.27). Potential changes within a

Debye length from the interface can be detected. However, the Debye length is reduced

as the ionic strength of the solution increases. Since typical dimensions of antibodies are

longer than Debye length at physiological buffer concentrations, it was largely believed

that such sensors would not work.

(b)

(a) Figure 7.27 (a) Debye length limitation for biosensing using an FET [185]and (b) reduction in sensor output with increased physiological buffer solution (PBS) concentration [152]

187

However it has been shown that this is not true [152]. The fallacy of the theory is due to the incorrect assumption that antibodies are rigid bodies and they adsorb to surfaces only at their C3 domain. Further, protein engineering, receptor selection/design and analyte orientation can be used to increase analyte-surface proximity. Figure 7.28 summarizes the various methods investigated to improve FET protein sensing using protein engineering.

Change receptor topography to tune orientation of analyte charge [186] Differential epitope recognition

Use of antibody fragments instead of antibodies as receptor [188]

Interfacial polymer film links FET surface to the analyte specific receptor [187] APTES: typically used since it has high reactivity with metal oxides. Has 3 alkoxy groups which bonds with other APTES molecules forming 4-5 layer thick interface

APDMES: only 1 alkoxy group which bonds with interface or with one APDES molecule. Reduced layer thickness

Figure 7.28 Various methods to overcome the Debye length challenge in protein sensing using FETs

A second challenge is the instability of Silicon MOSFET in physiological buffer solution which will be addressed here. Figure 7.29 shows comparison of the current of an

188

AlGaN HFET and a Si MOSFET soaked in PBS for several hours. The Si MOSFET shows a drift in current. High-κ dielectrics are investigated next using MOS capacitors as test structures to determine alkali ion penetration into the oxide as a result of soaking in

PBS solution.

Figure 7.29 Drift in current of Si MOSFET with time when exposed to PBS solution

7.7.3 Experimental

MOS capacitors are fabricated with p-type Si substrate. Prior to deposition, the wafers were cleaned using the standard clean process consisting of RCA1 (1NH4OH:

o 1H2O2: 5 de-ionized (DI) water at 70 C for 10 minutes) and RCA2 (1HCl: 1 H2O2: 5 DI at 70oC for 10 minutes). This was followed by a 1 minute dip in 1HF:10 DI and a 1 minute DI rinse. The ALD pulsing sequence for one cycle was 0.1 sec. trimethylaluminum (TMA) pulse, 4 sec. N2 purge, 0.1 sec. H2O pulse, and 4 sec. N2 purge. Typical ALD deposition rates of 0.8 Å/cycle were obtained. The samples were then subjected to various anneals to determine the optimum anneal condition with minimal hysteresis and interface state density. The various anneal conditions used were

189

o o 450 C in forming gas (10% H2, 90% N2), 600 C in oxygen ambient and 700, 800 and

900oC in nitrogen ambient. Aluminum metal was deposited on the topside and patterned by photolithography and lift-off to obtain square electrodes with various areas of

275×275, 550×550, 1100×1100, 1650×1650 and 2200×2200 µm2. The square electrodes were designed additionally with holes and slots to permit various levels of ion permeation and a control electrode was included with no holes. Finally, aluminum metal was deposited on the backside of the wafer to complete the capacitor fabrication. This was followed by a post-metallization anneal at 450oC for 10 min. in nitrogen ambient.

7.7.4 Oxide Quality Characterization

The oxide quality was characterized by hysteresis and multifrequency capacitance-voltage measurements using an Agilent 4284 LCR meter. Hysteresis characteristics are obtained by sweeping the capacitor from depletion to accumulation and then reversing the sweep direction. Figure 7.30(a) shows the hysteresis characteristics obtained for samples subjected to various anneal conditions. All measurements were done at 100 kHz frequency. As-grown and low temperature forming gas annealed (FGA) samples show a hysteresis of 120 mV due to slow traps in the oxide.

After annealing between 600 to 800oC, the oxide traps are reduced and no hysteresis is observed. Annealing at 900oC results in a large hysteresis indicative of the formation of a large number of oxide traps as the oxide is annealed at temperatures above the crystallization temperature (850oC). Ellipsometry was used to measure the oxide thickness. For the comparative study between ALD Al2O3 and thermal SiO2, a target thickness of 100 nm was chosen. As-grown Al2O3 was measured to be 103 nm. After

190

annealing up to 800oC the thickness reduced to 101 nm while annealing at 900oC resulted

in a larger thickness reduction down to 93 nm. The dielectric constant for the annealed

samples is calculated to be 8.65 from C-V measurements.

(a) (b)

Figure 7.30(b) shows multi-frequency capacitance-voltage (C-V) measurements

for ALD Al2O3 under various anneal conditions. It should be noted that the drop in

191 accumulation capacitance at a frequency of 1 MHz is due to the series resistance.

Frequency dispersion in the depletion region is due to a frequency dispersive contribution to capacitance by interface traps which decrease with increasing frequency. Negligible dispersion is observed for all samples except for the 800oC anneal sample. This correlates with an order of magnitude increase in interface density from ~1010 cm-2 eV-1 for anneals at 700 oC to ~1011 cm-2eV-1 range for anneals at 800oC. Thus, annealing at 700oC in nitrogen ambient was found to be the optimal condition and was used for all the subsequent ALD Al2O3 samples used in this study.

Thermally grown silicon oxide (SiO2) was used as the control sample. The sample was prepared using the same p-doped substrate and wafer cleaning procedure as described above for ALD Al2O3. Dry silicon oxide was grown in an atmospheric tube furnace at 1050oC with an oxygen ambient followed by a 20 minute nitrogen anneal at the same temperature. Multi-frequency C-V curves for SiO2 indicate a good oxide quality with negligible frequency dispersion due to interface states [Fig. 7.30(c)]. The oxide thickness was measured to be 116 nm with a calculated dielectric constant of 3.8.

Reducing the oxide thickness further increases the capacitance and hence the sensitivity of a bio sensor. The MOSFET channel current is directly proportional to the

oxide capacitance, Cox. Where Thus, increasing ε (using high-k dielectrics such

as Al2O3) while concurrently reducing the oxide thickness, tox, provides a large sensitivity boost, critical for biosensing applications. MOS capacitors using Al2O3 as their dielectric and with reduced thicknesses were obtained by repeating the ALD process and reducing the number of cycles to obtain samples with target oxide thicknesses of 50, 25 and 10 nm,

192 in addition to the 100 nm sample. The measured oxide thickness values using ellipsometry were 52, 30 and 12 nm, respectively. The effect of increased dielectric constant and reducing oxide thickness is illustrated in Fig. 7.30(d) where C-V plots

(swept from depletion to accumulation and back) obtained from MOS capacitors formed with various Al2O3 oxide thicknesses and SiO2 as the gate dielectric are juxtaposed.

Excellent dielectric properties are observed for all ALD oxides with no observable hysteresis.

7.7.5 Results and Discussion

The in vivo physiological environment can be simulated by conducting experiments in physiological buffer solutions (pH 7.4, 0.15M Na+,K+). Natural in vivo protein environments contain comparable concentrations of alkali ions at a similar pH.

Hence, impermeability of ions or immunity of transistor electrical response to these environments serves as a viable proof of applicability of Si-based FET sensors for in-vivo measurements.

7.7.5.1 Triangular Voltage Sweep Technique

Mobile ion contamination in semiconductor technology is generally performed on a MOS capacitor using C-V bias temperature stressing (BTS) or the triangular voltage sweep (TVS) technique. Initially, the BTS technique was utilized. However, charge injection into the Al2O3 dielectric with stress, resulted in shifting of the C-V curve in a direction opposite to that expected due to Na+ ion contamination. Thus this technique was rendered unsuitable for use with high-κ dielectrics. Hence, the TVS method was preferred. Further, the TVS technique has a higher sensitivity than BTS. TVS also leads

193 to reduced measurement times since measurements are done at high temperature, unlike

BTS which requires sequential heating, stress and cooling prior to the C-V measurement.

Permeation of mobile charges into the oxide can be quantified using the TVS method.

The TVS technique is based upon measuring the charge flow through the oxide at an elevated temperature in response to an applied time-varying voltage. The MOS sample is heated to a temperature (~250oC) where the mobile ions have sufficient thermal energy, and thus mobility, to respond to an applied bias. The MOS capacitor is stressed for 5 minutes at a voltage that generates about 1 MV/cm electric field across the oxide. This moves all the mobile ions to the capacitor plate charged with the opposite polarity. A triangular voltage ramp [Fig. 7.31(a)] is subsequently applied to the gate of the capacitor.

The ramp frequency should be slow enough so that the ions can drift through the oxide.

Hence, a quasi-static capacitance-voltage C-V measurement is performed. This generates a displacement current in the capacitor. As the voltage crosses from positive to negative or negative to positive, a peak in the measured capacitance is observed. The capacitor is next stressed at an opposite polarity bias and a reverse voltage sweep is applied. The capacitance is obtained by measuring the charge flow (ΔQ) through the oxide when a time varying voltage is applied (ΔV) given by ΔQ/ΔV. The peaks in the two sweep directions are generally not identical with a larger peak observed when sweeping from positive to negative bias (depletion to accumulation in this case) This is due to the larger number of Na+ ion traps at the metal-oxide interface than the oxide-semiconductor interface [153]. Next, a high frequency C-V measurement is performed, where the ions do not have sufficient time to respond, and no significant peak due to mobile ions is

194 observed. Using this as the baseline, the area between these two curves (high frequency and low frequency) is determined by integration to obtain the mobile ion charge density within the oxide [Fig. 7.31(b)]. Finally, MOS capacitors with ALD Al2O3 and thermal

SiO2 gate dielectrics were soaked in PBS solution for varying amounts of time and subsequently measured by the TVS technique.

Voltage

Stress +V Voltage Ramp

+ 0 + A+ A Time

Voltage Slope -V Stress

(a) (b) Figure 7.31 (a) Triangular voltage ramp technique for detecting alkali ions (A+), and (b) illustration of the peak obtained with low frequency C-V measurements due to mobile ions and calculation of ion concentration.

7.7.5.2 Thermal Silicon Oxide versus ALD Aluminum Oxide

Figure 7.32(a) shows the result of Triangular Voltage Sweep measurements for a

o typical 100nm SiO2 MOS capacitor at 250 C. Ramp rates of 0.5 V/sec were used for all the measurements in this study. TVS measurements were conducted prior to dipping in

PBS solution and after soaking in PBS for 30 min, 60 min, and 90 min. It should be noted

195

that thermal SiO2 shows a mobile ion peak prior to soaking in PBS. This is due to

incorporation of some alkali ion contamination from the tube furnace during thermal

oxidation. Additionally, as the soak time in PBS is increased, a clear linear increase in the

mobile ion peak is observed. This indicates significant penetration of ions from the PBS

solution into the SiO2 oxide. The area between consecutive curves quantifies the

increased mobile charge (alkali ions) after each soak and is determined by numerical

(a) (b)

Figure 7.32 (a) Triangular voltage sweep measurements of a typical thermal SiO2 MOS capacitor at 250oC, and (b) relationship between increases in alkali ions concentration with increasing soak times in PBS for the control SiO2 based capacitor. The line is joins of the measured data.

integration. Table 7.4 and Fig. 7.32(b) tabulate the increase in alkali ion penetration into

SiO2 MOS capacitors with increasing soak times in PBS solution.

Table 7.4 Relationship between increased alkali ion concentration into thermal SiO2 oxide (~100nm) and soak time in physiological buffer solution (PBS)

Time (min) 0 30 60 90 ∆[Alkali ions] 0 1.77 3.69 10.87 (× 1010cm-2)

196

The experiment was then repeated with a 100 nm thick ALD Al2O3 gate dielectric. The results are depicted in Fig. 7.33(a). No response due to alkali ion penetration is observed. The MOS device was next soaked for longer intervals of time up to 24 hours and the immunity to alkali ions penetration was confirmed for all time durations studied here. The three gate electrode topologies, holes, slots and no holes also showed no measurable differences either (not shown here).

(a) (b)

197

7.7.5.3 ALD Al2O3 Thickness Study

Reduction in oxide thickness provides an additional benefit of increasing capacitance, hence increased sensitivity to analyte charge. This is particularly critical due to the low signal typically generated in such sensors and the exponentially increasing signal with decreasing thickness. Hence, MOS capacitors with reducing ALD Al2O3 oxide thicknesses were also fabricated and soaked in PBS as described above. TVS measurements were performed to test alkali ion penetration into these oxides. Figure

7.33(b, c, d) depicts the TVS measurement results for 50 nm, 25 nm, 10 nm Al2O3 thicknesses, respectively. No mobile ion response is observed for soak times in PBS up to

24 hrs for any of these thinner Al2O3 oxide thicknesses.

Thus, the long-term stability of Si MOSFETs in high osmolarity biological buffers is improved with the use of Al2O3 as the gate dielectric. Al2O3 can also be used with other high dielectric constant materials forming nanolaminates, to further boost the sensitivity.

198

CHAPTER 8 TUNNELING FIELD EFFECT TRANSISTORS

High power consumption is a growing concern with current complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs). Supply voltage scaling has not kept pace with device scaling, due to rising leakage currents as the threshold voltage (Vth) is reduced. With Vth fixed, a reduction in VDD will result in reduced gate overdrive and low ON currents. VDD directly impacts the total power density. The dynamic and static power consumption is given by:

(8.1)

(8.2) where, = frequency, is the total capacitive load, and is the sum of all leakage currents in the device in the off state.

(a) (b) Figure 8.1(a) Increase in leakage current with voltage scaling for an MOS transistor due to the lower limit on sub-threshold slope (b) comparison of various candidate technologies to improve MOSFET performance [189]

199

Threshold voltage scaling issues arise from the fundamental limit in the steepness

of the transition slope from off to on state represented by the inverse subthreshold slope.

The inverse subthreshold slope is given by: . where, is the

depletion layer capacitance, which has a lower limit of or 60 mV/decade at room

temperature. Thus, threshold voltage scaling results in an increase in leakage currents as

illustrated in Fig. 8.1 (a). Hence, alternate techniques for carrier injection, instead of

thermionic injection need to be considered. Tunnel field effect transistors were proposed

as an alternative, utilizing interband tunneling as the injection mechanism, and had the

ability to achieve low inverse subthreshold slopes below 60 mV/decade [154], [155].

(a) (b)

200

The basic structure of a TFET is shown in Fig. 8.2(a). It is a gated p-i-n diode operating in reverse bias with the intrinsic region serving as the channel region.

Application of a positive gate bias induces an n-channel and creates a p-n junction at one end. If the p side is highly doped, the resulting p-n junction has a thin depletion region, similar to a Zener diode. Application of a drain bias further increases the band bending at the junction and results in the flow of a reverse tunneling current. Figure 8.2(b) shows a simulated band diagram for a Si TFET with 1V applied at both gate and drain. The resulting tunneling action is illustrated. This is an ambipolar device. Application of a negative gate bias alternately can form a tunnel junction between the drain side and the induced p-channel. In order to suppress this ambipolar behavior the source and drain are often doped asymmetrically.

The TFET device structure was originally proposed by Quinn et al. [156] to study the electronic properties of a two-dimensional inversion layer formed in MOSFETs.

Reddick and Amaratunga [157] referred to this device as a silicon surface tunnel transistor and first discussed the use of these devices as an alternate to MOSFETs.

Hansch et al. [158] reported on the use of a δ-doping layer to improve tunnel currents.

Simulations also showed the benefit of using SiGe in the delta-doped region [159].

However, the experimental results utilized thermally grown silicon oxide with polysilicon as the gate and high gate biases up to 8V were required to produce a current density of

1×10-3 µA/µm [160]. Lateral TFETs using strained-Ge channel on a ultra thin-SOI substrate with double gate action exhibited on currents of 300 µA/µm for a gate and drain bias of 3V [161]. More recently lateral TFETs using spike anneal for source/drain and

201 utilizing high-k/metal gate obtained ON currents of 100 µA/µm with a drain bias of 1V and gate overdrive of 2V [162]. Silicon vertical p-channel [163] and n-channel TFET

[164] were recently reported using thermal oxide as gate dielectric and demonstrated on-

5 currents of 1 µA/µm and 0.02 µA/µm respectively with ON/OFF ratio's of 10 for VDD of

1V.

As can be seen from previous results, although silicon TFETs have low leakage currents, the ON-currents are considerably low. Hence, III-V channel materials with lower bandgaps have also been investigated to further boost the ON-currents [165].

Recent work on InGaAs homojunctions shows ION of 24 µA/µm for In0.53Ga0.47As and

ION of 60 µA/µm for In0.7Ga0.3As both at VDS = 0.75V [166]. However, these devices also exhibit significantly high OFF currents, which increases as the bandgap is reduced. The leakage floor is due to SRH generation-recombination which is confirmed by the reverse leakage of the p-i-n diode. The use of the InAs/GaSb broken gap heterostructure was also shown to boost ON-currents [167]. GaAs0.35Sb0.65/In0.7Ga0.3As heterojunctions showed

3 ION of 190 µA/µm at VDS of 0.75V with ON/OFF ratio of 10 [166].

8.1 Device Structure

In this work two types of TFETs were investigated. Si/SiGe TFETs as an extension of the prior work on Si/SiGe RITDs and TFETs utilizing the broken gap

GaSb/InAs structure.

202

8.1.1 Si/SiGe TFET

o 100 nm n+ Si 320oC 100 nm n+ Si 350 C n δ-doping 500-350oC n δ-doping 500-320oC 1 nm Si 500oC 300 nm i Si 500oC 30 nm p-Si Ge 500oC 100 nm p+ Si 650-500oC 0.9 0.1

Si p+ substrate (<0.005 ohm-cm) Si p+ substrate (<0.005 ohm-cm) (a) (b) Figure 8.3 Structure for MBE grown p-TFETS (a) Sample M1 is an all Si TFET incorporating a n δ-doping region with a 300 nm channel (b) Sample M2 comprises of a 30 nm Si0.9Ge0.1 channel also with an n δ-doping region

(b) (a ) Figure 8.4 Band diagram for (a) sample M1 with all Si channel and (b) sample M2 with Si0.9Ge0.1 channel

The first two structures investigated were p-channel TFETs grown using LT-

MBE. The first (sample M1) is a Si only p+-i-n+ structure with a 300 nm channel and incorporating an n-type δ-doping spike in the drain side as shown in Fig. 8.3(a). The

203 second structure (sample M2) incorporates a Si0.9Ge0.1 channel to lower the tunneling barrier. However, critical thickness limitations restrict the channel length to 30 nm. A 1 nm Si region is added below the n δ-doping to reduce dopant diffusion. The growth temperature of the structure is 500oC for the p region and channel region and is dropped down to 320oC for sample M1 and 350oC for channel M2, to reduce n-dopant segregation.

(a) (b) Figure 8.5 Simulation results for (a) drain current-drain voltage and (b) drain current- gate voltage characteristics of all Si channel p-TFET (sample M1)

The simulated band diagram for each structure at equilibrium and with application of gate and drain bias is illustrated in Fig. 8.4. The δ-doping peak is assumed to be 1×1021

-3 cm .The drain current-drain voltage (ID-VD) and drain current-gate voltage (ID-VG) characteristics for each structure is shown in Fig. 8.5 and Fig. 8.6. Non-local band to band tunneling model is utilized. The metal workfunction is assumed to be close to midgap and is chosen as 4.5 and the dielectric constant of the gate oxide is chosen to be

204

15. ION of 45 µA/µm and 89 µA/µm are obtained for structures M1 and M2 at

VDD=1V. As expected, lowering the bandgap of the channel increases the tunneling current.

(a) (b) Figure 8.6 Simulation results for (a) drain current-drain voltage and (b) drain current-gate voltage characteristics of Si0.9Ge0.1 channel p-TFET (sample M2)

In order to increase the on-current, the bandgap near the tunneling junction should be reduced further. However the Ge content is restricted by critical thickness. Hence, a mixed Si0.6Ge0.4/Si channel is chosen, similar to the RITD design with the SiGe region close to the tunneling junction. These structures were grown using CVD. The design of the resulting pTFET (sample CP) and nTFET (sample CN) is illustrated in Fig. 8.7.

205

25 nm n+ Si 100 nm n+ Si

96 nm i Si n δ-doping

1 nm Si 4 nm Si0.6Ge0.4 4 nm Si Ge p δ-doping 0.6 0.4 95 nm i Si 1 nm Si0.6Ge0.4 100 nm p+ Si 5×1019 cm-3 100 nm p+ Si 5×1019 cm-3 Si p+ substrate Si p+ substrate

(a) (b) Figure 8.8 Structure for CVD grown TFETs (a) Sample CM is an n-TFET incorporating a p δ-doping region with a 100 nm Si/SiGe channel (b) Sample CP is a p-TFET incorporating a n δ-doping region with a 100 nm Si/SiGe channel

(a) (b) Figure 8.7 Band diagram for (a) Sample CM, n-TFET incorporating a p δ-doping region with a 100 nm Si/SiGe channel (b) Sample CP, p-TFET incorporating a n δ-doping region with a 100 nm Si/SiGe channel

Figure 8.8 shows the banddiagram for the two structures at equilibrium and with gate and drain bias applied.

206

8.1.2 Broken Gap TFET

+ 18 -3 + 18 -3 GaSb p 100 nm 5×10 cm GaSb p 100 nm 5×10 cm undoped 5 nm GaSb undoped 10 nm GaSb undoped 1 nm AlSb

undoped 50 nm In0.8Ga0.2As undoped 5 nm GaSb

18 -3 undoped 50 nm In Ga As 1 µm InAs buffer 2×10 cm 0.8 0.2 18 -3 200 nm n+ GaAs 2×1018 cm-3 1 µm InAs buffer 2×10 cm GaAs n+ substrate 2-5×1018 cm-3 200 nm n+ GaAs 2×1018 cm-3

GaAs n+ substrate 2-5×1018 cm-3 (a) (b) Figure 8.10 n-TFET broken gap heterostructures investigated with (a) GaSb/InGaAs tunneling junction (b) AlSb included in GaSb to create a quasi- bound state

(a) (b) Figure 8.9 Band diagram for n-TFET Broken gap heterostructures investigated with (a) GaSb/InGaAs tunneling junction (b) AlSb included in GaSb to create quasi-bound state

207

The GaSb/InAs material system is explored to improve the ON current. As discussed earlier, the system is unique due to its 'broken gap' band alignment and the heterostructure being lattice matched with a lattice constant of 6.1Å [167]. Two n-TFET structures were investigated in this work as shown in Fig. 8.9 and their corresponding band diagrams are illustrated in Fig. 8.10. Pure InAs has a conduction band below the valence band of GaSb, resulting in a tunnel diode operation, and tunneling occurring immediately upon the application of drain bias. Inclusion of Ga in the channel to form

InGaAs, induces a bandgap increase and raises the conduction band above the valence band of GaSb. Now a gate bias is necessary to form the broken bandgap. Too large a Ga content however will suffer from critical thickness concerns hence In0.8Ga0.2As is chosen here. The second n-TFET structure includes an AlSb barrier in the GaSb region forming a quasi-bound state which could increase the tunneling current density [168].

GaSb p+ 100 nm 5×1018 cm-3

undoped 50 nm Al0.6Ga0.4Sb

500 nm n+ InAs 5×1018 cm-3

1 µm InAs buffer 2×1018 cm-3 200 nm n+ GaAs 2×1018 cm-3 GaAs n+ substrate 2-5×1018 cm-3

(a) (b) Figure 8.11 p-TFET broken gap heterostructure with AlGaSb/InAs as tunneling junction (a) device structure schematic and (b) simulated banddiagram

208

The p-TFET structure (Fig. 8.11) utilizes Al0.6Ga0.4Sb as the channel material.

Application of a negative gate bias, moves the valence band upwards with respect to the

InAs conduction band forming a tunneling junction between the InAs and Al0.6Ga0.4Sb.

The top GaSb serves as the ohmic contact.

8.2 Device Fabrication Process

The device fabrication begins by defining the mesa with the first mask level. The mesa is etched using photoresist as the etch mask. For the Si/SiGe TFETs, the devices undergo a standard clean process next, prior to gate oxide deposition. This consists of

o RCA1 clean consisting of NH4OH:H2O2:H2O (1:1:5), heated at 70 C for 10 minutes

o followed by RCA2 clean consisting of HCl:H2O2:H2O (1:1:5), heated at 70 C for 10 minutes. An HF dip in 1:10 HF for 1 minute is performed just prior to gate oxide deposition, to remove any oxide formed during the clean. For the broken gap TFETs, the devices are soaked in (NH4)2S for 10 minutes followed by a 1 min rinse in DI water prior to gate oxide deposition. Atomic layer deposition (ALD) is used to deposit an

Al2O3/HfO2 gate stack which forms a conformal gate oxide around the mesa. Al2O3 is deposited first and serves to increase the oxide barrier, to reduce tunneling through the oxide. Al2O3 also form a more stable oxide with Si in comparison with HfO2. Titanium

Nitride (TiN) is deposited next using reactive sputtering followed by Al to form the conformal gate metal. TiN is used to obtain a midgap workfunction while Al is added for ease of direct probing since it is a softer metal. A second lithography step is used to etch the gate metal between devices (gate isolation). Bisbenzocyclobutene (BCB) is spin coated to obtain a planarized surface, followed by etch back process to just reveal the top

209 of the mesa. The gate oxide and gate metal on top of the mesa are now etched. A third lithography step is used to define the top metal contact and e-beam evaporation is used to form an ohmic contact to the top of the mesa. The BCB is now stripped off using dry etching. Finally, backside metal is deposited and a gate metal anneal performed using rapid thermal anneal (RTA). The schematic of the final device structure is illustrated in

Fig. 8.12 along with a photo micrograph of the final fabricated device.

8.3 Process Optimization

Ni/Cr/Al/Cr (drain) TiN/Al drain gate (gate) n+

Al2O3/HfO2 i

p+ Si substrate (b) Al (source) (a) Figure 8.12 (a) schematic of fabriacted TFET and (b) photomicrograph showing final device

8.3.1 Mesa etch

Silicon wet etch is normally done using HF:HNO3:DI water. However due to the high doping levels, especially in the δ-doped regions, etching may be inhibited and a change in the color of the surface is observed with increased etch time [Fig. 8.13(a)], without any change in etch depth or even reduction in depth, indicating formation of an oxide. However, use of buffered HF dip does not have any effect. Hence ICP-RIE was 210 used to dry etch with a CF4/O2 plasma. A comparison of tunnel diode performance with wet and dry etch for a Si/SiGe tunnel diode is shown in Fig. 8.13(b). No significant increase in valley current is observed. The small difference in performance is due to the two samples being from different locations on the wafer.

(a) (b) Figure 8.13 (a) Wet etching effect on highly doped silicon surface (b) dry versus wet etching effect on tunnel diode performance

For the GaSb/InAs mesa etch, several etch recipes were evaluated. The primary issue was the formation of antimony oxide (Sb2O3) during the wet etch of Sb containing compounds, which was not soluble in most etches [169]. The first etch attempted was using HCl:H2O2:H2O. However this solution attacked the metal even when protected by a photoresist mask on top as shown in Fig. 8.14(a). A H3PO4:H2O2:H2O etch [170] was tried next. In this case a Sb2O3 deposit was obtained as shown in Fig. 8.14(b). Addition of tartaric acid could possibly dissolve this oxide. Hence both HCl:H2O2:H2O:Nak tartrate

(7 ml: 80 ml: 100 ml: 7.5 gm) [171] and H3PO4:H2O2:H2O:NaK tartrate (5 ml: 10 ml: 100 ml: 7.4 gm ) [170] were tried. However, not much change was obtained with this 211

addition. The NaK tartrate tends to precipitate out over time and stirring the NaK

tartrate:H2O solution for several hours with a stirrer can be tried to get better results. A

dry etch using ICP-RIE with a BCl3/Ar mixture was developed. Dry etching of InAs

using the same plasma however results in the formation of InCl3 residue which inhibits

etching. Typically heating the substrate can remove this residue however the ICP-RIE

tool used can only be heated upto 50oC. Hence the GaSb dry etch (which stops on InAs)

was followed by an InAs wet etch using H3PO4:H2O2:H2O. Finally an NH4OH etch

(a) (b)

212

(NH4OH:H2O 1:2) was attempted for etching GaSb and this was found to be effective, without any Sb oxide formation, and can be used without the need to protect the metal with photoresist. This etch is also selective and stops on InAs.

8.3.2 Gate oxide using atomic layer deposition

100 Hz- 1MHz

(a) (b)

Figure 8.15 Oxide characterization of 100 nm Al2O3 deposited by ALD (a) multi-frequency C-V characteristics showing no frequency dispersion (b) multi-frequency G-V plots (c) interface state density calculated using conductance technique

(c)

Initial optimization of gate oxide was done for Al2O3 as gate dielectric as detailed in chapter 7. The pulse and purge times used for the two precursors [trimethylaluminum

(TMA) and water] are 0.1 sec and 4 sec with a deposition temperature of 300oC.

213

Multifrequency C-V and normalized G-V curves for a 100 nm oxide along with calculated Dit is shown in Fig. 8.15. Very good interface quality is obtained with interface state density in the 1010 cm-2ev-1 range. In order to boost the dielectric constant further the use of HfO2 instead of Al2O3 is preferable since HfO2 is known to have a much higher dielectric constant of about 25.

as-grown after anneal

90 µm diameter dot

(a) (b)

The precursors used for HfO2 [172] are (MeCp)2Hf(OMe)(Me) and H2O where

Cp=C5H5 and Me=CH3. Initial deposition conditions used were one cycle comprising of 2 pulse of Hf with pulse and purge times of 0.4 sec/4 sec followed by 1 pulse of water (0.2 sec/4 sec [Run 1]). The deposition temperature was 350oC. 250 cycles resulted in a thickness of 7.4 nm as measured by ellipsometer. Thus, a growth rate of ~0.29 Å/cycle was obtained. The dielectric constant obtained from C-V measurements was 7.5 [Fig.

8.16(a)]. The pulse and purge times were increased to 2 pulses of Hf precursor (0.5/5

214 sec) and 1 pulse of H2O (0.6/5 sec) [Run 2]. 250 cycles now resulted in 9.1 nm with the growth rate increased to 0.364 Å/cycle indicating the surface was under dosed in the first case. The dielectric constant went up to 8.65. Metal anneal at 450oC in nitrogen for 1 minute using RTA resulted in significant reduction of Cox and hence dielectric constant.

The interface quality on the other hand was improved.

(a) (b) o Figure 8.17 (a) Effect of post metal anneal at 400 C for 1 min in N2 and (b) effect of post oxide deposition anneal on Al2O3/HfO2 gate stack with TiN/Al gate metal

215

(a) (b)

Figure 8.18 Oxide characterization of Al2O3/HfO2 gate dielectric stack with 5/5.5 nm thickness deposited by ALD (a) multi- frequency C-V characteristics showing no frequency dispersion (b) multi-frequency G-V plots (c) interface state density calculated using conductance technique

(c)

An Al2O3/HfO2 stack was tried to prevent formation of SiO2, which is believed to be the cause of the low dielectric constant. The H2O pulse and purge times were further increased (2 pulses Hf: 0.4/4 sec and 1 pulse H2O 0.8/8 sec) to ensure sufficient dose.

o o Al2O3 was deposited at 300 C and then the chamber temperature was raised to 350 C for the deposition of HfO2. The effect of oxide and metal anneal on test capacitor structures grown on bare p-Si substrate is illustrated in Fig. 8.17. TiN/Al (25 nm/25nm) gate metal stack is deposited using sputtering. Post metal anneal is found to be essential. However, post oxide anneal results in a Vth shift and an increase in hysteresis and is not performed

216

on the TFET samples. The multifrequency capacitance and conductance plots along with

interface state density estimate using the conductance technique, for a sample with

400oC metal anneal and no oxide anneal is shown in Fig. 8.18. The targeted oxide

thickness for this layer was 2.5 nm Al2O3 (35 cycles) and 7.5 nm HfO2 (188 cycles). The

stack thicknesses obtained from spectroscopic ellipsometry were 5 nm Al2O3 and 5.5 nm

HfO2. The dielectric constant for the stack was 11.4. Assuming a Al2O3 dielectric

constant of 8.5 this gives a HfO2 dielectric constant of 16.5.

8.4 Results

The results for the MBE grown p-TFETs are presented first. The experimentally

obtained drain current-drain voltage (ID-VDS) and drain current-gate voltage (ID-VGS) are

shown in Fig. 8.19 and 8.20 respectively. All currents are normalized by the mesa

circumference. A maximum ION of 0.05 µA/µm at VGS = -2.5V and VDS = 2.5V is

obtained for sample M1 which is an all silicon p-TFET with an n δ-doped region. ION for

(a) (b)

Figure 8.19 Experimental drain current-drain voltage (ID-VD) characteristics for MBE grown p-TFET devices with (a) 300 nm Si only channel and (b) 30 nm Si0.9Ge0.1 channel

217

structure M2 with a Si0.9Ge0.1 channel and n δ-doped region is improved to 4.8 µA/µm at

VGS = -1.5V and VDS = 2V. However the shorter channel results in increased reverse

leakage current as illustrated in the p-i-n diode I-V characteristics (Fig. 8.21). The

4 ION/IOFF ratio is also severely degraded from 10 in M1 to 5 in M2.

5 10 1400

1200 ) 4 Structure M1 2 10 1000 Structure M2 800 ) 3 2 10 600 400 2 10 200

Current Density (A/cm 0 1 -200 10 0.0 0.2 0.4 0.6 0.8 1.0 Voltage (V)

100

10-1 10-2

10-3 CurrentDensity (A/cm 10-4 10-5 0 -1 -2 -3 -4 -5 Voltage (V)

Figure 8.21Comparison of reverse leakage current for the two MBE grown p- TFET structures. Inset showing forward and reverse I-V characteristics for 300 nm channel device

(a) (b) Figure 8.20 Experimental drain current-gate voltage (ID-VG) characteristics for MBE grown p-TFET devices with (a) 300 nm Si only channel and (b) 30 nm Si0.9Ge0.1 channel

218

(a) (b) Figure 8.22 (a) Drain current-drain voltage and (b) drain current-gate voltage characteristics for CVD grown p-TFET with a composite Si0.6Ge0.4/Si channel

The CVD grown p-TFET results are presented in Fig. 8.22. The ON-currents are lower than that for the p-TFET with the Si0.9Ge0.1 channel grown with MBE. At the same gate bias of -1.5V and drain bias of 2V, the drain current is 0.8 µA/µm compared to 4.8

µA/µm in the later. This can be expected since the δ-spike peak doping density strongly affects the tunneling current. MBE grown samples, with their non-equilibrium growth mode can achieve electrically active dopants exceeding the solid solubility limit.

However, in CVD growth the maximum active dopants is restricted by the solid solubility limit and has been a reason for the lower peak current densities in tunnel diodes grown with this technique. The addition of larger Ge fraction helps boost the current. Further, the larger channel length of 100 nm reduces the p-i-n diode leakage current and improved

4 ION/IOFF ratio of ~10 is obtained. The diode leakage currents for the pTFET and nTFET structures is presented in Fig. 8.23. No gate modulation was observed with the n-TFET

219 structures while modulation with negative gate bias was observed (Fig. 8.24) and this needs to be further investigated.

(a) (b) Figure 8.23 p-i-n diode leakage current characteristics for 100nm Si0.6Ge0.4/Si channel, CVD grown (a) pTFET and (b) n-TFET structures

(a) (b) Figure 8.24 (a) Drain current-drain voltage and (b) drain current-gate voltage characteristics for CVD grown n-TFET with a composite Si0.6Ge0.4/Si channel showing gate modulation only with negative gate bias

220

No gate modulation was obtained for all the broken gap heterostructure devices and ohmic-like I-V characteristics were obtained for both tunnel diode and tunnel-FET structures. It is believed that the larger dislocation density due to the significant lattice mistmatch between the GaAs substrate and the GaSb/InAs structure could be a likely reason. Smaller device sizes and the use of InP substrate will be investigated in the future.

8.5 Conclusion

In this chapter, various tunneling field effect transistor structures were proposed in the Si/SiGe and GaSb/InAs material systems. A process for fabricating vertical TFET structures with surround gate oxide and gate metal was developed. Gate stack optimization was performed to obtain good interface quality with a composite

Al2O3/HfO2/TiN/Al gate stack. Finally, the first results obtained for MBE grown and

CVD grown Si/SiGe p-TFETs are reported.

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CHAPTER 9 CONCLUSION AND FUTURE WORK

The focus of this dissertation has been the reduction in power consumption of electronic devices through the use of novel circuit and device architectures. Two tunneling based devices, namely Si-based resonant interband tunnel diodes and tunneling field effect transistors have been studied.

9.1 Si/SiGe Resonant Interband Tunnel Diodes

Tunnel diodes are capable of operation at low supply voltages, below 0.5V. This work takes a significant step towards large scale integration of these devices into standard

CMOS processes. Growth optimizations were performed to improve the performance of

Si/SiGe resonant interband tunnel diodes (RITD) using chemical vapor deposition resulting in high peak to valley current ratio's of upto 5.2. The effect of barrier thickness variation was also studied. Some techniques to possibly improve the tunneling current density such as the use of arsenic instead of phosphorus as the n-type dopant and varying the n-cap doping to enhance the δ-doping were investigated. Across the wafer variations for a 200 mm wafer are also reported, which is critical for manufacturing and has never been reported before in literature. CVD, being a nearer to equilibrium growth than MBE, greatly reduces point defect formation and hence much lower valley currents have been possible in this work. Further work needs to focus on improving the peak tunneling current densities. Obtaining symmetric δ-doping regions are crucial. Presently from

SIMS measurements it is clear that the n δ-doping spike is absent. Dopant segregation is 222 a critical issue for n-dopants. Use of different precursor gases such as trisilane and use of

N2 as carrier gas to lower growth temperature can be investigated to sharpen the δ-doping profiles. Further optimization is also required to improve across the wafer uniformity.

9.2 Tunnel Diode VLSI circuit design

For the first time tunnel diodes have been integrated into a standard EDA tool to allow detailed simulations of power, speed and robustness to process variations. The large legacy of CMOS based circuits built over the last 40 years also includes the great improvements in simulation tools, which are essential for VLSI design. If tunnel diode based circuits are to replace CMOS, work on developing detailed models and standard cell libraries for VLSI design are essential. This work takes a first step towards this EDA integration. A memory array has been designed using the 90 nm process technology with

0.5V supply voltage and its speed and power are compared with SRAM. Future work includes development of more advanced physics based models for tunnel diode including experimental across the wafer variation data. Boolean and multivalue logic are also exciting future applications and standard cell design for logic circuits should also be investigated as a next step.

9.3 Anodic oxidation for III-V passivation

Replacement of Si with higher mobility materials in the channel is a hot topic of investigation in the industry presently. However, forming good quality oxides on III-V semiconductors has been a 40 year old issue precluding their use as MOSFETs. In this work anodic oxidation was investigated as a means to modify the stoichiometry of the native oxide formed on GaAs. It is believed that arsenic oxide is unstable, forming

223 metallic arsenic which is responsible for Fermi level pinning and poor gate modulation in

III-V semiconductors. Addition of gallium sulfate during anodic oxidation of GaAs is shown to reduce the interface state densities due to metallic arsenic. Future work can focus on InGaAs, which is a lower band gap material, and is more promising for use as a channel material. InGaAs has also shown better results for surface passivation with atomic layer deposition.

9.4 High-κ dielectrics in bio-sensors

Si-based biosensors can be used for in vivo biosensing, providing real time sensing, for example by mounting on the tip of disposable biopsy needles. The low cost of Si devices makes this possible. However, Si MOSFETs are unstable in the presence of alkali ions, which are found in high concentrations in bodily fluids. This is due to alkali ions penetrating into silicon oxide and shifting the threshold voltage, causing false fluctuations in the sensor readings. This is especially critical in bio sensors where the signal level is very small. In this dissertation, Al2O3 deposited by atomic layer deposition has been investigated as an alternate to SiO2 as the gate dielectric. Excellent immunity to alkali ions is found even with oxides as thin as 10 nm. Al2O3 has an added benefit of higher dielectric constant which boosts the sensitivity of the sensor. Future work includes building MOS transistors with this dielectric and testing its application as an immunoFET by functionalizing the gate. Further, nanolaminates of higher dielectric constant materials such as HfO2 and Ta2O5 along with Al2O3 can be investigated to improve sensitivity while retaining the alkali ion impermeability benefits of Al2O3.

224

9.5 Tunneling field effect transistors.

Finally, Si and GaSb/InAs based tunneling FET devices are investigated. TFETs promise low leakage currents with steep subthreshold slopes, not limited by the 60 mV/decade limit of MOSFETs. However they suffer from much lower ON currents due to low tunneling probabilities. The inclusion of SiGe and delta doping along with surround gate topologies show promise in improving ON currents. Future work involves scaling these devices and implementing a top contact for source instead of a backside contact. Further, the large parasitic capacitance due to the gate oxide and metal directly being on top of the source region needs to be reduced. This can be done by incorporating low-k materials which are thermally stable to allow metal anneal after deposition o f this low-k material. One possible technique is the evaporation of silicon oxide before gate metal deposition, with thickness equal to the source region thickness, just stopping at the channel region. This will reduce the gate-source coupling capacitance and also reduce the gate leakage. GaSb/InAs tunnel diodes and tunnel FETs were also investigated and some process recipes were developed. However, no NDR region for tunnel diodes or gate modulation for TFETs was observed. Scaling of device size is again critical to reduce the number of dislocations per device, generated as a result of the large lattice mismatch between substrate and the device. The use of InP substrate instead of GaAs can also be studied.

225

APPENDIX A TUNNEL DIODE INTEGRATION INTO CADENCE

A.1 Schematic Implementation

1. Design a symbol for the tunnel diode

New Cellview Tool (Composer Symbol)

Figure A.1 Symbol definition for tunnel diode

In symbol editing window create schematic view for the cell. This allows the symbol to be generated in a schematic netlist.

Design Create Cellview From Cellview (From view Name symbol To view Name schematic)

2. Develop a VerilogA model

In symbol editing window create verilogA view for the cell.

Design Create Cellview From Cellview (From view Name symbol To view Name

VerliogA-Editor).

Write verilogA model for diode. A veriloga.va file is created in the cell folder. 226

`include "constants.vams" `include "disciplines.vams" module ritd(A, C); inout A,C; electrical A,C; parameter real mc=0; //montecarlo simulation parameter real length=0.2; // default length in um parameter real width=0.2; // default width in um parameter real Ipeak=500e-9; // default peak current in Amps // default nominal current in Amps (peak current varies in montecarlo // simulations, nominal current is the designed current) parameter real Inom=500e-9; parameter real PVCR=4.08; // default PVCR value

//current scaling factor (I-V fitted to data from S-Y Park et.al., // Electronic Letters,42, 719, 2006 and scaled to desired peak current // value parameter real K=Ipeak/0.0056; // parameter variation Δ (see derivation in section 4.3.4.4 parameter real del=-(1/0.8081)*ln(Ipeak/Inom); // spacer thickness = 8; factor change in cap. parameter real Cf=8/(8+del); parameter real area = length*width; // Capacitance variation. Base capacitance from N. Jin et.al., // C is function of V actually. Voltage dependence not included here parameter real c=Cf*11.5e-15*area; // capacitance per unit area * area

// value of current at peak voltage parameter real Ipp = ((3.9726e-6 + 1*(0.04363*0.17- 0.25206*pow(0.17,2)+13.01095*pow(0.17,3)- 383.81624*pow(0.17,4)+6433.82263*pow(0.17,5)- 64088.9768*pow(0.17,6)+373781.07135*pow(0.17,7)- 1177878.92116*pow(0.17,8)+1546882.23192*pow(0.17,9))))*K;

// value of current at valley voltage parameter real Ivv = (5.75579 -78.49873*0.4+471.21293*pow(0.4,2)- 1633.94703*pow(0.4,3)+3607.68882*pow(0.4,4)- 5261.48962*pow(0.4,5)+5069.66501*pow(0.4,6)- 3112.35078*pow(0.4,7)+1104.7228*pow(0.4,8)- 172.73929*pow(0.4,9))*Inom/0.0056+(pow((((Ipeak-Inom)/Inom)+1),3.04)- 1)*Inom/4; parameter real m=(Ipp-Ivv)/(0.17-0.4);

// slope of NDR region parameter real c1=(Ipp*0.4-Ivv*0.17)/(0.4-0.17); real Id; //dc current real Ia; //ac current

227 analog begin // polynomial fit - dry etch data 75 um diameter mesa // Reverse bias region if (V(A,C)<=0) Id = ((0.00001 + 1*(0.0441*V(A,C)+0.09487*pow(V(A,C),2)+2.51143*pow(V(A,C),3)+28.42744*p ow(V(A,C),4)+180.36246*pow(V(A,C),5)+664.217*pow(V(A,C),6)+1409.13559*p ow(V(A,C),7)+1597.06626*pow(V(A,C),8)+748.52473*pow(V(A,C),9))))*K;

// peak current region else if (V(A,C)>0 && V(A,C)<=0.17) Id = ((3.9726e-6 + 1*(0.04363*V(A,C)- 0.25206*pow(V(A,C),2)+13.01095*pow(V(A,C),3)- 383.81624*pow(V(A,C),4)+6433.82263*pow(V(A,C),5)- 64088.9768*pow(V(A,C),6)+373781.07135*pow(V(A,C),7)- 1177878.92116*pow(V(A,C),8)+1546882.23192*pow(V(A,C),9))))*K;

// NDR region else if (V(A,C)>0.17 && V(A,C)<=0.4)

// original fitting data for NDR region

//Id = ((-44.85963 + 1541.44848*V(A,C)- 23284.52549*pow(V(A,C),2)+203006.65544*pow(V(A,C),3)- 1125958.97791*pow(V(A,C),4)+4120513.88103*pow(V(A,C),5)- 9950513.9764*pow(V(A,C),6)+15291863.65026*pow(V(A,C),7)- 13572248.2101*pow(V(A,C),8)+5301255.10931*pow(V(A,C),9)))*K;

// linear approximation for NDR region for monte-carlo simulation

Id = m*V(A,C)+c1;

//Id=(-0.0167*V(A,C)+8.44e-3)*K;

// valley current region Jv+ΔJv else if (V(A,C)>0.4) Id = (5.75579 -78.49873*V(A,C)+471.21293*pow(V(A,C),2)- 1633.94703*pow(V(A,C),3)+3607.68882*pow(V(A,C),4)- 5261.48962*pow(V(A,C),5)+5069.66501*pow(V(A,C),6)- 3112.35078*pow(V(A,C),7)+1104.7228*pow(V(A,C),8)- 172.73929*pow(V(A,C),9))*Inom/0.0056+(pow((((Ipeak- Inom)/Inom)+1),3.04)-1)*Inom/4;

// ac current through capacitor Ia = c*ddt(V(A,C)); I(A,C) <+ Id+Ia; // instantaneous power $pwr(V(A,C)*I(A,C)); end endmodule

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3. When executing schematic in Analog Design Environment for the symbol to be linked to

the veriloga model change order in viewlist

4. g g v S u v O S v

(place veriloga before schematic)

A.2 Layout Implementation

1. Adding new layers: Two new layers are added to represent the tunnel diode and via

connecting metal contact to tunnel diode (reference: cadence documentation:

techfileuser.pdf)

Load techfile.cds

gy g L

gy g y

Add new layer Purpose Pairs. RD (tunnel diode definition) and VR (via to tunnel

diode) added

gy g S v g y

techfile.cds)

Figure A.2 Screen shot showing adding new layers for layout implementation of tunnel diode

229

Edit color, style etc.

Figure A.3 Screenshot showing how to specify attributes for new layere

Tools Display resource manager

2. Modifying binary technology file

a. Tools Technology file manager Load /~path/techfile.cds

b. Tools Technology file manager Edit Rules Double click on each class to

open edit window

c. Tools Technology file manager Save (reflects changes into binary file)

Figure A.4 Screenshot showing modification of technology file 230

3. Append to Ascii file

a. Tools Technology file manager Load /~path/techfile.cds

b. Tools Technology file manager Dump (Enter Ascii tech file location and

name)

Figure A.5 Screenshot showing modificating of ascii technology file c. Modify Ascii technology file

; ASCII technology File for Si-Based Resonant Interband Tunnel Diode ;****************** ; Controls ;****************** controls ( techparams (

(RitdWidthMin 0.28) (RitdSpace 0.28) (VRWidth 0.12) (VRSpace 0.12)

) ; techparams ) ;controls ;***************************** ; LAYER DEFINITION ;***************************** layerDefinitions ( techLayers ( ; (LayerName Layer # Abbreviation) ;User-Defined Layers: (RD 49 RD) (VR 155 VR) ); techLayers techLayerPurposePriorities( ; (LayerName Purpose) (RD drawing) 231

(VR drawing) ) ;techLayerPurposePriorities techDisplays( ; (Layer Name Purpose Packet Vis Sel Con2ChgLy DrgEnbl Valid) ( RD drawing RD_drawing t t t t t) ( VR drawing VR_drawing t t t t t) ) ;techDisplays ); layerDefinitions ;************************** ; Layer Rules ;************************** layerRules ( viaLayers( ;(layer1 viaLayer layer2) ( RD VR M1) ) ;viaLayers ) ;layerRules ;********************** ; Physical Rules ;********************* physicalRules ( spacingRules ( ; (rule layer1 layer2 value) ; RD ( minSpacing "RD" techParam "RitdSpace") (minWidth "RD" techParam "RitdWidthMin") ;VR (minSpacing "VR" techParam "VRSpace") minWidth "VR" techParam "VRWidth") ) ;spacingRules

232

d. Load modified ascii technology file

e. Save: Tools Technology file manager Save (reflects change into binary file,

techfile.cds)

4. Implement Tunnel Diode Layout as parameterized cell (pcell)

a. Create new layout cell with same cell name as symbol

b. Layout Tools Pcell Define stretch in x and y to allow runtime size

modification (reference: Cadence documentation: pcellref.pdf)

Pwell Ndiffusion

Via to TD TD

Figure A.6 Parameterized cell definition

A.3 Parasitic Extraction

1. Add Design Rule Check

//************************* // // RITD DRC Rules // //************************

// RITD layer LAYER RD 246 LAYER MAP 246 DATATYPE==0 246

// M1-RITD via layer LAYER VR 247 LAYER MAP 247 DATATYPE==0 247 233

Rule1 {@RITD minimum width >= 0.2 INT RD < 0.2}

Rule2 {@RITD space >= 0.28 EXT RD < 0.28 }

Rule3 {@RITD minimum enclosure in RX >=0.04 ENC RD RX < 0.04}

Rule4 {@VR exact length and width >=0.12 NOT RECTANGLE VR == 0.12 BY == 0.12 ORTHOGONAL ONLY}

Rule5 {@via space >= 0.14 EXT VR < 0.14 }

Rule6 {@RITD-via space >=0.14 EXT VR RD < 0.14}

2. Add LVS rules

// LVS Rules // //************************

//RITD layer LAYER RD 246 LAYER MAP 246 DATATYPE==0 246 // M1-RITD via layer LAYER VR 247 LAYER MAP 247 DATATYPE==0 247 RITD_diff = nsd ENCLOSE RD

// bottom contact CONNECT RITD_diff m1_mod1 m1_par BY CA_rx

// top contact of RITD with M1 CONNECT RD m1_mod1 m1_par BY VR

DEVICE ritd RD RITD_diff(C) RD(A)

3. Add to calview.cellmap

(ritd (research ritd symbol) ( (a A) (c C) ) ( (width width) (length length) ) 234

)

4. In stream.map add:

RD drawing 246 0 VR drawing 247 0 5. Calibre is used for DRC, LVS and parasitic extraction

a. Calibre setup netlist export schematic view should be first in list

b. Calibre setup layout export layer map file stream.map (modified)

c. Calibre Calibre view cellmap file (modified calview.cellmap)

d. Calibre Run DRC (Design rule check)

e. Calibre Run LVS (layout versus schematic)

f. Caibre Run PEX (parasitic extraction)

g. PEX output format calibreview

h. PEX output use names from schematic

A.4 Monte-Carlo Implementation

The following spectre program is used when running monte-carlo simulations to vary the tunnel diode process parameters and should be included along with the model files. simulator lang=spectre ahdl_include "./veriloga.va" statistics process { // process variation vary Ip dist=gauss std=6 percent=yes vary Ip1 dist=gauss std=6 percent=yes } // mismatch correlate param=[Ip Ip1] cc=0.8 }

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APPENDIX B RITD FABRICATION PROCESS

B.1 Top metal pattern

5. Lift-off process (LOR 5A/Shipley 1813)

a. Clean sample with acetone followed by IPA and DI water rinse. Dehydration bake

at 150oC for 5 min.

b. LOR 5A spin coat 4000 rpm (acceleration: 8000 r/s) for 30 seconds.

c. Prebake at 150oC for 3 minutes. Prebake temperature defines the undercut. Higher

temperature (upto 190oC) reduces undercut and is preferred for defining smaller

features. However lift-off maybe more difficult.

d. Spin coat Shipley 1813 at 5000 rpm (acceleration: 10000 r/s) for 30 seconds.

e. Softbake at 115oC for 1 minute.

f. Expose with EV 620 aligner for 2.5 seconds. Use mask ohmic 1.

Figure B.1 Ohmic 1 mask

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g. Develop in MF319 for 50 seconds.

10 µm 1 µm 2 µm 3 µm

Figure B.2 Lines and spaces test for LOR5A/S1813 recipe 6. Oxygen Descum

a. Pressure: 30 mT

b. RF power: 30 W

c. ICP power: 0 W

d. DC voltage ~ 167V

e. Oxygen flow: 50 sccm

f. Time: 1 min 30 seconds

7. Oxide Etch

a. 15 sec in buffered HF for Silicon

b. 30 sec in HCl:H2O (1:1) for GaSb/InAs or InGaAs diodes

8. Metal deposition

237

a. Ti/Au (15/100 nm) if using wet etch process for mesa etching. Use Ti/Au/Cr

(15/100/25 nm) if using dry etch to avoid Au exposure during dry etch.

Alternately use Ni/Cr (15/25 nm).

b. Pt/Au (15/100) or Pt/Au/Cr (15/100/25 nm) for GaSb/InAs for wet and dry

etching respectively

c. Ni/Ge/Au/Ni/Au (25/33/100/25/100 nm) for InGaAs RTD

9. Lift off metal

a. Heat NMP to 80oC (set hotplate to 90oC). Soak samples for 15 minutes

b. Rinse in Methanol (methanol dissolves NMP)

c. Rinse in IPA

d. Blow dry with N2 gun

B.2 Photoresist etch mask

Some wet etch recipes can also remove top metal hence a top photoresist to protect the metal is essential. For example Si wet etch (HF/HNO3/H2O) removes aluminum (Note: aluminum is easily etched by HF), H3PO4/H2O2/H2O for III-V wet etch removes Au based metal stacks. This layer is also needed as a TLM isolation step.

1. Spin coat Shipley 1813

a. Clean sample with acetone followed by IPA and DI water rinse. Dehydration bake

at 150oC for 5 min.

b. S1813 spin coat: 300 rpm (acceleration: 100 r/s) for 5 seconds followed by spin

at 3000 rpm (acceleration: 5000 r/s) for 60 seconds.

c. Soft bake at 115oC for 1 minute.

238

d. Expose with EV 620 aligner for 2.5 seconds. Use mask isolation 1. Figure B.3

shows the alignment of ohmic 1 level to isolation 1 mask.

e. Develop in MF 319 for 1 minute 30 seconds.

f. Hard bake: 115oC for 1 minute 30 seconds.

Figure B.3 Photoresist etch mask step

Note: This mask can also be used as the ohmic 1 step if a clear field mask is needed

(for example using AZ5214 instead of bilayer process for lift-off).

B.3 Mesa etch

1. Silicon

a. Wet etch: Use HF/HNO3/H2O 2:100:100. Etch rate is about 40 nm in 30 sec.

However due to the high doping in the samples, etching maybe inhibited and a

change in the color of the surface is observed with increased etch time, without

any change in etch depth.

a. Dry etch: Alternately dry etch can be used instead of wet etch using a

CF4/O2 process. Recipe for plasma therm SLR770 ICP RIE

b. Pressure: 10 mT

c. CF4 flow: 42 sccm 239

d. O2 flow: 8 sccm

e. RF power: 30W

f. ICP power: 300W

g. DC voltage ~ 150V (fluctuates between 120-170V)

h. Etch rate ~ 60 nm/minute

2. GaSb/InAs

a. GaSb wet etch: NH4OH:H2O (1:2) etches ~ 20 nm/minute. Stops on InAs.

b. GaSb dry etch (using plasma therm SLR770 ICP RIE)

a. Pressure: 10 mT

b. BCl3 flow: 20 sccm

c. Ar flow: 5 sccm

d. RF power: 20W

e. ICP power: 150W

f. DC voltage ~ 120V

g. Etch rate ~ 50 nm/minute (initially slower)

b. InAs wet etch: H3PO4: H2O2:H2O 1:1:10, etches ~ 150 nm in 25 seconds

B.3 Bottom ohmic metal

Use LOR/S1813 process as discussed in section B.1 with mask ohmic 2. Figure B.4 shows ohmic 2 aligned to ohmic 1 level. Additionally mask isolation 2 can also be used to form ohmic 2 if a clear field mask is to be utilized (for AZ5214 process). Both ohmic 1 and ohmic 2 can also be done using AZ-5214 provided using isolation 1 and isolation 2 masks as shown in Fig. B.6 (provided no photoresist etch mask step is required).

240

Figure B.4 Ohmic 2 mask step

Figure B.5 Ohmic 1 aligned to isolation 2, used here as ohmic 2 with AZ514 lift- off process instead of bilayer process

Figure B.6 Use of isolation 1 and isolation 2 as ohmic 1 and ohmic 2 mask steps when using AZ 5214 instead of bilayer process, requiring clear field masks

241

APPENDIX C TFET FABRICATION PROCESS

C.1 Mesa etch mask

Follow step B.2 for photoresist etch mask patterning

C.2 Mesa etch

Follow step B.3 for etching Si or III-V TFETs

C.3 Pre-treatment before oxide deposition

1. Silicon - Standard clean process

o a. NH4OH:H2O2:H2O 1:1:5 at 70 C for 10 minutes

b. DI water rinse for 5 minutes

o c. HCl:H2O2:H2O 1:1:5 at 70 C for 10 minutes

d. DI water rinse for 5 minutes

e. HF dip in 1:10 HF:DI water for 1 minute followed by a 1 minute DI water rinse

just before ALD oxidation

2. III-V

a. Soak in (NH4)2S for 10 minutes followed by 1 minute rinse in DI water

C.4 Gate oxide deposition - using ALD

o 1. Al2O3 : Deposition temperature 300 C deposition rate: 0.83 Å/cycle

TMA: Pulse time: 0.1 seconds Purge time: 4 seconds

H2O: Pulse time: 0.1 seconds Purge time: 4 seconds

242

o 2. HfO2: Deposition temperature 350 C deposition rate: 0.3 Å/cycle

Hf precursor: Pulse time: 0.4 seconds Purge time: 4 seconds, 2 pulses per cycle

H2O: Pulse time: 0.8 seconds Purge time: 8 seconds

C.5 Gate metal deposition

1. TiN sputtering (25 nm)

a. N2 flow: 5 sccm

b. Ar flow: 15 sccm

c. RF gun power: 400 W

d. Time: 14 min 53 sec

C.6 Gate isolation

Use S1813 process as detailed in section B.2 for masking gate area. Mask Isolation 2 (see

Fig. C.1).

Figure C.1 Gate isolation mask

243

C.7 Gate metal etch

1. Al is etched by MF 319 while developing in the previous step. Develop for 1 minute

longer till all the metal is gone. Alternately the TiN dry etch also etches Al.

2. TiN etch (using plasma therm SLR770 ICP RIE)

a. Pressure: 10 mT

b. BCl3 flow: 10 sccm

c. Cl2 flow: 5 sccm

d. RF power: 40 W

e. ICP power: 300 W

f. DCV ~ 150V

g. etch time: 2.30 min etches 50 nm

C.8 BCB spin coat

1. AP3000 (adhesion promoter)

a. spread: 250 rpm (acceleration: 950 r/s), 5 seconds

b. spin: 3000 rpm (acceleration: 3500 r/s), 15 seconds

2. Cyclotene 3022.25

a. spread: 500 rpm (acceleration: 1900 r/s), 10 seconds

b. spin: 1500 rpm (acceleration: 2000 r/s), 30 seconds

3. Soft bake 110oC 1 minute on a hotplate

4. Hard cure at 250oC for 1 hour in blue M oven (nitrogen ambient)

a. Keep oven open to let it cooldown to about 50oC.

b. Place sample of holder covered with aluminum foil.

244

c. Heat oven to 150oC and keep samples at this temperature for 15 minutes

d. Heat oven to 250oC. Cure samples for 1 hour at 250oC

e. After cure time set oven temperature back to 95oC (or 115oC) and let samples cool

down in oven. When oven gets to 150oC (takes about 1 hour), take samples out.

f. BCB thickness after cure ~ 1.6 µm.

C.9 BCB etch back

Dry etch BCB using plasma therm SLR770 ICP RIE

a. Pressure: 30 mT

b. O2 flow: 40 sccm

c. CF4 flow: 10 sccm

d. RF power: 30 W

e. ICP power: 200 W

f. DCV ~ 130V

g. etch rate: 100 nm/minute

Etch back till top metal just exposed.

C.10 Gate metal/oxide etch

Etch the gate metal and oxide on top of the mesa to expose the drain/source contact region. Dry etch metal using recipe in section C.7. This etch also etches BCB. About 50 nm BCB is etched by a 2.30 min metal etch.

C.11 Gate oxide etch

Al2O3 can be etched by BHF however it also etches Al and sometimes strips BCB, hence is avoided. HfO2 cannot be wet etched. The following dry etch recipe etches both oxides

245

a. Pressure: 10 mT

b. BCl3 flow: 10 sccm

c. Ar flow: 5 sccm

d. RF power: 30 W

e. ICP power: 150 W

f. DCV ~ 170V

g. etch rate: Al2O3 ~ 2.2 nm/minute, HfO2 ~ 2.7 nm/ minute

This etch does not etch BCB significantly.

C.12 Top metal pattern

Use LOR5A/S1813 bilayer process as detailed in section B.1 for patterning top source/drain contact metal with ohmic 1 mask. This mask was not designed to align ohmic 1 in the end. Hence no alignment markers are present for this step. Use TLM structures and large rectangular patterns to roughly align.

C.13 BCB strip

Use recipe in C.9 to remove remaining BCB and expose gate contact.

C.14 Back metal deposition

Deposit 150 nm Al as back contact

C.15 Metal anneal

o Anneal gate metal in RTA oven at 400 C for 1 min in N2 ambient (Note this step can also be done after gate metal isolation, just before BCB spin coat).

246

APPENDIX D MATLAB CODE

%Extracting interface state density from capacitance voltage and conductance voltage plots obtained using CSM-win software. clear;

Nf = 13; %Nf is the number of different frequencies in the measurement typically 13 for 100Hz to 1MHz, 10 for 1kHz to 1MHz %dia = 90; % Dia is the diameter of the measured dot in µm side = 100; % side for square dots in µm type = 1; % type=0 for n-type ; type=1 for p-type material temp = 300; % temp is the measurement temperature material= 1; % material=0 for GaAs/InGaAs ; material =1 for Si bandgap = 1.1; % bandgap of the material cv=uiimport('*.xls'); % excel file saved from CSM program containing C- V data gv=uiimport('*.xls'); % % excel file saved from CSM program containing G(w)/w vs Voltage data %------

Vg=cv.data(:,1); Nvg= length (Vg); for (i=1:Nf) Cap(:,i)=cv.data(:,i+1)*1e-12; %data in pF convert to F. end for (i=1:Nf) Con(:,i)=gv.data(:,i+1)*1e-12; %data already normalized as G(w)/w in pF end for (i=1:Nf) freq_data=cell2mat(gv.colheaders(i+1)); [freq(i),data]=strread(freq_data,'%d %s'); end q = 1.6e-19; if (type==0) % n-type if (material==0) % GaAs/InGaAs sigma=1e-15; vth=4.4e7;

247

density=4.7e17; end if (material==1) % Si sigma=1e-15; vth=2.3e7; density=3.2e19; end end if (type==1) % p-type if (material==0) % GaAs/InGaAs sigma=1e-15; vth=1.8e7; density=9e18; end if (material==1) % Si sigma=1e-15; vth=1.6e7; density=1.8e19; end end

%nor_cap = (Cap*4*1e8)/(pi*dia^2); % convert capacitance to F/cm^2, dia in µm nor_cap = (Cap*1e8*1e6)/(side^2); % convert capacitance to F/cm^2, side in µm for (i=1:Nvg) for (j=1:Nf)

%nor_con(i,j) = (Con(i,j)*4*1e8)/(pi*dia^2*q); % normalize conductance to Conductance/(q*area*w) F/cm2. Data from CSM-win software already divided by 2*pi*f

nor_con(i,j) = (Con(i,j)*1e8)/(side^2*q);

end end if (type==0) % n-type for (i=1:Nf) frequ(i)=bandgap-8.625e- 5*temp*log((sigma*vth*density)/(2*pi*freq(i))); end end if (type==1) % p-type for (i=1:Nf) frequ (i) = 8.625e- 5*temp*log((sigma*vth*density)/(2*pi*freq(i))); end end 248

% interface state extraction for (i=1:Nf) Gmax=1; for (j=1:Nvg) if nor_con(j,i)>nor_con(Gmax,i); Gmax=j; Dit(i)=2.5*nor_con(j,i); %Nicollian Brews Pg 197 end

end nor_con(Gmax,i) end data1 = cat(2,transpose(frequ),transpose(Dit)); xlswrite ('Dit_*', data1); % store Dit information to excel file Vgx = Vg; whitebg([1 1 1]); subplot (2,2,1); hold all; colormap(jet(128)); for (i=1:Nf) plot (Vgx,nor_cap(:,i),'LineWidth',2);xlabel('gate bias'), ylabel ('capacitance (uF/cm^2)') end subplot (2,2,2); hold all; xlswrite ('Cnorm_*',nor_cap); % store normalized capacitance information to excel file for (i=1:Nf) plot (Vgx,nor_con(:,i),'LineWidth',2); xlabel('gate bias'), ylabel ('Corrected Conductance (G/Awq)') end xlswrite ('Con_noanneal_400_100um', nor_con); % store normalized conductance information to excel file subplot (2,2,3); hold on; shading interp; view(2); [cs,H]= contourf(Vgx,frequ,transpose(nor_con)); clabel (cs,H,'FontSize',15,'Color','black') %,colorbar xlabel('gate bias'), ylabel('energy level in bandgap'); axis ([min(Vgx),max(Vgx),min(frequ),max(frequ)]); subplot (2,2,4); plot (frequ,Dit,'LineWidth',2); xlabel('energy level in bandgap'), ylabel ('Dit')

249

APPENDIX E SILVACO CODE

E.1 Si/SiGe RITD go atlas

mesh space.mult=1.0 ^diag.flip x.mesh location=0.0 spacing=0.5 x.mesh location=1.0 spacing=0.5 y.mesh loc=0 spacing=0.1 y.mesh loc=0.08 s=0.00005 y.mesh loc=0.3 s=0.00005 y.mesh loc=0.5 spacing=0.1 region num=1 material=silicon region num=2 material=sige y.min=0.099 y.max=0.104 x.composition=0.4 elec name=anode top elec name=cathode bottom qtregion number=1 pts.normal=5 pts.tunnel=300 x1=0 y1=0.11 x2=1 y2=0.11 x3=1 y3=0.1 x4=0 y4=0.1

doping uniform p.type conc=2e19 y.max=0.1 doping gaussian conc=3e20 char=1e-3 p.type y.min=0.1 y.max=0.101 peak=0.1005 doping gaussian conc=1.5e20 char=6e-4 n.type y.min=0.105 y.max=0.107 peak=0.106 doping uniform n.type conc=1e20 y.min=0.107 material material=Si me.tunnel=0.19 mh.tunnel=0.16 trap donor e.level=0.4 density=5e15 degen.fac=2 sign=1e-13 sigp=1e-13 solve init output con.band val.band eigens=2 save outf=sigeritd.str tonyplot sigeritd.str

250 models temperature=300 srh fermi ni.fermi print bbt.std bbt.nonlocal bbt.nlderivs bgn trap.tunnel

#Solving schrodinger-poisson equation for finding quantized energy #levels in band-diagram, separate solution for electrons and holes

#model temp=300 schrodinger eigens=8 fixed.fermi ^calc.fermi #qy.min=0.09 qy.max=0.14 fermi new.eig qminconc=1e13 srh num.band=2 bgn

#output con.band val.band j.conduc j.electron j.hole j.total eigens=2 #save outf=sigeritdp.str

#model temp=300 schrodinger eigens=8 fixed.fermi ^calc.fermi #qy.min=0.09 qy.max=0.14 fermi new.eig qminconc=1e13 srh num.band=2 bgn

#output con.band val.band j.conduc j.electron j.hole j.total eigens=2 #save outf=sigeritdn.str

#tonyplot -overlay sigeritdp.str sigeritdn.str

method climit=1.0 dvmax=0.005 trap solve init log outf=ritd_forward1.log solve name=anode vanode=0 vstep=0.01 vfinal=0.05 solve name=anode vanode=0.05 vstep=0.02 vfinal=0.6 solve name=anode vanode=0.6 vstep=0.05 vfinal=1 log off tonyplot ritd_forward1.log exit

E.2 p-Tunnel FET go atlas mesh space.mult=1.0 ^diag.flip x.mesh location=-0.002 spacing=0.0005 x.mesh location=0 spacing=0.0005 x.mesh location=0.0050 spacing=0.001 x.mesh location=0.009 spacing=0.001 x.mesh location=0.01 spacing=0.0005 x.mesh location=0.012 spacing=0.0005 y.mesh loc=0 spacing=0.01 y.mesh loc=0.045 s=0.0005 y.mesh loc=0.055 s=0.0005 y.mesh loc=0.135 s=0.005 251 y.mesh loc=0.14 s=0.0005 y.mesh loc=0.16 s=0.0005 y.mesh loc=0.200 s=0.01 region num=1 material=Si x.min=0 x.max=0.01 y.min=0 y.max=0.200 region num=2 material=sige x.min=0 x.max=0.01 y.min=0.145 y.max=0.149 x.composition=0.2 region num=3 material=oxide x.min=0.01 x.max=0.012 y.min=0 y.max=0.200 region num=4 material=oxide x.max=0 x.min=-0.002 y.min=0 y.max=0.200 elec num=1 x.min=0.012 x.max=0.012 y.min=0.05 y.max=0.15 name=gate elec num=2 x.min=0 x.max=0.01 y.min=0 y.max=0 name=source elec num=3 x.min=0 x.max=0.01 y.min=0.2 y.max=0.2 name=drain elec num=4 x.min=-0.002 x.max=-0.002 y.min=0.05 y.max=0.15 name=gate

qtregion number=1 pts.normal=10 pts.tunnel=300 x1=0 y1=0.175 x2=0.01 y2=0.175 x3=0.01 y3=0.135 x4=0 y4=0.135 material material=oxide permittivity=15 contact name=gate workfunction=4.5 doping uniform p.type conc=1e19 x.min=0 x.max=0.01 y.min=0 y.max=0.05 doping uniform n.type conc=1e16 x.min=0 x.max=0.01 y.min=0.05 y.max=0.15 doping gaussian n.type conc=1e21 char=1e-3 y.min=0.15 y.max=0.151 peak=0.1505 doping uniform n.type conc=1e20 x.min=0 x.max=0.01 y.min=0.151 y.max=0.2 models cvt numcarr=2 temperature=300 srh fermi ni.fermi print bbt.nonlocal bbt.nlderivs bgn method climit=1e-4 maxtrap=10 solve init output con.band val.band eigens=2 save outf=ptfet.str tonyplot ptfet.str log outf=idvg_ptfet.log solve name=drain vdrain=0 vstep=0.05 vfinal=1 solve name=gate vgate=0 vstep=-0.01 vfinal=-0.05 solve name=gate vgate=-0.05 vstep=-0.05 vfinal=-1 #log outf=idvd_ptfet.log #solve name=gate vgate=0 vstep=-0.05 vfinal=-1 #solve name=drain vdrain=0 vstep=0.01 vfinal=0.05 #solve name=drain vdrain=0.05 vstep=0.05 vfinal=1 output con.band val.band eigens=2 save outf=ptfet1.str tonyplot ptfet1.str tonyplot idvg_ptfet.log #tonyplot idvd_ptfet.log

Exit 252

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