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_ US005420609A United States Patent [191 [11] Patent Number: 5,420,609 Izzi et al. [45] Date of Patent: May 30, 1995
[54] B ’ SYSTEMS ODS OTHER PUBLICATIONS [75] Inventors: Innis _J. Izzi, Plano, Tex; Richard E- Brooktree, “Bt459”, Product Data Book, 1989, 1989, pp. Downing, Hoffman Estates, 111. 5_35 through 5_115_ _ Texas Instruments Incorporated, “TMS34070-2-Co1or [73] Assignee: Texas Instruments Incorporated, Palate”, Production Data, 1986 pp 1_15_ Dallas, Tex- Brooktree, “RAMDAC Products”, Winter 1990 Prod [21] Appl No _ 143 335 uct Selection Guid, Winter, 1990, pp. 9-15. . .. , _ Primary Examiner-—Ulysses Weldon [22] Flledi Oct 26, 1993 Assistant Examiner-Matthew Luu Attorney, Agent, or Firm—Robert D. Marshall, yJr.; Related U _S_ Application Data James C. Kesterson; Richard L. Donaldson [63] Continuation of Ser. No. 723,342, Jun. 28, 1991. [57] ABSTRACT A frame buffer is provided, including a plurality of [51] Int. Cl! ...... 90099295143; input nodes and a plurality of multiplexing circuits_ """"""""" 9O /199_’307//239 Each multiplexing circuit has a ?rst input coupled to a e307/240 241312315. 244' 3287103’ 104 105’ rispwive input- mde' Firs.‘ °°mr°1 ciri’uitry is pm‘ ’ ’ ’ ’ ’ 106 152’ 153’ 154; vlded for selectively couphng a second input of each ’ ’ ’ multiplexer circuit to outputs of others of the multiplex [56] References Cited ing circuits. Second control circuitry is coupled to each multiplexing circuit for selecting between the ?rst and U.S. PATENT DOCUMENTS second inputs. 4,769,632 9/1988 Work et al. . 4,815,033 3/ 1989 Harris . 8 Claims, 14 Drawing Sheets
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zo_mm§mz m3 m2 Rm mwm mum 2E 3m US. Patent May 30, 1995 Sheet 10 of 14 5,420,609 .3:05a I. .6528 .6528 UN US. Patent May 30, 1995 Sheet 14 of 14 5,420,609 / w vs: is: E5 5Q@cI2;Ix . <|>l2><, 6:1Qm1xc x _ _ 5,420,609 1 2 The provision of a circuit called a color palette ena FRAME BUFFER, SYSTEMS AND METHODS bles a compromise between these con?icting require ments. The color palette stores color data words which CROSS-REFERENCE TO RELATED specify colors to be displayed in a form that is ready for APPLICATIONS digital-to-analog conversion directly from the color This application is a continuation of US. application palette. The color codes stored in the memory for each Ser. No. 07/723,342, ?led Jun. 28, 1991. pixel have a limited number of bits, thereby reducing The following patent application, assigned to Texas ' the memory requirements. The color codes are em Instruments Incorporated, the assignee of the present ployed to select one of a number of color registers or application, and is cross-reference and incorporated palette locations. Thus, the color codes do not them into present application by reference. selves de?ne colors, but instead, identify preselected palette locations. These color registers or palette loca tions each store color data words which are longer than ’ Ser. No. Docket No. Title the color codes in the pixel map memory. The number 07/544,775 'I'I- l 5 123 PACKED BUS SELECTION 15 of such color registers or palette locations provided in OF MULTIPLE PIXEL the color palette is equal to the number of selections DEP'I'HS IN PALETTE provided by the color codes. For example, a 4-bit color DEVICES, SYSTEM AND METHODS code can be used to select 24 or 16 palette locations. The color data words can be rede?ned in the palette from 20 frame to frame to provide many more colors in an ongo Notice ing sequence of frames than are present in any one frame. (C) Copyright, Texas Instruments Incorporated, For overall operational ef?ciency, circuitry is re 1990. A portion of the Disclosure of this patent docu quired which can convert the color codes stored in the ~ ment contains material which is subject to copyright 25 protection. The copyright owner has no objection to ‘ graphic system memory into addresses for retrieving facsimile reproduction by anyone of the patent docu the color data words from the corresponding palette locations. For compatibility with a wide-range of ment or the patent disclosure, as it appears in the U.S. Patent and Trademark O?ice, patent tile or records, but graphics processing systems, such circuitry should be otherwise reserves all rights in its copyright whatso 30 able to operate in conjunction with control signals hav ever. ing speeds on the order of 140 M2. Thus, any improve ment in the circuitry converting color codes to color TECHNICAL FIELD OF THE INVENTION words is advantageous. The present invention relates in general to memories Due to the advantages of color palette devices, sys and in particular, to a sequential access memory, sys 35 tems and methods, any improvement in their implemen tems and methods. tation is advantageous in computer graphics technol ogy. BACKGROUND OF THE INVENTION SUMMARY OF THE INVENTION Without limiting the general scope of the invention, its background is described in connection with com According to the invention‘, the frame buffers pro puter graphics, as an example only. vided which includes a plurality of input nodes and a In computer graphics systems, the low cost of dy plurality of multiplexing circuits. Each of the multiplex namic random access memories (DRAM) has made it ing circuits has a ?rst input coupled to a respective economical to provide a bit map or pixel map system input node. First control circuitry is provided which memory. In such a bit map or pixel map memory, a 45 selectively couples the second input of each of the mul color code is stored in a memory location correspond tiplexer circuits to the outputs of others of the multi ing to each pixel to be displayed. A video system is plexing circuits. Second control circuitry is also pro provided which recalls the color codes for each pixel vided which is coupled to each of the multiplexer cir and generates a raster scan video signal corresponding cuits for selecting between the ?rst and second inputs. to the recalled color codes. Thus, the data stored in the The present invention allows for the high-speed con memory determine the display by determining the color version of a multi-bit word received at the input nodes generated for each pixel (picture element) of the dis into at least one output word. According to further play. aspects of the invention, a multi-bit color code is re The requirement for a natural looking display and the ceived at the inputs and a corresponding plurality of minimization of required memory are con?icting. In 55 color data words addressing an associated palette mem order to have a natural looking display, it is necessary to ory output. have a large number of available colors. This, in turn, BRIEF DESCRIPTION OF THE DRAWINGS necessitates a large number of bits for each pixel in order to specify the particular color desired from For a more complete understanding of the illustrated among a large number of possibilities. The provision of 60 embodiments of the present invention, and the advanta a large number of bits per pixel, however, requires a geous thereof, reference is now made to the following large amount of memory for storage. Since a number of descriptions, taken in conjunction with the accompany bits must be provided for each pixel in the display, even ing drawings, in which: a modest size display would therefore require a large FIG. 1 is a functional block diagram of a graphics memory. Thus, it is advantageous to provide some 65 processor system utilizing one embodiment of the pres method to reduce the amount of memory needed to ent invention; store the display while retaining the capability of choos FIG. 2 is a more detailed functional block diagram of ing among a large number of colors. a graphics processor for use with the invention; 5,420,609 3 4 FIG. 3 is a schematic diagram depicting a preferred bidiectionally coupled to processing system 12 via bus architecture for video RAM depicted in FIG. 1; 16. While graphics processor 18 operates as a data pro FIG. 4 is a functional block diagram of a video palette cessor independent of host processing system 12, graph depicted in FIG. 1; ics processor 18 is fully responsive to requests output FIG. 5 is a simpli?ed functional block diagram of from host processing 12. Graphics processor 18 further selector shown in FIG. 4 according to one embodiment communicates with memory 20 via video memory bus of the invention; 28. Graphics processor 12 controls the data stored FIGS. 6a-6f are a complete electrical schematic dia within video RAM 30, RAM 30 forming a portion of gram of the selector shown in FIG. 4 according to one ' memory 20. In addition, graphics processor 18 may be embodiment of the invention; 10 controlled by programs stored in either video RAM 30 FIG. 7 is a timing diagram illustrating the operation or in read-only memory 32. Read~only memory 32 may of the selector of FIG. 6; also include various types of graphic image data, such as FIG. 8 is a functional block diagram of a selected pair alpha numeric characters in one or more font styles and of bit paths shown in FIG. 6, including provision for frequently used icons. Further, graphics processor 12 VGA pass through; 15 controls data stored within video palette 22 via bidirec FIG. 9 is an electrical schematic diagram of a ?rst tional bus 34. Finally, graphics processor 18 controls embodiment of a selected one of the bit paths shown in digital-to-video converter 24 via video control bus 36. FIG. 8; Video RAM 30 contains bit map graphic data which FIG. 10 is an electrical schematic diagram of a sec control the video image presented to the user as manip ond embodiment of a selected one of the bit paths 20 ulated by graphics processor 18. In addition, video data shown in FIG. 8; corresponding to the current display screen are output FIG. 11 is a flmctional block diagram of a selected from video RAM 30 on bus 38 to video palette 22. pair of the bit paths shown in FIG. 6 including provi Video RAM 30 may consist of a bank of several sepa sion for VGA pass through and NIBBLE MODE oper rate random access memory integrated circuits, the ation; and 25 output of each circuit typically being only one or 4 bits FIG. 12 is an electrical schematic diagram depicting wide as coupled to bus 38. one embodiment of a selected one of the 3:1 multiplex Video palette 22 receives high speed video data from ers depicted in FIG. 11. video random access memory 30 via bus 38 and data from graphics processor 18 via bus 34. In turn, video DETAILED DESCRIPTION OF PREFERRED 30 palette 22 converts the data received on bus 38 into a EMBODIMENTS video level which is output on bus 40. This conversion Referring ?rst to FIG. 1, a block diagram of a graph is achieved by means of a look-up table which is speci ics computer system 10 is depicted as constructed in ?ed by graphics processor 18 via video memory bus 34. accordance with the principles of the illustrated em The output of video palette 22 may comprise color, hue bodiment of the present invention. For clarity and brev 35 and saturation signals for each picture element or may ity in understanding the inventive concepts herein, a comprise red, green and blue primary color levels for detailed description of the complete graphics process each pixel. Digital-to-video converter 24 converts the ing system will not be provided. A more complete de digital output of video palette 22 into the necessary tailed discussion, however, can be found in patent appli analog levels for application to video display 26 via bus cation Serial No. 07/544,775, ?led Jun. 24, 1990, (attor~ 4040 neys’ docket no. TI-l5l23), assigned to the assignee of Printed wiring board 14 also includes a VGA pass the present application and hereby incorporated by through port 43 coupled to palette 42. In the VGA reference. Also incorporated by reference herein are pass-through mode, data from the VGA connector of Texas Instruments TMS 34010 User’s Guide (August most VGA supported personal computers is fed di 1988); TIGA-340 (TM) Interface, Texas Instruments 45 rectly into palette 42 without the need for external data Graphics Architecture, User’s Guide, 1989; TMS 34020 multiplexing. This allows a replacement graphics board User’s Guide (January 1990); and TMS 44C251 Speci? to remain “downward compatible” utilizing the existing cation, all of which documents are currently available graphic circuitry often located on the mother board of to the general public from Texas Instruments Incorpo the associated post processing system 12. rated. These documents give a more thorough descrip— 50 Video palette 22 and digital-to-video converter 24 tion of graphics processing systems in general. may be integrated together to form a “programmable Graphics computer system 10 includes a host pro palette” 42 or simply “palette” 42. cessing system 12 coupled to a graphics printed wiring Video display 26 receives the video output from digi board 14 through a bidirectional bus 16. Located on tal-to-video converter 24 and generates the speci?ed printed wiring board 14 are a graphics processor 18, 55 video image for viewing by the user of graphics com memory 20, a video palette 22 and a digital-to-video puter system 10. Signi?cantly, video palette 22, digital converter 24. Video display 26 is driven by graphics to-video converter 24 and video display 26 may operate board 14. in accordance with either of two major video tech Host processing system 12 provides the major com-' niques. In the ?rst technique, video data are speci?ed in putational capacity for graphics computer system 10 terms of color, hue and saturation for each individual and determines the content of the visual display to be pixel. In the second technique, the individual primary presented to the user on video display 26. The details of color levels of red, blue and green are speci?ed for each the construction of host processing system 12 are con individual pixel. Upon selection of the desired design ventional in nature and known in the art and therefore using either of these two techniques, video palette 22, will not be discussed in further detail herein. 65 digital-to-video converter 24 and video display 26 are Graphics processor 18 provides the data manipula customized to implement the selected technique. How tion capability required to generate the particular video ever, the principles of the present invention in regard to display presented to the user. Graphics processor 18 is the operation of the graphics processor 18 are un 5,420,609 5 6 changed regardless of the particular design choice of data necessary for the control and operation of graphics the video technique. All of the signals that contribute to processor 18. These functions include control of the display color in some way are regarded as color signals timing of memory access, and control of data and mem even though they may not be of the red, blue, green ory multiplexing. technique. Graphics processor 18 also includes input/output FIG. 2 illustrates graphics processor 18 in further registers 56 and a video display controller 58. Input detail. Graphics processor 18 includes central process /output registers 56 are bidirectionally coupled to bus ing unit 44, graphics hardware 46, register ?les 48, in 60 to enable reading and writing within these registers. struction cache 50, host interface 52, memory interface Input/output registers 56 are preferably within the ordi 54, input/ output registers 56 and video display control 0 nary memory space of central processing unit 44. Input ler 58. /0utput registers 56 contain data which specify the The central processing unit 44 performs a number of control parameters of video display controller 58. In general purpose data processing functions including accordance with the data stored within the input/out arithmetic and logic operations normally included in a put registers 56, video display controller 58 controls the general purpose central processing unit. In addition, signals on video control bus 36 for the desired control of central processing unit 44 controls a number of special palette 42. For example, data within input/output regis purpose graphics instructions, either alone or in con ters 56 may include data for specifying the number of junction with graphics hardware 46. pixels per horizontal line, the horizontal synchroniza Graphics processor 18 includes a major bus 60 which tion and blanking intervals, the number of horizontal is connected to most parts of graphics processor 18, lines per frame and the vertical synchronization and including central processing unit 44. Central processing blanking intervals. unit 44 is bidirectionally coupled to a set of register ?les Referring next'to FIG. 3 a typical graphics memory 48, including a number of data registers, via bidirec system con?guration for video RAM 30 is depicted in tional register bus 62. Register ?les 48 serve as the re which eight VRAM memories 68 are used as an array, pository of the immediately accessible data used by 25 two of which are depicted as 680 and 68b. Each VRAM central processing unit 44. memory 68, or unit, includes four sections, or planes, 0, Central processing unit 44 is also connected to in 1, 2 and 3. The construction of each plane is such that a struction cache 50 by instruction cache bus 64. Instruc single data lead 70 is used to write information to that tion cache 50 is further coupled to bus 60 and may be plane. In a system which uses a 32-bit data bus, such as loaded with instruction words from video memory 20 30 data bus 28, there would be eight VRAM memories, (FIG. 1) via video memory bus 28 and memory inter each VRAM memory having four data leads connected face 54. The purpose of instruction cache 50 is to speed to-the input data bus. For example, for 32-bit data bus up the execution of certain functions of central process 28, VRAM memory 68a would have its four data leads ing unit 44. For example, a repetitive function that is 70 connected to data bus 28 leads 0, 1, 2, and 3, respec often used within a particular portion of the program tively. Likewise, the next VRAM memory 68b would executed by central processing unit 44 may be stored , have its four leads 0, 1, 2, and 3 connected to data bus 28 within instruction cache 50. Access to instruction cache leads 4, 5, 6, and 7, respectively. This pattern continues 50 via instruction cache bus 64 is much faster than ac for the remaining six VRAMs such that the last VRAM cess to video memory 20 and thus, the overall program has its leads connected to leads 28, 29, 30, 31 (not executed by central processing unit 44 may be sped up 40 shown) of bus 28. by a preliminary loading of the repeated or often used The VRAM memories 68 are arranged such that the sequences of instructions within instruction cache 50. pixel information for the graphics display is stored seri Host interface 52 is coupled to central processing unit ally across the planes in the same row. Assuming a 4-bit 44 via host interface bus 66. Host interface 52 is further per pixel system, then the bits for each pixel are stored connected to host processing system 12 via host system 45 in separate VRAM memory. In such a situation, pixel 0 bus 16. Host interface 52 serve to control the communi would be the first VRAM 68a and pixel 1 would be the cations between host processing system 16 and graphics second VRAM 68b. The pixel storage for pixels 2-7 are processor 18. Typically, host interface 52 would com not shown, but these would be stored in column 1 of municate graphics requests from the host processing VRAMS 68c, d. e, ? g and h. The pixel information for system 16 to graphics processor 18, enabling host sys pixel 8 would be stored in the ?rst VRAM 68a, still in tem 16 to specify the type of display to be generated by row A, but in column 2 thereof. video display 26 and causing graphics processor 18 to Each VRAM plane has a serial register 72 for shifting perform a desired graphic function. out information from a row of memory. In the preferred Central processing unit 44 is further coupled to embodiment, the shifting out is performed in response graphics hardware 46 via graphics hardware bus 68. 55 to a shift clock signal SCLK (not shown) generated on Graphics hardware 46 is additionally connected to palette 42 (FIG. 1). The outputs from these registers are major bus 60. Graphics hardware 46 operates in con connected to bus 38 in the same manner as the data junction with central processing unit 44 to perform input leads are connected to input bus 28. Thus, data graphic processing operations. In particular, graphics from a row memory, such as row A, would be moved hardware 46 under control of central processing 44 is into register 72 and output serially from each register 72 operable to manipulate data within the bit map portion and in parallel on bus 38. This would occur for each of video RAM 30. plane of the eight VRAM memory array. Memory interface 54 is coupled to bus 60 and further The memory configuration depicted in FIG. 3 is not coupled to video memory bus 28. Memory interface 54 limited to the handling of 4-bit pixel description data. serves to control the communication of data and in 65 For example, if the information for each pixel was to be structions between graphics processor 18 and memory described in eight bits, then two VRAMs 68 would be 20. Memory 20 includes both the bit map data to be required per pixel. Further, for increased ability in han displayed on video display 26 and the instructions and dling data, shift registers 72 would be split in half with 5,420,609 7 8 each half used to output data onto bus 38. The split to pending application, Ser. No. 07/544,775 (Attorney’s register approach allows for differences in the number Docket No. TI-15123). of pixels required by the display and the number of bits FIG. 5 is a more detailed block diagram of a portion per pixel desired. A more complete description of this of selector 78 (also known as the “frame buffer”). In the feature can be found in co-assigned application Ser. No. preferred embodiment, selector 78 receives 32 bits of 07/544,775 (Attorneys’ Docket No. TI-l5l23) and red, green and blue color codes from video RAM 34 hence, will not be repeated here. and outputs four corresponding 8-bit addresses. In FIG. Returning to FIGS. 1 and 2, graphics processor 18 5, only nine inputs (Po-Pg) of the 32 inputs P0-P31) 0f operates in two different address modes to address the preferred embodiment (see FIG. 6) are shown for memory 20. These two address modes are X-Y address convenience. It is important to recognize that numerous ing and linear addressing. In linear addressing, the start con?gurations are possible, such varying numbers of of a ?eld is formed by a single multibit linear address. input bits and output bits can be handled. In the pre The ?eld size is determined by the data within a status ferred embodiment, selector 78 is con?gurable to re register within central processing unit 44. In X-Y ad ceive color codes of either 4, 8, 16 or 32 bits and to dressing, the start address is a pair of X and Y coordi output a corresponding number of l,- 2, 4, or 8-bit ad nate values. The ?eld size is equal to the size of a pixel, dresses, each addressing a location in RAM 76, in re that is, the number of bits required to specify the partic sponse. ~ ular data of a particular pixel. Selector 78 includes a bank of 2:1 multiplexers 96 FIG. 4 is a more detailed depiction of palette 42 em each having an A data input coupled to a respective phasizing the color palette RAM and the circuitry con 20 trolling it. Palette 42 includes an input latch 74 coupled input P. In the preferred embodiment, 32 multiplexers 96 are provided which transfer 32 bits of address data to video memory 20 (see FIG. 1) via bus 38. In the preferred embodiment, input latch 74 receives color (color codes) which arrive at the inputs P0-P31 to a codes output from eight VRAM memories 68 compris corresponding bank of 32 latches 98. The multiplexers pass data from the A inputs to the multiplexer outputs ing video RAM memory 30. Color palette RAM 76 25 provides color data words in response to color codes on the rising edge of signal LD and then hold the data received at input latch 74. Selector 78 couples color until the next DOT clock arrives. The DOT Clock palette RAM 76 and input latch 74, in the illustrated signal DOT latches the 32-bit word from multiplexers embodiment receiving 32 bits of color code data from 92 into the bank of 32 latches 98 and at the same time, latch 74 and outputting 8 bits of address data to color 30 toggles control signal LD, thereby switching the 2:1 palette RAM 76. In the illustrated embodiment color multiplexers to select the B data inputs. See FIG. 6 and palette RAM 76 is a high speed dual-port static RAM the accompanying text below for a more complete un (SRAM); however, color palette RAM 76 may also be derstanding of this switching process. implemented using dynamic random access memories The B inputs of 2:1 multiplexers 96 are fed from an (DRAMs). 35 array of transmission gates con?gured in four groups Graphics processor 18 (FIG. 2) controls the contents comprising 8, 4, 2, and l-bit sections. Transmission gates of the color data words output to video display 26 in 100 comprise the l-bit section, transmission gates 102 response to color codes received at latch 74 by the comprise the 2-bit section, transmission gates 104 com reading and writing of color data words into and out of prise the 4-bit section and transmission gates 106 com color palette RAM 76 using registers and control cir 40 prise the 8-bit section. One set of transmission gates cuitry 80 and bus 34. Palette 42 also includes true color 100-106 is activated at any one time. - pipeline delay 82, clock control circuitry 84, output The inputs of transmission gates 100-106 are respec multiplexer 86 and digital-to-analog converters 8. Also tively coupled to the Q outputs of the 32 latch bank of depicted in FIG. 4 are palette test and accumulator latches 98. Each successive row of transmission gates is registers 90, analog test registers 92, and video multi 45 fed from the latches 98 of the rows below such that data plexer and control circuitry 94. For a more complete can be shifted upward toward the least signi?cant bit description of these components, reference is made to MDd) (the “LSB”). Since a new 32 bit word arrives and pending application Ser. No. 07/544,775 (Attorney’s is switched through selector 78 with every LD, each Docket No., TI-l5l23) incorporated herein by refer DOT clock is 'used to shift groups of data upward ence. through the active transmission gate group during the Palette 42 also is operable in a “nibble mode”. The interval between each rising edge of LD (the “LD “nibble mode” is used in a system con?guration such as clock interval”). Thus, if transmission gates 100 (the 1 that depicted in FIG. 3 in which graphics processor 18 bit group) are activated the data are shifted up by 1 bit, controls two VRAM’s 20a and 20b. VRAM 20a has if transmission gates 102 are activated (the 2 bit group) four VRAM sections with 4-bit nibble-wide shift regis 55 the data are shifted up 2 bits, if transmission gates 104 ters 72 operating in parallel to supply 16 bits of output are activated (the 4 bit group) the data are shifted up 4 connected to the high four nibbles of each byte of a bits, and if transmission gates 106 (the 8 bit group) are four-byte wide input latch 74. VRAM 20a also has four activated the data are shifted up 8 bits. VRAM sections each with 4-bit nibble-wide outputs In the preferred embodiment, the 8 bit address output and has 16 bits of output connected to the low four 60 of selector 78 to color palette RAM 76 is made through nibbles respectively of the 4 bytes of input latch 72. In a bank of eight latches 108 also clocked by clock signal the nibble mode, palette 42 can switch between VRAM DOT. Each DOT clock that initiates an upward data 20a and VRAM 20b. For example, to switch between shift also latches and outputs the 8 bit result of the previ two different images. Graphics processor 18 outputs a ous shift through latches 108. Further, it is important to signal NIBBLE FLAG which directs palette 42 to 65 note that in the preferred operating mode, a continuous output to display 26 either the four high nibbles or the ?ow of the 32-bit words of color codes are received by four low nibbles. For a complete system level descrip selector 78. For high speed operation therefore, the ?rst tion of this special nibble mode, reference is again made DOT after signal LD not only latches the new 32 bit 5,420,609 9 10 word into latches 98, but it also latches and outputs the high which in turn forces signal LD high such that last 8 bit word address of the last 32-bit word received. , multiplexers 96 never switch to pass data from their B Selector 78 (the frame buffer) always outputs an 8-bit data inputs and no shifting occurs. address regardless of the number of bits of color data Transmission gate control circuitry 115 activates the output per pixel. A page register (not shown) is there selected group of transmission gate groups 100, 102, fore used which makes up the missing most signi?cant 104, and 106 to achieve the desired “data wrapping.” bits of any given address when the number of bits per Signals CONTROL 1 and CONTROL 2 are set such address word output is less than 8. } that each divide ratio of the DOT clock to control FIGS. 6a-f are a complete schematic diagram of signal LOAD will activate the corresponding group of selector 78 shown in FIG. 5. FIG. 6 further depicts a 10 transmission gates. The transmission gate group which second set of multiplexers, including 3:1 multiplexers is activated is strictly a function of the number of data 110 (see, e.g., FIG. 6b) and 2:1 multiplexers 112 (FIG. bits/pixel. Thus, for example, when a 16 bit pixel bus is 6b), multiplexer control circuitry 114 (FIG. 6f) and used (i.e. 16 bits are received at inputs P0 to P15) and 2 transmission gate control circuitry 115 (FIG. 6}). Multi bits per pixel are desired (i.e. 2-bit words are output on plexers 110 and 112 are operable to switch VGA pass outputs MD() and MD1) then LOAD will be a divide by through signals directly to the outputs MDO-MD7 and eight of the DOT clock and tranmission gates 102 (the provide for the “special nibble mode”. 2-bit group) will be activated. Similarly, if a 32 bit pizel Multiplexer control circuitry 114 determines the rela bus is used (i.e. 32 bits are received at inputs P0 to P31 tionship between signal LOAD and the DOT clock. and 8 bits per pixel are desired (i.e. 8 bits are output on Multiplexer control circuitry 114 operates in two 20 outputs MDQ to MD7) then LOAD will be a divide by modes. In the ?rst mode, control signal SEQD is set four of the DOT clock and transmission gates 106 (the high (to a logic “l”) by CLOCK control circuitry 84 8-bit group) will be activated. As a ?nal example, when such that control signal LD is forced high and its com- ' a 16 bit pixel bus is used and 4 bits per pixel are desired plement LD is forced low (to a logic “0”) which in turn then LOAD will be a divide by eight of the DOT clock forces multiplexers 96 to always look at the data arriv 25 and transmission gates 104 (the 4-bit group) will be ing at inputs Px and never at the “wrap da ” appearing activated. In this manner, the activation of transmission at the B inputs of multiplexers 96. In this mode, since gates 100/ 102/ 104/ 106 corresponds to the timing of new pixel information (a new color data word) arrives control signal LOAD and the DOT clock. on every DOT edge no “wrapping” is required. In this In the VGA pass through mode, the VGA data ap case, the eight least signi?cant bits received at inputs 30 pearing on VGA connector 43 (FIG. 4) is selected using P0-P7 are received and clocked directly to outputs multiplexers 110 and 112 and directly passed to the MD0~MD7. With each DOT clock, multiplexer control output/latches 108. In a separate special nibble mode, circuitry 115 outputs a signal LD, thereby selecting the one of two 4-bit nibbles comprising the 8-bit word ap A inputs of multiplexers 96. (Therefore, in this mode, pearing on latches 98a-98h is selected and passed multiplexer control circuitry 114 never outputs a signal 35 through to output latches 108a-108d. The outputs of 5 such that the B inputs of multiplexers 96 can be output latches 108e-108h are unused in the special nib selected for “wrapping data”.) The result is a continu ble mode. The selection of the special nibble mode is ous stream of addresses corresponding to the data re made through the application of a signal N/F (nibble ceived at inputs P0-P7 is clocked through to input flag) to be described in further detail below. If the 4 MDO-MD7. least signi?cant bits of the 8-bit word are desired, i.e., In the second operating mode, when data shifting those appearing at the outputs of latches 208a-208d, among latches 98 (FIG. 5) is desired, control signal multiplexers 110 merely pass the data appearing at the SEQD is set low. In this mode of operation, signal LD, outputs of latches 98a-98d directly to outputs which switches the inputs of multiplexers 96 to receive MDO-MD3. If, on the other hand, the four most signi? data at the iinputs, is set'to a logic “1” (and corre 45 cant bits of the 8-bit word, i.e., those signals appearing spondingly LD is set to a logic “0”) on the ?rst DOT at the outputs of latches 98e-98h, are desired, then the clock after receipt of the control signal LOAD. On the four most signi?cant bits are shifted upward four bits by second DOT clock after signal LOAD is received, multiplexers 110 and 112. Speci?cally, the output of select signal LD goes high and signal LD goes low such latch 98e is now coupled to the input of latch 1080 that the B inputs of multiplexers 96 are activated and 50 through multiplexer 110a, the output of latch 98f cou data shifting can occur. Signal LD remains high until pled to the input of latch 108b by multiplexer 110b, the the ?rst DOT clock after receipt of the subsequent output of latch 98g coupled to the input of latch 108a by rising edge of control signal LOAD. multiplexer 1101: and ?nally, the output of latch 98h is The interval between rising edges of control signal coupled to the input of latch 108d by multiplexer 110d. LOAD is equal to the number of bits in the color code 55 Referring to the timing diagram of FIG. 7, a brief received at inputs Po-P31 divided by the number of bits example will demonstrate the operation of the im of each of the addresses to be output on outputs proved frame bu?'er 78 according to the present inven MD0-MD7. For example, if a 32 bit color data word is tion. In this example, the pixel bus width (the number of received at inputs Po-P31 and 8-bits per pixel is desired bits of color codes received from video RAM 30) has at outputs MD0-MD7, for DOT clocks occur between 60 been selected to be 32 bits while the number of bits per each rising edge of control signal LOAD. Thus, each of pixel (i.e. the number of bits of address being output to the four 8-bit addresses making up the 32-bit color code palette RAM 76 to access a color data word for a single can be shifted upward and latched prior to the switch pixel) has been selected to be 8. In the example con?gu ing of a new 32-bit color code through multiplexers 96. ration therefore, each 32-bit word of color codes deliv It is important to note that when control signal LOAD 65 ered from video RAM 30 provides four 8-bit addresses is equal to the DOT clock, i.e., when 8-bit color codes to access color data words for four pixels. For this data are being received and 8-bit addresses are being output, con?guration, four DOT clock intervals are provided clock control circuitry 84 sets control signal SEQD during the LD interval. For convenience, FIG. 7 only