DONALD S. FUSSELL Trammell Crow Regents' Professor Department of Computer Sciences the University of Texas at Austin Austin, T

DONALD S. FUSSELL Trammell Crow Regents’ Professor Department of Computer Sciences The University of Texas at Austin Austin, TX 78712 (512) 471-9719 U.S. Citizen

Education

Ph.D., 1980, Computer Science, The University of Texas at Dallas M.S., 1977, Computer Science, The University of Texas at Dallas B.A., 1973, Mathematics and Social Science, Dartmouth College

Academic Experience

1995– Trammell Crow Regents Professor, Department of Computer Sciences, The University of Texas at Austin 2005– Fellow of the IC2 Institute, The University of Texas at Austin 2005– Associate Director, Digital Media Collaboratory, IC2 Institute, The University of Texas at Austin

1986–94 Associate Professor, Department of Computer Sciences, The University of Texas at Austin 1980–86 Assistant Professor, Department of Computer Sciences, The University of Texas at Austin 1992–94 Director, Advanced Projects Branch, Applied Research Laboratory, The University of Texas at Austin

1998– Member, Institute for Computational Engineering and Sciences, The University of Texas at Austin 1994– Member, Computer Engineering Research Center, The University of Texas at Austin

Industrial Experience

2000-2003 Chief Science Oﬃcer and Vice President of Research and Development, Matrix.Net, Inc., Austin, Texas In charge of all technical operations for Internet infrastructure startup On leave from UT.

1998 Consultant, Austin Ventures, Inc., Austin, Texas Evaluation of 3-D graphics architecture.

1 1996 Consultant, Motorola Inc., Austin, Texas Evaluation of signal processing architecture. 1994 Consultant, Cirrus Logic, Inc., Fremont, California, Evaluation of 3-D graphics architecture. 1992-2001 Member, Technical Advisory Board, VTEL Inc., Austin, Texas

1991 Consultant, IBM Corporation, Austin, Texas Design of high-performance graphics display subsystem. 1989 Consultant, Ross Technology, Inc. Austin, Texas Expert in trade secrets lawsuit.

1987–88 Consultant, AT&T Bell Laboratories, Murray Hill, NJ Design of large-scale multiprocessor for high-performance graphics. 1987 Visiting Member of Technical Staﬀ, AT&T Bell Laboratories, Murray Hill, NJ Design of large-scale multiprocessor for high-performance graphics. 1985–86 Consultant, McGinnis, Lockridge and Kilgore, Austin, Texas Expert witness in trade secrets lawsuit. 1984 Consultant, IBM Corporation, Austin, Texas Design of RT-PC system display architecture. 1982–83 Consultant, Bausch and Lomb, Austin, Texas Design review of drafting system software. 1981–82 Consultant, V-R Information Systems, Inc., Austin, Texas Design of interactive graphics command input system for design automation software. 1981–83 Founder and Vice President of Research and Development, Infovision, Inc., Austin, Texas Austin startup creating turnkey interactive CAD systems for architects, draftsmen, and engi- neers. 1981 Visiting Faculty Associate, IBM Corporation, Austin, Texas Hardware/software design of experimental prototype systems.

Research Interests

Computer Graphics Computer Games and Immersive Training and Education

Grant and Contract Support

2 Technical Lead - US Army Subcontract from Camber Inc. “Immersive Courseware for AMEDD Field Medical Training”, April 1, 2005 through May 31, 2007 for the amount of $1,600,000. Principal Investigator - TARP “The MetaBuffer: Combining Realtime Parallel Graphics with Multiresolution VR Displays”, January 1, 2000 through December 31, 2001 for the amount of $168,000. Principal Investigator - NSF Grant CDA 96-24082 “System Support for a Hierarchy of Distributed Applications,” October 1, 1996 through September 30, 2001 for the amount of $996,000. Principal Investigator - Fujitsu Labs of America, Inc. Contract “Application of Learning Techniques to Combinational Verification,” January 1, 1996 through July 30, 1996 for the amount of $8,000. Principal Investigator - Fujitsu Labs of America, Inc. Contract “Computer Aided Design of VLSI Circuits,” April 1, 1996 through March 31, 1999 for the amount of $6,000. Principal Investigator - SRC Contract 97-DJ-388 “Automated Verification of Large Systems” September 1, 1997 through May 31, 1998 for the amount of $150,000. Co-Principal Investigator - Semiconductor Research Corporation Contract 95-DJ-388, “Integrated Approaches to Test and Verification,” September 1, 1995 through August 31, 1996 for the amount of $300,000. Co-Principal Investigator - SRC Contract 94-DP-388 “Formal Techniques for Test and Verification of Circuits” September 1, 1994 through August 31, 1995 for the amount of $420,000. Principal Investigator - NASA Contract 3573-IST94-0080 “Multiresolution Information Archival and Analysis System” September 1, 1994 through August 31, 1998 for the amount of $763,000. Co-Principal Investigator - Texas Advanced Technology Program ATPD-469 “Software Tools for Automated Formal Verification and Verification-Based Test” January 1, 1994 though December 31, 1995 for the amount of $275,640. Co-Principal Investigator - Texas Advanced Research Program ARP-209 “Towards Multiresolution Database Management Systems” January 1, 1994 through December 31, 1995 for the amount of $150,226. Co-Principal Investigator - NSF Grant IRI-9312003 “Towards Multiresolution Database Management Systems” November 15, 1993 through October 31, 1996 for the amount of $317,998. Principal Investigator - SRC Contract 93-DJ-292 “Multilevel Verification and Testing of VHDL Designs” June 1, 1993 through May 31, 1994 for the amount of $150,000 extended through August 31, 1994 for an additional $38,250. Principal Investigator - SRC Contract 92-DJ-292 “Novel Techniques for Design Verification and Verification-Based Test” June 1, 1992 through May 31, 1993 for the amount of $149,000. Co-Principal Investigator - ONR Contract N00014-86-K-0763 “Formulation and Programming of Distributed and Parallel Computation”

3 University Research Initiative Program, September 15, 1986 through October 1, 1989 for the amount of $2,065,613. Principal Investigator - ONR Contract N00014-86-K-0597 “The METRIC Architecture–Eﬃcient Concurrent Execution Through Modular Micro-Parallelism” July 1, 1986 through December 31, 1988 for the amount of $280,000. Co-Investigator - ONR Contract N00014-86-G-0199 “A Design and Execution Environment for Parallel Computations” Department of Defense University Research Instrumentation Program, September 1, 1986 through August 1, 1988 for the amount of $600,000. Principal Investigator - ONR Contract N00014-83-K-0730 “Fault-tolerance and Wafer-scale Integration in VLSI” August 1, 1983 through December 31, 1986 for the amount of $367,972. Principal Investigator - IBM Corporation Grant “Characterization of Distributed Control Schemes” June 1, 1982 through December 31, 1982 for the amount of $16,000. Principal Investigator - NSF Grant MCS-8109489 “Stochastic Modeling of Complex Phenomena in Computer Graphics” August 1, 1981 through January 31, 1984 for the amount of $59,861. Co-Principal Investigator - NSF Grant MCS-8104017 “Theory and Applications of Database Concurrency Control” June 1, 1981 through November 30, 1983 for the amount of $100,001. Extended through May 31, 1986 in the additional amount of $155,511.

PhD Students

C. Mohan, Graduation: August 1981. I.V. Ramakrishnan, Graduation: May 1983. Peter Varman, Graduation: August 1983. Krishna Palem, Graduation: May 1986. Richard Simpson, Graduation: May 1988. Ramakrishna Thurimella, Graduation: August 1989. Chris Buckalew, Graduation: August 1990. Sampath Rangarajan, Graduation: September 1990. Shinichiro Haruyama, Graduation: September 1990. K.R. Subramanian, Graduation: September 1990. Karl Kelvin Thompson, Graduation: May 1991. Won Woo Park, Graduation: August 1991. Alvin T. Campbell, Graduation: December 1991. Boaz Super, Graduation: August 1992.

4 Jawahar Jain, Graduation: May 1993. John Bunda, Graduation: May 1993. Mark Tarlton, Graduation: August 1993. Jihun Park, Graduation: August 1994. Robert Read, Graduation: May 1995. Glenn G. Lai, Graduation: August 1995. Priyadarsan Patra, Graduation: December 1995. Wei Xu, Graduation: May 2000. Emilio Camahort, Graduation: May 2001. Dana Marshall, Graduation: May 2001.

Journal Publications

1. “Computer Rendering of Stochastic Models” (with A. Fournier and L. Carpenter), Communi- cations of the ACM, vol. 24, no. 6, June 1981, pp. 371–384. 2. “Compatibility and Commutativity of Lock Modes” (with C. Mohan and A. Silberschatz), Information and Control, vol. 61, no. 1, April 1984, pp. 38–64. 3. “A Robust Matrix-Multiplication Array” (with I.V. Ramakrishnan and P. Varman), IEEE Transactions on Computers, October, 1984, pp. 919–922. 4. “Lock Conversion in Non-two-phase Protocols” (with C. Mohan and A. Silberschatz), IEEE Transactions on Software Engineering, January, 1985. 5. “On the Power of the Frame Buffer” (with A. Fournier), ACM Transactions on Graphics, vol. 7, no. 2, April 1988, pp. 103–128. 6. “On Mapping Homogeneous Graphs on a Linear Array-Processor Model” (with I.V. Ramakr- ishnan and A. Silberschatz), IEEE Transactions on Computers, vol. C-35, no. 3, pp. 189–209. 7. “Fault-tolerant VLSI Sorters” (with P. Varman and I.V. Ramakrishnan), Journal of Circuits, Systems, and Signal Processing, vol. 6, no. 2, 1987, pp. 153–174. 8. “Illumination Networks: Fast Realistic Rendering with General Reflectance Functions” (with C. Buckalew), Computer Graphics, vol. 23, no. 3, August, 1989, pp. 89–98. 9. “Built-In Testing of Integrated Circuit Wafers” (with S. Rangarajan and M. Malek) IEEE Transactions on Computers, February, 1990. 10. “Successive Approximation in Graph Algorithms” (with R. Thurimella) Theoretical Computer Science, 74, pp. 19–35. 11. “Adaptive Mesh Generation for Global Diffuse Illumination” (with A.T. Campbell), Computer Graphics, vol. 24, no. 3, August, 1990, pp. 155–164. 12. “Probabilistic Verification of Boolean Functions” (with J. Abraham, J. Bitner and J. Jain), Formal Methods in Systems Design, vol. 1, no. 1, Kluwer Academic Publishers, 1992, pp. 61– 115.

5 13. “Topological Channel Routing” (with S. Haruyama and D.F. Wong), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 11, no. 10, October 1992, pp. 1177–1197. 14. “Diagnosing Arbitrarily Connected Parallel Computers with High Probability” (with S. Ran- garajan), IEEE Transactions on Computers, vol. 41, no. 5, May, 1992. 15. “Finding Triconnected Components By Local Replacement” (with V. Ramachandran and R. Thurimella) SIAM Journal on Computing, vol. 22, no. 3, pp. 586–616, June 1993. 16. “Pipelined Diagnosis of Wafer-Scale Linear Arrays” (with S. Rangarajan and M. Malek), Jour- nal of Parallel and Distributed Computing, vol. 20, no. 2, February 1994, pp. 212–223. 17. “Hinted Quad Trees for VLSI Geometry DRC Based on Efficient Searching for Neighbors” (with G.G. Lai and D.F. Wong), IEEE Transactions on Computer-Aided Design, vol. 15, no. 3, March 1996, pp. 317–324. 18. “Automatic Verification of Implementations of Large Circuits Against HDL Specifications” (with Y. Hoskote, J. Abraham and J. Moondanos), IEEE Transactions on Computer Aided Design, vol. 16, no. 3, March 1997, pp. 217-228.

19. “Forward Dynamics Based Realistic Animation of Rigid Bodies” (with J. Park), Computers and Graphics, vol. 21, no. 4, September, 1997, pp. 483–496. 20. “Indexed BDDs: Algorithmic Advances in Techniques to Represent and Verify Boolean Func- tions” (with J. Jain, J. Bitner, M. Abadir, and J.A. Abraham), IEEE Transactions on Com- puters, vol. 46, no. 11, November, 1997, pp. 1230–1245.

21. “FLOVER - A Filtering Based Approach to Combinatorial Veriﬁcation” (with R. Mukherjee, J. Jain, M. Fujita, and J. Abraham), IEEE Transactions on Computer-Aided Design, November 1999. 22. “Lossless Subdivision-Based Representation of Arbitrary Meshes using Kite Trees” (with W. Xu, R. Hammersley, and K. Lu), International Journal on the Foundations of Computer Science, Special Issue on Volume and Surface Triangulations, Winter 2001.

6 Refereed Conference Presentations

1. “Stochastic Modeling in Computer Graphics” (with A. Fournier), Seventh Annual Conference on Computer Graphics and Interactive Techniques, July 1980. 2. “Deadlock Removal Using Partial Rollback in Database Systems” (with Z. Kedem and A. Silberschatz), 1981 ACM SIGMOD International Conference on Management of Data, April 1981. 3. “A Theory of Correct Locking Protocols for Database Systems” (with Z. Kedem and A. Sil- berschatz), Seventh International Conference on Very Large Data Bases, September 1981. 4. “Compatibility and Commutativity in Non-Two-Phase Locking Protocols” (with C. Mohan and A. Silberschatz), ACM SIGACT-SIGMOD Symposium on Principles of Database Systems, March 1982. 5. “Fault-tolerant Wafer-scale Architectures for VLSI” (with P. Varman), Ninth Annual Sympo- sium on Computer Architecture, April 1982. 6. “A VLSI-oriented Architecture for Real-time Raster Display of Shaded Polygons” (with D. Rathi), Graphics Interface ’82, May 1982. 7. “A Biased Non-Two-Phase Locking Protocol” (with C. Mohan and A. Silberschatz), Second International Conference on Databases-Improving Usability and Responsiveness, June 1982. 8. “Realizing Fault-tolerant Binary Trees in VLSI” (with P. Varman), Twentieth Annual Allerton Conference on Communications, Control, and Computing, October 1982. 9. “Systolic Matrix Multiplication on a Linear Array” (with I.V. Ramakrishnan and A. Silber- schatz), Twentieth Annual Allerton Conference on Communications, Control, and Computing, October 1982. 10. “On Mapping Cube Graphs onto Linear Systolic Arrays” (with I.V. Ramakrishnan and A. Silberschatz), Conference on Information and Systems Science, The Johns Hopkins University, March 1983. 11. “Fault-tolerant (VLSI) Data Structures” (with P. Varman), Conference on Information and Systems Science, The Johns Hopkins University, March 1983.

12. “On Mapping Homogeneous Graphs on a Linear Array-Processor Model” (with I.V. Ramakr- ishnan and A. Silberschatz), 1983 International Conference on Parallel Processing, August 1983. 13. “Design of Robust Systolic Algorithms” (with P. Varman), 1983 International Conference on Parallel Processing, August 1983.

14. “Robust Systolic Algorithms for Relational Database Operations” (with I.V. Ramakrishnan, A. Silberschatz, and P. Varman), 1983 Real-time Systems Symposium, December 1983. 15. “The Complexity of Scheduling Systems of Non-identical Processors” (with K. Palem), 1984 Annual Southeastern Conference on Combinatorics, Graph Theory, and Computing, March 1984.

16. “Designing Systolic Algorithms for Fault-tolerance” (with P. Varman), Fifth Annual Interna- tional Conference on Computer Design, October 1984.

7 17. “On Hypergraph Characterizations of Multiprocessor Scheduling - Algorithms through Slicing Arguments” (with K. Palem), The Symposium on the Complexity of Approximately Solved Problems, Columbia University, New York, NY, April 17-19, 1985. 18. “Token-triggered Systolic Diagnosis of Wafer-scale Arrays” (with Y. H. Choi and M. Malek), Workshop on Wafer-scale Integration, Southampton University, England, July 10-12, 1985. 19. “Straight-Line Testing of Switches for Wafer-Scale Processor Arrays” (with Y. H. Choi and M. Malek), 1986 International Conference on Computer Aided Design, November, 1986. 20. “Vertex Decompositions of Planar Graphs” (with R. Thurimella), Symposium on Combina- torics and Complexity, Chicago, Ill., June 1987. 21. “A New Algorithm for Routing Power and Ground Nets on a Single Layer” (with S. Haruyama), 1987 International Conference on Computer Aided Design, November, 1987. 22. “A Probabilistic Method for Fault Diagnosis of Multiprocessor Systems” (with S. Rangarajan), 1988 International Symposium on Fault-Tolerant Computing, June, 1988. 23. “Separation Pair Detection” (with R. Thurimella), 1988 Aegean Workshop on Computing, June, 1988. 24. “Fault Diagnosis of Linear Processor Arrays” (with S. Rangarajan and M. Malek), IEEE International Workshop on Defect and Fault-Tolerance in VLSI Systems, October, 1988. 25. “Topological Channel Routing” (with S. Haruyama and M. Wong), 1988 International Con- ference on Computer Aided Design, November, 1988. 26. “Successive Approximation in Parallel Graph Algorithms” (with R. Thurimella), 6th Annual Symposium on Theoretical Aspects of Computer Science, February, 1989. 27. “Probabilistic Diagnosis of Multiprocessor Systems with Arbitrary Connectivity” (with S. Rangarajan), 1989 International Symposium on Fault-Tolerant Computing, June, 1989. 28. “Finding Triconnected Components by Local Replacement” (with V. Ramachandran and R. Thurimella), 16th International Colloquium on Automata, Languages and Programming, July, 1989. 29. “Applying Space Subdivision Techniques to Volume Rendering” (with K.R. Subramanian), Visualization 90, October 1990. 30. “Topological Routing Using Geometric Information” (with S. Haruyama and M. Wong) 1990 International Conference on Computer Aided Design, November, 1990. 31. “Rectifying Corrupted Files in Distributed File Systems” (with S. Rangarajan) 1991 Interna- tional Conference on Distributed Computing Systems, May 1991, pp. 446–453. 32. “Automatic Termination Criteria for Ray-tracing Hierarchies” (with K.R. Subramanian) Graph- ics Interface 91, May 1991, pp. 93–100. 33. “Probabilistic Diagnosis Algorithms Tailored to System Topology’ (with S. Rangarajan) 1991 International Conference on Fault-Tolerant Computing, June 1991, pp. 230–239. 34. “Advantages of Multithreaded Processors” (with R. Jenevein and W.W. Park) 1991 Interna- tional Conference on Parallel Processing, August 1991, pp. I97–101. 35. “Probabilistic Design Veriﬁcation” (with J. Abraham, J. Bitner and J. Jain), Proceedings of the 1991 IEEE International Conference on Computer Aided Design, November, 1991.

8 36. “Efficient Fault Diagnosis of Switches in Wafer Arrays” (with M. Malek and S. Rangarajan), Proceedings of the 1992 International Conference on Wafer-Scale Integration, January, 1992, pp. 341–351. 37. “IBDDs: An Efficient Functional Representation for Digital Circuits” (with M. Abadir, J. Abraham, J. Bitner and J. Jain), Proceedings of the 1992 European Conference on Design Automation, March 1992, pp. 440–446. 38. “Functional Partitioning for Verification and Related Problems” (with J. Abraham, J. Bitner and J. Jain), Proceedings of the 1992 Brown/MIT Conference on Advanced Research in VLSI and Parallel Systems, May 1992, pp. 210–226. 39. “Non-Uniform Patch Luminance for Global Illumination” (with B. Bian and N. Wittels), Proceedings of Graphics Interface ’92, June 1992. 40. “Efficient Verification of Multipliers and Other Difficult Functions Using IBDDs” (with J. Abraham, J. Bitner and J. Jain), Proceedings of the 1992 Custom Integrated Circuits Confer- ence, June 1992. 41. “A Multi-Resolution Relational Data Model”(with R. Read and A. Silberschatz), Proceedings of the 18th International Conference on Very Large Databases, August 1992. 42. “Motion Control Using Extended Generalized Coordinate Transformations” (with J. Park and J.C. Browne), Proceedings 1992 Eurographics Workshop on Animation, September 1992. 43. “Realistic Animation Using Musculotendon Skeleton Dynamics and Suboptimal Control” (with J. Park, J.C. Browne and M. Pandey), Proceedings 1992 Eurographics Workshop on Anima- tion, September 1992. 44. “Following Footprints of Reality” (with J. Park and M. Pandey), Proceedings of the First Pacific Conference on Computer Graphics and Applications, August 1993. 45. “16-Bit vs. 32-Bit Instructions for Pipelined Microprocessors” (with J. Bunda, W. Athas, and R. Jenevein), Proceedings of the 20th Annual International Symposium on Computer Architecture, May 1993. 46. “HV/VH Trees: A New Spatial Data Structure for Fast Region Queries” (with G. Lai and D.F. Wong), Proceedings of the 30th Annual Design Automation Conference, June 1993. 47. “System Wide Multiresolution” (with R. Read and A. Silberschatz), Proceedings of the Inter- national Workshop on Next Generation Information Technologies and Systems, June 1993. 48. “Using Indexed BDDs in Specifying and Verifying Complex Circuits” (with M. Abadir, J.A. Abraham, J. Bitner and J. Jain) Proceedings of the 1993 IFIP Workshop on Logic and Archi- tecture Synthesis, December, 1993. 49. “Abstraction of Data Path Registers for Multilevel Verification of Large Circuits” (with J.A. Abraham, Y. Hoskote and J. Moondanos) Proceedings of the Fourth Great Lakes Symposium on VLSI, March, 1994. 50. “A New Scheme to Compute Variable Orders for Binary Decision Diagrams” (with J.A. Abra- ham, J. Bitner, J. Jain and D. Moundanos) Proceedings of the Fourth Great Lakes Symposium on VLSI, March, 1994. 51. “Evaluating Power Implications of CMOS Microprocessor Design Decisions” (with J. Bunda and W. Athas) Proceedings of the 1994 International Workshop on Low Power Design, April, 1994.

9 52. “Constructing Solvers for Radiosity Equation Systems”(with W. Xu), Proceedings of the Fifth Eurographics Workshop on Rendering, June, 1994. 53. “Efficient Algorithmic Circuit Verification Using Indexed BDDs” (with M. Abadir, J.A. Abra- ham, J. Bitner and J. Jain), Proceedings of the 24th Annual International Symposium on Fault-Tolerant Computing, June, 1994. 54. “A Fast Solver of Radiosity Equation Systems” (with W. Xu), Proceedings of the Second Pacific Conference on Computer Graphics and Applications, August, 1994. 55. “Analysis and Improvement of Some Testability Measure Approximation Algorithms” (with J. Abraham, J. Bitner and J. Jain), Proceedings of the 1994 Asia Test Symposium, November, 1994.

56. “Efficient Building Blocks for Delay-Insensitive Circuits,” (with P. Patra), Proceedings of the 1st IEEE International Symposium on Advanced Research in Asynchronous Circuits and Systems, Nov. 1994, pp. 196–205. 57. “Energy-Efficient Instruction Set Architecture for CMOS Processors,” (with J. Bunda and W. Athas), Proceedings of the Twenty-Eighth Annual Hawaii International Conference on System Sciences, Jan. 1995, vol. 1, pp. 298–305. 58. “Power-Efficient Delay-Insensitive Codes for Data Transmission,” (with P. Patra), Proceedings of the Twenty-Eighth Annual Hawaii International Conference on System Sciences, Jan. 1995, vol. 1, pp. 316–323. 59. “Fully Asynchronous, Robust, High-throughput, Arithmetic Structures,” (with P. Patra), Pro- ceedings of Eighth International Conference on VLSI Design, Jan. 1995. 60. “Efficient Variable Ordering and Partial Representation Algorithms” (with Jawahar Jain, Di- nos Moundanos, James Bitner, Jacob A. Abraham, and Don E. Ross), Proceedings of Eighth International Conference on VLSI Design, Jan. 1995, pp. 81–86.

61. “Automated verification of temporal properties specified as state machines in VHDL” (with J. A. Abraham and Y. V. Hoskote), Proceedings Fifth Great Lakes Symposium on VLSI, Buffalo, NY, March 1995, pp. 100–105. 62. “Observations on Verification Techniques Based On Learning” (with Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita and Jacob A. Abraham), Proceedings of the 1995 ACM/IEEE International Workshop on Logic Synthesis, pp. 6.31–6.40. 63. “On More Efficient Combinational ATPG using Functional Learning” (with R. Mukherjee, J. Jain, M. Fujita, J.A. Abraham), Proc. 9th International Conference on VLSI Design, January 1996, pp. 107-110. 64. “IFS Coding with Multiple DC Terms and Domain Blocks” (with W. Xu), Proc. ImageTech Conf. on Imaging Mathematics and Applications, Atlanta, GA, Mar. 1996 65. “Efficient delay-insensitive RSFQ circuits” (with P. Patra), Proceedings of International Con- ference on Computer Design, 1996, IEEE Computer Society, October 1996. 66. “Conservative delay insensitive circuits” (with P. Patra), Proceedings of the Fourth Workshop on Physics and Computation, 1996, New England Institute for Complex Systems, November 1996.

10 67. “On efficient adiabatic design of MOS circuits” (with P. Patra), Proceedings of the Fourth Workshop on Physics and Computation, 1996, New England Institute for Complex Systems, November 1996. 68. “Delay insensitive logic for RSFQ superconductor technology” (with P. Patra and S. Polonsky), Proceedings of the Third International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC ’97), IEEE Computer Society, April 1997. 69. “Multiresolution BSP Trees Applied to Terrain, Transparency, and General Objects” (with C.A. Wiley, A.T. Campbell, S. Szygenda, and F. Hudson), Proceedings Graphics Interface ’97, May 1997. 70. ‘Multiresolution Rendering of Complex Botanical Scenes” (with D. Marshall and A.T. Camp- bell) Proceedings Graphics Interface ’97, May 1997. 71. “Model Simplification Using Directional Clustering” (with D. Marshall and A.T. Campbell), Technical Sketch, SIGGRAPH ’97, August, 1997. 72. “Uniformly Sampled Light Fields,” (with E. Camahort and A. Lerios), Proceedings of the Ninth Eurographics Workshop on Rendering, Vienna, Austria, July 1998. 73. “Digital Warrior: Blending Pedagogy and Game Technology,” (with Aubrey White, John Stawasz, Sheilagh O’Hare, Roy Jenevein, and Darrell Woelk), The Interservice/Industry Train- ing, Simulation and Education Conference, Orlando, FL, November 28–December 1, 2005 74. “Interactive Lesion Segmentation on DCE MRI using a Markov Model,” (with Q. Wu, M. Salganicoff, A. Krishnan, and M. Markey), SPIE Medical Imaging: Image Processing, pp. 1487–1496, 2006. 75. “Registration of DCE MR Images for Computer-aided Diagnosis of Breast Cancer,” (with Q. Wu, G. Whitman, and M. Markey), IEEE 40th Asilomar Conference on Signals, Systems, and Computers, October 2006. 76. “Parametric Kernels for Sequence Data Analysis,” (with Y. Shin), Proceedings of the 20th International Joint Conference on Artificial Intelligence, Hyderabad, India, January 6–12, 2007. 77. “Fast and Lazy Build of Acceleration Structures from Scene Hierarchies,” (with W. Hunt and W. Mark), 2007 IEEE/EG Syposium on Interactive Ray Tracing, Ulm, Germany, October 10–12, 2007. 78. “Ray Scheduling to Improve Ray Coherence and Bandwidth Utilization,” (with P. Navratil, W. Mark, and C. Lin), 2007 IEEE/EG Syposium on Interactive Ray Tracing, Ulm, Germany, October 10–12, 2007. 79. “A Line-Space Analysis of Light-Field Representations” (with E. Camahort and F. Abad), Graphical Models 71(5):169-183, September 2009, doi:10.1016/j.gmod.2009.02.003 80. “Fast, Exact, Linear Booleans” (with G. Bernstein), Proceedings of the Eurographics Sym- posium on Geometry Processing, Berlin, July 15-19, 2009, published as Computer Graphics Forum 28-5:1269-1278, Eurographics Association. 81. “Frankenrigs: Building Character Rigs from Multiple Sources” (with C. Miller and O. Arikan), in ACM SIGGRAPH Symposium on Interactive 3D Graphics and Games, ACM Press, Febru- ary 2010. 82. “Increasing Hardware Utilization for Peta-Scale Visualization” (with P. Navratil and C. Lin), Proceeedings of the 6th High-End Visualization Workshop, December 2010, Obergurgl, Austria.

11 Book Chapters

“Wafer-scale Testing/Design For Testability,” in Wafer-scale Integration, Earl Swartzlander, ed., Kluwer Academic Publications, 1989.

Books

Responsive Computer Systems: Steps Toward Fault-Tolerant, Real-Time Systems, Don- ald S. Fussell and Miroslaw Malek, ed., Kluwer Academic Publications, 1995.