Iowa State University Capstones, Theses and Graduate Theses and Dissertations Dissertations
2014 Design of a class-F power amplifier with reconfigurable output harmonic termination in 0.13 µm CMOS Kossi Komi Sessou Iowa State University
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Recommended Citation Sessou, Kossi Komi, "Design of a class-F power amplifier with reconfigurable output harmonic termination in 0.13 µm CMOS" (2014). Graduate Theses and Dissertations. 13663. https://lib.dr.iastate.edu/etd/13663
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Design of a class-F power amplifier with reconfigurable output harmonic termination in 0.13 µm CMOS
by
Kossi Komi Sessou
A thesis submitted to the graduate faculty
in partial fulfillment of the requirements for the degree of
MASTER OF SCIENCE
Major: Electrical Engineering
Program of Study Committee: Nathan Neihart, Major Professor Ayman Fayed Mani Mina
Iowa State University
Ames, Iowa
2014
Copyright © Kossi Komi Sessou, 2014. All rights reserved. ii
TABLE OF CONTENTS
Page
LIST OF FIGURES ...... iv
LIST OF TABLES ...... vi
NOMENCLATURE ...... vii
ACKNOWLEDGEMENTS ...... ix
ABSTRACT………………………………...... x
CHAPTER 1 INTRODUCTION: ...... 1
1.1 Motivation ...... 1 1.2 Thesis Organization ...... 3
CHAPTER 2 RF POWER AMPLIFIER OVERVIEW ...... 4
2.1 Linear Power Amplifiers ...... 4 2.1.1 Class A Power Amplifiers ...... 5 2.1.2 Class B Power Amplifiers ...... 6 2.1.3 Class C Power Amplifiers ...... 7 2.2 Switch Mode Power Amplifiers...... 8 2.2.1 Class D Power Amplifiers ...... 8 2.2.2 Class E Power Amplifiers ...... 8 2.2.3 Class-F Power Amplifiers ...... 9 2.3 Advanced Mode Power Amplifiers ...... 11
CHAPTER 3 DESIGN OF AN OUTPUT MATCHING NETWORK SUITABLE FOR COGNITIVE RADIO APPLICATIONS ...... 13
3.1 Re-configurability of Power Amplifiers ...... 15 3.1.1 Multi-Band Approach ...... 15 3.1.2 Wide-Band approach ...... 16 3.2 Proposed Wide Band PA with Tunable Harmonics ...... 18
CHAPTER 4 CIRCUIT IMPLEMENTATION ...... 23
4.1 Power Transistor Consideration and Load Pull Simulations ...... 23
iii
4.2 Main PA Module ...... 25 4.3 Input Matching Network ...... 30 4.4 Stability ...... 31
CHAPTER 5 MEASUREMENT RESULTS ...... 34
5.1 Test Bench Setup ...... 34 5.2 Measurement Procedure...... 36 5.3 Performance Measurement ...... 37 5.3.1 Small Signal Characteristics ...... 37 5.3.2 Large Signal Characteristics ...... 40 5.3.3 Performance at 1200 MHz ...... 43
CHAPTER 6 SUMMARY AND CONCLUSION ...... 47
6.1 Summary ...... 47 6.2 Perspectives...... 47
APPENDIX MEASUREMENT MATLAB SCRIPS ...... 49
REFERENCES ...... 55
iv
LIST OF FIGURES
Page
Fig. 2.1 Basic power amplifier structure ...... 5
Fig. 2.2 Drain voltage and current waveform shaping with different number of harmonic peaking ...... 10
Fig. 3.1 Mobile handset radio today ...... 14
Fig. 3.2 Schematic of (a) the proposed 4th-order resonant tank and (b) the
frequency response of ZIN with and without a 50 termination ...... 20
Fig. 3.3 Resonator poles and zeros contours ...... 21
Fig. 3.4 Proposed load network with single FET active device ...... 22
Fig. 4.1 Stack-FET active device schematic ...... 23
Fig. 4.2 Stack-FET active device layout ...... 24
Fig. 4.3 Simplified schematic of the proposed class-F power amplifier with tunable harmonic termination ...... 27
Fig. 4.4 Time domain lumped-element model for the transformer ...... 27
Fig. 4.5 Third harmonic control transformer layout ...... 28
Fig. 4.6 Second harmonic control transformer layout ...... 28
Fig. 4.7 Momentum extraction of the a)Winding inductance, b)Quality factor and c) Coupling coefficient of the third harmonic control transformer...... 29
Fig. 4.8 Momentum extraction of the a)Winding inductance, b)Quality factor and c) Coupling coefficient of the second harmonic control transformer ...... 29
Fig. 4.9 Wideband resistive input matching network...... 31
Fig. 4.10 Stability from 700 MHz to 1200 MHz ...... 32
Fig. 4.11 Die photograph. total area, with pads is 1.5 mm 1.5 mm ...... 33
Fig. 5.1 Measurement bench setup ...... 35
Fig. 5.2 Measurement test bench setup for large signal ...... 35
v
Fig. 5.3 Measurement test bench setup for small signal ...... 36
Fig. 5.4 Measured and simulated small signal input return loss S11 from 700 MHz to 1200 MHz ...... 38
Fig. 5.5 Measured and simulated small signal performance S21 (a) 700 MHz (b) 900 MHz (c) 1200 MHz ...... 39
Fig. 5.6 Simulated and measured large signal performance: Gain and PAE for the PA configured to operate at (a) 700 MHz, (b) 900 MHz, and (c) 1200 MHz ...... 40
Fig. 5.7 Simulated and measured large signal performance: Pout for the PA configured to operate at 700 MHz, 900 MHz, and 1200 MHz ...... 41
Fig. 5.8 Simulated and measured large signal performance (left) and small signal (right) at 1200 MHz after transformer correction ...... 43
Fig. 5.9 Simulated and measured large signal performance (left) and small signal (right) at 900 MHz after transformer correction ...... 44
Fig. 5.10 Simulated and measured large signal performance (left) and small signal (right) at 700 MHz after transformer correction ...... 44
Fig. 5.11 Simulated and measured input return loss at 700 MHz, 900 MHz and 1200 MHz after transformer correction ...... 45
vi
LIST OF TABLES
Page
Table 2.1 Summary of power amplifier classes and merits ...... 12
Table 5.1 Operating frequency selection ...... 37
Table 5.2 Summary of power amplifier performance compared to previously published designs ...... 42
vii
NOMENCLATURE
RFC Radio Frequency Choke
FCC Federal Communications Commission
GSM Global System for Mobile Communication
LTE Long Term Evolution
3GPP 3rd Generation Partnership Project
WiMAX Worldwide Interoperability for Microwave Access
WCDMA Wideband Code Division Multiple Access
CMOS Complementary Metal Oxide Semiconductor
MOSFET Metal Oxide Field Effect Transistor
BJT Bipolar Junction Transistor
HEMT High Electron Mobility Transistor
QAM Quadrature Amplitude Modulation
P-I-N P dopped - Intrinsic (undopped) - N dopped region
MEMS Micro-Electromechanical Systems
MMIC Monolithic Microwave Integrated Circuit
ADS Advanced Design System
FR-4 Flame Retardant 4
DUT Device Under Test
GPIB General Purpose Interface Bus
VSG Vector Signal Generator
RMS Root Mean Square
viii
CW Continuous Wave
Q Quality Factor
ix
ACKNOWLEDGEMENTS
It is with a great pleasure that I acknowledge the many people who have helped me through this journey. Most importantly, I would like to thank Dr. Nathan M. Neihart for his support, guidance and mentorship throughout my graduate study here at Iowa State
University. Also, thank you to Dr. Ayman Fayed and Dr. Mani Mina for being on my committee and providing advice and support.
A special thanks goes out to MOSIS, Marina del Rey, CA, for providing 0.130 µm
CMOS process fabrication support. Additional thanks are reserved to everyone else who helped along the way, especially Mr. Leland E. Harker for helping me with my evaluation board fabrication and critical packaged die mounting.
In addition, I would also like to thank my friends, colleagues, the department faculty and staff for making my time at Iowa State University a wonderful experience.
Finally, I would like to thank my family for all the financial help and the source of unending love and support in my entire education journey. My parents deserve all the credits for teaching me the sense of hard work, perseverance and ethics. They have led me to where
I am now and I cannot thank them enough.
x
ABSTRACT
Next generation wireless communication technology requires mobile devices and base stations to support multiband multimode frequencies with higher data rate because of the type of enriched and enhanced features and services that are provided to the end user. The challenge for next generation PA designers is to provide high efficiency, output power and good linearity across multiple frequency bands, modulation standards and bandwidth.
Current industry solution involves parallel PAs dedicated to a single band of operation. As more and more features are added, more and more PAs will be required with increasing cost, area and complexity. As a solution to this problem, one tunable fully integrated class-F power amplifier with reconfigurable output harmonic termination is proposed, designed, fabricated and tested with a commercially available 0.13µm CMOS process technology. By using the coupling between the primary and the secondary winding of an on chip transformer with a variable secondary termination capacitance, the second and third harmonic short and open circuit frequencies are dynamically tuned from 700 MHz to 1200 MHz and achieve high efficiency and output power. To overcome CMOS process low break down voltage, a series voltage combining approach is used for the power device to boost output power, by allowing the power supply to exceed process limits.
The fabricated die was packaged and mounted to a printed circuit board for evaluation.
Compared to previously publish fully integrated PAs, our design exhibits superior peak power added efficiency, 48.4%, and decent saturated output power and power gain of 24.6 dBm and 16.5 dB respectively with reconfigurability from 700 MHz to 1200 MHz.
1
CHAPTER I
INTRODUCTION
1.1 Motivation
The challenge for next generation PA designers is to maintain high efficiency and good linearity across multiple different frequency bands, modulation standards, and bandwidths.
With mobile technology becoming almost ubiquitous and with the types of enriched features and services that are available to consumers, mobile devices are being required to support higher data rates [1-4]. This has led to the independent development of several spectrally efficient communication standards (e.g., LTE and WiMAX) which is increasing the number of frequency bands and the amount of spectrum fragmentation [5] and is leading to an environment wherein systems must communicate over many different, sometimes non- contiguous, frequency bands. Moreover, to ease network migration and allow wide roaming, systems must also support multiple legacy-standards as well, further complicating the problem.
To provide the needed level of support, modern transmitters utilize multiple, parallel
PAs, with each separate PA dedicated to a specific communication standard and/or band within a given standard. This leads to a large, complex, and expensive PA module that will ultimately limit game-changing innovation in future wireless systems. To solve this problem, researchers have recently started to develop reconfigurable PAs capable of covering several frequency bands [4, 6-8]. There are several common approaches to increasing the flexibility of PAs: using a single power cell combined with multiple, parallel matching networks and switches [6]; using tunable matching networks [7]; and using wide-band power amplifiers that simultaneously cover all bands of interest [4, 8].
2
Using a single power cell with multiple matching networks is not much more efficient than using multiple, parallel, power amplifiers. While it is true that the power cell can be quite large, the passive elements in a typical matching network are also large and don’t scale with technology. Another, potentially more serious problem with switchable matching networks is the loss introduced by the switches which directly reduces efficiency. The overall area can be reduced by using a tunable matching network. By using tunable elements, most notably varactors [7], the frequency response of a single matching network can be tuned over a wide range. Unfortunately, using tunable elements in the signal path can result in serious non-linear distortion.
An alternative is to use broadband power amplifiers in order to cover multiple bands simultaneously. One popular method to obtain broadband operation is through the use of a distributed architecture [9]. Distributed PAs, however, suffer from large area and relatively low efficiencies. Another approach is to use a broadband output matching network [8], but these are not compatible with some high-efficiency PA architectures, namely class-F.
In this thesis a fully integrated CMOS class-F PA capable of reconfigurable operation from 700 MHz to 1200 MHz is presented. The bandwidth of a class-F PAs is typically limited by the need to properly terminate the 2nd- and 3rd-harmonics at the output. This has traditionally required high-Q harmonic resonators which have very narrow bandwidths. The proposed system gets around this problem through the use of a novel tunable output matching network capable of providing real-time tuning of the fundamental, 2nd- and 3rd-harmonic terminations, thereby maintaining high efficiency over the entire range of frequencies. This tunability is achieved through the use of integrated transformers and a bank of parallel capacitors. It is important to note that this PA does not support signals with instantaneous
3 bandwidths from 700–1200 MHz, instead it supports narrow-band signals over a wide range of potential operating frequencies.
1.2 Thesis Organization
In Chapter 2, an overview of RF power amplifiers is presented. The different classes of operation are briefly described and discussed. After a good understanding of basic power amplifiers, their operation, and the important performance metrics, we introduce the design methods for reconfigurable power amplifiers suitable for next generation wireless communication systems in Chapter 3 which closes with our proposed harmonic tunable power amplifier theory. Then, in Chapter 4 a full detailed implementation of our circuit is presented and discussed with design procedures.
In Chapter 5, the characterization procedure of the fabricated PA is discussed and the measured results are presented and compared with previously published work. This thesis then closes in Chapter 6 with a summary and future perspectives.
4
CHAPTER 2
RF POWER AMPLIFIER OVERVIEW
An RF power amplifier is an electronic device used to amplify a low radio frequency signal to a relatively large signal. In a more functional definition, an RF power amplifier is a device that allows us to convert DC power into electromagnetic power. How well that conversion takes place is quantified by the drain efficiency. Among other characterization metrics we can notably distinguish output power or power delivered to the load (radiated power at the antenna), gain, input and output return losses and linearity. When used in mobile handsets, these metrics are often evaluated by means of requirement dictated by the
FCC with its past or current 3GPP standards that defines the transmitting and receiving frequencies, spectral regrowth limits, tolerance on adjacent channel power and leakage ratio to just name a few. They are all related to the basic characterization metrics mentioned above.
Linearity is used to classify power amplifiers in two major categories: linear power amplifiers and switch-mode power amplifiers. In this chapter, a review of the different classes of power amplifiers is presented with their pros and cons. Particular attention was given to class-F power amplifier because its usage in our proposed design. There are also some advanced modes PAs that are briefly discussed.
2.1 Linear Power Amplifiers
Linear mode power amplifiers are characterized by their relative conduction angle and efficiency. The conduction angle is defined as the proportion of the RF input signal measured in degrees over which the active device is conducting current. If the device conducts over an
5 entire cycle, it is said to have 360o conduction angle. Based on the conduction angle, set by the bias condition, linear PAs can be subdivided into three classes of operations: Class A, B
VDD
IDC RFC DC Block Impedance L Transformation V Network Resonates @ f0 Ropt=Load Line
M1 RL =50 Ω RFIN
Active Device
Fig. 2.1: Basic power amplifier structure and C. A brief description and characteristics of these classes of operation are discussed in the following Sections. We will use the basic structure of an RF power amplifier shown in
Fig. 2.1 where M1 is the power amplifier active device and RFC is a large inductor used to isolate RF from DC. is the supply voltage. Although not shown in Fig. 2.1, there is a
DC blocking cap at the input as well. An impedance transformation network is required to scale the 50 Ω antenna impedance down to a value based on the output power requirement given by (2.1).
2.1.1 Class A Power Amplifiers
In class A mode of operation, the device is biased at 100% duty cycle with 360o conduction angle. Assuming an ideal active device with zero knee voltage, the resulting drain voltage and current are sinusoidal leading to a maximum output power of
6
where is the load seen by the active device, often a scale down version of the
antenna impedance. Since the device conduct at all time, the DC power will be constant at
The achievable drain efficiency , defined as the ratio between the output power and the
DC power.
At maximum output power, the drain efficiency is
As seen in (2.4), the theoretical maximum is thus only 50% in an ideal class A operation.
This class offers a superior linearity as the active device is always in conduction mode.
2.1.2 Class B Power Amplifiers
Attempts to improve the efficiency of class A PAs have led to the introduction of class B
PAs where the conduction angle is reduced to 180o by biasing the RF transistor at the threshold voltage. This comes with a price tag on linearity because the drain current becomes half sinusoidal as the device only conducts half of the period. The spectrum of an ideal sine wave is a single tone at the fundamental frequency but as discontinuity, such as in half sinusoidal wave case, is introduced, high level of harmonic contain show up in the spectrum
7 and gets amplified as well as the fundamental. This is bad for the PA because nonlinear harmonic distortion are present at the output. The output saturates earlier because the total harmonic and fundamental power is now considered as the total input.
For an ideal class B PA, the maximum theoretical drain efficiency is about 78.5%
[10]. It is important to note that PAs biased with a conduction angle between 360o and 180o are very common and are known as class AB PAs. They exhibit drain efficiencies between
50% and 78.5%.
2.1.3 Class C Power Amplifiers
As common sense dictates, a further reduction in the conduction angle or in the DC power will result in higher drain efficiency. Class C PAs are exactly a byproduct of this idea.
From class B operation, a further reduction in the conduction angle leads to a device operation of less than half a full cycle. To achieve this condition, the active device is biased well below the turn on voltage requiring a large driving signal for linear amplification causing several linear distortion and early compression due to higher total harmonic power at the input. Here, it is important to note that the distortion is related to the input and output spectrum contain and not the linear power gain of the PA. The maximum theoretical drain efficiency can reach 100% but this only happens at zero degree conduction angles where the output will be driven toward zero [10]. In order to maintain output power, the amplitude of the current pulses must approach infinity. So, this class of operation, although very promising in efficiency, is not suitable for practical implementation at our frequency of interest because linearity will be completely loss hence a compromise is needed when considered as a design choice.
8
2.2 Switch Mode Power Amplifiers
In switch mode PAs, the active device is operated as a switch and can be classified in three main categories: class D, E and F. Each class has advantages and drawbacks but they all have superior drain efficiency with poor linearity performance when compared to linear
PAs.
2.2.1 Class D Power Amplifiers
In class D operation, two or more active devices are often used in push-pull configuration to create a square wave drain voltage or current with current only pulled through one device at the time and thus lead to a maximum 100% drain efficiency for an ideal configuration
[10]. This class of PAs is not suitable for microwave RFIC applications due to limited switching speed and device nonlinear output capacitance that need to charge and discharge once every cycle and resulting in severe power loss [10]. The power loss results from the unavoidable moment where both voltage and current coexist. Deep submicron processes with higher transition frequencies are promising but are very costly and at this time only a few researchers have access to it. The ultimate solution is class E PA invented by [11] in 1975.
2.2.2 Class E Power Amplifiers
Proposed by [11], class E PAs solve the mystery around the switching speed of the active device in class D by using the device output capacitance in conjunction with a tuned output network in such a way that the drain voltage and current do not coexist or the overlap is minimized. This condition is guaranteed by holding the drain voltage high when the device is off with an output capacitor from the drain to ground and then release the voltage to zero
9 with a zero slope just before the device comes back on and current starts flowing [11]. The beauty of this class of PA is that is very simple and the device parasitic output capacitor can be embedded into the load network facilitating integration. It can also achieve, in ideal configuration, 100% drain efficiency and is very tolerant to switching speed and component uncertainty [10].
2.2.3 Class-F Power Amplifiers
Up to this point, the theme to improve drain efficiency has been non-overlapping drain voltage and current by using different methods. An ideal class-F power amplifier can achieve
100% drain efficiency in theory by using harmonic resonators in the output matching network to shape the drain voltage and current waveforms. A maximized efficiency is typically achieved when the drain-voltage is a square wave and the drain-current is a half- sine waveform as a designer will often desire [12]. This goal is achieved in implementation by presenting a short-circuit to all even-order harmonics and an open-circuit to all odd-order harmonics. A partial Fourier-series analysis can be used to understand the impact of the harmonics as shown in (2.5) and (2.6) where , and are the drain voltage, current, and the number of harmonics controlled, respectively, with their respective DC component and .
10
12 0.15 N=1 10 N=2 0.1 N=4 8
6
VDD 0.05 I0
4 Drain Current (A) Current Drain Drain Voltage (V) Voltage Drain 2 0 N=1 0 N=3 N=5 -2 -0.05 0 2 4 6 8 0 2 4 6 8 t (rad) t (rad) (a) (b)
Fig. 2.2: Drain voltage (a) and current (b) waveform shaping with different number of harmonic peaking
∑ [ ]
∑ [ ]
A plot of (2.5) and (2.6) is shown in Fig. 2.2 with different values of . Truncating only the fundamental , leads to a sine wave for both drain voltage and current but as the higher order terms are also introduced ( and ), we can see that the drain waveform is shaped to a square wave and the current becomes a clipped sine wave. Additional introduction of higher order terms or harmonics reduces the ripple amplitude in both waveforms as shown in Fig. 2.2 by and where up to the 5th the harmonics of the voltage and 4th harmonic of the current are introduced. Therefore, in practice, only the fundamental, up to the current 2nd-, and voltage 3rd-harmonics components need to be
11 controlled because truncating up to higher-order harmonics increases complexity but only gives marginal improvement in overall efficiency [1, 10].
2.3 Advanced Mode Power Amplifiers
In addition to the classical classes of power amplifiers presented until this point, we also have advanced mode of power amplifiers more geared toward practical implementation, efficiency and linearity. This group of PAs is derived from classical PAs and use different techniques to improve efficiency. For instance, a class J PA is an extension of class-F to broadband design with efficiency of class AB or better [13]. It however requires a complex load at the fundamental frequency in order to correctly shape the voltage waveform [14] and makes it difficult to design.
Most of the switch mode power amplifiers discussed earlier are not the perfect candidate for usage in emerging wireless communication systems unless some type of linearization technique is added. Many feedback linearization techniques are employed to take advantage of switch mode PAs because of their attractive efficiency. Such techniques are power back off, pre-distortion, adaptive pre-distortion, feed-forward, dynamic biasing or envelop tracking, envelop elimination and restoration, linear amplification with non-linear components, Cartesian feedback and polar feedback [15]. Each of these techniques employs a specific method to enhance linearity without severely degrading efficiency because of linearity-vs-efficiency tradeoff.
In summary, classical switch mode PAs are still attractive although their linearity performance does not allows them currently to be used in linear wireless communication systems with modulated signal such as LTE, WCDMA, 802.11a/b/g/n, to just name a few,
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TABLE 2.1: SUMMARY OF POWER AMPLIFIER CLASSES AND MERITS o * Class Conduction Angle ( ) Drain Efficiency (%) Linearity
A 360 50
B 180 78.5
C 0 100
D - 100
E - 100
F - 100 * Theoretical Maximum
without any kind of linearization technique such as envelope tracking or polar modulation.
This is due to the available advance mode PA operation that can assist switch mode PAs in
linear applications. In Table 2.1 we summarize the different classes of power amplifiers and
their merits. Linear mode PAs have poor theoretical maximum drain efficiency compare to
100 % for switch mode PAs. In terms of linearity, linear PAs are a better choice.
Now that we have revisited the different classes of PAs, we will now focus in the next
chapter on configurability aspect of PAs which is necessary for next generation of wireless
communication networks and systems.
13
CHAPTER 3
DESIGN OF AN OUTPUT MATCHING NETWORK SUITABLE FOR COGNITIVE RADIO APPLICATIONS
The advent of cognitive radio and the constant increasing of features available to the end user drive the need of reconfigurable wireless network and systems. Cognitive radio refers to a smart radio that can observe its environment, change operation parameters if necessary to operate in such environment independent of time and space [16]. This idea involves both software and hardware harmony. At the software level, observation, orientation, planning, action, decision making and a learning process will be involved. At the hardware level however, electrical reconfigurability is necessaries to complement software level instructions in the cognitive cycle described in [16]. To that extent, we will focus on the hardware aspect and specifically the power amplifier reconfigurability in the transmitter.
Our attention is geared toward power amplifiers because of their importance in the entire transmitter chain. The overall performance of the transmitter is determined by the capability of the PA at the end of the chain [17, 18]. Moreover, in today’s front end transmitter module several parallel PAs often crafted in exotic process are found. This is due to the need to support different standards and features. An example of a typical radio found in today’s mobile handset is shown in Fig 3.1. For a multiband-multimode operation, the industry’s current solution is parallel PAs with a switch to select the band of operation. This approach is not very efficient and severe mismatch issues may arise at the antenna interface with the added switch and matching network loss. In one of Fujitsu Semiconductor Wireless Products, as depicted in Fig 3.1, high level of integration is not offered in the state of the art radio making it not cost effective and area efficient. To overcome these issues, and move toward a smart radio, several techniques and approaches have emerged. Two major approaches will be
14
Multimode- Multiband parallel PAs
Fig. 3.1: Mobile handset radio today
presented and evaluated in the following sections before presenting our approach. The first approach is a multiband idea concurrently or with switchable elements. The second popular way to achieve reconfigurability is through the usage of broadband power amplifier that simultaneously covers multiple frequency bands.
15
3.1 Reconfigurability of Power Amplifiers
3.1.1 Multi-Band Approach
In an attempt to cover multiple frequency bands, proponents of multi-band approach rely on the use of tuning elements such as RF MEMS devices, varactors or capacitive banks in the load matching network. One popular way to realize multiband functionality is through the use of one main power cell combined with different matching networks, each tuned to a specific frequency of operation and controlled by switches [6]. Although this approach may save some marginal area, it is not any better than the traditional way of using parallel PAs.
The same issues seen in today’s handset may still exist as a switch is required in the signal path. In large signal operation, the switch will see a large signal across it and the problem of power handling capability of the switch arises.
Significant reduction in area and a boost in system level efficiency can, on the other hand, be achieved by using a single reconfigurable output match and a single power device.
In this approach however, varactors [7], p-i-n diodes [8], RF MEMS [19, 20] devices or tunable components are required for tunability over a wide range of frequencies. The main drawback of this approach is the introduction of severe non-linear distortion [19] in the signal path which is problematic in today’s handsets devices with stringent linearity requirements.
In addition to that, dedicated processes are required for implementation and most of these processes are still in development. We need to find ways to implement reconfigurable PAs in traditional process similar to the majority of the functional blocks in the front end transmitting and receiving chain.
Multiband response can also be concurrent and remove the need of variable or switches in the design and all the issues associated with them [21]. In the context of future radio
16 systems, this will be considered a partial solution because the concurrent frequencies covered are for the majority part two single frequencies at most. The requirement for dynamic reconfigurability is non-existent and multiple PAs are still required to cover all frequency bands of interest. This has led to the use of wideband approach where more frequency bands are supported simultaneously.
3.1.2 Wide-Band Approach
Wide band power amplifier design is very promising because it allows us to design a single power amplifier with a single matching network to operate in a wide range of frequencies. The actual design of broadband matching network is however not a straight forward task. Popular approaches for broadband PAs take advantage of distributed and balanced amplifiers [4]. These distributed PAs [9] suffer however from large area and efficiency degradation due to the requirement to use multiple devices [22].
Higher order Chebyshev low pass network [22] can also be used to synthesize wideband input and output matching networks but this approach is not suitable for integrated circuit design in the low gigahertz range where most consumer wireless devices predominately operate. These matching networks are often implemented using transmission line stubs [1,
23, 24] that can be very high Q in MMIC applications. In integrated circuit design however, component count and low Q inductors considerably degrade insertion loss and efficiency and make distributed element approach not a good candidate for high level of integration and reconfigurability needed for a game changing next generation of wireless communication systems.
17
In wide band output matching network, another issue is the fact that one also has to settle for a suboptimal optimum impedance matching at certain frequencies. PAs do not have the same optimum impedance for saturated output power, peak efficiency and linearity at the same frequency to begin with. Now, by requiring PAs to operate over a large range of frequencies without any form of readjustment of the load impedance can be challenging and leads to poor performance [25]. In literature, we often see approaches such as mode transferring technique [26], load tracking [27] or the distributed approach [9] mentioned earlier. The mode transferring approach utilizes a dual complementary classes notably class-
F and inverse class-F, to achieve wide band operation. Integrated implementation issues arises here as well because the load in [26] was realized using stubs.
A load tracking approach, on the other hand, relies on primitive methods of PA design and adapts them to wideband operation. It mainly consists of finding the optimum impedances at arbitrary selected frequencies within a given band of interest by using load pull simulation. Then, an optimum load trajectory can be drawn on the Smith Chart and using lumped elements, a network can be design to track that optimized load trajectory [27]. In this approach however, a lot of iteration is involved to get a frequency response close to the load trajectory. Also, the number of samples may be very high to accurately model the optimum load across frequency. Moreover, the inherent difference in the sweet spot for efficiency, output power and linearity leads to three or more trajectories and one has to settle for a suboptimum trajectory which may or may not be accurately modeled by the response of an iteratively designed load network.
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3.2 Proposed Wide Band PA with Tunable Harmonics
In typical class-F, as described in the chapter 2, resonators or quarter wavelength transmission lines are used for harmonic peaking at fixed frequencies. At the foundation of the proposed tunable class-F load is a transformer that allow the user to control the frequency at which the load presents a short-circuit at the second harmonic and an open circuit at the third harmonic. The main building block used to accomplish the tunability is a high-order transformer based resonator shown in Fig. 3.2(a).
A simple analysis of the resonator can show that the input impedance of the network is as follow:
⁄ where √ is the mutual inductance between inductors and with coupling coefficient . We begin by assuming that the load impedance is purely capacitive and
⁄ , the input impedance is now:
In the frequency domain, it can be shown that has a pole at DC, and a pair of complex conjugate poles located at:
√
and two real zeroes located at:
√
19
√
where ⁄ √ and ⁄ √ .
We will consider our system as having two distinct zeroes and a pole at , and respectively because the pole at DC is not very importance in RF design and having an imaginary complex conjugate pole in s-domain results in infinite gain or high impedance response at that particular frequency. So, we aim to control the location of the poles and zeros given five parameters, and . Only two out of the three pole/zeros can be
independently controlled because it can be shown that the ratio is constant. In the realm
of class-F PAs, we would like to place the first zero, at the fundamental providing a low impedance path to the load. By setting the complex conjugate poles at the third- harmonic frequency, a high impedance open circuit response can be obtained and the gain is in theory approaching infinity because of its location on the imaginary axis.
In the above analysis, was assumed to be purely capacitive. Now, by adding the
50 (RL) termination impedance in parallel with capacitor , the input impedance becomes
As seen in (3.6), the pole at DC is removed and replaced by a pole while the second pole remains constant. The location of the zeros however cannot be clearly determined due to the complexity of (3.6) numerator. A design insight can be gained from (3.2) because a plot of the two equation leads to a conclusion that the frequency location of the two zero does not change as shown in Fig. 3.2(b). The only variation is an increase to a positive, non-zero of
20
the real part of at the frequency . It can be shown that the scale down value is controlled by and . The network in Fig. 3.2(a) is designed for illustration. The first zero and the pole are set at = 900 MHz and = 2700 MHz respectively. The input impedance is plotted in Fig. 3.2(b) for two cases: is purely capacitive for the first case and for the second case, a parallel 50 resistor is added for the termination impedance. The second zero, , is located at 3450 MHz (well beyond the desired band), and the location of all poles and zeroes stays unchanged in both cases. By adding a 50 resistor, the real part of
increases from 0 to about 5 as shown in Fig. 3.2(b) by the dashed line.
A simple way to set the poles and zeros is to plot them as a function of the variables and as seen in Fig. 3.3 where the contours at three different pairs of and are plotted with . The intersection of the two curves gives us and values that are simple to evaluate. To see where the remaining zero, is located, one can evaluate with the values previously found for and . Doing so, it can be shown there exist a unique
80 C2 With Load Without Load
) 60 L2 40 k
L1
Real Part of ( Zin Real 20
C1 50 Ω
Z Z 0 IN LOAD 0 1 2 3 4 5 Frequency (GHz) (a) (b)
Fig. 3.2: Schematic of (a) the proposed 4th-order resonant tank and (b) the frequency response of ZIN with and without a 50 termination.
21
contour level of that intersects with the intersection of and . The different solutions are marked in Fig. 3.3 by , and respectively for and
fundamentals frequencies. For all cases, we can notice that is located at high frequencies beyond our band of interest.
Now the component choice is given by , and levels. There is however and infinite number of solution for each level but one has to keep in mind that an impedance scaling is also needed and thus introduce a second constraint that will allow us to find the values of , and assuming the value of has previously been set based on manufacturability considerations. A goal of 0.6 and 0.5 values are set for the third and the second harmonic transformers respectively.
In Fig. 3.4, the load network is shown with standard FET. If we assume a target of 27 dBm output, we would need a factor of 17 impedance transformation at the device’s drain with 1.2 V supply. However, it would be very difficult to achieve because the choke inductor
4 2.1 2.7
3.6
4.6 0.9
0.7 3 3.45 4.6
2.1 2.7 3.6
2 f1 f1 (GHz) 3.45 1.2 S3 S2 1 f 0.9 Z 1 S1 0.7 2.68
f 2.1 3.6 P 2,3 f 2.7 Z 2 0 0 1 2 3 4 f2 (GHz)
Fig. 3.3: Resonator poles and zeros contours
22
Fig. 3.4: Proposed load network with single FET active device
alone can be as lossy as the required optimum impedance, , or more. In addition to that, we have losses through the load network that leads to higher and ultimately lower output power. In Chapter 4, we will discuss the topology of the active device that can withstand such process limitation in detail.
23
CHAPTER 4
CIRCUIT IMPLEMENTATION
In this chapter, we will discuss the implementation of our proposed PA. Design consideration of the stacked active device power cell and layout optimization and robustness are clearly presented and discussed. Then, we elaborate on the input and output matching networks before discussing our circuit stability.
4.1 Power Transistor Consideration and Load Pull Simulation
CMOS process technology is not tolerant to high supply due to low breakdown voltage.
With our proposed tunable class-F load matching network, the output power will be very limited if a process allowed supply is used. The impedance transformation ratio will also be too large and costing a lot in term of efficiency and output power. One way to alleviate this
VDD
RFC
Impedance Transformation D4 Network Gate 4 M4 S4,D3 Gate 3 M3 S3,D2 Gate 2 M2 RL =50 Ω S2,D1 Gate 1 M1 S1
Active Device
Fig. 4.1: Stack-FET active device schematic
24
D4 G4 Guard Ring M4 S4,D3 G3
M3
S3,D2 G2
M2 S2,D1 G1 M1
S1 D=Drain S=Source G=Gate Fig. 4.2: Stack-FET active device layout burden is to use a stacked-fet topology for the active device [2]. A schematic is shown in Fig.
4.1. Another way is to use IO devices with thick gate oxide. These devices are however slow, have low transition frequency, and limit performance. In that spirit, core legacy devices are used in a stacked configuration with a higher supply. As shown in Fig. 4.1, we use 4 stacked transistors M1-M4 so that 4X supply voltage can be used to increase output power which is proportional to the square of the supply voltage.
The sizing and layout of M1-M4 is very critical for performance and action have been taken in design phase to minimize the device on resistance and parasitic capacitances. The sizing of the transistors is done iteratively with a load pull simulation. A load pull is a
25 process in which several loads are presented to the device to determine the load impedance that gives optimum performance. Simulation tools such as ADS have this functionality and save time in the design phase. Here, careful layout strategy is vital in system reliability and performance. A possible flaw of the core device is a possible non uniform current through the network especially in the regions where two devices are connected. These regions are label in
Fig. 4.1 as , where is the transistor from ground up, and are their source and drain respectively. For these connection points, a stack of metals with dense vias from the lowest metal to the top most metal in our process are used to minimize resistance through the connection point as seen in Fig. 4.2.
All four devices are identical and have a gate length and width of 120 nm, 2.4 mm respectively with 140 fingers. The number of finger is determined by the peak drain current and is chosen such that the current density through each finger is kept under process maximum tolerance.
4.2 Full PA Module
In Fig. 4.3, a schematic of the proposed fully integrated class-F PA with reconfigurable harmonic termination is shown. The efficient delivery of watts range of saturated output power with ever-shrinking power supply voltages is a fundamental challenge in the design of
CMOS PAs due to the reduction in minimum feature size. In addition to this scale-down in supply voltage comes a decrease in the optimal termination resistance for the PA, which requires a step up in its load current for a given output power. With an optimum termination resistance of 1–5 , typically, it is difficult for CMOS PAs to reach high output power and high efficiencies compared to today’s GaAs and GaN processes, which offer higher
26 breakdown and supply voltages. Significant losses and die area incurs because the impedance transformer is often synthesized using a passive matching network.
As mentioned earlier, the proposed power cell consists of a stack of four transistors in order to prevent this issue. In this structure, the voltage swing at the drain of M4 is divided across all four transistors thereby permitting a 4X increase in the maximum allowed supply voltage [2]. As a result, a higher output power and efficiency is gained due to a 4X greater optimum termination resistance and hence a lower impedance transformation ratio to drive a
50 load [2]. The respective gates of transistors M2 through M4 are biased in such a way that each individual transistor does not to exceed the process maximum voltage rating.
Transistor M1 is biased at the edge of just turning on and also controls the gain through its trans-conductance .The reconfigurable output matching network is composed of two 4th- order resonators as described in Chapter 3. The first resonator, consisting of and , controls the location of the 3rd-harmonic open-circuit termination as well as provides the necessary impedance scaling. The second resonator, consisting of
and , controls the location of the 2nd-harmonic short-circuit termination.
The variable capacitors, and are made using a bank of fixed capacitors and switches.
The transformers were designed and simulated using ADS Momentum and equivalent time domain lumped-element models were then created as seen in Fig. 4.4, for use in PA simulations. It consists of two 9-element model for each winding where is the series inductance of the primary; is the series inductance of the secondary with series resistances
and respectively. The inter-winding capacitance is denoted , the oxide capacitance is and , and refer to the lossy substrate capacitance, resistance and the coupling coefficient between the primary and the secondary respectively.
27
CT3
RFC L2 DC BLOCK k2
L1 Vb3 M4 C2f0 k1 C1 Vb2 M3 RL
L1f0 L2f0 CT2 Vb1 M2
Widband RF M1 IN Input MN Bias
Fig. 4.3: Simplified schematic of the proposed class-F power amplifier with tunable harmonic termination.
Rsub Csub Rsub Csub
Cox Cbr Cox
3 4 L2 Rs2 k L1 Rs1 1 2
Cox Cbr Cox
Csub Rsub Csub Rsub
Fig. 4.4: Time domain lumped-element model for the transformer
28
Fig. 4.5: Third harmonic control transformer layout
Fig. 4.5: Second harmonic control transformer layout
A parallel stack of the top two thick metals with dense vias are used as a single trace in the design of the transformers for higher quality factor and less loss in the load network. It also helps improve the transformation network efficiency. The layouts of the implemented transformers used to control the third and the second harmonics of the drain voltage and currents are shown in Fig. 4.5 and 4.6 respectively. The substrate under the transformers was
29 left undoped. The added benefit for our transformers is the reduction in the induced Eddy currents in the substrate under the transformer. This leads to less loss in the substrate and higher peak quality factor Q [28]. We define Q as the ratio of the imaginary part of the input impedance of an inductor to the real part as seen in (4.1).
In the transformers characterization through the ADS 2.5D Momentum simulator, the Q is evaluated for each winding separately. The mutual inductance is extracted along with the primary and secondary winding inductances needed to calculate the coupling coefficient as seen in Fig. 4.7 and 4.8 respectively for the third and the second harmonic control
15 20 1.5 L Q k 1 1 2 L Q 2 2 L 15 10 m 1
10
5
Quality Factor Quality 0.5 Inductance (nH) Inductance
5 Coupling Coefficient
0 0 0 0 2 4 6 8 10 0 2 4 6 8 10 0 2 4 6 8 10 Frequency (GHz) Frequency (GHz) Frequency (GHz) (a) (b) (c) Fig. 4.7: Momentum extraction of the a) Winding inductances, b) Quality factor and c) Coupling coefficient of the third harmonic control transformer
4 20 1.5 L Q k 1f0 L1f0 1 L Q 2f0 L2f0 15 3 L m 1
2 10
Quality Factor Quality 0.5
Inductance (nH) Inductance 1 5 Coupling Coupling Coefficient
0 0 0 0 2 4 6 8 10 0 2 4 6 8 10 0 2 4 6 8 10 Frequency (GHz) Frequency (GHz) Frequency (GHz) (a) (b) (c) Fig. 4.8: Momentum extraction of the a) Winding inductance, b) Quality factor and c) Coupling coefficient of the second harmonic control transformer
30 transformers.
In our frequency of interest, we can see that the extracted inductances and coupling coefficients are relatively constant. A quality factor of about 8~10 was achieved with a very high self-resonating frequencies where an inductor impedance becomes capacitive and leads to undesired behavior. The third harmonic transformer exhibits a coupling coefficient of about 0.65 compared to a 0.6 desired value. On the other hand the second harmonic control transformer shows a value of about 0.52 for a desired 0.5 coupling coefficient. These coupling coefficient were expected as we initially set them at these level for manufacturability reasons although higher or lower values can be achieved but are very hard to realize. Ultimately, a variation in the coupling coefficient will lead to a different set of solutions as it is the first parameter we set in our design procedure. However, our system is not too sensitive to a small variation of . The desired inductance values for the third harmonic transformer are 4 nH for the primary and 2 nH for the secondary winding and the extracted values are 4.1 nH and 1.9 respectively as shown in Fig. 4.7. On the other hand the second harmonic transformer was designed for equal primary and secondary inductance of 2 nH while the momentum extraction shows about 2.1 nH which is very close to our desired value as seen in Fig. 4.8.
4.3 Input Matching Network
The input matching network consists of a resistive network with wideband response as proposed in [29]. A simplified schematic is shown in Fig. 4.9. The resistor is mainly used for stability. The value of is determined by the series combination of and . The gate
31
capacitor and are finally used to set the inductor value. Design equations can be found in [29].
4.4 Stability
Stability is a very important aspect of circuit design and implementation especially in
RFIC design. It was noticed in the older radio frequency vacuum-tube transmitters that the tubes and their circuits can potentially show a damped or undamped oscillations based on the circuit losses, the feedback coupling , the grid and anode voltage level, and the reactance or tuning of the parasitic circuits [12]. If the input or the output port impedance presents a negative real part, the part may oscillate and thus become unstable [30]. An input or output negative real part of the impedance is analog to input and output reflection coefficients magnitudes, | | and | | respectively greater than unity [30]. We can then define two types of stabilities: unconditional stability and conditional stability.
Unconditional stability occurs when | | and | | independent of the source and load passive impedances while a network can be considered conditional stable when unconditional stability condition is only true for a certain range of source and load passive impedances [30].
Vbias
DC R2 BLOCK Rg M1
L0 C g s WIDEBAND INPUT MN R1 Gate Source M1 Fig. 4.9: Wideband resistive input matching network
32
There are three main independent methods to evaluate stability of a given circuit: the
stability factor test, the stability factor and the phase margin. To determine the stability, one can use any of the three tests.
The stability factor, also known as Rollet’s condition [30] is defined as
| | | | | |
| |
And
| |
Both conditions are necessary and sufficient for unconditional stability [30] but involves two separate condition verification. The test however, only need a single condition for unconditional stability and is defined as
| |
| | | |
In our design, we rely mainly on the test for its simplicity. The concept of stability circle can be used to separate stable and unstable regions of the source or load reflection
8 700 900 6
1200
4
2
0 0 2 4 6 Frequency (GHz) Fig. 4.10: Stability from 700 MHz to 1200 MHz
33 coefficient plane to provide stability requirement insights. A lossy element such as resistor is shown to help with stability [31] by reducing the loop gain and forcing a bandwidth increase because of constant gain bandwidth product condition. Depending on the location of the stability circle, one can use either a series or a shunt resistor or both to stabilize an active device [31]. The size of the resistor depends on the frequency and can be swept until while monitoring the gain as it drops. Stability was evaluated at the entire tuning range of our proposed PA and beyond. A plot of the simulated from 700 MHz to 1200 MHz is shown in
Fig. 4.10 and shows that the stability condition is satisfied.
The proposed PA with real time harmonic termination tuning capability was manufactured in a 0.13 µm CMOS process and occupies a total area of 1.5 mm 1.5 mm including bonding pads. A die photo is shown in Fig. 4.11. Characterization of the fabricated
PA was performed under both small-signal and large-signal conditions and will be discussed in the next Chapter.
1.5 mm
1
.
5 5 mm
Fig. 4.11: Die photograph. Total area, with pads is 1.5 mm 1.5 mm.
34
CHAPTER 5
MEASUREMENT RESULTS
In order to verify the performance of the PA, the die was first packaged in a 20-lead QFN package and mounted to a two metal layers FR4 printed circuit board (PCB). The bottom layer is dedicated to ground plane to reduce ground inductance, a major factor in stability.
All measurements are referred to the package pins with 4.8 V power supply voltage setting.
In this chapter, we will discuss the PA characterization. Our measurement setup, PCB design and performance measurement results under small and large signal operation at 700 MHz,
900 MHz and 1200 MHz are presented and compared to simulation results and finally compared to previously published power amplifiers.
5.1 Test Bench Setup
A measurement bench is built as shown in Fig. 5.1 to evaluate large and small signal performance of our fabricated PA. A more detailed semi block diagram shown in Fig. 5.2 was used in large signal characterization. The E4418B power meter comes with a power sensor that can measure power level from -70 dBm to +20 dBm. Our design power amplifier however will generate power above +20 dBm hence the use of a 20 dB attenuator between the DUT output port and the power sensor port. In this case all measured power will be 20 dB below their actual level and need to be considered in data processing along with any cable loss. As far as small signal test bench is concerned, the Agilent E5071C Network analyzer was use with DC power supplies as shown in Fig. 5.3.
35
Fig. 5.1: Measurement bench setup
GPIB Cables Matlab Instrument Control
E4418B Power
Meter
e
l b
a DC Supplies & Digital Multi-
C
B Meters
I
P G
E4438C VSG
Packaged PA Die 20 dB Attenuator
Evaluation Board Fig. 5.2: Simplified measurement test bench setup for large signal
36
GPIB Cables Matlab Instrument Control
DC Supplies & Digital Multi- Meters
E5071C Network analyzer
Packaged PA Die 10 dB Attenuator
Evaluation Board
Fig. 5.3: Simplified measurement test bench setup for small signal
A 10 dB attenuator, as seen in Fig. 5.3, was used to protect the network analyzer and operate below maximum operation range. It was then de-embedded from our measurement by adding 10 dB to our measured gain or insertion loss (S21) and isolation (S12). The input return loss (S11) does not change but the output return loss (S22) is de-embedded by adding 20 dB because the incident power at the output port is first attenuated by 10 dB and the reflected power measured at the same port coming from the PA output is also attenuated by 10 dB.
5.2 Measurement Procedure
The measurement procedure adopted was very straight forward for both small signal and large signal characterization. In the small signal case, the test was done manually by setting the correct DC voltages in a sequence that guaranties no overvoltage across any device in the power cell. A careful attention was given to any abnormal fluctuation in the drain current.
Turn on and turn off sequence was developed. Once the device is turned on and operational,
37
S-parameter data are saved to a file on the Network Analyzer and later processed in ADS and
Matlab.
Full automation was used in large signal characterization. With Matlab Instrument
Control toolkit, GPIB commands are read and written to each test equipment at their respective assigned or default physical addresses. After a turn on sequence and frequency setting through the switch voltages SW1, SW2 and SW3 as shown in Table 5.1, the input power is sweeps with the VSG at the fundamental frequency of interest. A power measurement function is written and called after the input power is set and the output settles.
This function takes as input the power meter’s virtual device variable name and returns the reading of the power meter. The reading is done by querying the device measurement channel and writes the data to an index of output power vector variable for further processing. Another function is also called at each input power level to measure the RMS drain current and voltage for drain efficiency and PAE calculations.
TABLE 5.1: OPERATING FREQUENCY SELECTION
Frequency VSW1 VSW2 VSW3 (MHz) (V) (V) (V) 700 1.2 0 0 900 0 0 1.2 1200 0 1.2 0
5.3 Performance Measurement
5.3.1 Small Signal Characteristics
The Agilent E5071C network analyzer was used to measure small-signal S-parameters and results compared with model simulation are shown in Fig. 5.4. The measured S11 is below -10 dB from 400 MHz to 1800 MHz. The relative lower return loss seen with the
38
0
-5
-10
-15
Meas S 11 700 MHz Meas S
-20 11 900 MHz Magnitude (dB) Magnitude Meas S 11 1200 MHz Sim S 11 700 MHz Sim S -25 11 900 MHz Sim S 11 1200 MHz
-30 0 1 2 3 4 5 Frequency (GHz) Fig. 5.4: Measured and simulated small signal input return loss S11 from 700 MHz to 1200 MHz simulated results can be attributed to the bond wires and PCB trace loss along with on chip resistors tolerance. The real-time harmonic tuning is well portrayed, however, by the measured S21 compared with simulation as seen in Fig. 5.5. The PA dynamic configurations were 700 MHz, 900 MHz, and 1200 MHz. As clearly depicted in Fig. 5.5(a-c) the 2nd - and
3rd -harmonic notches move across frequency to support the various fundamental frequencies in the fixed pass band. While the positions of the notches are in good agreement with the frequency position for the harmonics of the 700 MHz and 900 MHz fundamentals, when the
PA was tuned to operate at 1200 MHz, the 3rd-harmonic notch was shifted inward toward lower frequencies due to parasitic unaccounted for and impacted large signal performance.
39
Meas S Meas S 21 700 MHz 20 21 900 MHz Sim S Sim S 20 21 700 MHz 21 900 MHz 10 10 0
0 -10 Magnitude (dB) Magnitude Magnitude (dB) Magnitude -20 -10 -30
-20 0 0.5 1 1.5 2 2.5 0 1 2 3 4 Frequency (GHz) Frequency (GHz) a) b)
Meas S 20 21 1200 MHz Sim S 21 1200 MHz 10
0
-10
Magnitude (dB) Magnitude -20
-30
0 1 2 3 4 5 Frequency (GHz) c) Fig. 5.5: Measured and simulated small signal performance S21 (a) 700 MHz (b) 900 MHz (c) 1200 MHz
40
5.3.2 Large Signal Characteristics
The large-signal characterization was performed with the fundamental at 700 MHz, 900
MHz, and 1200 MHz, respectively using an Agilent E4438C vector signal generator to generate a CW driving waveform and an Agilent E4418B power meter at the output for power measurements. In this case as well, all test equipment was de-embedded from the results and all measurements are thus taken with respect to the package pins. The measured and simulated power added efficiency (PAE) with PA configuration of 700 MHz, 900 MHz,
20 50 20 50
12 32 12 32
Meas Gain
700 MHz Meas Gain PAE PAE (%)
900 MHz PAE (%) Gain (dB) Gain Sim Gain (dB) Gain 700 MHz Sim Gain 900 MHz 4 Meas PAE 14 4 14 700 MHz Meas PAE 900 MHz Sim PAE 700 MHz Sim PAE 900 MHz
-4 -4 -4 -4 -5 0 5 10 15 20 25 30 -5 0 5 10 15 20 25 30 Pout (dBm) Pout (dBm) (a) (b) 20 50
12 32 Meas Gain 1200 MHz Sim Gain 1200 MHz Meas PAE 1200 MHz Sim PAE
1200 MHz
PAE PAE (%) Gain (dB) Gain 4 14
-4 -4 -5 0 5 10 15 20 25 30 Pout (dBm)
(c)
Fig. 5.6: Simulated and measured large signal performance: Gain and PAE for the PA configured to operate at (a) 700 MHz, (b) 900 MHz, and (c) 1200 MHz.
41 and 1200 MHz is 48.3%, 43.1%, and 30% respectively, as seen in Fig. 5.6(a-c). The relative drop in PAE in the 1200 MHz mode is attributed to the shift in the location of the 3rd- harmonic termination noted above with the earlier compression of its gain curve. The measured power gain is shown in Fig. 5.6(a-c) to be approximately 14 dB to 16.5 dB and is overall constant up to the relative compression point for each mode. The measured maximum saturated output power as seen in Fig. 5.7 is between 20 dBm and 24.6 dBm and is in good agreement with simulations for the most part.
30
20
10
Meas Pout
700 MHz Pout (dBm) Pout Meas Pout 900 MHz Meas Pout 0 1200 MHz Sim Pout 700 MHz Sim Pout 900 MHz Sim Pout 1200 MHz -10 -20 -10 0 10 20
Pin (dBm)
Fig. 5.7: Simulated and measured large signal performance: Pout for the PA configured to operate at 700 MHz, 900 MHz, and 1200 MHz.
42
In Table 5.2, the measured results are summarized and compared with previously published works. It is seen that the proposed PA has the highest PAE and is among the highest saturated output powers of all fully integrated CMOS power amplifier design. The relative high output power achieved in [2] can be attributed to the use of off chip matching network components that provide higher Q especially for transmission lines compared to low
Q on chip inductors. In integrated design however, the matching network loss is excessive and hurts efficiency directly.
TABLE 5.2: SUMMARY OF POWER AMPLIFIER PERFORMANCE COMPARED TO PREVIOUSLY PUBLISHED DESIGNS Freq Mod. Max Peak Max Psat Ref. Tech. (GHz) Scheme VDD PAE Gain Note (dBm) (V) (%) (dB) 0.13µm OMN with off [2] 1.9 WCDMA 6.5 29.4 41.4 14.6 SOI CMOS chip stubs 0.18µm 64 QAM transformers on [3] 1-5 5.0 20-22 18-36 18-20 CMOS 54 Mb/s chip 90 nm [4] 5.2-13 CW 2.8 25.2 21.6 18.5 Fully integrated CMOS 0.13µm [32] 0.6-2.8 CW 1.5 21 16* 20 Fully integrated CMOS 0.18µm [33] 5.0 CW 2.0 15.4 40.6 - Fully integrated CMOS 0.13µm 64 QAM [34] 2.4 3.3 19.5 24.8 21 Fully integrated CMOS 54 Mb/s 65 nm 12.5* [35] 1.8 CW 3.3 18.0 21.3 Fully integrated CMOS * 0.18µm [36] 1.95 CW 3.4 26.0 46.4 26 Fully integrated CMOS 90 nm [37] 1.9 CW 2.5 24.0 12 - Fully integrated CMOS 0.18µm Two Chip with [38] 1.95 WCDMA 3.3 26.0 20 19.9 CMOS LINC*** This 0.13µm 14- 0.7-1.2 CW 4.8 20-24.6 30-48.3 Fully integrated work CMOS 16.5
* Drain Efficiency **Graph Estimation *** Linear amplification using nonlinear components
43
5.3.3 Performance at 1200 MHz
As discussed above, our measurement for both small and large signal are slightly deviated from our simulation results mainly at 1200 MHz. We then, investigated our design for possible or probable causes and address them.
First off all, looking at the shift in measured small signal response, we can speculate that more capacitance or inductance is present in the secondary windings at that frequency. With this hypothesis, we revisited our simulation test bench and make changes to the transformer time domain model for a better simulation and measurement correlation. Good agreement was thus achieved by adjusting the secondary winding inductance and its series loss. The impact is severe at 1200 MHz compare to 700 MH and 900 MHz because the second and third harmonics are at even higher frequencies and a small change in inductance will result in large change in the respective winding resonance frequency. This frequency, which sets the location of the second and third harmonic terminations is therefore affected differently across
20 50 Meas S 20 21 1200 MHz New Sim S 21 1200 MHz 10 12 32 0 Meas Gain 1200 MHz Sim Gain 1200 MHz Meas PAE -10
1200 MHz PAE PAE (%)
Gain (dB) Gain Sim PAE 1200 MHz 4 14 Magnitude (dB) Magnitude -20
-30
-4 -4 -5 0 5 10 15 20 25 30 0 1 2 3 4 5 Pout (dBm) Frequency (GHz)
Fig. 5.8: Simulated and measured large signal performance (left) and small signal (right) at 1200 MHz after transformer correction.
44
20 50 Meas S 20 21 900 MHz New Sim S 21 900 MHz 10
12 32 Meas Gain 0 900 MHz Sim Gain 900 MHz Meas PAE 900 MHz -10 Sim PAE
900 MHz
PAE PAE (%) Gain (dB) Gain
4 14 (dB) Magnitude -20
-30
-4 -4 -5 0 5 10 15 20 25 30 0 1 2 3 4 Pout (dBm) Frequency (GHz)
Fig. 5.9: Simulated and measured large signal performance (left) and small signal (right) at 900 MHz after transformer correction.
20 50 Meas S 21 700 MHz New Sim S 20 21 700 MHz
12 32 10 Meas Gain 700 MHz Sim Gain 700 MHz Meas PAE 700 MHz 0 Sim PAE
700 MHz
PAE PAE (%) Gain (dB) Gain
4 14 Magnitude (dB) Magnitude -10
-4 -4 -20 -5 0 5 10 15 20 25 30 0 0.5 1 1.5 2 2.5 Pout (dBm) Frequency (GHz)
Fig. 5.10: Simulated and measured large signal performance (left) and small signal (right) at 700 MHz after transformer correction.
frequency. Clearly, by fixing this issue at high frequencies, some notable impact will be seen at lower frequencies as well but with lesser degree.
Another discrepancy in our large signal measured results compared to simulations as shown in Fig. 5.6, is a slight deviation in the peak PAE and the saturated output power across all three frequencies. Our hypothesis is that the temperature and loss in the choke play an
45
0
-5
-10
-15
Meas S -20 11 700 MHz Magnitude (dB) Magnitude Meas S 11 900 MHz Meas S 11 1200 MHz Sim S -25 11 700 MHz Sim S 11 900 MHz Sim S 11 1200 MHz -30 0 1 2 3 4 5 Frequency (GHz)
Fig. 5.11: Simulated and measured input return loss at 700 MHz, 900 MHz and 1200 MHz after transformer correction. important role in that mismatch behavior. In fact, as the temperature goes high, as our investigations have suggested, the power gain and the saturated output power drops. This theory was then verified in simulation and results are shown in Fig. 5.8 and 5.9 and 5.10 respectively for 1200 MHz, 900 MHz and 700 MHz with simulation temperature of 300o C.
There is now a better correlation between our measurements and simulation results. The measured input return loss compared to our new simulation results is also improved as shown in Fig. 5.11.
To address these issues, a better model of the transformer is needed. It should account for transmission lines and parasitic inductances that we not extracted by our layout extraction of the full PA. Our tool is only capable of extracting resistors and capacitors reason why an EM tool was used for the design of the transformers. As far as temperature is concerned, heat sink usage is a possible solution. It can to keep temperature low or minimize its fluctuation with
46 output power level in conjunction with pulse measurement to allow the PA to cool off between measurements.
47
CHAPTER 6
CONCLUSION
6.1 Summary
A novel magnetic tunable 700–1200 MHz class-F PA with real time reconfigurable harmonic termination capability is proposed and fabricated in standard 0.13 µm CMOS process technology. A stack-FET approach is used for the core device in order to solve the low breakdown voltage issue in CMOS PA design. It allows us to use higher supply voltage than process limits. The fabricated PA exhibits a maximum of 48.3%, 43.1%, and 30% in
PAE respectively for 700 MHz, 900 MHz, and 1200 MHz settings with a saturated output power of 24.8 dBm. We have demonstrated that the proposed harmonic reconfigurable output matching network provides a means for achieving high output power and efficiency over a wide range of potential operating frequency vital for the next generation cognitive wireless communication systems.
6.2 Perspectives
Our design was mainly applicable to constant envelop signal and linearity was not an integral part of performances measured. In future work, we will investigate the application of modulated signal with high peak to average power ratio. Linearization techniques such envelop elimination and restoration can be added to improve efficiency further. It will require an excellent DC-DC converter [15] that will need a lot of attention in terms of bandwidth that can limit the PA frequency of operation.
We can further extend the operation range of the proposed PA to high frequency bands and cover the entire handset communication frequency bands both existing and upcoming
48 standards. Higher Q and coupling coefficient inductor design are needed to achieve this versatility. Along with this versatility, a two stage approach can be used while investigating the challenges of the inter-stage matching requirements for a tunable power amplifier.
49
APPENDIX
MEASUREMENT MATLAB SCRIPTS
The following scripts have been used to take large signal measurements data presented in this work. The three major scripts are as follow:
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%% PIN SWEEP SCRIPT %%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % % % For this script to work, three functions are required: % % Measure_Power.m and Measure_DC_RF.m, Measure_result % % % % This Script is used to generate power from the Agilent E4438C % % Vector Signal Generator, measure output power from the Agilent % % E4418B power meter and write data to a csv file % % % % % % % % By Kossi Sessou % % December 7, 2013 % % % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% clear all filename='../Desired_filename.csv'; fid=fopen(filename,'w'); fprintf(fid,'%s,%s, %s, %s, %s, %s, %s\n %s, %s, %s, %s, %s, %s, %s\n',... 'Freq','Pin', 'VDC_a', 'VDC_VDD', 'IAC_a','IDC_a','Pout_Cpl','MHz',... 'dBm','V', 'V', 'A','A','dBm'); fclose(fid); for f=[700 900 1200] % Frequency vector
Data=Measure_result(f,-28,1,20); % Measurement function dlmwrite(filename,Data,'-append'); % Append result to a csv file end %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%% PIN SWEEP FUNCTION %%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % % % For this script to work, two functions are required: % % Measure_Power.m and Measure_DC_RF.m % % % % % % This Script is used to generate power from the Agilent E4438C % % Signal Generator and measure output power from the Agilent % % E4418B power meter % % The DC bias and current measurements are done with HP E3631A % % % % % % * % % * % % * By Kossi Sessou % % * * November 10, 2013 % % * * % % * % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% function result= Measure_result(Freq,start,step,stop)
% Define measurement devices GPIB addresses a=gpib('ni',0,8); % HP Digital Multimeter 34401A g=gpib('ni',0,13); % Agilent Power Meter E4418B v=gpib('ni',0,7); % Agilent Signal generator E4428C d=gpib('ni',0,3); % HP Power Supply E3631A % ** NEED TO CHANGE ADDRESS BASED ON VDD CONNECTON ** e=gpib('ni',0,26); % HP DMM 34401A
% Initialize variables n=1; Pin=-40; Frequency=Freq;
% Set the devices for read and write a.EOIMode = 'on'; set(a,'EOSMode','read&write'); set(a,'EOSCharCode','LF'); a.OutputBufferSize = 3000; a.InputBufferSize = 3000; a.Timeout = 120; d.EOIMode = 'on'; set(d,'EOSMode','read&write'); set(d,'EOSCharCode','LF'); d.OutputBufferSize = 3000; d.InputBufferSize = 3000; d.Timeout = 120; g.EOIMode = 'on'; set(g,'EOSMode','read&write'); set(g,'EOSCharCode','LF'); g.OutputBufferSize = 3000;
51 g.InputBufferSize = 3000; g.Timeout = 120; set(v,'EOSMode','read&write'); set(v,'EOSCharCode','LF'); v.OutputBufferSize = 3000; v.InputBufferSize = 3000; v.Timeout = 120; set(e,'EOSMode','read&write'); set(e,'EOSCharCode','LF'); e.OutputBufferSize = 3000; e.InputBufferSize = 3000; e.Timeout = 120;
% Open the devices fopen(a) fopen(d) fopen(g) fopen(v) fopen(e)
% Set measurement frequency freq_str_w_unit=strcat(num2str(Frequency),'MHZ'); % to string freq_str=num2str(Frequency); % to string fprintf(g,strcat(['FREQuency ',freq_str_w_unit])) % Power Meter freq fprintf(v,strcat(['FREQ ' freq_str ' MHz'])); % VSG Sig. Gen. freq pause(3)
fprintf(v,'OUTP:STAT ON'); % Turn RF ON %%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% BIGIN OF SWEEP %%%%%%%%%%%%%%%%%%%%%%%%%%% for Pin=start:step:stop % Sweep range %% fprintf(v,strcat(['POW:AMPL ',num2str(Pin),'dBm'])); % Set Pin level pause(1)
temp1=Measure_Power(g); % Meas. output power temp2=Measure_DC_RF(v,a,e); % Measure DC and Pin %% result(n,:)=[Freq temp2 temp1]; % Write to a row clear temp clear temp1 clear temp2 clrdevice(g) n=n+1; % Increment n end
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% END OF SWEEP %%%%%%%%%%%%%%%%%%%%%%%%%% fprintf(v,'POW:AMPL -40 dBm'); % Amplitude to -40 fprintf(v,'OUTP:STAT OFF'); % Turn RF OFF
% Close delete and clear all virtual devices
52 fclose(a) fclose(d) fclose(g) fclose(v) fclose(e) delete(a) delete(d) delete(v) delete(g) delete(e) clear a clear d clear g clear h clear d end
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%% End of Measure_result function %%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%% Power Measurement Function %%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% function pout= Measure_Power(g) pout=0; fprintf(g,'CONF1'); fprintf(g,'READ1?'); % read from power meter upper screen data=fscanf(g); % Write power meter data temp=str2num(data); % Convert power meter data to a number pout=temp; % Write result to output variable pout clear data end
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%% End of Power Measurement Function %%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%% Measure_DC_RF function %%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% function DC_RF =Measure_DC_RF(v,a,e) %% fprintf(v,'POW:AMPL?'); % Query the amplitude temp=fscanf(v); % Get amplitude reading Pin=str2num(temp); % Write Input amplitude to a vector %Pmeas=Measure_Power(g); % Measure output power possibly
%%
%% fprintf(e,'MEASure:VOLTage:DC?') % Query Voltage at P25V output temp=fscanf(e); % Get voltage reading V_DC_e=str2num(temp); % Write voltage to a vector
fprintf(a,'MEASure:VOLTage:DC?') % Query Voltage at DMM output 34401A temp=fscanf(a); % Get voltage reading V_DC_a=str2num(temp); % Write voltage to a vector
%% %%%%%%%%%%%%%%%%%%%%%%%% AVERAGING CURRENTS %%%%%%%%%%%%%%%%%%%%% %% I_DC_d=0; I_DC_a=0; I_AC_a=0;
% DC Current Measurment for m=1:5 fprintf(a,'MEASure:CURRent:DC?') % DC Current at DMM output 34401A temp=fscanf(a); % Get current reading I_DC_a=I_DC_a + str2num(temp); % Write current to a vector end I_DC_a=I_DC_a/m; % Current average @ DMM output 34401A
% AC Current Measurment for m=1:5 fprintf(a,'MEASure:CURRent:AC?') % AC Current at DMM output 34401A temp=fscanf(a); % Get current reading I_AC_a=I_AC_a + str2num(temp); % Write current to a vector end I_AC_a=I_AC_a/m; % Current average @ DMM output 34401A
%%%%%%%%%%%%%%%%%%%% AVERAGING CURRENTS END %%%%%%%%%%%%%% DC_RF=[Pin,V_DC_a,V_DC_e,I_AC_a I_DC_a]; end %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%% End of Measure_DC_RF function %%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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