Lecture 6: Thin-Film-Transistors (Tfts)

OSEOSE--6820:6820: FlatFlat PanelPanel DisplaysDisplays

Lecture 6: Thin-film-transistors (TFTs)

Dr. Zhibing Ge College of Optics and Photonics University of Central Florida

College of Optics & Photonics Photonics & Display Group UCF CREOL & FPCE 1 OutlineOutline

1.Background 2.MOSFET characteristics 3.TFT driving schemes 4.Power consumption

2 LiquidLiquid ÎÎ CrystalsCrystals

• Solid → Anisotropic Liquid→ Isotropic • As T increases, order parameter decreases. Crystal: S=1; LC: S~0.6-0.8, Isotropic: S=0.

T Crystal Nematic LC Isotropic 3 LiquidLiquid CrystalCrystal MoleculesMolecules

F F H C CN 2n+1 n 2.4Å C5H11 C3H7 2.4Å 15.9Å 18.8Å

5CB Terphenyl

From: Dr. S. Gauza 4 LCLC MovementMovement UnderUnder FieldField

++ E +++ ε// positive

--- -- ε⊥ Δε = ε// −ε⊥ > 0 E negative - + E - + - + all angles in - + the plane ⊥ to E are possible for the Δε = ε// −ε⊥ <0 -Δε materials 5 InducedInduced DipoleDipole

Note: This does NOT stand for a single LC molecule.

6 DifferentDifferent DrivingDriving ApproachesApproaches

1. Direct Addressing 2. Passive Addressing 3. Active Addressing

Direct driving PM driving AM driving 7 DirectDirect DriveDrive AddressingAddressing

• Thresholdless nature of material is irrelevant • Every pixel is independently addressed • For lower resolutions only <50 pixels inch

8 PassivePassive MultiplexingMultiplexing

time pixel voltage Frame 1 (row-column) S+D +S T +S +D +D // // +S +S S-D +D // // +S S+D +S +S +D +D

Row Signals // // +S Δ t S-D +D +D

// // 1 2 3 . . . N -D

+D +D +D

-D -D -D

Column Signals NW Display!! 9 ExampleExample

Image to display:

Signal sequence:

Vs 0 0 0

0 Vs 0 0

0 0 Vs 0

0 0 0 Vs

-Vd-Vd-Vd-Vd -Vd-Vd-Vd-Vd +Vd -Vd -Vd +Vd +Vd -Vd -Vd +Vd

10 Driving Scheme

1 N −1 V 2 = (S + D)2 + (D)2 on N N 1 N −1 V 2 = (S − D)2 + (D)2 off N N

Von ≥ Vth + Δ

Voff ≤ Vth V N ≤ ( th )2 max Δ

Alt and Pleshko, IEEE Trans. Electronic Devices ED-21,146-155 (1974) 11 Active Matrix Addressing

www.eetkorea.com 12 Schematic of AMLCD

13 Present LCD System

LCD Panel

LCD-TV System Board Timing controller Tuner

Source drivers . Gate drivers

Video processor By Prof. JL Lin at NCKU

14 AMAM DrivingDriving SchemeScheme

TFT (switch) + LC cell (capacity) Hydrant (switch)+ Bucket (capacity)

Each pixel could be controlled independently!

15 StorageStorage CapacitorCapacitor

Leakage Current: • LC is not a perfect capacitor, it has certain resistivity • Add a storage capacitor to hold voltage

Scan line Storage capacitor LC capacitor

Data line Data Storage LC capacitor

Performance of the TFT is critical!

16 MOSFETMOSFET

MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor )

(a) Circuit symbol for the n-channel enhancement type MOSFET

(b) Simplified circuit symbol for the n-channel enhancement type MOSFET

G：Gate 、B：Body 、D：Drain 、S：Source

D D

B G G S S (a) (b) (c) 17 TFTTFT andand MOSFETMOSFET

TFT MOSFET

Amorphous Silicon Silicon

Architecture Architecture

18 FabricationFabrication ProcessProcess ofof aa--SiSi TFTTFT

http://www.freescience.org/philip/research/images/Image1.gif 19 CrossCross--sectionalsectional ViewView ofof aa PixelPixel

20 SwitchSwitch--on/offon/off StatesStates

Switch-on

Switch-off

21 ElectronElectron MobilityMobility

TFT

MOSFET LTPS a-Si

22 ApplicationsApplications ofof aa--SiSi andand polypoly--SiSi

Poly-Si technology trend:

23 WorkingWorking StatesStates ofof MOSFETMOSFET

(a) Linear region

(b) Edge of saturation

-4 10 1.5x10-5 10-5 Ion -6 V =10V -5 V =20V 10 D 1.2x10 G 10-7 Linear -6 -8 region 10 9.0x10 16V (A) -9 Subthrehold (A) D 10 D -6 I I -1 Saturation -10 swing=(slope) 6.0x10 10 region 12V -11 10 3.0x10-6 10-12 8V Ioff 4V 10-13 0.0 -10-50 5 10152025 0 5 10 15 20 VD(V) VG(V)

2.0x10-7

1.5x10-7 @small value of VD

-7 (A) 1.0x10 D

I VD=0.1V 5.0x10-8 VT 0.0 -5 0 5 10 15 VG(V) 25 LinearLinear RegionRegion

Boundary condition:

26 LinearLinear RegionRegion ModelingModeling

Boundary condition:

The charge in the inversion layer:

Q = −C ⋅[V −V (y) −V ] GS c T 0 μ ∂Vc ( y) I DS = C ox (VGS − V c ( y) − VT 0 ) × W × × I DS = Q×v×W ∂y

∂Vc (y) I dy C (V V ( y) V ) W dV ( y) v = μE where E = DS = ox GS − c − T 0 × × μ × c ∂y

Channel current: 1 W I = (μC)( )[2(V −V )V −V 2 ], 0 ≤ V ≤ V −V DS 2 L GS T DS DS DS GS T 27 II--VV CharacteristicsCharacteristics inin LinearLinear RegionRegion

Triode region VDS < VDS(Sat)= VGS-VT

A larger VDS value A small VDS value

In TFT LCD: VG >10 V, so VDS < VGS-VT 28 SaturationSaturation RegionRegion

1 W 2 Replacing V by V -V in I = (μC)( )[2(V −V )V −V ], DS GS T DS 2 L GS T DS DS

Saturation current:

1 W I = (μC)( )(V −V )2 , V > V −V DS 2 L GS T DS GS T

29 II--VV CharacteristicsCharacteristics inin SaturationSaturation RegionRegion

Saturation region

V > V (Sat) VDS = VDS(Sat)= VGS-VT (VGD =VT ) DS DS

30 LargeLarge SignalSignal BehaviorBehavior

Triode region (VDS < VDS(Sat))

VDS(Sat) = VGS –VT

2 iD = Kn[2(VGS −VT )VDS −VDS ]

Saturation region (VDS >VDS(Sat) ) 2 iD = K n ()V GS − VT

∂vDS r (rds ) = | = ∞ o VGS =const ∂iD ro：small signal output resistance μW nC ox K ：Conduction parameter K = n n 2L Cox：the oxide capacitance per unit area 、ε ： ε ox tox ox the oxide thickness and C = permittivity ox tox

31 Cont.Cont.

2 z For small values of VDS , VDS is small and so near the origin, we can approximate the transistor as a linear resistor

2 iD = Kn[2()VGS −VT VDS −VDS ]

When VDS is small () iD = Kn[2 VGS −VT VDS ]

∂vDS −1 ro (rds) = = [2Kn ()VGS −VT ] ∂iD

So, ro will be affected by Kn ,VGS, and VT

32 ExampleExample

Scan line l=6(μm) w=8.8(μm) Vscan = -10 ~ 12(V) Vt= 0(V) scan-on time = 17(μs) A 2 μn Cox=1.16e-004 (A/V )

CST CLC Data line WμnCox −1 r (rds) =[ ()V −V ] = 686.81(Ω) o L GS T

33 ChargingCharging TimeTime

Taking a XGA (1024×RGB×768 Dot) panel size for example (operated in 60Hz), then the framing time for each row is: 1 1 × ≅ 21.7μs 60 768 VGH 1 VGL t For SXGA (1280×RGB×1024), the time is: 2 1 1 × ≅ 16.28μs 21.7μs … 60 1024 768 In the panel pixel circuit, the design must satisfy the following equation: 1

Ichargedtcharge > CchargedVcharge 2 designer 16.28μs … dtcharge: charging time 1024 C : pixel capacitor charge 16.6ms dVcharge: (the maximum gray level voltage)

34 InversionInversion SchemeScheme

Dot inversion has the best optical performance.

35 PolarityPolarity InversionInversion

Common Electrode has fixed potential. Common Electrode has Interchanging potentials. + - + - V common V0 V0 V1 V1 V0 V0 V0 V0 …. + …. V1 V1 V1 V1 V254 V254 Gray Levels Gray V2 V2 V2 Frame NV255 Frame N+2 V255 V2 V3 V3 V3 V3 …. …. …. V255 V255 …. Frame N+1 Frame N+3 V254 V254 V252 V252 V252 V252 …. …. V253 V253 V253 V253 Gray Levels V1 V1 V common - V254 V254 V254 V254 V0 V0 V255 V255 V255 V255

Frame NFrame N+1 Frame N+2 Frame N+3

Requires a high source voltage Less source voltage output (half of the output from TFT. left one). Suitable for all frame, row, column, Limited to row and frame inversions. and dot inversions.

Polarity inversion is to reduce the ion trapping.

36 DetailedDetailed ChargingCharging ModelModel ofof aa PixelPixel

CGD Feedthrough voltage: ΔVP = • ΔVG CST + CLC + CGD 37 CorrectionCorrection ofof FeedthroughFeedthrough VoltageVoltage

Gate V Feedthrough V resulting from Gate V change Source V

Com. V

Correction V Com. V of after Com. electrode correction

V on LC + Polarity - Polarity

38 PowerPower IssueIssue

The charge stored in capacitor is proportional to supplied voltage, that is q = Cv . When VC(0) = 0, the Q-V curve is:

t t dv Wt()== vidt VC⎛ ⎞ dt The energy stored in capacitor : c ∫∫−∞ −∞ ⎝ dt⎠

t t 1 2 = C vdv= Cv() t ∫−∞ 2 −∞

1 2 Wt()= Cv() t v(−∞) = 0 c 2

+ Q

+q + v v − −q

0 − V

39 DerivationDerivation ofof P=P=NN(1/2)fCV(1/2)fCV2

next frame VVV VGH … VGL n columns 1/mf (s) C C C

C C C …

1/f (s) V: data voltage m rows C: capacitor in the pixel

Assume C and V are equal for every pixel. 40