By Remy David, Director of Marketing and Technology, GESPAC S.A. VME & COMPACTPCI
WhyWhy CompactPCICompactPCI willwill replacereplace VMEVME
In just a year, the CompactPCI bus has risen to prominence in the board industry worldwide, prompting users to compare it with VME and to wonder if it could replace VME in many applications. There are two ways to compare buses. The first is to look at the intricate details of the bus signals, bus transceiv- er technology and timing diagrams. From this point of view, VME (and VME64x) fares as an outstanding technology with plenty of growth potential. The other way is to see what silicon components, system and software facilities a given architecture offers to simplify system design. From this perspective, PCI and CompactPCI offers unique possibilities thanks mostly to the broad silicon support and "system-ori- ented" concepts like Plug and Play. While the installed base of applications and customers ensures VME many more years of existence, these powerful force are already at work to make CompactPCI the dominant industrial OEM bus at the end of the decade.
istorically, new industrial bus standards typical- model of a typical system. The Physical layer (1) ly have originated from a number of sources. defines the board format and the connector type and H As semiconductor companies introduced new positions. The Electrical layer (2) defines the transceiv- microprocessors, they also built a series of er technology, pin assignment, clock speeds, etc. … By Remy David, Director of Marketing and Technology, board and system products designed mainly to sim- The Protocol layer (3) describes how elementary trans- GESPAC S.A. plify the use and speedVME the acceptance& COMPACTPCI of their chips. fers, arbitration and responses to interrupts are made. These buses often were a direct extension of the Layer 4 deals with the way boards are mapped in the microprocessor local bus onto a backplane. This is address space and how they are detected and con- how Multibus and Versabus - which eventually evolved figured. This and the following layers are no longer into Versa Modules Europe (VME) - came to be. specific to the bus but deal with system design issues. WhyWhy CompactPCICompactPCI willwillAnother replacereplace source for buses isVMEVME the computer industry. For example, layer (5) provides recommended archi- When IBM introduced the PC in 1981, it needed a tecture models for selecting and interconnecting In just a year, the CompactPCI bus has risen to prominence schemein the board for industryallowing worldwide,add-on functions prompting to be easily peripherals in a manner that ensure compliance with users to compare it with VME and to wonder if it could replaceadded VME and in many removed. applications. The PC/ISA There bus are was not an end a Reference Platform Standard. The Hardware two ways to compare buses. The first is to look at the intricatein itselfdetails but of merely the bus a neededsignals, featurebus transceiv in an open- system Abstraction Layer (6) is provided to allow different hard- er technology and timing diagrams. From this point of view, design.VME (and VME64x) fares as an outstanding ware implementations while maintaining compatibility technology with plenty of growth potential. The other way is Historyto see whatincludes silicon a number components, of smaller, system innovative com- at the higher layers. BIOS or OpenFirmware software and software facilities a given architecture offers to simplify paniessystem design.who independently From this perspective, defined busPCI architecture. reside on this layer. Next the Operating System layer (7) and CompactPCI offers unique possibilities thanks mostly toFor the example broad silicon GESPAC support defined and "system-ori the G-64 -bus in 1979, rests as the foundation for what the system is ulti- ented" concepts like Plug and Play. While the installed basePro-Log of applications the STD and bus customers in the mid ensures 70's, and more recent- mately intended for: run the user Application software. VME many more years of existence, these powerful force arely alreadyAmpro atdefined work tothe make PC/104 CompactPCI bus. These the buses have Eventually all layers have to be addressed for a system dominant industrial OEM bus at the end of the decade. done well in the market because they were aimed at to work. specific needs and were relatively independent from istorically, new industrial bus standards typical- model anyof givena typical chip system. or computer The Physical maker. layer (1) Difference between computer and ly have originated from a number of sources. definesAn the active, board butformat commercially and the connector less successful type and source of semiconductor maker's buses. H As semiconductor companies introduced new positions.buses The has Electrical been layerinstitutions (2) defines like thethe transceiv- IEEE. Notable ven- Buses developed by chipmakers, like VME, tend to microprocessors, they also built a series of er technology,tures include pin assignment, the STE clock bus speeds, and etc.more … recently board and system products designed mainly to sim- The Protocol layer (3) describes how elementary trans- focus on the elementary functions of the system. In the Futurebus. While none of these buses was ever plify the use and speed the acceptance of their chips. fers, arbitration and responses to interrupts are made. These buses often were a direct extension of the Layer 4endorsed deals with bythe away large boards company are mapped or ingained the market microprocessor local bus onto a backplane. This is addressacceptance, space and theyhow havethey arecontributed detected toand the con- development how Multibus and Versabus - which eventually evolved figured.of This new and technologies the following that layers eventually are no made longer their way in into Versa Modules Europe (VME) - came to be. specificmany to the of bus the but buses deal withthat systemare in usedesign today. issues. Another source for buses is the computer industry. For example,It is fair layerto say, (5) however,provides thatrecommended the most importantarchi- contri- When IBM introduced the PC in 1981, it needed a tecturebution models to thefor bus/boardselecting marketand interconnecting have been done by the scheme for allowing add-on functions to be easily peripheralsComputer in a manner and the that Semiconductor ensure compliance industries. with added and removed. The PC/ISA bus was not an end a Reference Platform Standard. The Hardware in itself but merely a needed feature in an open system Abstraction Layer (6) is provided to allow different hard- design. ware implementationsBOARD LEVEL while maintainingVS. SYSTEM compatibility LEVEL History includes a number of smaller, innovative com- at the BUSEShigher layers. BIOS or OpenFirmware software reside on this layer. Next the Operating System layer (7) panies who independently defined bus architecture. Buses in system hierarchy For example GESPAC defined the G-64 bus in 1979, rests as the foundation for what the system is ulti- Pro-Log the STD bus in the mid 70's, and more recent- matelyBuses intended are for: elaborate run the usertechnologies Application and software. specialists have ly Ampro defined the PC/104 bus. These buses have Eventuallydedicated all layers careers have to beto addressedrefine them. for aThey system can also be done well in the market because they were aimed at to work.emotional subjects; as recent "battle of the buses" specific needs and were relatively independent from have shown. But one must not lose sight of the big pic- any given chip or computer maker. Differenceture. Buses between are essentially computer communication and schemes Figure 1. Layered model of the elements of a An active, but commercially less successful source of semiconductordesigned to build maker's systems. buses. Figure 1 shows a layered typical open system buses has been institutions like the IEEE. Notable ven- Buses developed by chipmakers, like VME, tend to tures include the STE bus and more recently focus on the elementary functions of the system. In the Futurebus. While none of these buses was ever Copyright 1998 by Real-Time Magazine 98-4 (http://www.realtime-info.be) 31 endorsed by a large company or gained market acceptance, they have contributed to the development of new technologies that eventually made their way in many of the buses that are in use today. It is fair to say, however, that the most important contri- bution to the bus/board market have been done by the Computer and the Semiconductor industries. BOARD LEVEL VS. SYSTEM LEVEL BUSES Buses in system hierarchy Buses are elaborate technologies and specialists have dedicated careers to refine them. They can also be emotional subjects; as recent "battle of the buses" have shown. But one must not lose sight of the big pic- ture. Buses are essentially communication schemes Figure 1. Layered model of the elements of a designed to build systems. Figure 1 shows a layered typical open system
Copyright 1998 by Real-Time Magazine 98-4 (http://www.realtime-info.be) 31 VME systems are gaining (not losing) interest!
! Many companies are defecting from CPCI back to VME ! CPCI hype is being recognized for what it is
Arizona Digital, Inc. 2 Global Merchant Embedded Slot Card Market, 2002 & 2003 US$ in Millions
2002 Total: US$ 2,306 Million 2003 Total: US$ 2,348 Million
$2,500 $203 $227 $2,000 $246 $228
$527 $557 $1,500
$1,000 $536 $609
$500 $794 $727
$0 2002 2003
PICMG 1.0 (SBCs Only) ISA PCI CompactPCI VME By Bus Architecture 2004 (by $ volume)
4% 7% VME 25% CPCI 8% PCI (slot) ISA Other* 15% Stand Alone 16% PMC pc/104 11% 4% 10% SwFbr Current and Forecast Markets
! VME: $1.15 billion – 5% - 10% continued growth
" Strong mil-COTS segment
" Realtime apps in wireline, wireless & 3-G, Industrial Automation
! cPCI: $200 million including OS and firmware
" Soft market – packet switching and “last mile” apps in doubt
" Custom board markets
! PC 104/+: $50 million
" Niche market
" Threat from FPGAs
! ATCA: cure looking for a disease
" Strong possibilities for high bandwidth (e.g., WDM) apps
" 3-G and wireless possibilities
" Solution for a world of connected devices?
" Multi $billions if it takes hold – middle ground not likely ElectronicsMarket forecasters
Boards, Busses, Backplanes and Bandwidth Nagging Questions That Must Be Looking Past the Millenium Addressed
• What Ever Happened to the Great Telecom Revolution? THE BUS WARS • VME vs. cPCI vs. PCI: We know the players - but on whose court and by what rules are we keeping • Proprietary Architectures will continue to dominate score? embedded designs • The High End Board Market will be dominated by VME and the 5-row DIN Connector• Will the Internet and CTI Fulfill Their Promise? • cPCI and the 2mm HM connector will dominate Telecom and the 3U Industrial and Transportation markets cPCI • PCI will inherit the PC Architecture markets and VME challenge cPCI in Telecom • number of legal backplanes under PICMG spec: Asset & Problem • will continue to dominate multiprocessing applications • choice of telecom engineers for software compatibility, • is driven by long-life cycle applications rear-connect phone lines allowing unrestricted card • COTS will be a major driving force insertion and front end card swapping. • Presidential politics will drive military design starts • 6U form factor provides additional pin-outs • higher volume customers will switch to contract • Long lead-time design process by telco engineers can be manufacturing to cPCI’s Advantage. • VME’s incorporation of high-speed serial data flow will • In House or Contract Manufacturing Decisions Could extend its high-end market dominance Hamper Merchant Opportunities • need for hot swap: technical and patent issues Why cPCI? • All present day computers have some sort of PCI bus (including VME SBCs) • Only 47 lines for 32 bit bus • Inexpensive silicon & connectors • IP (Xilinx, opencores.org, etc.) • VME interface chips (e.g. Tundra Tsi148) are bridges to PCI • PMC cards used in VME modules • “Slave” terminated block read !"#$% !"#$%&'$'()*+,-./0$&123*,#-$4/(*5/6,*-#-7+$8-1*3
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!"#$%&&'( A: Yes, since VME64x and CompactPCI use the same Euroboard mechanical packaging, it is possible to combine both architectures into a single chassis. A special VME64x bridge connector pinout has been proposed for VME64x to CPCI bridgeboards. This special connector has all of the VME64x signals on a single 2- mm connector. A bridgeboard would connect to the VME64x bus with the top connector and the CPCI bus with the bottom connector. This implementation would require a special backplane with both VME64x and CompactPCI on the same PCB. The same expert that simulated the design of CompactPCI validated the VME64x 2mm-bridge pinout.
Back to Top
Q: Will CompactPCI system run real -time operati ngHome systems Support well ? FAQ's Back to Top A: The performance of CompactPCI is particularly well tuned to real-time application, from machine control to machine vision and fast data acquisition. Q:-- What Choose other an FAQ speci categoryficati ons-- has the PICMG issued? Operating systems like OS-9, PSOS, VxWorks will run very well on CompactPCI hardware and will be instrumental in the expected success of CompactPCI in these FAQsA: The found first efinf CompactPCIort of the PICMG Technol wasogy to publish a specification for passive backplane markets. computers using both PC style (card edge connector) ISA and PCI bus. This was Howcomplet caned I get in earlya copy 1995. of the The Compact PICMGPCI has Specif alsoicat issuedion? a specification for PCI to PCI Back to Top Wherebridges does that t heallow Compact passivePCI backplane specificat ioncomput comeers from to ?extend the number of PCI slots. Does CompactPCI support all of the "Plug-and-Play" configuration features in the The CompactPCI project is a more recent effort driven by a subcommittee of Q: What products are or soon-to-be available on CompactPCI ? PCI specification? Whatcompanies other specif withinicat theions PI CMG.has the PICMG issued? A: Pentium CompactPCI CPU boards are available in 3U format and 6U format What is the PICMG? Back to Top from three CompactPCI vendors today (January 1996) with more on the way. What is a bridge chip and what type of role does it have with data transfers? System level add-on function such as 100 Mbit/s Ethernet, fast SCSI, accelerated Can I have more than 8 slots in a CompactPCI system? Q: What is the PICMG? VGA and analog and digital I/O are currently available. Other companies have Are there system integration issues when combining CPCI and VME64x on the same backplane? announced plans for PowerPC CPU boards, fast fiber optics networks, image A: The PCI Industrial Computers Manufacturer's Group is a consortium of more Can you combine CompactPCI and VME64x? acquisition and processing, motion controllers, and carrier boards for the popular than 85 industrial computer product vendors. PICMG's charter is to develop PMC and IndustryPack mezzanine board standards. Will CompactPCI system run real-time operating systems well? Whatspecif producticationss arefor PCIor soon-based-to-be syst availableems and on boards Compact forPCI use? in industrial computing applications. Member companies include industry leaders such as IBM, Texas Back to Top How many connectors are used on 6U CPCI plug-in boards? WhichMicrosyst Operatems,ing I ndustSystemsrial canComput Compacter Source,PCI comput DEC,ers GESPAC, run? Pro-Log, Teknor and Q: How many connectors are used on 6U CPCI plug-in boards? WhatZiatech. processors Membership can be in implement PICMG ised open on Compact to any organizatPCI? ion or individual with a Whatlegitimat othere int functerestions in could helping benef to itext fromend Compact the PCIPCI standard? in the industrial A: Four or five 2-mm connectors are used on 6U CPCI plug-in boards. Identical Whatmarket areplace. the sof Thetware PICMG implicat canions be ofcont PCIact anded Compactat (617) PCI224?-1100. connector configurations are used on the upper and lower 3U sections of a 6U What are the system implications of CompactPCI? board. The CPCI bus is on the bottom connector. The upper connector set can be AreBack Compact to TopPCI products less prone to early obsolescence? used for a second CPCI bus or for 220 user I/O pins and 44 grounds. A 19-row What are the unique features and benefits of CompactPCI? Q: What is a bridge chip and what type of role does it have with data version of the 2-mm connector can be placed between the upper and lower What is the CompactPCI bus? transfers? connector sets providing 95 more user I/O pins and 19 grounds. What applications does CompactPCI target ? What is Compact PCI? Back to Top HowA: The many bridge elect chiprical loadsacts as can a tsorthe deskt of "superop PCI buf busfer" support chip. ?Interrupts, plug-and-play Whatinformat doesion, the and acronym data are Compact easilyPCI and st generallyand for? automatically transferred across the Q: Which Operating Systems can CompactPCI computers run? Whatbridge. are A t hebridge Origins chip of exact Compacts a onePCI-clock? penalty (generally about 30 nanoseconds) per transaction. If the data transaction is a burst mode type - transferring hundreds A: Pentium based CompactPCI computers can run all operating systems that have or thousands of bytes at a time - this overhead is extremely small. One advantage of
ever been ported to the PC, including MS-DOS, Windows 3.11, Windows 95, bridge chips is that each side of the bridge can be performing data transfers to Q:Back How to Top can I get a copy of the CompactPCI Specification? Windows NT, OS/2, BSD UNIX, LINUX, OS-9000 and QNX. PowerPC based cards on its side of the bridge simultaneously. Thus, a dual PCI system separated CompactPCI computers will be able to run AIX, SOLARIS, Windows NT, Mac OS A:byQ: aYouWhat bridge can other getchip specia cancopy fibe catiby t ransfcallingons haserring the the PI dat CMGPIaCMG at at a i781 ssuedtotal-246 of?-9318. twice tPIheCMG usual members 133 and OS. receiveMbytes/ freesecond copies rat ofe. the specifications and updates. You can get a membership applicatA: The ionfirst by ef callingfort of tthehe PIsameCMG number. was to publish a specification for passive backplane Back to Top Backcomput toers Top using both PC style (card edge connector) ISA and PCI bus. This was Backcomplet to edTop in early 1995. The PICMG has also issued a specification for PCI to PCI Q: What processors can be implemented on CompactPCI ? Q:bridges Can t hatI have allow more passive than backplane 8 slots computin a CompactPCIers to extend system the number? of PCI slots. Q:The Where Compact doesPCI the project CompactPCI is a more specirecentfi efcatiforton driven come by from a subcommit? tee of A: Although PCI has gained most of its recognition as a local bus for 80x86 based A:companies Yes. Each within Compact the PICMG.PCI bus is limited to eight slots for electrical loading reasons. PCs; PCI is at the core of all modern microprocessor designs. PowerPC and DECÕs A:This Ziat canech be Corporat easily expandedion initiated wit theh PCICompact-PCI PCIbridge eff ortchips, in 1994 available under ftromhe auspices a number of Alpha, for example, are supported with chip sets with PCI interfaces and can benefit ofmanufBack the t oPCIact Topurers. Industrial Computers Manufacturer's group (PICMG). The CompactPCI from CompactPCI. In fact, CompactPCI is the industrial bus that does the most specification is the result of a concerted effort of the CompactPCI subcommittee Q: What is the PICMG? justice to these very high performance new chips, giving them a system bus with all composedBack to Top of the following companies: Digital Equipment, GESPAC, I-Bus, Pro-Log, From cPCI FATeknor,Q: VMIC, and Ziatech. the bandwidth that these chips are capable of. A: The PCI Industrial Computers Manufacturer's Group is a consortium of more Q: Are there system integration issues when combining CPCI and VME64x on Backthan 85to Topindustrial computer product vendors. PICMG's charter is to develop A:Back Yes, to Topsince VME64x and CompactPCI use the same Euroboard mechanical thespecif sameications backpl for PCIane-based? systems and boards for use in industrial computing packaging, it is possible to combine both architectures into a single chassis. A applications. Member companies include industry leaders such as IBM, Texas Q:A: DoesWhen CompactPCI the CPCI is tsupporthe mast alerl busof the it is"Pl normallyug-and-Pl placeday" confi on tguratihe lefton side features of the specialQ: What VME64x other functibridgeons connect coulord benefipinout thas from been CompactPCI proposed f?or VME64x to CPCI iMicrosystn the PCIems, speci Industficatirialon Comput? er Source, DEC, GESPAC, Pro-Log, Teknor and A: CompactPCI can benefit all applications requiring very high data transfer rates. chassis. The bridgeboard would be the last CPCI slot and the first VME64x slot. The bridgeboards. This special connector has all of the VME64x signals on a single 2- Ziatech. Membership in PICMG is open to any organization or individual with a DatA: aCompact communicatPCI canion intbeneferfacesit all applicatsuch asions ATM requiring and broadband very high I SDNdata tareransf gooder rates. means that the bridge would have to be the VME64x system controller. This would mmexamples. connect In or.the A field bridgeboard of high-energy would physics connect research, to the f VME64xast multi-channel bus wit hdat thea top A:legit Yes,imat eincluding interest tinhe helping use of tPCIo ext-tendo-PCI the bridges. PCI standard The CPCI in the specif industicatrialion details a Data communication interfaces such as ATM and broadband ISDN are good backplanebemarket easyplace. to power implement The supply PICMG wit slot canh ftor hebe plug Tundracont-inact PSUs.ed Semiconduct at (617)The PSU 224or -1100.can Universe be powered chip. f rom connectacquisitexamples.ionor Icardsandn the t he couldfield CPCI of also high bus benef-energy witith f romtphysicshe Compactbot tresearch,om connectPCI. f Manyastor. mult ofThisi -channelthe implement most dat excita ingation would 110/ 220 VAC or 48 VDC, and can supply +5.0V, +3.3V, and +/ -12V. Pins are also requireapplicatacquisit ionsiona special cards are probably could backplane also yet benef twito behit inventbotfromh CompactVME64xed, but ifPCI andhist. Manyory Compact is ofany the indicatPCI most onion, excit the theing same PCB. defWhenBackined to t hefTopor VME64x"Current Share",is the mast "Supplyer bus Fail", the and bridgeboard "Supply Derat is te",he andlast "IVME64xnhibit". The slot and Thesophistapplicat sameicationsion expert are of probablysyst thatems simulat yetwill tincreaseo edbe inventthe t designoed, use but all of ifavailable Compacthistory is comput anyPCI indicat validating bandwidtion,ed t hetheh VME64x that "Currentthe first Share"CPCI slot signal. The is used bridgeboard for two or would more tPSUshen have running to support in a redundant the interrupt 2mmCompactsophist-bridgeicatPCIion computpinout of syst.ersems have will increase to offer. to use all available computing bandwidth that confcapabilitQ: Whatiguraties iion.s anormally briThedge "Supply chi associatp Fail"and ed whatand wit "Supply typeh a CPCI of Derat rol eCPU doese" signals board. it have indicat It wiwouldthe datathe be viabilit possibley of to CompactPCI computers have to offer. transfers? Back ttoo TopTop tlayouthe PSUs the t oCPCI the CPCI bus backwardssystem. The wit "Inhibith the" CPCIsignal CPUis usually at the connect far righted .t oThis a front would Back to Top panelmake swit thech bridge and isboard used ato slave turn oftof botthe hPSU. the VME64x and CPCI bus. Q: What are the software implications of PCI and CompactPCI ? A: The bridge chip acts as a sort of "super buffer" chip. Interrupts, plug-and-play Q: Will CompactPCI system run real -time operating systems well ? information, and data are easily and generally automatically transferred across the Q: What are the software implications of PCI and CompactPCI ? Back to Top A: The PCI architecture, developed by Intel, has been carefully planned to simplify bridge. A bridge chip exacts a one-clock penalty (generally about 30 nanoseconds) A:tA:he ThesofThetware PCIperf architormanceintegratectionure, of of developedCompact a peripheralPCI by Idevice. ntisel, part has icularlyFor been example, caref wellully t unedall planned PCI to or real Compact to -tsimplifime PCIy per transaction. If the data transaction is a burst mode type - transferring hundreds Q: Can you combine CompactPCI and VME64x? applicatdevicesthe soft havewareion, fintarom setegrat machineofion 256 of regist a contperipheralersrol which to device.machine cont ainFor vision infexample,ormat andion all f aston PCI t hedat or device aCompact acquisit identPCIion.ity, or thousands of bytes at a time - this overhead is extremely small. One advantage of Operatasdevices well asing have a syst great a emsset deal of like 256 of OSsof registt-9,wareers PSOS, programmablewhich VxWorkscontain inf paramet willormat runioners very on such t hewell asdevice on address Compact identity, PCI bridge chips is that each side of the bridge can be performing data transfers to hardwaremaps,as well or as int aanderrupt great will dealt ypesbe ofinst and sofrumentt levels.ware alprogrammable As in athe result expect, t parametheed syst successemers CPU such of can as Compact address automatPCIically in these cardsA: Yes, on itsinces side VME64x of the bridge and Compact simultaneously.PCI use tThus,he same a dual Euroboard PCI syst mechanicalem separated marketdetmaps,ect andors. int identerruptify t ypesa device and on levels. the busAs a and result conf, theigure syst item wit houtCPU tcanhe need automat for icallyjumpers bypackaging, a bridge chipit is possiblecan be t ransfto combineerring datbotah atarchit a totectalures of twice into tahe single usual chassis. 133 A ondet tecthe peripheral.and identif yPCI a device is a key on elementthe bus andof t heconf "Plugigure and it wit Play"hout conceptthe need. for jumpers Mbytspeciales/ secondVME64x rat bridgee. connector pinout has been proposed for VME64x to CPCI Backon the to peripheral. Top PCI is a key element of the "Plug and Play" concept. bridgeboards. This special connector has all of the VME64x signals on a single 2- Back to Top Backmm connect to Top or. A bridgeboard would connect to the VME64x bus with the top Back to Top Q: What products are or soon-to-be available on CompactPCI ? connector and the CPCI bus with the bottom connector. This implementation would Q: What are the system implications of CompactPCI ? Q: Can I have more than 8 slots in a CompactPCI system? Q: What are the system implications of CompactPCI ? require a special backplane with both VME64x and CompactPCI on the same PCB. A: Pentium CompactPCI CPU boards are available in 3U format and 6U format The same expert that simulated the design of CompactPCI validated the VME64x A: Modern computer architecture has an internal PCI bus, which usually supports A: Yes. Each CompactPCI bus is limited to eight slots for electrical loading reasons. from three CompactPCI vendors today (January 1996) with more on the way. 2mm-bridge pinout. PCIA: Modernadd-on computslots. Thiser archit is theect caseure has for nearlyan internal all Pent PCIium bus, PCs, which Alpha usually workst supportations,s This can be easily expanded with PCI-PCI bridge chips, available from a number of SystandPCI PowerPCemadd level-on slot addsysts. Thisems-on f isbasedunct theion case on such t hefor PREP nearlyas 100 orall MbitCHRP Pent/iums refEt PCs,herneterence Alpha, plat fast workstform SCSI statandard.,ions, accelerated manufacturers. and PowerPC systems based on the PREP or CHRP reference platform standard. Back to Top VGACompact andPCI analog makes and it possible digital I /tOo build are currentany computly available.er compliant Other wit companiesh these hardware have CompactPCI makes it possible to build any computer compliant with these hardware announcedsystem designs. plans As f ora resultPowerPC, Compact CPUPCI boards, systems fast can fiber be optbuiltics using net works,standard image Back to Top system designs. As a result, CompactPCI systems can be built using standard Q: Will CompactPCI system run real -time operating systems well ? acquisitcomponentions and and processing,can run pract moticallyion any cont operatrollers,ing systandem carrier and t boardshousands for of the popular components and can run practically any operating system and thousands of PMCapplicat andion I sofndusttwareryPack packages mezzanine without board modif icatstandards.ion. Q: Are there system integration issues when combining CPCI and VME64x on application software packages without modification. A: The performance of CompactPCI is particularly well tuned to real-time theapplicat sameion, backpl fromane machine? control to machine vision and fast data acquisition. Back ttoo TopTop Operating systems like OS-9, PSOS, VxWorks will run very well on CompactPCI Back to Top A: When the CPCI is the master bus it is normally placed on the left side of the hardware and will be instrumental in the expected success of CompactPCI in these Q: Are CompactPCI products less prone to early obsolescence? chassis. The bridgeboard would be the last CPCI slot and the first VME64x slot. The Q:Q: HowAre CompactPCI many connectors products are less used prone on to 6 Uearl CPCIy obsol plugescence-in boards? ? markets. means that the bridge would have to be the VME64x system controller. This would A: Yes. Unlike the desktop PC market which is driven by volume and fast changing A:A: FourYes. Unlikeor five t he2-mm deskt connectop PC marketors are which used is on driven 6U byCPCI volume plug and-in boards.fast changing Identical beBack easy to tTopo implement with the Tundra Semiconductor Universe chip. consumer demand, CompactPCI is driven by professional customers who value connectconsumeror demand, configurat Compactions arePCI used is driven on t byhe prof upperessional and lowercustomers 3U sect whoions value of a 6U productproduct ststabilitabilityy and long term availability.y. AllAll major major Compact CompactPCIPCI manuf manufactacturersurers WhenQ: What the VME64xproducts is are the or mast sooner -tobus-be the avai bridgeboardlable on CompactPCI is the last VME64x? slot and board.have at The least CPCI 10 years bus of is experienceon the bot eachtom connect serving tor.he TheOEM upper market connectplace andor sethave can be usedhave fator least a second 10 years CPCI of experience bus or for each 220 servinguser I/ Othe pins OEM and market 44 grounds.place and Ahave 19-row the first CPCI slot. The bridgeboard would then have to support the interrupt estestablishedablished reputreputationsions for protectinging ttheirheir cust customersomers f romfrom t hethe dangers dangers of of early early capabilities normally associated with a CPCI CPU board. It would be possible to version of the 2-mm connector can be placed between the upper and lower A: Pentium CompactPCI CPU boards are available in 3U format and 6U format obsolescence.obsolescence. This is achieved by aa carefcarefulul select selectionion of of component componentss and and their their layoutfrom t hreethe CPCI Compact bus PCIbackwards vendors wit todayh the (January CPCI CPU 1996) at twitheh f armore right on. This the way.would connector sets providing 95 more user I/O pins and 19 grounds. suppliers,suppliers, andand even, in many cases, byby ststockingocking several several years’ years’ wort worthh of of demand demand of of makeSystem the level bridge add board-on funct a slaveion such to bot ash 100the VME64xMbit/s Et andhernet CPCI, fast bus. SCSI, accelerated keykey component components.s. VGA and analog and digital I/O are currently available. Other companies have Back to Top Backannounced to Top plans for PowerPC CPU boards, fast fiber optics networks, image Back to Top Back to Top acquisition and processing, motion controllers, and carrier boards for the popular Q: Which Operating Systems can CompactPCI computers run? Q: Can you combine CompactPCI and VME64x? Q:Q: What What areare thethe unique featuresA and andCOD benefibenefitsts of Aof CompactPCI CompactPCI interface?? to IU FADCPMC andPCI Indust ryPackprototype mezzanine board exists. standards. A: Pentium based CompactPCI computers can run all operating systems that have Back to Top everA:A: Compared Compared been port ttoed st tandardo the PC, deskt includingopop PCIPCI,, CompactCompact MS-DOS,PCIPCI Windows support supportss t 3.wicetwice11, as Windowsas many many PCI PCI 95, slotslotss (8(8 versusversus 4) and offers a packaging schemescheme t hatthat is is much much bet betterter suit suiteded for for use use Windows NT, OS/2, BSD UNIX, LINUX, OS-9000 and QNX. PowerPC based Q: How many connectors are used on 6U CPCI plug-in boards? inin indust industrialrial applicatapplications. For example, CompactCompact PCI PCI cards cards are are designed designed for for front front- - CompactPCI computers will be able to run AIX, SOLARIS, Windows NT, Mac OS loadingloading andand removalremoval from a card cage.cage. TheThe cards cards are are f irmlyfirmly held held in in posit positionion by by their their andconnect OS.or, card guides on both sides, and a faceplate, which solidly screws, into the A: Four or five 2-mm connectors are used on 6U CPCI plug-in boards. Identical connector, card guides on both sides, and a faceplate, which solidly screws, into the connector configurations are used on the upper and lower 3U sections of a 6U cardcard cage.cage. CardsCards are mounted vertverticallyically allowingallowing f orfor nat naturalural or or f orcedforced air air convect convectionion Backfor cooling. to Top Finally the pin-and-socket connector of the CompactPCI card is board. The CPCI bus is on the bottom connector. The upper connector set can be for cooling. Finally the pin-and-socket connector of the CompactPCI card is used for a second CPCI bus or for 220 user I/O pins and 44 grounds. A 19-row signifsignificanticantlyly moremore reliable and has betbettterer shockshock and and vibrat vibrationion charact characteristeristics,ics, than than version of the 2-mm connector can be placed between the upper and lower Q:tthehe card Whatcard edgeedge processors connectconnector can of the be stst iandardandardmplemented PCIPCI cards. cards. on The CompactPCIThe power power and and signal? signal pins pins on on connector sets providing 95 more user I/O pins and 19 grounds. tthehe Compact CompactPCIPCI connector are ststagedaged soso asas t too allow allow t hethe specif specificaticationion in in the the fut futureure A:to supportAlthough hot PCI swapping, has gained a feature most that of is it verys recognit importantion fasor faault local tolerant bus f systor 80emsx86 based to support hot swapping, a feature that is very important for fault tolerant systems Back to Top PCs;andand whichwhich PCI isis notatnot t hepossible core ofon allstandard modern PCIPCI microprocessor.. designs. PowerPC and DECÕs Alpha, for example, are supported with chip sets with PCI interfaces and can benefit Q: Which Operating Systems can CompactPCI computers run? fBackBackrom Compactttoo TopTop PCI. In fact, CompactPCI is the industrial bus that does the most justQ: iceWhat to itshese the CompactPCI very high perf busormance? new chips, giving them a system bus with all A: Pentium based CompactPCI computers can run all operating systems that have tQ:he Whatbandwidt is theh tCompactPCIhat these chips bus are? capable of. ever been ported to the PC, including MS-DOS, Windows 3.11, Windows 95, A: CompactPCI is a very high performance industrial bus based on the standard Windows NT, OS/2, BSD UNIX, LINUX, OS-9000 and QNX. PowerPC based A: CompactPCI is a very high performance industrial bus based on the standard Back to Top CompactPCI computers will be able to run AIX, SOLARIS, Windows NT, Mac OS and OS. Q: What other functions could benefit from CompactPCI ? Back to Top
Q: What processors can be implemented on CompactPCI ?
A: Although PCI has gained most of its recognition as a local bus for 80x86 based PCs; PCI is at the core of all modern microprocessor designs. PowerPC and DECÕs Alpha, for example, are supported with chip sets with PCI interfaces and can benefit from CompactPCI. In fact, CompactPCI is the industrial bus that does the most justice to these very high performance new chips, giving them a system bus with all the bandwidth that these chips are capable of.
Back to Top
Q: What other functions could benefit from CompactPCI ? !"#$%&"'()*+'#&,-.+'-)/01
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!"#$%&&'( PICMG 2.16
Topologies
• The PSB links runs across a Star or Dual Star configuration (not a bus) in a centralized topology. • Each line interconnecting a Node Slot and Fabric Slot represents a Link that is a 10/100/1000 Mbps full duplex Ethernet connection
(Two Link Ports) (One Link Port) PICMG 2.16
About PICMG 2.16 (CompactPCI Packet Switching Backplane cPSB)
• cPCI can still be used (control plane); cPCI and H.110 compatible
• Overlays a packet-based switching architecture on top of CPCI to create an Embedded System Area Network (ESAN)
• Integrates Ethernet on backplane
• 95% of world-wide data travels on Ethernet! (up to 2Gb/s full duplex)
• 85% of installed networks are Ethernet Ethernet technology continues to be incorporated into more products than ever before
• Standard cPCI connector PICMG 2.16
Node and Fabric pin out • Connection to Node slots is done via J3/ P3 pins (up to 4 Gbps) • Connection to Fabric Slots is done via P3/P5 pins (up to 40/50 Gbps) VITA 31.1 Gigabit Ethernet on VME64x
About VITA 31.1
!Overview: Defines a pin out for implementing a 10/100/1000BASE-T Ethernet switched network across the P0/J0 VME64x backplane connectors. ! Topologies: Single star fabric switch or dual Possible VITA31.1 configuration star fabric switch architecture. ! Fabric Slot: Requires 1 or 2 dedicated fabric-switch slots. These utilize 5 2mm HM connectors and pin assignments are identical to the PICMG 2.16 Packet Switched Bus. Fabric switch cards can be used in either the VME or CompactPCI Environment. node boards (specifies 2mm HM numbering from bottom up as in PICMG) ! Node Slot: Fabric A – B19 P0 rows 2,3; Fabric B- B19 P0 rows 4,5; GNDs P0 Row 1,6 ! ! ! !!!!!!!!!!!!!!
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2344"% ! "#$%&'()!*+!,-).!/.0(#1(.2!*! 3&4-5&.!/.0(#1(.!60-11(7)!-1'! -1!0&40!)8(('!59)!:$#!1(.;$#$?87&-1.!;&.0!"@>A3!*BCD!$#! E@FG!HCBC!)I).(?! ! J&40!)8(('!1$1K57$6<&14!7-I(#! *!);&.60!;&.0!L! ! M.$#(K-1'K:$#;-#'!! ! +NNN!AG>!-'#())()! ! M.-.&6!$#!G9.$?-.&6!AG>! -''#())!?-1-4(?(1.! ! O#$-'6-).!:&7.(#&14! ! G9.$K1(4$.&-.&$1!-1'!-9.$KAP@Q AP@R!6#$))$%(#!:$#!.#9(!"794K1K "7-I!! ! "#$%&'()'*+!* "#(%(1.)!8-6<(.!7$))!;&.0!5-6'$%&1./1%'9".%-''+/5'%7"'?,0+@,%-'9".%-A'=&1-1'9."5B8%-' 6$1.#$7! +.1'@B,3%'"/'+'-,/031'&1,0&%'CD'@"+.5A' ! '' T$M!7-I(#!*QH!9)&14!.;$!8#&$#K !"#$%&'()**+'9".%-'+.1'8"#9+%,@31'@"%&'7,%&'EF!G?'6A)C'".'HF=I'J)A)'-4-K &.IKU9(9(!;&.0!-'%-16('!6$1K %1#A'I'.1+.'F ! VDC expects that over 50% of CompactPCI PICMG 2.17 (StarFabric) Other Fabrics or Slot SBCs will be 2.16 compliant in 2004. 3% Serial Interconnects ! StarFabric has achieved acceptance in 2% several markets, including Military / Aerospace, with several design wins. Product rollouts continue. PICMG 2.16 ! PCI-Express Advanced Switching is (Ethernet Fabric) expected to have a significant impact 29% when silicon is readily available. None ! InfiniBand is alive and well, particularly in 67% “supercomputing”; Embedded InfiniBand initiative under way within IBTA and VITA. Silicon readily available. ! RapidIO product rollouts continue; expect increasing native support for RapidIO in PowerPC CPUs. Xilinx shipping FPGAs containing PowerPC processors and RapidIO interfaces. !"#$%&'()*+,-)&$'.","-"/0$1 !"##$%&'($ ) !"#$#%&''#()*+#)$,+#"-.)#+$*#$#./0),1#,-""),1/-"#1-# )2)03#-1+)0#"-.) ) 4$".5/.1+#$660)6$1)* H 7 !"#1+/*#)8$9:')#)$,+#-;#<#"-.)*# H H +$*#=#*):$0$1)#,-""),1/-"* 7 >**&9/"6#?@AB:*#'/"C*#1+/*# 5-&'.#3/)'.#<#D#=#D#?@AB:*# H H -0#EF@AB:*#-;#$660)6$1) *3*1)9#B$".5/.1+ ) %$/'&0)#-2)0+)$.#/*#0).&,). H H 1-#-"'3#"G? H !"#$%&&'( PICM 2.17 StarFabric About PICMG 2.17 ! Defines backplane, Node Boards and Switch Boards ! 3 types of Boards ! Basic ! Multi-Segment ! Fabric Native ! Compatible with existing PICMG specs. ! Migration path to PCI Express Advanced Switching ! 2.5Gbs per Slot (with four 622Mbytes/s links); roadmap up to 10Gbs ! High Availability, Multiple classes of traffic (asynchronous and isochronous). ! Redundant, point to point, high-speed serial connection ! Virtual Backplane possible (shelf address) ! CompactPCI connector with the addition of a type A 2mm HM module. VXS – VITA 41 • Very high speed switched serial interconnect for VME • VXS is a second wave VME Renaissance technology • Two new versions of the spec were ratified during year 2003 – Accommodate conduction cooling – Accommodate PMC seated in front of new P0 connector • Rear Transition Module (RTM) spec in draft 13 PICMG 1.3 (Industrial PCI Express) About PICMG 1.3 (IPCI-E) !PCI-Express over PICMG 1.X type of backplane ! Backplane can operate at 1X, 4X, 8X, or 16X ! Both full and half size SHB (Half-size SHB form factor based on half-size PCI-E board) ! The full-size SHB and backplane has 16X PCI-Express connectors (A and C) and one 8X PCI-Express connector (B). !Optional ATX, EPS, or BTX Power Supply Support VITA 48 Enhanced Ruggedized Design Implementation (ERDI) About VITA 48 ! Enclosed front removable slot card modules: ! High power ! EMI shielding ! forced air or liquid flow-thru cooling ! cold plate with ATR clamp-guides ! rugged modular slot-bay construction ! Nominal 6U-160mm form factor ! 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Random Interleaved 356/7/:5:/&2!05:5!:,5&13$,!:-!5&0!3,-4!0$1/2&1!,8&&/&2!/&!:#$!81$,! (??7%/51%4-+ Sampling (RIS) for The complete line of eight LeCroy PXD Digitizers from 150 MHz to 1 GHz Bandwidths B;C'17$!:-!:#$!81$,!:#,-82#!:D-!0/33$,$&:! • Complete line /&:$,356$15$1'(-1#--5'($of $3U5F+ PXI' digitizers The PXD series features a complete line of The PXD series digitizers include several software FEATCU,5+#/RE65S7! O1$,! )&:$,356$! 3-,! B;C'! 6-&3/28,5:/-&! 5&0! 05:5! APPLI CATI ONS !! @05+#6'($$5F':5• F6ast5$' PCI bus PXI digitizers with bandwidths ranging from tools to help you quickly get started and devel- :,5&13$,M!D#/7$!:#$!*-&3/28,5:/-&!K-3:D5,$!B8&6:/-&1!+,-./0$!:#$! 150 MHz to 1 GHz. It also features high channel oping test software in LabView, CVI,Visual C++, • 2 GS/s A/D sampling !! data-transferCommunications rates & wireless 154$!38&6:/-&57/:?!/&!:#$!3-,4!-3!38&6:/-&1!3-,!/&6781/-&!D/:#/&! ;271%/05--#7')515'(/G2%+%1%4-'' density with up to 8 channels in a single or Visual Basic. The PXD series software includes 81$,1X!-D&!1-3:D5,$ signals' , with excellent accuracy within the Getting Started application program for • Up to 1.2 GHz bandwidth Synthetic instrumentationcompact, rugged, modular architecture of PXI. interactive control. • Multi-card systems of up to 2 channels at 2 GS/s (4 channels at 1 GS/s) Electro-optic The PXD series digitizers are based on the The LeCroy PXD series provides a cost efficient, Laser/Radar desktop computer PCI standard and are fully PXI space efficient, high performance digitizer solu- • Pre-Trigger Multiple Record mode High energy physicscompliant. Fast data-transfer rates and improve- tion for production test applications including: • Fast data transfer rate to system RAM ments in test times are realized, compared to tra- • Analytical Instruments Embedded digitizerditional GPIB instruments. The plug-and-play • Disk Drive Testing • SDKs for C/C++, MATLAB, LabVIEW & LabWindows/CVI under Win 95/98/ Scope replacementfunctionality of these PXI digitizers provides ease • Communications Test Systems ME and Win NT/2000/XP of setup and use. • Automotive • Aerospace and Defense CAEN Struck Integrating High Performance VME, PCI and CPCI processors into CPU clusters for Data Acquisition and Control Systems L. Vivolo, M. Weymann, F. H. Worm Creative Electronic System, 70 Route du Pont-Butin, CH 1213 Petit-Lancy/Geneva,Switzerland email: , web: Abstract Data acquisition and control systems using a large number of embedded VME processors have a long tradition in High Energy Physics. More recently, CPCI is in some cases consi- dered as an alternative to VME. CES has developed a processor board architecture optimized for high-throughput deterministic bus operation, which can used with minimal adaptation on both backplanes. The RIO3 8064 (VME) and RIOC 4065 (CPCI) are to a large extend software compatible which helps to develop software solutions almost simultaneaously in both domains. Both boards couple the CPU bus directly to the backplane bus (VME or CPCI) and to two independent PCI busses. This twin-bus architecture allows to separate data flows in a similar way than VME/VSB architectures did in the past. The MFCC 844x, a PowerPC based PMC module is ideally suited to handle complex I/O protocols or to build multi-CPU clusters coupled by the carrier boards local PCI bus rather than the backplane bus. The CES PVIC allows to interconnect distant PCI segments (e.g a VME based processor cluster and a desktop workstation) using both memory mapped access and DMA mechanisms. With its backplane driver CES provides an ideal tool to integrate CPUs interconnected by PCI,VME,CPCI and PVIC into a homogeneous, network-oriented environment taking full advatage of the high bandwidth and low latency features of PCI and bakplane busses. Keywords: PowerPC, VME, PCI, CPCI, PVIC 1 Introduction The vast volume of data generated by physics detectors requires computing power beyond the reach of any existing single computer. On the other hand an ever higher bandwith is required for accomodating the data flow between the digitizing electronics and the final data analysis and storage stages. Looking at the dataflow through a typical data acquisition system of an HEP experiment we can distinguish different requirements for DAQ processors. In a front-end stage, sub-detector data are stored temporarily. A large fraction of the data may be rejected at this stage. Accepted data are forwarded to the following stages. Critical requirements here are low latencies and high I/O performance. In an Event-building stage data arriving in parallel on a large number of input channels are grouped together into complete events. This may imply covering relatively large distances and requires very high integrated throughput. Candidates are switched networks (e.g ATM) or high-performance bus-to-bus links like PVIC [5]. In the analysis stage complete events are processed. The key requirement here is CPU power. Proposed solutions include processor farms in which a large number of processors work in parallel. Each processor works on a single event at a time, the next event arriving is given to the first free processor in the farm. CES - CREATIVE ELECTRONIC SYSTEMS CPCIRIOC 4067PROCESSOR BOARDS PowerPC-Based CompactPCI 2.16 Switched Backplane Real-Time Processor Board Optional L3 cache PowerPC 7455 Optional (2 MBytes) PowerPC 7455 L3 cache (2 MBytes) 64-bit PowerPC bus at 100 MHz SDRAM PPC-to-XPC (up to 2 GBytes) FPGA 64-bit XPC bus at 100 MHz PCI #1 64-bit PCI bus XPC-to-CPCI XPC-to-PCI • User I/O • Serial Lines FPGA FPGA • Timers • SIC • NVRAM • 10/100 Base- • FEPROM Tx Ethernet • SSRAM CompactPCI Interface + GETH #1 GETH #2 BMA PPMC 64-bit CPCI bus J1 J2 J3 J4 J5 Back Panel Extension User I/O for PMC Carriers HIGHLIGHTS NEW FEATURES BRUTE FORCE POWER > Single or dual PowerPC 7455 at maximum CPU speed with 2 The RIOC 4067 is a derived version of the RIOC 4068 with CompactPCI MBytes external L3 cache (DDR SSRAM) 2.16 switched backplane. It provides a full function compatibility solution GLOBAL MEMORY AT CACHE SPEED at the slide–in slide-out level, but also features important innovative improvements. > Up to 2 GBytes SDRAM at 800 MBytes/s peak THREE CONCURRENT BUSES AT FULL SPEED The onboard PowerPC core is the latest PowerPC 7455 PowerPC chip featuring: > Local PCI, CompactPCI and switched backplane > 800 MHz to 1 GHz frequency HIGH-PERFORMANCE COMPACTPCI INTERFACE > First PowerPC to allow for the attachment of an L3 cache > Multichannel independent DMA engine > Improved memory access and parallel interconnection sequences > Automatic selection of CompactPCI system slot or peripheral slot In the case of the RIOC 4067, 2 MBytes of L3 cache (DDR SSRAM) have been incorporated, as well as provision for a twin CPU organization. STATE-OF-THE-ART SOFTWARE > BSPs for LynxOS®, VxWorks®, Integrity®, TimeSys® and The CES PowerPC-to-XPC bridge has been improved and allows 2 Linux® with CES-enhanced specifications GBytes of directly accessed global memory from all of the buses. > Network protocols on PCI and CompactPCI (TCP/IP and high- The second PCI 64-bit bus on J3 has been replaced by a CompactPCI speed channel mode - CES BP-Net) 2.16 switched backplane interface logic, which features the latest INTEL ADDITIONAL FEATURES Gigabit Ethernet couplers with large on-chip buffers to reduce the CPU > Onboard power control logic load. > One PPMC slot (64-bit at 33 MHz) The first PCI 64-bit bus is maintained for one onboard PPMC slot and now > 2 x Gigabit Ethernet backplane ports with latest INTEL 82544 chip incorporates a totally new power up control and monitoring logic for the > Backward compatible with RIOC 4065 family onboard CES PPMCs. ANCILLARY LOGIC GENERAL DESCRIPTION Ancillary logic includes SSRAM, NVRAM, Flash EPROM, Fast Ethernet This machine combines the latest primed CPU, CompactPCI and and RS232 connections. PCI advanced features, which include L3 cache, direct CompactPCI- to-memory interface and an independent PCI bus. The bus shares Special care has been given to temperature monitoring through the use of independent concurrent access to the global memory at sustained 400 multiple onboard sensors. MBytes/s throughput. The integration risk for strategic applications has been significantly reduced by the use of FPGA-based PowerPC-to-PCI and PowerPC- to-CompactPCI bridges, where all of the missing functions in existing commercial bridges have been added and fine-tuning of the application has been made possible. These features make the RIOC 4067 the ideal platform for computing intensive applications requiring both very quick access to the incoming traffic and large parallel computing capability. CES - CREATIVE ELECTRONIC SYSTEMS GENERALGPIO 8409 PURPOSE I/OS ! rable Reconfigurable I/O PMC and Rocket I/O Interconnect PMC nfi gu Reco Clock Flash Debug Generator EPROM Port Customer- PCI / PCI-X Specific 100 user I/Os Customer Virtex-II Pro CES IP Daughter Specific FPGA Interface Board 64 User I/Os UHS UHS RLDRAM RLDRAM SECURE CELLS LOGIC HIGHLIGHTS CES-DESIGNED I/O FUNCTION PMC FORM FACTOR: CES has designed a collection of GPIO-based I/O PMCs (for the GPIO > 32 / 64-bit PCI at 33 MHz, PCI-X at up to 133 MHz 8405 and GPIO-E 8405). They include an application-specific front-end > PTMC compliant option (over P3 / P4, no rear I/O capabilities) adaptation nose and a dedicated FPGA. USER-DEFINED I/O: The first CES-designed I/O function based on the GPIO 8409 is a high- > User-defined front-end electrical adaptation speed link PMC, which includes four channels at up to 3,125 Gbit/s > 100 (2 x 50) user-defined I/Os on the front-end equipped with SFP pluggable transceivers. > 64 user-defined I/Os for the rear electrical adaptation ONBOARD FPGA: CES - CREATIVE ELECTRONIC SYSTEMS > Onboard Virtex-II Pro FPGA > CES integration tools for user-specific FPGA development GPIO-BASED CUSTOM APPLICATIONS > Ultra-high-speed DDR RLDRAM memory (2 banks of 32 MBytes)GENERAL coupled to the FPGA PURPOSECES’ policy I/Ois to assistS customers in their PMC design by providing GPIO 8409 engineering assistance and advice, as well as a transfer of guaranteed > Dynamic reconfiguration capabilities ! rable Reconfigurable I/O PMC and Rocket I/O Interconnect PMC nfi gu ADDITIONAL FEATURES: PCI interfacing solutionsR alreadyeco used on our own PMCs. > 32 MBytes Flash EPROM Special training sessions to help customers develop their own GPIO- > Multiple thermal sensors based I/O function include: > Internal and external synchronization > Introduction to FPGA programming and validation tools Clock Flash Debug > Examination of Gaen genericerator protocolEPROM Port > Introduction to the CES tools for downline loading and control code Customer- PCI / PCI-X > AssistanceSpecific for generation of customer-specific protocols 100 user I/Os Customer Virtex-II Pro CES IP CES SECURE CELLS PACKAGE Daughter Specific FPGA Interface Part ofB otheard FPGA is dedicated to end-user applications.64 User I/Os A specific debug connector for the CES CISP 6443 tool allows support of multiple JTAG The secure cells package is a dynamic hardware-based, but user- UHS UHS accessible, control and monitoring function set for critical applications. chains, third party tools andRLDR AFPGAM RspecificLDRAM I/Os. It provides board-level mission change capabilities based on hardware, The CES “ISLE” conceptSECURE C EprovidesLLS LOGIC a normalized hardware IP environment software, environmental and bus load parameters, all monitored in real- for immediate customer integration with the GPIO resources. time. Amongst them, CES IP covers: HIGHLIGHTS CES-DESIGNED> RLDRAM controller I/O FUNCTION(dual port support) > DMA controller for high-speed PCI-X to / from the “ISLE” transfer GENERALPMC FORM DESCRIPTION FACTOR: CES> hasSide designed bandGPIO signaling a collection 8409CA (control, of GPIO-based status,- ROCKET FIFO, I/O PMCs interrupt, I/O (for INTERCONNECT the etc.) GPIO > 32 / 64-bit PCI at 33 MHz, PCI-X at up to 133 MHz 8405> Localand GPIO-E bus slave 8405). interface They include an application-specific front-end > PTMC compliant option (over P3 / P4, no rear I/O capabilities) adaptation> CES nosePowerPC and a dedicated405 service FPGA. block (embedded PowerPC 405 kernel The GPIO 8409 has been designed for building I/O subsystems connected The GPIO 8409CA supports the RocketIO connections with front panel USER-DEFINED I/O: The first CES-designed I/O function based on the GPIO 8409 is a high- to the PCI bus of the VME and CompactPCI CES real-time platforms. support) small form package connectors, which can house a variety of optical > User-defined front-end electrical adaptation speed link PMC, which includes four channels at up to 3,125 Gbit/s The front-end> section100 (2 incorporatesx 50) user-defined an ultra-high-speedI/Os on the front-end large dimension equippedEach “ISLE” with SFP istransceivers. specified pluggable withtransceivers. It aalso number maintains of I/O 100ports independent associated withuser-accessible the I/O programmable> logic64 user-defined device (FPGA I/Os forVirtex-II the rear Pro electrical XC2VP20 adaptation / XC2VP30), VHDL infrastructurebuses. (test bench, component instantiation, etc.) and CES which is connectedONBOARD on FPGA: one side to the PCI bus and on the other side either provides support> for64 theMBytes binary of and/orultra-high-speed source VHDL RLDRAM code. to the front panel> Onboard via an Velectricalirtex-II Pro adaptor FPGA or to the PMC I/O connector > 32 MBytes Flash EPROM (PN4) on the >rear CES. integration tools for user-specific FPGA development GPIO-BASED> CUSTOnboardOM V irtex-IIAPPLICA Pro FPGATIONS > Ultra-high-speed DDR RLDRAM memory (2 banks of 32 > Houses four pluggable SFP transceivers Due to the removableMBytes) coupledfront-end to theadaptor FPGA and to the reprogrammable CES’ policy is to assist customers in their PMC design by providing FPGA, the GPIO can be used to execute different I/O functions at different > Supports single-mode and multi-mode fibers at up to 3.125 Gbit/s > Dynamic reconfiguration capabilities50 User I/Os Clock Flash Debug engineering assistance and advice, as well as a transfer of guaranteed Generator EPROM Port > 32 / 64-bit PCI or PCI-X interface times as user-requirements change.SFP Transceiver PCI interfacing solutions already used on our own PMCs. ADDITIONAL FEATURES: > Multiple thermal sensors > 32 MBytes Flash EPROM PCI / PCI-X Special training sessions to help customers develop their own GPIO- An extended specification and a conduction cooledV irteversionx-II Pro will be > Secure cells package (option) > Multiple thermalSF PsensorsTransceiver FPGA based I/O function include: available soon. 64 User I/Os > Sockets for user-specific mini mezzanine > Internal and external synchronization > Introduction to FPGA programming and validation tools SFP Transceiver UHS UHS > Examination of a generic protocol RLDRAM RLDRAM > Introduction to the CES tools for downline loading and control code SFP Transceiver SECURE CELLS LOGIC > Assistance for generation of customer-specific protocols CES SECURE CELLS PACKAGE50 User I/Os VERSIONS AVAILABLE Part of the FPGA is dedicated to end-user applications. A specific debug The secure cells package is a dynamic hardware-based, but user- connector for theGPIO CES 8409AACISP 6443 tool allowsGeneral support Purpose of multiple I/O JTPMC,AG Virtex-II Pro (user interface without SFP cage) accessible, control and monitoring function set for critical applications. chains, third party tools and FPGA specific I/Os. It provides board-level mission change capabilities based on hardware, The CES “ISLE” GPIOconcept 8409BA provides a normalizedGeneral hardware Purpose IP environment I/O PMC, Virtex-II Pro (GPIO 8405 nose compatible) software, environmental and bus load parameters, all monitored in real- for immediate customer integration with the GPIO resources. time. GPIO 8409CA General Purpose I/O PMC, Virtex-II Pro (with SFP Amongst them, CES IP covers: cage, SFP tranceivers not included) > RLDRAM controller (dual port support) > DMA controller for high-speed PCI-X to / from the “ISLE” transfer GENERAL DESCRIPTION > Side band signaling (control, status, FIFO, interrupt, etc.) > Local bus slave interface The GPIO 8409 has been designed for building I/O subsystems connected > CES PowerPC 405 service block (embedded PowerPC 405 kernel to the PCI bus of the VME and CompactPCI CES real-time platforms. support) The front-end section incorporates an ultra-high-speed large dimension Each “ISLE” is specified with a number of I/O ports associated with the programmable logic device (FPGA Virtex-II Pro XC2VP20 / XC2VP30), VHDL infrastructure (test bench, component instantiation, etc.) and CES which is connected on one side to the PCI bus and on the other side either provides support for the binary and/or source VHDL code. to the front panel via an electrical adaptor or to the PMC I/O connector (PN4) on the rear. Due to the removable front-end adaptor and to the reprogrammable FPGA, the GPIO can be used to execute different I/O functions at different times as user-requirements change. An extended specification and a conduction cooled version will be available soon. CES - CREATIVE ELECTRONIC SYSTEMS S.A. - 38 AVENUE EUGÈNE-LANCE - 1212 GRAND-LANCY 1 - SWITZERLAND - TEL: +41.22.884.51.00 - FAX: +41.22.794.74.30 - [email protected] - HTTP://WWW.CES.CH The information in this datasheet is subject to change without notice and should not be construed as a commitment by CES. While reasonable precautions have been taken, CES assumes no responsibility for any errors that may appear in this datasheet. DOC 8409/D Version 1.2 - September 2004 - Creative Electronic Systems S.A. - All Rights Reserved 5363$!78920262:;$<:4 DCBADCBA 52=263> !""#$$$%&'($)*+$,--. /($#0121343 !;3>:= * Recommendations (Opinions): • IU: Continue prototype of cPCI fADC with “parallel” energy sum for calorimeters • CNU: Continue prototype study of “serial” energy sum • JLab: Continue “universal” fADC design, test in existing halls • Don’t overconstrain GlueX design space yet • Keep an eye on emerging “form factors” • CODA group should consider ramifications of “all ethernet” solution • GlueX will have electronics/DAQ collaborators from outside lab “push” vs “pull” ethernet Current CODA model push modules OC sparse data R event interrupt buffer in ROC pull ethernet GlueX CODA model? push modules large data blocks witch s no event interrupt buffer in modules push