Low-Voltage and Low-Power Libraries for Medical Socs

LOW-VOLTAGE AND LOW-POWER LIBRARIES FOR MEDICAL SOCS

A Thesis

Presented in Partial Fulﬁllment of the Requirements for the Degree Master of Science in the

Graduate School of The Ohio State University

Sidharth Balasubramanian, B. E.

Electrical & Computer Engineering Graduate Program

*****

The Ohio State University

2009

Thesis Committee:

Mohammed Ismail El-Naggar, Advisor Waleed Khalil c Copyright by

Sidharth Balasubramanian

2009 ABSTRACT

The recent focus on Green Electronics and a rapid revolution of bio-chips has led to the need for designs operating with lower supply voltages and consuming lesser power than before. This thesis focuses on the design of a library of low-voltage and low-power circuit designs on TSMC 0.13 µm process. A survey of existing well-known architectures for bio-medical acquisition systems is done, and some modifications to the existing system is presented. A low-voltage rail-to-rail amplifier is designed with a novel voltage-mode technique to obtain constant transconductance over the entire common-mode input range. The power consumption of this amplifier is less than 3

µW . A universal figure-of-merit is established to rank a rail-to-rail input stage, taking into account the complexity in designing in sub-micron processes. This new figure-of- merit accounts for the variation in transconductance, the maximum common-mode range possible and the power consumption. A chopper amplifier with about 33 dB gain, capable of operating from 1 V to 1.8 V is presented. A sub-threshold MOS-only voltage reference operating from a 0.5 V supply with a temperature coefficient of

20.8 ppm/oC is designed. A Dickson charge pump with an output voltage of 5 V is designed for pacing applications. A 1 V successive-approximation ADC with 8-bits of resolution is designed. A 1 V rail-to-rail comparator with a 1 V D-latch is designed as part of the ADC. The digital logic of the SAR ADC was implemented in Verilog-A.

ii Dynamic power consumption was measured over 100 clock cycles for the comparator and the latch together and was found to be 4.3 µW at a 1 MHz clock.

iii To my parents, for their love and suport.

iv ACKNOWLEDGMENTS

First, I give thanks to my parents, V. Balasubramanian and C. A. Dolly Jayashri, who have always been supportive and understanding. Any success that I have today, could not have been possible without them.

I express my gratitude to OSU for honoring and supporting me with a University

Fellowship for my ﬁrst academic year. My sincere thanks to all those who were responsible for helping me in receiving the fellowship.

My advisor, Professor M. Ismail, deserves thanks not only for his wisdom and guidance but also for the amount of freedom he gave me. It is a privilege to have worked with him. Through him, I learned what engineering really means. I also thank him for the conﬁdence he had in me, even when my mind was wandering with ideas and did not know what to do. I thank him sincerely for agreeing on this thesis.

I wish to thank Dr. Waleed Khalil, for agreeing to take the time to be a member of my Masters Examination Committee. I learnt a great deal about PLLs while working with him. His ideas and thought processes have surprised me so much, and I can’t wait to learn more from him. I also thank Dr. Steven Bibyk for being the nicest guy one could ever meet in his life. He is deﬁnitely an extremely student-friendly Prof.

I must thank Dr. Reano for having oﬀered his course on Integrated Optics. It was my most enjoyed course, where I learnt a great deal about Planar Optical Devices. I shall never forget the time I had spent working on his course.

v I also owe sincere thanks to my former advisor, Professor P. V. Ramakrishna at

College of Engineering, Guindy, Anna University Chennai, India for inculcating in me the desire to pursue graduate education in Electrical Engineering, in the beautiful ﬁeld of Analog VLSI Design. His teachings have always made me look at every problem from an entirely diﬀerent perspective. He taught me to learn by intuition rather than crunching pages and pages of math. A very valuable thing that I learnt from him is to decide to research in an area, only after I knew what existed in the other areas of

Electrical Engineering. My days spent with him in CEG at the Integrated Systems

Laboratory will never be forgotten in my entire life.

Having been away from home for the ﬁrst time in my life, my arrival in Columbus made me feel uncomfortable. But as days passed by, I found myself a new home and a family of friends who have made my stay in Columbus the ‘Best days of my Life’.

I am grateful to have had wonderful roomies. I learnt a great deal about life and realized that life was not just about studying and books, but there was a lot more to it. I learned to appreciate the imperfections in people, that can make life perfect for you. Eshwar, Gayathri, Sai, Sanky, Santhosh, Medha, Sami, Niharika, Shan - Thanks a ton all of you for making my days and for being the comical relief of my life! A special thanks to the one who named me ‘Tonty’. I will never forget those precious memories that have been built up with you and will cherish them forever in me.

I must thank my senior and friend, Shankar Thirunavukkarasu, who helped me with any question I had with regard to circuit analysis and design. There are still many others at CEG and OSU, whom I thank for having inﬂuenced and inspired me in every stage of my life.

vi VITA

May 12, 1987 ...... Born - Coimbatore, Tamil Nadu, India

June 2008 ...... B.E., Elec. & Comm. Engineering

2008–2009 ...... University Fellow, The Ohio State University October 2009–present ...... Graduate Teaching Associate, The Ohio State University

PUBLICATIONS

Research Publications

S. Balasubramanian. “Optical Modulators Using Planar Split-Ring Resonators” In Proceedings of the IEEE National Aerospace and Electronics Conference, 2009.

FIELDS OF STUDY

Major Field: Electrical & Computer Engineering

vii TABLE OF CONTENTS

Page

Abstract...... ii

Dedication...... iv

Acknowledgments...... v

Vita...... vii

List of Tables...... xi

List of Figures...... xii

Chapters:

1. Introduction...... 1

2. Bio-signals and Bio-acquisition Systems...... 5

2.1 Introduction...... 5 2.2 Bio-potentials...... 5 2.3 Bio-signal acquisition systems...... 8 2.3.1 Three-Opamp Instrumentation Amplifier...... 11 2.3.2 Switched-capacitor Amplifiers...... 13 2.3.3 Chopper Amplifier...... 15 2.3.4 Variants of the Chopper Amplifier...... 19

3. Low-Voltage Ampliﬁer with Rail-to-Rail Input Stage...... 22

3.1 Introduction...... 22 3.2 Low-Voltage Techniques for Ampliﬁer Design...... 23

viii 3.3 Rail-to-Rail Ampliﬁer...... 24 3.3.1 Existing techniques to obtain Constant-gm input stages.. 25 3.4 Voltage-Mode Design of a Rail-to-Rail Input Stage...... 27 3.5 Benchmarking Rail-to-Rail Input Stages...... 31 3.6 Simulation Results...... 33

4. Low-Voltage Chopper Ampliﬁer...... 37

4.1 Introduction...... 37 4.2 Chopper...... 37 4.2.1 Design Methodology...... 39 4.3 Main Ampliﬁer...... 41 4.4 Simulation Results...... 42

5. Dickson Charge Pump...... 46

5.1 Introduction...... 46 5.2 Charge Pump - The basic theory...... 46 5.3 The Dickson Charge-Pump...... 48 5.4 Dickson Charge pump as a Pacer...... 49 5.5 Simulation Results...... 50

6. Low-Voltage MOS-only voltage reference...... 55

6.1 Introduction...... 55 6.2 CMOS characteristics in Weak Inversion...... 56 6.3 MOS-only voltage reference...... 58 6.4 Simulation Results...... 59

7. Low-Voltage 8-bit SAR ADC...... 61

7.1 Introduction...... 61 7.2 Successive Approximation ADC...... 63 7.3 Building - Blocks...... 65 7.3.1 Rail-to-Rail Comparator...... 65 7.3.2 D-Latch...... 69 7.3.3 Level-shifter...... 71 7.4 Comparator Simulation Results...... 71 7.5 ADC Simulation Results...... 71

8. Conclusion...... 76

8.1 Future Work...... 76

ix Appendices:

A. Basel Problem...... 78

Bibliography...... 80

x LIST OF TABLES

Table Page

3.1 Rail-to-Rail Ampliﬁer – Performance Summary...... 34

3.2 Rail-to-Rail Ampliﬁer – Corner Simulation Performance Summary.. 36

4.1 Chopper Ampliﬁer - Eﬀect of Chopper supply on Gain...... 45

6.1 Low-voltage MOS-only reference – Performance Summary...... 60

7.1 Successive Approximation ADC – Performance Summary...... 74

xi LIST OF FIGURES

Figure Page

2.1 Cell Potential...... 7

2.2 Bio-signal Spectra...... 9

2.3 Electrode-Electrolyte Interface...... 10

2.4 Three-opamp Instrumentation Ampliﬁer...... 12

2.5 Switched-Capacitor Ampliﬁer...... 14

2.6 Chopper Ampliﬁcation Technique...... 18

3.1 Rail-to-Rail Ampliﬁer : Contribution of Input Swing due to NMOS and PMOS input diﬀerential pair...... 25

3.2 Node voltages VX and VY and eﬀective transconductance as a function of the input common-mode voltage...... 28

3.3 Node voltages VX and VY and eﬀective transconductance as a function of the input common-mode voltage for the Voltage-Mode technique. 29

3.4 Rail-to-rail ampliﬁer with a folded-cascode load - Schematic..... 30

3.5 A simple negative feedback model to bias the current source and sink - A behavioral simulation...... 31

3.6 Simulated transconductance variation as a function of input common- mode voltage...... 34

3.7 AC response of the rail-to-rail ampliﬁer...... 35

xii 4.1 Chopper – Schematic...... 38

4.2 Chopper Ampliﬁer – Schematic...... 41

4.3 Chopper Ampliﬁer – Transient Simulation...... 43

4.4 Chopper Ampliﬁer – Gain variation with chopper supply...... 44

5.1 Dickson Charge Pump - Transistor Implementation...... 48

5.2 Dickson Charge Pump as a Pacer...... 50

5.3 Dickson Charge Pump Pacer - Schematic...... 51

5.4 Dickson Charge Pump - Transient Simulation...... 52

5.5 Dickson Charge Pump Pulser - Simulation of Pulsing action..... 53

5.6 Dickson Charge Pump Pulser - Corner Simulation (Red=TT Blue=SF Green=SS)...... 54

6.1 MOS-only voltage reference - Schematic...... 57

6.2 Variation of reference voltage as a function of temperature at TT, FF and SS corners...... 59

7.1 Successive Approximation ADC - Binary Comparison Algorithm... 62

7.2 Successive Approximation ADC - System Structure...... 64

2 7.3 Successive Approximation ADC - Transient plot for VIN = 3 VREF .. 66

7.4 Successive Approximation ADC (Modiﬁed structure) - Transient plot

for VIN = VREF (Orange), VIN = 0.75VREF (Red) and VIN = 0.33VREF (Blue)...... 66

7.5 Successive Approximation ADC - Modiﬁed System Structure..... 67

7.6 A 1V Rail-to-rail Comparator - Schematic...... 68

xiii 7.7 Low-Voltage Low-power D-latch - Schematic...... 70

7.8 Low-power level-shifter...... 70

7.9 Dynamic Current Consumption over 100 Clock Cycles...... 72

7.10 SA ADC - Quantized ramp vs. time...... 73

7.11 SA ADC - Output code vs. Input Voltage...... 73

7.12 SA ADC - DNL plot...... 75

7.13 SA ADC - INL plot...... 75

xiv CHAPTER 1

INTRODUCTION

CMOS has enjoyed around three decades of royalty in research till now. BJTs are known to be advantageous in many senses, but CMOS designers have always come up with innovative techniques to match the performance of CMOS designs with that of BJT designs. Although CMOS today seems to meet its end in ultra-high speed systems, owing to insuﬃciently large fT or fMAX , researchers have now found it a new life in low power and low voltage systems. The end applications to such low voltage and low power systems are in bio - medical ICs, wearable devices and green electronics. Fortunately the scaling of device dimensions and the supply voltages prove to be a boon for such applications.

Issues with Low-Voltage and Low-Power

The proliferation of battery - operated systems call for IC designs with miserly power consumption. Reduction in supply voltage is one straight-forward method to reduce power consumption, but leads to a variety of design challenges. The funda- mental questions to be posed at any low voltage design are

1. In what regime, are the transistors biased in?

2. What is the maximum speed or bandwidth of operation?

1 3. How low is the voltage?

The reason behind such questioning is that as the supply voltage decreases, it implicitly means that the input and output signal swings are also limited. The threshold voltage does not scale proportionlly, because of which it becomes diﬃcult to bias a transistor in the saturation regime. When transistors operate in triode region, the resistances become linear or non - linear functions of the input, resulting in input- dependent performance parameters, leading to severe distortion which is unaccept- able by the IC design community. In the sub - threshold regime, minimal current is consumed and maximum gain is attainable, but at the cost of severely degraded bandwidth. Although this might initially sound bad, it actually does not when the application is targeted to low frequency applications, like medical ICs.

As for the low-voltage circuit design, Peter Kinget’s group at Columbia Univer- sity has already worked on 0.5 V techniques; Prof. Anantha’s group at MIT have researched that operation at ultra-low supply voltages of 0.3V oﬀers the most eﬃcient operating point for sub-micron digital circuits [1]. These work pave way for future systems operating from 0.5V. Although, this calls for the design of systems operating from a 0.5V supply, it is not very easy to design analog circuits with low power supplies. This thesis limits itself to voltages down to 1 V, as newer process technologies

(65 nm and 32 nm) can tolerate voltages up to a volt. IN analog circuits, the decrease in signal swing should be accompanied by a corresponding decrease in noise, so as to maintain a constant SNR. This decrease in noise is possible at the expense of more power. As a result, low-voltage does not imply low-power in analog circuits, although digital circuits consume lesser power at lower voltages.

2 Thesis Contribution

The challenges described above calls for intelligent circuit design techniques to meet the stringent performance speciﬁcations at low supply voltages. This disserta- tion investigates the challenges in low voltage and low power designs for bio - medical applications but the investigations are not necessarily limited to it.

A set of libraries have been designed for low - voltage and low - power applications on TSMC 0.13um process. A re - investigation of traditional rail - rail designs was carried out, resulting in a simple voltage-mode design of a rail - rail input stage for saturation and sub - threshold regime. A universal figure-of-merit for assessing the performance of rail - rail stages is introduced. Traditional instrumentation amplifiers have been studied and the traditional chopper amplifier has been modified and presented. A new charge pump system for high-voltage pacing has been designed. The custom library also comprises a low - power MOS-only voltage reference and a low - voltage SAR ADC with a charge redistribution DAC. Some of these libraries can be used to develop an end-to-end ECG/EEG/EMG recording system.

Chapter 2 provides a brief overview of bio - signals and bio - signal acquisition systems.

Chapter 3 delves into the theory of designing rail - rail input stages and describes the 1V rail - rail operation ampliﬁer design. The new ﬁgure of merit is also explained in this chapter.

Chapter 4 describes the design of a chopper ampliﬁer, using passive mixers and implicit sample - and - hold.

Chapter 5 introduces the design of a Dickson charge pump for the conversion of low - voltage pulses into high - voltage pulses.

3 In Chapter 6, a low - voltage low - power MOS - only reference is designed based on the EKV model and includes explanation of the relevant theory.

Chapter 7 describes the theory and design of a low - voltage SAR ADC.

Concluding remarks and recommendations for future work are given in Chapter 8.

4 CHAPTER 2

BIO-SIGNALS AND BIO-ACQUISITION SYSTEMS

2.1 Introduction

Bio - signals may be broadly classiﬁed as endogenous signals and exogenous sig-

nals. Endogenous signals arise from natural physiological processes, e.g., ECG, EEG,

EMG, respiratory signals, etc. Exogenous signals are those that are applied to the

body externally non-invasively and used to study internal organs, e.g., ultrasound

signals, NMR signals, etc.

2.2 Bio-potentials

Cells within the body are surrounded by a semi-permeable membrane that allows

certain substances to pass through it, while blocking other substances. These cells are

surrounded by body ﬂuids, otherwise known as intercellular ﬂuid, that are electrolytic

in nature; i.e. they contain charged particles called ions. Extremely common ions

found in the human body are the sodium (Na+), potassium (K+), calcium (Ca2+) and chloride (Cl−) ions. Cell membranes permit the ﬂow of K+ and Cl− ions while blocking (Na+) ions. In the process of seeking a balance of charge and concentration, instability occurs in the form of increased sodium concentration outside the cell,

5 making the cell negatively charged compared to the extracellular medium. K+ ions on the other hand tend to balance the electric charge, by moving into the cell, resulting in a higher K+ concentration inside the cell. Electric charge balance and concentration balance do not occur simultaneously. As a result, there exists a higher concentration of positive ions outside the cell, implying that the intercellular ﬂuid has a positive charge on it. Similarly the intracellular ﬂuid is negative in charge. At equilibrium, the concentration gradient of ions results in a charge gradient within the body, resulting in bio-potentials. These bio-potentials are called as resting potentials. Measurement

of these potentials is made from inside the cell with respect to the body ﬂuid and

hence the resting potentials are always measured to be static and negative. Resting

potentials are found to be in the order of -60 mV to -100 mV.

Excitation of a cell changes the characteristics of the membrane. It aﬀects the

ionic permeability of the cell membrane. There is a gush of sodium ions ﬂowing into

the cell, trying to balance the charge inside and outside the cell. In the meanwhile,

K+ ions ﬂow out of the cell to assist in attaining its concentration balance. But

Na+ ions move faster than the K+ ions resulting in the cell potential turning out

to be positive. This potential is called the action potential, which is of the order of

+20 mV. Once concentration equilibrium is reached, ionic currents (excitation) are

no longer present. The cell membrane reverts back to its semi-permeable condition,

and Na+ ions are blocked inside the cell. But by the process of sodium-potassium

pumps whose theory is not very well known, the K+ and Na+ ions move against the

concentration gradient (low concentration to high concentration) at the expense of

ATP energy. The Na+ ions are now pushed out of the cell, and the cell attains its

resting state. Figure 2.1 shows a typical waveform of the cell potential.

6 Figure 2.1: Cell Potential - Transient Waveform

7 Excitation of a single cell results in ﬂow of ionic currents which in turn can excite neighboring cells. As a result, a ﬂow of action potential can be seen. The rate of

flow of action potential differs for different cell fibers. Every cell exhibits a transient waveform as shown in Figure 2.1, if the cell potential could be measured. But in most cases, measurements are done non-invasively, where surface potential of a group of cells is measured. The exact method by which the cell potential manifests as a surface potential is unknown, but scientists have measured surface potentials of the muscular tissues (EMG - electro-myogram), the brain tissue (EEG - electro-encephalogram), the cardiac potentials (ECG - electro-cardiogram), potentials of the ocular tissue

(EOG - electro-oculogram), etc.

These transient surface potentials provide innumerous information regarding the tissue functions. For example, the ECG waveform provides information about the pumping of the heart. Each peak of the ECG waveform is of diﬀerent amplitudes, and the measure of each peak and corresponding time interval explains the functionality of the heart.

From a circuit or system designer’s point of view, all that matters is that the waveforms of these signals carry a lot of information and all of this must be preserved in a sensing system. These surface bio-signals occupy a small bandwidth within tens of kilohertz, and are of extremely small amplitudes. Figure 2.2 shows the spectra of the surface bio-signals.

2.3 Bio-signal acquisition systems

Bio-signals are acquired by means of electrode-electrolyte interfaces. The use of electrolytes reduces the resistance of the skin greatly. Impedance of dry skin

8 Figure 2.2: Spectra of bio-signals

9 Figure 2.3: Electrode-Electrolyte Interface

is 93 kΩ/cm2, while that of electrode gel on skin is 10.8 kΩ/cm2. On the other

hand, invasive electrodes lead to much reduced resistances of about 200 kΩ/cm2.

Commonly used electrode-electolyte interfaces are silver (Ag) electrodes in aqueous silver chloride (AgCl). Silver chloride is usually available as a gel which is applied on the body, before placement of an electrode. With a smaller electrode surface, a more area-speciﬁc biosignal is acquired. But small area of cross-section of the electrode by itself results in large resistance, making the system diﬃcult to design, and sometimes designed with compromise. Such interfaces may be modeled electrically as shown in

Figure 2.3. EA is the half-cell potential of the interface. RS is the resistance of the

electrolyte and CINT and RINT together represent the impedance of the electrode-

electrolyte interface. Owing to ohmic losses at this interface, the acquisition system

is expected to have extremely high input impedance. Such high input impedances

are easily guaranteed by a MOS input stage at low-frequencies.

Bio-signal acquisition systems generally comprise a front-end ampliﬁer, more com-

monly referred to as an instrumentation ampliﬁer, followed by a programmable ﬁlter,

sometimes a programmable gain ampliﬁer and ﬁnally an analog-digital converter. Of

all these, the front end instrumentation ampliﬁer is the most important block and

10 also consumes a lot of power. Further the noise contribution of this stage dominates

the total noise of the system, as explained by the Friss’ formula. For this reason,

various architectures have been attempted in the literature, for good noise and power

performance. Some major types of instrumentation ampliﬁers are viz.; Three op-amp

instrumentation amplifier, Switched-capacitor amplifiers and Chopper amplifier.

2.3.1 Three-Opamp Instrumentation Ampliﬁer

Figure 2.4 shows the three op-amp instrumentation ampliﬁer. This ampliﬁer com-

prises seven resistors in total, where RG is usually oﬀ-chip and is used to set the gain

of the ampliﬁer. The output voltage for arbitrary values of resistances is given by

Equation (2.2). 2R R5 R3 + R5 − VO = 1 + 1 + VIN − VIN (2.1) RG R4 R2 + R3 R4

If R2 and R5 were equal, and R3 and R4 were equal, then the diﬀerential gain of

the amplifier is given by VO 2R R2 + − = 1 + (2.2) VIN − VIN RG R3 The second stage of this instrumentation amplifier is a conventional differential amplifier with an input resistance of R4 + R3. The first stage comprising two opamps

acts as a buffer with infinite input impedance. The gain of this buffer may be tuned

by varying the value of RG. We see that there is just one resistor that sets the gain

of this instrumentation ampliﬁer. Tunability of this resistance may be achieved by a

potentiostat, or a switched resistor (binary)string. Change in the value of the resistor

RG increases the diﬀerential mode gain, but leaves the common mode gain of the

buﬀer unaﬀected, thus resulting in large values of Common Mode Rejection Ratio

(CMRR).

11 Figure 2.4: Three-Opamp Instrumentation Ampliﬁer

If R2 and R3 were made equal, then the diﬀerential gain would be

2R AV = 1 + (2.3) RG

When the resistors R2−4 are not matched, the CMRR gets affected greatly, and may be compensated by manually tuning R2. The key features of this amplifier are its high differential gain, high input resistance and high CMRR. Finite gain and bandwidth of the operational amplifiers affect the performance of the instrumentation amplifier greatly in terms of the overall gain obtained, bandwidth reduction due to additional poles, and offset errors. This design also suffers from noise due to resistors. Furthermore, it requires the matching of six resistors, which is not so easy

12 to guarantee. Owing to the presence of an oﬀ-chip element, RG, this does not qualify

as a suitable candidate for implantable chips.

2.3.2 Switched-capacitor Ampliﬁers

Moving our focus on to switched capacitor ampliﬁer, it is well suited for low-

frequency applications. Switched-capacitor ampliﬁers work on the principle of con-

servation of charge. The input signal is sampled and stored in capacitors. The charge

stored in a capacitor is transfered on to another capacitor, by the use of an opera-

tional ampliﬁer. Such an operation of charge transfer from one capacitor to another

results in amplification. Switched-capacitor amplifiers also exhibit implicit offset can-

cellation.

The operation of the switched-capacitor ampliﬁer takes place in two steps: SAM-

PLE phase and the AMPLIFY Phase. Consider the circuit shown in Figure 2.5. In

the SAMPLE phase, switches 1 are closed, and switches 2 are open. The input signal

is sampled on to capacitor CI . Consider that the other plate of CI is connected to

VOFFSET . Hence the charge stored in capacitor CI is given by

QCI = CI (VOFFSET − VIN ) (2.4)

QCF = CF (VOFFSET − 0) (2.5)

During the amplify phase, switches 1 are open and switches 2 are closed. The charge stored in the capacitors are conserved, and the new charges stored in the capacitor are

QCI = CI (VOFFSET − 0) (2.6)

QCF = CF (VOFFSET − VOUT ) (2.7)

13 Figure 2.5: Switched-Capacitor Ampliﬁer

14 From the charge conservation principle, total charge in the capacitors during SAM-

PLE and AMPLIFY phase are equal. Therefore,

QCI + QCF |SAMP LE = QCI + QCF |AMP LIF Y (2.8)

CI (VOFFSET − VIN ) + CF VOFFSET = CI VOFFSET + CF (VOFFSET − VOUT ) (2.9)

CI (−VIN ) = CF (−VOUT ) (2.10)

VO CI AV = = (2.11) VIN CF It is worthy to note that the amplifier offset has been cancelled, and that the gain of the amplifier is positive. This is because, the input is sampled on one plate of the capacitor, CI . In the amplify phase, this plate is grounded, and the other plate which is now at −VIN is applied to the negative terminal of the opamp, resulting in another

1 inversion. This amplifier is also used to cancel the f noise which at low frequencies resembles the offset of the amplifier, at the cost of inreased thermal noise, which is limited by the minimum value of capacitance. As any switching circuit, this class of amplifiers also suffer from charge injection and clock feed-through errors. Moreover, the effect of sampling results in the need for a front-end anti-aliasing filter, thus increasing complexity, or rather increased power. The switched capacitor amplifier also has a minimum clock frequency of operation determined by the amount of leakage current.

2.3.3 Chopper Ampliﬁer

The third kind of amplifier to be discussed is the chopper amplifier, where a signal is chopped to a high frequency prior to amplification, i.e. the input signal is translated to a higher frequency, known as the chopper frequency. The chopped

15 signal is then fed to the amplifier. The output of the amplifier contains the amplified

signal, low frequency noise, and the DC oﬀset of the ampliﬁer. The output of the

ampliﬁer also has a chopper. As a result, the signal is brought back to baseband and

the low-frequency noise and the DC oﬀset get translated to the chopper frequency.

Let the input signal be denoted by x(t) and the chopper frequency be denoted as

fCHOPPER.

xchopped(t) = x(t) ∗ cos(2πfCHOPPERt) (2.12)

Let n 1 denote the flicker noise of the amplifier, and VOF F SET,AMP denote the f amplifier’s input-referred offset. The input of the amplifier is given by

VIN,AMP = xchopped(t) + n 1 (t) + VOF F SET,AMP (2.13) f

Let the gain of the ampliﬁer be A. The output of the chopper ampliﬁer is given

by,

VOUT = A.VIN,AMP .cos(2πfCHOPPERt) (2.14)

h i VOUT = A. xchopped(t) + n 1 (t) + VOF F SET,AMP .cos(2πfCHOPPERt) (2.15) f

A A V = x(t) + .x(t).cos(4πf t) OUT 2 2 CHOPPER h i +A. n 1 (t) + VOF F SET,AMP .cos(2πfCHOPPERt) (2.16) f

We notice that the low-frequency noise and the amplifier DC offset (last term in Equation (2.16)) are translated to the chopper frequency. A low pass filter may be used to filter out the translated noise and the DC offset and the 2fCHOPPER

16 component of the signal. Figure 2.6 illustrates the chopper ampliﬁcation technique with associated signal spectra at each stage.

Choice of Chopper Signal Frequency

The choice of the chopper signal determines the amount of reduction in ﬂicker noise contribution at the output.

• Chopper frequency is chosen greater than twice the input signal bandwidth,

so as to prevent aliasing of the signal. Although not commonly mentioned in

textbooks, it also holds good as the minimum frequency of the carrier signal in

amplitude modulation technique.

fCHOPPER > 2BSIG (2.17)

• Chopper frequency should also be chosen to be greater than the frequency

f 1 at which thermal noise and ﬂicker noise are equal. f =T hermal

fCHOPPER ≥ f 1 (2.18) f =T hermal

• Translated signal should fall within the bandwidth of the ampliﬁer.

fCHOPPER + BSIG ≤ BAMP LIF IER (2.19)

1 • Assuming flicker noise to be a function of f , if fCHOPPER is M times the input signal bandwidth, then the chopper amplification technique offers a 10log(M)

dB reduction in ﬂicker noise as compared to traditional ampliﬁcation technique.

17 Figure 2.6: Chopper Ampliﬁcation Technique

18 2.3.4 Variants of the Chopper Ampliﬁer

The conventional chopper amplifier needs a filter at its output to filter out the high frequency signal. Any filter design is known to be complex and it makes great sense to avoid complexity and make the design procedure simpler. From the discussion so far, we have seen that the chopper signal results in two different versions of the original signal; one at baseband and the other at 2fCHOPPER. Assuming a square wave was used, a polar square wave to be specific,

x(t) × square(t) × square(t) = x(t) (2.20)

As a result, there does not exist a 2fCHOPPER component at the output. On the contrary, the square wave having infinte number of harmonics, results in infinite versions of the flicker noise tail leaking into the baseband. But a source of comfort is the fact that the infinite scaled sum of flicker noise tail is convergent and finite.

If an infinitely large fCHOPPER was used, and the tail of the flicker noise equals the thermal noise floor, say Sthermal(f) which is expressed as power spectral density.

Total noise at baseband is given by,

1 1 1 Noise at baseband = S (f) ∗ 1 + + + ... thermal 32 52 72

∞ X 1 = S (f) ∗ (2.21) thermal (2n − 1)2 n=1 3 π2 = S (2.22) 4 6 thermal

The proof for Equation (2.22) is given in Appendix A and is well known as the

Basel problem. If a sinusoidal chopper was used, the noise at baseband would have

19 been merely Sthermal(f). As a result, noise at baseband due to a square-wave chopper

3 π2 is times the noise due to a conventional chopper, which equals about a 0.9 dB 4 6 increase in noise and is not much of an issue. On the other hand, the need for a

ﬁlter has still not been alleviated, as there still exists high frequency noise at all odd

harmonics of the chopper frequency, which have not been removed.

If instead of a square wave, a pseudo-random chip sequence (chopper signal) is

used, it helps to spread the signal at the input. At the output of the ampliﬁer,

another pseudo-random chopper helps to de-spread the signal back to baseband. As

a result of this chopper, the noise and DC oﬀset have spread. From the discussion

in the previous section, we see that the use of a polar square-wave (which is very

much similar to polar chip sequences) helps to retrieve the signal without generating

any other high-frequency components of the signal itself. Although the total noise

over inﬁnite bandwidth still remains constant before and after spreading, the low-pass

characteristics of any subsequent stage, most likely a pre-ampliﬁer or sample-and-hold

of an ADC will integrate the noise over a ﬁnite bandwidth, thus reducing the total

noise contribution. It should not be forgotten that the spreading brings down the noise level. In the case of a pseudo-random chopper, the spread is a function of the length of the chip sequence, and the pseudo-random chiprate. The chip sequences are easily generated using Linear Feedback Shift Registers [2].

Choice of PN sequence as chopper

An interesting thing to consider is the choice of the PN sequence. The longer the PN sequence, the lesser correlation does it exhibit to any random PN sequence generated.

20 • A Linear Feedback Shift Register (LFSR) of length N, can generate 2N − 1

combinations of N-bit sequences, excluding the all-zero state.

• A Maximum-Length sequence (M-sequence) of PN codes has a length 2N − 1,

implying the LFSR runs through all possible combinations of N-bits.

• The Maximum-Length sequence contains 2N−1 occurences of high (or +1) and

2N−1 − 1 occurences of low (or -1). As a result, the average value of the M-

sequence (MLSDC ) is

(+1) 2N−1 + (−1) 2N−1 − 1 MLS = DC 2N − 1 1 = (2.23) 2N − 1

Thus we see that the increase in the length of the sequence improves the DC

performance of the chopper ampliﬁer.

21 CHAPTER 3

LOW-VOLTAGE AMPLIFIER WITH RAIL-TO-RAIL INPUT STAGE

3.1 Introduction

With the past couple of decades seeing a very steep growth in the VLSI industry, designs operating with a supply voltage of 15 V are now being carried out at 1 V and even lesser. The channel length has also seen a tremendous decrease from 2 um processes to 90 nm and 65 nm processes. Scaling in the MOS threshold voltage has unfortunately not been propitious to the scaling in supply voltage. Hence, there is a restricted input swing. As a result, there is a need for amplifiers to operate with rail-to-rail inputs [3]. Although the rail-to-rail operation is possible by means of a complementary differential pair [3], the effective transconductance does not remain constant. A number of techniques have been proposed to make the transconductance of the circuit, constant over the entire input range [4,5,6,7,8,9, 10, 11, 12, 13].

A survey of existing constant transconductance imput stages was done to highlight the short-comings of the approaches. A new voltage-mode design technique for rail- to-rail input stages is introduced that alleviates circuit complexity. Considering the fact that rail-to-rail operational ampliﬁers are now becoming an unavoidable building

22 block in low-voltage design, it is worthwhile to have a ﬁgure-of-merit to quantify

the overall performance of all rail-to-rail input stages, and rank the rail-to-rail input

stage, accounting for the complexity in design speciﬁcations.

3.2 Low-Voltage Techniques for Ampliﬁer Design

Low-voltage and low-power design may be achieved using devices operating in sub-

threshold regime, or by the use of bulk-driven transistors, or by cascading circuits

instead of cascoding. The bulk-driven techniques have been prevalent over the last

decade, but they oﬀer poor noise performance as compared to gate-driven circuits.

The bulk-driven transistor has a transconductance of gmb as compared to the gm

oﬀered by a gate-driven transistor. gmb is lesser than the gm as ﬂuctuations at the bulk induce the channel much lesser as compared to those at the gate. The drain noise current of the transistor is given by,

2 ind = 4kT γgm∆f (3.1)

The gate-driven equivalent input-referred noise is,

2 2 ind eng = 2 gm 4kT γ∆f = (3.2) gm

On the other hand, the bulk-driven equivalent input-referred noise is,

i2 e2 = nd nb g2 mb 4kT γg ∆f = m (3.3) g2 mb

The occurence of gmb in the denominator of the bulk-driven input referred noise makes it larger compared to the gate-driven input referred noise. Although, the bulk-driven

23 technique has the potential to improve design at lower voltages, it performs badly in

terms of the total noise contribution.

An other method to achieve larger, rather rail-to-rail input swings at low-voltages

is by using a complementary diﬀerential pair [3]. But the simultaneous operation of

the NMOS and PMOS input pairs over certain voltages, makes the eﬀective transcon-

ductance to vary over the entire input common-mode range. The subsequent section

will discuss the rail-to-rail ampliﬁer in detail, and the techniques so far used to obtain

constant transconductance.

3.3 Rail-to-Rail Ampliﬁer

The NMOS-input diﬀerential pair can take inputs from a certain value above VSS all the way up to a certain value above VDD. The PMOS-input diﬀerential pair can take inputs from a certain value below VSS all the way up to a certain value below

VDD. Combining both of them, an overlapping range of common mode voltages is obtained, resulting in rail-to-rail operation, as shown in Figure 3.1. The overlapping of the common mode ranges significantly affects the performance of the circuit. At lower input voltages, NMOS pair is switched off, and PMOS pair alone conducts. The

total transconductance is gmp . At higher input voltages, when PMOS pair is switched

oﬀ, the total transconductance is gmn . In the overlapping range, the transconductance

is gmn + gmp . In cases where gmn and gmp are designed to be equal, we see that there is a 100% increase in transconductance when the common mode ranges overlap. As a result, the gain and unity-gain frequency vary with common mode voltage. This becomes an issue of concern, while compensating rail-to-rail operational ampliﬁers or in gm-C integrators.

24 Figure 3.1: Rail-to-Rail Ampliﬁer : Contribution of Input Swing due to NMOS and PMOS input diﬀerential pair

3.3.1 Existing techniques to obtain Constant-gm input stages

With the actual input stage comprising a total of six transistors (four input transistors, two transistors for sourcing and sinking current), an additional two to ten transistors are required in order to achieve constant rail-to-rail transconductance. In

[4], a 1:1 current mirror is used to replicate the Ip and In. This technique has previously been attempted in case of bipolar transistors [5]. But the limitation of this method in MOS input stages is that, it works only for input transistors in the weak- inversion mode, as it helps to maintain the sum of PMOS and NMOS bias currents a constant. The same work [4] discusses a 3:3 current mirror to obtain constant gm in case of strong-inversion operation and reports a 16% variation in gm over the entire input common mode range. This work [4] also senses the diﬀerential pair source node to re-bias the circuit currents and reports a transconductance variation of 5% over the entire input common mode range. Another design [6, 10] that is reported to be less

25 sensitive to weak inversion mode makes use of MOS trans-linear circuits to guarantee

the sum of the square root of bias currents a constant. The use of current-mode

min/max circuits to realize constant gm input stages was reported in [7,9]. In this

work, for lower common mode voltages, the eﬀective transconductance is gmp and

for mid-range and higher common mode voltages, the eﬀective transconductance is

max(gmn , gmp ), but reports a 7% variation in gm for strong inversion, and a 20%

variation in gm for weak inversion transistors. All of the designs discussed so far de-

mand the transconductance parameters, Kn and Kp to be equal. Sakurai and Ismail

[8] report a constant-gm input stage design that accounts for mismatch in Kn and

Kp. It uses current monitor circuits to monitor the value of In and Ip and reports

a 10% deviation in transconductance over the rail-to-rail common mode range. Lin

et al. [11] reports current min/max selection circuits again, but also accounts for mo-

bility variations and mismatch in Kn and Kp in its design, making it more robust for low-voltage applications. All of the techniques discussed so far, achieve satisfactory constant gm with complex additional circuitry, resulting in increased chip area and power consumption. Wang et al. [12] introduces a rail-to-rail CMOS input stage with the tail currents transition regions overlapped, by using a pair of DC level shifters and reports a transconductance variation of ± 5%. In [13], a novel feed-forward canceling

section that produces exactly the same variations in transconductance and current

as the input stage is designed, whose output currents are subtracted from the output

currents of the input stage, resulting in constant gm over all regions of operation. It

reports a transconductance variation of around ± 4%. Techniques so far mentioned

have one thing in common - All of them operate, or rather process currents. This

26 might be the major reason for obtaining diﬀerent characteristics for transistors in weak inversion and strong inversion.

3.4 Voltage-Mode Design of a Rail-to-Rail Input Stage

In the current-mode technique, for weak inversion transistors, the sum of the

PMOS and NMOS bias currents is required to be constant, and in strong inversion, the sum of the square-root of PMOS and NMOS currents is required to be constant. It is also worthwhile to note that the saturation voltage of the transistor is proportional to drain current in weak inversion, and to the square-root of the drain current in strong inversion [14]. This reduces the problem to making the sum of the saturation voltages a constant. If some sort of voltage-mode processing could be used, similar performance could be obtained for input transistors of any operating regime.

The source nodes of the PMOS and NMOS differential pairs are labeled in Fig- ure 3.1 as VX and VY respectively. In addition, Figure 3.2 indicates their variation with the input common-mode voltage and also identifies the transition points of operation of the transistors. It assumes a load with infinite dynamic range, because of which the source nodes VX and VY continue to increase linearly with input common- mode voltage. If by some sort of means, the regions B and C were made to coincide, the common mode ranges would not overlap, and rail-to-rail operation with constant transconductance operation would be achieved, as shown in Figure 3.3. As the input common mode voltage (VCM ) is increased, region ’B’ occurs approximately when VY

equals drain source voltage of the current sink (VDSN ). Region ’C’ occurs approxi-

mately when VX equals (VDD − VSDP ), where VSDP is the source-drain voltage of the

PMOS current source. Thus, for nodes B and C to overlap, we may arrive at the

27 Figure 3.2: Node voltages VX and VY and eﬀective transconductance as a function of the input common-mode voltage

28 Figure 3.3: Node voltages VX and VY and eﬀective transconductance as a function of the input common-mode voltage for the Voltage-Mode technique

condition,

VSDP + VDSN = VDD + |VSS| (3.4)

In order to solve for VDSN and VSDP , we are still in need of one more equation.

By intuition, one might choose the simplest solution, which is,

V + |V | V = V = DD SS = V (3.5) SDP DSN 2 MID

Obviously, this is a valid solution, but the problem is that when VCM = VMID, all the input transistors see an eﬀective gate source voltage of zero, because of which the transconductance at VMID becomes zero! So this eventually leads us to the fact that

29 Figure 3.4: Rail-to-rail ampliﬁer with a folded-cascode load - Schematic

VDSN and VSDP are not only unequal, instead VX is greater than a small value by

VMID and VY is lesser than VMID by a small value. Assuming that the transistors have

to turn ON, the diﬀerence is evidently the transistor’s threshold voltage. Hence, VX

should be a |VTP | greater than VMID, and VY should be VTN lesser than VMID. This

can be done by biasing the current source/sink transistors to achieve such voltages

across them. Figure 3.4 shows a rail-to-rail input stage with a folded-cascode load,

biased accordingly to achieve rail-to-rail operation.

In order to account for process variations, the nodes VX and VY may be controlled

by negative feedback loops. Figure 3.5 shows a simple model to set the voltage

at these nodes. Two op-amps connected in unity feedback conﬁguration with one

terminal connected to the diﬀerential pair source node and the other to the desired

30 Figure 3.5: A simple negative feedback model to bias the current source and sink - A behavioral simulation

voltage level (external voltage source or an on-chip transistor node). VCNTRL1 and

VCNTRL2 which set the voltage at VX and VY may be generated by on-chip bias circuitry or external voltage sources. A behavioral simulation using this setup was done.

3.5 Benchmarking Rail-to-Rail Input Stages

Considering the fact that the same design may be carried out in diﬀerent processes and that the process of designing at lower supply voltages by itself is a mammalian task, there is a need to rank a rail-to-rail input stage. For example, a gain of 100 dB is good. But it is much better, when obtained from a design operating with a

1V supply compared to a 3.3 V supply. On similar lines, the major parameters are identified for a rail-to-rail amplifier to benchmark its performance. In principle, this may be applied to any analog building block, provided the critical parameters are identified.

31 Benchmarking Change in Transconductance

The designs [4,5,6,7,8,9, 10, 11, 12, 13] do not have a common ground of

comparison. They were carried out with supplies from 2V to 5V, and in diﬀerent pro-

cesses. Above all, the transconductance variation in each of these designs is reported

as a convenient number. For instance, if the transconductance varies from gm1 to gm2 , and the diﬀerence in variation was ∆gm, the percentage change in transconductance ∆g ∆g ∆g may be reported as m or m or m . Obviously one of them will gm1 gm2 mean (gm1 , gm2 ) be lesser, and will be eventually preferred to be reported. In order to avoid such ambiguity, the denominator should be chosen as the transconductance at mid-supply,

(VDD+|VSS |) VMID = 2 . Mid-supply is chosen since that is generally the DC value of vir- tual ground in most operational ampliﬁer stages. So the transconductance variation of the rail-to-rail input stage may be denoted as the ratio of the change in transconductance to the mid-supply transconductance, as given by Equation (3.6) . Smaller the value of this number, better is the circuit in terms of performance.

∆g Change in Transconductance = m (3.6) gm(VMID)

Benchmarking the Input Common-Mode Range

Although Equation (3.6) captures change in transconductance, it does not tell

anything about the input common mode range achieving that constant transcon-

ductance or variation in transconductance. Greater the input common mode range,

better is the circuit performance. On a similar note, the smaller the supply voltage,

more complex is the circuit design, and hence a ﬁgure-of-merit is introduced as,

∆gm VDD + |VSS| FOM1 = (3.7) gm(VMID) ∆VCM

32 Thus, a lower ﬁgure-of-merit still denotes a better circuit performance.

Benchmarking Power Consumption

When comparing two designs with identical FOM1, it makes great sense to com- pare their power consumption. The design consuming lesser power obviously becomes the favored choice as it eventually results in longer battery life, at the same circuit behavior. So the FOM1 may be multiplied by the total current consumption, to yield Equation (3.8). The interesting thing to note is that the numerator of this metric contains the product of current and VDD + VSS, thus accounting for the power consumption. The unit of this ﬁgure-of-merit, although not important, is ampere.

∆gm VDD + |VSS| FOM2 = I (3.8) gm(VMID) ∆VCM

The FOM2 was calculated for [8] and [12] as 33.3 µA and 9.06 µA respectively.

Appropriate conversion of their reported transconductance variation was done to

obtain their FOM2.

3.6 Simulation Results

The transconductance variation over the entire input-common mode range was

simulated and illustrated in Figure 3.6. The small-signal response was also simulated,

and the frequency response is obtained as shown in Figure 3.7.

33 Table 3.1: Rail-to-Rail Ampliﬁer – Performance Summary

Parameter Performance

Supply Voltage 1 V

Power Consumption 2.9 µW

Gain 76 dB

Unity Gain Frequency 2.8 MHz

Phase Margin 71o

Figure-of-Merit 0.458 µA

Figure 3.6: Simulated transconductance variation as a function of input common- mode voltage

34 Figure 3.7: AC response of the rail-to-rail ampliﬁer

35 Table 3.2: Rail-to-Rail Ampliﬁer – Corner Simulation Performance Summary

Parameter TT FF SS FS SF

Power Consumption 2.9844 µW 3.23207 µW 2.87499 µW 2.9896 µW 2.98179 µW 36

Gain 76.987 dB 72.115 dB 84.1491 dB 74.905 dB 79.332 dB

Unity Gain Frequency 1.8417 MHz 2.4 MHz 1.0445 MHz 1.7358 MHz 1.9495 MHz

Phase Margin 71o 76.97o 61.24o 73.84o 72.37o CHAPTER 4

LOW-VOLTAGE CHOPPER AMPLIFIER

4.1 Introduction

Bio-signal acquisition systems have been explained in Chapter 2, including a treat-

ment of chopper ampliﬁers. This chapter explains the design and simulation of the

chopper ampliﬁer, operating from a 1V supply.

4.2 Chopper

The chopper comprises of MOS switches, connected in a cross-coupled fashion.

These switches take a diﬀerential input and a diﬀerential chopper signal. The chopper

signal swings from VSS to VDD and drives the switches in cut-oﬀ and triode region. The advantage of this circuit is its robustness to the non-linearity of the MOS switches.

The schematic of the chopper is shown in Figure 4.1

The transistors may be considered to be operating in triode region and may be modeled using the EKV transistor model [14], where the bulk is used as the reference node. Using this model, the drain current in a transistor operating in triode regime is given by, K I = (V − V − αV )2 − (V − V − αV )2 (4.1) DS 2α G TO S G TO D 37 Figure 4.1: Chopper – Schematic

where VG, VS, VD and VTO represent the gate, source, drain and threshold voltages of the MOS transistor respectively, measured with respect to the bulk. α denotes the

non-linearity of the threshold-voltage along the channel. An α of 1 implies that the

threshold voltage increases linearly along the channel.

Referring to Figure 4.1, let the drain voltages of all four transistors be at a pseu-

doground named V ∗. Using the above equation,

K I = (V − V − αV )2 − (V − V − αV ∗)2 (4.2) 1 2α C1 TO IN1 C1 TO K I = (V − V − αV )2 − (V − V − αV ∗)2 (4.3) 2 2α C2 TO IN1 C2 TO K I = (V − V − αV )2 − (V − V − αV ∗)2 (4.4) 3 2α C2 TO IN2 C2 TO K I = (V − V − αV )2 − (V − V − αV ∗)2 (4.5) 4 2α C1 TO IN2 C1 TO

38 By subtracting I1 and I4, we obtain,

I1 − I4 = K(VIN1 − VIN2 )[−2(VC1 − VTO ) + α(VIN1 + VIN2 )] (4.6)

Similarly,

I2 − I3 = K(VIN1 − VIN2 )[−2(VC2 − VTO ) + α(VIN1 + VIN2 )] (4.7)

The diﬀerential output current is thus given by,

IOUT = I1 − I4 − (I2 − I3) (4.8)

= −K(VIN1 − VIN2 )(VC1 − VC2 ) (4.9)

The negative sign indicates the reversal in the direction of the output currents.

The same treatment is applicable to PMOS transistors too. It is also worthy to note that the output diﬀerential current is not inﬂuenced by the nonlinearity of the transistor’s threshold voltage along the channel. This is true even when the transistors are biased in the saturation regime. In this case, we switch the transistors between

cut-oﬀ and triode region. In other words, the inputs are directly loaded onto VO1 and

VO2 when VC1 is high, and are swapped onto VO2 and VO1 when VC1 is low.

4.2.1 Design Methodology

Since the transistor operates as a switch, it is important that the ON resistance of the switch is as minimum as possible. The ON resistance, RON of the switch is given as, 1 RON = 0 W (4.10) K L (VGS − VT − VDS) Monolithic switches suﬀer from eﬀects like charge injection and clock feedthrough, the major cause being the gate-source capacitance and the gate-drain capacitance.

39 When the gate-voltage of an NMOS goes from a high to a low, the slope of this transition gets diﬀerentiated by the gate-source (or gate-drain) capacitance, into a current that removes charge from the load capacitance. As a result, the ﬁnal charge stored on the capacitor is lesser than the input. On the contrary, PMOS capacitors result in injection of charge into the capacitor, thereby increasing the output voltage as compared to the actual value. Thus, the voltage error is positive in a PMOS, and negative in an NMOS. It is also observed that a larger load capacitor reduces the amount of charge injected, but limits the bandwidth of the system.

On the contrary, an NMOS and a PMOS placed in parallel to form a transmission gate, alleviate the issue of charge injection to a small extent. The positive charge injection of the PMOS transistor, may be canceled by the negative charge injection of the NMOS transistor, for properly chosen values of NMOS and PMOS aspect ratios.

However the injection is cancelled only for one particular value of VIN .

Considering the structure shown in Figure 4.1, it is seen that for the differential inputs, the transistors of similar paths are triggered at the same instant of time, resulting in the same injection (positive or negative) in both the output arms. The differential way of sensing the inputs, implicitly offers charge injection and clock feedthrough cancellation. However, the input dependent injection remains uncanceled. There does exist asymmetry in the differential paths, leading to some finite input-independent injection and feedthrough errors. The clock-feedthrough spikes on the output arm that act as high frequency components are easily filtered by the finite bandwidth of the main amplifier. So the main criteria in choosing the transistor sizes is the ON resistance, which demands minimum L, and a large W. A sufficiently large W is chosen for this purpose.

40 Figure 4.2: Chopper Ampliﬁer – Schematic

The advantage also comes if one of the clocks could be removed, and if only one clock was used. This is possible if the second path uses PMOS transistors instead of

NMOS. Thus a single-phase clock may be used, avoiding unnecessary complexity in a clock generation. The schematic of such a chopper is shown in Figure 4.2.

4.3 Main Ampliﬁer

The main amplifier was chosen to be a conventional current-source loaded five- transistor differential pair, with PMOS input transistors. PMOS was chosen specif- ically because of its better flicker noise performance compared to its NMOS coun- terpart. A popular explanation for flicker noise being less in PMOS devices is that

PMOS transistors are buried in separate wells in an n-well process. The drain noise current of a transistor is given by,

2 8kT gm(1 + η) Kf ID 2 ind = + 2 ∆f (A ) (4.11) 3 fCOX L

41 where

∆f = a small bandwidth of interest at a frequency f

gm = the small-signal transconductance of the transistor (mS) g η = m gmbs k = Boltzmann’s constant(m2kgs−2K−1)

T = temperature (K)

Kf = the ﬂicker noise coeﬃcient (F-A)

f = frequency (Hz)

Mean square noise of the transistor, reﬂected at its gate is given by [15],

2 2 in 8kT (1 + η) Kf 2 en = 2 = + 0 ∆f (V ) (4.12) gm 3gm 2fCOX W LK

Equation (4.12) is believed to contain the oversimpliﬁed version of the ﬂicker noise model.

The sizes of the transistors were chosen large so as to minimize the ﬂicker noise contribution.

4.4 Simulation Results

The transient simulation of the chopper ampliﬁer is shown in Figure 4.3. The main ampliﬁer operates from a supply of 1 V, while the chopper transistors are gated at 1.2V. Bootstrapping may be adopted, but is not necessary owing to very small input signal swings. The increase in gate voltage of the chopper results in increased feedthrough at the output, and also results in larger signal swing. If the subsequent

42 Figure 4.3: Chopper Ampliﬁer – Transient Simulation

43 Figure 4.4: Chopper Ampliﬁer – Gain variation with chopper supply

44 Table 4.1: Chopper Ampliﬁer - Eﬀect of Chopper supply on Gain

Chopper Supply Gain 1.2 32 dB 1.8 33 dB

circuit samples at the same rate as the chopper, and using non-overlapping clocks with appropriate phase shifts, then the feedthrough spikes may be removed. Table

4.1 shows the chopper ampliﬁer gain variation with respect to the supply. Figure 4.4 shows the variation in the output voltage for various chopper supplies. It is worthy to note that larger gating voltages result in larger clock feedthrough

45 CHAPTER 5

DICKSON CHARGE PUMP

5.1 Introduction

Pacemakers, brain and retinal stimulators require high voltages for stimulation.

Low voltage medical solutions need a conversion from low-voltage to high-voltage in order to be able to integrate with stimulators. The pursuit of a technique to obtain higher voltages from lower voltages has existed ever since man discovered electricity. A variety of charge pumps exist in the literature that can serve the purpose of obtaining larger voltage pulses from low-voltage pulses, by charge storing techniques. Charge pumps have been in existence for a very long time, and have been widely used in

EEPROM and ﬂash memories. Subsequent sections provide a treatment of charge pumps and delve into the Dickson charge pump topology.

5.2 Charge Pump - The basic theory

Charge pumps generally consist of capacitors that are used as energy storage elements. A certain amount of charge is stored in a capacitor to develop a voltage across it. Let us consider a capacitor C1 charged to VDD. The total charge on the

46 capacitor is now,

QC1 = C1VDD (5.1)

If the same charge is transferred onto a capacitor C2 to develop a voltage VO

across it, then

QC2 = QC1 (5.2)

C1VDD = C2Vo (5.3)

C1 Vo = VDD (5.4) C2

Storing the same amount of charge onto a smaller capacitor develops a larger voltage across it. So the gain in voltage obtained is a function of the ratio of the capacitors. For a 64x increase in voltage, the ratio of capacitors is to be 64:1. In reality, the error in the ratio of the capacitors is proportional to ratio of capacitors itself.

So it becomes difficult to maintain a single pair of capacitors with their capacitances in the ratio 64:1. As a result, the boosted voltage from a small ratio capacitor may again be stored on another capacitor, and thus the final voltage may be obtained as six cascaded sections of 2:1 capacitors. It should be noted that the charge should flow in one direction only, so every cascaded section contains diodes to restrict the flow of charge backwards through the sections. So the concepts of charge sharing, storing and transferring phenomena are together involved in this technique. Although cascaded sections theoretically help to obtain higher voltages, there exists a drop across the diodes, which result in longer cascaded sections than required to obtain a specific boost in voltage.

47 Figure 5.1: Dickson Charge Pump - Transistor Implementation

5.3 The Dickson Charge-Pump

Figure 5.1 shows an n-stage transistor implementation of Dickson charge pump.

The transistors are connected with their gates and drains connected, so as to act as diodes and provide a uni-directional charge ﬂow. CLK and CLK are out of phase by

o 180 and oscillate between 0 to VDDLOW . C1 to C4 are the bootstrapping capacitors which help to couple charge from one stage to another.

In one phase of the clock, the ﬁrst capacitor charges to VDDLOW , when its bottom plate is at GND. During the next phase, the bottom plate raises to VCLK , as a result

of which the top plate raises to VDDLOW + VCLK . This eventually charges the next

capacitor, to VDDLOW + VCLK . On the next clock phase, bottom plate of the second

capacitor becomes VCLK as a result of which the top plate reaches VDDLOW + 2VCLK and so on. Thus during every clock cycle, each capacitor keeps charging, and at the

th n stage, a voltage of VDDLOW + nVCLK is obtained. It is assumed that the change of VCLK on one plate of the capacitor results in the same change on the other plate, and that there is no drop acros the transistor. In reality, this scenario does not exist at all. The diode drop voltage results in a further decrease in output voltage. Stray capacitances due to the transistors, do not reﬂect the same change in voltage on the

48 other plate of the capacitor. For an n-stage charge pump comprising n transistors,

the output voltage reaches,

C IOUT Vo = VDDLOW + n VCLK − VT − − VT (5.5) C + Cp (C + Cp)fCLK

Cp refers to the parasitic capacitance at each node. VT is the threshold voltage of the transistor. It is thus observed that a higher clock frequency results in a higher output voltage.

The other thing to note is that the VT of each transistor is diﬀerent owing to body eﬀect. Assuming a no-load condition, Equation (5.5) may be re-written as,

N X C V = V + V − V − V (5.6) o DDLOW C + C CLK T,i T,N+1 i=1 p

th where VT,i denotes the threshold voltage of the i stage transistor. The threshold

voltage increases with every stage, since every additional stage oﬀers a higher voltage.

5.4 Dickson Charge pump as a Pacer

For the desired application, 1V is the maximum voltage available for the system.

So VDDLOW and VCLK are both chosen to be equal to 1V. A large pump capacitor,

reduces the error signiﬁcantly but at the cost of increased charging or pumping time.

After the last stage, a PMOS transistor was placed so as to connect the output of

the charge pump to the load, for a short time duration. The bulk of the PMOS is

connected to the MOS terminal connected to the charge pump. When the gate of the

PMOS is low (GND), the PMOS is ON. When the PMOS is OFF, the output has to

drop back to GND potential, which is achieved by means of the NMOS transistors,

gated at 0 to VDDLOW . The issue faced here is that in order to switch oﬀ this transistor,

the gate voltage must be atleast greater than a VT less than the charge pump voltage,

49 Figure 5.2: Dickson Charge Pump as a Pacer

or the PMOS remains turned ON. As a result, the entire charge pump is replicated with inverted clocks fed at the output stage, as shown in Figure 5.2. The top path will be referred to as the main path and the bottom path will be referred to as the differential path. The word differential here signifies that the pulsing action is differential. When the differential path PMOS transistor is ON, the output also gates the PMOS transistor in the main path, thus guaranteeing it to be OFF. The input

IN and IN vary between 0 and VDDLOW .

5.5 Simulation Results

The pump capacitors were designed using NMOS varactors as shown in Figure 5.3.

This implementation made it sensitive to the fast NMOS corner. An alternative would be to use PMOS varactors, but this would make the simulation results sensitive to the fast PMOS corner. Hence, NMOS and PMOS capacitors could be used for alternate stages in both the main path and the diﬀerential path. This results in

50 Figure 5.3: Dickson Charge Pump Pacer - Schematic

51 Figure 5.4: Dickson Charge Pump - Transient Simulation

52 Figure 5.5: Dickson Charge Pump Pulser - Simulation of Pulsing action

sacriﬁcing performance at the best corners, for a better performance at the worst- corners. Although this results in a better performance than earlier, the NMOS diodes in the main and the diﬀerential path, still restrict the performance of the structure.

Simulation of the charge pump with the pulser circuitry loaded but unactivated is shown in Figure 5.4. The pulsing action of the charge pump is illustrated in Figure 5.5.

Figure 5.6 shows the corner simulations for the integrated pump and pulser.

53 Figure 5.6: Dickson Charge Pump Pulser - Corner Simulation (Red=TT Blue=SF Green=SS)

54 CHAPTER 6

LOW-VOLTAGE MOS-ONLY VOLTAGE REFERENCE

6.1 Introduction

The demand for lower supply voltages, along with the continuous scaling in technology has also called for low-voltage references. Voltage references are required to be well-deﬁned, with no sensitivity to power supply, temperature and load conditions.

The bandgap reference has proved to be a good design for temperature-independent references, where diodes or bipolar junction transistors are used to generate a ’proportional to absolute temperature’ (PTAT) voltage, which when combined with the

’negative to absolute temperature’ (NTAT) voltage of the bipolar junction drop (VBE) yields a temperature-independent reference voltage. This design although popular, needs a costly BiCMOS process, as the parasitic bipolar transistor in CMOS processes is not always well characterised. As a result, a MOS-only solution has been sought after. On the other hand, the band-gap voltage of Silicon at room temperature is approximately 1.12eV, which limits the minimum power supply voltage to a higher value. Eﬀorts have also been made over the last few years to develop sub-1V voltage references.

55 6.2 CMOS characteristics in Weak Inversion

The MOS in sub-threshold region behaves very similar to that of the bipolar transistor. The sub-threshold current of the MOS transistor is given by [16, 17],

VGS −VTH η VDS −VDS nVt nVt Vt IDSSUB = Io.e .e . 1 − e (6.1) where,

W kT 2 I = µC e1.8 o ox L q

Cd n = 1 + = sub-VTH slope factor Cox η = DIBL coeﬃcient

Equation (6.1) indicates that the operating region must be carefully chosen, and parameters like temperature and aspect ratio must be considered as critical variation or mismatch factors.

The mobility is also a function of temperature, and hence we may write the current,

Io as a function of temperature, with α being a process-dependent parameter, relating the characteristic current to the temperature. Using a temperature To as reference,

T α Io(T ) = Io (To) (6.2) To

Similarly the threshold voltage, VTH may be referred to a temperature, To and may be written as [18],

VTH (T ) = VTH (To) − θ (T − To) (6.3) where θ depends mainly on the doping levels of the substrate.

56 Figure 6.1: MOS-only voltage reference - Schematic

The temperature dependence of the gate-source voltage, VGS may be given as [18],

α T T kT T IDS(T ) VGS(T ) = (VGS(To) + θTo) 1 − + VGS(To) + n .ln To To q To IDS(To) (6.4)

Thus, we see that the VGS voltage of a MOS transistor in weak-inversion exhibits a linear dependence on temperature. To be speciﬁc, the VGS of the NMOS transistor exhibits a negative dependence on temperature. For a PMOS device, the |VGS|

increases linearly with temperature.

57 6.3 MOS-only voltage reference

The previous section reveals that the VGS of the NMOS and PMOS transistors

in weak inversion exhibits a negative and positive linear dependence with temper-

ature respectively. As a result, |VGSP | − VGSN exhibits a positive dependence on

temperature. If this diﬀerence is established across an element that follows the same

positive dependence, a temperature-independent current will be established across

the element. The simplest element that exhibits a positive temperature coeﬃcient

is the resistor. This temperature-independent current, may be mirrored to gener-

ate a temperature-independent current source/sink, or fed into a load, to generate a

temperature-independent voltage reference.

The transistors, M5 and M6 in Figure 6.1 are connected in such a way that the

diﬀerence in their gate-source voltages drop across the resistor, R. Transistors M1−M4

help to force identical currents in the two braches. V I = R R dI 1 dV dR ⇒ = R R − V (6.5) dT R2 dT R dT In order to have a temperature-independent current, dI = 0 dT dV V dR ⇒ R = R dT R dT dR 1 dV = R (6.6) dT I dT If Equation (6.6) is satisﬁed, a temperature independent current ﬂows trough the transistors, as a resutl of which, the gate of M1,2 becomes a temperature-independent voltage.

58 Figure 6.2: Variation of reference voltage as a function of temperature at TT, FF and SS corners

6.4 Simulation Results

The variation of the reference voltage as a function of temperature is shown in

Figure 6.2. The temperature coeﬃcient of the reference voltage at typical simulation conditions was 20.8 ppm/oC. The power consumed by the circuit was 20.4761 nW from a 0.5 V supply.

59 Table 6.1: Low-voltage MOS-only reference – Performance Summary

Temperature Range Voltage Variation

−50oC to +85oC 1.92567 mV

−50oC to +50oC 312.1914 µV

60 CHAPTER 7

LOW-VOLTAGE 8-BIT SAR ADC

7.1 Introduction

Although real-world signals might be analog, analog signal processing means complex circuitry and huge power consumption. As a result, there is a migration into the digital domain, to ease signal processing. Moreover, post-processing techniques like feature extraction, clinical analyses, etc. are easily possible on digital domain.

Various A/D converters do exist in the literature, but the right choice of architecture has to be made with regard to power consumption and low-voltage operation.

Delta-Sigma A/D converters oﬀer very large dynamic ranges at the cost of burning more power. Pipelined ADCs are not so necessary, since the bio-signals considered in this thesis, are of low-frequency. The use of pipelined ADCs for low-frequency bio- applications would instead translate to expensive hardware. SA ADCs win over the other two candidates in terms of less hardware and less power. This chapter discusses the design and simulation of a 1V 8-bit successive approximation ADC.

61 Figure 7.1: Successive Approximation ADC - Binary Comparison Algorithm

62 7.2 Successive Approximation ADC

The successive approximation ADC samples the input on a clock cycle, and re- solves N-bits in N-clock cycles, in an algorithm very similar to the binary search. V V Input is first compred with REF . If it is greater than REF , it is then compared 2 2 V V V V with REF + REF . If not, it is compared with REF − REF and so on. As a result, 2 4 2 4 the input voltage is required to be compared with multiple reference voltages every clock cycle, resulting in the need for multiple reference voltages in the system, making it no different from a Flash ADC. A modification to this algorithm is illustrated in V V Figure 7.1. The input signal is compared with REF . If greater, REF is subracted 2 2 V V from the input and compared with REF . If not, it is simply compared with REF . 4 4 V In the next clock cycle, subtraction (if required) and comparison is done with REF 8 and so on.

The references may be obtained using resistors or capacitors, but the latter is chosen as they maintain better ratios. The charge-redistribution DAC, more simply known as the capacitor array, comprises capacitors whose values are in powers of C C C 2, i.e. , , , and so on. The capacitor array is connected to the comparator, 2 4 8 whose other terminal is connected to a constant common-mode voltage. Initially the input is sampled onto the capacitor, by closing all input sampling switches. Once sampling is done, the input switches are open and the reference and ground switches are connected according to the binary search algorithm. During every clock cycle, the voltage on the other end of the capacitor changes, and tends to settle to the value seen by the other terminal of the comparator, which is the common-mode voltage.

This is illustrated in Figure 7.3. In eﬀect, the concept of an opamp trying to make its

63 Figure 7.2: Successive Approximation ADC - System Structure

64 inputs equal as a result of feedback is taking place, except for the fact that it happens in a sampled time domain.

For an N-bit SA ADC, there are N capacitor arms, implying there are N input switches. At such low-voltages, the sampling switches suffer from huge ON resistances because of the low gate-drive. Bootstrapping techniques are used to sample the input signal, but in this case, it would result in N bootstrap switches, implying more power consumption. The existing architecture is modified by sampling the input signal onto the other terminal of the comparator, as shown in Figure 7.5. The digital logic is accordingly modified, which must only account for an inversion in the opamp terminals. In this case, the process still remains the same, except for the fact that the settled value is different. The capacitor array’s terminal that is connected to the comparator finally settles to the value seen by the other terminal of the comparator, which is the input voltage itself. This is illustrated in Figure 7.4. The digital logic is modeled on Verilog-A and the comparator was designed for rail-to-rail operation and operates from a 1V supply. The reference and the ground switches of the DAC are gated with a higher supply voltage, generated by means of a level-shifter.

7.3 Building - Blocks

7.3.1 Rail-to-Rail Comparator

Comparators are ideally blocks of very huge gains, which may be achieved by cascaded amplifiers. But cascaded amplifiers suffer from multiple poles, which degrade the rise-time and fall-time characteristics. The regenerative latch is a cross-coupled inverter, which results in a positive feedback action, thus providing good rise and fall-time characteristics, and makes a good comparator. The theory and analysis

65 2 Figure 7.3: Successive Approximation ADC - Transient plot for VIN = 3 VREF

Figure 7.4: Successive Approximation ADC (Modiﬁed structure) - Transient plot for VIN = VREF (Orange), VIN = 0.75VREF (Red) and VIN = 0.33VREF (Blue)

66 Figure 7.5: Successive Approximation ADC - Modiﬁed System Structure

67 Figure 7.6: A 1V Rail-to-rail Comparator - Schematic

68 for such comparators are dealt beautifully in Allen and Holberg [19]. The scaling

in voltage demands a rail-to-rail comparator. Similar to the rail-to-rail ampliﬁer,

NMOS and PMOS input transistors are used and they drive the same load structure.

Cross-coupled NMOS transistors are used as the load, so as to provide a regenerative

action. The NMOS loads are directly driven by the PMOS input transistors, while

the NMOS transistors drive the load through a PMOS current mirror. Care should

be taken so that paths through the NMOS and PMOS input transistors, result in the

same phase at the output. The schematic of the rail-to-rail comparator is shown in

Figure 7.6. The signal at the input of the NMOS transistor suﬀers no inversion after

passing through the current mirror, whereas that at the PMOS transistor suﬀers an

inversion. The connection between the drains of transistors M1 and M10 takes care

of the inversion. The drains of M4 and M9 are connected for the same reason. The reset state of this comparator is at GND, with transistors M11 and M12 being the resetting transistors. The output of the comparator is buﬀerred through an inverter.

The output of this comparator is an RZ waveform.

7.3.2 D-Latch

In order to make the output of the comparator latch high or low for the entire clock cycle, a D-latch is used. The schematic of the D-latch is shown in Figure 7.7.

The schematic is basically a modiﬁcation of the circuit, extracted out of the work by Nikolic et al. [20]. The signiﬁcance of this latch is that no clock is required. The clock signal is hidden inside the output of the rail-to-rail comparator and serves the purpose of timing. The D-latch is also provided with a SLEEP mode, so as to reduce power consumption during the idle mode.

69 Figure 7.7: Low-Voltage Low-power D-latch - Schematic

Figure 7.8: Low-power level-shifter

70 7.3.3 Level-shifter

The level shifter, shown in Figure 7.8, was used to convert the low-voltage pulses

(VDDL ) from the digital logic to high-voltage gating pulses to switch the capacitive

DAC array. The level-shifter here assumes a dedicated supply voltage (VDDH ) to achieve level-conversion. A pump may be used for the purpose of level shifting, but is

not necessary since the level shift is not so huge. The conversion of a VDDL to a VDDH is straight-forward and may be easily achieved using two cascaded inverters with diﬀerent supply voltages, and with GND being the intermediate voltage level. The translation of a GND to a GND although being the same potential is not easy, since

in the cascade of inverters, the intermediate node becomes a VDDL , which might not be suﬃcient to turn OFF the subsequent inverter stage. As a result, a bootstrapping

is done in the intermediate stage, where the VDDL is converted to 2VDDL by storing charge in the capacitor C.

7.4 Comparator Simulation Results

The dynamic current consumption was measured at various clock frequencies over

100 clock cycles. At an operating clock frequency of 100 kHz, the dynamic current consumption was a little over 4uA. The plot of the dynamic current consumed by the comparator at select frequencies is shown in Figure 7.9.

7.5 ADC Simulation Results

The entire ADC was integrated with the Verilog-A module and the charge-redistribution

DAC and simulated. A slowly varying input ramp was fed to the ADC, so as to enable the ADC to hit all possible codewords. Figure 7.10 shows the quantized output of

71 Figure 7.9: Dynamic Current Consumption over 100 Clock Cycles

72 Figure 7.10: SA ADC - Quantized ramp vs. time

Figure 7.11: SA ADC - Output code vs. Input Voltage

73 Table 7.1: Successive Approximation ADC – Performance Summary

Parameter Performance

Supply Voltage 1 V

Power Consumption 5 µW

Resolution 8 bits

Maximum Clock Frequency 1 MHz

1 Sampling rate 10 of the clock frequency

INL +0.25 LSB / -0.25 LSB

DNL +0.45 LSB / -0.4 LSB

Oﬀset Error +0.73 LSB

the ADC with respect to time. The data was stored and exported to MATLAB, to reveal the quantizer transfer function as illustrated in Figure 7.11.

Histogram analysis was done on the recorded data, to obtain the INL and DNL of the SA ADC. These plots are shown in Figure 7.13 and Figure 7.12. The speciﬁcations of the designed ADC are summarized in Table 7.1.

74 Figure 7.12: SA ADC - DNL plot

Figure 7.13: SA ADC - INL plot

75 CHAPTER 8

CONCLUSION

The work of this thesis used TSMC 0.13 µm to perform schematic simulation of all circuits. This work presents the ﬁrst attempt of a design of a low-voltage and low-power library of circuits, targeting medical applications. All of the designs are functional at 1 V by simulation.

The design of these circuits on 0.5 µm processes or higher, results in larger supply voltages, which are not capable of being easily generated. The same designs on advanced processes is not necessary, leave alone the issues of reliability, as it only makes the design procedure more complicated. Moreover as previously mentioned, further reduction in supply voltage results in increased leakage energy Calhoun et al.

[1], which becomes a serious issue. Hence, a process technology of 0.13 µm or 0.18

µm seem to be more favorable and convenient for such bio-chips.

8.1 Future Work

The eﬀect of scaling on these designs is an interesting work, as scaling is not easily applicable to analog CMOS circuits. Another extension of this work is the character- ization of these designs for implantable or invasive applications. Bronchoscope is a camera at the end of a tube, which is made to pass through the oesophagus tube, to

76 take pictures of the gastric cells, and the inner walls of the intestines. In such cases, the designs might be required to operate at higher frequencies, with data telemetered from inside the body to a receiver beside the patient bed. The effect of body fluids on the packaging of such devices and their influence on the circuit performance could be studied. Wireless power transfer is also a good area to research, as it requires the modeling of the patient’s body as a communication channel, and involves a great deal of communication theory in it.

77 APPENDIX A

BASEL PROBLEM

Let f(x) = x be a function deﬁned over the interval, x ∈ (−π, π).

The Fourier series coeﬃcient for this function is,

Z π 1 inx an = xe dx 2π −π cos(nπ) sin(nπ) = i − i n n2π (−1)n a = i (A.1) n n

From the Parseval’s identity for the function f(x),

∞ X 1 Z π |a |2 = x2dx n 2π n=−∞ −π

∞ X 1 1 Z π = x2dx n2 2π n=−∞ −π

∞ X 1 π2 2 = n2 3 n=1

∞ X 1 π2 = (A.2) n2 6 n=1

1 1 1 π2 ⇒ 1 + + + + ... = 22 32 42 6

78 Collecting the odd and even terms of the series,

1 1 1 1 1 π2 1 + + + ... + + + + ... = 32 52 22 42 62 6

1 1 1 1 1 π2 1 + + + ... + 1 + + + ... = 32 52 22 22 32 6

1 1 1 π2 π2 1 + + + ... + = 32 52 22 6 6

1 1 3 π2 1 + + + ... = 32 52 4 6

Generalizing the equation, ∞ X 1 3 π2 = (A.3) (2n − 1)2 4 6 n=1

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