United States Patent [19] [11] Patent Number: 4,573,141 Matsukawa [45] Date of Patent: Feb. 25, 198‘

[54] SEMICONDUCI‘ OR MEMORY DEVICE OTHER PUBLICATIONS HAVING TUNNEL Data of an Expert Committee on the Research of Elec [75] Inventor: Naohiro Matsukawa, Yokohama, tronic Computers—the Institute of Electronics an Japan Communications Engineers of Japan——“Possibility c [73] Assignee: Tokyo Shibaura Denki Kabushiki Super High-Speed Computers Using an Esaki ’ Kaisha, Japan Primary Examiner-James W. Mof?tt Attorney, Agent, or Firm-Finnegan, Henderson, [21] Appl. No.: 472,605 Farabow, Garrett & Dunner [22] Filed: Mar. 7, 1983 [57] ABSTRACT [30] Foreign Application Priority Data A semiconductor memory device has at least one men Mar. 8, 1982 [JP] Japan ...... 57-36019 ory which includes ?rst and second tunnel diode connected in series in a forward-bias direction betwee [51] Int. Cl.4 ...... G11C 11/38 ?rst and second power source terminals. The ?rst an [52] US. Cl...... 365/175 second power source terminals are held at constar [58] Field of Search ...... ; ...... 365/ 105, 175, 243 potentials. A switching MOS is connected 2 [56] References Cited one end to a connection point between the ?rst an second tunnel diodes. The potential at the connectio U.S. PATENT DOCUMENTS point between the ?rst and second tunnel diodes is de 3,855,582 12/1974 Roberts ...... 365/203 termined by the potential at the other end of the switcl ing MOS transistor. FOREIGN PATENT DOCUMENTS 2425739 l/1975 Fed. Rep. of Germany ...... 365/175 7 Claims, 4 Drawing Figures

DWLl DWLO WLi WLN MCHPH) Bl-H MClN / ( S l P P e vs V0 [V5 v0 vss v0 1 SENSEAMPLIFIERCIRCUIT

VDz VS vs( VB vs( vovs ( v0 DCOM MCMi MCMP ( MCMtPH) SAC

4,573,143 1 2 each connected to those memory cells MC1(P+ 1) to SEMICONDUCTOR MEMORY DEVICE HAVING MCMN which are arranged in the same row, and word TUNNEL DIODES lines WLl to WLN each connected to those memory cells MC11 to MCMN which are arranged in the same BACKGROUND OF THE INVENTION column. The memory device further includes a sense This invention relates to a semiconductor memory ampli?er circuit SAC which is connected to the bit lines device having tunnel diodes. BL01 to BLOM and also to the bit lines BL11 to BLlM. Two types of random-access memories (RAMs) are The device has dummy cells DC01 to DCOM connected known, i.e., a dynamic RAM and a static RAM. A to the bit lines BL01 to BLOM, respectively and other dynamic RAM has a plurality of memory cells each dummy cells DC11 to DClM connected to the bit lines formed of one MOS transistor and one . A BL11 to BLlM, respectively. The dummy cells DC01 static RAM has a plurality of memory cells each formed to DCOM are connected to a word line DWLO, and the of six MOS or four MOS transistors and two dummy cells DC11 to DClM to a word line DWLl. . The dynamic RAM needs to undergo a data The memory cells MC11 to MCMP, memory cells refreshing operation in order to preserve the data stored MC1(P+1) to MCMN, dummy cells DC01 to DCOM therein. The static RAM cannot be made with a high and dummy cells DC11 to DCIM are each formed of a packing density because each of its memory cells in switching MOS transistor and two tunnel diodes (or cludes many elements. Esaki diodes). Each MOS transistor has its gate con nected to the corresponding word line and its current SUMMARY OF THE INVENTION path connected at one end to the corresponding bit line. An object of the present invention is to provide a Corresponding two tunnel diodes are connected in se semiconductor memory device which need not undergo ries in a forward-bias direction between power source data refreshing operation and which can be formed of a terminals VD and VS. A connection point between the small number of elements. tunnel diodes is coupled to the other end of the current A according to the invention 25 path of the switching MOS transistor. comprises at least one including ?rst and Suppose the word line WLl is made active and the second tunnel diodes connected in series in a forward switching MOS transistor TR1 of the memory cell bias direction between a ?rst terminal held at a substan MC11 is turned on. The potential on the bit line BL01 tially constant potential and a second terminal held at a then changes. The currents ?owing through the tunnel 30 reference potential and a switching means connected at diodes TD1 and TD2 of the memory cell MC11 vary as one end to a connection point between the ?rst and shown in FIG. 2. Speci?cally, the current flowing second tunnel diodes, a bit line connected to the other through the diode TD2 changes as indicated by a solid end of the switching means, a word line connected to line curve and the current ?owing through the diode the switching means for supplying a signal to control 35 TD1 changes as represented by a broken-line curve. the switching means, and means for setting the potential As will be clearly understood from FIG. 2, current at a connection point between the ?rst and second tun ?ows through the switching MOS transistor TR1 ex nel diodes to a predetermined level through the bit line. cept for the points A1, A2 and A3 (hereinafter referred According to the invention, the switching means is to as “current stable points”) where the same current closed to set the potential on the data line at a predeter mined level, thereby writing data into the memory cell. 40 ?ows through the tunnel diodes TD1 and TD2. When The data is held by a current which ?ows through the the transistor TR1 is turned off while the current is ?rst and second tunnel diodes. A data refreshing opera ?owing through the transistor TR1, the potential at the tion is thus unnecessary. Since each memory cell is connection point between the diodes TD1 and TD2 composed of two tunnel diodes and one switching changes to a value corresponding to one of the current means, the semiconductor memory device of the inven stable points A1, A2 and A3. If the potential on the bit tion can be constituted by a small number of elements. line BL01 is set at, for example, about VSS level while the transistor TR1 is on, and the transistor TR1 is there BRIEF DESCRIPTION OF THE DRAWINGS after turned off, the potential at the connection point FIG. 1 is a circuit diagram of a semiconductor mem between the diodes TD1 and TD2 will be held at a ory device embodying the present invention; 50 potential VAl which corresponds to the current stable FIG. 2 illustrates the -current characteristics point A1. If the potential on the bit line BL01 is set at of two tunnel diodes used in the memory device shown about VDD level while the transistor TR1 is on and the in FIG. 1; transistor TR1 is thereafter turned off, the potential at FIG. 3 shows a sense ampli?er circuit used in the the connection point between the diodes TD1 and TD2 memory device shown in FIG. 1; and 55 will be held at a potential VA2 which corresponds to FIG. 4 shows another semiconductor memory device the current stable point A2. The potential at the connec embodying the present invention. tion point between the two tunnel diodes of any mem ory cell other than the cell MC11 can be selectively set DETAILED DESCRIPTION OF THE at the potential VAl or VA2 in a similar manner. In this PREFERRED EMBODIMENT 60 ‘case, it is preferable that the points A1 and A2 be set at FIG. 1 shows a memory device embodying the pres or near the minimal points of the V-I characteristic ent invention. The memory device includes memory curves of the tunnel diodes TD1 and TD2, respectively cells MC11 to MCMP which are arranged in a matrix so that minimum currents will flow at the current stable array and other memory cells MC1(P+1) to MCMN points A1 and A2. which are also arranged in a matrix array. The device 65 Moreover, the potential at a connection point be further includes bit lines BL01 to BLOM each con tween the two tunnel diodes of, for example, the nected to those memory cells MC11 to MCMP which dummycell DC11 can be set at a potential level VA3 are arranged in the same row, bit lines BL11 to BLlM which corresponds to the current stable point A3. This 4,573,143 3 4 is achieved by setting the potential on the bit line BL11 DL and one of the bit lines BLl to BLM which is con substantially equal to the potential level VA3, e.g. nected to the memory cell, is turned on by a control (VDD+VSS)/2 by means of the sense ampli?er circuit signal from an external circuit (not shown). SAC while the word line DWLl is kept active, and Further, the two tunnel diodes of each of the dummy then rendering the word line DWLl inactive. As shown cells used in the device of FIG. 1 may be replaced by in FIG. 3, the circuit SAC includes sense ampli?ers two high resistance elements. SAl to SAM, switching MOS transistors each con What is claimed is: nected between a data line DLO and a corresponding 1. A semiconductor memory device comprising: one of bit lines BL01 to BLOM, and other switching at least one memory cell having ?rst and second VIOS transistors each connected between a data line 10 power source terminals held at substantially con DLl and a corresponding one of bit lines BL11 to stant potentials, ?rst and second tunnel diodes con BLlM. Both data lines DLO and DLl are connected to nected in series in a forward-bias direction between in external circuit (not shown). The potential on the bit the ?rst and second power source terminals and a ine BL11 can thus be set at (VDD+VSS)/2 when the switching means connected at one end to a connec :xternal circuit sets the potential on the data line DLO at tion point between the ?rst and second tunnel di :VDD+VSS)/ 2 and one of the switching MOS transis odes; zors connected to the bit line BL11 is turned on, and a bit line connected to the other end of said switching :onsequently a potential at the connection point be vween the two tunnel diodes of the dummy cell can be means; and a word line connected to said switching means to :et at the potential VA3. 20 To read data from,‘ for example, the memory cell supply a signal for controlling the conduction state vICll, the word lines WL1 and DWLl are made ac of said switching means, the potential at the con ive. The potential on the bit line BL01 is then set at the nection point between said ?rst and second tunnel iotential level VAl or VA2 according to the data diodes being set at one of predetermined ?rst and .tored in the memory cell MC11. At the same time, the 25 second potential levels during a write operation iotential on the bit line BL11 is set at the potential level according to the potential on said bit line. / A3. The sense ampli?er circuit SAC senses the differ 2. A semiconductor memory device according to :nce between the potentials on the bit lines BL01 and claim 1, further comprising at least one dummy cell 3L11, thus reading the data from the memory cell which has two tunnel diodes and a switching means vICll. In order to reduce the power consumption of connected to a connection point between the two tunnel :ach dummy cell, it is preferable to write data of poten diodes. ial level VA3 into the dummy cell immediately before 3. A semiconductor memory device according to he data reading cycle and to write data of potential claim 2, wherein the connection point between said two evel VA] or VA2 into the dummy cell after the data tunnel diodes of said dummy cell is set at a potential eading cycle. 35 level between the ?rst and second potential levels. In the memory device shown in FIG. 1, each of the 4. A semiconductor memory device according to memory cells is comprised of one MOS transistor and claim 2, wherein said switching means is a MOS transis W0 tunnel diodes. Each memory cell can store the data tor. vithout being subjected to a data refreshing operation. 5. A semiconductor memory device according to ."he memory device can therefore be made with a high claim 1, wherein said switching means is a MOS transis racking density. tor. The present invention is not limited to the embodi 6. A memory cell comprising: ient described above. The dummy cells DC01 to ?rst and second power source terminals held at sub )COM and the dummy cells DC11 to DClM may be stantially constant potentials; mitted and the sense ampli?er circuit SAC may be 45 ?rst and second tunnel diodes connected in series in a eplaced by comparators CMPl to CMPM as shown in forward-bias direction between said ?rst and sec IG. 4. In the embodiment of FIG. 4, the comparators ond power source terminals; and IMPl to CMPM compare potentials on bit lines BLI to a switching means connected at one end to a connec ELM with a reference potential, and data can be read tion point between said ?rst and second tunnel ut from memory cells MC11 to MCMN. The reference diodes, the potential at the connection point being otential is applied from, for example, a connection set at approximately one of the ?rst and second oint between two resistors which are connected in predetermined potential levels according to the eries between power source terminals VD and VS. potential at the other end of said switching means. To write data into each memory cell of the device 7. A memory cell according to claim 6, wherein said nown in FIG. 4 from a data write-in circuit, one of the 55 switching means is a MOS transistor. 105 transistors which is connected between a data line * * * it *

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