Intel 80200 Prod Brf Rev1.qxd 9/10/03 4:41 PM Page 1

product brief

Intel® 80200 Processor based on Intel® XScale™ — Delivers Core Performance Breakthrough

Product Highlights

Intel® 80200 Processor 32-bit high-performance CPU (200, 400, 600, 733 MHz) based on Intel® XScale™ microarchitecture developer.intel.com Extended Temperature Operating Range (-40C to +85C) for the 200, 400 and 600 MHz Bins ARM* v.5TE compliant Intel® Superpipelined RISC technology 7-stage integer/8-stage memory superpipelined core – high core speeds with low power 32 KB data and instruction caches 2 KB Mini data for accelerated streaming from ultra-low power to high-performance Power Management Unit processing. Everything from handheld devices 128-entry Branch Target Buffer to enterprise infrastructure products can process 32-entry Instruction, 32-entry Data Memory rich content by utilizing Intel XScale Management Units technology based processors. High core Performance Monitoring Unit performance paves the way for extremely complex applications – especially applications 32-bit Interface that require processor intensive calculations. 64-bit Core Memory Bus with ECC The Intel 80200 processor can be combined with ASIC peripherals to provide solutions targeted at selected market segments. The Based on Intel® XScale™ Microarchitecture 80200 processor, for example, could be combined with an ASIC with high-bandwidth The Intel 80200 processor is based on the Intel PCI interfaces, memory controllers, and XScale microarchitecture. This microarchitecture networking microengines to provide a highly is compliant with the ARM Version 5TE ISA integrated, high-performance, I/O or network instruction set (excluding the floating point processor. Several companies have customized instruction set). When combined with the Intel® ASICs for use with the 80200 in a variety of 80312 I/O companion chip or a customized third applications. Intel has also made the 80200 party ASIC, the Intel 80200 processor becomes a external bus spec available to facilitate the very powerful I/O and embedded processing development of these custom solutions. solution. The Intel 80200 processor is manufactured on Intel’s 0.18-micron semiconductor process technology. This process technology enables the ® Intel 80200 Product Overview core to operate over a wide The Intel 80200 processor based on Intel range of speed and power, producing industry- XScale microarchitecture is Intel’s first of a new leading MIPS/mW performance. generation of processors giving developers of a wide range of applications the ability to optimize their designs for the needs of their applications Intel 80200 Prod Brf Rev1.qxd 9/10/03 4:41 PM Page 2

The Intel® 80200 Processor – Greater I/O StrongARM* SA-110 processor. It is also compliant with Performance Through Faster Cores ARM v.5TE ISA. Users can maximize code density with the 16-bit Thumb* instruction set. The ARM v.5TE ISA The Intel 80200 processor is available in four speed executes either a 32-bit ARM instruction set or the Thumb grades: 200 MHz, 400 MHz, 600 MHz, and 733 MHz. instruction set. Intel has recently announced the 80200T, an Extended Temperature (-40C to +85C) version of the 80200, to expand the range of applications that can take advantage of the Intel XScale technology based processor. The 80200T is available in 200, 400 and 600 MHz speed grades. The Not Just Faster Cores – but many other variety of core speeds allows developers to select the core features too that best balances performance with power consumption. Even at 733 MHz the Intel 80200 processor dissipates less The Intel XScale microarchitecture surrounds the core than 1.3W! This is accomplished using the Intel with instruction and data memory management units; Superpipelined RISC Technology – the 7-stage integer, 8- instruction, data, and mini-data caches; write, fill, pend, and stage memory superpipelined core achieves high speed branch target buffers; power management, performance with ultra-low power consumption. monitoring, debug, and JTAG units; coprocessor interface; High-performance applications can be further enhanced and core memory bus. ® with use of the 32 KByte data and instruction caches. A 2 Intel Dynamic Voltage Management and frequency KByte mini-data cache is also included to help avoid scaling on-the-fly allows designers to utilize the right blend “thrashing” of the data cache for frequently changing data of performance and power for their application. ® streams. The combination of speed and larger caches Intel Media Processing Technology provides a high level allows users to implement complex applications and of integration between the execution core and advanced processor intensive calculations like audio encode/decode communication functions. The Intel 80200 processor or video compression/decompression. includes a 40-bit Multiply Accumulate Unit, support for The Intel 80200 processor based on Intel XScale 16-bit SIMD, and DSP Extensions. microarchitecture is code compatible with the Intel®

Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Block Diagram Intel 80200 Prod Brf Rev1.qxd 9/10/03 4:41 PM Page 3

Features Benefits

Intel® Superpipelined Technology 7-stage integer/8-stage memory superpipelined core achieves high speed and ultra-low power

Intel® Dynamic Voltage Management Dynamic voltage and frequency scaling on-the-fly allows applications to utilize the right blend of performance and power

Intel® Media Processing Technology Multiply-Accumulate Coprocessor performs two simultaneous 16-bit SIMD multiplies with 40-bit accumulation for efficient media processing

Power Management Unit Gives power savings via idle, sleep, and quick wake-up modes

128-entry Branch Target Buffer Keeps pipeline filled with statistically correct branch choices

32 KB Instruction Cache Keeps local copy of important instructions to enable high performance and low power

32 KB Data Cache Keeps local copy of important data to enable high performance and low power

2 KB Mini-Data Cache Avoids "thrashing" of the D-Cache for frequently changing data streams

32-entry Instruction Memory Management Unit Enables logical-to-physical address translation, access permissions, I-Cache attributes

32-entry Data Memory Management Unit Enables logical-to-physical address translation, access permissions, D-Cache attributes

4-entry Fill and Pend Buffers Promotes Core efficiency by allowing non-blocking and "hit-under-miss" operation with D-Caches

Performance Monitoring Unit Furnishes two 32-bit event counters and one 32-bit cycle counter for analysis of hit rates, etc.

Debug Unit Uses Hardware Breakpoints and 256-entry Trace History Buffer (for flow change messages) to debug programs

32-bit Coprocessor Interface Provides high performance interface between core and

64-bit Core Memory Bus with simultaneous Gives up to 4.8 GBytes/sec. @ 600 MHz bandwidth for internal accesses 32-bit input path and 32-bit output path

8-entry Write Buffer Allows the Core to continue execution while data is written to memory

Extended Temperature Support Enables customers to take advantage of the 80200’s performance in a (200, 400 and 600 MHz only) broader array of applications and operating environments

Intel® 80200 Processor-based on Intel® XScale™ Microarchitecture Performance Characteristics Intel 80200 Prod Brf Rev1.qxd 9/10/03 4:41 PM Page 4

Product Ordering Information

Intel® 80200 Product Order Code: FW80200M200, FW80200M400, FW80200M600, FW80200M733 FW80200M200T, FW80200M400T, FW80200M600T Evaluation Kit Product Code: IQ80310 (This unit does not ship with JTAG. A listing of JTAG vendors is available at developer.intel.com/design/iio/devtools/tptools.htm) Intel® I/O Processor Literature

P roduct Briefs: Manuals/Guides: 273168 i960® RM/RN Processor Product Brief 273139 Intel® i960® RM/RN I/O Processor Design Guide 273169 i960® RM/RN Processor Evaluation Board 273158 i960® RM/RN I/O Microprocessor Product Brief Developer’s Manual 273357 Intel® 80303 I/O Processor Product and 273160 IQ80960RM/RN Evaluation Board Manual Evaluation Board Brief 273353 Intel® 80303 I/O Processor Developer’s Manual ® 273426 Intel IOP310 I/O Processor Chipset 273308 Intel® 80303 I/O Processor Design Guide P roduct Brief 273401 Intel® IQ80303 Evaluation Board Manual 273427 Intel® 80200 Processor Product Brief 273411 Intel® 80200 Processor Developer’s Manual 273435 Intel® IOP310 I/O Processor Chipset Evaluation Board Brief 273410 Intel® 80312 I/O Companion Chip Developer’s Manual Data Sheets: 273354 Intel® 80310 I/O Processor Chipset Design Guide 273156 Intel® 80960RM I/O Processor 273431 Intel® IQ80310 Evaluation Board Manual 273157 Intel® 80960RN I/O Processor 273358 Intel® 80303 I/O Processor 273355 Intel® 80303 I/O Processor Specification Update 273414 Intel® 80200 Processor 273415 Intel® 80200 Processor Specification Update 273425 Intel® IOP310 I/O Processor Companion Chip Data Sheet 273416 Intel® IOP310 I/O Companion Chip Specification Update

Intel Access

Developer’s Site developer.intel.com

I/O Building Blocks Home Page developer.intel.com/design/iio

Intel XScale Microarchitecture developers.intel.com/design/intelxscale

Other Intel Support developer.intel.com/design/litcentr Intel Literature Center (800) 548-4725 7a.m. to 7 p.m. CST (U.S. and Canada) International locations please contact your local sales office. General Information Hotline (800) 628-8686 or (916) 356-3104 5 a.m. to 5 p.m. PST

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

*Other brands and names are the property of their respective owners.

For more information, visit the Intel Web site at: developer.intel.com

UNITED STATES AND CANADA EUROPE ASIA-PACIFIC JAPAN SOUTH AMERICA Intel Corporation Intel Corporation (UK) Ltd. Intel Semiconductor Ltd. Intel Kabushiki Kaisha Intel Semicondutores do Brazil Bldg. Pipers Way 32/F Two Pacific Place P.O. Box 115 Tsukuba-gakuen Rue Florida, 1703-2 and CJ22 2200 Mission College Blvd. Swindon 88 Queensway, Central 5-6 Tokodai, Tsukuba-shi CEP 04565-001 Sao Paulo-SP P.O. Box 58119 Wiltshire SN3 1RJ Hong Kong, SAR Ibaraki-ken 305 Brazil Santa Clara, CA 95052-8119 UK Japan USA © Intel Corporation 2002 Order Number: 273427-001 Printed in USA/1102/5K/IL21643 SJ