Failure Modes and Mechanisms in Electronic Packages Failure Modes and Mechanisms in Electronic Packages

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A service of lOOP '" Failure Modes and Mechanisms in Electronic ----_...... _._ .. _._-_ .. _------Packages

Pu1igandla Viswanadham Technology Development Group, Circuit (ard Assembly Raytheon TI Sytems Ine., Lewisville, 1)(

Pratap 5ingh President RAMP Labs, Round Rock, 1)(

al SPRINGER-SCIENCE+BUSINESS MEDIA, BV Cover design: Curtis Tow Graphics

AII rights reserved. No part of this book covered by the copyright hereon may be reproduced or used in any form or by any means-graphic, electronic, or mechanical, including photocopying, recording, taping, or information storage and retrieval systems-without the written permission of the publisher.

1 2 3 4 5 6 7 8 9 10 XXX 01 00 99 98

Library of Congress Cataloging-in-Publication Data Viswanadham, Puligandla. Failure modes and mechanisms in electronic packages / by Puligandla Viswanadham, Pratap Singh. p. cm. Inc1udes bibliographical references and index. ISBN 978-1-4613-7763-4 ISBN 978-1-4615-6029-6 (eBook) DOI 10.1007/978-1-4615-6029-6 1. Electronic packaging--Defects. 2. Semiconductors--Failures. I. Singh, Pratap, 1940- . II. Title. TK7870.15.V57 1997 621.381'046--DC21 97-26388 CIP

British Library Cataloguing in Publication Data available "Pailure Modes and Mechanisms in Electronic Packages" is intended to present technically accurate and authoritative information from highly regarded sources. The publisher, editors, authors, advisors, and contributors have made every reasonable effort to ensure the accuracy of the information, but cannot assume responsibility for the accuracy of ali information, or for the consequences of its use. Contents

Foreword xv

Preface xvii

Acknowledgments xix

1 Introduction 1 1.1 The Technology 1.2 Packaging Failure 3 1.3 Approach and Methodology 4 1.4 Packaging Hierarchy 5 1.5 Failure Detection 6 1.6 Analysis 7 1.7 Modes and Mechanisms 8 1.8 Physics of failure and statistical models 9 1.9 Prevention 10 1.10 The Future 10 1.11 Suggested Readings 11

2 Electronics Packaging 12 2.1 Introduction 12 2.2 Packaging Nomenclature 13 2.3 Package Function 13 2.4 Plated-Through-Hole and Surface Mount Technology 15 2.5 Chip Level Packaging 15 2.5.1 Wire Bond or Ribbon Bond Packaging 16 2.5.2 Flip Chip Packaging 18 2.5.3 Tape Automated Bonding (TAB) Packaging 20 2.5.4 Ball Grid Array (BGA) Packaging 21 2.5.5 Chip Scale Packages (CSPs) 21 2.6 Printed Circuit Board Assembly 21 2.6.1 Printed Circuit Trace 26

v vi / Contents

2.6.2 Solder Mask 28 2.6.3 Preserving Printed Circuit Board (PCB) Solderability 28 2.6.4 PCB Materials 29 2.6.5 Flexible Circuits 29 2.6.6 Molded Circuits 30 2.7 Connectors, Cables, and Sockets 31 2.7.1 Introduction 31 2.7.2 Connector Types and Classifications 34 2.7.3 Connectors and PCB Assembly 34 2.7.3.1 Flux Contamination of Contacts 35 2.7.3.2 Conformal Coating Contamination 36 2.7.3.3 Dust and Debris Accumulation in Open Slots 36 2.7.3.4 Insertion Stresses on SMT Connector Solder Joints 36 2.7.3.5 Contact Metallurgy 36 2.7.3.6 Polarization for Alignment and Mating of Contacts 37 2.7.4 Sockets 37 2.7.4.1 Socket or Solder Attachment 39 2.7.4.2 Production vs. Test Sockets 40 2.7.5 Flat or Ribbon Cable Connectors 41 2.7.6 Optical Connectors 41 2.7.7 Elastomeric Connectors 43 2.8 Box Level Package 45 2.9 Cost of Failures 45 2.10 Summary 47 2.11 Suggested Readings 47 2.12 References 48

3 Why Failures Occur 51 3.1 Introduction 51 3.2 Stress vs. Strength 52 3.3 Poor Design Practices 53 3.3.1 Component Spacing 54 3.3.2 Clearance Between Component and PCB 54 3.3.3 Orientation (Components) 54 3.3.4 Stress Concentration (Trace Entry to Pad) 55 3.3.5 Stress Relief 55 3.3.6 Pad Vias 55 3.3.7 Test Point Accessibility 55 3.3.8 Alignment Forces During Reftow 56 3.3.9 Tolerances Accumulation 57 3.3.10 Under Design 57 3.3.11 Bending (Lack of Stiffness) 57 3.3.12 Polarization for Blind Mating 57 3.4 Manufacturing Defects 58 3.4.1 Warpage 59 3.4.2 Manufacturing Contaminants 60 3.5 Electrical Design Considerations 61 3.5.1 Physical Size of the Printed Wiring Board 61 Contents / vii

3.5.2 Power and Ground System Impedance 61 3.5.3 Signal Return Paths 62 3.5.4 Localized and Distributed Capacitance 62 3.5.5 Signal Integrity: Signal Ringing, Overshoot, and Undershoot 63 3.5.6 Component Thermal Margin 64 3.6 Material Characteristics 65 3.6.1 Coefficient of Thermal Expansion (CTE) Mismatch 65 3.6.2 Moisture Absorption 66 3.6.3 Environmental Corrosion 67 3.6.4 Materials Incompatibility 67 3.6.5 Melting Point Hierarchy 68 3.6.6 Metal Migration 68 3.7 Summary 68 3.8 References 69

4 Failure Detection 70 4.1 Introduction 70 4.1.1 Analytical Modeling 70 4.1.2 Statistical Simulation 71 4.1.3 Environmental Stress Testing 71 4.2 Analytical Modeling 72 4.2.1 Finite Element Modeling 72 4.2.2 Tolerance Analysis 74 4.2.3 Stress Analysis 75 4.3 Simulation 75 4.3.1 Electrical Simulation 75 4.3.1.1 Key Simulation Parameters 76 4.3.1.2 Determining the Values for Key Parameters 76 4.3.1.3 Tools 77 4.3.2 Mechanical Simulation 78 4.4 Environmental Stress Tests 78 4.4.1 Accelerated Tests 79 4.4.2 STRIFE Testing 80 4.4.3 Thermal Cycling 81 4.4.4 Thermal Shock 82 4.4.5 Insulation Resistance 83 4.4.6 Highly Accelerated Stress Test (HAST) 83 4.4.7 Temperature, Humidity, and Bias 87 4.4.8 Vibration 88 4.4.9 Mechanical Shock (Drop Test) 88 4.4.10 Salt Fog Test 88 4.4.11 Torque Test 89 4.4.12 Dust Test 89 4.4.13 Flowing Gas Test 90 4.5 Test Methodology Innovations 93 4.6 Summary 93 4.7 Suggested Readings 94 4.8 References 94 viii / Contents

5 Failure Analysis 96 5.1 Introduction 96 5.2 Visual Inspection 97 5.2.1 Optical Inspection 99 5.2.2 X-rays 100 5.2.3 Thermal ImaginglInfrared Microscopy 100 5.2.3.1 Localized louIe Heating 101 5.2.4 Acoustic Imaging 101 5.2.4.1 Scanning Laser Acoustic Microscopy (SLAM) 103 5.2.4.2 C-Mode Acoustic Microscopy 103 5.3 Decapsulation 105 5.3.1 Wet Decapsulation 106 5.3.2 The Plasma Technique (Dry Decapsulation) 106 5.4 Moire Interferometry 107 5.5 Dye Penetrants 109 5.6 Metallurgical Analysis 110 5.6.1 Metallurgical Examination 111 5.7 Chemical Analysis 112 5.7.1 Volumetric Analysis 112 5.7.2 Gravimetric Analysis 112 5.8 Atomic Absorption Emission Spectroscopies 113 5.9 UVNisible Spectroscopy 113 5.10 Infrared Spectroscopy 114 5.11 Thermoanalytical Methods 115 5.11.1 Differential Scanning Calorimetry 117 5.11.2 Thermomechanical Analyzer 117 5.11.3 Thermogravimetric Analysis 122 5.12 Chromatography 123 5.13 Electron Beam Analysis 124 5.13.1 Auger Electron Spectroscopy (AES) 125 5.13.2 X-rayIPhotoelectron Spectroscopy (XPSIESCA) 125 5.13.3 Secondary Ion Mass Spectrometry (SIMS) 127 5.13.4 Scanning Electron Microscopy (SEM) 128 5.14 Laser Induced Ionization Mass Spectrometry (LIMS) 132 5.15 Summary 133 5.16 Suggested Readings 133 5.17 References 133

6 Failure Modes and Mechanisms 136 6.1 Introduction 136 6.2 Failure Mode Types 137 6.2.1 Electrical Shorts 137 6.2.2 Electrical Opens 137 6.2.3 Intermittent Failures 138 6.3 Printed Circuit Board 138 6.3.1 Material-Related Defects 139 6.3.1.1 Prepreg Defects 139 Contents / ix

6.3.1.2 Measling, Crazing, and Haloing 139 6.3.1.3 Blistering and Delamination 141 6.3.1.4 Summary 141 6.3.2 SignalJPower Plane Plating Surface Defects 141 6.3.2.1 Copper Etch Shorts 141 6.3.2.2 Copper Etch Opens 141 6.3.2.3 Mechanical Circuit Damage 142 6.3.2.4 Handling Defects of Plated Copper Surfaces 142 6.3.2.5 Particulate Contamination 143 6.3.2.6 Pits and Scratches 145 6.3.2.7 Reduced Conductor Spacing 145 6.3.2.8 Summary 145 6.3.3 Through-Hole Defects 150 6.3.3.1 Partially Drilled Holes 151 6.3.3.2 Epoxy Smear 155 6.3.3.3 Nailheading 156 6.3.3.4 Inner Plane Delamination 157 6.3.3.5 PTH Copper Grain Structure 158 6.3.3.6 PTH Copper Plating Defects 158 6.3.3.7 PTH Solderability 159 6.3.3.8 Pink Ring 164 6.3.3.9 Summary 169 6.3.4 Solder Mask Related Defects 170 6.3.5 PCB Defect Elimination 170 6.4 Components and Packages 172 6.4.1 Introduction 172 6.4.2 Insertion Mount (PIH) Components 173 6.4.3 Surface Mount Components 173 6.4.3.1 SMT Chip Tombstoning 175 6.4.3.2 Modeling of Tombstoning Failures 176 6.4.3.3 SMT Chip Skewing 176 6.4.3.4 SMT Chip Cracking 176 6.4.4 SMT Packages 178 6.4.4.1 Package Failures 178 6.4.4.2 Interconnect Failures 187 6.4.4.2.1 Bond Pad Corrosion 187 6.4.4.2.2 Wire Bond Fails 188 6.4.4.3 Encapsulation Defects 190 6.4.4.4 Leads Related Failures 191 6.4.4.5 Summary 193 6.5 Interconnection Failures 193 6.5.1 Solder Joint Voids 193 6.5.1.1 PTH Solder Joint Voids 195 6.5.1.2 Hole Fill 196 6.5.1.3 SMT Solder Joint Voids 196 6.5.1.4 SMT Void Formation 199 6.5.1.5 Voids in BGA Joints 200 x / Contents

6.5.1.6 Summary 201 6.5.2 Intermetallics 201 6.5.2.1 Introduction 201 6.5.2.2 Intermetallic Formation 203 6.5.2.2.1 Copper-Tin Intermetallics 203 6.5 .2.2.2 Nickel-Tin Intermetallics 204 6.5.2.2.3 Gold-Tin Intermetallics 204 6.5.2.3 Effect on Solderability 205 6.5.2.4 Effect on Joint Strength 205 6.5.2.5 Summary 206 6.5.3 Thermal Ratcheting 206 6.5.4 Solder Balling 210 6.5.4.1 Solder Balling During Wave Solder 210 6.5.4.2 Solder Balling During SMT Reflow 210 6.5.4.3 Solder Webbing 213 6.5.4.4 Solder Ball Test 213 6.5.4.5 Summary 213 6.6 Lead-Free Solders 213 6.6.1 Introduction 213 6.6.2 Tin-Bismuth Solder 214 6.6.3 Lead Contamination of Tin-Bismuth Solder 215 6.6.4 Indium Solder Corrosion 215 6.6.5 Summary 218 6.7 Corrosion and Migration 218 6.7.1 Introduction 218 6.7.1.1 Factors Affecting Corrosion and E1ectrornigration 219 6.7.2 Corrosion 220 6.7.2.1 Electrode Potentials and Galvanic Corrosion 220 6.7.2.2 Conditions for Corrosion 221 6.7.3 Electrornigration 221 6.7.3.1 Conditions for Electrornigration 222 6.7.3.2 Conductive Anodic Filament 225 6.7.3.3 Conditions for Conductive Anodic Filament formation 226 6.7.3.4 Measurement of Migration Propensity 226 6.7.4 Electrornigration and Corrosion of Select Metals 228 6.7.4.1 Silver 228 6.7.4.2 Copper 230 6.7.4.3 Tin 230 6.7.4.4 Lead 230 6.7.4.5 Gold 231 6.7.5 Failure Analysis of Corrosion and Electrornigration 231 6.7.6 Prevention of Corrosion and Electrornigration Phenomena 232 6.7.7 Tin Whiskers 233 6.7.7.1 Introduction 233 6.7.7.2 Whisker Growth Mechanism 234 6.7.7.3 Whisker Prevention 234 6.7.7.4 Summary 236 Contents / xi

6.8 Connector Failures and Mechanisms 236 6.8.1 Introduction 236 6.8.2 Mechanical Failures 238 6.8.2.1 Bent Pins and Contacts 238 6.8.2.2 Card Warpage 240 6.8.2.3 Handling and Shipping Damage 240 6.8.2.4 Tolerances and Interference 240 6.8.2.5 Contact Fabrication 242 6.8.2.6 Temperature-Induced Mechanisms 242 6.8.2.7 Summary 244 6.8.3 Contact Corrosion 244 6.8.3.1 Introduction 244 6.8.3.2 Gold Plating Wear 245 6.8.3.3 Manufacturing Contaminant Corrosion 245 6.8.3.4 Dust 247 6.8.3.5 Connector Housing 247 6.8.3.6 Summary 249 6.8.4 Fretting Corrosion 249 6.8.4.1 Introduction 249 6.8.4.2 Fretting Corrosion Variables 249 6.8.4.3 The Fretting Mechanism 251 6.8.4.4 Socket Device Walk Out 251 6.8.4.5 Summary 252 6.8.5 Frictional Polymerization on Palladium Plating 252 6.8.6 Contact Arcing Due to Hot Plugging 252 6.8.7 Summary 253 6.9 Solder Fatigue and Creep 253 6.10 Failures in Nonsemiconductor Components 256 6.10.1 Introduction 256 6.10.2 Resistors 257 6.10.3 Capacitors 258 6.10.4 Oscillators 260 6.10.5 Inductors 260 6.11 Electro Static Discharge (ESD) Failures 262 6.11.1 Introduction 262 6.11.2 ESD Failure Mechanisms 262 6.11.3 ESD Charge Generation 263 6.11.4 Prevention of Static Charge 266 6.11.4.1 Minimizing Charge Buildup 266 6.11.4.2 Draining of Charge 267 6.11.4.3 Neutralizing Static Charge 267 6.11.4.4 Shielding from Field and Discharge Effects 268 6.11.5 Summary 268 6.12 PCB Laminates and Hollow Glass Fibers 268 6.13 Radiation-Induced Failures 270 6.13.1 Damage Prevention 272 6.14 Summary 272 xii / Contents

6.15 Suggested Readings 273 6.16 References 273

7 Failure Models 283 7.1 Introduction 283 7.1.1 Physics-of-Failure Models 284 7.1.2 Statistical Models 284 7.2 A Survey of Physical Models 285 7.2.1 Arrhenius Model 287 7.2.2 Eyring Model 287 7.2.3 VoltagelField Effect Model 288 7.2.4 Current Model 288 7.2.5 Power Model 289 7.2.6 Temperature Cycling Models 289 7.2.7 Humidity Models 289 7.2.7.1 Lawson Model 290 7.2.7.2 Eyring Humidity Model 290 7.2.7.3 Peck and Zierdt Model 291 7.2.7.4 Reich and Hakim Model 292 7.2.7.5 Sbar and Kozakiewicz Model 292 7.2.7.6 Weick Model 292 7.2.7.7 Stroehle Model 293 7.2.7.8 Hallek 293 7.2.7.9 SIM-Lawson Model 293 7.2.8 Humidity Ingress and Package/Card Damage Models 294 7.2.8.1 Memis Model 294 7.2.8.2 Conductive Anodic Filament Model 294 7.2.9 Solder Joint Fatigue Models 295 7.2.9.1 Coffin-Manson Model 295 7.2.9.2 Hughes Model 296 7.2.9.3 Steinberg Model 297 7.2.9.4 Englemaier Models 297 7.2.9.4.1 Leadless Model 297 7.2.9.4.2 Leaded Model 298 7.3 Physics-of-Failure Based Models for Devices 299 7.3.1 Black's Model 299 7.3.2 Fowler-Nordheim Model 299 7.3.3 Kidson Model 300 7.3.4 Kato and Niwa Model 300 7.4 Accelerated Factors and Transforms 301 7.4.1 Introduction 301 7.4.2 Temperature Acceleration 302 7.4.3 Mechanical Deflection Test 304 7.4.4 Vibration Acceleration 304 7.5 Summary 307 7.6 References 307 Contents / xiii

8 Failure Prevention 310 8.1 Introduction 310 8.2 Concurrent Engineering and DFM 311 8.3 DFM Examples 314 8.3.1 Discrete Component Orientation 314 8.3.2 Discrete Component Pad Geometry 314 8.3.3 Shadowing by Tall Components 316 8.4 Design for Assembly 317 8.4.1 DFA for Electronic Packaging Assembly 319 8.5 Design for Test 320 8.6 Design for Qualification 320 8.7 Design for Reliability 322 8.7.1 Stress on Solder Joints 323 8.7.2 Depanelling Stresses 323 8.7.3 Mother Board Mounting 323 8.7.4 Mechanical Damage 323 8.8 Continuous Improvement Through Defect Management 324 8.9 Summary 325 8.10 References 325 Appendices 327 Appendix A 327 Appendix B 336 Appendix C 338 Appendix D 348 Appendix E 359 About the Authors 361 Index 363 Foreword

Those of us who grew up in the "through-hole" age of electronic packaging are probably more amazed and appreciative than are our children at the incredible growth of electronic performance capability. My son, an electrical engineering student, seems almost to take for granted the innovations that leave me somewhat awestruck at times. Electronic circuit designers delight in packing more punch into less volume, while reminding us that their job has become increasingly challenging. The lay person also has learned from the media that the industry has been working wonders in shrinking the transistor and expanding the power of "the chip." Much attention is focussed on the silicon and on the marvelous production and entertainment tools we now see in our offices and homes. Between the silicon and the end product lies the less publicized world of circuit-level packaging. We leave it to a cadre of technologists to take the schematics and parts lists and to develop the processes that tum the designers' concepts into physical reality. And while the silicon transistor is shrinking, the engineering challenges of packaging multiple chips and associated components into increasingly dense subsystems are growing. Further, the transistor may have to function without failure through severe industrial or military environments over the lifetime of the product. Weare often asked to provide help to people who do surface mount technology (for instance), but experience failures because they lack basic understanding of the importance of land pattern geometries, solder volume, lead forming, stepped stencils, thermal management, and so forth. How little do we typically appreciate the electronic packaging engineer's skills and expertise! This leads to the purpose of this book: to gather some of this expertise into a useful, convenient, and timely reference of current electronic packaging alternatives with the associated manufacturing pitfalls and problems. This book will aid a wide range of readers, from the student to the practicing packaging or process engineer. Topics range from an overview of electronic

xv xvi / Foreword packaging history and current trends to the details of failure mechanisms and failure analysis tools and techniques. The student, the circuit designer, and the systems engineer will learn the current terminology, and gain a better appreciation of electronic packaging options, challenges, design tradeoff considerations, and potential problems. The packaging practitioner will be able to delve much more deeply into specific problem areas, and will learn how to analyze or, better yet, avoid problems. For the uninitiated engineer, this book should create some sense of the technical difficulties involved in current electronic packaging alternatives. For the packag• ing specialist, the book is a valuable collection of knowledge, technical depth, and important references. Whatever the reader's level of experience, I hope he or she leaves with a better sense of when to call a more advanced expert for help. Speaking of expertise, I have had the pleasure of working with one of the authors, whom we affectionately refer to as Viswam. He has been with us for a fairly short time as of the writing of this book, and yet I have watched with great satisfaction and admiration as his reputation spreads rapidly. The steady flow of demands for his time are a tribute to Viswam as a skilled technologist, a patient mentor, and a fine gentleman. Knowing Viswam thus, I am certain that he has likewise collaborated with the finest of his colleagues in the preparation of this work. We are all fortunate to benefit from the fruits of their collective efforts.

Rich Karm, Manager Circuit Card Assemblies Raytheon, TI Systems Preface

Electronic Packaging is a broad area of technology that encompasses several packaging levels-the chip/device, the component package, the carrier/substrate, the assembly, and the system. Failures occurs at all packaging levels, as well as stages of manufacturing and operation, for a variety of reasons and include design, materials and processing, and the environment. The purpose of this book is to provide a comprehensive account of failures encountered in electronic packages, with determination of their causes, analysis, and prevention. The emphasis is on first and second level packaging since many excellent books on device level failures already exist. Much of the failure related literature is dispersed among journals, magazines, conference proceedings, etc. It is not easily accessible unless the busy practicing engineer is willing to undertake an exhaustive literature search. Failure Modes and Mechanisms in Electronic Packages is intended to serve as an introduction to the subject for those entering the field of electronic packaging, and as a reference for practicing engineers. The book provides its readers with a perspective of the failures and their nature, origin, and causes. It is also intended to enable the technologist to perform root-cause analysis and understand the mechanistic as• pects of the failures. It describes the testing methodologies as well as the analyti• cal methods. An important aspect of the book is the several real life examples of failures commonly observed in the packaging industry. Methods to prevent failures and enhance product reliability are also addressed. The first chapter is an introduction that considers aspects such as packaging hierarchy, methodology, and failure detection and prevention. The second chapter describes electronic packaging in general, the different types of packages, printed circuit board assembly features, connectors, cables, and sockets, and provides packaging nomenclature. The third chapter deals with the various reasons for failures with a discussion of stress versus strength aspects, poor design practices,

xvii xviii / Preface manufacturing related defects, and materials related aspects. Chapter 4 describes a variety of techniques to detect failures. These include analytical modeling and a host of environmental tests that induce failures under test conditions. The fifth chapter describes selected physicochemical analytical techniques that are most commonly used for analyzing failures and establishing failure mechanisms. These include bulk analysis methods such as volumetric and gravimetric analysis, spec• troscopic techniques such as UV -visible and infrared spectroscopies, and electron beam techniques such as electron spectroscopies for chemical analysis, auger electron spectroscopy, etc. The chapter's intent is to provide the reader with a perspective of what the techniques are and what they are capable of but is not intended to be a treatise on the technique. The sixth chapter is by far the biggest chapter in the book and contains a fairly large sample of failure examples from the areas of printed circuit board, devices and packages, surface mount and insertion mount package-to-board interconnections, corrosion and electromigra• tion, lead free solder related failures, connector failures, and electrostatic dis• charge type failures. The seventh chapter covers a number of failure models that are in vogue. Approximately 20 different models are surveyed to provide the reader with a glimpse of how packaging technologists use models to predict the failures, and use the models to their advantage in making design improvements. The last chapter addresses an important issue, namely, failure prevention and discusses salient aspects of concurrent design and design for manufacturing with several pertinent examples. The book also contains several appendices with useful information. Although the book assumes no prior knowledge of electronic packaging on the part of the reader, the level of appreciation will perhaps be greater with a knowledge and background in basic physical sciences. The book can also be used as a textbook in conjunction with other packaging texts where microelectronics packaging is taught. Thus it is directed toward educational and industrial organiza• tions so that the newcomers to the industry will be better equipped to deal with some of the problems encountered, and the practicing engineer can use it as a source book on failure modes and mechanisms. It is the authors' hope that the book serves in some measure to bring to light the importance of understanding failure modes and mechanisms in electronic packaging and to develop an increasing awareness of these in the packaging com• munity.

Puligandla Viswanadham Pratap Singh Acknowledgments

In June 1995 Jeanne Glasser invited us to write a book for Van Nostrand Reinhold. It was a timely and fortunate coincidence that we were contemplating a book on a topic of current interest in electronic packaging, namely Failure Modes and Mechanisms. The topic was so akin to one of the subjects indicated in her letter, Product Reliability and Testing, that it culminated in the present work. Preparation of this book was facilitated by the assiduous efforts of dedicated people at Chapman and Hall. We like to thank them all with special mention to Bob Hauserman, Steve Yun, James Harper, and MaryAnn Cottone for their perseverance and patience. We thank the reviewers for their critical evaluation and favorable review of the book proposal. The material for this book came from a variety of sources in the open literature. Many of our colleagues have generously contributed their time in valuable discus• sions. We especially thank Dennis Goodrich for his contribution to Chapter 3, Section 3.5 on the electrical considerations that result in failures, and Chapter 4, Section 4.3, Simulation, a valuable addition in providing a more complete perspective on failures in packaging. The enthusiastic cooperation we received from the Texas Instruments' Lewis• ville Failure Analysis Laboratory personnel is remarkable indeed. Monique Thi• bault, Robert Champaign, Gene Garret, Chris Gardner, and Jim Wyatt have been especially helpful in providing the much needed photographs of typical analytical traces and graphs, photographs, and photodocumentation required. We thank Barbara Waller, manager of the failure analysis laboratory, who reviewed the initial draft of Chapter 5 and provided us with valuable comments. We thank Joslyn Kitchens and Jim Grider for excellent graphics and photographs of the packages. The authors also thank Jennifer Young for her timely and efficient help in the literature search. We want to thank the Institute for Interconnecting and Packaging Electronics Circuitry, and especially Dieter Bergman, for permitting us to reproduce several

xix xx / Acknowledgments printed circuit board related defects. We also thank Sonoscan Inc., UFE Inc. and mM for providing pertinent pictures. The first author (Puligandla Viswanadham) would like to thank his friends and colleagues at Texas Instruments Inc., for their strong support, help, and excellent discussions. He wants to especially thank Steve Dunford, David Stark, and Mike Wolverton. Viswanadham also wants to thank Rich Karm and Gary Tanel for their constant encouragement and support throughout the preparation of this book, and for providing an excellent environment that has enhanced his job satisfaction and professionalism and enabled the preparation of this book. The cheerful, constant, and timely help from Jean Thornton for administrative and graphical support is greatly appreciated. The second author (Pratap Singh) would like to thank Abe Torres of mM for supporting the preparation and planning of the book while the author was working at IBM. Pratap would also like to acknowledge the help received from Carl Williams of Dell Computer Corp. for taking the system packaging photographs and the kind permission from Dell Computer Corporation for their use. Acknowl• edgment is also due Kermit Aguayo of Xetel Corporation for providing the photographs of solder ball defects, and cracked capacitor. Both authors would like to thank their former colleagues Steve Heineke and William Mace for their help and valuable discussions in the preparation of this book. Lastly, the authors express their indebtedness to their respective families for their constant support, encouragement, patience, and love during the prepara• tion of the book. Viswanadham thanks his wife Santha, his children Usha and Sayi, and his son-in-law Joe. Pratap thanks his wife Saroj for her understanding and perseverance when writing the book took priority over other chores and his children Anuj and Raj for their helpful suggestions and words of support.

Puligandla Viswanadham Flower Mound, Texas

Pratap Singh Round Rock, Texas.