LT3575 Isolated Flyback Converter Without an Opto-Coupler

LT3575 Isolated Flyback Converter without an Opto-Coupler

FEATURES DESCRIPTION n 3V to 40V Input Voltage Range The LT®3575 is a monolithic switching regulator specifi c- n 2.5A, 60V Integrated NPN Power Switch ally designed for the isolated fl yback topology. No third n Boundary Mode Operation winding or optoisolator is required for regulation. The n No Transformer Third Winding or part senses the isolated output voltage directly from the Optoisolator Required for Regulation primary side fl yback waveform. A 2.5A, 60V NPN power n Improved Primary-Side Winding Feedback switch is integrated along with all control logic into a Load Regulation 16-lead TSSOP package. n V Set with Two External Resistors OUT The LT3575 operates with input supply voltages from n BIAS Pin for Internal Bias Supply and Power 3V to 40V, and can deliver output power up to 14W with NPN Driver no external power switch.The LT3575 utilizes boundary n Programmable Soft-Start mode operation to provide a small magnetic solution with n Programmable Power Switch Current Limit improved load regulation. n Thermally Enhanced 16-Lead TSSOP The output voltage is easily set with two external resistors APPLICATIONS and the transformer turns ratio. Off the shelf transformers are available for many applications. n Industrial, Automotive and Medical Isolated L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks and No RSENSE and ThinSOT is a trademark of Linear Technology Corporation. All other Power Supplies trademarks are the property of their respective owners.

TYPICAL APPLICATION 5V Isolated Flyback Converter

VIN Load Regulation 12V TO 24V 1 3:1 + V = 24V 10μF357k 0.22μF1k VOUT IN VIN 5V, 1.4A SHDN/UVLO 24μH 2.6μH47μF 51.1k 0 – VOUT VIN = 12V 80.6k LT3575 RFB RREF –1 TC 6.04k RILIM OUTPUT VOLTAGE ERROR (%) OUTPUT VOLTAGE SS SW VC GND TEST BIAS –2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 28.7k 10k 11.5k IOUT (A) 10nF 4.7nF 4.7μF 3575 TA01b

3575 TA01

3575f 1 LT3575 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION SW ...... 60V TOP VIEW VIN, SHDN/UVLO, RFB, BIAS ...... 40V SS, V , TC, R , R ...... 5V NC 1 16 NC C REF ILIM V 2 15 NC Maximum Junction Temperature ...... 125°C IN SW 3 14 GND Operating Junction Temperature Range (Note 2) SW 4 17 13 TEST GND LT3575E, LT3575I ...... –40°C to 125°C BIAS 5 12 TC Storage Temperature Range ...... –65°C to 150°C SHDN/UVLO 6 11 RREF SS 7 10 RFB RILIM 8 9 VC

FE PACKAGE 16-LEAD PLASTIC TSSOP

TJMAX = 125°C, θJA = 38°C/W, θJC = 10°C/W EXPOSED PAD (PIN 17) IS GND, MUST BE CONNECTED TO GND

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT3575EFE#PBF LT3575EFE#TRPBF 3575FE 16-Lead Plastic TSSOP –40°C to 125°C LT3575IFE#PBF LT3575IFE#TRPBF 3575FE 16-Lead Plastic TSSOP –40°C to 125°C Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/

ELECTRICAL CHARACTERISTICS The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. VIN = 12V, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS Input Voltage Range l 340V Quiescent Current SS = 0V 4.5 mA VSHDN/UVLO = 0V 01 μA Soft-Start Current SS = 0.4V 7 μA SHDN/UVLO Pin Threshold UVLO Pin Voltage Rising l 1.15 1.22 1.32 V

SHDN/UVLO Pin Hysteresis Current VUVLO = 1V 2.2 2.8 3.2 μA Soft-Start Threshold 0.7 V Maximum Switching Frequency 1000 kHz

Switch Current Limit RILIM = 10k 2.8 3.5 4.2 A

Minimum Current Limit VC = 0V 400 mA

Switch VCESAT ISW = 0.5A 75 125 mV

RREF Voltage VIN = 3V 1.21 1.23 1.25 V l 1.20 1.26

RREF Voltage Line Regulation 3V < VIN < 40V 0.01 0.03 %/ V l RREF Pin Bias Current (Note 3) 100 600 nA

3575f 2 LT3575

IREF Reference Current Measured at RFB Pin with RREF = 6.49k 190 μA

Error Ampliﬁ er Voltage Gain VIN = 3V 150 V/V

Error Ampliﬁ er Transconductance ΔI = 10μA, VIN = 3V 150 μmhos

Minimum Switching Frequency VC = 0.35V 40 kHz

TC Current into RREF RTC = 20.1k 27.5 μA

BIAS Pin Voltage IBIAS = 30mA 2.9 3 3.1 V Note 1: Stresses beyond those listed under Absolute Maximum Ratings to 125°C operating junction temperature range are assured by design may cause permanent damage to the device. Exposure to any Absolute characterization and correlation with statistical process controls. The Maximum Rating condition for extended periods may affect device LT3575I is guaranteed over the full –40°C to 125°C operating junction reliability and lifetime. temperature range. Note 2: The LT3575E is guaranteed to meet performance specifi cations Note 3: Current fl ows out of the RREF pin. from 0°C to 125°C junction temperature. Specifi cations over the –40°C

TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.

Output Voltage Quiescent Current Bias Pin Voltage 5.20 8 3.2 VIN = 40V 5.15 7 VIN = 40V WITH BIAS = 20V 3.0 VIN = 12V 5.10 6 2.8 5.05 5

(V) V = 5V WITH BIAS = 5V 5.00 4 IN 2.6 (mA) OUT Q I V 4.95 3 2.4 BIAS VOLTAGE (V) 4.90 2 2.2 4.85 1

4.80 0 2.0 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)

3575 G01 3575 G02 3575 G03

3575f 3 LT3575

TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.

Switch Saturation Voltage Switch Current Limit Switch Current Limit vs RILIM 500 4.5 4

450 4 MAX ILIM 3.5 400 3.5 25°C 3 350 3 125°C 2.5 300 2.5 VOLTAGE (mV) 250 2 –50°C 2.0 CESAT 200 1.5 1.5 150 CURRENT LIMIT (A) 1 1 100 SWITCH CURRENT LIMIT (A) SWITCH V MIN ILIM 50 0.5 0.5 0 0 0 0 500 10001500 2000 2500 3000 –50 –250 25 50 75 100 125 0 1020 30 40 50 60 SWITCH CURRENT (mA) TEMPERATURE (°C) RILIM RESISTANCE (kΩ) 3575 G04 3575 G05 3575 G06

SHDN/UVLO Falling Threshold SS Pin Current 1.28 12

10 1.26

8 1.24 6 1.22 /UVLO VOLTAGE (V) /UVLO VOLTAGE 4 SS PIN CURRENT (μA) SHDN 1.20 2

1.18 0 –50 –25 05025 75100 125 –60 –40–20040 20 6080 100 120 140 TEMPERATURE (°C) TEMPERATURE (°C) 3575 G07 3575 G08

3575f 4 LT3575 PIN FUNCTIONS NC (Pins 1, 15, 16): No Connect Pins. Can be left open of the switch. or connected to any ground plane. VC (Pin 9): Compensation Pin for Internal Error Amplifi er. VIN (Pin 2): Input Voltage. This pin supplies current to Connect a series RC from this pin to ground to compensate the internal start-up circuitry and as a reference voltage the switching regulator. A 100pF capacitor in parallel helps for the DCM comparator and feedback circuitry. This pin eliminate noise. must be locally bypassed with a capacitor. RFB (Pin 10): Input Pin for External Feedback Resistor. This SW (Pins 3, 4): Collector Node of the Output Switch. This pin is connected to the transformer primary (VSW). The pin has large currents fl owing through it. Keep the traces to ratio of this resistor to the RREF resistor, times the internal the switching components as short as possible to minimize bandgap reference, determines the output voltage (plus electromagnetic radiation and voltage spikes. the effect of any non-unity transformer turns ratio). The average current through this resistor during the fl yback BIAS (Pin 5): Bias Voltage. This pin supplies current to the period should be approximately 200μA. For nonisolated switch driver and internal circuitry of the LT3575. This pin applications, this pin should be connected to V . must be locally bypassed with a capacitor. This pin may IN also be connected to VIN if a third winding is not used and if RREF (Pin 11): Input Pin for External Ground-Referred VIN ≤ 15V. If a third winding is used, the BIAS voltage should Reference Resistor. This resistor should be in the range of be lower than the input voltage for proper operation. 6k, but for convenience, need not be precisely this value. SHDN/UVLO (Pin 6): Shutdown/Undervoltage Lockout. For nonisolated applications, a traditional resistor voltage divider may be connected to this pin. A resistor divider connected to VIN is tied to this pin to program the minimum input voltage at which the LT3575 TC (Pin 12): Output Voltage Temperature Compensation. will operate. At a voltage below ~0.7V, the part draws no Connect a resistor to ground to produce a current quiescent current. When below 1.22V and above ~0.7V, proportional to absolute temperature to be sourced into the part will draw 7μA of current, but internal circuitry will the RREF node. ITC = 0.55V/RTC. remain off. Above 1.22V, the internal circuitry will start TEST (Pin 13): This pin is used for testing purposes only and a 7μA current will be fed into the SS pin. When this and must be connected to ground for the part to operate pin falls below 1.22V, 2.8μA will be pulled from the pin to properly. provide programmable hysteresis for UVLO. GND (Pin 14, Exposed Pad Pin 17): Ground. The exposed SS (Pin 7) : Soft-Start Pin. Place a soft-start capacitor pad of the package provides both electrical contact to here to limit start-up inrush current and output voltage ground and good thermal contact to the printed circuit ramp rate. Switching starts when the voltage at this pin board. The exposed pad must be soldered to the circuit reaches ~0.7V. board for proper operation and should be well connected RILIM (Pin 8): Maximum Current Limit Adjust Pin. A resistor with many vias to an internal ground plane. should be tied to this pin to ground to set the current limit. Use a 10k resistor for the full current capabilities

3575f 5 LT3575 BLOCK DIAGRAM

D1 V T1 + IN VOUT C1 L1A L1B C2 R3 V – N:1 OUT

VIN RFB SW TC CURRENT FLYBACK Q3 Q2 ERROR ONE – TC CURRENT A2 AMP SHOT COMPARATOR + + –g R6 m – V1 I2 1.23V + A1 120mV 20μA + – V R IN REF DRIVER BIAS S R R4 Q Q1 S BIAS MASTER LATCH + C5 A4 RSENSE – 0.01Ω GND R1 1.22V SHDN/UVLO + INTERNAL A5 – REFERENCE OSCILLATOR AND I1 REGULATORS 7μA R2 2.8μA VC Q4 SS R7 RILIM C4

C3 3573 BD

3575f 6 LT3575 OPERATION The LT3575 is a current mode switching regulator IC The LT3575 features a boundary mode control method, designed specifi cally for the isolated fl yback topology. The where the part operates at the boundary between continuous special problem normally encountered in such circuits is conduction mode and discontinuous conduction mode. The that information relating to the output voltage on the isolated VC pin controls the current level just as it does in normal secondary side of the transformer must be communicated to current mode operation, but instead of turning the switch the primary side in order to maintain regulation. Historically, on at the start of the oscillator period, the part detects this has been done with optoisolators or extra transformer when the secondary side winding current is zero. windings. Optoisolator circuits waste output power and the extra components increase the cost and physical size Boundary Mode Operation of the power supply. Optoisolators can also exhibit trouble Boundary mode is a variable frequency, current-mode due to limited dynamic response, nonlinearity, unit-to-unit switching scheme. The switch turns on and the inductor variation and aging over life. Circuits employing extra current increases until a VC pin controlled current limit. The transformer windings also exhibit defi ciencies. Using an voltage on the SW pin rises to the output voltage divided extra winding adds to the transformer’s physical size and by the secondary-to-primary transformer turns ratio plus cost, and dynamic response is often mediocre. the input voltage. When the secondary current through the diode falls to zero, the SW pin voltage falls below V . The LT3575 derives its information about the isolated IN A discontinuous conduction mode (DCM) comparator output voltage by examining the primary side fl yback detects this event and turns the switch back on. pulse waveform. In this manner, no optoisolator nor extra transformer winding is required for regulation. The output Boundary mode returns the secondary current to zero voltage is easily programmed with two resistors. Since this every cycle, so the parasitic resistive voltage drops do not IC operates in boundary control mode, the output voltage is cause load regulation errors. Boundary mode also allows calculated from the switch pin when the secondary current the use of a smaller transformer compared to continuous is almost zero. This method improves load regulation conduction mode and no subharmonic oscillation. without external resistors and capacitors. At low output currents the LT3575 delays turning on the The Block Diagram shows an overall view of the system. switch, and thus operates in discontinuous mode. Unlike Many of the blocks are similar to those found in traditional a traditional fl yback converter, the switch has to turn on switching regulators including: internal bias regulator, to update the output voltage information. Below 0.6V on oscillator, logic, current amplifi er and comparator, driver, the VC pin, the current comparator level decreases to and output switch. The novel sections include a special its minimum value, and the internal oscillator frequency fl yback error amplifi er and a temperature compensation decreases in frequency. With the decrease of the internal circuit. In addition, the logic system contains additional oscillator, the part starts to operate in DCM. The output logic for boundary mode operation, and the sampling current is able to decrease while still allowing a minimum error amplifi er. switch off-time for the error amp sampling circuitry. The typical minimum internal oscillator frequency with VC equal to 0V is 40kHz.

3575f 7 LT3575 APPLICATIONS INFORMATION

ERROR AMPLIFIER—PSEUDO DC THEORY In combination with the previous VFLBK expression yields an expression for VOUT, in terms of the internal reference, In the Block Diagram, the RREF (R4) and RFB (R3) resistors can be found. They are external resistors used to program programming resistors, transformer turns ratio and diode the output voltage. The LT3575 operates much the same way forward voltage drop: as traditional current mode switchers, the major difference ⎛ R ⎞ ⎛ 1 ⎞ VV= ⎜ FB ⎟ ⎜ ⎟ −−VI(R ESR) being a different type of error amplifi er which derives its OUT BG ⎝ RN⎠ ⎝ α ⎠ FSEC feedback information from the fl yback pulse. REF PS Operation is as follows: when the output switch, Q1, Additionally, it includes the effect of nonzero secondary turns off, its collector voltage rises above the VIN rail. The output impedance (ESR). This term can be assumed to amplitude of this fl yback pulse, i.e., the difference between be zero in boundary control mode. More details will be it and VIN, is given as: discussed in the next section. VFLBK = (VOUT + VF + ISEC • ESR) • NPS Temperature Compensation VF = D1 forward voltage The fi rst term in the VOUT equation does not have a tem- ISEC = Transformer secondary current perature dependence, but the diode forward drop has a signifi cant negative temperature coeffi cient. To compen- ESR = Total impedance of secondary circuit sate for this, a positive temperature coeffi cient current NPS = Transformer effective primary-to-secondary source is connected to the RREF pin. The current is set by turns ratio a resistor to ground connected to the TC pin. To cancel the The fl yback voltage is then converted to a current by temperature coeffi cient, the following equation is used: the action of RFB and Q2. Nearly all of this current fl ows δV R 1 δV FFB=− ••TC or , through resistor RREF to form a ground-referred voltage. δT RNTC PS δT This voltage is fed into the fl yback error amplifi er. The −R 1 δV R fl yback error amplifi er samples this output voltage R = FB • • TC≈ FB TC δ δ δ information when the secondary side winding current is NVPS F / T T NPS zero. The error amplifi er uses a bandgap voltage, 1.23V, δ δ as the reference voltage. (VF/ T) = Diode’s forward voltage temperature coeffi cient The relatively high gain in the overall loop will then cause (δVTC/δT) = 2mV the voltage at the RREF resistor to be nearly equal to the bandgap reference voltage VBG. The relationship between VTC = 0.55V V and V may then be expressed as: FLBK BG The resistor value given by this equation should also be ⎛ V ⎞ V verifi ed experimentally, and adjusted if necessary to achieve α FLBK = BG ⎜ ⎟ or, optimal regulation overtemperature. ⎝ RFB ⎠ RREF ⎛ ⎞ ⎛ ⎞ The revised output voltage is as follows: RFB 1 VV= ⎜ ⎟ ⎜ ⎟ FLBK BG ⎝ R ⎠ ⎝ α⎠ ⎛ R ⎞ ⎛ 1 ⎞ REF VV= FB − V OUT BG ⎜ ⎟ ⎜ α⎟ F ⎝ RNREF⎠ ⎝ PS ⎠ α = Ratio of Q1 IC to IE, typically ≈ 0.986 ⎛ V ⎞ R V = Internal bandgap reference − ⎜ TC ⎟ •–()FB IESR BG ⎝ R ⎠ N α SEC TC PS

3575f 8 LT3575 APPLICATIONS INFORMATION

ERROR AMPLIFIER—DYNAMIC THEORY Selecting RFB and RREF Resistor Values

Due to the sampling nature of the feedback loop, there The expression for VOUT, developed in the Operation section, are several timing signals and other constraints that are can be rearranged to yield the following expression for RFB: required for proper LT3575 operation. RNVREF• PS⎣⎡() OUT+ V Fα + V TC ⎦⎤ R = Minimum Current Limit FB VBG The LT3575 obtains output voltage information from the where, SW pin when the secondary winding conducts current. The sampling circuitry needs a minimum amount of time VOUT = Output voltage to sample the output voltage. To guarantee enough time, VF = Switching diode forward voltage a minimum inductance value must be maintained. The α primary side magnetizing inductance must be chosen = Ratio of Q1, IC to IE, typically 0.986 above the following value: NPS = Effective primary-to-secondary turns ratio t ⎛088. µH⎞ LV≥=••MIN NV •• N⎜ ⎟ VTC = 0.55V PRI OUT PS OUT PS ⎝ ⎠ IMIN V The equation assumes the temperature coeffi cients of the diode and V are equal, which is a good fi rst-order t = minimum off-time, 350ns TC MIN approximation. IMIN = minimum current limit, 400mA Strictly speaking, the above equation defi nes RFB not as The minimum current limit is higher than that on the Elec- an absolute value, but as a ratio of RREF. So, the next trical Characteristics table due to the overshoot caused by question is, “What is the proper value for RREF?” The the comparator delay. answer is that RREF should be approximately 6.04k. The LT3575 is trimmed and specifi ed using this value of RREF. Leakage Inductance Blanking If the impedance of RREF varies considerably from 6.04k, When the output switch fi rst turns off, the fl yback pulse additional errors will result. However, a variation in RREF of appears. However, it takes a fi nite time until the transformer several percent is acceptable. This yields a bit of freedom primary side voltage waveform approximately represents in selecting standard 1% resistor values to yield nominal the output voltage. This is partly due to the rise time on RFB/RREF ratios. The RFB resistor given by this equation the SW node, but more importantly due to the trans- should also be verifi ed experimentally, and adjusted if former leakage inductance. The latter causes a very fast necessary for best output accuracy. voltage spike on the primary side of the transformer that Tables 1-4 are useful for selecting the resistor values for is not directly related to output voltage (some time is also RREF and RFB with no equations. The tables provide RFB, required for internal settling of the feedback amplifi er RREF and RTC values for common output voltages and circuitry). The leakage inductance spike is largest when common winding ratios. the power switch current is highest. Table 1. Common Resistor Values for 1:1 Transformers In order to maintain immunity to these phenomena, a fi xed VOUT (V) NPS RFB (kΩ) RREF (kΩ) RTC (kΩ) delay is introduced between the switch turn-off command 3.3 1.00 18.7 6.04 19.1 and the beginning of the sampling. The blanking is internally 5 1.00 27.4 6.04 28 set to 150ns. In certain cases, the leakage inductance may 12 1.00 64.9 6.04 66.5 not be settled by the end of the blanking period, but will 15 1.00 80.6 6.04 80.6 not signifi cantly affect output regulation. 20 1.00 107 6.04 105

3575f 9 LT3575 APPLICATIONS INFORMATION Table 2. Common Resistor Values for 2:1 Transformers predict output power. In addition, the winding ratio can VOUT (V) NPS RFB (kΩ) RREF (kΩ) RTC (kΩ) be changed to multiply the output current at the expense 3.3 2.00 37.4 6.04 18.7 of a higher switch voltage. 5 2.00 56 6.04 28 The graphs in Figures 1-3 show the maximum output 12 2.00 130 6.04 66.5 power possible for the output voltages 3.3V, 5V, and 12V. 15 2.00 162 6.04 80.6 The maximum power output curve is the calculated output power if the switch voltage is 50V during the off-time. To Table 3. Common Resistor Values for 3:1 Transformers achieve this power level at a given input, a winding ratio VOUT (V) NPS RFB (kΩ) RREF (kΩ) RTC (kΩ) value must be calculated to stress the switch to 50V, 3.3 3.00 56.2 6.04 20 resulting in some odd ratio values. The curves below are 5 3.00 80.6 6.04 28.7 examples of common winding ratio values and the amount 10 3.00 165 6.04 54.9 of output power at given input voltages. One design example would be a 5V output converter with Table 4. Common Resistor Values for 4:1 Transformers a minimum input voltage of 20V and a maximum input V (V) N R (kΩ) R (kΩ) R (kΩ) OUT PS FB REF TC voltage of 30V. A three-to-one winding ratio ﬁ ts this design 3.3 4.00 76.8 6.04 19.1 example perfectly and outputs close to ten watts at 30V 5 4.00 113 6.04 28 but lowers to eight watts at 20V.

Output Power TRANSFORMER DESIGN CONSIDERATIONS A fl yback converter has a complicated relationship between Transformer specifi cation and design is perhaps the most the input and output current compared to a buck or a critical part of successfully applying the LT3575. In addition boost. A boost has a relatively constant maximum input to the usual list of caveats dealing with high frequency current regardless of input voltage and a buck has a isolated power supply transformer design, the following relatively constant maximum output current regardless of information should be carefully considered. input voltage. This is due to the continuous nonswitching behavior of the two currents. A fl yback converter has both Linear Technology has worked with several leading magnetic discontinuous input and output currents which makes it component manufacturers to produce pre-designed fl yback similar to a nonisolated buck-boost. The duty cycle will transformers for use with the LT3575. Table 5 shows the affect the input and output currents, making it hard to details of several of these transformers.

14 14 14 MAXIMUM MAXIMUM MAXIMUM MAX P MAX P MAX P OUT OUTPUT OUT OUTPUT OUTPUT OUT 12 POWER 12 POWER 12 POWER 10:1 7:1 7:1 4:1 2:1 5:1 10 10 5:1 3:1 10 4:1 3:1 8 3:1 8 2:1 8 1:1

6 2:1 6 6 1:1

OUTPUT POWER (W) 4 OUTPUT POWER (W) 4 OUTPUT POWER (W) 4 1:1 2 2 2

0 0 0 0 5 1015 20 2530 35 40 45 0 5 1015 20 25 3035 40 45 0 5 1015 20 25 3035 40 INPUT VOLTAGE (V) INPUT VOLTAGE (V) INPUT VOLTAGE (V) 3575 F01 3573 F02 3573 F03

Figure 1. Output Power for 3.3V Output Figure 2. Output Power for 5V Output Figure 3. Output Power for 12V Output

3575f 10 LT3575 APPLICATIONS INFORMATION

Table 5. Predesigned Transformers—Typical Speciﬁ cations, Unless Otherwise Noted TARGET APPLICATION*

TRANSFORMER DIMENSION LPRI LLEAKAGE RPRI RSEC VO IO PART NUMBER (W × L × H) (mm) (μH) (nH) NP:NS (mΩ) (mΩ) VENDOR (V) (A) 750311306 15.24 × 13.3 × 11.43 100 1750 3:1 285 46 Würth Elektronik 12 1 750311307 15.24 × 13.3 × 11.43 100 2000 2:1 290 104 Würth Elektronik 24 0.5 750311308 15.24 × 13.3 × 11.43 100 2100 1:1 325 480 Würth Elektronik 24 0.5 750310564 15.24 × 13.3 × 11.43 63 450 3:1 115 50 Würth Elektronik ±5 1 750311303 15.24 × 13.3 × 11.43 50 800 5:1 106 13 Würth Elektronik 5 3 750311304 15.24 × 13.3 × 11.43 50 800 4:1 146 17 Würth Elektronik 5 3 750311305 15.24 × 13.3 × 11.43 50 1200 3:1 175 28 Würth Elektronik 12 1 PA2627NL 15.24 × 13.3 × 11.43 50 766 3:1 420 44 Pulse Engineering 3.3 3 750310471 15.24 × 13.3 × 11.43 25 350 3:1 57 11 Würth Elektronik 5 2 750310562 15.24 × 13.3 × 11.43 25 330 2:1 60 20 Würth Elektronik 12 0.8 750310563 15.24 × 13.3 × 11.43 25 325 1:1 60 60 Würth Elektronik 12 0.8 PA2364NL 15.24 × 13.3 × 11.43 25 1000 7:1 125 5.6 Pulse Engineering 3.3 1.5 PA2363NL 15.24 × 13.3 × 11.43 25 850 5:1 117 7.5 Pulse Engineering 5 1 PA2362NL 15.24 × 13.3 × 11.43 24 550 4:1 117 9.5 Pulse Engineering 3.3 1.5 PA2454NL 15.24 × 13.3 × 11.43 24 430 3:1 82 11 Pulse Engineering 5 1 PA2455NL 15.24 × 13.3 × 11.43 25 450 2:1 82 22 Pulse Engineering 12 0.5 PA2456NL 15.24 × 13.3 × 11.43 25 390 1:1 82 84 Pulse Engineering 12 0.3 750310559 15.24 × 13.3 × 11.43 24 400 4:1 51 16 Würth Elektronik 3.3 1.5 750311675 15.24 × 13.3 × 11.43 25 130 3:1 51 11 Würth Elektronik 5 2 750311342 15.24 × 13.3 × 11.43 15 440 2:1 85 22 Würth Elektronik 5 1.5 750311567 15.24 × 13.3 × 11.43 8 425 2:1 53 22 Würth Elektronik 5 2 750311422 17.7 × 14.0 × 12.7 50 574 5:1 80 8 Würth Elektronik 3.3 4 750311423 17.7 × 14.0 × 12.7 50 570 4:1 90 12 Würth Elektronik 5 2.4 750311457 17.7 × 14.0 × 12.7 50 600 4:1 115 12 Würth Elektronik 5 2.4 750311688 17.7 × 14.0 × 12.7 50 600 5:1 80 8 Würth Elektronik 3.3 4 750311689 17.7 × 14.0 × 12.7 50 600 4:1 115 12 Würth Elektronik 5 2.4 750311439 17.7 × 14.0 × 12.7 37 750 2:1 89 28 Würth Elektronik 12 1 PA2467NL 17.7 × 14.0 × 12.7 37 750 2:1 89 28 Pulse Engineering 12 1 PA2466NL 17.7 × 14.0 × 12.7 37 750 6:1 89 4.6 Pulse Engineering 3.3 4 PA2369NL 17.7 × 14.0 × 12.7 37 750 5:1 89 6.2 Pulse Engineering 5 2.5 750311458 17.7 × 14.0 × 12.7 15 175 3:1 35 6 Würth Elektronik 3.3 4 750311625 17.7 × 14.0 × 12.7 9 350 4:1 43 6 Würth Elektronik 3.3 4 750311564 17.7 × 14.0 × 12.7 9 120 3:1 36 7 Würth Elektronik 5 2.5 750311624 17.7 × 14.0 × 12.7 9 180 3:2 34 21 Würth Elektronik 15 1 *Target applications, not guaranteed

3575f 11 LT3575 APPLICATIONS INFORMATION Turns Ratio be required to avoid overvoltage breakdown at the output switch node. Transformer leakage inductance should be Note that when using an RFB/RREF resistor ratio to set output voltage, the user has relative freedom in selecting minimized. a transformer turns ratio to suit a given application.In An RCD (resistor capacitor diode) clamp, shown in contrast, simpler ratios of small integers, e.g., 1:1, 2:1, Figure 4, is required for most designs to prevent the 3:2, etc., can be employed to provide more freedom in leakage inductance spike from exceeding the breakdown setting total turns and mutual inductance. voltage of the power device. The ﬂ yback waveform is Typically, the transformer turns ratio is chosen to maximize depicted in Figure 5. In most applications, there will be a available output power. For low output voltages (3.3V or 5V), very fast voltage spike caused by a slow clamp diode that a N:1 turns ratio can be used with multiple primary windings may not exceed 60V. Once the diode clamps, the leakage relative to the secondary to maximize the transformer’s inductance current is absorbed by the clamp capacitor. current gain (and output power). However, remember that This period should not last longer than 150ns so as not to the SW pin sees a voltage that is equal to the maximum interfere with the output regulation, and the voltage during input supply voltage plus the output voltage multiplied by this clamp period must not exceed 55V. The clamp diode the turns ratio. This quantity needs to remain below the turns off after the leakage inductance energy is absorbed ABS MAX rating of the SW pin to prevent breakdown of and the switch voltage is then equal to: the internal power switch. Together these conditions place VSW(MAX) = VIN(MAX) + N(VOUT + VF) an upper limit on the turns ratio, N, for a given application. This voltage must not exceed 50V. This same equation Choose a turns ratio low enough to ensure: also determines the maximum turns ratio. 50VV – N < IN() MAX When choosing the snubber network diode, careful VV+ attention must be paid to maximum voltage seen by the OUT F SW pin. Schottky diodes are typically the best choice to For larger N:1 values, a transformer with a larger physical be used in the snubber, but some PN diodes can be used size is needed to deliver additional current and provide a if they turn on fast enough to limit the leakage inductance large enough inductance value to ensure that the off-time is spike. The leakage spike must always be kept below 60V. long enough to accurately measure the output voltage. Figures 6 and 7 show the SW pin waveform for a 24VIN, For lower output power levels, a 1:1 or 1:N transformer can 5VOUT application at a 1A load current. Notice that the be chosen for the absolute smallest transformer size. A 1: leakage spike is very high (more than 65V) with the “bad” N transformer will minimize the magnetizing inductance diode, while the “good” diode effectively limits the spike (and minimize size), but will also limit the available output to less than 55V. power. A higher 1:N turns ratio makes it possible to have An alternative to RC network is a Zener diode clamping. very high output voltages without exceeding the breakdown The Zener diode must be able to handle the voltage rating voltage of the internal power switch. and power dissipating during the switch turn-off time. Application Note 19 has more details on Zener diode Leakage Inductance snubber design for ﬂ yback converters. Transformer leakage inductance (on either the primary or For applications with SW voltage exceeding 50V, secondary) causes a voltage spike to appear at the primary Zener diode clamp must be considered. At higher operating after the output switch turns off. This spike is increasingly primary current, the leakage inductance spike can prominent at higher load currents where more stored energy potentially exceed the breakdown voltage of the internal must be dissipated. In most cases, a snubber circuit will power switch.

3575f 12 LT3575 APPLICATIONS INFORMATION

LS VSW < 60V

C R < 55V < 50V

CLAMP EITHER D ZENER OR RC

tOFF > 350ns

TIME 3575 F05 3575 F04 tSP < 150ns Figure 4. Snubber Clamping Figure 5. Maximum Voltages for SW Pin Flyback Waveform

10V/DIV 10V/DIV

3575 F06 3575 F07 100ns/DIV 100ns/DIV

Figure 6. Good Snubber Diode Limits SW Pin Voltage Figure 7. Bad Snubber Diode Does Not Limit SW Pin Voltage

3575f 13 LT3575 APPLICATIONS INFORMATION

Secondary Leakage Inductance The Switch Current Limit vs RILIM plot in the Typical In addition to the previously described effects of leakage Performance Characteristics section depicts a more inductance in general, leakage inductance on the secondary accurate current limit. in particular exhibits an additional phenomenon. It forms Undervoltage Lockout (UVLO) an inductive divider on the transformer secondary that effectively reduces the size of the primary-referred The SHDN/UVLO pin is connected to a resistive voltage ﬂ yback pulse used for feedback. This will increase the divider connected to VIN as shown in Figure 8. The voltage output voltage target by a similar percentage. Note that threshold on the SHDN/UVLO pin for VIN rising is 1.22V. unlike leakage spike behavior, this phenomenon is load To introduce hysteresis, the LT3575 draws 2.8μA from the independent. To the extent that the secondary leakage SHDN/UVLO pin when the pin is below 1.22V. The hysteresis inductance is a constant percentage of mutual inductance is therefore user-adjustable and depends on the value of (over manufacturing variations), this can be accommodated R1. The UVLO threshold for VIN rising is: by adjusting the RFB/RREF resistor ratio. 122.•()VR 1+ R 2 VIN(, UVLO RISING )= + 28.•µA R 1 Winding Resistance Effects R2

Resistance in either the primary or secondary will reduce The UVLO threshold for VIN falling is: overall efficiency (POUT/PIN). Good output voltage + = 122.•()VR 1 R 2 regulation will be maintained independent of winding VIN(, UVLO FALLING ) resistance due to the boundary mode operation of the R2 LT3575. To implement external run/stop control, connect a small NMOS to the UVLO pin, as shown in Figure 8. Turning the Bifi lar Winding NMOS on grounds the UVLO pin and prevents the LT3575 A bifi lar, or similar winding technique, is a good way to from operating, and the part will draw less than a 1μA of minimize troublesome leakage inductances. However, quiescent current. remember that this will also increase primary-to-secondary V capacitance and limit the primary-to-secondary breakdown IN voltage, so, bifi lar winding is not always practical. The R1

Linear Technology applications group is available and SHDN/UVLO extremely qualiﬁ ed to assist in the selection and/or design of the transformer. RUN/STOP LT3575 R2 CONTROL (OPTIONAL) Setting the Current Limit Resistor GND The maximum current limit can be set by placing a resistor 3575 F08 between the RILIM pin and ground. This provides some ﬂ exibility in picking standard off-the-shelf transformers that Figure 8. Undervoltage Lockout (UVLO) may be rated for less current than the LT3575’s internal power switch current limit. If the maximum current limit is needed, use a 10k resistor. For lower current limits, the following equation sets the approximate current limit: 3 RAIkILIM=−+65•(. 10 3 5 LIM ) 10

3575f 14 LT3575 APPLICATIONS INFORMATION Minimum Load Requirement schematics in the Typical Applications section for other possible values). If too large of an R value is used, the part The LT3575 obtains output voltage information through C will be more susceptible to high frequency noise and jitter. If the transformer while the secondary winding is conducting too small of an R value is used, the transient performance current. During this time, the output voltage (multiplied C will suffer. The value choice for C is somewhat the inverse times the turns ratio) is presented to the primary side of C of the R choice: if too small a C value is used, the loop the transformer. The LT3575 uses this refl ected signal to C C may be unstable, and if too large a C value is used, the regulate the output voltage. This means that the LT3575 C transient performance will also suffer. Transient response must turn on every so often to sample the output voltage, plays an important role for any DC/DC converter. which delivers a small amount of energy to the output. This sampling places a minimum load requirement on the Design Example output of 1% to 2% of the maximum load. The following example illustrates the converter design A Zener diode with a Zener breakdown of 20% higher process using LT3575. than the output voltage can serve as a minimum load if pre-loading is not acceptable. For a 5V output, use a 6V Given the input voltage of 20V to 28V, the required output Zener with cathode connected to the output. is 5V, 1A. VIN(MIN) = 20V, VIN(MAX) = 28V, VOUT = 5V, VF = 0.5V BIAS Pin Considerations and IOUT = 1A For applications with an input voltage less than 15V, the 1. Select the transformer turns ratio to accommodate BIAS pin is typically connected directly to the VIN pin. For the output. input voltages greater than 15V, it is preferred to leave the The output voltage is refl ected to the primary side by a BIAS pin separate from the VIN pin. In this condition, the BIAS pin is regulated with an internal LDO to a voltage of factor of turns ratio N. The switch voltage stress VSW is 3V. By keeping the BIAS pin separate from the input voltage expressed as: at high input voltages, the physical size of the capacitors N N = P can be minimized (the BIAS pin can then use a 6.3V or N 10V rated capacitor). S VVNVVV=+()50 +< SW() MAX IN OUT F Overdriving the BIAS Pin with a Third Winding Or rearranged to: The LT3575 provides excellent output voltage regulation without the need for an optocoupler, or third winding, but 50 − V N < IN() MAX for some applications with higher input voltages (>20V), ()VV+ it may be desirable to add an additional winding (often OUT F called a third winding) to improve the system effi ciency. On the other hand, the primary side current is multiplied by For proper operation of the LT3575, if a winding is used as the same factor of N. The converter output capability is: a supply for the BIAS pin, ensure that the BIAS pin voltage is at least 3.15V and always less than the input voltage. =−1 IDNIOUT() MAX08.•( 1 )• PK For a typical 24VIN application, overdriving the BIAS pin 2 will improve the effi ciency gain 4-5%. NV()+ V D = OUT F VN+ (()VV+ Loop Compensation IN OUT F The LT3575 is compensated using an external resistor- capacitor network on the VC pin. Typical values are in the range of RC = 50k and CC = 1.5nF (see the numerous 3575f 15 LT3575 APPLICATIONS INFORMATION The transformer turns ratio is selected such that the Table 7.Switching Frequency at Different Primary converter has adequate current capability and a switch Inductance at IPK stress below 50V. Table 6 shows the switch voltage stress fSW AT VIN(MIN) fSW AT VIN(MAX) L (μH) (kHz) (kHz) and output current capability at different transformer 15 174 205 turns ratio. 30 87 103 Table 6. Switch Voltage Stress and Output Current Capability vs 60 44 51 Turns-Ratio Note: The switching frequency is calculated at maximum output. VSW(MAX) AT VIN(MAX) IOUT(MAX) AT VIN(MIN) DUTY CYCLE N (V) (A) (%) In this design example, the minimum primary inductance is 1:1 33.5 1.26 16~22 used to achieve a nominal switching frequency of 200kHz at 2:1 39 2.07 28~35 full load. The 750311458 from Würth Elektronik is chosen 3:1 44.5 2.63 37~45 as the fl yback transformer. 4:1 50 3.05 44~52 Given the turns ratio and primary inductance, a custom- BIAS winding turns ratio is selected to program the BIAS ized transformer can be designed by magnetic component voltage to 3V~5V. The BIAS voltage shall not exceed the manufacturer or a multi-winding transformer such as a input voltage. Coiltronics Versa-Pac may be used. The turns ratio is then selected as primary: secondary: 3. Select the output diodes and output capacitor. BIAS = 3:1:1. The output diode voltage stress VD is the summation of 2. Select the transformer primary inductance for target the output voltage and refl ection of input voltage to the switching frequency. secondary side. The average diode current is the load current. The LT3575 requires a minimum amount of time to sample V the output voltage during the off-time. This off-time, =+IN VVD OUT tOFF(MIN), shall be greater than 350ns over all operating N conditions. The converter also has a minimum current limit, The output capacitor should be chosen to minimize the IMIN, of 400mA to help create this off-time. This defi nes the minimum required inductance as defi ned as: output voltage ripple while considering the increase in size and cost of a larger capacitor. The following equation NV()+ V L = OUT F • t calculates the output voltage ripple. MIN I OFF() MIN MIN LI 2 ΔV = PK The transformer primary inductance also affects the MAX 2CV OUT switching frequency which is related to the output ripple. If above the minimum inductance, the transformer’s primary 4. Select the snubber circuit to clamp the switch inductance may be selected for a target switching frequency voltage spike. range in order to minimize the output ripple. A fl yback converter generates a voltage spike during switch The following equation estimates the switching frequency. turn-off due to the leakage inductance of the transformer. In order to clamp the voltage spike below the maximum 11 f = = rating of the switch, a snubber circuit is used. There are SW + ttON OFF IPK + IPK many types of snubber circuits, for example R-C, R-C-D and + VIN NVPS() OUT V F L L

3575f 16 LT3575 APPLICATIONS INFORMATION

Zener clamps. Among them, RCD is widely used. Figure 9 RTC resistor for temperature compensation of the output shows the RCD snubber in a ﬂ yback converter. voltage. RREF is selected as 6.04k.

A typical switch node waveform is shown in Figure 10. A small capacitor in parallel with RREF fi lters out the During switch turn-off, the energy stored in the leakage noise during the voltage spike, however, the capacitor inductance is transferred to the snubber capacitor, and should limit to 10pF. A large capacitor causes distortion eventually dissipated in the snubber resistor. on voltage sensing. VV(•)− NV 6. Optimize the compensation network to improve the 1 2 = C C OUT LISPKSW f transient performance. 2 R The transient performance is optimized by adjusting the The snubber resistor affects the spike amplitude VC and compensation network. For best ripple performance, select duration tSP, the snubber resistor is adjusted such that a compensation capacitor not less than 1.5nF, and select tSP is about 150ns. Prolonged tSP may cause distortion a compensation resistor not greater than 50k. to the output voltage sensing. 7. Current limit resistor, soft-start capacitor and UVLO The previous steps fi nish the fl yback power stage design. resistor divider

5. Select the feedback resistor for proper output voltage. Use the current limit resistor RLIM to lower the current Using the resistor Tables 1-4, select the feedback resistor limit if a compact transformer design is required. Soft-start RFB, and program the output voltage to 5V. Adjust the capacitor helps during the start-up of the ﬂ yback converter . Select the UVLO resistor divider for intended input operation range. These equations are aforementioned. LS

C R VC NVOUT

VIN

3575 F10 tSP

3575 F09

Figure 9. RCD Snubber in a Flyback Converter Figure 10. Typical Switch Node Waveform

3575f 17 LT3575 TYPICAL APPLICATIONS

Low Input Voltage 5V Isolated Flyback Converter

D1 + VIN 3:1 VOUT 5V C1 5V, 700mA R1 R8 10μF C6 T1 C5 200k 2.6μH VIN 0.22μF 1k 24μH 47μF SHDN/UVLO – R2 VOUT D2 90.9k R3 80.6k LT3575 RFB RREF R4 6.04k TC

RILIM SW SS VC GNDTEST BIAS R6 R5 R7 28.7k 10k 4.53k V IN T1: PULSE PA2454NL C2 C3 D1: PDS835L 10nF 33nF D2: PMEG6010 C5: MURATA, GRM32ER71A476K 3575 TA02

±12V Isolated Flyback Converter

D1 + VIN 2:1:1 VOUT1 5V C1 12V, 200mA 10μF R1 C6 R8 T1 C5 8.3μH 200k VIN 0.22μF 1k 33.2μH 47μF SHDN/UVLO V – R2 OUT1 D3 D2 90.9k R3 V + 118k OUT2 LT3575 RFB C6 8.3μH RREF 47μF R4 – 6.04k VOUT2 TC –12V, 200mA

RILIM SW SS VC GNDTEST BIAS R6 R5 R7 59k 10k 4.99k VIN C2 C3 10nF 0.1μF T1: COILTRONICS VPH2-0083-R D1, D2: PDS540 D3: PMEG6010 C5, C6: MURATA, GRM32ER71A476K 3575 TA03

3575f 18 LT3575 TYPICAL APPLICATIONS

5V Isolated Flyback Converter

VIN D1 + 3:1:1 VOUT 12V TO 24V 5V, 1.4A (*30V) C1 C6 R8 10μF R1 T1 C5 0.22μF 1k 2.6μH 499k VIN 24μH 47μF SHDN/UVLO – R2 D3 VOUT 71.5k R3 80.6k R LT3575 FB RREF R4 6.04k TC

RILIM SW SS VC GNDTEST BIAS

D2 R6 R5 R7 28.7k 10k 11.5k *OPTIONAL THIRD C2 C4 WINDING FOR 10nF 4.7μF L1C C3 2.6μH 30V OPERATION 4700pF

3575 TA04 T1: PULSE PA2454NL OR WÜRTH ELEKTRONIK 750310471/750311675 D1: PDS835L D3: PMEG6010 C5: MURATA, GRM32ER71A476K

Efﬁ ciency

90 VIN = 24V 80 V = 12V 70 IN

EFFICIENCY (%) 30

0 0 0.2 0.40.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 IOUT (A) 3575 TA04b

3575f 19 LT3575 TYPICAL APPLICATIONS

3.3V Isolated Flyback Converter

V D1 IN 4:1:1 V + 12V TO 24V OUT 3.3V, 1.5A (*36V) C1 R1 C6 R8 10μF T1 C5 499k 0.22μF 1k 1.5μH VIN 24μH 47μF SHDN/UVLO – R2 D3 VOUT 71.5k R3 76.8k R LT3575 FB RREF R4 6.04k TC

RILIM SW SS VC GNDTEST BIAS

D2 R6 R5 R7 19.1k 10k 4.99k *OPTIONAL THIRD C2 C3 C4 L1C WINDING FOR 10nF 15nF 4.7μF 1.5μH 36V OPERATION

3575 TA05 T1: PULSE PA2362NL OR WÜRTH ELEKTRONIK 750310559 D1: PDS835L D3: PMEG6010

3575f 20 LT3575 TYPICAL APPLICATIONS

12V Isolated Flyback Converter

D1 VIN 3:1 VOUT 12V 12V, 700mA C1 R1 C6 R8 10μF T1 C5 499k 0.22μF 1k 4.5μH VIN 47μF SHDN/UVLO 40.5μH R2 V – 71.5k D2 OUT

LT3575 R FB R3 178k

RREF R4 TC 6.04k RILIM SS SW VC GNDTEST BIAS R6 R5 R7 7.87k 59k 10k VIN C2 C3 10nF 22nF T1: COILTRONICS VP3-0055-R 3575 TA06 D1: PDS835L D2: PMEG6010

3575f 21 LT3575 TYPICAL APPLICATIONS

Four Output 12V Isolated Flyback Converter

D1 + VIN 2:1:1:1:1 VOUT1 12V TO 24V 12V, 120mA C1 C6 R8 T1 C5 10μF 0.22μF 1k 8.3μH R1 VIN 33.2μH 47μF 499k – VOUT1 D5 D2 + SHDN/UVLO VOUT2 R2 R3 12V, 120mA 71.5k 8.3μH C6 118k 47μF LT3575 R FB – VOUT2 RREF D3 TC R4 + 6.04k VOUT3 RILIM 12V, 120mA 8.3μH C7 SS SW 47μF – VC GNDTEST BIAS VOUT3 D4 R6 R5 + R7 VOUT4 59k 10k 10k V 12V, 120mA IN C8 C2 C3 8.3μH 47μF 10nF 0.1μF – VOUT4

T1: COILTRONICS VPH2-0083-R 3575 TA07 D1-D4: PDS540 D5: PMEG6010

3575f 22 LT3575 PACKAGE DESCRIPTION FE Package 16-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663) Exposed Pad Variation BA

4.90 – 5.10* 2.74 (.193 – .201) (.108) 2.74 (.108) 16 1514 13 12 1110 9

6.60 ±0.10 2.74 4.50 ±0.10 (.108) SEE NOTE 4 2.74 6.40 (.108) (.252) 0.45 ±0.05 BSC

1.05 ±0.10

0.65 BSC RECOMMENDED SOLDER PAD LAYOUT 1342 5 6 7 8 1.10 4.30 – 4.50* (.0433) (.169 – .177) 0.25 MAX REF 0° – 8°

0.65 0.09 – 0.20 0.50 – 0.75 (.0256) 0.05 – 0.15 (.0035 – .0079) (.020 – .030) BSC (.002 – .006) 0.195 – 0.30 FE16 (BA) TSSOP 0204 (.0077 – .0118) TYP NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE MILLIMETERS FOR EXPOSED PAD ATTACHMENT 2. DIMENSIONS ARE IN (INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH 3. DRAWING NOT TO SCALE SHALL NOT EXCEED 0.150mm (.006") PER SIDE

3575f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 23 LT3575 TYPICAL APPLICATION

13V to 30VIN, +5V/–5VOUT Isolated Flyback Converter

T1 D1 + VIN 3:1:1:1 VOUT 13V TO 30V +5V, 500mA C6 R8 C1 R1 0.22μF 1k L1A L1B C5 10μF VIN 499k 63μH 7μH 47μF

SHDN/UVLO D4 COM R2 L1C R3 C6 64.9k 7μH 47μF LT3575 80.6k D2 RFB – VOUT RREF –5V, 500mA TC R4 6.04k RILIM SS SW VC GNDTEST BIAS *OPTIONAL THIRD WINDING FOR R5 R6 R7 D3 >24V OPERATION 28.7k 10k 7.68k C2 C3 C4 L1D T1: WÜRTH ELEKTRONIK 750310564 10nF 15nF 4.7μF 7μH D4: PMEG6010 D1, D2: PDS835L

3575 TA11

RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT3574/LT3573 40V Isolated Flyback Converters Monolithic No-Opto Flybacks with Integrated 0.65A / 1.25A 60V Switch LT3957/LT3958 40V/100V Flyback, Boost Converters Monolithic with Integrated 5A/3.3A Switch LT3757/LT3758 40V/100V Flyback, Boost Controllers Universal Controllers with Small Package and Powerful Gate Drive LT1737/LT1725 20V Isolated Flyback Controller No Opto-Isolator or Third Winding Required LT3825/LT3837 Isolated Synchronous Flyback Controllers No Opto-Isolator or Third Winding Required ® LTC 3803/LTC3803-3 200kHz/300kHz Flyback DC/DC Controllers VIN and VOUT Limited Only by External Components LTC3803-5

LTC3805/LTC3805-5 Adjustable Frequency Flyback Controllers VIN and VOUT Limited Only by External Components

3575f Linear Technology Corporation LT 0710 • PRINTED IN USA 24 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2010