Dr. Martin Bader, Executive Vice President, Unaxis Semiconductors and President Unaxis North America

Dear Readers Welcome to this new edition of Chip! I hope you had a good start to 2002 and that this year will be successful for all of us! The past year was tough on our industry and no one has escaped unscathed. Unaxis Semiconductors is no exception, as revenues were below original expectations. However, we still remained profitable with sales close to 2000 figures. The market situation has not been favorable but appears to have bottomed out now. I believe the first two quarters in 2002 will be challenging, but we anticipate the upswing in the second half of the year. In the meantime, our efforts are concentrated fully on R&D and further quality improvement of our products and services. Despite difficult market conditions, Unaxis Semiconductors did not reduce its R&D budget last year. On the contrary, a substantially higher amount was allocated to R&D in 2001. Our focus lies on new 300 mm products like the CLUSTERLINE® 300 (p. 47), the new LEPP 300 (p. 27), and a completely new system for the advanced packaging market that will be presented in the next edition of Chip. Unaxis investments will reach record levels in 2002 – mainly to improve laboratory facilities, and for construction of a new manufacturing cleanroom in Truebbach, Switzerland. The MEMS market seems to be expanding in the automotive and computer peripheral industries, while entering a more active phase particularly in the telecommunications and biomedical fields. In response to the current active interest in this subject, a whole section of this issue of Chip has been devoted to this technology (p. 8 – 21). The new Quality Management System is ready (p. 4) and Unaxis Semiconductors is preparing for the ISO 9001 re-certification at the end of February in Truebbach. All Unaxis Semiconductor sites worldwide will be ISO-certified by the first quarter of 2003. Following last year’s customer opinion survey, some significant improvements are on the way, especially in the area of customer relationship management and the sales and service organization (p. 6).

editorial I hope that you find Chip 6 informative and a pleasure to read, and we welcome your feedback (see Reply Card p. 46, or [email protected]). On behalf of Unaxis Semiconductors, I wish you enjoyable reading.

Dr. Martin Bader editorial

Unaxis Chip Lab on a CD Unaxis Insights Microlaboratories on The Making of a Worldwide a standard CD form 8 factor could be used Quality Management System 4 to run laboratory Creating Customer Value processes (image: Combining the power of sales and service 6 GyrosMicrolabs). Events 57

Telecom Mad about MEMS New growth for the semiconductor industry 8 Asia Pacific Microsystems The MEMS pioneer in Taiwan 12 MEMS Technology for Telecommunication 20 A massive increase in the demand for more bandwidth Scanning electron speeds up development. 14 microscope picture of a test structure for MEMS – a Playground for arrayed waveguide that New Thin Film Materials 17 shows the patterned Unaxis Supports DWDM with PECVD and RIE SiO2 fibers fanning out from a common DWDM (Densed Wavelength Division Multiplexed) input/output channel. will provide the solution for unlimited bandwidth. 20 Dry Etching InP for Multiple Applications New etching systems can accommodate numerous applications. 22 contents contents

Chip Unaxis Advanced Silicon LEPECVD Provides High-Quality Virtual Substrates for Ge-rich SiGe p-MOSFETs 24 30 LEPP 300 The Unaxis SIRIUS UHV-CVD system The extention of the CLUSTERLINE® 300 concept for PECVD processing 27 Customer-Oriented Process Development for SiGe Deposition Outlining the advantages of the SIRIUS UHV-CVD system for deposition of HBTs and other SiGe/Si structures 30 New Trends in SiGe Technology 41 Carbon-doped heterojunction bipolar transistors – Motorola Accompli™ 009 enhancing the capability of SiGe technology 33 New wireless devices The Photomask Success Story for the end user market Recent introduction of the new Unaxis MASK ETCHER IIITM would allow products like web tablets, ICP dry etch system caused a revolution in the global wearable computing, photomask industry. 36 or telematic devices to

Non-volatile Memory: the Key to become as common in contents our daily lives as mobile Advanced Memory Devices phones are today FRAM, MRAM, and OUM – which memory technology (image: Motorola). will win the day? 41 Money for Nothing … and Chips for Free Reducing initial target costs and increasing material utilization on the Unaxis CLUSTERLINE® 45 contents Advanced Packaging CLUSTERLINE® – Making 300 mm Possible 47 CLUSTERLINE® 300 The transition to 300 mm wafer processing The new Unaxis has been accomplished. 47 CLUSTERLINE® 300 The Advantages of Integrated Passives is being implemented in the first 300 mm IPDs (Integrated Passive Devices) are a booming area wafer bumping fab of advanced packaging. 51 of one of the world’s APiA – the New Alliance for largest providers of semiconductor Advanced Packaging Solutions 55 packaging and testing services.

Unaxis Chip Unaxis Insights

Creating Customer Value Combining the Power of Sales and Service

Ernst Gloor (left) and Ralf Kuhlmann (center) have been interviewed by Jürg Steinmann, Global Communications Manager Unaxis Semiconductors.

Chip interview with Ralf Kuhlmann, International Sales & Market Manager, and Ernst Gloor, General Manager Customer Support

Chip: Mr. Kuhlmann, in September 2001, you have taken on a new challenge. You are now responsible for the global Sales & Service organization of the Semiconductor Division of Unaxis. What is your analysis after the first six months? Kuhlmann: The time has passed incredibly quickly and a lot has happened. When I started, the market situation was really challenging, to say the least: a lot of quick decisions had to be taken. This led to decisive action within our Sales & Service Organization. Facing the volatile state of the current market situation, we need to increasingly concentrate on our strategic market segments, core activities, and our own strengths. I see potential for improvement in the partnership with our customers. Individual customer care will receive our We have taken a clear decision to manage Excellence Model (see article on page 4). special attention. The Sales & Service sales and customer support as one This has already led to visible results in the Organization needs to be much more organizational unit. We are convinced regional organizational structures and in conscious of its leadership role in that this is the only way to give our our sales and service operations. customer relationship management. customers the full benefit of the synergies Leaner structures have been between all sales and customer support established in some market segments, Chip: Have there been major activities. like the USA and Europe. A good changes already? example is the central coordination Kuhlmann: The most obvious change Gloor: We have already started the rollout and steering of the service teams with is also reflected in this interview situation: of the system sales and customer support regional responsibility. At the same interview we now feature as a “double pack”. processes defined by our Business time, our hotline and the availability of sales and service – in particular our reaction time for emergencies – will be “The Sales & Service Organization further improved. Our service contracts with customers in the USA and Europe needs to be much more conscious guarantee around-the-clock availability. of its leadership role in customer The experiences from these two markets will also be applied to the Asian markets relationship management.” at a later date. interview

6 | Chip Unaxis “I found a strong, highly motivated team, and we are well positioned in most market segments.”

sales support will be coordinated globally. already do. Our task will be to create an The product groups will be actively environment for independent, self-reliant involved and provide strong backup for decision making, and a culture of the internationally acting KAM. Only by empowerment. A better use of existing setting such clear responsibilities, we communication, information and can insure total customer care and that management tools will be a prime focus. resources are shared efficiently. The global KAM teams will have increased business Gloor: Classic field service will be responsibility and act as the interface extended considerably. As part of a between customer, product groups, service package, we will also offer our supply chain, and logistics. customers the possibility of having their Unaxis parts supply managed directly at Gloor: We have taken on the challenge their own premises. Thus, Unaxis insures to supply the complete service chain that parts and consumables in stock are as a one-stop solution provider for tailored exactly to the customers’ needs.

semiconductor technologies: from The improved parts supply management interview consulting and project planning to the will help achieve a higher up-time of implementation of complex process and installed systems. manufacturing lines. Our new Key A recently conducted customer Closer customer relationship ½ Global Key Account Managers Account Management needs to be well satisfaction survey confirms our decision for each customer plus prepared to fulfill this central role. to take this route. The response from our dedicated Lead Engineers Together with the introduction of customers also clearly shows the areas ½ Flexible and efficient sales and the KAM, Lead Engineers are being where we need to improve. We at Unaxis service teams who work appointed to cover technical support consider this a unique opportunity to closely with our customers at the customer location. come to the best possible solution – interview Enhanced level of service together with our customers. ½ 24 h hotline in Europe and Chip: What are the next steps? the USA based on a service contract, implementation Kuhlmann: The operational business in Asia at a later date processes are still too complex in some Markets ½ Higher competence of the areas and not always focused on the sales and service specialists needs of our customers. Here, we need through intensified product to simplify systematically to increase and process cross-training our efficiency. service product portfolio We are clearly dedicated to Business parts Global sales & market Chip: How will this affect customer Excellence according to ISO 9001/EFQM training Sales strategies relations, and how will the customer and need to continually work on KAM and market management develop improvements. Our benchmark can only (Key Account Mgmt.) in the future? be the top performers in our markets. CRM Kuhlmann: In addition to our existing I found a strong, highly motivated team, (Customer Relationship Mgmt.) systems and project business, we will and we are well positioned in most market re-focus strongly on Key Account segments. We know the demands put Customer Product installation Management (KAM). From now on, the upon the teams of our Sales & Service Support Groups previously mostly regional customer and Organization and what a great job they

Unaxis Chip | 7 Telecom

Lab on a CD Microlaboratories on a standard CD form factor Mad about MEMS could be used to run routine or non-routine laboratory processes. Hundreds of samples can New Growth For Semiconductor Industry be processed in parallel on the disposable CDs (image: Gyros Microlabs).

MEMS Defined: Micro Electro Mechanical Systems. MICRO indicates that these systems are very small. They have micron- sized features. ELECTRO- MECHANICAL suggests motors, pivots, links, switches, gears, and actuators. SYSTEMS suggests a set of functions related to a goal or purpose. MEMS are used to sense and manipulate the physical environment by responding to various kinds of input – chemical, light, pressure, vibration, and acceleration.

Valerie Thomson, Technical Journalist, Zurich the automotive industry, such as actuators carrier-grade MEMS-based devices for airbags, or to the computing peripheral for use in optical switches, while Tiny, low-power hearing implants, sector, such as inkjet printer heads and Switzerland’s Sysmelec SA is making miniature test tubes – so small that an storage devices. automation tools for assembling optical entire laboratory can fit on a postage In the past few years, using materials components, and Colibrys SA is stamp-sized piece of glass, cheap such as ceramic, plastic, metals, quartz, automating production for its high-quality sensors that detect hazardous chemical and even diamonds, engineers are optical MEMS components. agents, and chip-sized packaging for moving the use of MEMS beyond its The fast-growing biomedical sector is devices that contain thousands of tiny current niche markets. The technology also proving to be a market for MEMS mirrors to switch telephone traffic at the is increasingly being used by the technology. New implantable devices are speed of light are some of the systems telecommunications equipment industry of great interest for treating specific being developed that exploit Micro Electro where makers of optical switches, tunable diseases (e.g. chronic pain and Mechanical Systems (MEMS) technology. lasers, attenuators and filters see MEMS Parkinson’s). Micromachined components, MEMS is being used in a much wider as a cost-efficient solution in the field of with their small size and low power range of industries than expected. optical networking. Sercalo Microsystems consumption, are ideal in this application. Historically, MEMS use was limited to of Liechtenstein, for example, sells Companies such as Medtronic

8 | Chip Unaxis (Minnesota) are working on implants the right combination of expertise and for treating vascular disease, tremors, manufacturing capacity. It now leads and neurological conditions. that market, while other semiconductor Plastics vendors, for example, are industry players, Motorola, VTI Hamlin, already prototyping biochips created and Sensanor, share the rest of a market using the same nozzle plates used to estimated to be about half a billion dollars make inkjet printers. Prototypes exist, this year. created by the likes of Applied It should be noted however that MicroSWISS, such as grippers, tweezers, MEMS processes are more demanding. saw blades, and plane iron tools. Such Indeed, lithography performance is more tools enable things like minimal invasive advanced than is customary for an IC surgery, making recovery faster and safer foundry, points out Eric Mounier of Yole Accelerometer for patients undergoing operations. Developpement of Lyons, a company that “Every foundry has its own particular One of the latest Even household names, such as has just published a report about MEMS way of making MEMS, using different accelerometer systems, including Electrolux-AEG, Bosch, Siemens, manufacturing, entitled FABEurope. materials and different processes, and ASIC, sensor and Whirlpool, Bauknecht, Miele, and Philips, At the end of 2000 in Europe there were although there are plenty of foundries, not MEMS packaging, are working with MEMS vendors to make 8 MEMS-specific foundries, 7 integrated all have the capability of making MEMS used in car airbags smarter and more efficient appliances. optics foundries, and 4 wafers foundries for all applications – from biomedical to (image: Colibrys) announced or extended, according to telecom applications. Typically, in Europe, Semiconductor industry’s know-how Yole Developpement. Including integrated MEMS facilities concentrate on a limited in demand for MEMS optics and wafers, along with MEMS- number of MEMS products for different The micromachining industry got its related foundries, there are more than markets,” says Yole Developpement first hint of a bigger and alternative 150 foundries in Europe, as Yole’s strategist, Eric Mounier. market to its traditional integrated circuit research shows. About 80 percent of the processes or semiconductor market back in the Because of the limited availability come from semiconductors and 20 percent seventies when bulk-etched silicon wafers of MEMS foundries, however, major are unique to MEMS (Table 1). Four were used to produce pressure sensors. equipment manufacturers, especially in semiconductor processes are in use for Then came the demand for polysilicon the telecommunication sector, have been MEMS production today. MEMS specific actuators used in hard disk drives. buying such foundries to ensure product The semiconductor industry is seeing supply; for example, Alcatel acquired the its know-how and much of its capital Scottish MEMS foundry, and Kymata and Table 1: Overview of selected MEMS equipment being exploited in ways Analog Devices acquired the Irish MEMS manufacturing processes that it had not imagined as existing maker BCO Technologies. Manufacturing Techniques Products microelectronics manufacturing processes MEMS foundries, like semiconductor and infrastructure are used to enable mass foundries, can be more cost-effective Surface IC semiconductors Actuators and electro- fabrication of MEMS. For example Karl than internal manufacturing, but MEMS micromachining static motors Suss, who used to generate most of its foundries are constrained by a need to Bulk Etch techniques Mirrors and accelerators revenue from the semiconductor industry be highly flexible and expandable. A micromachining for airbags but has now become a major supplier standard IC foundry performs one or two Electro discharge Machine shop Conductive materials to the MEMS industry. standard processes, but a MEMS foundry micromachining techniques Semiconductor industry giant Analog performs a wide variety of processes, LIGA Lithography Electrostatic motors Devices began supplying accelerometers such as bulk, surface, and nontraditional and electroplating and gears, telecoms, and defense sector to the auto industry because it had processes.

Unaxis Chip | 9 Optoelectronics for telecommunications Telecommunications equipment manufacturers are experimenting with optoelectronics devices with shutters for high- speed fiber-optic switches (image: Colibrys).

packaging MEMS will do a lot to expedite Table 2: MEMS markets and applications and propel the growth in the uptake of Market Applications MEMS. Although MEMS is a relatively new technology area, the benefits of Communications ½ Cross-connects inside optical switches common standards for everything from based on micromirrors and other MEMS ½ documentation to packaging will go far Optical attenuators ½ Tunable filters to create economies of scale and ease ½ Tunable lasers of trade. Packaging advances are also required. Military ½ Munitions guidance ½ It is the single most expensive and time- Surveillance ½ Arming systems consuming task in overall MEMS product ½ Embedded sensors development. ½ Aircraft control processes include bonding two wafers As a market, MEMS is highly ½ Inertial systems used in unmanned vehicles together, deep reactive ion etching (DRIE) fragmented, which is also a sign of and flight systems that can etch completely through the immaturity. While the supply-side can Info Tech ½ Data storage magneto-resistive (MR) tape heads wafer, aligning a wafer on the backside in boast of supply-chains established in ½ Tiny micro-magnets for non-volatile memory addition to the front side, building Europe, the US, and East Asia, the ½ Inkjet printers structures on quartz as well as silicon demand side is extremely diverse. There ½ Rear-projection screen TVs wafers, and deep anisotropic wet etches are a number of niche-like, fast-growing Biomedical ½ DNA amplification using such etchant chemicals as KOH MEMS product lines. ½ Polymerase Chain Reaction (PCR) (potassium hydroxide), TMAH (tetra- The annual compound growth rate ½ Biochips for detection of hazardous chemical methyl-ammonia-hydroxide), or EDP for MEMS, is estimated to be between 26 and biological agents (ethylene-diamine-brenzkatechin- and 50 percent over the next five years by ½ Microsystems for high throughput screening and selelction – hybridization chips or genosensors pyrazine). groups such as the MEMS Roadmapping ½ Biochips for DNA analysis Today the amount spent on research Association and NEXUS. Clearly, MEMS ½ Microfluidic chips used as diagnostic devices and development (R&D) is still small devices are going to impact a range of where one drop of blood can be tested for compared to IC industry R&D. But industries during the next few years, but it a whole range of diseases recent press announcements suggest is important not to over-hype these tiny Medical ½ Blood pressure sensors that a larger array of MEMS products devices. “On the whole, MEMS products ½ Muscle stimulators are moving into production. Many of the are disruptive for the biochip, for example, ½ Drug delivery systems packaging and testing hurdles are being which is clearly a threat to those who ½ Pacemakers addressed by industry and the research manufacture more traditional laboratory ½ Prosthetics ½ institutions that work with industry. testing equipment” as Roger Bischofberger Implanted pressure sensors An industry roadmap, similar to that of of Applied MicroSWISS points out. Such Automotive ½ Internal navigation systems the semiconductor industry, is being discontinuous innovations, as they are ½ Air-condition compressor sensor developed, and a number of organizations called by the market analysts, take a lot ½ Intelligent tires ½ are being formed to commercialize MEMS. longer to become a commercial success Airbag sensors ½ Fuel level and vapor pressure sensors (Table 2). ½ Brake force sensors and suspension control The future of MEMS Steve Walsh, an expert on MEMS, says accelerometers MEMS as a mass market technology that there is invariably a time lag between ½ Accelerometer still has to mature. Two efforts underway the discovery of a new technology and Other ½ Earthquake sensors in the industry to standardize and to its deployment in commercial systems. ½ Avionics pressure systems come up with inexpensive methods of His research (Table 3) is helping to inform

10 | Chip Unaxis Magnetic printing heads High-speed, high throughput devices deliver toner to paper without de-magnetizing the ink, Valerie Thompson making it perfect for secure MSc., has been a paper documents in the banking freelance business and industry, such as personalized high-tech writer for more cheques (image: Colibrys). than 10 years. A Canadian based in Zurich, she tracks the trends and developments of Europe’s purveyors of advanced technology. Table 3: Time to full commercialization for selected MEMS products

Product Discovery Product evolution Full commercialization

MEMS pressure and flow sensors 1954 1960 1990 to present

Accelerometers 1974 1985 1998

Gas sensors as used in 1986 1994 2005 process controls the roadmapping efforts of the MEMS Micro injector nozzles 1972 1984 1998 industry. e.g. fuel nozzles for engines

MEMS technology has finally entered Optical waveguide sensors 1980 1986 2004 a rapid growth phase, according to Frost Biochemical microfluidic systems 1980 1986 2004 and Sullivan’s Technical Insights, and for remote testing the market is expected to quadruple by Rate sensors as used in radars 1982 1990 2002 2004. Telecommunications use of MEMS and gyroscopes is slated for growth. MEMS-based Chromatography, e.g. gas 1975 1980 2001 variable optical attenuators, tunable conductivity detection filters, and tunable lasers have expanded Source: from a chapter in MEMS 2000, a book in-progress by Steve Walsh, a SPIE publication the market beyond switches. The telecommunications segment is expected to increase by more than 30 percent of the total MEMS market in 2005, according Table 4: MEMS market hurdles to Frost and Sullivan. Sensor sales Automation of manufacturing process Highly fragmented market currently lead the market, but actuator In the latter half of 2001, announcements on both sides MEMS is a technology that can be applied to a highly diverse sales will far outpace them by 2005. of the Atlantic suggest that micro-assembly systems for range of devices. How do MEMS foundries approach a market MEMS chips for rear projection TVs manufacturing and checking the dimensions of microsystems that includes Procter and Gamble, surgeons in a hospital in and microcomponents will be in use. But there is plenty Brussels, and tool and die makers in the Czech Republic. will enjoy an expanding market share, of opportunity for more automation. New commercialization organizations will help to segment says Stanford Resources, a market the markets and develop channels to market. There is room intelligence services firm focusing on to improve. the global electronic display industry. Process analysis Quality control standards MEMS technology is of critical Today, the development of most MEMS devices still requires Frequently, the quality of many MEMS devices fabricated importance to the growth of other cutting a dedicated research effort directed at formulating a suitable at either academic or commercial facilities is low. Part of the fabrication sequence. An interface which separates design problem is that the technology is so new that the fabricators edge areas of science and technology. from fabrication allowing the designer to use process- have not yet understood how to define quality, much less Scientists are increasingly using MEMS in independent design tools and methodologies will reduce measure it. the amount of time and effort required to successfully experimental genomics and proteomics realize MEMS devices, say the experts. systems to help them characterize Packaging Human resources and analyze things at the molecular level. Furthermore, scanning tunneling Every time a new MEMS device is developed, a new The need for trained engineers and designers is strong. and specialized package has to be designed. It is a huge Working with MEMS requires knowledge of the potential of microscopy, the key enabling technology engineering effort to package 3-D devices. Efforts are being microsystems technologies and techniques. Innovators will for nanotechnology, exploits MEMS. made to overcome this hurdle. Researchers, as well as require education and training or at least a very good vendors, in Europe have recently announced new products consultancy class in order to fully exploit MEMS in fields such Without MEMS there would be no and systems that begin to overcome this issue. as biomedical devices, telecom, and household appliances. scanning tunneling microscopes, and without these microscopes there Source: Proceedings “Mikrotechnik and Mikrosystemtechnik in der Telekommunikation”, NTB Buchs, 2001 would be no nanotechnology.

Unaxis Chip | 11 Telecom

Asia Pacific Microsystems – the MEMS Pioneer in Taiwan

Dr. Gordon Shyu, Vice President and Sales & Market Manager that it was about time to start engineers, about half of whom are R&D, Greater China, Kevin Chen, Sales & Service Manager Unaxis communication with big industry players and the rest work in production, Semiconductors Taiwan and venture capitalists. In July 2001, application, and quality. The headcount Two key persons were instrumental in Prof. Lin left his position of Executive of course is still growing, particularly starting up APM: CEO Prof. M. S. Lin and Vice President at ITRI and set up APM for the non-R&D departments. APM will CTO Prof. Star Huang. together with Prof. Huang. have approximately 70 employees at the Prof. M. S. Lin has been with the beginning and 300 at the end of 2002, Industrial Technology Research Institute Size, technology and business model when Asia Pacific Microsystems is for more than 20 years. He is proud to Currently, APM is located in the open lab planning to be up and running with their have started up new organizations in the within ITRI. At the moment, more than fifty first line of about 60’000 wafers/year ITRI, such as the Opto-Electronics and people are employed there: 80% of them in Hsin-Chu. System Laboratories. They are now the most important source for technology Dr. Star R. S. Huang know-how and serve as a reservoir of (left), CTO of professionals for the opto-electronic Asia Pacific Microsystems, industry in Taiwan. Later, he again and Dr. Henry Chen, pioneered the industry, this time with a Vice President of company rather than a research institute. the APM production MEMS technology was his choice. division Prof. Star Huang has been working in the research of MEMS technologies for more than 20 years. The quantity and quality of his publications have made him one of the most respected professionals in this field. His dream is to make MEMS a reality for mass production. Both Prof. Huang and Prof. Lin have been colleagues in the Electrical Engineering Department at the National A visit to APM. Tsing-Huang University since the late From left to right: Kevin Chen, 1970s. They knew their interests were Sales & Service perfectly aligned and have been doing Manager Unaxis market research until 2000. They agreed Semiconductors Taiwan; Albert Koller, General Manager of Unaxis Compound Semiconductors Europe; Dr. Huang and Dr. Chen from APM; Dr. Gordon Shyu, V. P. and Sales & Market Manager Greater China

12 | Chip Unaxis N.KOREA

Beijing Tokyo Seoul

universities. They are working towards partnerships with some RF system and packaging houses. S.KOREA APM plan to do foundry service for JAPAN customers, which will differ from IC foundry models since MEMS technology variation is so large that so far there is no standard process flow as exists for CMOS ICs. It will be more like a co-development model with customers. APM take CHINA customers’ concerns in intellectual property protection as top priority, therefore they will make the foundry process different from their own product lines to avoid any possible ambiguity. Taipei The first foundry candidate could be the optical switch technology, but the detail is still under development. TAIWAN Expectation from equipment suppliers Hong Kong Due to the low technology maturity, all MEMS process modules are verified only on R&D tools in a laboratory. It is challenging to select the right mass PHILIPPINES production tools and processes, particularly as some tool track records are only from IC, LCD, CD-ROM, or other applications. The field data for MEMS, particularly for manufacturing, are valuable. APM also need equipment APM’s first line is dedicated to R&D The business model will be primarily vendors’ help in the recipe development and small volume production. The smaller, focused on their own brand products. and tool modification for MEMS semi-auto 6" wafer line will be similar The first priorities are application. This kind of work should to an IC fab some ten or fifteen years ago. ½ sensor technologies for the automotive preferably be started before the shipping APM are not quite sure yet whether a industry, sampling is expected in or even during evaluation of tools. direct transfer of all IC fab methodologies mid-2002, The arrangement of time slots in the into MEMS fab is plausible. The ½ RF MEMS technologies for wireless equipment vendor’s lab for demonstration technology maturity, the market scale, communication, sampling is expected is therefore very important. and the business visibility are different. at the end of 2002. Experiences with their first line will provide For more information about APM please APM with the necessary information APM will develop these two technologies contact: [email protected]. and database to set up the second line on their own at APM and pursue various of about 200’000 wafers/year in 2004. R&D projects together with ITRI and

Unaxis Chip | 13 Telecom MEMS Technology for Telecommunication

Prof. Dr. Alex Dommann, Interstate University The motivation to develop a new low- of Applied Science, Buchs, NTB, Institute for cost HARMS process based on silicon Microsystemtechnology IµS-NTB molds and electroplating was the The impact of telecommunication liberalization and disruptive technical availability of deep reactive ion etching (DRIE) tools and processes and the changes brought on by the internet are driving a massive increase in the limited performance of existing low-cost demand for bandwidth that is unprecedented in history. HARMS processes for fabrication of replication tools – particularly in the case The need to pump more bits around adjustments have kept manual assembly of profile control for outforming and mold the world at the speed of light has made the industry norm. There is a great need stripping after electroplating. the development of optical components for efficient micro-packaging designs, The idea to use silicon molds for one of the most critical areas of research precision machines and production electroplating is not new, but has only and business. However, opto-electronics processes to automate opto-electronic been used for limited structure depths is a highly specialized field requiring component manufacturing. This is where (<100 µm) and aspect ratios (<5) [1]. interdisciplinary know-how to participate. assembly sees great creative potential Silicon molds for high aspect ratio Besides the glass fibers themselves, for MEMS technology. electroplating require uniform structure the electronic boxes which create, amplify, The new approach will downsize depth and a seed layer on the bottom of regenerate, switch, and receive tiny light both costs and space needed for the mold. Electroplated tools for injection pulses are critical drivers of transmission opto-electronic components and reduce molding and hot embossing additionally system performance and bandwidth costs and time for precision assembly, need smooth surfaces and positive trench capacity. All these components have to be where designs meet the silicon MEMS profiles for outforming. very precise in terms of geometry. Highly technology world. The process has a similar concept as trained operators still assemble most LIGA and is, therefore, called “SIGA” opto-electronic components by hand. New technologies for opto-electronic (Silicon LIGA). The potential range of Micron-level tolerances and individual components assembly applications of the SIGA technique covers SIGA (Silicon LIGA = Lithography Galvanic) various fields such as micro-mechanics, is a newly developed low-cost HARMS micro-optics, micro-fluidics, and Figure 1: Schematic (High Aspect Ratio Micro Systems) integrated microsystems. view of the parallel process to fabricate microsystems and At present, Contraves Space AG is waveguide combiner metal tools for injection molding or hot developing a laser-based communication embossing of micromechanical parts. terminal for geostationary satellites. The As for related replication technologies, carrier beam of the laser subsystem is a mold is filled with metal (Ni, Cu) by produced by a Nd:YAG ring laser. For this electroplating. Unlike the conventional space application, a diode laser pump LIGA process, which is based on module has to be developed. polymers, the SIGA mold is made of The goal was to investigate a light silicon, thus replacing deep lithography beam combiner for a diode laser pump with deep silicon etching. The main module without mode losses and with advantages of SIGA are the profile high mechanical stability. The application control, the ease with which the silicon has to guarantee a lifetime of more than mold can be stripped after electroplating, 10 years in space environment. With the moderate process costs, and the the new parallel waveguide combiner simplicity of the process steps. (Figure 1) it is possible to fulfill these

14 | Chip Unaxis Figure 2: Through- etched silicon stripes, 4 µm wide, 105 µm high and 8000 µm long

by profile-controlled DRIE to get 4 µm wide and 105 µm high silicon stripes. With thermal wet oxidation, silicon is

transformed into SiO2 which is used as Figure 4: Top view of waveguide core with low absorption shows pigtails (core diameter 50 µm), a diced polymer type characteristics. To get the cladding of the located on the left-hand side. Each pigtail device waveguide and mechanical stability, the delivers light from a separate laser diode. structures are recast with an adhesive The pigtails are mounted in V-grooves. with a refractive index of 1.4004. The exit surface of each pigtail is imaged The yield of the polymer type (Figure 3) onto the core of the collecting fiber (core is higher, but also the absorption of the diameter 200 µm). The goal is the perfect polymer core. The grooves are dry etched overlap of the images of all input fiber by DRIE too. The cladding is formed by cores at the position of the output fiber thermal wet oxide and a glass substrate core. Each image is performed by means Figure 3: Cross-section on the top of the structure. The cavities of a spherical lens. If necessary, a of DRIE-etched polymer are filled with adhesive which exhibits low cylindrical lens is put in front of the type structure absorption and a refractive index of 1.54. spherical lens, as shown in Figure 5. To characterize the device, the laser The advantage of this design is the specifications. The device combines diode facet is positioned face to face with reduction of alignment work and of low the output of eight laser diodes passively. a gap of 5 µm to the waveguides. The light loss due to the high transmittance More than one laser can be active at laser diode is temperature driven and of the lenses. the same time. This allows to drive the power-stabilized. The concept of the Micro Free Space laser diodes with half of the maximum The functionality of the parallel Combiner allows a clever packaging of output power, increasing therefore the waveguide combiner has been proven. available optical components such as lifetime of each laser diode. Due to new It is possible to map the facet of the laser optical fibers (used as cylindrical lenses possibilities in microsystem technology diode without any mode losses into a for beam shaping) and sphere-lenses for (parameter-ramping for DRIE [2], [3]), glass fiber. In addition, it is now possible the imaging of the input fiber cores onto we are capable of reproducing the to drive two laser diodes with half of the the output fiber. Even DOE (defractive postulated geometry. maximum power to get the postulated optical elements) could be integrated. Other passive light combiners [1] like output power at the end of the device. Y-couplers have rather high transmission This remarkably increases the lifetime losses. Active components like mirror, of the system. Figure 5: Silicon bench structure prism and waveguide switches [1] are The parallel waveguide combiner complex and therefore of low robustness. permits the production of laser pump Free space lens systems are expensive, modules with low power and high quite large, and less stable. The system reliability. This gives such devices the proposed below is smaller and more opportunity to open new markets. stable. We have investigated two different Conventional silicon micromachining types of parallel waveguide combiners, Another possible design of a parallel the oxide and the polymer type. Both waveguide combiner based on types were patented. For the oxide type conventional silicon micromachining (Figure 2), silicon is dry through-etched is shown in Figure 5. The schematic

Unaxis Chip | 15 Figure 6: Unaxis NE D200 PECVD system Figure 7: Plasma Box®

Highly precise technologies, such as Plasma Box® system allows production Prof. Dr. Alex Dommann photolithography and silicon-etching, can of single layer structures with lower stress was born in Lucerne, be used to build V-grooved silicon boards, values. The layers are of major interest to Switzerland. He received his Dr. Sc. from the ETH in Zurich which allow self-adjustment of all the sensor manufacturers and for the in 1988 after completing components (fibers and lenses) at the production of planar waveguides with his diploma in Solid-state exact positions. small birefringence effects. Physics from the University The whole system is divided into three ½ Impurities (outgassing flow from the of Zurich in 1984. In the planes to get a more symmetrical situation chamber cold walls) do not contaminate following years, he was research fellow at the for the imaging process. The positioning the deposited layer applied physics department ½ of the output fiber is done by maximizing Ultrapure layers are possible although of the California Institute of the total output power. The whole system no load-lock technology is used Technology, Pasadena (CA), can be molded completely after ½ The discharge is confined in a uniformly research scientist at packaging – the perfect condition for a heated reactor (in a convential PECVD the Paul Scherrer Institute in Würenlingen and at space-suitable combiner. system only the substrate holder is the “Laboratorium für Packaging of optical components is heated), allowing film deposition with Festkörperphysik” of the possible because of the high precision of excellent uniformities in thickness and ETH in Zurich. Since 1991, silicon boards. This concept relies on refractive index he has been professor of approved MEMS technologies. Several materials research and physics at the Interstate types of free space combiners are state In this study, the deposition was done University of Applied of the art. The novelty of the proposed with three different mixtures of N2/SiH4 Sciences Buchs, NTB, concept is to produce free space and NH3 /SiH4 ratios to get different layer- Switzerland, then on combiners on a small scale out of silicon. stress-types (compressive – low – tensile). sabbatical leave at the The system can be optimized and The work pressure and RF power Caltech in summer 1997. Since 1997he has been toleranced by computer simulations respectively are further parameters to Scientific Head of the before manufacturing (Figure 5). adjust. Increasing pressure results in Institute for Microsystems more stress (compressive to tensile) at NTB.

Planar optical waveguide components into the layer. The pressure and RF References Planar optical waveguides for applications power influence the plasma size. Also 1 A. Olsson, O. Larsson, J. Holm, L. Lundbladh, in optical communication can be different thicknesses were deposited to O. Öhman and G. Stemme, “Valve-less diffuser fabricated using conventional thin film demonstrate the dependency of the micropumps fabricated using thermoplastic replication,” Sensors and Actuators A 64, (1998) deposition techniques. We are currently stress on the thickness. Such planar 63 – 68. developing a beam splitter based on a waveguide will allow the microfabrication 2 M. Gmür, A. Dommann, H. Rothuizen, planar silicon oxynitride core with a silicon of optical devices with high integration R. Widmer and P. Vettiger, “SIGA: a new High oxynitride cladding layer. The concept of density. The refractive index contrast of the Aspect Ratio Micro System Process”, Proc. of nd the Plasma Box® of the Unaxis NE D200 waveguide can be adjusted by changing the 2 International Conference on Integrated MicroNanotechnology for Space Applications, PECVD system (Figure 7) permits to the nitrogen content in the planar silicon Pasadena, CA, vol. 1 (1999), 267. fabricate low-stress isolating layers oxynitride core. Due to the very small 3 A. Ayon, C. Lin, R. Braff, M. Schmidt et al., especially for micromechanical parts, internal stress of the layers and the low Etching characteristics and profile control in a planar optical silicon oxynitride core, and optical loss, it is possible to achieve time-multiplexed inductively coupled plasma microsystems. Unlike the conventional minimized radiation losses. etcher, IEEE Solid-State Sensor and Actuator Workshop, 1998, 41– 4. PECVD processes, which are based 4 H. Zappe, Introduction to Semiconductor on compensating multilayers of tensile For further information please contact: Integrated Optics, Artech House and compressive strained layers, the [email protected] Optoelectronics Library, 1995.

16 | Chip Unaxis Telecom

MEMS: a Playground for New Thin Film Materials

There are materials that do not only devices. Stresses of up to 100 MPa and provide auxiliary functions but the strains of up 0.1% have been obtained [2]. essential functionality of the device. PZT exhibits the perovskite structure, These are so-called functional materials. as shown in Figure 1. In the para-electric The useful functional materials provide high temperature phase the lead ions a transformation between driving signal occupy the corners of a cube, the Ti and

Dr. J. Baborowski, R. Lanz, PD Dr. P. Muralt, N. Ledermann or read-out signal on the one hand, and Zr ions are randomly mixed (solid solution) (from left to right), Ceramics Laboratory, Swiss Federal a sensor or actuator parameter on in the center of the cube, and the oxygen Institute of Technology EPFL, Lausanne, Switzerland the other hand. The driving and read-out ions the face centers, thus forming a signal can be an electrical, magnetic, regular octahedron around the central Micro-electro-mechanical systems, or or optical one. The sensor parameter cation. In the ferroelectric phase (below microsystems, constitute a fascinating can be a mechanical deformation, a about 350°C) the cube is distorted, mainly world of miniaturized functionality. The temperature change, a chemical reaction, due to a displacement of the central original notion of MEMS emphasized that etc. Actuation can mean a linear cation with respect to the oxygen mechanical elements are added to displacement, the emission of an octahedron. This displacement occurs microelectronics – as needed for motion ultrasonic wave, the phase shift of along the same direction for all unit cells sensors for instance. Today the actual a laser light beam for instance. Functional inside a ferroelectric domain. The field has become much wider. It now materials in MEMS is a young and vast structure becomes polar. The ions shift includes also optical, thermal, magnetic, field. Many opportunities are available in easily when an electric field is applied. For and fluidic (chemical and biological) microsystems. It is a very exciting field of this reason, PZT shows a large dielectric interactions and phenomena [1]. applied materials science. Let us take a constant (around 1000) and piezoelectric The basic material of a MEMS device is short look at piezoelectric MEMS. coefficients. This means that at a given most often Silicon. Silicon is inexpensive, field, a PZT capacitor can store 1000 has excellent elastic properties, a low Piezoelectric MEMS times more energy than a vacuum thermal expansion coefficient, and does Best known among bulk piezoelectric capacitor. The external field may also

not show creeping and aging because materials is PZT (PbZrxTi1–xO3), which switch the spontaneous electric it is a pure, monocrystalline material. In is applied in ultrasonic imaging, linear polarization by 180°. That’s why it is addition, the micromachining of silicon is actuators for nanoscience (e.g. atomic called ferroelectric, after the analogous well mastered today, either by means of force microscopy), high pressure valves, phenomenon occurring in magnetism. anisotropic wet etching, or anisotropic and many more. This material has also Thin films of PZT are very often deposited dry etching (deep silicon etching). To a been integrated as a thin film into MEMS by sol-gel techniques (chemical solution certain extent, one can fabricate devices by means of an “all-silicon” technology Figure 1: The unit based on electrostatic interactions cell of the perovskite between doped silicon elements. In structure general, however, many more material properties are needed than silicon can offer. Silicon is a bad electrical and a very good thermal conductor, for instance. Hence, one has to add metal films for improving electrical conduction, or

thermal insulator films (e.g. SiO2, Si3N4) for improving thermal insulation.

Unaxis Chip | 17 Telecom

deposition). Among piezoelectrics, there Figure 3: Basic operation modes of is another class of materials that are thin films in MEMS: not ferroelectric, but polar only. The The capacitor alignment of the polar axis cannot be structure puts the effectuated by an external field. It must be electric field along provided by the growth process. Typical direction 3. Piezoelectric representatives of this class of materials stresses in the film are ZnO and AlN (see the structure in plane (direction 1) Figure 2). They are well known as thin film plane bends an elastic structure that bend the flexural materials. Low temperature processes can be a beam, a bridge, or a membrane. structure and yield are carried out by sputtering in order to The size of the deflection along direction 3 an excursion in direction 3. achieve the unidirectional alignment of depends on the lateral dimensions. the polar axis (c-axis) perpendicular to It is in the region of micrometers/100 µm the film plane (see e.g. [3]). lateral size. The longitudinal mode affects developed for ultrasonic transducer arrays. Piezoelectric strains and stresses the thickness of the piezoelectric thin film. Figure 4 shows an example of a fabricated couple in various geometries to the A thickness change of typically 0.1 nm/V transducer structure. The admittance of a electric field. In planar thin films can be achieved. 300 µm wide element containing 2 µm PZT structures, the piezoelectric film is Quite a number of applications on a micromachined silicon membrane sandwiched between two electrodes have been demonstrated for flexural is depicted in Figure 5, showing the (Figure 3). The electric field stays thus structures: active cantilevers for atomic fundamental resonance at about 1 MHz. perpendicular to the film plane (direction force microscopy, accelerometers, The longitudinal effect will not be easily 3). Of importance in (polycrystalline) thin 2-dimensional mirror arrays for image exploitable in actuators and sensors. films is the longitudinal effect along the projection, microphones, ultrasonic However, this effect is very much suited electrical field, and a transverse effect in micromotors, Lamb wave pumps and for bulk wave transducers (RF-MEMS). the film plane (direction 1). Two basic filters, and others. Currently, there is also The fundamental thickness resonance structures can be applied. Most common much interest to evaluate piezoelectric of a 1 µm thick film occurs in the GHz to MEMS applications is the use of the MEMS for high frequency ultrasonic frequency range. This is very much transverse effect in flexural structures. imaging and ultrasonic sensors. Suitable suited for building microwave filters for Piezoelectric transverse stress in the film membrane or plate structures are telecommunications. At such high

Figure 2: The unit Figure 4: SEM cell of the wurtzite viewgraph showing structure the micromachined bridge of a suspended membrane with the etched Pt and PZT layers

18 | Chip Unaxis Figure 5: Admittance as a function of Prof. Dr. Paul Muralt frequency for a received a diploma in micromachined, Experimental Physics 300 µm wide PZT in 1978 at the Swiss thin film transducer Federal Institute of element [4] Technology in Zurich (ETH). He accomplished his frequencies, one has to use piezoelectric PhD thesis in the field of commensurate- materials with good acoustic properties, 0.005 0.002 C1-B-10dc incommensurate phase i.e. small acoustic losses and a high transitions at the Solid sound velocity. Aluminum nitride (AlN) State Laboratory of ETH. 0.001 has very superior properties in this 0.004 In the years 1984 and respect. PZT is too much damped at 1985, he held a post

Im (Y) ( doctoral position at the GHz frequencies. Figure 6 shows the ]

–1 0.003 0 IBM Research Laboratory in admittance of a bulk acoustic resonance Ω Zurich where he pioneered of an AlN resonator at 7.4 GHz. Figures 5 Ω the application of scanning and 6 thus illustrate the difference of 0.002 – 0.001 –1 tunneling microscopy to ) flexural and bulk waves made in thin film Re (Y) [ surface potential imaging. After a stay at the Free structures, as seen by the frequency University of Berlin, where – 0.002 spectrum. The resonances are a factor 0.001 he built up a tunneling 7’000 apart. microscope, he returned to Switzerland in 1987, 0 – 0.003 For more information please contact: where he joined the Balzers 1 1.05 1.1 1.15 1.2 1.25 1.3 group in Liechtenstein. [email protected] He specialized in sputter Frequency [MHz] deposition techniques, Reference and since 1991 managed 1 Senturia, S. D., Microsystems design, 2001. a department for Boston: Kluwer Academic development and 2 Muralt, P., “Ferroelectric thin films for applications of physical microsensors and actuators: a review,” vapor deposition G Conductance Micromech. Microeng., Vol. 10, processes. In 1993, he 0.08 B Susceptance pp. 136 –146, 2000. joined the Ceramics 3 Dubois, M.-A. and P. Muralt, “Stress and Laboratory of the Swiss piezoelectric properties of AlN thin films Federal Institute of deposited onto metal electrodes by pulsed 0.06 Technology EPFL in direct current reactive sputtering,” Lausanne. His research J. Appl. Phys., Vol. 89, pp. 6389 – 6395, 2001. interests are the deposition 4 Muralt, P. et al., “Study of PZT Coated 0.04 of ferroelectric and other Membrane Structures for Micromachined polar thin films, property- Ultrasonic Transducers.” Proc. of IEEE microstructure relationships, Ultrasonic Transducers, Atlanta, 2001. 0.02 the integration of 5 Lanz, R., M.-A. Dubois, and P. Muralt, “Solidly ferroelectric thin films mounted BAW filters for the 6 to 8 GHz range into memory devices, and based on AlN thin films,” Proc. of IEEE of piezo- and pyroelectric

Admittance Y [S] 0 Ultrasonics Conference 2001, Atlanta (USA), thin films into micro-electro- 2001. mechanical systems. More recently submicron Ð0.02 ferroelectric structures have Figure 6: Admittance attracted his attention. He of bulk acoustic wave gives lectures in thin film resonator showing Ð0.04 deposition and micro- the fundamental 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 patterning. thickness resonance Frequency [GHz] of a 300 nm thick AlN thin film [5]

Unaxis Chip | 19 Telecom

Unaxis Supports DWDM with PECVD and RIE DWDM = Densed Wavelength Division Multiplexed

Figure 1: Scanning electron microscope picture of a test structure for arrayed waveguides that shows the patterned

SiO2 fibers fanning out from a common input/output channel. The width and depth of the fibers are around 10 microns. It is clear that the intersection area is the most critical one for etching since its aspect ratio goes far above 10:1 (image: OpsiTech, Grenoble, France).

Dr. Emmanuel Turlot, unlimited bandwidth capability require frequent amplifications to avoid Managing Director Unaxis Semiconductors Grenoble for terrestrial communications at very transmission errors. WDM, however, low cost. But on the other hand, the separates the channels with the carrier The IT market segment of requirement to convert the optical signal optical frequency or wavelength with low telecommunications – despite its along the fiber regularly into an electrical power optical signals that can propagate temporary slowdown – is experiencing one and back impedes the bandwidth over kilometers without interactions or a doubling of the bandwidth capability and/or increases its cost drastically. This amplification need. Ultimately, DWDM of the global network every six months. is mainly because TDM (Time Division (Densed Wavelength Division Multiplexed) The advent of multi-format (text, Multiplexed) technology as opposed to solutions will offer unlimited bandwith. applications, etc.) and especially video WDM (Wavelength Division Multiplexed) As demand changes, more capacity data exchange via internet triggers is still widely used to separate the can be added, either by simple equipment this demand for rapid growth of the channels today. TDM requires high power upgrades or by increasing the number communication highway. On the one optical signals that propagate with high of wavelengths carried by the already hand, the optical fiber offers almost losses in the optical fibers and hence existing fibers.

20 | Chip Unaxis Figure 2: Schematics of the cut view of an SiO2 #2 optical waveguide arrangement SiO2 #3 manufactured via PECVD deposition 10 SiO2 #1 and RIE etching of Silicon SiO2 with three substrate different optical indices on a silicon substrate. The optical signal is confined in

SiO2 #2 core film and travels in a direction perpendicular to the cut view plane.

Figure 4 : Scanning To succeed, DWDM technology the optical fiber at the output of the Refractive index, thickness uniformity, electron microscope requires the development of new optical multiplexer, the characteristics of the stress, and SiH content are the items picture of an alignment structure components such as wide bandwidth waveguide should be as close as possible which are controlled to ensure planar light patterned in a optical amplifiers (active) and optical to the one of the fiber to reduce optical circuit performances. SiO2 film with the multiplexers (passive). Two kinds of losses. In particular, the difference It is also very important that the edges QUADRA RIE/HDP system. The height optical multiplexers are currently under between core SiO2 (SiO2 #2) and the of the waveguides, manufactured during of the etched film is development: either based on interference underlying one (SiO2 #1) is typically the etching of the core SiO2, are steep around 10 microns filters (bandwidth of 200 GHz typically) ranging from 10–3 to 10–2 (Figure 2). The and smooth to limit the optical losses due (Picture: OPSITECH, or on an array of optical waveguides, PECVD technique based on the SiH4/N20 to scattering. The dry etching process Grenoble,France) to separate or recombine the different gas mixture with GeH4 as a doping gas is of SiO2 based on CHF3/02 mixture is wavelengths or channels. The optical a deposition technique that is capable of inherently anisotropic and hence can waveguides-based multiplexers are manufacturing SiO2 films with optical index achieve edges as steep as 89°. Here integrated optics devices, i.e. control better than 10–4 as well as again, Unaxis is supporting its customers manufactured on silicon substrates optimizing its value by adjusting the Ge by developing integrated optic devices via the deposition and etching of several doping. In addition, the cladding SiO2 with the QUADRA system. In that case, micron thick SiO2 films. The waveguides (SiO2 #3) should have a very good the system is equipped with up to three are directly patterned with standard step coverage in order to fill the small RIE/HDP etching reactors with helium- lithography techniques on the substrate gaps at the crossing of the waveguides: cooled substrate holders. The reactors (Figure 1). in that case, liquid-source-based material are compatible with wafers up to 200 mm Like for optical fibers, optical is fed into the PECVD reactor. Unaxis has diameter. Thanks to the combined waveguides require SiO2 materials with a developed a production multi-chamber control of the ion energy and the wafer slightly different optical indices in order to tool, the QUADRA, equipped with PECVD temperature, the system can etch 10 µm ® channel the light through with minimum reactors based on Plasma Box design, thick SiO2 films without photoresist losses. Since the light has to be capable of depositing these three types degradation or residues left over at the transferred from this waveguide to of SiO2 into the same reactor (Figure 3). bottom or on the edges (Figure 4). Each chamber is equiped with an automatic end point detection system coupled Figure 3 : Picture of the QUADRA multi-reactor production system with pattern recognition capability leads taken from the load lock side. to a wafer-to-wafer etch thickness It consists of a vacuum central repeatability lower than 3%. handling chamber with four ports, one dedicated to the For more information please contact: load lock module, and the three others for the processing [email protected] modules, PECVD or RIE/HDP.

Unaxis Chip | 21 Telecom

Figure 1: SEM of InP via etching using hardbaked photoresist Dry Etching InP for etching mask Multiple Applications

David Lishan, Principal Scientist, Mike Devre, surface stoichiometry, and surface Russ Westerman, Don Malpass,Yao-Sheng Lee, Brad Reelfs, roughness are obstacles that typically Strategic Business Unit Compound Semiconductors, result from low vapor pressure indium St. Petersburg, USA reaction products. Although wet etching Frequency response, thermal conductivity, is often a selective, relatively inexpensive breakdown voltages, and optical properties and low damage process, its isotropic Backside contact (e.g. vias) – coupled with resource commitments – nature makes it unsuitable for many This is a deep etch approximately of ensure that the indium phosphide material applications. In response to these 50 to 100 µm used for defining contacts system will play an important role in limitations and problems, several dry through a thinned substrate to a device. high-speed electronics and photonics. etching chemistry approaches have been Typical applications utilize a vertical The diversity of applications and material explored and developed. Each of the sidewall structure however, sloped profiles combinations has provided a mixture of approaches is intended to address a may be realized using a photoresist etch structures requiring etching. Here we particular application. For example, mask erosion process (with the angle would like to present a selection of etching structures deeper than a micron require proportional to initial resist slope and results obtained on SHUTTLELOCK ® and processes providing high etching rates erosion). An example of anisotropic VERSALOCK™ systems for structures to maintain acceptable throughput, while profiles is shown in Figure 1. An elevated such as microlenses, device isolation, shallow features necessitate relatively temperature of approximately 160 ºC is backside vias, HBT emitter/base mesas, slow etching rates to retain control. necessary to obtain reasonable etch rates and optical devices. Each structure has In the remainder of this article we and desorb the low volatile halide etching

specific etching criteria like etch rate, discuss various etching chemistries products (InClx and InBrx). profile, surface morphology, and selectivity and system requirements for different that must be met for successful device applications. Etching requirements for a Microlenses production. We used a variety of gases and variety of applications have been roughly This is a deep etch used for creating a either a high density ICP or a low density grouped and described in the table below. curved lens-type structure with a typical RIE source to achieve the desired results. This simplification cannot represent the etch depth of 5 to 10 µm. The sloped InP and associated material systems total diversity of applications that naturally profiles are deliberately realized using a (e.g. InGaAs, InAlAs) have traditionally consist of a wide range of mask materials, photoresist etch mask erosion process presented obstacles to dry etching profiles, and etch depths even within the that requires a relatively low selectivity of technology. Low etch rates, loss of same application. near unity. An example of a lens profile in

Application Typical etch Selectivity to Profile Morphology Etch rate depth mask

Electronic devices 0.1 – 0.5 µm Moderate Near vertical Smooth Slow (e.g. HBTs, HEMTs) < 0.15 µm/min Microlenses 5 – 10 µm Near unity Variable Smooth ~ 0.5 µm/min Optical devices (e.g. lasers, VCSELs, 1 – 10 µm High Vertical Smooth walls ~ 0.5 µm/min waveguide detectors, modulators) Gratings 0.03 – 0.2 µm High Variable Smooth Slow < 0.06 µm/min Mesas (e.g. contacts, isolation) 1 – 5 µm Moderate 45 – 75 degrees Moderate ~ 0.5 µm/min Backside contact (e.g. vias) 50 – 100 µm High 60 – 90 degrees Not critical Fast > 1 µm/min

22 | Chip Unaxis Figure 2: SEM of Figure 3: SEMs of InP microlense etching vertical etching of InP using photoresist using SiO2 mask etching mask

mechanically or electrostatically at the discretion of the user. Another issue not often discussed is the maintenance of chamber cleanliness. Regardless of the etch chemistry involved, there is a strong tendency for reaction by-products to condense on the process chamber walls. Although the chamber itself cannot be heated to the appropriate temperature for safety reasons, chambers are now being designed with a removable InP is shown in Figure 2. The photoresist The wide range of applications and just heated liner. This forces reaction mask shape is determined either by as many different processes mandate a by-products to exit the chamber as reflowing the resist or with a gray scale flexible hardware set. Although RIE may vapor which is then condensed in photomask. be appropriate for certain applications, a specifically designed removable trap. the primary system accepted for most The process chamber can remain under Smooth vertical etch applications is the Inductively Coupled vacuum during trap substitution. This This application involves deep, vertical Plasma (ICP) source. An ICP type etching combination of hardware enhances etching approximately 1 to 10 µm in depth system with a separate bias control for module cleanliness and reduces the and is often used to define structures with the substrate enables critical control and maintenance downtime without a primary application in optical devices. versatility with independent management impacting processing. These applications include devices such of ion bombardment and reactive species as waveguides, vertical cavity surface formation while generating high-density Summary emitting lasers (VCSELs), diodes, and plasmas at low pressures. Material After many years of basic research, lasers. Typical applications require a damage, profile, selectivity, and etching InP and related materials are rapidly vertical profile with smooth surface rate can be positively influenced by moving into pilot line environments. New morphology. Sidewall smoothness is judicially balancing the physical and etching systems are available that can very dependent on the initial condition chemical components of the etching accommodate the numerous applications of the patterned mask material as high process. and the demanding increase in utilization. selectivity between the mask and InP The examples shown in this article Just several years ago the only option is employed. Examples of possible include process conditions ranging was RIE, now there are combination anisotropic profiles using a silicon from 5 ºC to 160 ºC, and thus it is clear ICP/RIE sources. Controlled substrate dioxide mask are shown in Figure 3. that substrate temperature must be temperature and self-cleaning chambers To accentuate the chemical aspect of the carefully managed. A very effective present more opportunity for appropriate etching, this process is run at 160 ºC. method is coupling the back of the etching processes. substrate to the chuck with a thin layer Mesa of flowing helium. The substrate is For more information please contact: In some device applications it is not “clamped” to the chuck either [email protected] critical to have a vertical profile, and in fact it may be desirable to have an intentionally Figure 4: SEMs of positively sloped profile (e.g. contact mesa structures in InP; photoresist metallization between layers). Etching mask (left), tungsten depths can vary from shallow to many nitride mask (right) microns and are usually sloped with an angle between 45 and 75 degrees. In general, this process also relies on mask erosion to generate the slope. Examples of mesa profiles using this process are shown in Figure 4.

Unaxis Chip | 23 Advanced Silicon

LEPECVD Provides High-Quality Virtual Substrates for Ge-rich SiGe p-MOSFETs

Dr. Matthias Kummer, Post-Doctoral Researcher, ETH Zurich, Switzerland

These days the vast majority of available SiGe products are based on the Hetero- Bipolar Transistor (HBT), with UHV-CVD as the established deposition technique for production. The HBT is produced either as a discrete device or combined with traditional Si CMOS technology in SiGe BiCMOS ICs. These integrated circuits, taking advantage of the superior electronic properties of SiGe and the low production costs of CMOS, are already Figure 1: Pseudo-3D rushing into the fast-growing wireless for standard processes (lithography, wet representations of AFM telecommunications market. Up to now, and dry chemical processing, or even images obtained from the primary role of the SiGe enhancement fundamental issues like mechanical virtual substrates with to Si CMOS ICs has been to add RF substrate stability for easy wafer handling 70% Ge concentration before (a) and after (b) functionality that otherwise would have and – last, not least – availability of process sequence to be implemented with additional, inexpensive substrates), it will give access optimization. The expensive III-V-based devices. to significantly higher performance levels troughs visible in (a) at astonishingly low additional cost, are as deep as 200 µm, SiGe CMOS as most of the processing steps will while the maximum corrugation amplitude A technological route with even more not change. in (b) is less than 15 µm. significance than the BiCMOS The main issue to be addressed for communications segment is the implementing SiGe CMOS, apart from introduction of the SiGe enhancement the detailed design issues for the actual into the CMOS technology itself. The device heterostructures, is the production combination of thin, tensilely strained of substrates which can provide the Si layers (for n-type MOSFETs) with thin, strain needed for the active layers. Due compressively strained Ge-rich layers to the relatively high mismatch between (for p-type MOSFETs) leads to strongly the lattice constants of Si and Ge of 4.2%, enhanced electron and hole mobilities the strained, active layers have to be for the n- and the p-type devices epitaxially deposited on some material respectively. This higher carrier mobility with an intermediate lattice constant. One will ultimately enhance virtually all of of the most promising approaches is to the important electrical characteristics grow a thick, compositionally graded SiGe of the transistors. A successful alloy buffer layer on a standard Si wafer, implementation of a SiGe-based CMOS with the concentration increasing from process could significantly boost the pure Si to the Ge fraction needed for the performance of this mainstream desired mismatch. If the concentration technology. If such an implementation gradient is shallow enough, the resulting adheres to some basic requirements virtual substrate will be fully relaxed and

24 | Chip Unaxis sufficiently defect-free for the subsequent Figure 2: High- epitaxial deposition of the active transistor resolution X-ray structures. The resulting requirements diffraction reciprocal space map (HR-XRD for very thick epitaxial layers and relatively RSM) around two low temperatures call for new approaches Bragg peaks obtained for the deposition processes. The from a complete development of LEPECVD at ETH Zurich p-MOSFET layer in collaboration with NTB Buchs and sequence fabricated with LEPECVD Unaxis came just in time to address these issues.

Ge-rich virtual substrates and SiGe p-MOSFETs Here we will present the latest advances achieved in the production of Ge-rich virtual substrates aimed at the implementation of SiGe p-MOSFETs. The first results obtained from a working high-performance SiGe p-MOSFET channel should be as high as possible, reaching down to 500°C at growth rates fabricated completely by LEPECVD and ideally pure Ge, it becomes increasingly between 4 and 10 nm/s. By balancing the processed by DaimlerChrysler Research & difficult to keep this strained layer flat. requirements for a low temperature to Development in Ulm, Germany, showed The reason lies in the “softer” properties suppress surface roughening and the a record hole mobility of more than of Ge compared with Si. Its melting point need for a sufficiently high temperature for 750 cm2/Vs [1]. After these encouraging (938°C) is considerably lower than that asserting the full relaxation, we developed results, we used the 4" LEPECVD of Si (1410°C), which gives Ge a much optimized process sequences suitable for prototype and development system stronger tendency to be elastically virtual substrates of up to 100% Ge at ETH Zürich to further improve the deformed upon application of strain at concentration. The effect of this structural quality of the virtual substrate typical temperatures used for epitaxy. optimization on the surface morphology with Ge concentrations starting from The key both for optimizing the virtual is shown in Figure 1. 50% and the Ge-rich active strained substrate and the strained channels is To verify the structural quality of the channel with concentrations up to a deposition process, which allows for complete p-MOSFET structures, we pure Ge. a wide temperature range without made extensive use of high-resolution The issues to be dealt with at higher degrading the film quality and with no X-ray diffraction reciprocal space Ge concentrations for the virtual substrate significant reduction of the growth rate. mapping. This method is ideally suited are the reduction of surface roughness Fortunately, this is exactly the strength for examining the crystal quality, the and the density of threading dislocations, of LEPECVD: as the energy needed for composition, the strain state and the while maintaining full relaxation of the film the growth reactions is almost completely thickness of individual layers of complete to the desired lattice constant. As for the supplied by a very intense plasma, device sequences. An example of such strained channel, its interfaces have to be LEPECVD is practically independent of a measurement is shown in Figure 2, sharp, and it must be kept completely free temperature in a surprisingly large documenting the high structural quality of dislocations and strain-induced process window. This allows for the of the (fully relaxed) virtual substrate roughening. While for optimizing the deposition of very thick (between 5 and and the (completely strained) active performance the Ge concentration in the 15 µm) virtual substrates at temperatures Ge-rich channel.

Unaxis Chip | 25 Dr. Matthias Kummer studied physics at the Swiss Federal Institute of Technology in Zuerich, Switzerland (ETHZ) from 1992 to1997 and received a diploma in Experimental of 80% or 90% Ge content on a virtual Physics from ETHZ with substrate with final Ge concentration of an STM study of SiGe 50% and 60%, respectively. The data heteroepitaxial structures labeled “old” are from the devices of [1], in 1998. where the other two SiGe devices have In 2001 Matthias Kummer received his PhD from the been obtained after the optimization ETHZ with a thesis on the of the deposition process sequence. fabrication of device grade As demonstrated, further research has SiGe heterostructures Figure 3: TEM image paid off with a 30% – 40% enhancement grown with plasma-assisted of the strained In addition to the AFM and X-ray for the 80% device, while the increase techniques, in particular LEPECVD, in the group of channel of a SiGe investigations, the shape and interface of the Ge concentration in the channel p-MOSFET structure. PD Dr. Hans von Känel. sharpness of the active, strained channel to 90% has boosted the performance The channel While writing the PhD thesis contains 90% Ge has been verified with transmission by a factor of 2. In comparison to the Si he worked at the Interstate and is grown on electron microscopy (TEM). As shown in reference device, it has to be stressed at University for Applied a 60% Ge virtual Figure 3, we were able to obtain perfectly this point that the only additional process Science of Technology in Buchs, Switzerland (NTB), in substrate. flat and abruptly defined Ge-rich channels step consisted of the LEPECVD epitaxy, the Institute of Microsystem by using appropriate process conditions. which amounted to roughly 40 min! Technology with Prof. Alex The results of these optimizations are Dommann, mainly on demonstrated again with the fabrication Reference high-resolution X-ray of transistor devices at DaimlerChrysler [1] C. Rosenblad, Chip 4, 2001 (p. 24) diffraction analysis. R&D. The obtained data are shown in Figure 4. The comparison concerns two important figures of merit, the saturation current and the maximum transconductance, of several transistors Figure 4: Comparison of the saturation current and the maximum transconductance for the transistors of [1] (“80% old”), a similar type fabricated from three different structures. obtained after optimization of the growth procedure (“80% new”), and They have all been prepared by LEPECVD a transistor with an active channel which contains 90% Ge (“90% new”). and consist of a strained Ge-rich channel For comparison, a Si reference transistor is included in the plots.

500 140 90% new 90% new D

m 120 400 80% new 80% new 80% old 100 80% old 300 Si reference Si reference 80

200 60 [mA/mm] [mS/mm] Maximum 40 100 Saturation current I 20 transconductance g 0 0 1 10 100 1 10 100

Gate length l g [ Gate length l g [ m]

26 | Chip Unaxis Advanced Silicon

Low Energy Plasma Processing (I) LEPP 300 The extention of the CLUSTERLINE® 300 concept for PECVD processing

Philipp Bartholet, Werner Bischof, Andreas Erhart, Steven for epitaxial and hetero-epitaxial Si and The system Ernst, Yuri Goeggel, Siegfried Wiltsche, Dr. Juergen Ramm, SiGe layers at low temperatures (300°C – The development project LEPP 300 was Strategic Business Unit High Speed Silicon 800°C). The development of the low initiated in May 2000 and integrated into energy plasma-enhanced chemical vapor a value engineering project (“Flash”). The market deposition (LEPECVD) process addressed Based on the experiences with experi- The SBU High Speed Silicon has taken this issue [2]. mental systems, the 200/300 mm single the strategic decision to develop Another challenge in Si and SiGe wafer bridge-type cluster tool (Figure 1) deposition processes for high frequency technology is wafer cleaning before was realized. The upgrade from 4" to devices in the silicon technology. The epitaxial growth (pre-epi clean). Current 300 mm wafer size was one of the Bipolar and BiCMOS markets are technologies utilize either an in-situ high challenges in this project. The LEPP 300 addressed by the already existing temperature bake in a hydrogen now allows processing of 200 mm as UHV-CVD SIRIUS batch-type system atmosphere (typically LPCVD approach well as 300 mm wafers from cassettes dedicated to the production of hetero- for single wafer processing) or an ex-situ without changeover. Another great bipolar transistors (HBT). HF dip (typically UHV-CVD approach challenge was the development of a The development of the LEPP 300 for batch systems). Although both self-cleaning procedure which resulted based on the CLUSTERLINE® 300 bridge procedures are compatible with the in many implications for the design of tool, however, was motivated by HBT production, a pre-epi clean at low the deposition system as well as for the the needs of the future CMOS technology. temperatures (< 400°C) would have plasma source. The handling system Electron and hole mobilities in strained many benefits, especially for processing is based on the Brooks Gemini GX 8000 Si and SiGe are above those physically prestructured substrates and substrates platform which is supported by Unaxis possible in bulk Si. Devices based on with temperature-sensitive material. strained Si and SiGe layers will push Low energy plasma cleaning (LEPC) the high frequency capabilities of MOS resolves these issues. Table 1: The most important requirements technology beyond conventional Si-MOS A selection of the most important for the LEPP 300: technology [1]. Growing a linearly requirements for the LEPP 300 is shown ½ Single wafer bridge tool based graded Si Ge layer (starting with a in Table 1. Unaxis Semiconductors owns 1–x x on the CLUSTERLINE® 300 Ge concentration x = 0 and a gradient all the intellectual property of the hardware platform of typically 10% Ge/µm) allows the and basic process steps. This ensures ½ Low temperature pre-epi formation of an almost strain-free “virtual that the system can serve all segments of cleaning module substrate” (VS) which can have a the CMOS market and other relevant ½ Damage-free plasma epi-reactor predetermined lattice constant depending markets. ½ Integrated chamber self- on the concentration x of Ge at the layer cleaning procedure for the Figure 1: surface. Because the difference in the deposition module Schematic of the LEPP 200/300 mm lattice constant between Si and Ge is ½ Deposition rates of epitaxial bridge-type cluster tool of the layers in the range of 0.01 nm/s approximately 4%, the pseudomorphic configuration existing in the Unaxis LEPC to 10 nm/s at 550°C substrate growth of Si or Si Ge with y > x on the Semiconductors laboratory. 1–y y temperature virtual substrate Si1–xGex allows the ½ Cleaning rates for the removal formation of strained channels for the 300 mm wafer Cleaning of C and O above 0.5 nm/s module fabrication of devices like MODFETs FOUP (Modulation Doped FETs) and MOSFETs. Based on this, the most important Load port modules requirement for the deposition technology LPMs is the high deposition rate 200 mm wafer open cassette LEPECVD Unaxis Chip | 27 Process module Advanced Silicon

Figure 3: Measurement scheme for the discharge characteristics IA UA(IA) explaining the terms plasma source filament “anode voltage” and “anode current”. stainless steel - reactor Power UA supply pump + flexible design of the LEPP 300 allows the connection combination of the LEPC and LEPECVD plasma processes. However, it also promotes the combination with other CVD or PVD wafer anode gas inlet processes. heater susceptor One of the unique properties of the LEPP 300 is the high efficiency in the gas utilization. Typical process pressures are 10–3 mbar and typical process gas

Figure 2: flows are 50 sccm. This reduces the costs Close-up of the software (ControlWORKS™). The Process development for consumables and also addresses LEPC module on the LEPP 300 consists of two new process The verification of the functionality of the environmental issues. ® CLUSTERLINE 300 modules. The LEPC module realizes newly designed plasma source was the A necessary presupposition for platform the plasma-enhanced low temperature starting point for process development. damage-free plasma processing is pre-epi clean in a hydrogen atmosphere Important aspects for the redesign of the the low voltage between filament and at low temperatures. The LEPECVD source were anode/ground of the DC discharge

module enables high deposition rates ½ increased wafer size, (anode voltage UA ). This voltage is utilizing the plasma enhancement for the ½ layer uniformity, influenced by the design of the deposition dissociation of the precursors and for ½ maintenance, and cleaning chamber and the process desorption processes during deposition. ½ ultra-high vacuum compatibility. parameters like gasflow, gas mixture,

This is the first time that the utilization and discharge current. The UA (IA) of plasma for pre-epi clean and for The deposition as well as the cleaning characteristics, plasma potential, and epitaxial growth are implemented and process are based on the same design floating potential of the wafer determine combined in a production system. of the plasma source. A variety of gases the ion energy at the wafer surface. This Figure 2 shows the LEPP 300 system at support the process development for ion energy has to be below the sputtering Unaxis Semiconductors. SiGe-CMOS and related fields. The threshold for damage-free plasma processing [3].

Figure 4: Low energy plasma cleaning LEPC module: Discharge characteristics in the LEPC module Figure 3 shows a schematic drawing of The discharge the cleaning/deposition module together characteristics UA(IA) 20 Ar flow with the explanation of the discharge for different argon 19 30 sccm gas flows. The data 30 sccm parameters UA (anode voltage) and IA

[V] 18

A 40 sccm illustrate the broad 17 (anode current). It is important for the 50 sccm process window 16 60 sccm reliability of the process that these for the condition 15 80 sccm discharge parameters can be stabilized of U < 25 V. voltage U 100 sccm A 14 and that they allow a broad process 13 window for different gas compositions and 12 Anode anode currents. Figure 4 shows a typical 11 example for the discharge characteristics 10 0 102030405060708090 in the argon plasma for the new LEPC

Anode current IA [A] module. For anode currents in the range between 10 A and 90 A, the anode

28 | Chip Unaxis Figure 5: LEPC module: The anode Anode voltage UA in function of the hydrogen voltage for different gas flow at 30 A anode current IA gas mixtures of 24 argon and hydrogen. Ar flow The broad process 22 70 sccm [V]

A 70 sccm window allows the U 20 30 sccm utilization of different LEPECVD module. Again, the anode hydrogen flows to 18 voltage can be controlled below 25 V over adjust the cleaning 16 rates. a large range of parameters. The anode 14 voltage is nearly unchanged if a process Anode voltage 12 gas like SiH4 is added to the argon 10 discharge. This is important for the 0 20 40 60 80 100 120 adjustment of the deposition rates. Hydrogen gas flow [sccm] Targets for process development The system is utilized for our own process voltage is always below 25 V which was rates are sufficient to remove the native development and related customer determined as a safe limit for damage-free oxide and hydrocarbons from the surface sampling. The in-house process plasma cleaning. Figure 5 illustrates how of a silicon wafer within a few minutes. development will focus on process steps the addition of hydrogen to the argon The main focus of this process, however, supporting SiGe-CMOS, especially for discharge changes the anode voltage. is the damage-free preparation of the the production of thick, linearly graded, The diagram also demonstrates that the single crystalline silicon surface for completely relaxed buffers for VS. An anode voltage does not vary over a large epitaxial growth at low temperature. important issue is the characterization of hydrogen flow range. Therefore, the LEPC in combination with homo and cleaning rate can be changed without Low energy plasma enhanced hetero epitaxial growth of Si and SiGe drastic increase in the anode voltage. In chemical vapour deposition layers. It is the intention to realize a contrast to etch rates, the cleaning rates The design of the deposition chamber completely dry process sequence – i. e. are only in the range of 0.5 nm/s. These differs from those of the LEPC module. without wet chemical wafer treatment – for The reason for this are material issues this application. The high-speed growth of Figure 6: LEPECVD module: The discharge characteristics to ensure the compatibility with the self- Si and SiGe amorphous and polycrystalline UA(IA) for different argon gas flows. Despite the different design of the LEPECVD module, its discharge characteristics cleaning procedure. Figure 6 shows an layers at low temperatures is yet another allow – as in case of the LEPC module – the utilization of a example for the UA (IA) characteristics challenge for process development. wide range of anode currents and argon flows. of an argon discharge in the new For more information please contact: [email protected] Discharge characteristics in the LEPECVD module References 24 Ar flow 1 K. Rim, S. Koester, M. Hargrove, J. Chu, 30 sccm P. M. Mooney, J. Ott, T. Kanarsky, P. Ronsheim, 22 40 sccm

[V] 50 sccm M. Ieong, A. Grill, and H.-S. P. Wong, Strained

A 20 60 sccm U Si NMOSFETs for High Performance CMOS 18 70 sccm Technology, VLSI 2001 Kyoto Conference 80 sccm Proceedings, 2001 16 2 H. von Kaenel, Using LEPECVD for SiGe, 14 Chip 2, Business & Technical News from Unaxis

12 Semiconductors, 1999, p. 32 or online at Anode voltage Anode voltage www.semiconductors.unaxis.com 10 3 J. Ramm, Low Energy Plasma Processing for 8 Hetero CMOS in a 300 mm Single Wafer Cluster 10 15 20 25 30 35 40 50 Tool, Chip 5, Business & Technical News from

Anode current IA [A] Unaxis Semiconductors, July 2001, p. 24 or online at www.semiconductors.unaxis.com

Unaxis Chip | 29 Advanced Silicon

Customer-Oriented Process Development for SiGe Deposition The SIRIUS® UHV-CVD system

Figure 1: Thickness Dr. Carsten Rosenblad, Process Physicist, High Speed distribution of a Silicon, Dr. Hans Martin Buschbeck, General Manager 10 ThPolySi poly-crystalline Si Strategic Business Unit High Speed Silicon 8 layer obtained by Mean nm = 236.765 For more than one year the CVD lab in model simulation to Min nm = 231.460 6 data from spectral Trübbach/ Switzerland has been active Max nm = 240.370 4 ellipsometry in 69 in demonstrating the advantages of the Std dev = 1.735 equidistant points SIRIUS® UHV-CVD system for deposition Uniformity = 0.73 % 2 on a 200 mm wafer of HBTs and other SiGe/Si structures. 0

240.4 nm Y in cm We have been able to prove the very high –2 throughput of the system combined with 238.9 nm 237.4 nm –4 a low growth-temperature which results 235.9 nm –6 in reduced cost of ownership. The low 234.4 nm ® growth-temperature of the SIRIUS 232.9 nm –8 system opens other fields of applications, 231.5 nm –10 very importantly the possibility to process –10 –5 0 5 10 pre-structured wafers besides blank X in cm substrates. Other structures successfully demonstrated on the SIRIUS® system are relaxed buffers with low germanium Figure 2: concentration. Sheet resistance (Rs) uniformity as obtained by resistivity Uniformity calibration measurement ® The SIRIUS UHV-CVD system is a mapping: 1% 200 mm substrate batch system. The issue of uniformity across the whole wafer and the wafer-to-wafer uniformity are of crucial importance for production. To investigate the uniformity of thickness and of B concentration a number of Si, SiGe and doped structures were deposited, and the thickness and the B concentration were measured by spectral ellipsometry and sheet resistance measurement mapping.

One wafer uniformity Thickness uniformity: The thickness Sheet resistance uniformity: the change of sheet resistance across uniformity of a poly-crystalline Si layer Figure 2 shows the uniformity of the sheet the wafer originates from the distribution deposited on a 200 nm oxide is shown resistance. Here we obtain a value of in thickness. This means that the in Figure 1, where we obtain a uniformity approx. 1%. From the observed geometry uniformity in resistivity, which is the of less than 1%. The uniformity is in this of the sheet resistance distribution, which product of the thickness and the sheet case defined as the standard deviation matches that of the thickness distribution, resistance, is expected to be even better divided by the mean value. we infer that the main contribution to than 1%.

30 | Chip Unaxis SIRIUS® UHV-CVD production system

Figure 3: Improvement of thickness uniformity over the batch

250

200

150

100 after auto-profiling 50 after GR calibration

0 Thickness of poly Si [nm] W1 W2 W3 W4 W5 Wafer Batch uniformity Calibration of growth rates To verify the throughput advantages of and alloy composition the SIRIUS® system for growing SiGe The deposition of epitaxial material on profiles for the SiGe HBT calibration work a Si substrate consists of the following After growth rate Table 1: Thickness was necessary to show the excellent four parts: calibration variation of Si grown on SiO2 of 5 wafers uniformity of the system for wafer-to- ½ Transport of the gaseous hydrogenic Thickness W1 [nm] 211.3 after growth-rate wafer uniformity over a whole batch of growth-precursor to the surface Thickness W2 [nm] 214.2 calibration; wafer 25 product wafers. of the wafer Thickness W3 [nm] 213.2 positions including ½ Absorption of the precursor Thickness W4 [nm] 213.7 extreme positions of Thickness uniformity: For thickness on the surface 25 production wafer Thickness W5 [nm] 213.9 uniformity calibration, an iterative process ½ Desorption of hydrogen batch; thickness measurement with of growth rate calibration was executed. ½ Diffusion of the growth-precursor min [nm] 211.3 ellipsometry We measured thickness of poly Si layers on the surface to a crystal surface site max [nm] 214.2 grown on SiO2 wafers in extreme (max–min)/(max+min) 0.7% positions of the batch. In fact, the wafers It has been shown that for temperatures mean [nm] 213.3 W1 and W5 are positioned outside the relevant to UHV-CVD (T < 600°C) the batch of 25 product wafers. Table 1 desorption of hydrogen from the surface Uniformity 0.5% shows the excellent batch uniformity of 0.5%. Figure 3 illustrates the Figure 4: improvements to earlier calibrations. mean Sheet resistance 170 1,4 uniformity uniformity of a batch 160 1,2 of wafers and across Sheet resistance uniformity: each wafer Additionally, the uniformity of the sheet 150 1 resistance (Rs) over a batch has been 140 0,8 quantified. Again five wafers from the 130 0,6 batch have been picked, including the Uniformity on 120 0,4 one wafer [%] extreme wafer positions (W1 & W5). 110 0,2 Rs uniformity on one wafer was around 1% (Figure 2 and Figure 4). Wafer-to- 100 0 W1 W2 W3 W4 W5 wafer uniformity of Rs over the whole Wafer batch is 3%.

Unaxis Chip | 31 Figure 5: The composition of a 45 SiGe alloy grown at 40 a temperature of 35 550°C for a fixed flow of SiH4-flow 30 of 25 sccm. The Ge 25 composition was determined by 20 HR-XRD and by SIMS. is the growth-rate limiting process [1]. The 15 growth process changes as a function

Ge composition on [%] 10 of the nature of the surface, e.g., the hydrogen desorption from a SiGe surface 5 is faster than from an Si surface. In 0 addition, the hydrogen desorption rate is 0 20406080100 a rapidly increasing function of increasing GeH4/He-Flow [sccm] wafer temperature. This translates into a strong growth-rate dependence of the temperature and the alloy composition. Figure 6: Intensity of Hence, it is unavoidable to systematically photoluminescence determine the growth-rate of Si and SiGe NP of UHV-CVD grown 6 SiGe/Si MQW Si/SiGe multi- different SiGe alloys at the growth- Si quantum well temperatures of interest for epitaxial [10 periods Si 0.85 Ge 0.15 growth experiments. In the following SiGe TO (4.4 nm)/Si (9 nm)]. 4 we have concentrated on one specific The luminescence growth-temperature of 550°C. Si TO signal from the UHV- CVD structure has 2 been compared to Ge concentration in the solid as a Intensity [a.u.] SiGe that resulting from a function of the SiH4 /GeH4 gas mixture TA Si substrate. The PL The Ge composition of the deposited Si NP was performed at 0 the “Laboratorium alloy is a function of the SiH4/ GeH4 für Nanotechnologie”, mixtures for a fixed temperature. 0.8 1.0 1.2 Energy [eV] Paul Scherrer An imported given material parameter is Institut, Villingen, the Ge composition, which must then be Switzerland [2]. set by adjusting the germane and silane flow according to a calibration. A typical Assessment of high crystalline centers (point defects, metallic calibration of the Ge composition of epitaxial quality and low defect density of contamination) for the excitons must be SiGe alloy layers grown is shown in Figure 5, UHV-CVD grown layers very low, and the lifetime of the charge demonstrating the Ge composition of Photoluminescence (PL) analysis is a carriers is high. an epitaxial SiGe layer as a function of the powerful technique for the assessment In addition, the absence of a broad

germane flow for a fixed SiH4 flow of of material quality. Figure 6 shows the band of luminescence in low energy areas 25 sccm. It should be noted that the photoluminescence resulting from a (~0.8 eV) of our spectrum is proof for the germane source gas is diluted by 1:20 in UHV-CVD synthesized 10 period SiGe/Si absence of defects in our grown layers.

He, i.e., for a GeH4/He-flow of 100 sccm, multi-quantum well (MQW). The existence

the actual flow of GeH4 is 5 sccm. of an intense and sharp SiGe peak for i.e. For more information please contact: The fraction of Ge in the layers was no-phonon (NP) recombination indicates [email protected] determined by high resolution X-ray no or very low defect densities. The diffraction (HR-XRD) and by secondary ion sharpness of the peak implies that the References mass spectroscopy (SIMS). From Figure 5 thickness for the SiGe layers in the MQW 1 B.S. Meyerson, K. J. Uram, F. K. LeGoues, we deduce a linear relationship between was very well reproduced. “Cooperative growth phenomena in silicon/germanium low-temperature epitaxy,” the flow of germane and the Ge Overall, from the high intensities and Appl. Phys. Lett. 53, 2555 (1988) composition in the alloy. The linear the existence of the PL signals we infer 2 D. Grützmacher, Private Communication relationship also holds for other flows of SiH4. that the volume density of recombination and Measurement

32 | Chip Unaxis Advanced Silicon

New Trends in SiGe Technology Carbon-doped heterojunction bipolar transistors – enhancing the capability of SiGe technology

Dr. Bernd Tillack, Manager Process Research, IHP, Frankfurt (Oder), Germany The suppression of boron diffusion in and Prof. Dr. H. Jörg Osten, Department Head Breakthrough, IHP, Frankfurt (Oder), Germany SiGe:C has been explained by the coupled diffusion of carbon atoms and The incorporation of low concentrations of carbon (< 1020 cm–3) into the point defects in silicon. Boron diffusion in silicon happens via an interstitial SiGe region of a heterojunction bipolar transistor (HBT) can significantly mechanism. The effective diffusion suppress boron outdiffusion caused by subsequent processing steps. coefficient is proportional to the This effect can be described by coupled diffusion of carbon atoms and normalized concentration of self- interstitials. The diffusion of carbon Si point defects. We discuss the increase in performance and process from carbon-rich regions results in margins in SiGe heterojunction bipolar technology by adding carbon. undersaturation of silicon self-interstitials SiGe:C HBTs demonstrate excellent static parameters, exceeding the in these regions, and hence in the suppression of boron diffusion [6]. performance of state-of-the-art SiGe HBTs. C also enhances the high We demonstrated that transistors frequency performance, because it allows the use of a high B doping with excellent static and dynamic parameters can be fabricated with level in a very thin SiGe base layer without outdiffusion from SiGe, even epitaxial SiGe:C layers [2–7]. The main if post-epitaxial implants and anneals are applied. result of these investigations was that carbon supersaturation can preserve steep doping profiles without degrading The present interest in the application cause undesirable conduction band fundamental transistor parameters. As of SiGe heterojunction bipolar transistors barriers, and thus significantly degrade a result, the RF performance can be (HBTs) stems from their potential device performance. A way to reduce improved markedly. Compared to SiGe applications in integrated circuits TED effects is to use a complex, and technologies, the addition of carbon operating at radio frequencies. High- hence expensive double-polysilicon provides significantly greater flexibility in performance SiGe devices are important transistor construction. Another solution process design, offers wider latitude in

for use in ICs operating at frequencies is to grow extended undoped Si1–xGex process margins and improves scalability + of up to several GHz, such as in spacer layers between the p Si1–xGex of the transistor [3]. mobile phones, where their low power and the emitter and collector layers. The SiGe:C base of the HBT is consumption is an important advantage. However, the thickness of the SiGe layer deposited by Reduced Pressure CVD Relatively costly GaAs processing has and therefore of these spacer layers must (RPCVD) in a commercial single-wafer already met competition from silicon and be minimized to avoid strain-induced system. The excellent manufacturability SiGe products. SiGe:C devices will push defect formation. of the SiGe:C epitaxy process is further into cost-critical market fields. The IHP approach incorporates carbon demonstrated by device data. One of the key problems in npn into the epitaxial base layer of the SiGe The HBTs were fabricated in a cost- SiGe technology is to retain the narrow HBT to suppress boron outdiffusion [2]. effective, epi-free well, single-polysilicon as-grown boron profile within the TED can also be strongly reduced by technology [5] using highly doped, SiGe base layer during post-epitaxial incorporating carbon into the SiGe base narrow base layers. This transistor processing. Heat treatments and layer. The diffusion coefficient of boron construction is especially vulnerable to transient enhanced diffusion (TED) in silicon can be reduced by more than performance degradation caused by caused by annealing implantation one order of magnitude when the enhanced boron diffusion. Therefore, it damage can broaden the profile into concentration of substitutional carbon is an ideal candidate to demonstrate the adjoining Si regions [1]. This can is raised to about 1020 atoms /cm3 [3–5]. the advantages of carbon incorporation.

Unaxis Chip | 33 Advanced Silicon

Figure 1 demonstrates the impact of the deposition of the Si/SiGe:C, which SiGe:C SiGe C on B diffusion. A model stack consisting may cause HBT base profile deviations. 1021 of SiGe/Si/SiGe:C/Si was deposited. B For both doping levels we obtain Ge Ge doping was identical for SiGe and SiGe:C. deviations smaller than ±10%. The results

] 20 After a high temperature anneal or demonstrate the excellent capability of

–3 10 Si implantation and anneal (not shown here) the IHP RPCVD epitaxy process and tool the B profile is unchanged in SiGe:C for the SiGe:C HBT technology. 19 10 BB and outdiffused in SiGe. Based on our We further investigated the possible understanding of the physics behind impact of carbon on electrical layer

18 suppressed dopant diffusion, only the properties in ternary layers containing 10 substitutional C has a significant impact carbon far above the solid solubility limit. on the suppression of boron outdiffusion. The influence of the low carbon

B concentration [cm 17 10 Therefore, the optimization of the epitaxial concentration needed to suppress process regarding the C incorporation boron diffusion on band alignment is 1016 is essential for the enhancement of negligible [8]. A comparison of the 0 100 200 300 400 device performance. In Figure 2, the C measured sheet resistances with the total Depth [ m] concentration measured by SIMS and boron concentration for two identically X-ray diffraction (XRD) is shown as boron-doped SiGe layers with and without Figure 1: SiGe/Si/SiGe:C/Si model stack after function of temperature for two different a C background led to identical results [3]. thermal treatment demonstrating suppression C source gas partial pressures. The The concentration of electrically active of B outdiffusion by C substitutional C (XRD) concentration boron is not affected by carbon introduction. decreases with increasing temperature IHP has demonstrated the first modular and increasing total C concentration. integration of SiGe:C HBTs into a 250nm 2.5 SIMS Ge 20% Nevertheless, at the low concentration epi-free, dual-gate CMOS-compatible XRD levels necessary for suppression of B platform. This module fully uses 2.0 diffusion in the HBT, most of the C is the advantages of carbon, including incorporated substitutionally. suppressed boron diffusion and increased

Figure 3 shows the RSbi (internal base thermal and processing stability [7]. Key 1.5 High C Level sheet resistance) wafer histograms for two parameters of the standard HBT module different doping levels of the SiGe:C base. used for prototyping are shown in Table 1. 1.0 We obtain excellent uniformity of RSbi for RF data for high performance HBTs both doping levels. This is especially substantially exceeding 100 GHz were

C concentration [%] remarkable taking into consideration that presented during the IEDM (International 0.5 the B doping had to be performed as a Electronic Device Meeting) 2001 [9]. The spike within a very narrow SiGe:C base development of a 0.18 µm SiGe:C RF Low C Level 0.0 (about 25 nm thick). Device data BiCMOS technology is ongoing. 500 550 600 650 700 demonstrates that the high B concen- Growth Temperature [°C] tration is within the narrow base after Acknowledgements processing. In Figure 4, the histogram of The authors thank the IHP staff and the Figure 2: Substitutional (XRD) and total C (SIMS) the HBT collector current is presented for technology team for their excellent support. concentration as function of the deposition temperature the doping levels used in Figure 3. at low and high C concentration level (constant C source Regarding the epitaxy, this parameter is For further information please contact: gas partial pressure for each level) sensitive to fluctuations during the [email protected]

34 | Chip Unaxis 6 (1.70 ± 0.07) kΩ (3.05 ± 0.10) kΩ

4 Dr. Bernd Tillack Prof. Dr. H.Jörg Osten is responsible for is currently in charge of No. of the process module the Breakthrough 2 development within Department at IHP and the technology team also leads a project to Wafer 1 Wafer 2 measured structures of IHP. He is a chemist develop alternative, 0 and received his PhD high-K dielectrics. He Ω 1.60 1.70 1.80 RSbi [k ] 2.90 3.00 3.10 3.20 from the University received his PhD at Halle-Merseburg in the Institute for Physical 1980. In 1981 he joined Chemistry of the Figure 3: Wafer the IHP as a staff Academy of Sciences histograms of the member of process in Berlin. In his later SiGe:C HBT internal technology. He had career he worked at base sheet resistance 2 been the project leader the University of Illinois (RSbi) for two A = 10 x (0.42 x 0.84) E of different IHP projects. in Chicago, and at different base doping 10 Within the currently Cambridge University. levels (24 sites of an ± –5 running IHP SiGe In 1987 he was 8” wafer) (2.03 0.11) 10 A program he has been appointed professor 8 responsible for the of physical chemistry development of the at the Academy of (1.48 ± 0.14) 10-5A VBE = 0.7 V V = 0 V SiGe/SiGe:C epitaxy. Sciences. He joined 6 CB T = 304 K Since 1998 he is in the IHP in 1988. From charge of the process 1997 to 2000, he research department. was responsible for 4 the heterojunction bipolar technology No. of transistors development at IHP, 2 leading to a low-cost Wafer 1 Wafer 2 HBT module with SiGe:C base. He also 0 managed the transfer 1.25 1.45 1.65 1.85 2.05 2.25 of that module into production at Motorola. HBT collector currentent [10–5 A]

Figure 4: Wafer histograms for the Parameter 0.25 µm (standard process) HBT collector current High for two different base performance High voltage doping levels (24 sites 2 AE (µm ) 0.42 ҂ 0.84 0.42 ҂ 0.84 of an 8” wafer)

Peak fmax (GHZ) 95 90

Peak fT (GHZ) 80 55 References 1 E. J. Prinz et al., IEEE Electron Device Lett. 12 BVCEO (V) 2.4 3.2 (1991), 42. BVEBO (V) 4.5 4.5 2 H. J. Osten et al., IEDM Techn. Dig. (1997), 803 3 H. J. Osten et al., Proc. BCTM (1999), 109 BVCBO (V) 6.0 9.0 4 D. Knoll et al., IEDM Techn. Dig. (1998), 703 β 150 150 Table 1: 5 D. Knoll et al., Proc. 28th ESSDERC, (1998), 142 Key parameter of 6 H. Rücker et al., Appl. Phys. Lett. 74 (1999), 3377 VA (V) 50 90 the IHP SiGe:C HBT 7 K. E. Ehwald et al., IEDM Techn. Dig. (1999), 561

NFmin (dB) 0.8 0.8 module, fabricated 8 H. J. Osten, J. Appl. Phys. 84 (1998), 2716. in a 0.25 µm BiCMOS 9 B. Heinemann et al., to be published Assoc. Gain (dB) 17 17 process at IEDM 2001

Unaxis Chip | 35 Advanced Silicon

The Photomask Success Story

Michael D. Archuletta, General Manager The biggest performance issue with Strategic Business Unit Photomask plasma dry etch is related to the amount of exposed chrome on the plate that makes up the circuit pattern for a given The recent introduction of the new Unaxis MASK ETCHER III™ ICP device level. Each pattered layer in a dry etch system, caused a veritable revolution in the global photomask device has more or less circuit pattern industry, which resulted in an enormous increase in mask etcher equipment density depending on the operational characteristics of the device at that level sales for Unaxis. The teamwork behind this technology development and (e.g. gates, contacts/vias, metal subsequent sales achievement are a great success. interconnect, etc.). The pattern to be etched on the photomasks will have more (or less) chrome exposed to the etching Unaxis dry etch system sales have The MASK ETCHER I™ was an process depending on the density of the nearly doubled in each of the past two early success, but it was essentially a pattern at that level. In mask making, years, and because of the worldwide wafer etching system converted to this is referred to as the chrome load of acceptance of the MASK ETCHER III™ handle square quartz substrates. Many the mask. Every mask level routinely has as the de-facto dry etch production modifications to the initial design were a different chrome load ranging from standard, the year 2001 was a true necessary to evolve the system into a true 1% – 2% up to as much as 70% – 80% highlight for the Unaxis Photomask photomask chrome etcher (Figure 1). and everything in between. Business Unit. By 1998, Unaxis introduced the MASK This chrome load (or pattern density) ETCHER II™, a much improved version difference at each mask level presented a The Unaxis MASK ETCHER™ of our original offering. Early sales of the problem unique to the ICP plasma etching evolution MASK ETCHER I™ together with the process. Our customers noted early on In 1995, Unaxis developed and later design improvements lead to the that the process parameters (or process introduced the MASK ETCHER I™, proliferation of the MASK ETCHER II™ recipes) on the dry etch system had to be a plasma dry etch system designed through 1999 to every major captive and adjusted for each different chrome load. specifically for etching chrome on quartz merchant mask shop in the world. Some mask levels with very low chrome plates. The dry etch process for chrome loads and others with high chrome loads on quartz was clean and extraordinarily Photomask technology each required their own special set of accurate. Dry etched masks tested by Along with 0.13 µm device production process parameters. the wafer fabs provided superior feature came the need to produce masks to This issue was causing a severe resolution, improved level-to-level overlay support the 0.09 µm technology node. impact on dry etch performance and ultimately higher device yields. By This has forced the demand for even specifications and more importantly on early 1998, device manufacturers began better mask lithography technology dry etch yield. It was possible for specifying that all critical mask layers be and most especially better dry etch customers to develop good process “dry etched” in order to provide the equipment. Our MASK ETCHER II™ etch conditions for very low-load parts necessary feature control specifications system technology was good, but not and different, but workable process required by the demands of their good enough to support sub-100 nm etch conditions for very high-load parts. constantly shrinking device designs. technology requirements. We realized For the in-between or widely varying This moved ICP dry etch mask making early in 1999 that a revolutionary system chrome load parts, the process into full production, driving a significant development was needed to sustain our set-up was mostly “hit and miss” increase in the sale of Unaxis state-of-the-art lead in photomask experimentation, usually at the expense MASK ETCHER™ systems. etching. of many wasted parts (yield loss) while

36 | Chip Unaxis Figure 1: The MASK ETCHERTM Evolution

MASK ETCHER I™

trying to develop a workable process Constantine, Russell MASK ETCHER II™ recipe that provided the requisite finished Westerman and Jason performance specifications on the varying Plumhoff. The results of chrome loads. Most mask shops reported this work formed the basis that this single chrome load related issue for our Generation III mask etch was responsible for keeping dry etch development program that ultimately species recombination rates at surfaces yields in the 50% – 60% range. resulted in the MASK ETCHER III™. near the mask, reactor geometry, and The experimental work demonstrated reactor materials). On the other hand, Generation III development program that mask etch critical dimension (CD) the resist etch showed an “inside out” The Unaxis Photomask Business Unit uniformity is composed of both chrome pattern (where the inside of the mask research team spent several years etch uniformity as well as resist etch etched faster than the outside) with the experimenting to understand the uniformity. The experimental data resist erosion pattern being dominated fundamental etch mechanisms inside confirmed that chrome etches in an by the ion component of the electrically our equipment that control chrome “outside in” pattern (where the outside charged plasma. The uniformity of the load related etch performance. This of the mask etches faster than the inside) resist etch was dependent on the overall work was published in a series of papers and is controlled by chemical diffusion uniformity of the plasma. The revelation presented at several worldwide with the etching species being was that these were two separate and photomask industry symposiums over electronically neutral. The Chlorine gas competing processes occurring simul- a period of three years from 1997 through used to etch the chrome appeared taneously in the reaction chamber, each 1999. The final paper in this series primarily unaffected by the plasma, affecting the overall etch performance was “Plasma Etch of Binary Cr Masks: meaning the chrome etch was dominated depending on whether the chrome load CD Uniformity Study of Photomasks by the neutral reactants within the plasma, was high (low resist load) or low (high Utilizing Varying Cr Loads” by Dr. Chris based on diffusion law (mass transport, resist load).

Unaxis Chip | 37 Advanced Silicon

Unaxis Mask Etcher IITM Baseline CD uniformity characterization “However, this theory provided the key 5% Cr load 50% Cr load to understanding the direction of our future development program.”

part has a CD uniformity signature where able to develop a series of hardware + the inside has etched faster than the configuration changes that proved we outside; again, this is what we expected could sufficiently alter and improve the Edge fast 3σ = 30 nm Center fast 3σ = 29 nm to see if the part was all resist. The CD neutral species etch of the chrome. uniformities are therefore “opposite” of We quickly learned that the Gen II source underetched overetched Source: BACUS 1999 what was predicted based on the etch was incapable of the wide operating Figure 2: Overall mechanisms of the chrome and resist. conditions needed to significantly CD uniformity These were the reasons why different Although these discoveries were improve the plasma uniformity enough to of features on the process conditions were needed for somewhat disconcerting, the empirical provide good high and low load process finished mask varying chrome loads and why using facts confirmed that low load CD specifications at the same time. Langmuir the wrong process recipe for the wrong uniformity performance is controlled by probe experiments indicated that the chrome load led to poor specification diffusion management and that high load best low power plasma uniformity we performance and yield loss in the existing CD uniformity performance is controlled could ever expect from our Gen II source equipment set. This seemed simple by plasma uniformity. was approximately 25% uniformity enough. However, it was not clear at first, Over three years of continuous and over a six-inch mask area. because a contradiction became dedicated experimentation by the Unaxis By the end of 1999, it became obvious apparent when we measured the overall photomask research group have yielded we needed to launch a Third Generation CD uniformity of features on the finished these results and provided the key to our ICP source project (Gen III). mask (Figure 2). future development program. At the same time, customers were The CD uniformity measurement Throughout this time, we were also asking us to improve particle control, plots are directly opposite of what was engaged in an ongoing program to pumping speeds, nine-inch mask expected. The illustration shows that the improve the plasma uniformity of our capability, and easier maintenance. It 5% (low chrome load) part has a CD Second Generation (Gen II) source and became imperative that we have the uniformity signature where the outside its chamber hardware associated with Gen III source and all other equipment has etched faster than the inside; this is neutral species control. After some improvements available by January 1, what we expected to see if the part was extraordinary software modeling work by 2001, to keep pace with the all chrome. The 50% (high chrome load) our Photomask science team, we were semiconductor technology roadmap

Figure 3: ICP source performance results, Generation III development project comparison New ICP source performance results Gen II/Gen III Ion density profiles Ion density profiles Gen IIICP: 500 W Gen III ICP: 500 W 8 E17 8 E17 7 E17 7 E17 ] ] 3 6 E17 mTorr 3 6 E17 mTorr 5 E17 50 5 E17 50 20 20 4 E17 4 E17 10 10 3 E17 3 E17 5 5 2 E17 2 2 E17 2 Ion density [/m 1 E17 Ion density [/m 1 E17 0 E00 0 E00 –25 –20 –15 –10 –5 0 –5 –10 –15 –20 –25 –25 –20 –15 –10 –5 0 –5 –10 –15 –20 –25 Distance from center [cm] Distance from center [cm]

38 | Chip Unaxis Figure 4: Factory Generation III development project acceptance data New ICP source performance results from the first MASK ETCHER III™ 1% Cr load 50% Cr load 80% Cr load

and to take advantage of what was expected (and proved) to be a strong technology investment year in the 3σ = 5.7 nm 3σ = 8.9 nm 3σ = 10.7 nm photomask industry. One optimized system hardware set for all CR loads underetched We are pleased to report the All test masks were etched with the same process recipe overetched accomplishment of all our Gen III development goals on schedule and under budget. Furthermore, the resulting using identical Gen III hardware, the years ago for the MASK ETCHER II™. Gen III source and process chamber very same process conditions and Our model is based on the calculations for improvements have demonstrated independent of chrome load. determining equipment value developed revolutionary new process performance for the wafer fab industry in the early capabilities. An example can be found Cost of ownership 1980s by Wright, Williams & Kelly (WWK). in Figure 3. This chart shows a plasma The value of this new system technology This has become the most widely uniformity comparison between the is much more than improved mask accepted model for determining tool cost older and the new source. specifications. Being able to achieve of ownership and we are using the more The operational characteristics of the acceptable performance specifications recent 1998 WWK SEMI standard version. Gen III source showed a marked plasma is important, but being able to do it with The components in the tool cost of uniformity improvement at a wide variety a single set of process parameters is ownership calculation are shown below: of vacuum pressures. The Gen II’s plasma extraordinary. Most importantly, it is now uniformity averages > 25% over a six-inch possible to etch any mask with any *Cost of ownership (COO) = area, while the Gen III’s plasma uniformity chrome load with almost any process averages < 5% over a nine-inch area. recipe without worry of yield loss. fixed costs + operating costs + scrap costs The new source supplies a much wider We have constructed a general cost equipment life i throughput i yield i utilization operating window and the capability to of ownership model for our new eventually etch nine-inch masks if MASK ETCHER III™ and compared it *Cost of ownership model: SEMI Standard © 1998 Wright, Williams & Kelly necessary. to a similar model developed several

MASK ETCHER III™ Figure 5: Typical final production system chrome structure The real proof of improvement is in the after etching on customer test masks finished mask etch performance specifications. Figure 4 is a summary of the factory acceptance data from the first MASK ETCHER III™ production system delivered in late December 2000. The original contractual CD uniformity specification for this system was 15 nm (3 sigma). The customer insisted we etch three different test masks, each with a significantly different chrome load (1%, 50% and 80%). The new Gen III system demonstrated “better than specified performance” on all three test masks

Unaxis Chip | 39 The MASK ETCHER II™ and MASK ETCHER III™ cost of ownership is summarized in Figure 6. Mask making is a capital intensive business with very expensive operating costs. In the comparison of the two systems you The MASK ETCHERTM III can see why the MASK ETCHER III™ has become so popular. The price is $300’000 higher, yet the MASK ETCHER III™ provides higher yields. “Now is the time for Note that rise in yield equals a cost-per-mask price dropping nearly $27. the MASK ETCHER IV™!” Over the five-year life of the tool, that represents enough savings to pay back the $300’000 price difference. The 70% yield factor in our calculation Summary You can only get about twelve plates represents only one additional plate per The Unaxis MASK ETCHER III™ is the per day to the etcher because the day. One extra plate sells for an average first, true third generation photomask dry lithography systems are very slow. of $17’500. Over a year’s production, this etch tool. Its performance clearly provides So, every plate counts. Our example represents an increase in sales revenue a generational leap over everything that’s shows what happens with a mere of approximately $4.35 million US Dollars. gone before, including our own earlier increase in yield of just ten percent (10%). That is more than twice the initial cost of versions of this tool technology. In fact, most customers are reporting the new etch tool. This simply means the Our customers have recognized this a significantly higher yield than this from Mask Etcher III™ pays for itself in less new bench mark in the industry and their Mask Etcher IIIs. However, our than 6 months! have shown their continued confidence example fully illustrates the case with When buying Unaxis products the real in Unaxis by placing purchase order just a 10% increase. winners are always our customers! commitments for new MASK ETCHER III™ systems. The MASK ETCHER III™ has Figure 6: Cost of helped to solidify Unaxis as the Description Mask Etcher IITM Mask Etcher IIITM ownership calculation undisputed leader in the development Fixed cost $ 1’500’000 $ 1’800’000 and installation of state-of-the-art Operating cost (per year/2 shifts) $ 198’000 $ 198’000 ICP dry etch systems for the photomask Scrap Cost (per year) $ 144’000 $ 144’000 industry. Equipment life (years) 5 5 We would like to take this opportunity Utilization % (90% uptime x 80% use) 72% 72% to thank our customers and all of the staff at Unaxis who helped to make the MASK Throughput (1PM-mask/hour {12 masks/day}) 0.75 0.75 ETCHER III™ a reality. Yield % (usable or repairable masks) 60% 70% This success story has encouraged us to start development of the next Cost of ownership (per mask) $ 430 $ 403 generation: MASK ETCHER IV™ waiting Total dry etch mask sales revenue (per year) to be made. ($ 17’500 per mask x 1,493 masks) $ 26’127’360

Total dry etch mask sales revenue (per year) For more information please contact ($ 17’500 per mask x 1,742 masks) $ 30’481’920 [email protected]

40 | Chip Unaxis Advanced Silicon

Non-volatile Memory:The Key to Advanced Memory Devices

Dr. Reinhard Benz, Product Manager Silicon Front End Notker Kling, General Manager Strategic Business Unit Solid state will not challenge the disk before 2010 Magneto Electronics

Almost 25% of the worldwide chip market HD are memory devices, each type used for their specific advantages: the high speed MO 100 of an SRAM, the high integration density ROM of a DRAM, or the non-volatile capability of a FLASH memory device. WORM/RW 10 The industry is searching for a “holy grail” of future memory technologies MRAM to service the new upcoming market 1 FLASH

of portable and wireless devices. Capacity [GByte] The next generation of cell phones and mobile PCs are being advertised 0.1 in the media and we already seem to be so familiar with them. But new wireless 0.01 devices for the end user market would 1988 1992 1996 2000 2004 2008 allow products like web tablets, two-way pagers, PDAs, wearable computing, micro-notebooks, or automotive Figure 1: Memory technologies computing devices like telematics to None of them combines features like: market trends become as common in our daily lives as ½ The ability to retain stored charge mobile phones are today. for long periods with zero applied Of course, some of these applications or refreshed power are already available based on existing ½ High speed of data writes memory technologies, but for a ½ Low power consumption successful market penetration a much ½ Large number of write cycles higher performance at a lower price is required. Therefore, the whole industry is So there is a need for a new memory investigating different advanced memory technology. Lower costs, lower power technologies like MRAM, FRAM, OUM consumption, non-volatile techniques, or polymer devices, which we would like and the new technology should be easy to to introduce to you in greater detail. integrate into existing CMOS technology. Comparing these requirements for future FRAM memories with current memory devices, The device of a ferroelectric RAM consists we see that each of them has certain of selected crystalline materials, typically a Figure 2: Rocking curve of AlN limitations: DRAMs are difficult to integrate, crystal unit cell of perovskite PZT (PbO, on Si showing piezo characteristic together with stress and SRAMs are expensive and FLASH devices ZrO2, TiO2) = Lead-Zirconate-Titanate. uniformity optimization enabled Data can be stored by applying a very low are too slow and have a limited number by the independent regulation

of write/erase cycles. EPROMs show high voltage: the electric field moves the center of bias voltage, power, and Ar2/N2 power requirements and a poor flexibility. atom by changing the crystal orientation ratio on the CLUSTERLINE® 200.

Unaxis Chip | 41 Advanced Silicon

Motorola’s Figure 3: Oxidation AccompliTM 009 test with Al thickness combines Tri-Band variations GSM technology, GPRS, e-mail, SMS, of the unit cell. This results in a polarization and phone of these internal dipols “up” or “down”. 2,5 functionality for The first series FRAM products were complete global introduced by Ramtrom in 1994, followed communication 2,0 0.0 nm Al capabilities. by several license agreements with over oxidation threshold numerous semiconductors manufac- turers (Figure 1). Today we find products 1,5 1.5 nm Al like 4 Mbit FRAMs (Samsung) and most 1 nm Al promising products like smartcards 1,0 (Matsushita) with the benefit of a much OXY source higher write speed and which are 1.25 nm Al environmentally uncritical compared 0,5 to FLASH-EEPROMs. Calculated Co thickness reduction [nm] Calculated Co thickness reduction Unaxis Semiconductors already has 0,0 0 100 200 300 400 500 600 extensive experience with piezo- and ferroelectric layers like PZT and SBT. Exposure time [sec] Critical piezoelectric layers such as ZnO or AlN have already been developed for Unaxis CLUSTERLINE® applications get extremely stable process conditions team who have had a head start with Figure 4: XRD Spectrum of (i. e. SAW filters or BAW devices). As for these layers. In-situ annealing in a Unaxis’ leading position in the thin film Ge2Sb2 Te 5 on part of a European consortium which is process module or RTP module is also head market. This team developed a CLUSTERLINE® 200, funded by the EU, Unaxis developed avilable on the CLUSTERLINE®. dedicated MRAM deposition system sample no. 6 as the processes for piezo- and ferroelectric and introduced a special new etch deposited, sample layers in the MEDCOM project (IST-1999- MRAM process for MRAM cells. Working with no. 13 after anneal 250°C, 10 min 11411) with outstanding results in terms A magnetic RAM device consists of a various industry partners as well as in a showing excellent of stress control, small rocking curve, and MTJ (magnetic tunnel junction) and a worldwide university/industry network, conformity with thickness uniformity (Figure 2). These very transistor; the electric current switches theoretical values critical and sensitive layer characteristics the magnetic polarity (spin), and this are achieved by the independent change is sensed as resistance change. adjustment of chuck bias, pulsed These magnetic cells allow a high sputtering, and precise temperature density, very fast read and write speed control. The outstanding vacuum (< 50 nsec), and low power consumption, conditions of the PVD process modules as well as unlimited read/write endurance. in the CLUSTERLINE® are essential for All these benefits make MRAM still one of the mostly reactive processes of the piezo- the most promising candidates to replace layer as well as for the critical interfaces existing DRAMs; only the compatibility to the layers of the top and bottom in terms of materials and the temperature electrodes. The lower deposition rate of management make it difficult to integrate reactive processes leads to relatively long MRAM into existing CMOS processes. process times. Therefore, a well-controlled MRAM applications belong to the thermal coupling between chuck and strategic technologies within Unaxis. For wafer and the vacuum conditions including the past four years this market has been the right pump package are essential to a major focus of the Magneto Electronics

42 | Chip Unaxis With features like pen input, a large touch screen, voice and handwriting recognition, the Cyberite system family is considered integrated digital the state-of-art system for this particular camera, GPS, or application, featuring the world’s smallest bluetooth network footprint and multi-target design in one access, the WTC Evita2000P from process chamber. This construction Innolabs Corp. in reduces expensive clean room space Taipei is a perfect and provides the lowest downtime example for fast, between different deposition steps. wireless, professional, UHV (10–10 mbar) vacuum conditions and mobile computing (image: Innolabs are prerequisites to successfully produce Corp.). MRAM devices. Field proven deposition sources combined with a sophisticated The class 100 R&D deposition process provide very smooth OUM advantages (Figure 4). In spite of the facility in film surfaces. High magnetic bit yield To convert certain chalcogenide material current downturn of the industry as a St. Petersburg is the result of precise control of the alloys between the crystalline and whole, we expect the first series products oxidation of an 8 –10 Ångstrom thin amorphous phases by applying a certain on the market in 2003. Unaxis will be well aluminum layer into alumina. temperature has been a well-known prepared: With the CLUSTERLINE® Unaxis has extensive experience in method for over 30 years and been used Unaxis also offers the synergies with its the deposition of ultra thin stacks for thin in optical rewritable CDs and DVDs. An Materials Devision that has a lot of film head SV/GMR structures (materials area where Unaxis – with an installed experience in different phase change Figure 5: Phase like NiFe, CoFe, PtMn, IrMn, etc.). base of several hundreds of sputtering targets, and its Data Storage Devision change of GeSbTe This technology is leveraged for high systems – has a world market share of with the real phase change experts. measuring the performance of magnetic thin film MRAM over 80%. Instead of by laser, the energy These synergies have existed since reflectivity as a function of stacks closely related to the thin film could also be applied by an electrical 1997 when Unaxis installed the first temperature for ® head technology. Unaxis also provides pulse controlled by a single transistor. CLUSTERLINE 300 for a 300 mm phase different electrode advanced dry etch technology that allows In optical phase change cells, the signal change disk application. materials corrosion-free patterning of the ultra thin is given by the change of the reflectivity. film deposited without contamination of The resistance also changes dramatically the critical tunnel layer. The etch process at the transition from the amorphous Reflectivity at 632 nm vs. annealing temperature can also be combined with an integrated to the crystalline phase. Such a device (GST, AITi + GST) PECVD dielectric cap. was developed by ECD, licensed to An integrated technology team in Ovonyx Inc. and is called Ovonic Unified 70 our dedicated R&D class 100 facility in Memory (OUM). 65 St.Petersburg, Florida, is responsible Under several binary, ternary and 60 for the unique combination of advanced quaternary phase change alloys which are 55 deposition and dry etch processes in described in literature, today GeSbTe 50 Unaxis production solutions. (GST) seems to be the most promising 45 GST

For more detailed descriptions target material for the manufacture of Reflectivity [%] 40 AlTi + GST of the Unaxis metallization and etch OUM devices. 35 30 solutions for MRAM applications, The biggest benefit of OUM seems to 0 50 100 150 200 250 300 please refer to previous issues of Chip be the easy integration into conventional Annealing temperature [°C] (the online edition on our web site: CMOS process technology for DRAM and www.semiconductors.unaxis.com). FLASH, also offering significant cost

Unaxis Chip | 43 CLUSTERLINE® 300: sputtering bridge “The perfect solution for the ultimate tool on 200 mm and memory technology still eludes us, 300 mm wafers for deposition of phase but – as they say – the race has only change layers (GST) including top and just begun.” bottom electrodes

Table 1: FRAM MRAM OUM Comparison of Operation ½ Selected crystalline ½ Cell with one MTJ and ½ Electrical energy the performance materials have bi- one transistor converts the chalco- of new memory stable center atom ½ Electric current genide (phase technologies ½ Data is stored by switches the change) material applying an voltage magnetic polarity between crystalline to polarize the internal ½ Change in magnetic (conductive) and dipoles polarity sensed as amorphous (resistive) ½ Non-linear FRAM resistance phase read capacitor ½ Cell reads be ½ No iron, no measuring resistance magnetism

Advantages ½ Low power ½ High density ½ High density consumption ½ Low power ½ Low power Today Unaxis offers a bridge tool ½ Fast write ½ Read/write speed ½ Easy to integrate solution for 200/300 mm wafers for deposition of GST as well as the bottom Disadvantages Limited read and write Material compatibility Limited write/erase 13 12 and top electrodes to form a OUM cycles (10 ) with CMOS cycles (10 ) memory cell. Industry proven/ In MEMS applications Thin Film Head DVD, CD-R analogies FRAM chip available on (SV/GMR, TMR) The race is still open the market MRAM chips available FRAM, MRAM or OUM – who will make the grade? As you can see in Table 1, each Table 2: FRAM MRAM OUM technology provides technical challenges Companies developing to be overcome, which are being examined Fujitsu Hynix British Aerospace memory Hitachi IBM Intel in intensive research programs at different technologies IBM Infineon Ovonyx companies. Diversification seems to be the worldwide Infineon Motorola STMicro name of the game, and each of the major Matsushita USTC players has its own favorite (or two). Micron So, it looks like the race for the memory Motorola technology our children will be using is still NEC Samsung open. At present we can safely say that a Toshiba total replacement of DRAM and SRAM will not take place by 2003, although some of the companies mentioned in Within the next few months we can The dust of the first rush is settling, some Table 2 claimed otherwise at the end of expect all three technologies to enter the of the original participants have dropped the last century. With the emphasis on market with a dedicated product. Each out and we are now entering the second portable/wireless devices, the required technology will find its place and grow round. The perfect solution for the ultimate endurance of memory is also under from there, we can already see a great memory technology still eludes us, but – as discussion. A “limited” read/write cycle deal of diversification. One thing is certain: they say – the race has only just begun. would be more than sufficient for the non-volatile memory will make its way accepted lifetime of some of the portable and will eventually replace DRAM, SRAM, For more information please contact: devices like cell phones, PDAs, etc. FLASH, etc. [email protected]

44 | Chip Unaxis Unaxis Insights

The Making of a Worldwide Quality Management System

Werner Eisl, Manager Corporate Business Excellence Apart from the obvious organizational Helmut Ritter, Quality Manager challenge the realization also requires some technical solutions. Increasing customer expectation can only be met by For us as a global IT equipment comprehensive management systems. This notion has struggled to supplier, any solution that meets customer demands can only be achieved by be generally accepted in commerce and industry for 25 years. cooperating across geographical and Today it is taken as a matter of course that a systematic and cultural boundaries. The greatest documented quality management system facilitates cooperation challenge lies in making this management system accessible and easy to use for and forms the basis for continuous improvement towards everyone. Our previous experience with Business Excellence – if it is designed to be user-friendly. document management systems was a great help in deciding upon the actual requirements for an international quality ½ All Unaxis locations can directly management system: access and take advantage of the ½ Worldwide, easy access for all locations best practices – we call them “Global ½ A representation of the processes Processes” – and if one location suitable for the Intranet can improve on a process, all others ½ Quick access to the relevant documents profit directly from that improvement via the Intranet in German and English, as well. or other languages, if required ½ This network forms the backbone of ½ Fulfillment of ISO 9001:2000 our knowledge management system, requirements which will be systematically extended ½ Maximum use of existing platforms to also incorporate technology, product to avoid additional investment, know-how, customers, employees introduction, license, and adjustment and suppliers. costs regarding release changes of products from different suppliers A knowledge network and its usage ½ A system easy to maintain and update Figure 1: The process have to be learned and experienced – this to support the continuous improvement overview of the Helmut Ritter and his team have networked process management system and development of the management quality management achieved just that with the creation of is the classroom for Unaxis. system towards Business Excellence. system in the Unaxis a web-based, worldwide process Intranet management system. The Unaxis IT How it all began The Unaxis solution divisions now have one of the most With the introduction of the SAP R/3 There are plenty of products on the modern and user-friendly process system for economic and operational market for the administration of quality management systems and will benefit processes and the creation of global management documentation, but none in the day-to-day application: business processes at Unaxis we have fulfilled our exact requirements. The result: ½ Increased quality and decreased cycle now undertaken the next step: we rolled up our sleeves and got to work time are two benefits that result directly implementing a quality management on our own solution. from the linking of processes and work system which is applicable at all Unaxis A first rough concept was developed instructions with precise release control locations worldwide, easy to understand by the Quality Management Group, then in the SAP-system. and equally easy to use. discussed with our IT specialists and

4 | Chip Unaxis and Quality Management Departments for Figure 2: Documentation their support. Together we managed to Intranet homepage structure. The quality find a solution by using existing platforms. management system Similar concepts could be applied start page is called up to other areas where document via the Unaxis Intranet homepage. management and access to information are important.

Start page management documentation Easy access The page with the process overview of the management system (Figure 1) Process model is easily accessible for all employees via the Intranet portal. Hyperlinks give access Process overview to all required documents. A double click brings the user to the process overview. Just by clicking into the fields within the graphic of the process structure, all main and subprocesses can be accessed, right Process model down to work instructions, checklists, etc. All process overviews can also be accessed directly via the menu in the top navigation bar.

Overview Process of all valid description Communication documents (flow-chart) E-mail buttons on the start page support the direct communication – regarding questions and improvement suggestions – between user and process owner. Valid documents: ½ Work instructions Any changes or updates to the system ½ Forms are communicated periodically on the ½ Checklists start page of the management system.

Maintenance and administration checked for feasibility. After that, the A first version was quickly finished, but without programming knowledge road was clear for the specialists to as always many details of operation All documents are archived and release- proceed with the design and realization emerged during testing. It took longer controlled in the SAP R/3 document of the IT concept. Intranet-suitable than expected – with a great deal of management system. The links in the representations of the processes were dedication and determination by the Intranet, which call up the documents compiled by the Quality Management project management – to get the system from SAP, are programmed to call up only Group, and the user interface was up and running. A lot of good will and very the released version of the document. This designed by an external company which hard work delivered the results in the end. means that the release of a new version provided a very valuable contribution At this point, we would like to extend our also guarantees an up-to-date state on to the project. sincere gratitude to all involved in the IT the Intranet. Easy, isn’t it?

Unaxis Chip | 5 Advanced Silicon Money for Nothing… …and Chips for Free by reducing initial target costs and increasing material utilization on the Unaxis CLUSTERLINE®

Dr. Reinhard Benz, Product Manager Silicon Front End Dr. Hans Hirscher, Manager Process and Application Silicon Front End

Currently, the main focus of the semiconductor industry is on cost savings. The following article shows how running costs can be reduced with the CLUSTERLINE® system by using the optimized sputtering source ARQ 131 for higher material efficiency of the targets.

Cost of ownership figures clearly show Considering all these aspects, real cost that the metallization cost for precious savings can mainly be achieved by Figure 1: Au alloy target on the copper materials like Au, Pt, and their alloys are increasing the material utilization over the backing plate dominated by the target costs. Therefore, total target life. the decision was taken to concentrate All investigations were focused on further developments for the sputtering expensive materials typically used for source on improved material utilization. front and back side metallization of Minimizing the target diameter, increasing discrete Silicon wafers as well as for III-V the transfer factor (amount of material applications for telecommunications. deposited on the wafer), extending the Products for both markets are mainly target life, and decreasing the weight for manufactured on wafers with a diameter recycling will bring down the running of 150mm or smaller; therefore a process costs for expensive target materials. solution for wafer sizes from 100 up to The amount of initial target material and 150mm was developed. the amount of material for recycling are Within Unaxis the sputter source important factors with regard to the ARQ 131 is “the standard” in the sputter Figure 2: Improvement of target utilization by reduction of bound capital. tools of the Data Storage Division. It is optimization of the magnet system Minimizing the recycling material is a used in over 3’000 CD metallizers and critical issue, especially for precious alloys several hundreds of rewritable disk like AuAs, AuGe, AuSn, or PtSi. Until now systems (phase change and MO). This Table 1: Geometrical differences between the only the precious component of the source has been developed to coat sputter sources ARQ 131 and ARQ 151 alloyed material deposited on the shields and of the remaining target material at the ARQ 131 ARQ 151 end of the target life have been recycled. A slight improvement in lowering the Target diameter (sputter material) 200 260 target recycling cost was achieved by Typical thickness of sputter material 6 mm – 9 mm 9 mm – 12 mm the recent development of an optimized Thickness of the backing plate 6 mm 6 mm recycling process by Unaxis Materials (see article “Gold Makes the Process” Target-substrate distance 30 mm – 50 mm 50 mm

by Carsten Rienecker, Sales Manager, Ratio of diameters sputter material to 6" substrate 1.33 1.73 Unaxis Materials Hanau published in Ratio of the volume at 9 mm target thickness 1 1.69 Materials, July 2001).

Unaxis Chip | 45 Advanced Silicon

Figure 4: Two ARQ 131s on a CLUSTERLINE® 200 showing Au alloy targets

optical discs with a diameter of usually The parameters for tuning are: 120 mm. For the semiconductor ½ Target-substrate distance applications on 150 mm wafers, the ½ Target diameter ARQ 151 is used as a standard. ½ Magnet system Table 1 shows the geometrical differences of the two sputter sources Making the distance between the target and points out that 69% less target and the substrate smaller allows a material has to be invested in an reduction of the target diameter. The ARQ 131 compared to an ARQ 151 limitations for shrinking it even further are when a target thickness of 9mm is the minimum space for the sputter plasma applied. and the increasing substrate temperature Therefore, the goal of the re-design (due to plasma heat load and target was to enable the use of the ARQ 131 temperature). Another limitation for target-substrate distance, and target in standard process modules of the decreasing the target diameter lies in utilization. The simulation was then CLUSTERLINE® for wafers up to 150 mm the restricted possibilities of arranging paired with the practical experience for while fulfilling all required properties for the magnets of the magnet system the layout of magnet systems, as well as plane layers. in the given area. with a corresponding simulation of the Figure 3: Improved Evaluation was focused on the Several optimization loops for the magnetic fields. material utilization following issues: magnet system layout were necessary to In the lab, predictions for using a using the optimized ½ Target utilization verify an improvement in target utilization. copper target over a complete target life magnet system B on ½ the ARQ 131 sputter Coating uniformity on the substrate Computer simulations assisted in were confirmed. In cooperation with source ½ Transfer factor calculating the effect of target diameter, customers the benefit was then shown on real gold alloy targets. The usable target material was nearly doubled. Figure 3 demonstrates the optimized Initial weight 100% target utilization. It shows the target material distribution with the original magnet system A and, after several experimental loops, with the optimized magnet system B. The compromise for improving the on the material on weight for utilization material utilization is a slight decrease in substrates the shields recycling thickness uniformity. A typical value achieved with the optimized ARQ 131 is ± 6% compared to ± 4% achieved with the standard ARQ 151 over the Mag. system A 23%7% 70% 30% target life.

For further information please contact: [email protected] Mag. system B 38%14% 48% 52%

46 | Chip Unaxis Advanced Packaging

CLUSTERLINE® – Making 300 mm Possible The transition to 300 mm wafer processing has been accomplished

Dr. Christian Linder, Manager Process and Application Advanced Packaging, Wolfgang Rietzler, Product Manager Clusterline, Hans Auer, General Manager Strategic Business Unit Advanced Packaging

Over the last few years, some leading IC manufacturers have accomplished the transition to 300 mm wafer processing. Amongst the most challenging key drivers for the 300 mm technology are cost reduction, larger production volume, increased silicon utilization, high-level automation, and enhanced reliability. At the moment four production lines are up and running, and another four have been scheduled to commence operation in 2001 followed by another eight which are planned to start beyond 2001 (source: Solid State Technology, May 2001). Most 300 mm fabs are focused on front end production, but a few are beginning to extend their activities to back end applications on wafer level. The major assembly and packaging companies have now become active also in this field. In recent years, wafer level packaging (WLP) using bumping technology for flip chip has emerged as a new and important concept in advanced packaging. While the technology so far has been used mainly for high I/O (microprocessor, high-end logic) and high-frequency devices, promising applications for the future are also higher volume devices,

Figure 1: PVD process modules with excellent performance for outstanding film characteristics

Unaxis Chip | 47 Advanced Packaging

such as DRAMs. SRAMs, ASICs and a strong shift from traditional passives are expected to follow this trend. packaging to advanced packaging can With the move to 300 mm, WLP tech- be observed. nology becomes even more attractive for back end processing since the majority CLUSTERLINE® 300 for WLP of the early 300 mm production is The major bumping process steps intended for high-end devices. In addition, include underbump metallization (UBM) or redistribution (RDL) using physical vapor deposition (PVD), photolithography, electroplating, stencil printing, metal Table 1: wet etching, resist stripping, as well ® Cost of ownership Description CLUSTERLINE 300 as reflow of the bump. Based on the calculation for the Operating cost (per year) $ 523’000 excellent collaboration with other leading CLUSTERLINE® 300 Scrap cost (per year) $ 60’000 equipment manufacturers for associated Utilization 72% back end processing, Unaxis offers highly sophisticated solutions with full process Total throughput (wafers/year) 349’440 compatibility resulting in high yield. Yield 95% By employing the CLUSTERLINE®, UBM and RDL sputtering processes Cost of ownership for advanced packaging have been (average per yielded wafer) $ 4.93 successfully performed for several years

48 | Chip Unaxis Figure 2: The CLUSTERLINE® 300 design provides excellent accessibility for easy maintenance.

in 150 mm as well as 200 mm production at various leading packaging companies. Significant assets of the new CLUSTERLINE® 300 are: ½ Straightforward extrapolation to 300mm applications ½ Excellent process performance for outstanding film characteristics ½ Bridge tool configuration enables processing of 200 mm as well as 300 mm wafers ½ High throughput due to short process times ½ Thin-wafer handling and processing capability ½ Substantially lower cost of ownership than for front end single wafer PVD systems

Sputtering targets for the CLUSTERLINE® 300 can be delivered by various material suppliers. Currently, all process specifi- cations are based on targets from Unaxis Materials. The long-term collaboration between Unaxis Materials and Unaxis Semiconductors has greatly supported the successful development of this new generation of large 400 mm targets with narrow tolerances in purity and structure properties. The R&D team for sputter sources has reached excellent results with the new cathode design and by optimizing the magnet system for best target utilization.

The process must fit the application Regarding technology performance, the UBM and RDL applications of the CLUSTERLINE® meet several requirements for optimum integration into the bumping process flow. A typical sequence starts with a clean-etch step using an ICP source which induces no damage to the pre-fabricated dies on

Unaxis Chip | 49 the wafer. This etching removes native oxides and other materials such as organic residues from the wafer surface. This way the subsequent metal films (first metal of the UBM/RDL stack, e.g. Ti or Al) achieve a low contact resistivity to the metal pads of the dies and an optimum adhesion to the pads, as well as to the passivation layers on the wafer surface. Next, barrier metal films such as NiV or TiW are deposited preventing diffusion of the bump metals to the die metals. The top metals of the UBM stack are used as seed layers e.g. for subsequent plating (Cu, NiV, or Au), or as wetable material for the solder of printed bumps. In the case of RDL, the top metals serve as the conductive interconnect lines (e.g. Al, Cu). Figure 4: 400 mm bonded AI target Precise control of process parameters mechanical stress can be specifically combined with the perfectly adjusted controlled by means of process power, design of module components of the gas flow, temperature, or RF bias. The CLUSTERLINE® (e.g. chuck configuration) result are low-stress film stacks providing guarantee optimum film characteristics. mechanical stability which is needed for Figure 3: Sheet For example, electrical film properties can the long term reliability of the bump resistance distribution be tuned for lowest possible resistivity at a structure. for a Cu film given maximum process temperature as on a 300 mm well as for appropriate uniformity. This More to come – stay with us oxide wafer; enables precise metal wet etching or Close partnerships with leading device the uniformity of homogeneously distributed plating current manufacturing firms and expert 1.6% (1 sigma) is typical for an for uniform bump heights. Furthermore, equipment manufacturers have played an UBM application. depending on the film material, the essential part in the successful operation of the CLUSTERLINE® in production. Currently, the CLUSTERLINE® 300 is being implemented in the first 300 mm wafer bumping fab of one of the world’s largest providers of semiconductor packaging and testing services. Unaxis Figure 5: Open has extensive experience in WLP and process module of the ® related fields, and is participating in CLUSTERLINE 300 ongoing installations of further 300 mm lines for advanced packaging For more information please contact: applications. [email protected]

50 | Chip Unaxis Advanced Packaging

The Advantages of Integrated Passives

Dr. Johann P. Seidel, Senior Scientist PVD, Andreas Huegli, Process Engineer CLC, Multiple choices are available to Hanspeter Friedli, Process Engineer LLS, Heinz Gloor, Product Manager LLS, create capacitors. Depending on the Hans Auer, General Manager Strategic Business Unit Advanced Packaging requirements, sputtering can be efficiently

done for Al2O3, AlN, SiO2, Si3N4, Ta2O5,

Market demand for higher performance and more compact TiO2, and some more dielectrics. Because electronic products (mobile phones, PDAs, digital cameras, etc.) of the relative low sputter rates of dielectric films, PECVD techniques are is behind the integration of passive components such as preferred for the thickness range above resistors, inductors, and capacitors. Especially the requirement 2.0 to 3.0 µm. Spin-on of high k for high-frequency signal handling and the integration of optical dielectrics is used as a low cost alternative. signals into electronic packages are a major driving force for the integration of passives into various devices. Sputtering Cathodic sputter deposition is the Because of their advantage in eliminated. This technology is ideal for most versatile solution for the production performance, size and assembly cost, products such as mobile phones with of electronic circuits. Although the integrated passive devices (IPDs) are yet their high volume and the need for small starting pressure should be better than another booming area of advanced size and low cost. 2x10–8 mbar to avoid contamination, packaging. Many of today’s electronic Yet another method for passive device sputtering takes place in a low-pressure products feature 500 or more passive integration in the early stages is to atmosphere of inert gas, such as argon, devices, making conventional packages combine them on the wafer level together in the range of 10–3 mbar. and board assemblies a problem in terms with the wafer level packaging steps. By A glow discharge is formed by applying of performance, yield and cost. IPDs establishing multiple metal/passivation a high voltage (approx. 200 V–2000 V) typically combine a number of passive layers (up to 5), the passive components between anode and cathode, which is components (resistors, capacitors, and are built directly onto the die between the formed by the material to be sputtered inductors) in a single package. These chip and the first level interconnect, which (diode sputtering). An electron source devices are increasingly built on glass thin is typically a solder bump. supports ionization of the inert gas, and film substrates rather than on silicon-like The methods to produce precise the positively charged argon ions are semiconductor devices or ceramic which resistors, capacitors, and inductors on accelerated towards the cathode (triode is very high in cost. The IPD is ideally wafers or substrates usually involve thin sputtering). These ions bombard the combined with wafer level packaging – film technology for most of the cathode material (target) with high energy yielding minimal size and low costs, applications. Resistors are preferably and force atoms and molecules to break since there is no longer a need for a made by sputtering of TaN, NiCr – away from the cathode by virtue of their conventional plastic package. including its ternary alloys – and SiCr kinetic energy. Some of these sputtered Another way to integrate passives is through a lift-off type photo resist. particulates are intercepted by the to build them right into the high-density Inductors are sputtered in the shape of substrate and form a uniform thin film substrates – as integrated passive a plating base and then enforced by an layer. Adding magnets nearby the target modules (IPMs). While the process electroplating step to increase the cross increases the travel-distance of the technology is identical to IPD, the section of the trace. Alternatively, they electrons, thus increasing the probability integration of the passives into the are sputtered over the full thickness and of collision with argon molecules substrate has the advantage that no etched by subtractive etch technology, (magnetron mode). This way high extra space is needed for the passives the latter being suitable only for ratios deposition rates can be managed at low and the assembly step of the devices is of thickness to line width below 0.25. pressure. To improve the film uniformity

Unaxis Chip | 51 Advanced Packaging

Figure 1: Resistance change due to non-zero TCR

Resistance change dR/R by a non-zero TCR NiCr 150 Ohm/sq. (± 25 ppm/˚K) vs. Cermet 1500 Ohm/sq. (± 50 ppm/˚K) dR/R25°C [%] 0.80 This process is called reactive RF-substrate bias. Controllable substrate 0.60 0.40 sputtering and is used frequently to heaters and coolers with an optional 0.20 Produce resistor films like Ta2N substrate bias are available with state- 0.00 Control the TCR of NiCr films of-the-art sputter systems such as –0.20 Stuff barriers such as TiN or TiW(N) LLS EVO or CLUSTERLINE®.

–0.40 Form insulating layers like Si3N4 –0.60 or Ta2O5 Thin films for integrated passive –0.80 applications –40 –20 0 20 40 60 80 100 120 140 Temperature [ ˚C] When increasing the flow rate of the Important applications of integrated Cermet (TCR ± 50 ppm/°K) NiCr (TCR ± 25 ppm/°K) reactive gas, the metal sputtering mode passives: with a high deposition rate due to a Clock terminators and filter networks metallic non-contaminated target, has to used in CPUs such as INTEL’s Pentium be distinguished from the compound EMI filters and ESD protectors Absolute resistance change of NiCr films mode, where with increasing reactive Zero Ohm jumper arrays as a function of time and temperature gas flow, reactive products are also Bus terminators such as serial/parallel dT (TCR) = 100˚K ,dt = 1000h at 150˚C formed at the target surface, causing the termination array networks and AC dR/R = f (t, T) [%] deposition rate to slow down. Slightly termination networks 1.50 doped NiCr resistors and Ta2N films are Precision resistor arrays, such as 1.25 sputtered in the metallic mode, whereas isolated and bussed resistor networks, 1.00 insulating layers will utilize the compound voltage divider networks, and audio 0.75 0.50 mode. To keep such processes stable, resistor arrays 0.25 a pulsed DC power supply may be helpful. 0.00 If the deposition should take place in the All these applications contain a more or 0 200 400 600 800 1000 1200 1400 1600 1800 2000 transient region between metallic and less large amount of resistors, capacitors, Sheet Resistance [Ohm/square] compound mode, a process control and inductors. High-quality requirements, dR/R non-zero TCR dR/R long-term drift can be installed, which maintains the especially for resistor films, lead to gas flow by mass spectrometry sputter-deposited thin film solutions. Figure 2: Resistance and the metal rate by optical emission change as a function across the substrate, either the substrates spectrometry (OES). If the target already Resistors of time and are rotated relative to the cathode (batch is an insulating material, then an RF Most important for the practical use of temperature type with rotating drum), or the magnetic plasma system – usually operating at resistors in IP circuits is the capability to field rotates behind the target (often used 13.56 MHz – is the appropriate solution. sustain a certain nominal resistance value with single wafer solutions). Very tight Sputtering can occur, because the target over the entire time of use. tolerances of film thickness < ± 2% is bombarded in the RF-field with ions and A non-zero temperature coefficient of across a 200 mm wafer can be realized. electrons alternatively. resistance (TCR) leads to a resistance Sputtering offers the highly interesting Heating the substrates before or during change as a function of variable operating possibility to change the chemical the deposition will influence the mobility temperatures (Figure 1), while a long-term composition of the deposited film by of the incoming molecules and atoms drift of the film material leads to a applying reactive gases such as oxygen and thus control gas incorporation. The resistance change as a function of time. or nitrogen to the inert gas atmosphere. deposition temperature influences film Figure 2 shows the superposition of both The properties of the deposited film parameters such as stress, adhesion, effects for a sheet resistance range from can be altered depending on the density, and resistance. Similar effects 2 Ohm/square to 2’000 Ohm/square. concentration of the added reactive gas. can be achieved by applying DC- or For this example, a temperature change

52 | Chip Unaxis Figure 5: Interconnect wiring with integrated passive devices

0.03% after 1’000 hours at 150°C.

Cermets are suitable materials when TaN: Nitrogen concentration and specific resistance higher sheet resistance values are required. as function of N2 flo w Compound targets, co-sputtering and 1.60 reactive sputtering are techniques to 1.40 250.0

realize a semicontinuous conductive 1.20 Ohm · cm] phase with an appropriate composition 200.0 1.00 of dielectric and conductive components. of 100°K during operation and storage TCR values below 200 ppm/°K and a 0.80 150.0 for 1’000 hours at 150°C was assumed. sheet resistance up to 2’000 Ohm/square 0.60 The most stable region is between 50 have been achieved with combinations N content [Mol] 0.40 Ta: 1 Mol 100.0 Ohm/square to 200 Ohm/square. of NiCr and SiO2 or Al2O3. If TCR Specific resistance [ Sophisticated sputter techniques like requirements are not so stringent, SiCr 0.20 reactive sputtering and sputtering of is a proven cermet material. Long-term 0.00 50.0 ternary alloys are the key for NiCr- and stability is comparable to standard 020255 10 15 N flow [sccm] Tantalum-based films with high stability NiCr films. 2 and low TCR over a wide range of sheet Ta-based thin films are an attractive N (Mol) Specific resistance [ Ohm · cm] resistance values, e.g. from 2 to 2’000 alternative to the NiCr films above. In Ohm/square. Furthermore, sputtered thin addition to its refractory nature, which Figure 3: Specific films exhibit a superior performance with implies that any imperfection frozen in resistance of TaN obtained on the respect to noise level, even in the GHz during deposition will not anneal out CLUSTERLINE®. frequency range. during lifetime, tantalum belongs to a NiCr films cover an especially wide class of metals known as valve metals, range of applications. Standard NiCr which form tough self-protective oxides, 300 films, reactively sputtered from a either through anodic oxidation or through

compound target in an oxygen heat treatment in an oxygen atmosphere. Ohm-cm] 6 atmosphere, are available with a sheet Since tantalum is such a reactive material, – 250 resistance up to 300 Ohm/square, a TCR the sputtered films have a tendency to below ± 25 ppm/°K and a long-term be contaminated during deposition. stability of about 0.1% deviation from the A controlled contamination is desirable 200 nominal value after 1’000 hours storage to achieve useful properties. The most at 150°C. common process is reactive sputtering in Resistor films for high-frequency a nitrogen atmosphere to form Ta N films. x Specific resistance [x 10 150 applications adhere well to highly polished By increasing the N flow the resistance 2 0 0.5 1 1.5 2 2.5 3 3.5 glass, quartz, sapphire or AlN substrates. rises and levels out at ~ 200 to –4 N2 – partial pr essure [x 10 mbar] Dissipation by magnetic materials should 250 µOhm · cm, whereas the TCR drops be avoided. NiCr films with very low Ni down from positive values and stays at Figure 4: Specific content, reactively sputtered in a nitrogen ~ –100 ppm/°K. The composition of resistance of TaN obtained on LLS EVO atmosphere, will match those these “plateau” films is very close to Ta2N requirements. and displays the greatest stability during Sputtering of ternary alloys such as load-life tests.

NiCrAl provide a TCR below ± 10 ppm/°K To reach a stable final value, Ta2N films and a long-term stability better than need a thermal post-treatment just like

Unaxis Chip | 53 Titanium-Tungsten or Titanium Nitride > 1012 Ohm · cm, a high dielectric will help to improve temperature stability of strength, and a high dielectric constant.

the circuit and reduce diffusion, migration, Ta 2O5 has a very high dielectric constant

and segregation of contact material into of 25 (at 100 kHz), followed by Al203 with

the resistance layers and vice versa. 9 and Si3N4 with 8. With a thickness of only ~ 200 nm, breakdown voltage values

Figure 6: Multilayer Capacitors of 50 V are reported with Ta2O5 and metallization NiCr films. A good indicator for plateau High-value bypass capacitors to be Si3N4, achieving a dielectric strength scheme with films is the fact that the TCR is only integrated via thin film techniques are a of 3 to 5 MV/cm. The achievable integrated thin film resistors (R) and negligibly changed during this heat challenge. For frequencies exceeding capacitance per square is comparable capacitors (C) treatment, whereas the resistance the 100 MHz range, thick film solutions to thick film capacitors. However, the thin value rises, depending on time and show an increasing dielectric dispersion, film version appears much more stable temperature. The sheet resistance therefore thin film capacitors are superior. and better suited to high-frequency increases because during heat treatment Integrated thin film capacitors may exist of requirements.

the surface of the Ta2N film is changed a sputtered conductive bottom electrode, to self-protective oxide and the electrical an RF, or a reactively sputtered dielectric Conclusion

effective thickness of the Ta2N layer layer such as AlN, Al2O3, Si3N4, SiO2, or When it comes to integrated thin film

decreases. This effect may be used for Ta 2O5, and a conductive top electrode. circuits, state-of-the-art technology thermal trimming of the resistors without Generally, a great variety of metal/insulator is guaranteed with a Unaxis sputter any laser cut, which is an important fact combinations is possible, depending on deposition system, whether a load lock for very-high-frequency applications. the technical requirements and the batch system such as LLS EVO or a The common sheet resistance range compatibility with the materials below and single wafer system such as the ® for Ta2N films is 30 to 300 Ohm/square above the capacitor. CLUSTERLINE . with a TCR between –70 to –130 ppm/°K. Unified solutions with only one base All coated substrates distinguish

Long-term stability is better than 0.05% material are Ta // Ta2O5 // Ta or Al // themselves through

after 1’000 hours at 150°C. For higher Al2O3 // Al, which could theoretically be ½ Very low TCR sheet resistance requirements performed with only one sputter source, ½ Excellent long-term stability cermet films such as TaSi are available. using the technique of reactive DC ½ Low stress or RF sputtering. More sophisticated ½ Extremely tight tolerances High-conductive films for solutions have electrode stacks, including ½ High uniformity interconnect wiring adhesion layers as well as barrier layers. ½ Small critical dimensions In high-density and high-frequency Typical electrode materials are either good ½ Highly reproducible values from applications combined with integrated conductors, such as Al, Au, Cu, Pt, or substrate to substrate and from passives, aluminum or copper rewiring is perform a good adhesion, such as Cr, batch to batch

used instead of the more expensive gold, MnO2, Nb, Ta, Ti, and TiW. Additional which was typically used in former hybrid barrier layers to avoid diffusion and High uniformity, high process flexibility, applications. The thickness range of these migration – once between the surrounding excellent yield, and easy-to-service layers is between 0.5 µm and 5.0 µm, of the capacitor and second between equipment with high up-time are the thin enough to be sputtered within a conductor and insulator of the capacitor advantages that speak for an economical reasonable amount of time with modern itself – are materials such as Ni, NiCr, integrated passive thin film solution.

planar magnetron technology. Adhesion Ta xN, TiN, TiOx, ZrO2, and many more. promoters such as Chrome or Titanium, Suitable dielectrics for capacitors For more information please contact: and barrier layers such as Nickel, have a high insulation resistance [email protected]

54 | Chip Unaxis Advanced Packaging

APiA – the New Alliance for Advanced Packaging Solutions

Hans Auer, General Manager Strategic Business Unit Advanced Packaging A worldwide alliance The APiA unites a global group of industry leaders with the expertise, insight, and The APIA members technical know-how necessary to pursue viable solutions to sophisticated packaging challenges. The founding members of the alliance represent Asia, Europe, and the United States – a culturally diverse organization that incorporates the strengths of each geographical region: ½ August Technology Automated, visual micro-defect inspection equipment ½ Casio Computer Manufacturing and process development of WL-CSP and wafer bump ½ Dainippon Screen Manufacturing Coat/bake/develop equipment ½ EBARA Corporation Advanced plating technology and equipment ½ Flip Chip Technologies Solder bumping services and wafer level packaging solutions ½ Ultratech Stepper Unaxis Semiconductors is a founding member of a group of leading Advanced photolithography systems semiconductors equipment and process suppliers who together ½ Unaxis Semiconductors Thin film production solutions announced the Advanced Packaging and Interconnect Alliance (APiA) on December 5th, 2001. Comprehensive, risk-free, advanced packaging solutions The great challenge of creating high- implementation of commercially viable, Remaining competitive in the dynamic performance, low-cost packaging for comprehensive and risk-free packaging environment of the industry requires constantly advancing semiconductor solutions that address the escalating considerable effort in technology devices requires innovative solutions manufacturing and performance development and in the establishment that can only result from a collaborative challenges of the industry. The alliance of manufacturing infrastructure. The effort between leading companies in the will concentrate on enhancing the alliance will offer a complete line of industry. Equipment, process technology productivity and reliability of the equipment commercially viable and proven advanced and process material companies holding and process solutions critical for packaging and interconnect production leading positions in their field of emerging advanced packaging and interconnect solutions. APiA is a unique source packaging and interconnect technologies processes, as well as developing for equipment, materials, technology, have joined forces. The APiA is focused guidelines and standards to enable and expertise, and provides next on accelerating the development and easy adoption of these technologies. generation technology solutions while

Unaxis Chip | 55 Unaxis Semiconductors Dainippon Screen Ultratech Stepper Ebara August Technology

Process flow diagram of the Flip Chip Technologies Casio Computer 300 mm advanced packaging pilot line

minimizing the inherent risks associated work together in technology development, companies, bump service providers, with the adoption of these technologies. creating an integrated and seamless equipment and materials suppliers, and process for turnkey advanced packaging other interested parties. The alliance 300 mm advanced packaging solutions. Completion of the first will foster an open dialogue between demonstration line US-based process development equipment suppliers and device The alliance will concentrate on bump and demonstration line is scheduled manufacturers serving as both a forum processing and wafer level chip scale for the second half of 2002. to discuss advanced interconnect issues packaging – a market in which all and requirements, as well as a venue founding APiA members have leading Creating advanced packaging for members to share technology, process technology positions. APiA plans to guidelines and standards and market information. establish 300 mm pilot lines in the United The commercialization of emerging If you are interested in the Advanced States and Asia to be used by alliance technologies requires standards and Packaging and Interconnect Alliance members as well as customers. For the guidelines for successful implementation. please visit: www.apialliance.com. first time, customers will be able to APiA will lead this effort for the advanced evaluate a working 300 mm advanced packaging technologies by acting as For more information about Unaxis packaging process line, collaborating with a central information resource, and by within APiA please contact: Close to 200 visitors attended the first each individual supplier to evaluate tools establishing a standards committee. [email protected]. APiA Seminar at the and process technologies. The 300 mm This committee will be open to chip Hotel Francs in Chiba pilot lines will allow member companies to manufacturers, assembly and packaging

The APiA Press Conference at Semicon Japan, December 5th 2001 (from left to right): Jeff O’Dell, August; Juerg Steinmann, Unaxis; Akira Ogata, Ebara; Nobutoshi Ogami, Dainippon Screen Manufacturing; Art Zafiropoulo and Ellery Buchanan, Ultratech; Yukio Kasio, Casio; Gil Olachea, Flip Chip Technologies

56 | Chip Unaxis Unaxis Insights

February 5th –7th Semicon Korea Seoul www.semikorea.org

March 4th –6th Key Conference Key West, Florida, USA www.keyconference.com

26th –27th Semicon China Shanghai www.semi.org

April 8th –11th GaAs Mantech San Diego www.gaas.org

10th –12th Diskcon Japan / ODP Tokyo www.diskconjapan.com

16th –18th Semicon Europe Munich, Germany www.semi.org

23th –25th Photomask Japan Yokohama www.spie.org

May 12 th –16th IPRM Stockholm, Sweden www.congrex.com/iprm2002

July 8th –12th IPFA Singapore www.ieee.org/ipfa

22th –24th Semicon West San Francisco Wafer Processing www.semi.org 17th –19th Final Manufacturing

For updates please check www.semiconductors.unaxis.com events

events Unaxis at Semicon West, Semicon Japan, Semicon Europe, and Semicon Taiwan (from left to right)

Unaxis Chip | 57