Skylake Platform Controller Hub H and LP (SKL PCH H / LP)

Register Information (UART, I2C, GSPI, eMMC, SDXC, and GPIO)

June 2015

Document Number: 332219-002 You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. Intel technologies may require enabled hardware, specific software, or services activation. Check with your system manufacturer or retailer. All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest Intel product specifications and roadmaps. The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. No computer system can be absolutely secure. Intel does not assume any liability for lost or stolen data or systems or any damages resulting from such losses. Warning: Altering PC clock or memory frequency and/or voltage may (i) reduce system stability and use life of the system, memory and processor; (ii) cause the processor and other system components to fail; (iii) cause reductions in system performance; (iv) cause additional heat or other damage; and (v) affect system data integrity. Intel assumes no responsibility that the memory, included if used with altered clock frequencies and/or voltages, will be fit for any particular purpose. Check with memory manufacturer for warranty and additional details. Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548- 4725, or go to: http://www.intel.com/design/literature.htm Code names featured are used internally within Intel to identify products that are in development and not yet publicly announced for release. Customers, licensees and other third parties are not authorized by Intel to use code names in advertising, promotion or marketing of any product or services and any such use of Intel's internal code names is at the sole risk of the user. Intel, Ultrabook, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2015, Intel Corporation. All Rights Reserved.

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Contents

1 UART Interface (D30:F0/F1 and D25:F0)...... 33 1.1 UART PCI Configuration Registers Summary...... 33 1.1.1 Device ID and Vendor ID Register (DEVVENDID)—Offset 0h...... 33 1.1.2 Status and Command (STATUSCOMMAND)—Offset 4h...... 34 1.1.3 Revision ID and Class Code (REVCLASSCODE)—Offset 8h ...... 35 1.1.4 Cache Line Latency Header and BIST (CLLATHEADERBIST)—Offset Ch ...... 36 1.1.5 Base Address Register (BAR)—Offset 10h ...... 36 1.1.6 Base Address Register High (BAR_HIGH)—Offset 14h...... 37 1.1.7 Base Address Register 1 (BAR1)—Offset 18h...... 37 1.1.8 Base Address Register1 High (BAR1_HIGH)—Offset 1Ch ...... 38 1.1.9 Subsystem Vendor and Subsystem ID (SUBSYSTEMID)—Offset 2Ch...... 39 1.1.10 Expansion ROM Base Address (EXPANSION_ROM_BASEADDR)—Offset 30h .... 39 1.1.11 Capabilities Pointer (CAPABILITYPTR)—Offset 34h...... 40 1.1.12 Interrupt Register (INTERRUPTREG)—Offset 3Ch ...... 40 1.1.13 Power Management Capability ID (POWERCAPID)—Offset 80h...... 41 1.1.14 PME Control and Status (PMECTRLSTATUS)—Offset 84h ...... 42 1.2 UART Memory Mapped Registers Summary ...... 43 1.2.1 Receive Buffer Register (RBR)—Offset 0h ...... 43 1.2.2 Transmit Holding Register (THR)—Offset 0h ...... 44 1.2.3 Divisor Latch Low Register (DLL)—Offset 0h...... 44 1.2.4 Interrupt Enable Register (IER)—Offset 4h...... 45 1.2.5 Divisor Latch High (DLH)—Offset 4h...... 46 1.2.6 FIFO Control Register (FCR)—Offset 8h ...... 46 1.2.7 Line Control Register (LCR)—Offset Ch ...... 47 1.2.8 MCR (MCR)—Offset 10h ...... 48 1.2.9 LSR (LSR)—Offset 14h ...... 49 1.2.10 MSR (MSR)—Offset 18h ...... 51 1.2.11 SCR (SCR)—Offset 1Ch ...... 51 1.2.12 SRBR_STHR0 (SRBR_STHR0)—Offset 30h ...... 52 1.2.13 FAR (FAR)—Offset 70h ...... 53 1.2.14 TFR (TFR)—Offset 74h ...... 54 1.2.15 RFW (RFW)—Offset 78h ...... 54 1.2.16 USR (USR)—Offset 7Ch ...... 55 1.2.17 TFL (TFL)—Offset 80h ...... 56 1.2.18 RFL (RFL)—Offset 84h...... 56 1.2.19 SRR (SRR)—Offset 88h ...... 57 1.2.20 SRTS (SRTS)—Offset 8Ch...... 57 1.2.21 SBCR (SBCR)—Offset 90h ...... 58 1.2.22 SDMAM (SDMAM)—Offset 94h...... 59 1.2.23 SFE (SFE)—Offset 98h ...... 59 1.2.24 SRT (SRT)—Offset 9Ch...... 60 1.2.25 STET (STET)—Offset A0h...... 60 1.2.26 HTX (HTX)—Offset A4h ...... 61 1.2.27 DMASA (DMASA)—Offset A8h ...... 61 1.2.28 CPR (CPR)—Offset F4h...... 62 1.0 UART Additional Registers Summary ...... 64 1.1 CLOCKS (CLOCKS)—Offset 200h ...... 64 1.2 RESETS (RESETS)—Offset 204h ...... 65 1.3 Active LTR (ACTIVELTR_VALUE)—Offset 210h ...... 65 1.4 IDLE LTR (IDLELTR_VALUE)—Offset 214h...... 66

332219-002 3 1.5 reg_TX_BYTE_COUNT (TX_BYTE_COUNT)—Offset 218h ...... 67 1.6 reg_RX_BYTE_COUNT (RX_BYTE_COUNT)—Offset 21Ch...... 68 1.7 SW SCRATCH 0 (SW_SCRATCH_0)—Offset 228h...... 69 1.8 reg_CLOCK_GATE (CLOCK_GATE)—Offset 238h...... 69 1.9 reg_REMAP_ADDR_LO (REMAP_ADDR_LO)—Offset 240h...... 70 1.10 reg_REMAP_ADDR_HI (REMAP_ADDR_HI)—Offset 244h...... 70 1.11 Capabilities (CAPABLITIES)—Offset 2FCh ...... 71 1.12 UART Byte Address Control (GEN_REGRW7)—Offset 618h ...... 72 1.3 UART DMA Controller Registers Summary ...... 72 1.3.1 DMA Transfer Source Address Low (SAR_LO0)—Offset 800h ...... 73 1.3.2 DMA Transfer Source Address High (SAR_HI0)—Offset 804h...... 74 1.3.3 DMA Transfer Destination Address Low (DAR_LO0)—Offset 808h...... 75 1.3.4 DMA Transfer Destination Address High (DAR_HI0)—Offset 80Ch ...... 76 1.3.5 Linked List Pointer Low (LLP_LO0)—Offset 810h...... 77 1.3.6 Linked List Pointer High (LLP_HI0)—Offset 814h ...... 78 1.3.7 Control Register Low (CTL_LO0)—Offset 818h ...... 78 1.3.8 Control Register High (CTL_HI0)—Offset 81Ch...... 80 1.3.9 Source Status (SSTAT0)—Offset 820h ...... 81 1.3.10 Destination Status (DSTAT0)—Offset 828h ...... 82 1.3.11 Source Status Address Low (SSTATAR_LO0)—Offset 830h...... 83 1.3.12 Source Status Address High (SSTATAR_HI0)—Offset 834h ...... 83 1.3.13 Destination Status Address Low (DSTATAR_LO0)—Offset 838h ...... 84 1.3.14 Destination Status Address High (DSTATAR_HI0)—Offset 83Ch...... 84 1.3.15 DMA Transfer Configuration Low (CFG_LO0)—Offset 840h ...... 85 1.3.16 DMA Transfer Configuration High (CFG_HI0)—Offset 844h...... 87 1.3.17 Source Gather (SGR0)—Offset 848h...... 88 1.3.18 Destination Scatter (DSR0)—Offset 850h ...... 89 1.3.19 Raw Interrupt Status (RawTfr)—Offset AC0h ...... 89 1.3.20 Raw Status for Block Interrupts (RawBlock)—Offset AC8h ...... 90 1.3.21 Raw Status for Source Transaction Interrupts (RawSrcTran)—Offset AD0h...... 90 1.3.22 Raw Status for Destination Transaction Interrupts (RawDstTran)—Offset AD8h ...... 91 1.3.23 Raw Status for Error Interrupts (RawErr)—Offset AE0h ...... 91 1.3.24 Interrupt Status (StatusTfr)—Offset AE8h ...... 92 1.3.25 Status for Block Interrupts (StatusBlock)—Offset AF0h ...... 93 1.3.26 Status for Source Transaction Interrupts (StatusSrcTran)—Offset AF8h...... 93 1.3.27 Status for Destination Transaction Interrupts (StatusDstTran)—Offset B00h ...93 1.3.28 Status for Error Interrupts (StatusErr)—Offset B08h...... 94 1.3.29 Mask for Transfer Interrupts (MaskTfr)—Offset B10h ...... 94 1.3.30 Mask for Block Interrupts (MaskBlock)—Offset B18h...... 95 1.3.31 Mask for Source Transaction Interrupts (MaskSrcTran)—Offset B20h ...... 96 1.3.32 Mask for Destination Transaction Interrupts (MaskDstTran)—Offset B28h ...... 97 1.3.33 Mask for Error Interrupts (MaskErr)—Offset B30h...... 97 1.3.34 Clear for Transfer Interrupts (ClearTfr)—Offset B38h ...... 98 1.3.35 Clear for Block Interrupts (ClearBlock)—Offset B40h...... 98 1.3.36 Clear for Source Transaction Interrupts (ClearSrcTran)—Offset B48h ...... 99 1.3.37 Clear for Destination Transaction Interrupts (ClearDstTran)—Offset B50h...... 99 1.3.38 Clear for Error Interrupts (ClearErr)—Offset B58h ...... 100 1.3.39 Combined Status register (StatusInt)—Offset B60h ...... 100 1.3.40 DMA Configuration (DmaCfgReg)—Offset B98h ...... 101 1.3.41 DMA Channel Enable (ChEnReg)—Offset BA0h ...... 102 2 Generic SPI Interface (D30:F2)...... 103 2.1 Generic SPI PCI Configuration Registers Summary ...... 103 2.1.1 Device ID and Vendor ID Register (DEVVENDID)—Offset 0h ...... 103

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2.1.2 Status and Command (STATUSCOMMAND)—Offset 4h...... 104 2.1.3 Revision ID and Class Code (REVCLASSCODE)—Offset 8h ...... 105 2.1.4 Cache Line Latency Header and BIST (CLLATHEADERBIST)—Offset Ch ...... 105 2.1.5 Base Address Register (BAR)—Offset 10h ...... 106 2.1.6 Base Address Register High (BAR_HIGH)—Offset 14h...... 107 2.1.7 Base Address Register 1 (BAR1)—Offset 18h...... 107 2.1.8 Base Address Register1 High (BAR1_HIGH)—Offset 1Ch ...... 108 2.1.9 Subsystem Vendor and Subsystem ID (SUBSYSTEMID)—Offset 2Ch...... 109 2.1.10 Expansion ROM base address (EXPANSION_ROM_BASEADDR)—Offset 30h .. 109 2.1.11 Capabilities Pointer (CAPABILITYPTR)—Offset 34h...... 110 2.1.12 Interrupt Register (INTERRUPTREG)—Offset 3Ch ...... 110 2.1.13 PowerManagement Capability ID (POWERCAPID)—Offset 80h...... 111 2.1.14 PME Control and Status (PMECTRLSTATUS)—Offset 84h ...... 111 2.2 Generic SPI (GSPI) Memory Mapped Registers Summary ...... 112 2.2.1 SSP (GSPI) Control Register 0 (SSCR0)—Offset 0h ...... 112 2.2.2 SSP (GSPI) Control Register 1 (SSCR1)—Offset 4h ...... 114 2.2.3 SSP (GSPI) Status Register (SSSR)—Offset 8h ...... 115 2.2.4 SSP (GSPI) Data (SSDR)—Offset 10h...... 116 2.2.5 SSP (GSPI) Time Out (SSTO)—Offset 28h...... 117 2.2.6 SPI Transmit FIFO (SITF)—Offset 44h ...... 117 2.2.7 SPI Receive FIFO (SIRF)—Offset 48h ...... 118 2.3 Generic SPI (GSPI) Additional Registers Summary ...... 119 2.3.1 CLOCKS (CLOCKS)—Offset 200h ...... 119 2.3.2 RESETS (RESETS)—Offset 204h ...... 120 2.3.3 ACTIVE LTR (ACTIVELTR_VALUE)—Offset 210h ...... 121 2.3.4 Idle LTR Value (IDLELTR_VALUE)—Offset 214h ...... 122 2.3.5 TX Bit Count (TX_BIT_COUNT)—Offset 218h ...... 123 2.3.6 Rx Bit Count (RX_BIT_COUNT)—Offset 21Ch...... 123 2.3.7 reg_SSP_REG (SSP_REG)—Offset 220h...... 124 2.3.8 SPI CS CONTROL (SPI_CS_CONTROL)—Offset 224h...... 125 2.3.9 SW SCRATCH [3:0] (SW_SCRATCH)—Offset 228h ...... 125 2.3.10 Clock Gate (CLOCK_GATE)—Offset 238h ...... 126 2.3.11 Remap Address Low (REMAP_ADDR_LO)—Offset 240h ...... 126 2.3.12 Remap Address High (REMAP_ADDR_HI)—Offset 244h ...... 127 2.3.13 Delay Rx Clock (DEL_RX_CLK)—Offset 250h ...... 127 2.3.14 Capabilities (CAPABLITIES)—Offset 2FCh...... 128 2.4 Generic SPI (GSPI) DMA Controller Registers Summary ...... 129 2.4.1 DMA Transfer Source Address Low (SAR_LO0)—Offset 800h ...... 130 2.4.2 DMA Transfer Source Address High (SAR_HI0)—Offset 804h ...... 131 2.4.3 DMA Transfer Destination Address Low (DAR_LO0)—Offset 808h ...... 132 2.4.4 DMA Transfer Destination Address High (DAR_HI0)—Offset 80Ch...... 133 2.4.5 Linked List Pointer Low (LLP_LO0)—Offset 810h ...... 134 2.4.6 Linked List Pointer High (LLP_HI0)—Offset 814h...... 135 2.4.7 Control Register Low (CTL_LO0)—Offset 818h ...... 135 2.4.8 Control Register High (CTL_HI0)—Offset 81Ch ...... 137 2.4.9 Source Status (SSTAT0)—Offset 820h...... 138 2.4.10 Destination Status (DSTAT0)—Offset 828h ...... 139 2.4.11 Source Status Address Low (SSTATAR_LO0)—Offset 830h ...... 139 2.4.12 Source Status Address High (SSTATAR_HI0)—Offset 834h...... 140 2.4.13 Destination Status Address Low (DSTATAR_LO0)—Offset 838h...... 140 2.4.14 Destination Status Address High (DSTATAR_HI0)—Offset 83Ch ...... 141 2.4.15 DMA Transfer Configuration Low (CFG_LO0)—Offset 840h ...... 142 2.4.16 DMA Transfer Configuration High (CFG_HI0)—Offset 844h ...... 143 2.4.17 Source Gather (SGR0)—Offset 848h ...... 144 2.4.18 Destination Scatter (DSR0)—Offset 850h...... 145

332219-002 5 2.4.19 Raw Interrupt Status (RawTfr)—Offset AC0h ...... 145 2.4.20 Raw Status for Block Interrupts (RawBlock)—Offset AC8h ...... 146 2.4.21 Raw Status for Source Transaction Interrupts (RawSrcTran)—Offset AD0h.... 146 2.4.22 Raw Status for Destination Transaction Interrupts (RawDstTran)—Offset AD8h ...... 147 2.4.23 Raw Status for Error Interrupts (RawErr)—Offset AE0h ...... 147 2.4.24 Interrupt Status (StatusTfr)—Offset AE8h ...... 148 2.4.25 Status for Block Interrupts (StatusBlock)—Offset AF0h ...... 148 2.4.26 Status for Source Transaction Interrupts (StatusSrcTran)—Offset AF8h...... 149 2.4.27 Status for Destination Transaction Interrupts (StatusDstTran)—Offset B00h . 149 2.4.28 Status for Error Interrupts (StatusErr)—Offset B08h...... 150 2.4.29 Mask for Transfer Interrupts (MaskTfr)—Offset B10h ...... 150 2.4.30 Mask for Block Interrupts (MaskBlock)—Offset B18h...... 151 2.4.31 Mask for Source Transaction Interrupts (MaskSrcTran)—Offset B20h ...... 152 2.4.32 Mask for Destination Transaction Interrupts (MaskDstTran)—Offset B28h ..... 152 2.4.33 Mask for Error Interrupts (MaskErr)—Offset B30h...... 153 2.4.34 Clear for Transfer Interrupts (ClearTfr)—Offset B38h ...... 153 2.4.35 Clear for Block Interrupts (ClearBlock)—Offset B40h...... 154 2.4.36 Clear for Source Transaction Interrupts (ClearSrcTran)—Offset B48h ...... 154 2.4.37 Clear for Destination Transaction Interrupts (ClearDstTran)—Offset B50h..... 155 2.4.38 Clear for Error Interrupts (ClearErr)—Offset B58h ...... 155 2.4.39 Combined Status register (StatusInt)—Offset B60h ...... 156 2.4.40 DMA Configuration (DmaCfgReg)—Offset B98h ...... 156 2.4.41 DMA Channel Enable (ChEnReg)—Offset BA0h ...... 157 3 EMMC Interface (D30:F4)...... 159 3.1 EMMC PCI Configuration Registers Summary ...... 159 3.1.1 Device & Vendor ID (VID_DID)—Offset 0h ...... 159 3.1.2 PCI Status & Command (STATUSCOMMAND)—Offset 4h...... 160 3.1.3 Rev ID & Class Code (REVCLASSCODE)—Offset 8h ...... 161 3.1.4 Carche Line & Latency & Header Type & BIST (CLLATHEADERBIST)—Offset Ch ...... 161 3.1.5 Base Address Low (BAR0)—Offset 10h...... 162 3.1.6 Base Address Register high (BAR0_HIGH)—Offset 14h...... 163 3.1.7 Base Address Register1 (BAR1)—Offset 18h ...... 163 3.1.8 (BAR1_HIGH)—Offset 1Ch ...... 164 3.1.9 Subsystem Vendor ID (SUBSYSTEMID)—Offset 2Ch ...... 165 3.1.10 (EXPANSION_ROM_BASEADDR)—Offset 30h ...... 165 3.1.11 Capabilities Pointer (CAPABILITYPTR)—Offset 34h ...... 166 3.1.12 (INTERRUPTREG)—Offset 3Ch ...... 166 3.1.13 Power Management Capability ID Register (POWERCAPID)—Offset 80h ...... 167 3.1.14 Power Management Control and Status Register (PMECTRLSTATUS)—Offset 84h...... 168 3.1.15 General Purpose PCI RW Register1 (GEN_REGRW1)—Offset B0h ...... 169 3.1.16 General Purpose PCI RW Register2 (GEN_REGRW2)—Offset B4h ...... 169 3.1.17 General Purpose PCI RW Register3 (GEN_REGRW3)—Offset B8h ...... 170 3.1.18 General Purpose PCI RW Register4 (GEN_REGRW4)—Offset BCh ...... 170 3.1.19 General Input Register (GEN_INPUT_REG)—Offset C0h...... 171 3.2 EMMC Memory Mapped Registers Summary...... 171 3.2.1 SDMA System Address Register/Argument2 Register (sdmasysaddr)—Offset 0h ...... 173 3.2.2 Block Size Register (blocksize)—Offset 4h ...... 173 3.2.3 Block Count Register (blockcount)—Offset 6h ...... 174 3.2.4 Argument1 Register (argument1)—Offset 8h ...... 175 3.2.5 Transfer Mode Register (transfermode)—Offset Ch ...... 175

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3.2.6 Command Register (command)—Offset Eh...... 176 3.2.7 Response Register (Reponse 0)—Offset 10h...... 177 3.2.8 Buffer Data Port Register (dataport)—Offset 20h ...... 178 3.2.9 Present State Register (presentstate)—Offset 24h ...... 178 3.2.10 Host Control 1 Register (hostcontrol1)—Offset 28h ...... 181 3.2.11 Power Control Register (powercontrol)—Offset 29h ...... 182 3.2.12 Block Gap Control Register (blockgapcontrol)—Offset 2Ah...... 183 3.2.13 Wakeup Control Register (wakeupcontrol)—Offset 2Bh ...... 184 3.2.14 Clock Control Register (clockcontrol)—Offset 2Ch ...... 185 3.2.15 Timeout Control Register (timeoutcontrol)—Offset 2Eh ...... 186 3.2.16 Software Reset Register (softwarereset)—Offset 2Fh...... 187 3.2.17 Normal Interrupt Status Register (normalintrsts)—Offset 30h...... 188 3.2.18 Error Interrupt Status Register (errorintrsts)—Offset 32h...... 190 3.2.19 Normal Interrupt Status Enable Register (normalintrstsena)—Offset 34h...... 191 3.2.20 Error Interrupt Status Enable Register (errorintrstsena)—Offset 36h ...... 193 3.2.21 Normal Interrupt Signal Enable Register (normalintrsigena)—Offset 38h ...... 194 3.2.22 Error Interrupt Signal Enable Register (errorintrsigena)—Offset 3Ah...... 195 3.2.23 Auto CMD12 Error Status Register (autocmderrsts)—Offset 3Ch ...... 196 3.2.24 Host Control2 Register (hostcontrol2)—Offset 3Eh ...... 197 3.2.25 Capabilities Register (capabilities)—Offset 40h ...... 199 3.2.26 Maximum Current Capabilities Register (maxcurrentcap)—Offset 48h ...... 202 3.2.27 Force Event REGISTER for AUTO CMD Error Status (ForceEventforAUTOCMDErrorStatus)—Offset 50h...... 203 3.2.28 Force Event Register for Error Interrupt Status (forceeventforerrintsts)—Offset 52h...... 204 3.2.29 ADMA Error Status Register (admaerrsts)—Offset 54h...... 205 3.2.30 ADMA System Address Register0&1 (admasysaddr01)—Offset 58h...... 206 3.2.31 ADMA System Address Register1 (admasysaddr2)—Offset 5Ch...... 207 3.2.32 ADMA System Address Register1 (admasysaddr3)—Offset 5Eh ...... 207 3.2.33 Preset Value Register for Initialization (Preset Value 0)—Offset 60h ...... 208 3.2.34 Preset Value Register for Default Speed (Preset Value 1)—Offset 62h ...... 209 3.2.35 Preset Value Register for High Speed (Preset Value 2)—Offset 64h...... 209 3.2.36 Preset Value Register for SDR12 (Preset Value 3)—Offset 66h ...... 209 3.2.37 Preset Value Register for SDR25 (Preset Value 4)—Offset 68h ...... 209 3.2.38 Preset Value Register for SDR50 (Preset Value 5)—Offset 6Ah ...... 209 3.2.39 Preset Value Register for SDR104 (Preset Value 6)—Offset 6Ch ...... 209 3.2.40 Preset Value Register for DDR50 (Preset Value 7)—Offset 6Eh...... 209 3.2.41 Boot Timeout Control Register (boottimeoutcnt)—Offset 70h ...... 210 3.2.42 Slot Interrupt Status Register (slotintrsts)—Offset FCh ...... 210 3.2.43 Host Controller Version Register (hostcontrollerver)—Offset FEh ...... 211 3.3 EMMC Additional Registers Summary ...... 211 3.3.1 Software LTR Value (SW_LTR_val)—Offset 804h...... 212 3.3.2 Auto LTR Value (Auto_LTR_val)—Offset 808h...... 213 3.3.3 Capabilities Bypass (Cap_byps)—Offset 810h ...... 214 3.3.4 Capabilities Bypass 1 (Cap_byps_reg1)—Offset 814h ...... 214 3.3.5 Capabilities Bypass 2 (Cap_byps_reg2)—Offset 818h ...... 215 3.3.6 (reg_D0i3)—Offset 81Ch ...... 216 3.3.7 (Tx_CMD_dly)—Offset 820h...... 217 3.3.8 (Tx_DATA_dly_1)—Offset 824h ...... 218 3.3.9 (Tx_DATA_dly_2)—Offset 828h ...... 218 3.3.10 (Rx_CMD_Data_dly_1)—Offset 82Ch...... 219 3.3.11 (Rx_Strobe_Ctrl_Path)—Offset 830h ...... 220 3.3.12 (Rx_CMD_Data_dly_2)—Offset 834h...... 221 3.3.13 (Master_Dll)—Offset 838h ...... 222 3.3.14 (Auto_tuning)—Offset 840h ...... 222

332219-002 7 4 SDXC (D30:F6)...... 225 4.1 SDXC PCI Configuration Registers Summary...... 225 4.1.1 Device & Vendor ID (DEVVENDID)—Offset 0h ...... 225 4.1.2 PCI Status & Command (STATUSCOMMAND)—Offset 4h...... 226 4.1.3 Rev ID & Class Code (REVCLASSCODE)—Offset 8h ...... 227 4.1.4 Carche Line & Latency & Header Type & BIST (CLLATHEADERBIST)—Offset Ch ...... 228 4.1.5 Base Address Low (BAR0)—Offset 10h...... 228 4.1.6 Base Address Register high (BAR0_HIGH)—Offset 14h...... 229 4.1.7 Base Address Register1 (BAR1)—Offset 18h ...... 230 4.1.8 (BAR1_HIGH)—Offset 1Ch ...... 230 4.1.9 Subsystem Vendor ID (SUBSYSTEMID)—Offset 2Ch ...... 231 4.1.10 (EXPANSION_ROM_BASEADDR)—Offset 30h ...... 231 4.1.11 Capabilities Pointer (CAPABILITYPTR)—Offset 34h ...... 232 4.1.12 (INTERRUPTREG)—Offset 3Ch ...... 233 4.1.13 Power Management Capability ID Register (POWERCAPID)—Offset 80h ...... 233 4.1.14 Power Management Control and Status Register (PMECTRLSTATUS)—Offset 84h...... 234 4.1.15 General Purpose PCI RW Register1 (GEN_REGRW1)—Offset B0h ...... 235 4.1.16 General Purpose PCI RW Register2 (GEN_REGRW2)—Offset B4h ...... 235 4.1.17 General Purpose PCI RW Register3 (GEN_REGRW3)—Offset B8h ...... 236 4.1.18 General Purpose PCI RW Register4 (GEN_REGRW4)—Offset BCh ...... 236 4.1.19 General Input Register (GEN_INPUT_REG)—Offset C0h...... 237 4.2 SDXC Memory Mapped Registers Summary ...... 237 4.2.1 SDMA System Address Register/Argument2 Register (sdmasysaddr)—Offset 0h ...... 239 4.2.2 Block Size Register (blocksize)—Offset 4h ...... 239 4.2.3 Block Count Register (blockcount)—Offset 6h ...... 240 4.2.4 Argument1 Register (argument1)—Offset 8h ...... 241 4.2.5 Transfer Mode Register (transfermode)—Offset Ch ...... 242 4.2.6 Command Register (command)—Offset Eh ...... 242 4.2.7 Response Register (Reponse 0)—Offset 10h ...... 244 4.2.8 Buffer Data Port Register (dataport)—Offset 20h...... 244 4.2.9 Present State Register (presentstate)—Offset 24h...... 245 4.2.10 Host Control1 Register (hostcontrol1)—Offset 28h...... 248 4.2.11 PowerControl Register (powercontrol)—Offset 29h ...... 249 4.2.12 Block Gap Control Register (blockgapcontrol)—Offset 2Ah ...... 250 4.2.13 Wakeup Control Register (wakeupcontrol)—Offset 2Bh...... 251 4.2.14 Clock Control Register (clockcontrol)—Offset 2Ch ...... 252 4.2.15 Timeout Control Register (timeoutcontrol)—Offset 2Eh ...... 253 4.2.16 Software Reset Register (softwarereset)—Offset 2Fh ...... 254 4.2.17 Normal Interrupt Status Register (normalintrsts)—Offset 30h ...... 255 4.2.18 Error Interrupt Status (errorintrsts)—Offset 32h ...... 257 4.2.19 Normal Interrupt Status Enable Register (normalintrstsena)—Offset 34h ...... 258 4.2.20 Error Interrupt Status Enable Register (errorintrstsena)—Offset 36h...... 259 4.2.21 Normal Interrupt Signal Enable Register (normalintrsigena)—Offset 38h ...... 261 4.2.22 Error Interrupt Signal Enable Register (errorintrsigena)—Offset 3Ah ...... 262 4.2.23 Auto CMD12 Error Status Register (autocmderrsts)—Offset 3Ch...... 263 4.2.24 Host Control 2 Register (hostcontrol2)—Offset 3Eh...... 264 4.2.25 Capabilities Register (capabilities)—Offset 40h...... 266 4.2.26 Maximum Current Capabilities Register (maxcurrentcap)—Offset 48h ...... 268 4.2.27 Force Event REGISTER for AUTO CMD Error Status (ForceEventforAUTOCMDErrorStatus)—Offset 50h ...... 269 4.2.28 Force Event Register for Error Interrupt Status (forceeventforerrintsts)—Offset 52h ...... 270

8 332219-002

4.2.29 ADMA Error Status Register (admaerrsts)—Offset 54h...... 271 4.2.30 ADMA System Address Register0&1 (admasysaddr01)—Offset 58h...... 272 4.2.31 ADMA System Address Register1 (admasysaddr2)—Offset 5Ch...... 273 4.2.32 ADMA System Address Register1 (admasysaddr3)—Offset 5Eh ...... 273 4.2.33 Preset Value Register for Initialization (Preset Value 0)—Offset 60h ...... 274 4.2.34 Preset Value Register for Default Speed (Preset Value 1)—Offset 62h ...... 275 4.2.35 Preset Value Register for High Speed (presetvalue2)—Offset 64h...... 275 4.2.36 Preset Value Register for SDR12 (presetvalue3)—Offset 66h ...... 275 4.2.37 Preset Value Register for SDR25 (presetvalue4)—Offset 68h ...... 275 4.2.38 Preset Value Register for SDR50 (presetvalue5)—Offset 6Ah ...... 275 4.2.39 Preset Value Register for SDR104 (presetvalue6)—Offset 6Ch ...... 275 4.2.40 Preset Value Register for DDR50 (presetvalue7)—Offset 6Eh ...... 275 4.2.41 Slot Interrupt Status Register (slotintrsts)—Offset FCh ...... 275 4.2.42 Host Controller Version Register (hostcontrollerver)—Offset FEh ...... 276 4.3 SDXC Additional Registers Summary...... 277 4.3.1 Software LTR Value (SW_LTR_val)—Offset 804h...... 277 4.3.2 Auto LTR Value (Auto_LTR_val)—Offset 808h...... 278 4.3.3 (Cap_byps)—Offset 810h ...... 279 4.3.4 (Cap_byps_reg1)—Offset 814h ...... 279 4.3.5 (Cap_byps_reg2)—Offset 818h ...... 280 4.3.6 (reg_D0i3)—Offset 81Ch ...... 281 4.3.7 (Tx_CMD_dly)—Offset 820h...... 282 4.3.8 (Tx_DATA_dly_1)—Offset 824h ...... 283 4.3.9 (Tx_DATA_dly_2)—Offset 828h ...... 283 4.3.10 (Rx_CMD_Data_dly_1)—Offset 82Ch...... 284 4.3.11 (Rx_Strobe_Ctrl_Path)—Offset 830h ...... 285 4.3.12 (Rx_CMD_Data_dly_2)—Offset 834h...... 286 4.3.13 (Master_Dll)—Offset 838h ...... 286 4.3.14 (Auto_tuning)—Offset 840h ...... 287 5 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3) ...... 289 5.1 I2C PCI Configuration Registers Summary ...... 289 5.1.1 Device ID and Vendor ID Register (DEVVENDID)—Offset 0h...... 289 5.1.2 Status and Command (STATUSCOMMAND)—Offset 4h...... 290 5.1.3 Revision ID and Class Code (REVCLASSCODE)—Offset 8h ...... 291 5.1.4 Cache Line Latency Header and BIST (CLLATHEADERBIST)—Offset Ch ...... 292 5.1.5 Base Address Register (BAR)—Offset 10h ...... 292 5.1.6 Base Address Register High (BAR_HIGH)—Offset 14h...... 293 5.1.7 Base Address Register 1 (BAR1)—Offset 18h...... 294 5.1.8 Base Address Register1 High (BAR1_HIGH)—Offset 1Ch ...... 294 5.1.9 Subsystem Vendor and Subsystem ID (SUBSYSTEMID)—Offset 2Ch...... 295 5.1.10 Expansion ROM Base Address (EXPANSION_ROM_BASEADDR)—Offset 30h .. 295 5.1.11 Capabilities Pointer (CAPABILITYPTR)—Offset 34h...... 296 5.1.12 Interrupt Register (INTERRUPTREG)—Offset 3Ch ...... 296 5.1.13 PowerManagement Capability ID (POWERCAPID)—Offset 80h...... 297 5.1.14 PME Control and Status (PMECTRLSTATUS)—Offset 84h ...... 298 5.1.15 PCI Device Idle Capability Record (PCIDEVIDLE_CAP_RECORD)—Offset 90h. 298 5.1.16 SW LTR Update MMIO Location Register (D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h ...... 299 5.1.17 Device IDLE pointer register (DEVICE_IDLE_POINTER_REG)—Offset 9Ch ..... 300 5.1.18 Device PG Config (D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h...... 300 5.2 I2C Memory Mapped Registers Summary...... 301 5.2.1 I2C Control (IC_CON)—Offset 0h...... 302 5.2.2 I2C Target Address (IC_TAR)—Offset 4h ...... 304 5.2.3 I2C High Speed Master Mode Code Address (IC_HS_MADDR)—Offset Ch ..... 304

332219-002 9 5.2.4 I2C Rx/Tx Data Buffer and Command (IC_DATA_CMD)—Offset 10h...... 305 5.2.5 Standard Speed I2C Clock SCL High Count (IC_SS_SCL_HCNT)—Offset 14h . 306 5.2.6 Standard Speed I2C Clock SCL Low Count (IC_SS_SCL_LCNT)—Offset 18h .. 307 5.2.7 Fast Speed I2C Clock SCL High Count (IC_FS_SCL_HCNT)—Offset 1Ch ...... 307 5.2.8 Fast Speed I2C Clock SCL Low Count (IC_FS_SCL_LCNT)—Offset 20h...... 308 5.2.9 I2C Interrupt Status (IC_INTR_STAT)—Offset 2Ch ...... 309 5.2.10 I2C Interrupt Mask (IC_INTR_MASK)—Offset 30h ...... 310 5.2.11 I2C Raw Interrupt Status (IC_RAW_INTR_STAT)—Offset 34h ...... 311 5.2.12 I2C Receive FIFO Threshold (IC_RX_TL)—Offset 38h ...... 312 5.2.13 I2C Transmit FIFO Threshold (IC_TX_TL)—Offset 3Ch...... 313 5.2.14 Clear Combined and Individual Interrupt (IC_CLR_INTR)—Offset 40h ...... 313 5.2.15 Clear RX_UNDER Interrupt (IC_CLR_RX_UNDER)—Offset 44h ...... 314 5.2.16 Clear RX_OVER Interrupt (IC_CLR_RX_OVER)—Offset 48h ...... 314 5.2.17 Clear TX_OVER Interrupt (IC_CLR_TX_OVER)—Offset 4Ch ...... 315 5.2.18 Clear RD_REQ Interrupt (IC_CLR_RD_REQ)—Offset 50h ...... 315 5.2.19 Clear TX_ABRT Interrupt (IC_CLR_TX_ABRT)—Offset 54h ...... 316 5.2.20 Clear RX_DONE Interrupt (IC_CLR_RX_DONE)—Offset 58h ...... 316 5.2.21 Clear ACTIVITY Interrupt (IC_CLR_ACTIVITY)—Offset 5Ch ...... 317 5.2.22 Clear STOP_DET Interrupt (IC_CLR_STOP_DET)—Offset 60h ...... 317 5.2.23 Clear START_DET Interrupt (IC_CLR_START_DET)—Offset 64h ...... 318 5.2.24 Clear GEN_CALL Interrupt (IC_CLR_GEN_CALL)—Offset 68h...... 318 5.2.25 I2C Enable (IC_ENABLE)—Offset 6Ch ...... 319 5.2.26 I2C Status (IC_STATUS)—Offset 70h...... 320 5.2.27 I2C Transmit FIFO Level (IC_TXFLR)—Offset 74h ...... 321 5.2.28 I2C Receive FIFO Level (IC_RXFLR)—Offset 78h ...... 321 5.2.29 I2C SDA Hold Time Length (IC_SDA_HOLD)—Offset 7Ch...... 322 5.2.30 I2C Transmit Abort Source (IC_TX_ABRT_SOURCE)—Offset 80h ...... 322 5.2.31 DMA Control (IC_DMA_CR)—Offset 88h ...... 324 5.2.32 DMA Transmit Data Level (IC_DMA_TDLR)—Offset 8Ch...... 325 5.2.33 I2C Receive Data Level (IC_DMA_RDLR)—Offset 90h...... 325 5.2.34 I2C ACK General Call (IC_ACK_GENERAL_CALL)—Offset 98h ...... 326 5.2.35 I2C Enable Status (IC_ENABLE_STATUS)—Offset 9Ch...... 326 5.2.36 I2C SS and FS Spike Suppression Limit (IC_FS_SPKLEN)—Offset A0h ...... 327 5.2.37 Clear RESTART_DET Interrupt (IC_CLR_RESTRART_DET)—Offset A8h...... 328 5.3 I2C Additional Registers Summary ...... 328 5.3.1 Soft Reset (RESETS)—Offset 204h ...... 329 5.3.2 Active LTR (ACTIVELTR_VALUE)—Offset 210h...... 329 5.3.3 Idle LTR (IDLELTR_VALUE)—Offset 214h...... 330 5.3.4 TX Ack Count (TX_ACK_COUNT)—Offset 218h ...... 331 5.3.5 RX ACK Count (RX_BYTE_COUNT)—Offset 21Ch ...... 332 5.3.6 Interrupt Status for Tx Complete (TX_COMPLETE_INTR_STAT)—Offset 220h 333 5.3.7 Tx Complete Interrupt Clear (TX_COMPLETE_INTR_CLR)—Offset 224h...... 333 5.3.8 SW Scratch Register 0 (SW_SCRATCH_0)—Offset 228h ...... 334 5.3.9 SW Scratch Register 1 (SW_SCRATCH_1)—Offset 22Ch ...... 334 5.3.10 SW Scratch Register 2 (SW_SCRATCH_2)—Offset 230h ...... 335 5.3.11 SW Scratch Register 3 (SW_SCRATCH_3)—Offset 234h ...... 335 5.3.12 Clock Gate (CLOCK_GATE)—Offset 238h ...... 336 5.3.13 Remap Address Low (REMAP_ADDR_LO)—Offset 240h...... 336 5.3.14 Remap Address High (REMAP_ADDR_HI)—Offset 244h ...... 337 5.3.15 Capabilities (CAPABLITIES)—Offset 2FCh ...... 337 5.4 I2C DMA Controller Registers Summary ...... 338 5.4.1 DMA Transfer Source Address Low (SAR_LO0)—Offset 800h ...... 339 5.4.2 DMA Transfer Source Address High (SAR_HI0)—Offset 804h...... 340 5.4.3 DMA Transfer Destination Address Low (DAR_LO0)—Offset 808h...... 341 5.4.4 DMA Transfer Destination Address High (DAR_HI0)—Offset 80Ch ...... 342

10 332219-002

5.4.5 Linked List Pointer Low (LLP_LO0)—Offset 810h ...... 343 5.4.6 Linked List Pointer High (LLP_HI0)—Offset 814h...... 344 5.4.7 Control Register Low (CTL_LO0)—Offset 818h ...... 344 5.4.8 Control Register High (CTL_HI0)—Offset 81Ch ...... 346 5.4.9 Source Status (SSTAT0)—Offset 820h...... 347 5.4.10 Destination Status (DSTAT0)—Offset 828h ...... 348 5.4.11 Source Status Address Low (SSTATAR_LO0)—Offset 830h ...... 348 5.4.12 Source Status Address High (SSTATAR_HI0)—Offset 834h...... 349 5.4.13 Destination Status Address Low (DSTATAR_LO0)—Offset 838h...... 350 5.4.14 Destination Status Address High (DSTATAR_HI0)—Offset 83Ch ...... 350 5.4.15 DMA Transfer Configuration Low (CFG_LO0)—Offset 840h ...... 351 5.4.16 DMA Transfer Configuration High (CFG_HI0)—Offset 844h ...... 352 5.4.17 Source Gather (SGR0)—Offset 848h ...... 353 5.4.18 Destination Scatter (DSR0)—Offset 850h...... 354 5.4.19 Raw Interrupt Status (RawTfr)—Offset AC0h...... 355 5.4.20 Raw Status for Block Interrupts (RawBlock)—Offset AC8h...... 355 5.4.21 Raw Status for Source Transaction Interrupts (RawSrcTran)—Offset AD0h ... 356 5.4.22 Raw Status for Destination Transaction Interrupts (RawDstTran)—Offset AD8h...... 356 5.4.23 Raw Status for Error Interrupts (RawErr)—Offset AE0h...... 357 5.4.24 Interrupt Status (StatusTfr)—Offset AE8h...... 358 5.4.25 Status for Block Interrupts (StatusBlock)—Offset AF0h ...... 358 5.4.26 Status for Source Transaction Interrupts (StatusSrcTran)—Offset AF8h ...... 359 5.4.27 Status for Destination Transaction Interrupts (StatusDstTran)—Offset B00h . 359 5.4.28 Status for Error Interrupts (StatusErr)—Offset B08h ...... 360 5.4.29 Mask for Transfer Interrupts (MaskTfr)—Offset B10h...... 360 5.4.30 Mask for Block Interrupts (MaskBlock)—Offset B18h ...... 361 5.4.31 Mask for Source Transaction Interrupts (MaskSrcTran)—Offset B20h...... 362 5.4.32 Mask for Destination Transaction Interrupts (MaskDstTran)—Offset B28h..... 362 5.4.33 Mask for Error Interrupts (MaskErr)—Offset B30h ...... 363 5.4.34 Clear for Transfer Interrupts (ClearTfr)—Offset B38h...... 364 5.4.35 Clear for Block Interrupts (ClearBlock)—Offset B40h ...... 364 5.4.36 Clear for Source Transaction Interrupts (ClearSrcTran)—Offset B48h...... 365 5.4.37 Clear for Destination Transaction Interrupts (ClearDstTran)—Offset B50h .... 365 5.4.38 Clear for Error Interrupts (ClearErr)—Offset B58h ...... 365 5.4.39 Combined Status register (StatusInt)—Offset B60h...... 366 5.4.40 DMA Configuration (DmaCfgReg)—Offset B98h...... 367 5.4.41 DMA Channel Enable (ChEnReg)—Offset BA0h...... 367 6 GPIO for SKL PCH-H ...... 369 6.1 GPIO Community 0 Registers Summary...... 369 6.1.1 Family Base Address (FAMBAR)—Offset 8h ...... 374 6.1.2 Pad Base Address (PADBAR)—Offset Ch ...... 375 6.1.3 Miscellaneous Configuration (MISCCFG)—Offset 10h ...... 375 6.1.4 Pad Ownership (PAD_OWN_GPP_A_0)—Offset 20h ...... 376 6.1.5 Pad Ownership (PAD_OWN_GPP_A_1)—Offset 24h ...... 378 6.1.6 Pad Ownership (PAD_OWN_GPP_A_2)—Offset 28h ...... 378 6.1.7 Pad Ownership (PAD_OWN_GPP_B_0)—Offset 30h ...... 378 6.1.8 Pad Ownership (PAD_OWN_GPP_B_1)—Offset 34h ...... 378 6.1.9 Pad Ownership (PAD_OWN_GPP_B_2)—Offset 38h ...... 378 6.1.10 Pad Configuration Lock (PADCFGLOCK_GPP_A)—Offset A0h ...... 378 6.1.11 Pad Configuration Lock (PADCFGLOCKTX_GPP_A)—Offset A4h...... 380 6.1.12 Pad Configuration Lock (PADCFGLOCK_GPP_B)—Offset A8h ...... 382 6.1.13 Pad Configuration Lock (PADCFGLOCKTX_GPP_B)—Offset ACh ...... 382 6.1.14 Host Software Pad Ownership (HOSTSW_OWN_GPP_A)—Offset D0h ...... 382

332219-002 11 6.1.15 Host Software Pad Ownership (HOSTSW_OWN_GPP_B)—Offset D4h...... 383 6.1.16 GPI Interrupt Status (GPI_IS_GPP_A)—Offset 100h...... 383 6.1.17 GPI Interrupt Status (GPI_IS_GPP_B)—Offset 104h...... 385 6.1.18 GPI Interrupt Enable (GPI_IE_GPP_A)—Offset 120h ...... 385 6.1.19 GPI Interrupt Enable (GPI_IE_GPP_B)—Offset 124h ...... 387 6.1.20 GPI General Purpose Events Status (GPI_GPE_STS_GPP_A)—Offset 140h .... 387 6.1.21 GPI General Purpose Events Status (GPI_GPE_STS_GPP_B)—Offset 144h .... 389 6.1.22 GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A)—Offset 160h...... 389 6.1.23 GPI General Purpose Events Enable (GPI_GPE_EN_GPP_B)—Offset 164h...... 391 6.1.24 SMI Status (GPI_SMI_STS_GPP_B)—Offset 184h ...... 391 6.1.25 SMI Enable (GPI_SMI_EN_GPP_B)—Offset 1A4h ...... 392 6.1.26 NMI Status (GPI_NMI_STS_GPP_B)—Offset 1C4h...... 393 6.1.27 NMI Enable (GPI_NMI_EN_GPP_B)—Offset 1E4h ...... 394 6.1.28 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_0)—Offset 400h...... 395 6.1.29 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_0)—Offset 404h...... 397 6.1.30 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_1)—Offset 408h...... 398 6.1.31 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_1)—Offset 40Ch ...... 398 6.1.32 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_2)—Offset 410h...... 398 6.1.33 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_2)—Offset 414h...... 398 6.1.34 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_3)—Offset 418h...... 399 6.1.35 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_3)—Offset 41Ch ...... 399 6.1.36 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_4)—Offset 420h...... 399 6.1.37 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_4)—Offset 424h...... 399 6.1.38 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_5)—Offset 428h...... 399 6.1.39 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_5)—Offset 42Ch ...... 399 6.1.40 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_6)—Offset 430h...... 399 6.1.41 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_6)—Offset 434h...... 399 6.1.42 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_7)—Offset 438h...... 400 6.1.43 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_7)—Offset 43Ch ...... 400 6.1.44 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_8)—Offset 440h...... 400 6.1.45 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_8)—Offset 444h...... 400 6.1.46 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_9)—Offset 448h...... 400 6.1.47 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_9)—Offset 44Ch ...... 400 6.1.48 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_10)—Offset 450h...... 400 6.1.49 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_10)—Offset 454h...... 400 6.1.50 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_11)—Offset 458h...... 401 6.1.51 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_11)—Offset 45Ch...... 401 6.1.52 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_12)—Offset 460h...... 401 6.1.53 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_12)—Offset 464h...... 401 6.1.54 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_13)—Offset 468h...... 401 6.1.55 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_13)—Offset 46Ch...... 401 6.1.56 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_14)—Offset 470h...... 401 6.1.57 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_14)—Offset 474h...... 401 6.1.58 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_15)—Offset 478h...... 402 6.1.59 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_15)—Offset 47Ch...... 402 6.1.60 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_16)—Offset 480h...... 402 6.1.61 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_16)—Offset 484h...... 402 6.1.62 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_17)—Offset 488h...... 402 6.1.63 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_17)—Offset 48Ch...... 402 6.1.64 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_18)—Offset 490h...... 402 6.1.65 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_18)—Offset 494h...... 402 6.1.66 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_19)—Offset 498h...... 403 6.1.67 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_19)—Offset 49Ch...... 403 6.1.68 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_20)—Offset 4A0h...... 403 6.1.69 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_20)—Offset 4A4h...... 403

12 332219-002

6.1.70 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_21)—Offset 4A8h ...... 403 6.1.71 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_21)—Offset 4ACh ...... 403 6.1.72 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_22)—Offset 4B0h ...... 403 6.1.73 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_22)—Offset 4B4h ...... 403 6.1.74 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_23)—Offset 4B8h ...... 404 6.1.75 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_23)—Offset 4BCh ...... 404 6.1.76 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_0)—Offset 4C0h ...... 404 6.1.77 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_0)—Offset 4C4h ...... 404 6.1.78 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_1)—Offset 4C8h ...... 404 6.1.79 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_1)—Offset 4CCh...... 404 6.1.80 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_2)—Offset 4D0h...... 404 6.1.81 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_2)—Offset 4D4h...... 404 6.1.82 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_3)—Offset 4D8h...... 405 6.1.83 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_3)—Offset 4DCh...... 405 6.1.84 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_4)—Offset 4E0h ...... 405 6.1.85 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_4)—Offset 4E4h ...... 405 6.1.86 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_5)—Offset 4E8h ...... 405 6.1.87 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_5)—Offset 4ECh ...... 405 6.1.88 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_6)—Offset 4F0h ...... 405 6.1.89 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_6)—Offset 4F4h ...... 405 6.1.90 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_7)—Offset 4F8h ...... 406 6.1.91 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_7)—Offset 4FCh ...... 406 6.1.92 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_8)—Offset 500h ...... 406 6.1.93 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_8)—Offset 504h ...... 406 6.1.94 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_9)—Offset 508h ...... 406 6.1.95 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_9)—Offset 50Ch ...... 406 6.1.96 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_10)—Offset 510h ...... 406 6.1.97 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_10)—Offset 514h ...... 406 6.1.98 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_11)—Offset 518h ...... 407 6.1.99 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_11)—Offset 51Ch ...... 407 6.1.100Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_12)—Offset 520h ...... 407 6.1.101Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_12)—Offset 524h ...... 407 6.1.102Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_13)—Offset 528h ...... 407 6.1.103Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_13)—Offset 52Ch ...... 407 6.1.104Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_14)—Offset 530h ...... 407 6.1.105Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_14)—Offset 534h ...... 407 6.1.106Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_15)—Offset 538h ...... 408 6.1.107Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_15)—Offset 53Ch ...... 408 6.1.108Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_16)—Offset 540h ...... 408 6.1.109Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_16)—Offset 544h ...... 408 6.1.110Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_17)—Offset 548h ...... 408 6.1.111Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_17)—Offset 54Ch ...... 408 6.1.112Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_18)—Offset 550h ...... 408 6.1.113Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_18)—Offset 554h ...... 408 6.1.114Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_19)—Offset 558h ...... 409 6.1.115Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_19)—Offset 55Ch ...... 409 6.1.116Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_20)—Offset 560h ...... 409 6.1.117Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_20)—Offset 564h ...... 409 6.1.118Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_21)—Offset 568h ...... 409 6.1.119Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_21)—Offset 56Ch ...... 409 6.1.120Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_22)—Offset 570h ...... 409 6.1.121Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_22)—Offset 574h ...... 409 6.1.122Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_23)—Offset 578h ...... 410 6.1.123Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_23)—Offset 57Ch ...... 410 6.2 GPIO Community 1 Registers Summary...... 410

332219-002 13 6.2.1 Family Base Address (FAMBAR)—Offset 8h ...... 419 6.2.2 Pad Base Address (PADBAR)—Offset Ch...... 420 6.2.3 Miscellaneous Configuration (MISCCFG)—Offset 10h...... 420 6.2.4 Pad Ownership (PAD_OWN_GPP_C_0)—Offset 20h...... 421 6.2.5 Pad Ownership (PAD_OWN_GPP_C_1)—Offset 24h...... 423 6.2.6 Pad Ownership (PAD_OWN_GPP_C_2)—Offset 28h...... 423 6.2.7 Pad Ownership (PAD_OWN_GPP_D_0)—Offset 2Ch ...... 423 6.2.8 Pad Ownership (PAD_OWN_GPP_D_1)—Offset 30h...... 423 6.2.9 Pad Ownership (PAD_OWN_GPP_D_2)—Offset 34h...... 423 6.2.10 Pad Ownership (PAD_OWN_GPP_E_0)—Offset 38h ...... 423 6.2.11 Pad Ownership (PAD_OWN_GPP_E_1)—Offset 3Ch...... 423 6.2.12 Pad Ownership (PAD_OWN_GPP_F_0)—Offset 40h ...... 423 6.2.13 Pad Ownership (PAD_OWN_GPP_F_1)—Offset 44h ...... 423 6.2.14 Pad Ownership (PAD_OWN_GPP_F_2)—Offset 48h ...... 423 6.2.15 Pad Ownership (PAD_OWN_GPP_G_0)—Offset 4Ch ...... 423 6.2.16 Pad Ownership (PAD_OWN_GPP_G_1)—Offset 50h...... 423 6.2.17 Pad Ownership (PAD_OWN_GPP_G_2)—Offset 54h...... 423 6.2.18 Pad Ownership (PAD_OWN_GPP_H_0)—Offset 58h...... 424 6.2.19 Pad Ownership (PAD_OWN_GPP_H_1)—Offset 5Ch...... 424 6.2.20 Pad Ownership (PAD_OWN_GPP_H_2)—Offset 60h...... 424 6.2.21 Pad Configuration Lock (PADCFGLOCK_GPP_C_0)—Offset 90h ...... 424 6.2.22 Pad Configuration Lock (PADCFGLOCKTX_GPP_C_0)—Offset 94h...... 425 6.2.23 Pad Configuration Lock (PADCFGLOCK_GPP_D_0)—Offset 98h ...... 427 6.2.24 Pad Configuration Lock (PADCFGLOCKTX_GPP_D_0)—Offset 9Ch ...... 427 6.2.25 Pad Configuration Lock (PADCFGLOCK_GPP_E_0)—Offset A0h ...... 427 6.2.26 Pad Configuration Lock (PADCFGLOCKTX_GPP_E_0)—Offset A4h...... 427 6.2.27 Pad Configuration Lock (PADCFGLOCK_GPP_F_0)—Offset A8h ...... 428 6.2.28 Pad Configuration Lock (PADCFGLOCKTX_GPP_F_0)—Offset ACh...... 428 6.2.29 Pad Configuration Lock (PADCFGLOCK_GPP_G_0)—Offset B0h...... 428 6.2.30 Pad Configuration Lock (PADCFGLOCKTX_GPP_G_0)—Offset B4h ...... 428 6.2.31 Pad Configuration Lock (PADCFGLOCK_GPP_H_0)—Offset B8h ...... 428 6.2.32 Pad Configuration Lock (PADCFGLOCKTX_GPP_H_0)—Offset BCh ...... 428 6.2.33 Host Software Pad Ownership (HOSTSW_OWN_GPP_C_0)—Offset D0h ...... 428 6.2.34 Host Software Pad Ownership (HOSTSW_OWN_GPP_D_0)—Offset D4h ...... 430 6.2.35 Host Software Pad Ownership (HOSTSW_OWN_GPP_E_0)—Offset D8h ...... 430 6.2.36 Host Software Pad Ownership (HOSTSW_OWN_GPP_F_0)—Offset DCh ...... 430 6.2.37 Host Software Pad Ownership (HOSTSW_OWN_GPP_G_0)—Offset E0h ...... 430 6.2.38 Host Software Pad Ownership (HOSTSW_OWN_GPP_H_0)—Offset E4h ...... 430 6.2.39 GPI Interrupt Status (GPI_IS_GPP_C_0)—Offset 100h ...... 431 6.2.40 GPI Interrupt Status (GPI_IS_GPP_D_0)—Offset 104h...... 432 6.2.41 GPI Interrupt Status (GPI_IS_GPP_E_0)—Offset 108h ...... 432 6.2.42 GPI Interrupt Status (GPI_IS_GPP_F_0)—Offset 10Ch ...... 432 6.2.43 GPI Interrupt Status (GPI_IS_GPP_G_0)—Offset 110h...... 432 6.2.44 GPI Interrupt Status (GPI_IS_GPP_H_0)—Offset 114h ...... 433 6.2.45 GPI Interrupt Enable (GPI_IE_GPP_C_0)—Offset 120h...... 433 6.2.46 GPI Interrupt Enable (GPI_IE_GPP_D_0)—Offset 124h...... 434 6.2.47 GPI Interrupt Enable (GPI_IE_GPP_E_0)—Offset 128h ...... 434 6.2.48 GPI Interrupt Enable (GPI_IE_GPP_F_0)—Offset 12Ch ...... 434 6.2.49 GPI Interrupt Enable (GPI_IE_GPP_G_0)—Offset 130h...... 435 6.2.50 GPI Interrupt Enable (GPI_IE_GPP_H_0)—Offset 134h...... 435 6.2.51 GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_0)—Offset 140h . 435 6.2.52 GPI General Purpose Events Status (GPI_GPE_STS_GPP_D_0)—Offset 144h. 436 6.2.53 GPI General Purpose Events Status (GPI_GPE_STS_GPP_E_0)—Offset 148h . 437 6.2.54 GPI General Purpose Events Status (GPI_GPE_STS_GPP_F_0)—Offset 14Ch . 437 6.2.55 GPI General Purpose Events Status (GPI_GPE_STS_GPP_G_0)—Offset 150h. 437

14 332219-002

6.2.56 GPI General Purpose Events Status (GPI_GPE_STS_GPP_H_0)—Offset 154h 437 6.2.57 GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_0)—Offset 160h.. 437 6.2.58 GPI General Purpose Events Enable (GPI_GPE_EN_GPP_D_0)—Offset 164h.. 439 6.2.59 GPI General Purpose Events Enable (GPI_GPE_EN_GPP_E_0)—Offset 168h .. 439 6.2.60 GPI General Purpose Events Enable (GPI_GPE_EN_GPP_F_0)—Offset 16Ch .. 439 6.2.61 GPI General Purpose Events Enable (GPI_GPE_EN_GPP_G_0)—Offset 170h.. 439 6.2.62 GPI General Purpose Events Enable (GPI_GPE_EN_GPP_H_0)—Offset 174h.. 439 6.2.63 SMI Status (GPI_SMI_STS_GPP_C_0)—Offset 180h ...... 439 6.2.64 SMI Status (GPI_SMI_STS_GPP_D_0)—Offset 184h ...... 440 6.2.65 SMI Status (GPI_SMI_STS_GPP_E_0)—Offset 188h ...... 441 6.2.66 SMI Enable (GPI_SMI_EN_GPP_C_0)—Offset 1A0h ...... 442 6.2.67 SMI Enable (GPI_SMI_EN_GPP_D_0)—Offset 1A4h ...... 443 6.2.68 SMI Enable (GPI_SMI_EN_GPP_E_0)—Offset 1A8h ...... 444 6.2.69 NMI Status (GPI_NMI_STS_GPP_C_0)—Offset 1C0h...... 445 6.2.70 NMI Status (GPI_NMI_STS_GPP_D_0)—Offset 1C4h ...... 446 6.2.71 NMI Status (GPI_NMI_STS_GPP_E_0)—Offset 1C8h...... 447 6.2.72 NMI Enable (GPI_NMI_EN_GPP_C_0)—Offset 1E0h ...... 448 6.2.73 NMI Enable (GPI_NMI_EN_GPP_D_0)—Offset 1E4h ...... 449 6.2.74 NMI Enable (GPI_NMI_EN_GPP_E_0)—Offset 1E8h ...... 450 6.2.75 PWM Control (PWMC)—Offset 204h...... 451 6.2.76 GPIO Serial Blink Enable (GP_SER_BLINK)—Offset 20Ch...... 451 6.2.77 GPIO Serial Blink Command/Status (GP_SER_CMDSTS)—Offset 210h...... 452 6.2.78 GPIO Serial Blink Data (GP_SER_DATA)—Offset 214h ...... 453 6.2.79 GSX Controller Capabilities (GSX_CAP)—Offset 21Ch ...... 453 6.2.80 GSX Channel-0 Capabilities DW0 (GSX_C0CAP_DW0)—Offset 220h...... 454 6.2.81 GSX Channel-0 Capabilities DW1 (GSX_C0CAP_DW1)—Offset 224h...... 455 6.2.82 GSX Channel-0 GP Input Level DW0 (GSX_C0GPILVL_DW0)—Offset 228h.... 455 6.2.83 GSX Channel-0 GP Input Level DW1 (GSX_C0GPILVL_DW1)—Offset 22Ch ... 456 6.2.84 GSX Channel-0 GP Output Level DW0 (GSX_C0GPOLVL_DW0)—Offset 230h 456 6.2.85 GSX Channel-0 GP Output Level DW1 (GSX_C0GPOLVL_DW1)—Offset 234h 457 6.2.86 GSX Channel-0 Command (GSX_C0CMD)—Offset 238h ...... 457 6.2.87 GSX Channel-0 Test Mode (GSX_C0TM)—Offset 23Ch ...... 458 6.2.88 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_0)—Offset 400h ...... 459 6.2.89 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_0)—Offset 404h ...... 461 6.2.90 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_1)—Offset 408h ...... 462 6.2.91 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_1)—Offset 40Ch ...... 462 6.2.92 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_2)—Offset 410h ...... 462 6.2.93 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_2)—Offset 414h ...... 463 6.2.94 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_3)—Offset 418h ...... 463 6.2.95 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_3)—Offset 41Ch ...... 463 6.2.96 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_4)—Offset 420h ...... 463 6.2.97 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_4)—Offset 424h ...... 463 6.2.98 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_5)—Offset 428h ...... 463 6.2.99 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_5)—Offset 42Ch ...... 463 6.2.100Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_6)—Offset 430h ...... 463 6.2.101Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_6)—Offset 434h ...... 463 6.2.102Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_7)—Offset 438h ...... 464 6.2.103Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_7)—Offset 43Ch ...... 464 6.2.104Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_8)—Offset 440h ...... 464 6.2.105Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_8)—Offset 444h ...... 464 6.2.106Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_9)—Offset 448h ...... 464 6.2.107Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_9)—Offset 44Ch ...... 464 6.2.108Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_10)—Offset 450h ...... 464 6.2.109Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_10)—Offset 454h ...... 464 6.2.110Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_11)—Offset 458h ...... 464

332219-002 15 6.2.111Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_11)—Offset 45Ch...... 465 6.2.112Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_12)—Offset 460h...... 465 6.2.113Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_12)—Offset 464h...... 465 6.2.114Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_13)—Offset 468h...... 465 6.2.115Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_13)—Offset 46Ch...... 465 6.2.116Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_14)—Offset 470h...... 465 6.2.117Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_14)—Offset 474h...... 465 6.2.118Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_15)—Offset 478h...... 465 6.2.119Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_15)—Offset 47Ch...... 465 6.2.120Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_16)—Offset 480h...... 466 6.2.121Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_16)—Offset 484h...... 466 6.2.122Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_17)—Offset 488h...... 467 6.2.123Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_17)—Offset 48Ch...... 467 6.2.124Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_18)—Offset 490h...... 467 6.2.125Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_18)—Offset 494h...... 467 6.2.126Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_19)—Offset 498h...... 467 6.2.127Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_19)—Offset 49Ch...... 468 6.2.128Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_20)—Offset 4A0h...... 468 6.2.129Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_20)—Offset 4A4h...... 468 6.2.130Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_21)—Offset 4A8h...... 468 6.2.131Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_21)—Offset 4ACh...... 468 6.2.132Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_22)—Offset 4B0h...... 468 6.2.133Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_22)—Offset 4B4h...... 468 6.2.134Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_23)—Offset 4B8h...... 468 6.2.135Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_23)—Offset 4BCh...... 468 6.2.136Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_0)—Offset 4C0h ...... 469 6.2.137Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_0)—Offset 4C4h ...... 469 6.2.138Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_1)—Offset 4C8h ...... 469 6.2.139Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_1)—Offset 4CCh ...... 469 6.2.140Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_2)—Offset 4D0h ...... 469 6.2.141Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_2)—Offset 4D4h ...... 469 6.2.142Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_3)—Offset 4D8h ...... 469 6.2.143Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_3)—Offset 4DCh...... 469 6.2.144Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_4)—Offset 4E0h ...... 469 6.2.145Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_4)—Offset 4E4h ...... 470 6.2.146Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_5)—Offset 4E8h ...... 470 6.2.147Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_5)—Offset 4ECh ...... 470 6.2.148Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_6)—Offset 4F0h...... 470 6.2.149Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_6)—Offset 4F4h...... 470 6.2.150Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_7)—Offset 4F8h...... 470 6.2.151Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_7)—Offset 4FCh ...... 470 6.2.152Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_8)—Offset 500h ...... 470 6.2.153Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_8)—Offset 504h ...... 470 6.2.154Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_9)—Offset 508h ...... 471 6.2.155Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_9)—Offset 50Ch ...... 471 6.2.156Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_10)—Offset 510h...... 471 6.2.157Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_10)—Offset 514h...... 471 6.2.158Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_11)—Offset 518h...... 471 6.2.159Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_11)—Offset 51Ch ...... 471 6.2.160Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_12)—Offset 520h...... 471 6.2.161Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_12)—Offset 524h...... 471 6.2.162Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_13)—Offset 528h...... 471 6.2.163Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_13)—Offset 52Ch ...... 472 6.2.164Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_14)—Offset 530h...... 472 6.2.165Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_14)—Offset 534h...... 472

16 332219-002

6.2.166Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_15)—Offset 538h ...... 472 6.2.167Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_15)—Offset 53Ch ...... 472 6.2.168Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_16)—Offset 540h ...... 472 6.2.169Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_16)—Offset 544h ...... 472 6.2.170Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_17)—Offset 548h ...... 472 6.2.171Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_17)—Offset 54Ch ...... 472 6.2.172Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_18)—Offset 550h ...... 473 6.2.173Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_18)—Offset 554h ...... 473 6.2.174Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_19)—Offset 558h ...... 473 6.2.175Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_19)—Offset 55Ch ...... 473 6.2.176Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_20)—Offset 560h ...... 473 6.2.177Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_20)—Offset 564h ...... 473 6.2.178Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_21)—Offset 568h ...... 473 6.2.179Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_21)—Offset 56Ch ...... 473 6.2.180Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_22)—Offset 570h ...... 473 6.2.181Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_22)—Offset 574h ...... 474 6.2.182Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_23)—Offset 578h ...... 474 6.2.183Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_23)—Offset 57Ch ...... 474 6.2.184Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_0)—Offset 580h ...... 474 6.2.185Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_0)—Offset 584h ...... 474 6.2.186Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_1)—Offset 588h ...... 474 6.2.187Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_1)—Offset 58Ch ...... 474 6.2.188Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_2)—Offset 590h ...... 474 6.2.189Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_2)—Offset 594h ...... 474 6.2.190Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_3)—Offset 598h ...... 475 6.2.191Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_3)—Offset 59Ch ...... 475 6.2.192Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_4)—Offset 5A0h ...... 475 6.2.193Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_4)—Offset 5A4h ...... 475 6.2.194Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_5)—Offset 5A8h ...... 475 6.2.195Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_5)—Offset 5ACh ...... 475 6.2.196Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_6)—Offset 5B0h ...... 475 6.2.197Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_6)—Offset 5B4h ...... 475 6.2.198Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_7)—Offset 5B8h ...... 475 6.2.199Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_7)—Offset 5BCh ...... 476 6.2.200Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_8)—Offset 5C0h ...... 476 6.2.201Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_8)—Offset 5C4h ...... 476 6.2.202Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_9)—Offset 5C8h ...... 476 6.2.203Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_9)—Offset 5CCh ...... 476 6.2.204Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_10)—Offset 5D0h ...... 476 6.2.205Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_10)—Offset 5D4h ...... 476 6.2.206Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_11)—Offset 5D8h ...... 476 6.2.207Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_11)—Offset 5DCh ...... 476 6.2.208Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_12)—Offset 5E0h...... 477 6.2.209Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_12)—Offset 5E4h...... 477 6.2.210Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_0)—Offset 5E8h ...... 477 6.2.211Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_0)—Offset 5ECh ...... 477 6.2.212Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_1)—Offset 5F0h...... 477 6.2.213Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_1)—Offset 5F4h...... 477 6.2.214Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_2)—Offset 5F8h...... 477 6.2.215Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_2)—Offset 5FCh ...... 477 6.2.216Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_3)—Offset 600h ...... 477 6.2.217Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_3)—Offset 604h ...... 478 6.2.218Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_4)—Offset 608h ...... 478 6.2.219Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_4)—Offset 60Ch ...... 478 6.2.220Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_5)—Offset 610h ...... 478

332219-002 17 6.2.221Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_5)—Offset 614h ...... 478 6.2.222Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_6)—Offset 618h ...... 478 6.2.223Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_6)—Offset 61Ch...... 478 6.2.224Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_7)—Offset 620h ...... 478 6.2.225Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_7)—Offset 624h ...... 478 6.2.226Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_8)—Offset 628h ...... 479 6.2.227Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_8)—Offset 62Ch...... 479 6.2.228Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_9)—Offset 630h ...... 479 6.2.229Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_9)—Offset 634h ...... 479 6.2.230Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_10)—Offset 638h ...... 479 6.2.231Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_10)—Offset 63Ch ...... 479 6.2.232Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_11)—Offset 640h ...... 479 6.2.233Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_11)—Offset 644h ...... 479 6.2.234Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_12)—Offset 648h ...... 479 6.2.235Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_12)—Offset 64Ch ...... 480 6.2.236Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_13)—Offset 650h ...... 480 6.2.237Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_13)—Offset 654h ...... 480 6.2.238Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_14)—Offset 658h ...... 480 6.2.239Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_14)—Offset 65Ch ...... 480 6.2.240Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_15)—Offset 660h ...... 480 6.2.241Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_15)—Offset 664h ...... 480 6.2.242Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_16)—Offset 668h ...... 480 6.2.243Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_16)—Offset 66Ch ...... 480 6.2.244Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_17)—Offset 670h ...... 481 6.2.245Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_17)—Offset 674h ...... 481 6.2.246Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_18)—Offset 678h ...... 481 6.2.247Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_18)—Offset 67Ch ...... 481 6.2.248Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_19)—Offset 680h ...... 481 6.2.249Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_19)—Offset 684h ...... 481 6.2.250Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_20)—Offset 688h ...... 481 6.2.251Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_20)—Offset 68Ch ...... 481 6.2.252Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_21)—Offset 690h ...... 481 6.2.253Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_21)—Offset 694h ...... 482 6.2.254Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_22)—Offset 698h ...... 482 6.2.255Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_22)—Offset 69Ch ...... 482 6.2.256Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_23)—Offset 6A0h ...... 482 6.2.257Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_23)—Offset 6A4h ...... 482 6.2.258Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_0)—Offset 6A8h ...... 482 6.2.259Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_0)—Offset 6ACh ...... 482 6.2.260Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_1)—Offset 6B0h ...... 482 6.2.261Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_1)—Offset 6B4h ...... 482 6.2.262Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_2)—Offset 6B8h ...... 483 6.2.263Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_2)—Offset 6BCh ...... 483 6.2.264Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_3)—Offset 6C0h ...... 483 6.2.265Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_3)—Offset 6C4h ...... 483 6.2.266Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_4)—Offset 6C8h ...... 483 6.2.267Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_4)—Offset 6CCh ...... 483 6.2.268Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_5)—Offset 6D0h ...... 483 6.2.269Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_5)—Offset 6D4h ...... 483 6.2.270Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_6)—Offset 6D8h ...... 483 6.2.271Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_6)—Offset 6DCh...... 484 6.2.272Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_7)—Offset 6E0h ...... 484 6.2.273Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_7)—Offset 6E4h ...... 484 6.2.274Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_8)—Offset 6E8h ...... 484 6.2.275Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_8)—Offset 6ECh ...... 484

18 332219-002

6.2.276Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_9)—Offset 6F0h ...... 484 6.2.277Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_9)—Offset 6F4h ...... 484 6.2.278Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_10)—Offset 6F8h ...... 484 6.2.279Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_10)—Offset 6FCh ...... 484 6.2.280Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_11)—Offset 700h ...... 485 6.2.281Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_11)—Offset 704h ...... 485 6.2.282Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_12)—Offset 708h ...... 485 6.2.283Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_12)—Offset 70Ch ...... 485 6.2.284Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_13)—Offset 710h ...... 485 6.2.285Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_13)—Offset 714h ...... 485 6.2.286Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_14)—Offset 718h ...... 485 6.2.287Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_14)—Offset 71Ch ...... 485 6.2.288Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_15)—Offset 720h ...... 485 6.2.289Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_15)—Offset 724h ...... 486 6.2.290Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_16)—Offset 728h ...... 486 6.2.291Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_16)—Offset 72Ch ...... 486 6.2.292Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_17)—Offset 730h ...... 486 6.2.293Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_17)—Offset 734h ...... 486 6.2.294Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_18)—Offset 738h ...... 486 6.2.295Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_18)—Offset 73Ch ...... 486 6.2.296Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_19)—Offset 740h ...... 486 6.2.297Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_19)—Offset 744h ...... 486 6.2.298Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_20)—Offset 748h ...... 487 6.2.299Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_20)—Offset 74Ch ...... 487 6.2.300Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_21)—Offset 750h ...... 487 6.2.301Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_21)—Offset 754h ...... 487 6.2.302Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_22)—Offset 758h ...... 487 6.2.303Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_22)—Offset 75Ch ...... 487 6.2.304Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_23)—Offset 760h ...... 487 6.2.305Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_23)—Offset 764h ...... 487 6.2.306Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_0)—Offset 768h ...... 487 6.2.307Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_0)—Offset 76Ch...... 488 6.2.308Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_1)—Offset 770h ...... 488 6.2.309Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_1)—Offset 774h ...... 488 6.2.310Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_2)—Offset 778h ...... 488 6.2.311Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_2)—Offset 77Ch...... 488 6.2.312Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_3)—Offset 780h ...... 488 6.2.313Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_3)—Offset 784h ...... 488 6.2.314Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_4)—Offset 788h ...... 488 6.2.315Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_4)—Offset 78Ch...... 488 6.2.316Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_5)—Offset 790h ...... 489 6.2.317Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_5)—Offset 794h ...... 489 6.2.318Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_6)—Offset 798h ...... 489 6.2.319Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_6)—Offset 79Ch...... 489 6.2.320Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_7)—Offset 7A0h...... 489 6.2.321Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_7)—Offset 7A4h...... 489 6.2.322Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_8)—Offset 7A8h...... 489 6.2.323Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_8)—Offset 7ACh...... 489 6.2.324Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_9)—Offset 7B0h...... 489 6.2.325Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_9)—Offset 7B4h...... 490 6.2.326Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_10)—Offset 7B8h ...... 490 6.2.327Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_10)—Offset 7BCh ...... 490 6.2.328Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_11)—Offset 7C0h ...... 490 6.2.329Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_11)—Offset 7C4h ...... 490 6.2.330Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_12)—Offset 7C8h ...... 490

332219-002 19 6.2.331Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_12)—Offset 7CCh ...... 490 6.2.332Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_13)—Offset 7D0h ...... 490 6.2.333Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_13)—Offset 7D4h ...... 490 6.2.334Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_14)—Offset 7D8h ...... 491 6.2.335Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_14)—Offset 7DCh ...... 491 6.2.336Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_15)—Offset 7E0h...... 491 6.2.337Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_15)—Offset 7E4h...... 491 6.2.338Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_16)—Offset 7E8h...... 491 6.2.339Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_16)—Offset 7ECh...... 491 6.2.340Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_17)—Offset 7F0h...... 491 6.2.341Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_17)—Offset 7F4h...... 491 6.2.342Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_18)—Offset 7F8h...... 491 6.2.343Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_18)—Offset 7FCh...... 492 6.2.344Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_19)—Offset 800h...... 492 6.2.345Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_19)—Offset 804h...... 492 6.2.346Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_20)—Offset 808h...... 492 6.2.347Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_20)—Offset 80Ch ...... 492 6.2.348Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_21)—Offset 810h...... 492 6.2.349Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_21)—Offset 814h...... 492 6.2.350Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_22)—Offset 818h...... 492 6.2.351Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_22)—Offset 81Ch ...... 492 6.2.352Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_23)—Offset 820h...... 493 6.2.353Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_23)—Offset 824h...... 493 6.3 GPIO Community 2 Registers Summary ...... 493 6.3.1 Family Base Address (FAMBAR)—Offset 8h ...... 494 6.3.2 Pad Base Address (PADBAR)—Offset Ch...... 495 6.3.3 Miscellaneous Configuration (MISCCFG)—Offset 10h...... 495 6.3.4 Pad Ownership (PAD_OWN_GPD_0)—Offset 20h ...... 497 6.3.5 Pad Ownership (PAD_OWN_GPD_1)—Offset 24h ...... 498 6.3.6 Pad Configuration Lock (PADCFGLOCK_GPD_0)—Offset A0h ...... 498 6.3.7 Pad Configuration Lock (PADCFGLOCKTX_GPD_0)—Offset A4h...... 499 6.3.8 Host Software Pad Ownership (HOSTSW_OWN_GPD_0)—Offset D0h ...... 500 6.3.9 GPI Interrupt Status (GPI_IS_GPD_0)—Offset 100h ...... 502 6.3.10 GPI Interrupt Enable (GPI_IE_GPD_0)—Offset 120h ...... 503 6.3.11 GPI General Purpose Events Status (GPI_GPE_STS_GPD_0)—Offset 140h .... 504 6.3.12 GPI General Purpose Events Enable (GPI_GPE_EN_GPD_0)—Offset 160h ..... 505 6.3.13 Pad Configuration DW0 (PAD_CFG_DW0_GPD_0)—Offset 400h...... 506 6.3.14 Pad Configuration DW1 (PAD_CFG_DW1_GPD_0)—Offset 404h...... 508 6.3.15 Pad Configuration DW0 (PAD_CFG_DW0_GPD_1)—Offset 408h...... 509 6.3.16 Pad Configuration DW1 (PAD_CFG_DW1_GPD_1)—Offset 40Ch...... 509 6.3.17 Pad Configuration DW0 (PAD_CFG_DW0_GPD_2)—Offset 410h...... 509 6.3.18 Pad Configuration DW1 (PAD_CFG_DW1_GPD_2)—Offset 414h...... 510 6.3.19 Pad Configuration DW0 (PAD_CFG_DW0_GPD_3)—Offset 418h...... 510 6.3.20 Pad Configuration DW1 (PAD_CFG_DW1_GPD_3)—Offset 41Ch...... 510 6.3.21 Pad Configuration DW0 (PAD_CFG_DW0_GPD_4)—Offset 420h...... 510 6.3.22 Pad Configuration DW1 (PAD_CFG_DW1_GPD_4)—Offset 424h...... 510 6.3.23 Pad Configuration DW0 (PAD_CFG_DW0_GPD_5)—Offset 428h...... 510 6.3.24 Pad Configuration DW1 (PAD_CFG_DW1_GPD_5)—Offset 42Ch...... 510 6.3.25 Pad Configuration DW0 (PAD_CFG_DW0_GPD_6)—Offset 430h...... 510 6.3.26 Pad Configuration DW1 (PAD_CFG_DW1_GPD_6)—Offset 434h...... 510 6.3.27 Pad Configuration DW0 (PAD_CFG_DW0_GPD_7)—Offset 438h...... 511 6.3.28 Pad Configuration DW1 (PAD_CFG_DW1_GPD_7)—Offset 43Ch...... 511 6.3.29 Pad Configuration DW0 (PAD_CFG_DW0_GPD_8)—Offset 440h...... 511 6.3.30 Pad Configuration DW1 (PAD_CFG_DW1_GPD_8)—Offset 444h...... 511 6.3.31 Pad Configuration DW0 (PAD_CFG_DW0_GPD_9)—Offset 448h...... 511

20 332219-002

6.3.32 Pad Configuration DW1 (PAD_CFG_DW1_GPD_9)—Offset 44Ch ...... 511 6.3.33 Pad Configuration DW0 (PAD_CFG_DW0_GPD_10)—Offset 450h...... 511 6.3.34 Pad Configuration DW1 (PAD_CFG_DW1_GPD_10)—Offset 454h...... 511 6.3.35 Pad Configuration DW0 (PAD_CFG_DW0_GPD_11)—Offset 458h...... 511 6.3.36 Pad Configuration DW1 (PAD_CFG_DW1_GPD_11)—Offset 45Ch ...... 512 6.4 GPIO Community 3 Registers Summary...... 512 6.4.1 Capability List Register (CAP_LIST_0)—Offset 4h...... 513 6.4.2 Family Base Address (FAMBAR)—Offset 8h ...... 514 6.4.3 Pad Base Address (PADBAR)—Offset Ch ...... 514 6.4.4 Miscellaneous Configuration (MISCCFG)—Offset 10h ...... 515 6.4.5 Pad Ownership (PAD_OWN_GPP_I_0)—Offset 20h ...... 516 6.4.6 Pad Ownership (PAD_OWN_GPP_I_1)—Offset 24h ...... 517 6.4.7 Pad Configuration Lock (PADCFGLOCK_GPP_I_0)—Offset 90h...... 517 6.4.8 Pad Configuration Lock (PADCFGLOCKTX_GPP_I_0)—Offset 94h ...... 518 6.4.9 Host Software Pad Ownership (HOSTSW_OWN_GPP_I_0)—Offset D0h...... 520 6.4.10 GPI Interrupt Status (GPI_IS_GPP_I_0)—Offset 100h ...... 521 6.4.11 GPI Interrupt Enable (GPI_IE_GPP_I_0)—Offset 120h ...... 522 6.4.12 GPI General Purpose Events Status (GPI_GPE_STS_GPP_I_0)—Offset 140h . 523 6.4.13 GPI General Purpose Events Enable (GPI_GPE_EN_GPP_I_0)—Offset 160h... 524 6.4.14 SMI Status (GPI_SMI_STS_GPP_I_0)—Offset 180h ...... 525 6.4.15 SMI Enable (GPI_SMI_EN_GPP_I_0)—Offset 1A0h ...... 526 6.4.16 NMI Status (GPI_NMI_STS_GPP_I_0)—Offset 1C0h ...... 527 6.4.17 NMI Enable (GPI_NMI_EN_GPP_I_0)—Offset 1E0h...... 528 6.4.18 Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_0)—Offset 400h ...... 529 6.4.19 Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_0)—Offset 404h ...... 531 6.4.20 Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_1)—Offset 408h ...... 532 6.4.21 Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_1)—Offset 40Ch...... 532 6.4.22 Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_2)—Offset 410h ...... 532 6.4.23 Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_2)—Offset 414h ...... 532 6.4.24 Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_3)—Offset 418h ...... 532 6.4.25 Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_3)—Offset 41Ch...... 532 6.4.26 Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_4)—Offset 420h ...... 532 6.4.27 Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_4)—Offset 424h ...... 532 6.4.28 Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_5)—Offset 428h ...... 532 6.4.29 Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_5)—Offset 42Ch...... 533 6.4.30 Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_6)—Offset 430h ...... 533 6.4.31 Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_6)—Offset 434h ...... 533 6.4.32 Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_7)—Offset 438h ...... 533 6.4.33 Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_7)—Offset 43Ch...... 533 6.4.34 Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_8)—Offset 440h ...... 533 6.4.35 Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_8)—Offset 444h ...... 533 6.4.36 Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_9)—Offset 448h ...... 533 6.4.37 Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_9)—Offset 44Ch...... 533 6.4.38 Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_10)—Offset 450h ...... 534 6.4.39 Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_10)—Offset 454h ...... 534 7 GPIO for SKL PCH-LP ...... 535 7.1 GPIO Community 0 Registers Summary...... 535 7.1.1 Family Base Address (FAMBAR)—Offset 8h ...... 539 7.1.2 Pad Base Address (PADBAR)—Offset Ch ...... 540 7.1.3 Miscellaneous Configuration (MISCCFG)—Offset 10h ...... 540 7.1.4 Pad Ownership (PAD_OWN_GPP_A_0)—Offset 20h ...... 542 7.1.5 Pad Ownership (PAD_OWN_GPP_A_1)—Offset 24h ...... 543 7.1.6 Pad Ownership (PAD_OWN_GPP_A_2)—Offset 28h ...... 543 7.1.7 Pad Ownership (PAD_OWN_GPP_B_0)—Offset 30h ...... 543

332219-002 21 7.1.8 Pad Ownership (PAD_OWN_GPP_B_1)—Offset 34h ...... 543 7.1.9 Pad Ownership (PAD_OWN_GPP_B_2)—Offset 38h ...... 543 7.1.10 Pad Configuration Lock (PADCFGLOCK_GPP_A)—Offset A0h...... 543 7.1.11 Pad Configuration Lock (PADCFGLOCKTX_GPP_A)—Offset A4h ...... 545 7.1.12 Pad Configuration Lock (PADCFGLOCK_GPP_B)—Offset A8h...... 547 7.1.13 Pad Configuration Lock (PADCFGLOCKTX_GPP_B)—Offset ACh...... 547 7.1.14 Host Software Pad Ownership (HOSTSW_OWN_GPP_A)—Offset D0h...... 547 7.1.15 Host Software Pad Ownership (HOSTSW_OWN_GPP_B)—Offset D4h...... 549 7.1.16 GPI Interrupt Status (GPI_IS_GPP_A)—Offset 100h...... 549 7.1.17 GPI Interrupt Status (GPI_IS_GPP_B)—Offset 104h...... 551 7.1.18 GPI Interrupt Enable (GPI_IE_GPP_A)—Offset 120h ...... 551 7.1.19 GPI Interrupt Enable (GPI_IE_GPP_B)—Offset 124h ...... 552 7.1.20 GPI General Purpose Events Status (GPI_GPE_STS_GPP_A)—Offset 140h .... 552 7.1.21 GPI General Purpose Events Status (GPI_GPE_STS_GPP_B)—Offset 144h .... 554 7.1.22 GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A)—Offset 160h...... 554 7.1.23 GPI General Purpose Events Enable (GPI_GPE_EN_GPP_B)—Offset 164h...... 556 7.1.24 SMI Status (GPI_SMI_STS_GPP_B)—Offset 184h ...... 556 7.1.25 SMI Enable (GPI_SMI_EN_GPP_B)—Offset 1A4h ...... 557 7.1.26 NMI Status (GPI_NMI_STS_GPP_B)—Offset 1C4h...... 558 7.1.27 NMI Enable (GPI_NMI_EN_GPP_B)—Offset 1E4h ...... 559 7.1.28 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_0)—Offset 400h...... 560 7.1.29 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_0)—Offset 404h...... 562 7.1.30 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_1)—Offset 408h...... 563 7.1.31 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_1)—Offset 40Ch ...... 563 7.1.32 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_2)—Offset 410h...... 563 7.1.33 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_2)—Offset 414h...... 563 7.1.34 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_3)—Offset 418h...... 564 7.1.35 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_3)—Offset 41Ch ...... 564 7.1.36 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_4)—Offset 420h...... 564 7.1.37 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_4)—Offset 424h...... 564 7.1.38 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_5)—Offset 428h...... 564 7.1.39 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_5)—Offset 42Ch ...... 564 7.1.40 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_6)—Offset 430h...... 564 7.1.41 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_6)—Offset 434h...... 564 7.1.42 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_7)—Offset 438h...... 565 7.1.43 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_7)—Offset 43Ch ...... 565 7.1.44 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_8)—Offset 440h...... 565 7.1.45 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_8)—Offset 444h...... 565 7.1.46 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_9)—Offset 448h...... 565 7.1.47 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_9)—Offset 44Ch ...... 565 7.1.48 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_10)—Offset 450h...... 565 7.1.49 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_10)—Offset 454h...... 565 7.1.50 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_11)—Offset 458h...... 566 7.1.51 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_11)—Offset 45Ch...... 566 7.1.52 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_12)—Offset 460h...... 566 7.1.53 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_12)—Offset 464h...... 566 7.1.54 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_13)—Offset 468h...... 566 7.1.55 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_13)—Offset 46Ch...... 566 7.1.56 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_14)—Offset 470h...... 566 7.1.57 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_14)—Offset 474h...... 566 7.1.58 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_15)—Offset 478h...... 567 7.1.59 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_15)—Offset 47Ch...... 567 7.1.60 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_16)—Offset 480h...... 567 7.1.61 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_16)—Offset 484h...... 567 7.1.62 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_17)—Offset 488h...... 567

22 332219-002

7.1.63 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_17)—Offset 48Ch ...... 567 7.1.64 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_18)—Offset 490h ...... 567 7.1.65 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_18)—Offset 494h ...... 567 7.1.66 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_19)—Offset 498h ...... 568 7.1.67 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_19)—Offset 49Ch ...... 568 7.1.68 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_20)—Offset 4A0h ...... 568 7.1.69 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_20)—Offset 4A4h ...... 568 7.1.70 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_21)—Offset 4A8h ...... 568 7.1.71 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_21)—Offset 4ACh ...... 568 7.1.72 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_22)—Offset 4B0h ...... 568 7.1.73 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_22)—Offset 4B4h ...... 568 7.1.74 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_23)—Offset 4B8h ...... 569 7.1.75 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_23)—Offset 4BCh ...... 569 7.1.76 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_0)—Offset 4C0h ...... 569 7.1.77 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_0)—Offset 4C4h ...... 569 7.1.78 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_1)—Offset 4C8h ...... 569 7.1.79 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_1)—Offset 4CCh...... 569 7.1.80 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_2)—Offset 4D0h...... 569 7.1.81 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_2)—Offset 4D4h...... 569 7.1.82 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_3)—Offset 4D8h...... 570 7.1.83 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_3)—Offset 4DCh...... 570 7.1.84 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_4)—Offset 4E0h ...... 570 7.1.85 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_4)—Offset 4E4h ...... 570 7.1.86 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_5)—Offset 4E8h ...... 570 7.1.87 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_5)—Offset 4ECh ...... 570 7.1.88 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_6)—Offset 4F0h ...... 570 7.1.89 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_6)—Offset 4F4h ...... 570 7.1.90 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_7)—Offset 4F8h ...... 571 7.1.91 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_7)—Offset 4FCh ...... 571 7.1.92 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_8)—Offset 500h ...... 571 7.1.93 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_8)—Offset 504h ...... 571 7.1.94 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_9)—Offset 508h ...... 571 7.1.95 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_9)—Offset 50Ch ...... 571 7.1.96 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_10)—Offset 510h ...... 571 7.1.97 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_10)—Offset 514h ...... 571 7.1.98 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_11)—Offset 518h ...... 572 7.1.99 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_11)—Offset 51Ch ...... 572 7.1.100Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_12)—Offset 520h ...... 572 7.1.101Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_12)—Offset 524h ...... 572 7.1.102Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_13)—Offset 528h ...... 572 7.1.103Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_13)—Offset 52Ch ...... 572 7.1.104Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_14)—Offset 530h ...... 572 7.1.105Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_14)—Offset 534h ...... 572 7.1.106Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_15)—Offset 538h ...... 573 7.1.107Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_15)—Offset 53Ch ...... 573 7.1.108Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_16)—Offset 540h ...... 573 7.1.109Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_16)—Offset 544h ...... 573 7.1.110Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_17)—Offset 548h ...... 573 7.1.111Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_17)—Offset 54Ch ...... 573 7.1.112Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_18)—Offset 550h ...... 573 7.1.113Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_18)—Offset 554h ...... 573 7.1.114Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_19)—Offset 558h ...... 574 7.1.115Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_19)—Offset 55Ch ...... 574 7.1.116Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_20)—Offset 560h ...... 574 7.1.117Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_20)—Offset 564h ...... 574

332219-002 23 7.1.118Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_21)—Offset 568h...... 574 7.1.119Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_21)—Offset 56Ch...... 574 7.1.120Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_22)—Offset 570h...... 574 7.1.121Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_22)—Offset 574h...... 574 7.1.122Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_23)—Offset 578h...... 575 7.1.123Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_23)—Offset 57Ch...... 575 7.2 GPIO Community 1 Registers Summary ...... 575 7.2.1 Family Base Address (FAMBAR)—Offset 8h ...... 582 7.2.2 Pad Base Address (PADBAR)—Offset Ch...... 582 7.2.3 Miscellaneous Configuration (MISCCFG)—Offset 10h...... 583 7.2.4 Pad Ownership (PAD_OWN_GPP_C_0)—Offset 20h...... 584 7.2.5 Pad Ownership (PAD_OWN_GPP_C_1)—Offset 24h...... 586 7.2.6 Pad Ownership (PAD_OWN_GPP_C_2)—Offset 28h...... 586 7.2.7 Pad Ownership (PAD_OWN_GPP_D_0)—Offset 30h...... 586 7.2.8 Pad Ownership (PAD_OWN_GPP_D_1)—Offset 34h...... 586 7.2.9 Pad Ownership (PAD_OWN_GPP_D_2)—Offset 38h...... 586 7.2.10 Pad Ownership (PAD_OWN_GPP_E_0)—Offset 40h ...... 586 7.2.11 Pad Ownership (PAD_OWN_GPP_E_1)—Offset 44h ...... 586 7.2.12 Pad Ownership (PAD_OWN_GPP_E_2)—Offset 48h ...... 586 7.2.13 Pad Configuration Lock (PADCFGLOCK_GPP_C)—Offset A0h...... 586 7.2.14 Pad Configuration Lock (PADCFGLOCKTX_GPP_C)—Offset A4h ...... 588 7.2.15 Pad Configuration Lock (PADCFGLOCK_GPP_D)—Offset A8h ...... 590 7.2.16 Pad Configuration Lock (PADCFGLOCKTX_GPP_D)—Offset ACh...... 590 7.2.17 Pad Configuration Lock (PADCFGLOCK_GPP_E)—Offset B0h...... 590 7.2.18 Pad Configuration Lock (PADCFGLOCKTX_GPP_E)—Offset B4h ...... 590 7.2.19 Host Software Pad Ownership (HOSTSW_OWN_GPP_C)—Offset D0h...... 590 7.2.20 Host Software Pad Ownership (HOSTSW_OWN_GPP_D)—Offset D4h...... 592 7.2.21 Host Software Pad Ownership (HOSTSW_OWN_GPP_E)—Offset D8h ...... 592 7.2.22 GPI Interrupt Status (GPI_IS_GPP_C)—Offset 100h...... 592 7.2.23 GPI Interrupt Status (GPI_IS_GPP_D)—Offset 104h ...... 594 7.2.24 GPI Interrupt Status (GPI_IS_GPP_E)—Offset 108h...... 594 7.2.25 GPI Interrupt Enable (GPI_IE_GPP_C)—Offset 120h ...... 594 7.2.26 GPI Interrupt Enable (GPI_IE_GPP_D)—Offset 124h ...... 596 7.2.27 GPI Interrupt Enable (GPI_IE_GPP_E)—Offset 128h...... 596 7.2.28 GPI General Purpose Events Status (GPI_GPE_STS_GPP_C)—Offset 140h .... 596 7.2.29 GPI General Purpose Events Status (GPI_GPE_STS_GPP_D)—Offset 144h .... 598 7.2.30 GPI General Purpose Events Status (GPI_GPE_STS_GPP_E)—Offset 148h..... 598 7.2.31 GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C)—Offset 160h...... 598 7.2.32 GPI General Purpose Events Enable (GPI_GPE_EN_GPP_D)—Offset 164h...... 600 7.2.33 GPI General Purpose Events Enable (GPI_GPE_EN_GPP_E)—Offset 168h ...... 600 7.2.34 SMI Status (GPI_SMI_STS_GPP_C)—Offset 180h ...... 600 7.2.35 SMI Status (GPI_SMI_STS_GPP_D)—Offset 184h ...... 601 7.2.36 SMI Status (GPI_SMI_STS_GPP_E)—Offset 188h ...... 602 7.2.37 SMI Enable (GPI_SMI_EN_GPP_C)—Offset 1A0h ...... 603 7.2.38 SMI Enable (GPI_SMI_EN_GPP_D)—Offset 1A4h ...... 604 7.2.39 SMI Enable (GPI_SMI_EN_GPP_E)—Offset 1A8h ...... 605 7.2.40 NMI Status (GPI_NMI_STS_GPP_C)—Offset 1C0h...... 606 7.2.41 NMI Status (GPI_NMI_STS_GPP_D)—Offset 1C4h ...... 607 7.2.42 NMI Status (GPI_NMI_STS_GPP_E)—Offset 1C8h...... 608 7.2.43 NMI Enable (GPI_NMI_EN_GPP_C)—Offset 1E0h ...... 609 7.2.44 NMI Enable (GPI_NMI_EN_GPP_D)—Offset 1E4h...... 610 7.2.45 NMI Enable (GPI_NMI_EN_GPP_E)—Offset 1E8h ...... 611 7.2.46 PWM Control (PWMC)—Offset 204h ...... 612 7.2.47 GPIO Serial Blink Enable (GP_SER_BLINK)—Offset 20Ch ...... 612 7.2.48 GPIO Serial Blink Command/Status (GP_SER_CMDSTS)—Offset 210h ...... 613

24 332219-002

7.2.49 GPIO Serial Blink Data (GP_SER_DATA)—Offset 214h ...... 614 7.2.50 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_0)—Offset 400h ...... 614 7.2.51 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_0)—Offset 404h ...... 617 7.2.52 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_1)—Offset 408h ...... 618 7.2.53 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_1)—Offset 40Ch ...... 618 7.2.54 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_2)—Offset 410h ...... 618 7.2.55 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_2)—Offset 414h ...... 618 7.2.56 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_3)—Offset 418h ...... 618 7.2.57 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_3)—Offset 41Ch ...... 618 7.2.58 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_4)—Offset 420h ...... 618 7.2.59 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_4)—Offset 424h ...... 618 7.2.60 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_5)—Offset 428h ...... 618 7.2.61 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_5)—Offset 42Ch ...... 619 7.2.62 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_6)—Offset 430h ...... 619 7.2.63 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_6)—Offset 434h ...... 619 7.2.64 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_7)—Offset 438h ...... 619 7.2.65 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_7)—Offset 43Ch ...... 619 7.2.66 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_8)—Offset 440h ...... 619 7.2.67 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_8)—Offset 444h ...... 619 7.2.68 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_9)—Offset 448h ...... 619 7.2.69 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_9)—Offset 44Ch ...... 619 7.2.70 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_10)—Offset 450h ...... 620 7.2.71 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_10)—Offset 454h ...... 620 7.2.72 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_11)—Offset 458h ...... 620 7.2.73 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_11)—Offset 45Ch ...... 620 7.2.74 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_12)—Offset 460h ...... 620 7.2.75 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_12)—Offset 464h ...... 620 7.2.76 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_13)—Offset 468h ...... 620 7.2.77 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_13)—Offset 46Ch ...... 620 7.2.78 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_14)—Offset 470h ...... 620 7.2.79 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_14)—Offset 474h ...... 621 7.2.80 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_15)—Offset 478h ...... 621 7.2.81 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_15)—Offset 47Ch ...... 621 7.2.82 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_16)—Offset 480h ...... 621 7.2.83 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_16)—Offset 484h ...... 621 7.2.84 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_17)—Offset 488h ...... 622 7.2.85 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_17)—Offset 48Ch ...... 622 7.2.86 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_18)—Offset 490h ...... 622 7.2.87 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_18)—Offset 494h ...... 622 7.2.88 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_19)—Offset 498h ...... 623 7.2.89 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_19)—Offset 49Ch ...... 623 7.2.90 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_20)—Offset 4A0h ...... 623 7.2.91 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_20)—Offset 4A4h ...... 623 7.2.92 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_21)—Offset 4A8h ...... 623 7.2.93 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_21)—Offset 4ACh ...... 623 7.2.94 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_22)—Offset 4B0h ...... 623 7.2.95 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_22)—Offset 4B4h ...... 623 7.2.96 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_23)—Offset 4B8h ...... 623 7.2.97 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_23)—Offset 4BCh ...... 624 7.2.98 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_0)—Offset 4C0h...... 624 7.2.99 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_0)—Offset 4C4h...... 624 7.2.100Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_1)—Offset 4C8h...... 624 7.2.101Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_1)—Offset 4CCh...... 624 7.2.102Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_2)—Offset 4D0h...... 624 7.2.103Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_2)—Offset 4D4h...... 624

332219-002 25 7.2.104Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_3)—Offset 4D8h ...... 624 7.2.105Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_3)—Offset 4DCh...... 624 7.2.106Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_4)—Offset 4E0h ...... 625 7.2.107Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_4)—Offset 4E4h ...... 625 7.2.108Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_5)—Offset 4E8h ...... 625 7.2.109Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_5)—Offset 4ECh ...... 625 7.2.110Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_6)—Offset 4F0h...... 625 7.2.111Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_6)—Offset 4F4h...... 625 7.2.112Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_7)—Offset 4F8h...... 625 7.2.113Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_7)—Offset 4FCh ...... 625 7.2.114Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_8)—Offset 504h ...... 625 7.2.115Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_9)—Offset 508h ...... 626 7.2.116Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_9)—Offset 50Ch ...... 626 7.2.117Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_10)—Offset 510h...... 626 7.2.118Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_10)—Offset 514h...... 626 7.2.119Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_11)—Offset 518h...... 626 7.2.120Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_11)—Offset 51Ch ...... 626 7.2.121Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_12)—Offset 520h...... 626 7.2.122Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_12)—Offset 524h...... 626 7.2.123Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_13)—Offset 528h...... 626 7.2.124Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_13)—Offset 52Ch ...... 627 7.2.125Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_14)—Offset 530h...... 627 7.2.126Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_14)—Offset 534h...... 627 7.2.127Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_15)—Offset 538h...... 627 7.2.128Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_15)—Offset 53Ch ...... 627 7.2.129Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_16)—Offset 540h...... 627 7.2.130Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_16)—Offset 544h...... 627 7.2.131Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_17)—Offset 548h...... 627 7.2.132Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_17)—Offset 54Ch ...... 627 7.2.133Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_18)—Offset 550h...... 628 7.2.134Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_18)—Offset 554h...... 628 7.2.135Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_19)—Offset 558h...... 628 7.2.136Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_19)—Offset 55Ch ...... 628 7.2.137Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_20)—Offset 560h...... 628 7.2.138Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_20)—Offset 564h...... 628 7.2.139Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_21)—Offset 568h...... 628 7.2.140Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_21)—Offset 56Ch ...... 628 7.2.141Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_22)—Offset 570h...... 628 7.2.142Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_22)—Offset 574h...... 629 7.2.143Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_23)—Offset 578h...... 629 7.2.144Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_23)—Offset 57Ch ...... 629 7.2.145Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_0)—Offset 580h...... 629 7.2.146Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_0)—Offset 584h...... 629 7.2.147Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_1)—Offset 588h...... 629 7.2.148Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_1)—Offset 58Ch...... 629 7.2.149Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_2)—Offset 590h...... 629 7.2.150Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_2)—Offset 594h...... 629 7.2.151Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_3)—Offset 598h...... 630 7.2.152Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_3)—Offset 59Ch...... 630 7.2.153Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_4)—Offset 5A0h...... 630 7.2.154Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_4)—Offset 5A4h...... 630 7.2.155Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_5)—Offset 5A8h...... 630 7.2.156Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_5)—Offset 5ACh ...... 630 7.2.157Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_6)—Offset 5B0h...... 630 7.2.158Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_6)—Offset 5B4h...... 630

26 332219-002

7.2.159Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_7)—Offset 5B8h ...... 630 7.2.160Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_7)—Offset 5BCh ...... 631 7.2.161Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_8)—Offset 5C0h ...... 631 7.2.162Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_8)—Offset 5C4h ...... 631 7.2.163Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_9)—Offset 5C8h ...... 631 7.2.164Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_9)—Offset 5CCh ...... 631 7.2.165Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_10)—Offset 5D0h ...... 631 7.2.166Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_10)—Offset 5D4h ...... 631 7.2.167Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_11)—Offset 5D8h ...... 631 7.2.168Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_11)—Offset 5DCh ...... 631 7.2.169Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_12)—Offset 5E0h...... 632 7.2.170Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_12)—Offset 5E4h...... 632 7.2.171Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_13)—Offset 5E8h...... 632 7.2.172Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_13)—Offset 5ECh ...... 632 7.2.173Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_14)—Offset 5F0h...... 632 7.2.174Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_14)—Offset 5F4h...... 632 7.2.175Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_15)—Offset 5F8h...... 632 7.2.176Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_15)—Offset 5FCh...... 632 7.2.177Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_16)—Offset 600h...... 632 7.2.178Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_16)—Offset 604h...... 633 7.2.179Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_17)—Offset 608h...... 633 7.2.180Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_17)—Offset 60Ch ...... 633 7.2.181Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_18)—Offset 610h...... 633 7.2.182Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_18)—Offset 614h...... 633 7.2.183Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_19)—Offset 618h...... 633 7.2.184Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_19)—Offset 61Ch ...... 633 7.2.185Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_20)—Offset 620h...... 633 7.2.186Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_20)—Offset 624h...... 633 7.2.187Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_21)—Offset 628h...... 634 7.2.188Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_21)—Offset 62Ch ...... 634 7.2.189Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_22)—Offset 630h...... 634 7.2.190Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_22)—Offset 634h...... 634 7.2.191Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_23)—Offset 638h...... 634 7.2.192Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_23)—Offset 63Ch ...... 634 7.3 GPIO Community 2 Registers Summary...... 634 7.3.1 Family Base Address (FAMBAR)—Offset 8h ...... 636 7.3.2 Pad Base Address (PADBAR)—Offset Ch ...... 636 7.3.3 Miscellaneous Configuration (MISCCFG)—Offset 10h ...... 637 7.3.4 Pad Ownership (PAD_OWN_GPD_0)—Offset 20h...... 638 7.3.5 Pad Ownership (PAD_OWN_GPD_1)—Offset 24h...... 639 7.3.6 Pad Configuration Lock (PADCFGLOCK_GPD_0)—Offset A0h...... 639 7.3.7 Pad Configuration Lock (PADCFGLOCKTX_GPD_0)—Offset A4h ...... 640 7.3.8 Host Software Pad Ownership (HOSTSW_OWN_GPD_0)—Offset D0h ...... 642 7.3.9 GPI Interrupt Status (GPI_IS_GPD_0)—Offset 100h...... 643 7.3.10 GPI Interrupt Enable (GPI_IE_GPD_0)—Offset 120h...... 644 7.3.11 GPI General Purpose Events Status (GPI_GPE_STS_GPD_0)—Offset 140h.... 645 7.3.12 GPI General Purpose Events Enable (GPI_GPE_EN_GPD_0)—Offset 160h ..... 646 7.3.13 Pad Configuration DW0 (PAD_CFG_DW0_GPD_0)—Offset 400h ...... 647 7.3.14 Pad Configuration DW1 (PAD_CFG_DW1_GPD_0)—Offset 404h ...... 649 7.3.15 Pad Configuration DW0 (PAD_CFG_DW0_GPD_1)—Offset 408h ...... 650 7.3.16 Pad Configuration DW1 (PAD_CFG_DW1_GPD_1)—Offset 40Ch ...... 650 7.3.17 Pad Configuration DW0 (PAD_CFG_DW0_GPD_2)—Offset 410h ...... 650 7.3.18 Pad Configuration DW1 (PAD_CFG_DW1_GPD_2)—Offset 414h ...... 651 7.3.19 Pad Configuration DW0 (PAD_CFG_DW0_GPD_3)—Offset 418h ...... 651 7.3.20 Pad Configuration DW1 (PAD_CFG_DW1_GPD_3)—Offset 41Ch ...... 651

332219-002 27 7.3.21 Pad Configuration DW0 (PAD_CFG_DW0_GPD_4)—Offset 420h...... 651 7.3.22 Pad Configuration DW1 (PAD_CFG_DW1_GPD_4)—Offset 424h...... 651 7.3.23 Pad Configuration DW0 (PAD_CFG_DW0_GPD_5)—Offset 428h...... 651 7.3.24 Pad Configuration DW1 (PAD_CFG_DW1_GPD_5)—Offset 42Ch...... 651 7.3.25 Pad Configuration DW0 (PAD_CFG_DW0_GPD_6)—Offset 430h...... 651 7.3.26 Pad Configuration DW1 (PAD_CFG_DW1_GPD_6)—Offset 434h...... 651 7.3.27 Pad Configuration DW0 (PAD_CFG_DW0_GPD_7)—Offset 438h...... 652 7.3.28 Pad Configuration DW1 (PAD_CFG_DW1_GPD_7)—Offset 43Ch...... 652 7.3.29 Pad Configuration DW0 (PAD_CFG_DW0_GPD_8)—Offset 440h...... 652 7.3.30 Pad Configuration DW1 (PAD_CFG_DW1_GPD_8)—Offset 444h...... 652 7.3.31 Pad Configuration DW0 (PAD_CFG_DW0_GPD_9)—Offset 448h...... 652 7.3.32 Pad Configuration DW1 (PAD_CFG_DW1_GPD_9)—Offset 44Ch...... 652 7.3.33 Pad Configuration DW0 (PAD_CFG_DW0_GPD_10)—Offset 450h ...... 652 7.3.34 Pad Configuration DW1 (PAD_CFG_DW1_GPD_10)—Offset 454h ...... 652 7.3.35 Pad Configuration DW0 (PAD_CFG_DW0_GPD_11)—Offset 458h ...... 652 7.3.36 Pad Configuration DW1 (PAD_CFG_DW1_GPD_11)—Offset 45Ch...... 653 7.4 GPIO Community 3 Registers Summary ...... 653 7.4.1 Family Base Address (FAMBAR)—Offset 8h ...... 656 7.4.2 Pad Base Address (PADBAR)—Offset Ch...... 656 7.4.3 Miscellaneous Configuration (MISCCFG)—Offset 10h...... 657 7.4.4 Pad Ownership (PAD_OWN_GPP_F_0)—Offset 20h ...... 658 7.4.5 Pad Ownership (PAD_OWN_GPP_F_1)—Offset 24h ...... 660 7.4.6 Pad Ownership (PAD_OWN_GPP_F_2)—Offset 28h ...... 660 7.4.7 Pad Ownership (PAD_OWN_GPP_G_0)—Offset 30h...... 660 7.4.8 Pad Configuration Lock (PADCFGLOCK_GPP_F)—Offset A0h ...... 661 7.4.9 Pad Configuration Lock (PADCFGLOCKTX_GPP_F)—Offset A4h ...... 663 7.4.10 Pad Configuration Lock (PADCFGLOCK_GPP_G)—Offset A8h ...... 664 7.4.11 Pad Configuration Lock (PADCFGLOCKTX_GPP_G)—Offset ACh...... 664 7.4.12 Host Software Pad Ownership (HOSTSW_OWN_GPP_F)—Offset D0h ...... 664 7.4.13 Host Software Pad Ownership (HOSTSW_OWN_GPP_G)—Offset D4h...... 666 7.4.14 GPI Interrupt Status (GPI_IS_GPP_F)—Offset 100h ...... 666 7.4.15 GPI Interrupt Status (GPI_IS_GPP_G)—Offset 104h ...... 668 7.4.16 GPI Interrupt Enable (GPI_IE_GPP_F)—Offset 120h...... 668 7.4.17 GPI Interrupt Enable (GPI_IE_GPP_G)—Offset 124h ...... 670 7.4.18 GPI General Purpose Events Status (GPI_GPE_STS_GPP_F)—Offset 140h..... 670 7.4.19 GPI General Purpose Events Status (GPI_GPE_STS_GPP_G)—Offset 144h .... 672 7.4.20 GPI General Purpose Events Enable (GPI_GPE_EN_GPP_F)—Offset 160h ...... 672 7.4.21 GPI General Purpose Events Enable (GPI_GPE_EN_GPP_G)—Offset 164h...... 673 7.4.22 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_0)—Offset 400h ...... 673 7.4.23 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_0)—Offset 404h ...... 676 7.4.24 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_1)—Offset 408h ...... 677 7.4.25 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_1)—Offset 40Ch...... 677 7.4.26 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_2)—Offset 410h ...... 677 7.4.27 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_2)—Offset 414h ...... 677 7.4.28 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_3)—Offset 418h ...... 677 7.4.29 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_3)—Offset 41Ch...... 677 7.4.30 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_4)—Offset 420h ...... 677 7.4.31 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_4)—Offset 424h ...... 677 7.4.32 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_5)—Offset 428h ...... 677 7.4.33 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_5)—Offset 42Ch...... 678 7.4.34 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_6)—Offset 430h ...... 678 7.4.35 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_6)—Offset 434h ...... 678 7.4.36 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_7)—Offset 438h ...... 678 7.4.37 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_7)—Offset 43Ch...... 678 7.4.38 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_8)—Offset 440h ...... 678

28 332219-002

7.4.39 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_8)—Offset 444h ...... 678 7.4.40 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_9)—Offset 448h ...... 678 7.4.41 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_9)—Offset 44Ch ...... 678 7.4.42 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_10)—Offset 450h...... 679 7.4.43 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_10)—Offset 454h...... 679 7.4.44 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_11)—Offset 458h...... 679 7.4.45 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_11)—Offset 45Ch...... 679 7.4.46 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_12)—Offset 460h...... 679 7.4.47 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_12)—Offset 464h...... 679 7.4.48 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_13)—Offset 468h...... 679 7.4.49 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_13)—Offset 46Ch...... 679 7.4.50 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_14)—Offset 470h...... 679 7.4.51 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_14)—Offset 474h...... 680 7.4.52 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_15)—Offset 478h...... 680 7.4.53 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_15)—Offset 47Ch...... 680 7.4.54 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_16)—Offset 480h...... 680 7.4.55 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_16)—Offset 484h...... 680 7.4.56 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_17)—Offset 488h...... 680 7.4.57 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_17)—Offset 48Ch...... 680 7.4.58 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_18)—Offset 490h...... 680 7.4.59 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_18)—Offset 494h...... 680 7.4.60 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_19)—Offset 498h...... 681 7.4.61 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_19)—Offset 49Ch...... 681 7.4.62 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_20)—Offset 4A0h...... 681 7.4.63 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_20)—Offset 4A4h...... 681 7.4.64 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_21)—Offset 4A8h...... 681 7.4.65 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_21)—Offset 4ACh ...... 681 7.4.66 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_22)—Offset 4B0h...... 681 7.4.67 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_22)—Offset 4B4h...... 681 7.4.68 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_23)—Offset 4B8h...... 681 7.4.69 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_23)—Offset 4BCh ...... 682 7.4.70 Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_0)—Offset 4C4h...... 682 7.4.71 Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_1)—Offset 4C8h...... 682 7.4.72 Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_1)—Offset 4CCh...... 682 7.4.73 Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_2)—Offset 4D0h...... 682 7.4.74 Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_2)—Offset 4D4h...... 682 7.4.75 Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_3)—Offset 4D8h...... 682 7.4.76 Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_3)—Offset 4DCh ...... 682 7.4.77 Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_4)—Offset 4E0h ...... 682 7.4.78 Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_4)—Offset 4E4h ...... 683 7.4.79 Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_5)—Offset 4E8h ...... 683 7.4.80 Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_5)—Offset 4ECh...... 683 7.4.81 Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_6)—Offset 4F0h ...... 683 7.4.82 Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_6)—Offset 4F4h ...... 683 7.4.83 Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_7)—Offset 4F8h ...... 683 7.4.84 Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_7)—Offset 4FCh ...... 683 8SMBus Interface...... 685 8.1 SMBus Configuration Registers Summary ...... 685 8.1.1 Vendor ID (VID)—Offset 0h ...... 685 8.1.2 Device ID (DID)—Offset 2h...... 686 8.1.3 Command (CMD)—Offset 4h ...... 686 8.1.4 Device Status (DS)—Offset 6h ...... 687 8.1.5 Revision ID (RID)—Offset 8h ...... 688 8.1.6 Programming Interface (PI)—Offset 9h...... 688

332219-002 29 8.1.7 Sub Class Code (SCC)—Offset Ah...... 689 8.1.8 Base Class Code (BCC)—Offset Bh ...... 689 8.1.9 SMBus Memory Base Address_31_0 (SMBMBAR_31_0)—Offset 10h...... 689 8.1.10 SMBus Memory Base Address_63_32 (SMBMBAR_63_32)—Offset 14h ...... 690 8.1.11 SMB Base Address (SBA)—Offset 20h ...... 690 8.1.12 SVID (SVID)—Offset 2Ch ...... 691 8.1.13 SID (SID)—Offset 2Eh...... 691 8.1.14 Interrupt Line (INTLN)—Offset 3Ch ...... 692 8.1.15 Interrupt Pin (INTPN)—Offset 3Dh...... 692 8.1.16 Host Configuration (HCFG)—Offset 40h...... 693 8.1.17 TCO Base Address (TCOBASE)—Offset 50h...... 693 8.1.18 TCO Control (TCOCTL)—Offset 54h ...... 694 8.1.19 SMBus Power Gating (SMBSM)—Offset 80h ...... 694 8.2 SMBus I/O and Memory Mapped I/O Registers Summary...... 695 8.2.1 Host Status Register Address (HSTS)—Offset 0h ...... 696 8.2.2 Host Control Register (HCTL)—Offset 2h ...... 696 8.2.3 Host Command Register (HCMD)—Offset 3h ...... 698 8.2.4 Transmit Slave Address Register (TSA)—Offset 4h ...... 699 8.2.5 Data 0 Register (HD0)—Offset 5h ...... 699 8.2.6 Data 1 Register (HD1)—Offset 6h ...... 699 8.2.7 Host Block Data (HBD)—Offset 7h...... 700 8.2.8 Packet Error Check Data Register (PEC)—Offset 8h ...... 701 8.2.9 Receive Slave Address Register (RSA)—Offset 9h...... 701 8.2.10 Slave Data Register (SD)—Offset Ah ...... 701 8.2.11 Auxiliary Status (AUXS)—Offset Ch ...... 702 8.2.12 Auxiliary Control (AUXC)—Offset Dh ...... 703 8.2.13 SMLINK_PIN_CTL Register (SMLC)—Offset Eh...... 703 8.2.14 SMBUS_PIN_CTL Register (SMBC)—Offset Fh ...... 704 8.2.15 Slave Status Register (SSTS)—Offset 10h ...... 705 8.2.16 Slave Command Register (SCMD)—Offset 11h ...... 705 8.2.17 Notify Device Address Register (NDA)—Offset 14h ...... 706 8.2.18 Notify Data Low Byte Register (NDLB)—Offset 16h ...... 707 8.2.19 Notify Data High Byte Register (NDHB)—Offset 17h...... 707 8.3 SMBus Additional Registers Summary...... 707 8.3.1 TCO Configuration (TCOCFG)—Offset 0h ...... 707 8.3.2 General Control (GC)—Offset Ch ...... 708 9 Additional Configuration Registers...... 711 9.1 DMI Configuration Registers Summary...... 711 9.1.1 DMI Power Management Control (DMIPMCTL)—Offset 2334h ...... 711 9.2 IO Trap Registers Summary ...... 711 9.2.1 Trapped Cycle Register (TRPCYC1)—Offset 1E10h ...... 711 9.2.2 Trapped Write Data Register (TRPWRDATA1)—Offset 1E18h ...... 712 9.3 PCH_PCR Registers Summary...... 712 9.3.1 General Control & Function Disable (GCFD)—Offset 3418h...... 712 9.4 RTC Configuration Registers Summary...... 713 9.4.1 RTC Configuration (RC)—Offset 3400h...... 713

30 332219-002

Tables 1-1 Summary of UART PCI Configuration Registers...... 33 1-2 Summary of UART Memory Mapped Registers ...... 43 1-3 Summary of UART Additional Registers ...... 64 1-4 Summary of UART DMA Controller Registers ...... 72 2-1 Summary of Generic SPI PCI Configuration Registers ...... 103 2-2 Summary of Generic SPI (GSPI) Memory Mapped Registers ...... 112 2-3 Summary of Generic SPI (GSPI) Additional Registers ...... 119 2-4 Summary of Generic SPI (GSPI) DMA Controller Registers ...... 129 3-1 Summary of EMMC PCI Configuration Registers...... 159 3-2 Summary of EMMC Memory Mapped Registers ...... 172 3-3 Summary of EMMC Additional Registers ...... 212 4-1 Summary of SDXC PCI Configuration Registers ...... 225 4-2 Summary of SDXC Memory Mapped Registers...... 238 4-3 Summary of SDXC Additional Registers ...... 277 5-1 Summary of I2C PCI Configuration Registers ...... 289 5-2 Summary of I2C Memory Mapped Registers...... 301 5-3 Summary of I2C Additional Registers ...... 328 5-4 Summary of I2C DMA Controller Registers...... 338 6-1 Summary of GPIO Community 0 Registers...... 369 6-2 Summary of GPIO Community 1 Registers...... 410 6-3 Summary of GPIO Community 2 Registers...... 493 6-4 Summary of GPIO Community 3 Registers...... 512 7-1 Summary of GPIO Community 0 Registers...... 535 7-2 Summary of GPIO Community 1 Registers...... 575 7-3 Summary of GPIO Community 2 Registers...... 634 7-4 Summary of GPIO Community 3 Registers...... 653 8-1 Summary of SMBus Configuration Registers...... 685 8-2 Summary of SMBus I/O and Memory Mapped I/O Registers ...... 695 8-3 Summary of SMBus Additional Registers ...... 707 9-1 Summary of DMI Configuration Registers ...... 711 9-2 Summary of IO Trap Registers...... 711 9-3 Summary of PCH_PCR Registers ...... 712 9-4 Summary of RTC Configuration Registers ...... 713

332219-002 31 Revision History

Document Revision Description Revision Date Number Number

332219-001 001 • Initial release. March 2015 • Updated Tables 1-1, 2-1, 4-1 and 5-1. • Updated Sections 1.1.1, 2.1.1, 4.1.1 and 5.1.1. 332219-002 002 June 2015 • Updated chapters 6 and 7. • Added chapters 8 and 9. § §

32 332219-002

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1 UART Interface (D30:F0/F1 and D25:F0)

1.1 UART PCI Configuration Registers Summary

Table 1-1. Summary of UART PCI Configuration Registers

Offset Offset Register Name (ID)—Offset Default Value Start End

9D278086h / LP 9D288086h / LP 9D668086h / LP 0h 3h Device ID and Vendor ID Register (DEVVENDID)—Offset 0h A1278086h / H A1288086h / H A1668086h / H

4h 7h Status and Command (STATUSCOMMAND)—Offset 4h 100000h

8h Bh Revision ID and Class Code (REVCLASSCODE)—Offset 8h 0h

Cache Line Latency Header and BIST (CLLATHEADERBIST)—Offset Ch Fh 0h Ch

10h 13h Base Address Register (BAR)—Offset 10h 0h

14h 17h Base Address Register High (BAR_HIGH)—Offset 14h 0h

18h 1Bh Base Address Register 1 (BAR1)—Offset 18h 0h

1Ch 1Fh Base Address Register1 High (BAR1_HIGH)—Offset 1Ch 0h

2Ch 2Fh Subsystem Vendor and Subsystem ID (SUBSYSTEMID)—Offset 2Ch 0h

Expansion ROM Base Address (EXPANSION_ROM_BASEADDR)— 30h 33h 0h Offset 30h

34h 37h Capabilities Pointer (CAPABILITYPTR)—Offset 34h 80h

3Ch 3Fh Interrupt Register (INTERRUPTREG)—Offset 3Ch 100h

80h 83h Power Management Capability ID (POWERCAPID)—Offset 80h 48030001h

84h 87h PME Control and Status (PMECTRLSTATUS)—Offset 84h 8h

1.1.1 Device ID and Vendor ID Register (DEVVENDID)—Offset 0h

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

332219-002 33 UART Interface (D30:F0/F1 and D25:F0)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 DEVICEID VENDORID

Bit Default & Field Name (ID): Description Range Access

9D27h / LP Device ID (DEVICEID): This is a 16-bit value assigned to the controller. 9D28h / LP 9D66h / LP 31:16 A127h / H A128h / H A166h / H RO

8086 Vendor ID (VENDORID): Identifies the manufacturer of the device. 15:0 RO

1.1.2 Status and Command (STATUSCOMMAND)—Offset 4h

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 0

Default: 100000h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000100000000000000000000 RTA BME MSE RMA RSVD RSVD RSVD RSVD RSVD RSVD CAPLIST INTR_STATUS SERR_ENABLE INTR_DISABLE

Bit Default & Field Name (ID): Description Range Access

0h 31:30 Reserved. RO

0h Received Master Abort (RMA): If the completion status received from is UR, this 29 RW/1C bit is set. S/W writes a ‘1’ to this bit to clear it.

0h Received Target Abort (RTA): If the completion status received is CA, this bit is 28 RW/1C set. S/W writes a ‘1’ to this bit to clear it.

0h 27:21 Reserved. RO

1h Capabilities List (CAPLIST): Indicates that the controller contains a capabilities 20 RO pointer list. The first item is pointed to by looking at configuration offset 34h.

34 332219-002

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Bit Default & Field Name (ID): Description Range Access

Interrupt Status (INTR_STATUS): This bit reflects state of interrupt in the device. 0h Only when the Interrupt Disable bit in the command register is a 0 and this Interrupt 19 Status bit is a 1, will the device’s/function’s interrupt message be sent. RO Setting the Interrupt Disable bit to a 1 has no effect on the state of this bit. This bit reflects Legacy interrupt status.

0h 18:11 Reserved. RO

0h Interrupt Disable (INTR_DISABLE): Setting this bit disables INTx assertion. The 10 RW interrupt disabled is legacy INTx# interrupt.

0h 9 Reserved. RO

0h SERR# Enable (SERR_ENABLE): Not implemented 8 RW

0h 7:3 Reserved. RO

0h Bus Master Enable (BME) 2 RW

0h Memory Space Enable (MSE): 0 = Disables memory mapped Configuration space. 1 RW 1 = Enables memory mapped Configuration space.

0h 0 Reserved. RO

1.1.3 Revision ID and Class Code (REVCLASSCODE)—Offset 8h

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RID CLASS_CODES

Bit Default & Field Name (ID): Description Range Access

0h Class Codes (CLASS_CODES): The register is read-only and is used to identify the 31:8 RO generic function of the device.

0h Revision ID (RID): Indicates stepping of the host controller. Refer to Device and 7:0 RO Revision ID table in Vol1 of the EDS for specific value.

332219-002 35 UART Interface (D30:F0/F1 and D25:F0)

1.1.4 Cache Line Latency Header and BIST (CLLATHEADERBIST)—Offset Ch

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD LATTIMER MULFNDEV HEADERTYPE CACHELINE_SIZE

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h Multi Function Device (MULFNDEV): 0 = Single Function Device 23 RO 1 = Multi Function device

0h Header Type (HEADERTYPE): Implements Type 0 Configuration header. 22:16 RO

0h Latency Timer (LATTIMER): Hardwired to 00h. 15:8 RO

0h Cache Line Size (CACHELINE_SIZE) 7:0 RW

1.1.5 Base Address Register (BAR)—Offset 10h

Bits [31:12] indicate the Base Address register. Power-up software can determine how much address space the Interface Module requires by writing a value of all ones to the register and then reading the value back. The register returns zeros in all don't-care address bits, effectively specifying the address space required.

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

36 332219-002

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3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 TYPE BASEADDR PREFETCHABLE SIZEINDICATOR MESSAGE_SPACE

Bit Default & Field Name (ID): Description Range Access

0h Base Address (BASEADDR): Provides system memory base address for the 31:12 RW controller.

0h Size Indicator (SIZEINDICATOR) 11:4 RO

0h Prefetchable (PREFETCHABLE): Indicates that this BAR is not prefetchable. 3 RO

0h Type (TYPE): 00 indicates BAR lies in 32bit address range 2:1 RO 10 Indicates BAR lies in 64 bit address range

0h Memory Space Indicator (MESSAGE_SPACE): ‘0’ Indicates this BAR is present in 0 RO the memory space.

1.1.6 Base Address Register High (BAR_HIGH)—Offset 14h

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 BASEADDR_HIGH

Bit Default & Field Name (ID): Description Range Access

0h Base Address High (BASEADDR_HIGH) 31:0 RW

1.1.7 Base Address Register 1 (BAR1)—Offset 18h

Access Method

332219-002 37 UART Interface (D30:F0/F1 and D25:F0)

Type: CFG Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 TYPE1 BASEADDR1 PREFETCHABLE1 SIZEINDICATOR1 MESSAGE_SPACE1

Bit Default & Field Name (ID): Description Range Access

0h Base Address Register1 (BASEADDR1): This field is present if BAR1 is enabled. 31:12 RW

0h Size Indicator (SIZEINDICATOR1): Always will be zero as minimum size is 4K. 11:4 RO

0h Prefetchable (PREFETCHABLE1): Indicates that this BAR is not prefetchable. 3 RO

0h Type (TYPE1): 00 indicates BAR lies in 32bit address range 2:1 RO 10 Indicates BAR lies in 64 bit address range.

0h MESSAGE_SPACE1 0 RO

1.1.8 Base Address Register1 High (BAR1_HIGH)—Offset 1Ch

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 BASEADDR1_HIGH

38 332219-002

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Bit Default & Field Name (ID): Description Range Access

0h Base Address High 1 (BASEADDR1_HIGH) 31:0 RW

1.1.9 Subsystem Vendor and Subsystem ID (SUBSYSTEMID)— Offset 2Ch

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 SUBSYSTEMID SUBSYSTEMVENDORID

Bit Default & Field Name (ID): Description Range Access

0h Subsystem ID (SUBSYSTEMID): The register, in combination with the Subsystem 31:16 Vendor ID register make it possible for the operating environment to distinguish one RW/O subsystem from the other. This register is a Read Write Once type register.

0h Subsystem Vendor ID (SUBSYSTEMVENDORID): The register, in combination 15:0 with the Subsystem ID register, enables the operating environment to distinguish one RW/O subsystem from the other. This register is a Read Write Once register.

1.1.10 Expansion ROM Base Address (EXPANSION_ROM_BASEADDR)—Offset 30h

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

332219-002 39 UART Interface (D30:F0/F1 and D25:F0)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 EXPANSION_ROM_BASE

Bit Default & Field Name (ID): Description Range Access

0h Expansion ROM Base (EXPANSION_ROM_BASE): Value of 0 indicates no support 31:0 RO for Expansion ROM.

1.1.11 Capabilities Pointer (CAPABILITYPTR)—Offset 34h

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 0

Default: 80h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000010000000 RSVD CAPPTR_POWER

Bit Default & Field Name (ID): Description Range Access

0h 31:8 Reserved. RO

80h Capabilities Pointer (CAPPTR_POWER): Indicates what the next capability is. 7:0 RO This capability points to the PM Capability (0x80) structure.

1.1.12 Interrupt Register (INTERRUPTREG)—Offset 3Ch

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 0

Default: 100h

40 332219-002

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3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000100000000 RSVD INTPIN INTLINE MAX_LAT MIN_GNT

Bit Default & Field Name (ID): Description Range Access

0h Max Latency (MAX_LAT): Value of 0 indicates device has no major requirements 31:24 RO for the settings of latency timers

0h Min Latency (MIN_GNT): Value of 0 indicates device has no major requirements 23:16 RO for the settings of latency timers

0h 15:12 Reserved. RO

1h Interrupt Pin (INTPIN) 11:8 RO

0h Interrupt Line (INTLINE): Used to communicate to software the interrupt line that 7:0 RW the interrupt pin is connected to.

1.1.13 Power Management Capability ID (POWERCAPID)—Offset 80h

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 0

Default: 48030001h

3 2 2 2 1 1 840 1 8 4 0 6 2

01001000000000110000000000000001 RSVD NXTCAP VERSION POWER_CAP PMESUPPORT

Bit Default & Field Name (ID): Description Range Access

9h PME Support (PMESUPPORT) 31:27 RO

0h 26:19 Reserved. RO

332219-002 41 UART Interface (D30:F0/F1 and D25:F0)

Bit Default & Field Name (ID): Description Range Access

3h Version (VERSION): Indicates support for Revision 1.2 of the PCI Power 18:16 RO Management Specification

0h Next Capability (NXTCAP): Points to the next capability structure. This points to 15:8 RO NULL.

1h Power Management Capability (POWER_CAP): Indicates power management 7:0 RO capability.

1.1.14 PME Control and Status (PMECTRLSTATUS)—Offset 84h

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 0

Default: 8h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000001000 RSVD RSVD POWERSTATE NO_SOFT_RESET

Bit Default & Field Name (ID): Description Range Access

0h 31:4 Reserved. RO

1h No Soft Reset (NO_SOFT_RESET): When set, this bit indicates that devices 3 transitioning from D3hot to D0 because of PowerState commands do not perform an RO internal reset. Configuration Context is preserved.

0h 2 Reserved. RO

Power State (POWERSTATE): This field is used both to determine the current power state and to set a new power state. The values are: 00 = D0 state 0h 1:0 11 = D3HOT state RW Others = Reserved Notes: If software attempts to write a value of 01b or 10b in to this field,the data is discarded and no state change occurs. When in the D3HOT states, interrupts are blocked.

42 332219-002

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1.2 UART Memory Mapped Registers Summary

Table 1-2. Summary of UART Memory Mapped Registers

Offset Offset Default Register Name (ID)—Offset Start End Value

0h 3h Receive Buffer Register (RBR)—Offset 0h 0h

0h 3h Transmit Holding Register (THR)—Offset 0h 0h

0h 3h Divisor Latch Low Register (DLL)—Offset 0h 0h

4h 7h Interrupt Enable Register (IER)—Offset 4h 0h

4h 7h Divisor Latch High (DLH)—Offset 4h 0h

8h Bh FIFO Control Register (FCR)—Offset 8h 1h

Ch Fh Line Control Register (LCR)—Offset Ch 0h

10h 13h MCR (MCR)—Offset 10h 0h

14h 17h LSR (LSR)—Offset 14h 60h

18h 1Bh MSR (MSR)—Offset 18h 0h

1Ch 1Fh SCR (SCR)—Offset 1Ch 0h

30h 33h SRBR_STHR0 (SRBR_STHR0)—Offset 30h 0h

70h 73h FAR (FAR)—Offset 70h 0h

74h 77h TFR (TFR)—Offset 74h 0h

78h 7Bh RFW (RFW)—Offset 78h 0h

7Ch 7Fh USR (USR)—Offset 7Ch 6h

80h 83h TFL (TFL)—Offset 80h 0h

84h 87h RFL (RFL)—Offset 84h 0h

88h 8Bh SRR (SRR)—Offset 88h 0h

8Ch 8Fh SRTS (SRTS)—Offset 8Ch 0h

90h 93h SBCR (SBCR)—Offset 90h 0h

94h 97h SDMAM (SDMAM)—Offset 94h 0h

98h 9Bh SFE (SFE)—Offset 98h 0h

9Ch 9Fh SRT (SRT)—Offset 9Ch 0h

A0h A3h STET (STET)—Offset A0h 0h

A4h A7h HTX (HTX)—Offset A4h 0h

A8h ABh DMASA (DMASA)—Offset A8h 0h

F4h F7h CPR (CPR)—Offset F4h 43F32h

1.2.1 Receive Buffer Register (RBR)—Offset 0h

RBR mode is only available when LCR register, DLAB bit = 0.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

332219-002 43 UART Interface (D30:F0/F1 and D25:F0)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RBR RSVD

Bit Default & Field Name (ID): Description Range Access

0h 31:8 Reserved. RO

Receive Buffer (RBR): Data byte received on the serial input port in UART mode. The data in this register is valid only if the Data Ready (DR) bit in the Line Status Register (LCR) is set. 0h If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before 7:0 the next data arrives, otherwise it is overwritten, resulting in an over-run error. r If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO is preserved, but any incoming data are lost and an over-run error occurs.

1.2.2 Transmit Holding Register (THR)—Offset 0h

THR mode is only available when LCR register, DLAB bit = 0.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 THR RSVD

Bit Default & Field Name (ID): Description Range Access

0h 31:8 Reserved. RO

Transmit Holding Register (THR): Data to be transmitted on the serial output port in UART mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. 0h If FIFOs are disabled (FCR[0] = 0) and THRE is set, writing a single character to the 7:0 THR clears the THRE. Any additional writes to the THR before the THRE is set again WO causes the THR data to be overwritten. If FIFOs are enabled (FCR[0] = 1) and THRE is set, 64 characters of data may be written to the THR before the FIFO is full. Any attempt to write data when the FIFO is full results in the write data being lost.

1.2.3 Divisor Latch Low Register (DLL)—Offset 0h

DLL mode is only available when LCR register, DLAB bit = 1.

Access Method

44 332219-002

UART Interface (D30:F0/F1 and D25:F0)

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 DLL RSVD

Bit Default & Field Name (ID): Description Range Access

0h 31:8 Reserved. RO

Devisor Latch Low (DLL): Lower 8 bits of a 16-bit, read/write Divisor Latch register that contains the baud rate divisor for the UART. This register may be accessed only when the DLAB bit (LCR[7]) is set. 0h The output baud rate is equal to the serial clock frequency divided by sixteen times 7:0 RW the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur.

1.2.4 Interrupt Enable Register (IER)—Offset 4h

IER mode is only available when LCR register [7] (DLAB bit) = 0.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 ELSI RSVD RSVD ETBEI ERBFI PTIME EDSSI

Bit Default & Field Name (ID): Description Range Access

0h 31:8 Reserved. RO

PTIME (PTIME): THRE Interrupt Mode Enable: This is used to enable/disable the 0h 7 generation of THRE Interrupt. RW 0 = disabled 1 = enabled

0h 6:4 Reserved. RO

EDSSI (EDSSI): Enable Modem Status Interrupt: This is used to enable/disable the 0h generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 3 RW 0 = disabled 1 = enabled

332219-002 45 UART Interface (D30:F0/F1 and D25:F0)

Bit Default & Field Name (ID): Description Range Access

ELSI (ELSI): Enable Receiver Line Status Interrupt. This is used to enable/disable 0h the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 2 RW 0 = disabled 1 = enabled

ETBEI (ETBEI): Enable Transmit Holding Register Empty Interrupt. This is used to 0h enable/disable the generation of Transmitter Holding Register Empty Interrupt. This 1 is the third highest priority interrupt. RW 0 = disabled 1 = enabled

ERBFI (ERBFI): Enable Received Data Available Interrupt. This is used to enable/ disable the generation of Received Data Available Interrupt and the Character 0h Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest 0 RW priority interrupts. 0 = disabled 1 = enabled

1.2.5 Divisor Latch High (DLH)—Offset 4h

DLH mode is only available when LCR register [7] (DLAB bit) = 1

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 DLH RSVD

Bit Default & Field Name (ID): Description Range Access

0h 31:8 Reserved. RO

Devisor Latch High (DLH): Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may be 0h accessed only when the DLAB bit (LCR[7]) is set. 7:0 The output baud rate is equal to the serial clock frequency divided by sixteen times RW the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur.

1.2.6 FIFO Control Register (FCR)—Offset 8h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 1h

46 332219-002

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3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000001 TET RCVR RSVD RSVD FIFOE XFIFOR RFIFOR

Bit Default & Field Name (ID): Description Range Access

0h 31:8 Reserved. RO

RCVR Trigger (RCVR): This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. The following trigger levels 0h are supported: 7:6 00 = 1 character in the FIFO WO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full

TX Empty Trigger (TET): This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger 0h levels are supported: 5:4 00 = FIFO empty WO 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full

0h 3 Reserved. RO

0h XMIT FIFO Reset (XFIFOR): This resets the control portion of the transmit FIFO 2 and treatsthe FIFO as empty. WO Note that this bit is 'self-clearing'. It is not necessary to clear this bit.

0h RCVR FIFO Reset (RFIFOR): This resets the control portion of the receive FIFO and 1 treatsthe FIFO as empty. WO Note that this bit is 'self-clearing'. It is not necessary to clear this bit.

FIFOs Enabled (FIFOE): This is used to indicate whether the FIFOs are enabled or 1h 0 disabled. WO 00 = disabled 11 = enabled

1.2.7 Line Control Register (LCR)—Offset Ch

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 EPS PEN DLS STOP DLAB RSVD RSVD BREAK

332219-002 47 UART Interface (D30:F0/F1 and D25:F0)

Bit Default & Field Name (ID): Description Range Access

0h 31:8 Reserved. RO

0h Divisor Latch Access Bit (DLAB): This bit is used to enable reading and writing of 7 the Divisor Latch register(DLL and DLH) to set the baud rate of the UART. This bit RW must be cleared after initialbaud rate setup in order to access other registers

Break Control Bit (BREAK): This is used to cause a break condition to be transmitted to the receiving device. 0h If set to one the serial output is forced to the spacing (logic 0) state. When not in 6 Loopback Mode, as determined by MCR[4], the serial out line is forced low until the RW Break bit is cleared. If SIR_MODE == Enabled and active (MCR[6] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low.

0h 5 Reserved. RO

Even Parity Select (EPS): If UART_16550_COMPATIBLE == NO, then writeable 0h only whenUART is not busy (USR[0] is zero); otherwise always writable, always 4 readable. Thisis used to select between even and odd parity, when parity is enabled RW (PEN set toone). If set to one, an even number of logic 1s is transmitted or checked. If set tozero, an odd number of logic 1s is transmitted or checked.

Parity Enable (PEN): This bit is used to enable and disable parity generation and 0h 3 detection in transmitted and received serial character respectively. RW 0 = parity disabled 1 = parity enabled

Number of Stop Bits (STOP): This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. 0h If set to one and the data bits are set to 5 (LCR[1:0] set to zero) one and a half stop 2 RW bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR[1:0]) is zero, else 2 stop bit

Data Length Select (DLS): This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be 0h selected areas follows: 1:0 00 = 5 bits RW 01 = 6 bits 10 = 7 bits 11 = 8 bits

1.2.8 MCR (MCR)—Offset 10h

Modem Control Register

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RTS AFCE RSVD LoopBack

48 332219-002

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Bit Default & Field Name (ID): Description Range Access

0h 31:6 Reserved. RO

AFCE (AFCE): Auto Flow Control Enable. When FIFOs are enabled and the Auto Flow 0h Control Enable (AFCE) bit is set. The bit is used to help for flow control using external 5 IO pins with the pairing device. RW 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled

LoopBack (LoopBack): LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. 0h Data on the serial out line is held high, while serial data output is looped back to the 4 RW serial in line, internally. In this mode all the interrupts are fully functional. Also, in loop back mode, the modem control input (cts_n,) are disconnected and the modem control output (rts_n) are looped back to the inputs, internally.

0h Reserved 3 RW

0h Reserved 2 RW

RTS (RTS): Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR[5] set to zero), the rts_n signal is 0h set low by programming MCR[1] (RTS) to a high. In Auto Flow Control, (MCR[5] set 1 to one) and FIFOs enable (FCR[0] set to one), the rts_n output is controlled in the RW same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). The rts_n signal is de-asserted when MCR[1] is set low. Note that in Loopback mode (MCR[4] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input.

0h Reserved 0 RW

1.2.9 LSR (LSR)—Offset 14h

Line Status Register

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 60h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000001100000 BI FE PE OE DR RFE THRE TEMT RSVD

332219-002 49 UART Interface (D30:F0/F1 and D25:F0)

Bit Default & Field Name (ID): Description Range Access

0h 31:8 Reserved. RO

RFE (RFE): Receiver FIFO Error bit. This bit is only relevant when FIFOs are enabled (FCR[0] set to one). This is used to indicate if there is at least one parity error, 0h framing error, or break indication in the FIFO. 7 0 = no error in RX FIFO RW 1 = error in RX FIFO This bit is cleared when the LSR is read and the character with the error is at the top of the receiver FIFO and there are no subsequent errors in the FIFO

TEMT (TEMT): Transmitter Empty bit. If FIFOs enabled(FCR[0] set to one), this bit is 1h set whenever the Transmitter Shift Register and the FIFO are both empty. If FIFOs 6 RW are disabled, this bit is set whenever the Transmitter Holding Register and the Transmitter Shift Register are both empty.

THRE (THRE): Transmit Holding Register Empty bit. If THRE mode is disabled (IER[7] set to zero) and regardless of FIFO's being implemented/enabled or not, this bit indicates that the THR or TX FIFO is empty. This bit is set whenever data is transferred from the THR or TX FIFO to the transmitter shift register and no new data 1h has been written to the THR or TX FIFO. This also causes a THRE Interrupt to occur, if 5 RW the THRE Interrupt is enabled. If both THRE Interrupt and FIFO modes are active (IER[7] set to one and FCR[0] set to one respectively), the functionality is switched to indicate the transmitter FIFO is full, and no longer controls THRE interrupts, which are then controlled by the FCR[5:4] threshold setting

BI (BI): Break Interrupt bit. This is used to indicate the detection of a break sequence on the serial input data. It is set whenever the serial input (sin) is held in a logic '0' state for longer than the sum of start time + data bits + parity + stop bits. A 0h break condition on serial input causes one and only one character, consisting of all 4 zeros, to be received by the UART. RW In the FIFO mode, the character associated with the break condition is carried through the FIFO and is revealed when the character is at the top of the FIFO. Reading the LSR clears the BI bit. In the non-FIFO mode, the BI indication occurs immediately and persists until the LSR is read.

FE (FE): Framing Error bit. This is used to indicate the occurrence of a framing error in the receiver. A framing error occurs when the receiver does not detect a valid STOP bit in the received data. In the FIFO mode, since the framing error is associated with a character received, it is revealed when the character with the framing error is at the top of the FIFO. When 0h a framing error occurs, the UART tries to resynchronize. It does this by assuming that 3 the error was due to the start bit of the next character and then continues receiving RW the other bit i.e. data, and/or parity and stop. It should be noted that the Framing Error (FE) bit(LSR[3]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit(LSR[4]). 0 = no framing error 1 = framing error Reading the LSR clears the FE bit.

PE (PE): Parity Error bit. This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PEN) bit (LCR[3]) is set. In the FIFO mode, since the parity error is associated with a character received, it is revealed when the character 0h with the parity error arrives at the top of the FIFO. It should be noted that the Parity 2 Error (PE) bit (LSR[2]) is set if a break interrupt has occurred, as indicated by Break RW Interrupt (BI) bit (LSR[4]). 0 = no parity error 1 = parity error Reading the LSR clears the PE bit.

OE (OE): Overrun error bit. This is used to indicate the occurrence of an overrun error. This occurs if a new data character was received before the previous data was read. In the non-FIFO mode, the OE bit is set when a new character arrives in the receiver 0h before the previous character was read from the RBR. When this happens, the data in 1 the RBR is overwritten. In the FIFO mode, an overrun error occurs when the FIFO is RW full and anew character arrives at the receiver. The data in the FIFO is retained and the data in the receive shift register is lost. 0 = no overrun error 1 = overrun error Reading the LSR clears the OE bit.

DR (DR): Data Ready bit. This is used to indicate that the receiver contains at least one character in the RBR or the receiver FIFO. 0h 0 = no data ready 0 RW 1 = data ready This bit is cleared when the RBR is read in non-FIFO mode, or when the receiver FIFO is empty, in FIFO mode.

50 332219-002

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1.2.10 MSR (MSR)—Offset 18h

Modem Status Register

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 CTS DCTS RSVD

Bit Default & Field Name (ID): Description Range Access

0h 31:8 Reserved. RO

0h Reserved 7 RO

0h Reserved 6 RO

0h Reserved 5 RO

CTS (CTS): Clear to Send. This is used to indicate the current state of the modem control line cts_n.This bit is the complement of cts_n. When the Clear to Send input 0h (cts_n) is asserted it isan indication that the modem or data set is ready to exchange 4 data with the UART. RO 0 = cts_n input is de-asserted (logic 1) 1 = cts_n input is asserted (logic 0) In Loopback Mode (MCR[4] = 1), CTS is the same as MCR[1] (RTS).

0h Reserved 3 RO

0h Reserved 2 RO

0h Reserved 1 RO

DCTS (DCTS): Delta Clear to Send. This is used to indicate that the modem control line cts_n has changed since the last time the MSR was read. 0 = no change on cts_n since last read of MSR 0h 0 1 = change on cts_n since last read of MSR RO Reading the MSR clears the DCTS bit. In Loopback Mode (MCR[4] = 1), DCTS reflects changes on MCR[1] (RTS).Note, if the DCTS bit is not set and the cts_n signal is asserted (low) and a reset occurs(software or otherwise), then the DCTS bit is set when the reset is removed if the cts_nsignal remains asserted.

1.2.11 SCR (SCR)—Offset 1Ch

Scratchpad Register

Access Method

332219-002 51 UART Interface (D30:F0/F1 and D25:F0)

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 scr RSVD

Bit Default & Field Name (ID): Description Range Access

0h 31:8 Reserved. RO

0h scr (scr): This register is for programmers to use as a temporary storage space. 7:0 RW

1.2.12 SRBR_STHR0 (SRBR_STHR0)—Offset 30h

NOTE: There are a total of 16 Shadow Receive Buffer Registers (SRBR_STHR[15:0]. The register description is the same for all of them. The other registers are at the following offsets: SRBR_STHR1 at offset 34h SRBR_STHR2 at offset 38h SRBR_STHR3 at offset 3Ch ...... SRBR_STHR14 at offset 68h SRBR_STHR15 at offset 6Ch

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD srbr_sthr0

52 332219-002

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Bit Default & Field Name (ID): Description Range Access

0h 31:8 Reserved. RO

srbr_sthr0 (srbr_sthr0): Used as SRBR: This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any 0h incoming data is lost. An overrun error also occurs. 7:0 RW Used as STHR: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost.

1.2.13 FAR (FAR)—Offset 70h

FIFO Access Register

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD srbr_sthr

Bit Default & Field Name (ID): Description Range Access

0h 31:1 Reserved. RO

srbr_sthr (srbr_sthr): Writes have no effect when FIFO_ACCESS == No, always readable. This register isuse to enable a FIFO access mode for testing, so that the receive FIFO can bewritten by the master and the transmit FIFO can be read by the master when FIFOsare implemented and enabled. When FIFOs are not implemented 0h or not enabled itallows the RBR to be written by the master and the THR to be read 0 RW by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion ofthe receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty.

332219-002 53 UART Interface (D30:F0/F1 and D25:F0)

1.2.14 TFR (TFR)—Offset 74h

Transmit FIFO Read

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 tfr RSVD

Bit Default & Field Name (ID): Description Range Access

0h 31:8 Reserved. RO

tfr (tfr): Transmit FIFO Read. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, reading 0h this register gives the data at the top of the transmit FIFO. Each consecutive read 7:0 RW pops the transmit FIFO and gives the next data value that is currently at the top of the FIFO. When FIFOs are not implemented or not enabled, reading this register gives the data in the THR. Reset Value: 0x0

1.2.15 RFW (RFW)—Offset 78h

Receive FIFO Write

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RFFE RFPE RFWD

54 332219-002

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Bit Default & Field Name (ID): Description Range Access

0h Reserved 31:10 na

RFFE (RFFE): Receive FIFO Framing Error. These bits are only valid when FIFO 0h access mode is enabled (FAR[0] is set to one). When FIFOs are enabled, this bit is 9 used to write framing error detection information to the receive FIFO. When FIFOs WO are not implemented or not enabled, this bit is used to write framing error detection information to the RBR.

RFPE (RFPE): Receive FIFO Parity Error. These bits are only valid when FIFO access 0h mode is enabled (FAR[0] is set to one). When FIFOs are enabled, this bit is used to 8 write parity error detection information to the receive FIFO. When FIFOs are not WO implemented or not enabled, this bit is used to write parity error detection information to the RBR.

RFWD (RFWD): Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled(FAR[0] is set to one). When FIFOs are enabled, the data that 0h is written to the RFWD is pushed into the receive FIFO. Each consecutive write 7:0 WO pushes the new data to the next write location in the receive FIFO. When FIFOs are not implemented or not enabled, the data that is written to the RFWD is pushed into the RBR.

1.2.16 USR (USR)—Offset 7Ch

UART Status Register

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 6h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000110 TFE RFF TFNF RFNE RSVD

Bit Default & Field Name (ID): Description Range Access

0h 31:5 Reserved. RO

RFF (RFF): Receive FIFO Full. This is used to indicate that the receive FIFO is 0h completely full. 4 0 = Receive FIFO not full RO 1 = Receive FIFO Full This bit is cleared when the RX FIFO is no longer full.

RFNE (RFNE): Receive FIFO Not Empty. This is used to indicate that the receive 0h FIFO contains one or more entries. 3 0 = Receive FIFO is empty RO 1 = Receive FIFO is not empty This bit is cleared when the RX FIFO is empty.

332219-002 55 UART Interface (D30:F0/F1 and D25:F0)

Bit Default & Field Name (ID): Description Range Access

TFE (TFE): Transmit FIFO Empty. This is used to indicate that the transmit FIFO is 1h completely empty. 2 0 = Transmit FIFO is not empty RO 1 = Transmit FIFO is empty This bit is cleared when the TX FIFO is no longer empty

TFNF (TFNF): Transmit FIFO Not Full. This is used to indicate that the transmit FIFO 1h in not full. 1 0 = Transmit FIFO is full RO 1 = Transmit FIFO is not full This bit is cleared when the TX FIFO is full.

0h Reserved 0 RO

1.2.17 TFL (TFL)—Offset 80h

Transmit FIFO Level

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 tfl RSVD

Bit Default & Field Name (ID): Description Range Access

0h 31:5 Reserved. RO

0h tfl (tfl): Transmit FIFO Level. This is indicates the number of data entries in the 4:0 RO transmit FIFO. Reset Value: 0x0

1.2.18 RFL (RFL)—Offset 84h

Receive FIFO Level

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

56 332219-002

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3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 rfl RSVD

Bit Default & Field Name (ID): Description Range Access

0h 31:5 Reserved. RO

0h rfl (rfl): Receive FIFO Level. This is indicates the number of data entries in the 4:0 RO receive FIFO. Reset Value: 0x0

1.2.19 SRR (SRR)—Offset 88h

Software Reset Register

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 UR XFR RFR RSVD

Bit Default & Field Name (ID): Description Range Access

0h 31:3 Reserved. RO

XFR (XFR): XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR[2]). This can be used to remove the burden on software having to store 0h 2 previously written FCR values (which are pretty static) just to reset the transmit RW FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing'. It is not necessary to clear this bit.

RFR (RFR): RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit 0h (FCR[1]). This can be used to remove the burden on software having to store 1 previously written FCR values (which are pretty static) just to reset the receive FIFO RW This resets the control portion of the receive FIFO and treats the FIFO as empty. Note that this bit is 'self-clearing'. It is not necessary to clear this bit.

0h UR (UR): UART Reset. This asynchronously resets the UART controller and 0 RW synchronously removes the reset assertion.

1.2.20 SRTS (SRTS)—Offset 8Ch

Shadow Request to Send

Access Method

332219-002 57 UART Interface (D30:F0/F1 and D25:F0)

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 srts RSVD

Bit Default & Field Name (ID): Description Range Access

0h 31:1 Reserved. RO

srts (srts): Shadow Request to Send. This is a shadow register for the RTS bit (MCR[1]), this can be used to remove the burden of having to performing a read- modify-write onthe MCR. This is used to directly control the Request to Send (rts_n) output. TheRequest To Send (rts_n) output is used to inform the modem or data set 0h that theDW_apb_uart is ready to exchange data.When Auto RTS Flow Control is not 0 enabled (MCR[5] = 0), the rts_n signal is setlow by programming MCR[1] (RTS) to a RW high.In Auto Flow Control, (MCR[5] = 1) andFIFOs enable (FCR[0] = 1), the rts_n output is controlled in the same way, but isalso gated with the receiver FIFO threshold trigger (rts_n is inactive high whenabove the threshold).Note that in Loopback mode (MCR[4] = 1), the rts_n output is held inactive-highwhile the value of this location is internally looped back to an input.Reset Value: 0x0

1.2.21 SBCR (SBCR)—Offset 90h

Shadow Break Control Bit

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 sbcb RSVD

Bit Default & Field Name (ID): Description Range Access

0h 31:1 Reserved. RO

sbcb (sbcb): Shadow Break Control Register. This is a shadow register for the Break bit (LCR[6]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to 0h the receiving device. 0 RW If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. When in Loopback Mode, the break condition is internally looped back to the receiver.

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1.2.22 SDMAM (SDMAM)—Offset 94h

Shadow DMA Mode

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD sdmam

Bit Default & Field Name (ID): Description Range Access

0h 31:1 Reserved. RO

sdmam (sdmam): Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR[3]). This can be used to remove the burden of having to store the previously 0h written value to the FCR in memory and having to mask this value so that only the 0 RW DMA Mode bit gets updated. 0 = mode 0 1 = mode 1

1.2.23 SFE (SFE)—Offset 98h

Shadow FIFO Enable

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 sfe RSVD

332219-002 59 UART Interface (D30:F0/F1 and D25:F0)

Bit Default & Field Name (ID): Description Range Access

0h 31:1 Reserved. RO

sfe (sfe): Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR[0]). This can be used to remove the burden of having to store the previously 0h written value to the FCR in memory and having to mask this value so that only the 0 RW FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset. Reset Value: 0x0

1.2.24 SRT (SRT)—Offset 9Ch

Shadow RCVR Trigger

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 srt RSVD

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

srt (srt): Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits(FCR[7:6]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the 0h receiver FIFO at which the Received Data Available Interrupt is generated. It also 1:0 determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR[3]) = RW 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full

1.2.25 STET (STET)—Offset A0h

Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits(FCR[5:4]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TXempty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

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Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 stet RSVD

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

stet (stet): Shadow TX Empty Trigger: This is a shadow register for the TX empty trigger bits(FCR[5:4]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. 165 This is used to select the empty 0h threshold level at which the THRE Interrupts are generated when the mode is active. 1:0 RW The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full

1.2.26 HTX (HTX)—Offset A4h

Halt TX

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 htx RSVD

Bit Default & Field Name (ID): Description Range Access

0h 31:1 Reserved. RO

htx (htx): This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0h 0 = Halt TX disabled 0 RW 1 = Halt TX enabled Note, if FIFOs are not enabled, the setting of the halt TX register has no effect on operation.

1.2.27 DMASA (DMASA)—Offset A8h

DMA Software Acknowledge

Access Method

332219-002 61 UART Interface (D30:F0/F1 and D25:F0)

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD dmasa

Bit Default & Field Name (ID): Description Range Access

0h 31:1 Reserved. RO

dmasa (dmasa): This register is use to perform a DMA software acknowledge if a 0h transfer needs to be terminated due to an error condition. For example, if the DMA 0 disables the channel, then the UART should clear its request. This causes the TX WO request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing'. It is not necessary to clear this bit.

1.2.28 CPR (CPR)—Offset F4h

Component Parameter Register

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 43F32h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000001000011111100110010 RSVD RSVD RSVD SHADOW SIR_MODE FIFO_STAT FIFO_MODE DMA_EXTRA AFCE_MODE THRE_MODE FIFO_ACCESS SIR_LP_MODE APB_DATA_WIDTH ADDITIONAL_FEAT UART_ADD_ENCODED_PARAMS

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Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

FIFO_MODE (FIFO_MODE): 0x00 = 0 4h 0x01 = 16 23:16 0x02 = 32 to RO 0x80 = 2048 0x81- 0xff = reserved

0h 15:14 Reserved. RO

1h DMA_EXTRA (DMA_EXTRA): 0 = FALSE 13 RO 1 = TRUE

1h UART_ADD_ENCODED_PARAMS (UART_ADD_ENCODED_PARAMS): 0 = FALSE 12 RO 1 = TRUE

1h SHADOW (SHADOW): 0 = FALSE 11 RO 1 = TRUE

1h FIFO_STAT (FIFO_STAT): 0 = FALSE 10 RO 1 = TRUE

1h FIFO_ACCESS (FIFO_ACCESS): 0 = FALSE 9 RO 1 = TRUE

1h ADDITIONAL_FEAT (ADDITIONAL_FEAT): 0 = FALSE 8 RO 1 = TRUE

0h SIR_LP_MODE (SIR_LP_MODE): 0 = FALSE 7 RO 1 = TRUE

0h SIR_MODE (SIR_MODE): 0 = FALSE 6 RO 1 = TRUE

1h THRE_MODE (THRE_MODE): 0 = FALSE 5 RO 1 = TRUE

1h AFCE_MODE (AFCE_MODE): 0 = FALSE 4 RO 1 = TRUE

0h 3:2 Reserved. RO

APB_DATA_WIDTH (APB_DATA_WIDTH): 00 = 8 bits 2h 01 = 16 bits 1:0 RO 10 = 32 bits 11 = reserved

332219-002 63 UART Interface (D30:F0/F1 and D25:F0)

1.0 UART Additional Registers Summary

The registers in this section are memory-mapped registers based on the BAR defined in PCH Configuration space.

Table 1-3. Summary of UART Additional Registers

Offset Offset Default Register Name (ID)—Offset Start End Value

200h 203h CLOCKS (CLOCKS)—Offset 200h 0h

204h 207h RESETS (RESETS)—Offset 204h 0h

210h 213h Active LTR (ACTIVELTR_VALUE)—Offset 210h 800h

214h 217h IDLE LTR (IDLELTR_VALUE)—Offset 214h 800h

218h 21Bh reg_TX_BYTE_COUNT (TX_BYTE_COUNT)—Offset 218h 0h

21Ch 21Fh reg_RX_BYTE_COUNT (RX_BYTE_COUNT)—Offset 21Ch 0h

228h 22Bh SW SCRATCH 0 (SW_SCRATCH_0)—Offset 228h 0h

238h 23Bh reg_CLOCK_GATE (CLOCK_GATE)—Offset 238h 0h

240h 243h reg_REMAP_ADDR_LO (REMAP_ADDR_LO)—Offset 240h 0h

244h 247h reg_REMAP_ADDR_HI (REMAP_ADDR_HI)—Offset 244h 0h

2FCh 2FFh Capabilities (CAPABLITIES)—Offset 2FCh 10h

618h 61Bh UART Byte Address Control (GEN_REGRW7)—Offset 618h 0h

1.1 CLOCKS (CLOCKS)—Offset 200h

Private Clock Configuration

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 n_val m_val clk_en clk_update

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Bit Default & Field Name (ID): Description Range Access

clk_update (clk_update): Update the clock divider after seeting new m and n 0h 31 values. RW 0 – No clock Update 1 – Clock gets updated.

0h N_VAL (n_val): This is the denominator value (N) for the M over N divider logic that 30:16 creates CLK_OUT. RW Used to generate the input clk to the UART.

0h M_VAL (m_val): The numerator value (M) for the M over N divider logic that creates 15:1 RW the CLK_OUT. Used to generate the input clk to the UART.

0h clk_en (clk_en): UART Serial Clock (output of M/N, input to UART) Clock Enable 0 0 – Clock disabled RW 1 – Clock Enabled.

1.2 RESETS (RESETS)—Offset 204h

Software Reset

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 Reset RSVD reset_dma

Bit Default & Field Name (ID): Description Range Access

0h 31:3 Reserved. RO

0h Reset_DMA (reset_dma): Reset the DMA controller 2

Reset_UART (Reset): UART Host Controller reset. Used to reset the UART Host Controller by SW control. All Configuration State and Operational State will be forced to the Default state. There is no timing requirement (SW can assert and de-assert in back to back transactions) 0h This reset does NOT impact the settings by BIOS, the PCI configuration header 1:0 information, DMA channel configuration and interrupt assignment/mapping/etc. Driver should re-initialize registers related to Driver context following an UART host controller reset. 00 = UART Host Controller is in reset (Reset Asserted) 01 = Reserved 10 = Reserved 11 = UART Host Controller is NOT at reset (Reset Released)

1.3 Active LTR (ACTIVELTR_VALUE)—Offset 210h

Access Method

332219-002 65 UART Interface (D30:F0/F1 and D25:F0)

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 800h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000100000000000 RSVD RSVD snoop_value non_snoop_value snoop_requirment snoop_latency_scale non_snoop_requirment non_snoop_latency_scale

Bit Default & Field Name (ID): Description Range Access

Non_Snoop_Requirment (non_snoop_requirment): If the Requirement (bit 15) 0h is clear, that indicates that the device has no LTR requirement for this type of traffic 31 (i.e. it can wait for service indefinitely). If the 10-bit latency value is zero it indicates RO that the device cannot tolerate any delay and needs the best possible service/ response time.

0h 30:29 Reserved. RO

Non_Snoop_latency_scale (non_snoop_latency_scale): Support for codes 010 0h (1us) or 011 (32us) for Snoop Latency Scale (1us -> 32ms total span) only. Writes to 28:26 RO this CSR which don?t match those values will be dropped completely, next read will return previous value.

0h Non_Snoop_value (non_snoop_value): 10-bit latency value 25:16 RO

Snoop_Requirment (snoop_requirment): If the Requirement (bit 15) is clear, 0h that indicates that the device has no LTR requirement for this type of traffic (i.e. it 15 can wait for service indefinitely). If the 10-bit latency value is zero it indicates that RW the device cannot tolerate any delay and needs the best possible service/response time.

0h 14:13 Reserved. RO

Snoop_latency_scale (snoop_latency_scale): Support for codes 010 (1us) or 2h 011 (32us) for Snoop Latency Scale(1us -> 32ms total span) only. Writes to this CSR 12:10 RW which don?t match those values will be dropped completely, next read will return previous value.

0h Snoop_value (snoop_value): 10-bit latency value 9:0 RW

1.4 IDLE LTR (IDLELTR_VALUE)—Offset 214h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 800h

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3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000100000000000 RSVD RSVD snoop_value non_snoop_value snoop_requirment snoop_latency_scale non_snoop_requirment non_snoop_latency_scale

Bit Default & Field Name (ID): Description Range Access

Non_Snoop_Requirment (non_snoop_requirment): If the Requirement (bit 15) 0h is clear, that indicates that the device has no LTR requirement for this type of traffic 31 (i.e. it can wait for service indefinitely). If the 10-bit latency value is zero it indicates RO that the device cannot tolerate any delay and needs the best possible service/ response time.

0h 30:29 Reserved. RO

Non_Snoop_latency_scale (non_snoop_latency_scale): Support for codes 010 0h 28:26 (1us) or 011 (32us) for Snoop Latency Scale (1us -> 32ms total span) only. Writes to RO this CSR which don?t match those values will be dropped completely, next read will return previous value.

0h Non_Snoop_value (non_snoop_value): 10-bit latency value 25:16 RO

Snoop_Requirment (snoop_requirment): If the Requirement (bit 15) is clear, 0h that indicates that the device has no LTR requirement for this type of traffic (i.e. it 15 can wait for service indefinitely). If the 10-bit latency value is zero it indicates that RW the device cannot tolerate any delay and needs the best possible service/response time.

0h 14:13 Reserved. RO

Snoop_latency_scale (snoop_latency_scale): Support for codes 010 (1us) or 2h 011 (32us) for Snoop Latency Scale(1us -> 32ms total span) only. Writes to this CSR 12:10 RW which don?t match those values will be dropped completely, next read will return previous value.

0h Snoop_value (snoop_value): 10-bit latency value 9:0

1.5 reg_TX_BYTE_COUNT (TX_BYTE_COUNT)—Offset 218h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

332219-002 67 UART Interface (D30:F0/F1 and D25:F0)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD tx_byte_count tx_count_overflow

Bit Default & Field Name (ID): Description Range Access

0h tx_count_overflow (tx_count_overflow): 31 0= count valid RO 1= count overflow/invalid

0h 30:24 Reserved. RO

0h tx_byte_count (tx_byte_count): 24-bit up-counter which counts the number of 23:0 RO TX Bytes on the Serial bus. The Counter is forced to be cleared by software Read.

1.6 reg_RX_BYTE_COUNT (RX_BYTE_COUNT)—Offset 21Ch

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD rx_byte_count rx_count_overflow

Bit Default & Field Name (ID): Description Range Access

0h rx_count_overflow (rx_count_overflow): 0= count valid 31 RO 1= count overflow/invalid

0h 30:24 Reserved. RO

0h rx_byte_count (rx_byte_count): 24-bit up-counter which counts the number of 23:0 RO RX Bytes on the Serial bus. The Counter is forced to be cleared by software Read.

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1.7 SW SCRATCH 0 (SW_SCRATCH_0)—Offset 228h

NOTE: The same registers are available at the following offsets: SW SCRATCH 1: offset 22Ch SW SCRATCH 2: offset 230h SW SCRATCH 3: offset 234h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 SW_Scratch_0

Bit Default & Field Name (ID): Description Range Access

0h reg_SW_Scratch_0 (SW_Scratch_0): Scratch Pad Register for SW to generated 31:0 RW Local DATA for iDMA

1.8 reg_CLOCK_GATE (CLOCK_GATE)—Offset 238h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD sw_ip_clk_ctl sw_dma_clk_ctl

332219-002 69 UART Interface (D30:F0/F1 and D25:F0)

Bit Default & Field Name (ID): Description Range Access

0h 31:4 Reserved. RO

sw_dma_clk_ctl (sw_dma_clk_ctl): DMA Clock Control 0h 00 = Dyanamic Clock Gate Enable 3:2 01 = Reserved 10 = Force iDMA Clock off 11 = Force iDMA Clock on

sw_ip_clk_ctl (sw_ip_clk_ctl): Clock Control 0h 00 = Dyanamic Clock Gate Enable 1:0 01 = Reserved 10 = Force IP Clocks off 11 = Force IP Clocks on

1.9 reg_REMAP_ADDR_LO (REMAP_ADDR_LO)—Offset 240h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 uart_remap_addr_low

Bit Default & Field Name (ID): Description Range Access

0h uart_remap_addr_low (uart_remap_addr_low): Low 32 bits of BAR address 31:0 RW read by SW

1.10 reg_REMAP_ADDR_HI (REMAP_ADDR_HI)—Offset 244h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

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3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 uart_remap_addr_high

Bit Default & Field Name (ID): Description Range Access

0h uart_remap_addr_high (uart_remap_addr_high): High 32 bits of BAR address 31:0 RW read by SW

1.11 Capabilities (CAPABLITIES)—Offset 2FCh

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 10h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000010000 RSVD iDMA_present instance_type instance_number

Bit Default & Field Name (ID): Description Range Access

0h 31:9 Reserved. RO

0h DMA Present (iDMA_present): 0= DMA present 1= DMA not present 8 RO

Instant Type (instance_type):

1h 0000 = IC2 7:4 0001 = UART RO 0010 = SPI 0011 – 1111 = Reserved

0h Isntant Number (instance_number) 3:0 RO

332219-002 71 UART Interface (D30:F0/F1 and D25:F0)

1.12 UART Byte Address Control (GEN_REGRW7)—Offset 618h

This register controls the 16550 8-Bit Addressing Mode. After setting any of the bits in this register, BIOs/SW must immediately issue an MMIO Read transaction to a UARTn BAR0 + Offset Register (For example: 0x0F8, the read data can be disgarded). This MUST BE done in order for the UART 16550 8-bit Legacy Mode to become active.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 GEN_REG_RW7

Bit Default & Field Name (ID): Description Range Access

UART Byte Address Enable (GEN_REG_RW7): Settings: 0 = Inactive (Off) 1 = Active (On) 0h The following bits are assigned to the UART controllers: 31:0 RW Bit 0: UART0 controller Bit 1: UART1 controller Bit 2: UART2 controller Other bits are reserved

1.3 UART DMA Controller Registers Summary

The registers in this section are memory-mapped registers based on the BAR defined in PCH Configuration space.

Table 1-4. Summary of UART DMA Controller Registers

Offset Offset Default Register Name (ID)—Offset Start End Value

800h 803h DMA Transfer Source Address Low (SAR_LO0)—Offset 800h 0h

804h 807h DMA Transfer Source Address High (SAR_HI0)—Offset 804h 0h

808h 80Bh DMA Transfer Destination Address Low (DAR_LO0)—Offset 808h 0h

80Ch 80Fh DMA Transfer Destination Address High (DAR_HI0)—Offset 80Ch 0h

810h 813h Linked List Pointer Low (LLP_LO0)—Offset 810h 0h

814h 817h Linked List Pointer High (LLP_HI0)—Offset 814h 0h

818h 81Bh Control Register Low (CTL_LO0)—Offset 818h 0h

81Ch 81Fh Control Register High (CTL_HI0)—Offset 81Ch 0h

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Table 1-4. Summary of UART DMA Controller Registers (Continued)

Offset Offset Default Register Name (ID)—Offset Start End Value

820h 823h Source Status (SSTAT0)—Offset 820h 0h

828h 82Bh Destination Status (DSTAT0)—Offset 828h 0h

830h 833h Source Status Address Low (SSTATAR_LO0)—Offset 830h 0h

834h 837h Source Status Address High (SSTATAR_HI0)—Offset 834h 0h

838h 83Bh Destination Status Address Low (DSTATAR_LO0)—Offset 838h 0h

83Ch 83Fh Destination Status Address High (DSTATAR_HI0)—Offset 83Ch 0h

840h 843h DMA Transfer Configuration Low (CFG_LO0)—Offset 840h 203h

844h 847h DMA Transfer Configuration High (CFG_HI0)—Offset 844h 0h

848h 84Bh Source Gather (SGR0)—Offset 848h 0h

850h 853h Destination Scatter (DSR0)—Offset 850h 0h

AC0h AC3h Raw Interrupt Status (RawTfr)—Offset AC0h 0h

AC8h ACBh Raw Status for Block Interrupts (RawBlock)—Offset AC8h 0h

AD0h AD3h Raw Status for Source Transaction Interrupts (RawSrcTran)—Offset AD0h 0h

Raw Status for Destination Transaction Interrupts (RawDstTran)—Offset AD8h ADBh 0h AD8h

AE0h AE3h Raw Status for Error Interrupts (RawErr)—Offset AE0h 0h

AE8h AEBh Interrupt Status (StatusTfr)—Offset AE8h 0h

AF0h AF3h Status for Block Interrupts (StatusBlock)—Offset AF0h 0h

AF8h AFBh Status for Source Transaction Interrupts (StatusSrcTran)—Offset AF8h 0h

Status for Destination Transaction Interrupts (StatusDstTran)—Offset B00h B03h 0h B00h

B08h B0Bh Status for Error Interrupts (StatusErr)—Offset B08h 0h

B10h B13h Mask for Transfer Interrupts (MaskTfr)—Offset B10h 0h

B18h B1Bh Mask for Block Interrupts (MaskBlock)—Offset B18h 0h

B20h B23h Mask for Source Transaction Interrupts (MaskSrcTran)—Offset B20h 0h

B28h B2Bh Mask for Destination Transaction Interrupts (MaskDstTran)—Offset B28h 0h

B30h B33h Mask for Error Interrupts (MaskErr)—Offset B30h 0h

B38h B3Bh Clear for Transfer Interrupts (ClearTfr)—Offset B38h 0h

B40h B43h Clear for Block Interrupts (ClearBlock)—Offset B40h 0h

B48h B4Bh Clear for Source Transaction Interrupts (ClearSrcTran)—Offset B48h 0h

B50h B53h Clear for Destination Transaction Interrupts (ClearDstTran)—Offset B50h 0h

B58h B5Bh Clear for Error Interrupts (ClearErr)—Offset B58h 0h

B60h B63h Combined Status register (StatusInt)—Offset B60h 0h

B98h B9Bh DMA Configuration (DmaCfgReg)—Offset B98h 0h

BA0h BA3h DMA Channel Enable (ChEnReg)—Offset BA0h 0h

1.3.1 DMA Transfer Source Address Low (SAR_LO0)—Offset 800h

NOTE: SAR_LO0 is for DMA Channel 0. The same register definition,SAR_LO1, is available for Channel 1 at address 858h. SAR_LO0 (CH0): offset 800h

332219-002 73 UART Interface (D30:F0/F1 and D25:F0)

SAR_LO1 (CH1): offset 858h The starting source address is programmed by software before the DMA channel is enabled, or by an LLI update before the start of the DMA transfer. While the DMA transfer is in progress, this register is updated to reflect the source address of the current transfer.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 SAR_LO

Bit Default & Field Name (ID): Description Range Access

SAR_LO: Current Source Address of DMA transfer.

Updated after each source transfer. The SINC field in the CTL_LO[n]: Control Register determines whether the address increments or is left unchanged on every source transfer throughout the block transfer. When the channel is enabled (i.e. CH_EN is 1), the read back value will reflect the updated source transfer addresses. However, when the channel is disabled, the original programmed value will be reflected when reading this register.

It's important to notice the following: 1. Once the block transfer is in progress (i.e. when channel is enabled), the read- back value correlates with the OCP Read Address that one would see in an OCP tracker. 0h 2. If the read to this register comes during a block transfer, the LAST DMA Read 31:0 RW address sent on the OCP before the register read is what's reflected in the read-back value. 3. If the last DMA read was a burst read (i.e. burst length > 1), the read-back value reflects the first address of the burst read since this is what gets sent on the OCP fabric. 4. If the read to the register occurred after the whole block got transferred, then the channel gets disabled and the returned value would be the original programmed value. 5. Since the read-back value is OCP based, only DW aligned addresses will be reflected (i.e. OCP Byte-Enable values would not be reflected) 6. Based on the above remarks, this value should be used as pseudo DMA read progress indicator when the channel is enabled and not an absolute one.

Decrementing addresses are not supported.

1.3.2 DMA Transfer Source Address High (SAR_HI0)—Offset 804h

NOTE: SAR_HI0 is for DMA Channel 0. The same register definition, SAR_HI1, is available for Channel 1 at address 85Ch. SAR_HI0 (CH0): offset 804h SAR_HI1 (CH1): offset 85Ch The starting source address is programmed by software before the DMA channel is enabled, or by an LLI update before the start of the DMA transfer. While the DMA transfer is in progress, this register is updated to reflect the source address of the current transfer.

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Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 SAR_HI

Bit Default & Field Name (ID): Description Range Access

SAR_HI: Current Source Address of DMA transfer.

Updated after each source transfer. The SINC field in the CTL_LO[n]: Control Register determines whether the address increments or is left unchanged on every source transfer throughout the block transfer. When the channel is enabled (i.e. CH_EN is 1), the read back value will reflect the updated source transfer addresses. However, when the channel is disabled, the original programmed value will be reflected when reading this register.

It's important to notice the following: 1. Once the block transfer is in progress (i.e. when channel is enabled), the read- back value correlates with the OCP Read Address that one would see in an OCP tracker. 0h 2. If the read to this register comes during a block transfer, the LAST DMA Read 31:0 RW address sent on the OCP before the register read is what's reflected in the read-back value. 3. If the last DMA read was a burst read (i.e. burst length > 1), the read-back value reflects the first address of the burst read since this is what gets sent on the OCP fabric. 4. If the read to the register occurred after the whole block got transferred, then the channel gets disabled and the returned value would be the original programmed value. 5. Since the read-back value is OCP based, only DW aligned addresses will be reflected (i.e. OCP Byte-Enable values would not be reflected) 6. Based on the above remarks, this value should be used as pseudo DMA read progress indicator when the channel is enabled and not an absolute one.

Decrementing addresses are not supported

1.3.3 DMA Transfer Destination Address Low (DAR_LO0)—Offset 808h

NOTE: DAR_LO0 is for DMA Channel 0. The same register definition, DAR_LO1, is available for Channel 1 at address 860h. DAR_LO0 (CH0): offset 808h DAR_LO1 (CH1): offset 860h The starting destination address is programmed by software before the DMA channel is enabled, or by an LLI update before the start of the DMA transfer. While the DMA transfer is in progress, this register is updated to reflect the destination address of the current transfer.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

332219-002 75 UART Interface (D30:F0/F1 and D25:F0)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 DAR_LO

Bit Default & Field Name (ID): Description Range Access

DAR_LO: Current Destination Address of DMA transfer.

Updated after each destination transfer. The DINC field in the CTL_LO[n]: Control Register determines whether the address increments or is left unchanged on every destination transfer throughout the block transfer. When the channel is enabled (i.e. CH_EN is 1), the read back value will reflect the updated destination transfer addresses. However, when the channel is disabled, the original programmed value will be reflected when reading this register.

It's important to notice the following: 1. Once the block transfer is in progress (i.e. when channel is enabled), the read- back value correlates with the OCP Write Address that one would see in an OCP tracker. 0h 2. If the read to this register comes during a block transfer, the LAST DMA Write 31:0 RW address sent on the OCP before the register read is what's reflected in the read-back value. 3. If the last DMA write was a burst write (i.e. burst length > 1), the read-back value reflects the first address of the burst write since this is what gets sent on the OCP fabric. 4. If the read to the register occurred after the whole block got transferred, then the channel gets disabled and the returned value would be the original programmed value. 5. Since the read-back value is OCP based, only DW aligned addresses will be reflected (i.e. OCP Byte-Enable values would not be reflected) 6. Based on the above remarks, this value should be used as pseudo DMA write progress indicator when the channel is enabled and not an absolute one.

Decrementing addresses are not supported

1.3.4 DMA Transfer Destination Address High (DAR_HI0)— Offset 80Ch

NOTE: DAR_HI0 is for DMA Channel 0. The same register definition, DAR_HI1, is available for Channel 1 at address 864h. DAR_HI0 (CH0): offset 80Ch DAR_HI1 (CH1): offset 864h The starting destination address is programmed by software before the DMA channel is enabled, or by an LLI update before the start of the DMA transfer. While the DMA transfer is in progress, this register is updated to reflect the destination address of the current transfer.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

76 332219-002

UART Interface (D30:F0/F1 and D25:F0)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 DAR_HI

Bit Default & Field Name (ID): Description Range Access

DAR_HI: Current Destination Address of DMA transfer.

Updated after each destination transfer. The DINC field in the CTL_LO[n]: Control Register determines whether the address increments or is left unchanged on every destination transfer throughout the block transfer. When the channel is enabled (i.e. CH_EN is 1), the read back value will reflect the updated destination transfer addresses. However, when the channel is disabled, the original programmed value will be reflected when reading this register.

It's important to notice the following: 1. Once the block transfer is in progress (i.e. when channel is enabled), the read- back value correlates with the OCP Write Address that one would see in an OCP tracker. 0h 2. If the read to this register comes during a block transfer, the LAST DMA Write 31:0 RW address sent on the OCP before the register read is what's reflected in the read-back value. 3. If the last DMA write was a burst write (i.e. burst length > 1), the read-back value reflects the first address of the burst write since this is what gets sent on the OCP fabric. 4. If the read to the register occurred after the whole block got transferred, then the channel gets disabled and the returned value would be the original programmed value. 5. Since the read-back value is OCP based, only DW aligned addresses will be reflected (i.e. OCP Byte-Enable values would not be reflected) 6. Based on the above remarks, this value should be used as pseudo DMA write progress indicator when the channel is enabled and not an absolute one.

Decrementing addresses are not supported

1.3.5 Linked List Pointer Low (LLP_LO0)—Offset 810h

NOTE: LLP_LO0 is for DMA Channel 0. The same register definition, LLP_LO1, is available for Channel 1 at address 868h. LLP_LO0 (CH0): offset 810h LLP_LO1 (CH1): offset 868h The register needs to be programmed to point to the first Linked List Item (LLI) in memory prior to enabling the channel if block chaining is enabled.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 LOC RSVD

332219-002 77 UART Interface (D30:F0/F1 and D25:F0)

Bit Default & Field Name (ID): Description Range Access

LOC: Starting Address In Memory of next LLI if block chaining is enabled. Note that 0h 31:2 the two LSBs of the starting address are not stored because the address is assumed RW to be aligned to a 32-bit boundary. LLI accesses are always 32-bit accesses and cannot be changed or programmed to anything other than 32-bit.

0h 1:0 Reserved. RO

1.3.6 Linked List Pointer High (LLP_HI0)—Offset 814h

NOTE: LLP_HI0 is for DMA Channel 0. The same register definition, LLP_HI1, is available for Channel 1 at address 86Ch. LLP_HI0 (CH0): offset 814h LLP_LO1 (CH1): offset 86Ch The register needs to be programmed to point to the first Linked List Item (LLI) in memory prior to enabling the channel if block chaining is enabled.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 LOC RSVD

Bit Default & Field Name (ID): Description Range Access

LOC: Starting Address In Memory of next LLI if block chaining is enabled. Note that 0h the two LSBs of the starting address are not stored because the address is assumed 31:2 RW to be aligned to a 32-bit boundary. LLI accesses are always 32-bit accesses and cannot be changed or programmed to anything other than 32-bit.

0h 1:0 Reserved. RO

1.3.7 Control Register Low (CTL_LO0)—Offset 818h

NOTE: CTL_LO0 is for DMA Channel 0. The same register definition, CTL_LO1, is available for Channel 1 at address 870h. LLP_HI0 (CH0): offset 818h LLP_LO1 (CH1): offset 870h This register contains fields that control the DMA transfer. The CTL_HI register is part of the block descriptor (linked list item - LLI) when block chaining is enabled. It can be varied on a block-by-block basis within a DMA transfer when block chaining is enabled. If status write-back is enabled, CTL_HI is written to then control registers location of the LLI in system memory at the end of the block transfer.

Access Method

78 332219-002

UART Interface (D30:F0/F1 and D25:F0)

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 SINC DINC RSVD RSVD RSVD RSVD RSVD TT_FC INT_EN SRC_MSIZE LLP_DST_EN LLP_SRC_EN DEST_MSIZE DST_TR_WIDTH SRC_TR_WIDTH SRC_GATHER_EN DST_SCATTER_EN

Bit Default & Field Name (ID): Description Range Access

0h 31:29 Reserved. RO

0h LLP_SRC_EN: Block chaining is enabled on the source side only if the LLP_SRC_EN 28 RW field is high and LLPn.LOC is non-zero and (LLP_EN == 1)

0h LLP_DST_EN: Block chaining is enabled on the destination side only if the 27 RW LLP_DST_EN field is high and LLPn.LOC is non-zero and (LLP_EN == 1)

0h 26:22 Reserved. RO

TT_FC: The following transfer types are supported. Memory to Memory (00) 0h Memory to Peripheral (01) 21:20 RW Peripheral to Memory (10) Peripheral to Peripheral (11) Flow Control is always assigned to the DMA.

0h 19 Reserved. RO

DST_SCATTER_EN: 0 = Scatter disabled 0h 1 = Scatter enabled 18 RW Scatter on the destination side is applicable only when the CTL_LOn.DINC bit indicates an incrementing address control.

SRC_GATHER_EN: 0 = Gather disabled 0h 1 = Gather enabled 17 RW Gather on the source side is applicable only when the CTL_LOn.SINC bit indicates an incrementing address control.

0h SRC_MSIZE: Number of data items, each of width CTL_LOn.SRC_TR_WIDTH, to be 16:14 RW read from the source.

0h DEST_MSIZE: Number of data items, each of width CTL_LOn.DST_TR_WIDTH, to be 13:11 RW written to the destination.

SINC: Indicates whether to increment or decrement the source address on every 0h source transfer. If the device is fetching data from a source peripheral FIFO with a 10 fixed address, then set this field to No change. RW 0 = Increment 1 = Fixed (No Change)

0h 9 Reserved. RO

332219-002 79 UART Interface (D30:F0/F1 and D25:F0)

Bit Default & Field Name (ID): Description Range Access

DINC: Indicates whether to increment or decrement the destination address on 0h every destination transfer. If your device is writing data to a destination peripheral 8 FIFO with a fixed address, then set this field to No change. RW 0 = Increment 1 = Fixed (No change)

0h 7 Reserved. RO

SRC_TR_WIDTH: BURST_SIZE = (2 ^ MSIZE) 0h 1. Transferred Bytes Per Burst = (BURST_SIZE * TR_WIDTH) 6:4 2. For incrementing addresses and (Transfer_Width < 4 Bytes), the MSIZE RW parameter is ignored since only single transactions are supported (due to OCP limitations)

DST_TR_WIDTH: Destination Transfer Width. BURST_SIZE = (2 ^ MSIZE) 0h 1.Transferred Bytes Per Burst = (BURST_SIZE * TR_WIDTH) 3:1 2.For incrementing addresses and (Transfer_Width < 4 Bytes), the MSIZE RW parameter is ignored since only single transactions are supported (due to OCP limitations)

0h INT_EN: Interrupt Enable Bit. If set, then all interrupt-generating sources are 0 RW enabled.

1.3.8 Control Register High (CTL_HI0)—Offset 81Ch

NOTE: CTL_HI0 is for DMA Channel 0. The same register definition, CTL_HI1, is available for Channel 1 at address 874h. CTL_HI0 (CH0): offset 81Ch CTL_HI1 (CH1): offset 874h This register contains fields that control the DMA transfer. The CTL_HI register is part of the block descriptor (linked list item - LLI) when block chaining is enabled. It can be varied on a block-by-block basis within a DMA transfer when block chaining is enabled.If status write-back is enabled, CTL_HI is written to then control registers location of the LLI in system memory at the end of the block transfer.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 DONE BLOCK_TS CH_CLASS CH_WEIGHT

80 332219-002

UART Interface (D30:F0/F1 and D25:F0)

Bit Default & Field Name (ID): Description Range Access

0h CH_CLASS: A Class of (N_CHNLS-1) is the highest priority, and 0 is the lowest. This 31:29 field must be programmed within 0 to (N_CHNLS-1). RW A programmed value outside this range will cause erroneous behavior.

CH_WEIGHT: Channel Weight : Value of K assigns a weight of (K+1) in the round- robin arbitration between channels of the same class. A value of 0x7FF assigns an arbitration weight of 2048. Since K is from 0 to (2^11-1)=2047, Arbitration Weight ranges from 1 to 2048 **Restrictions : 1. CH_CLASS and CH_WEIGHT cannot be changed on the fly. Changes to either 0h values for ANY channel require that ALL channels be quiescent in order to propagate 28:18 those changes to the read and write arbiters without affecting their functionality. RW 2. Another possible way of achieving the quiescence requirement is to suspend ALL channels before changing the CH_CLASS and CH_WEIGHT. 3. Caution must be taken in descriptor-based (linked-list) multi-block transfers since the LLI.CTL_HI is one of the DW that needs to be read and loaded into the CTL_HI internal register. Hence, user needs to ensure that the CH_CLASS and CH_WEIGHT fields do not change from one descriptor to another nor do they disturb the aforementioned quiescence requirement.

DONE: If status write-back is enabled, the upper word of the control register, CTL_HIn, is written to the control register location of the Linked List Item (LLI) in 0h system memory at the end of the block transfer with the done bit set. 17 Software can poll the LLI CTL_HI.DONE bit to see when a block transfer is complete. RW The LLI CTL_HI.DONE bit should be cleared when the linked lists are set up in memory prior to enabling the channel. The DMA will not transfer the block if the DONE bit in the LLI is not cleared.

BLOCK_TS: Block Transfer Size (in Bytes). Since the DMA is always the flow controller, the user needs to write this field before the channel is enabled in order to indicate the block size. The number programmed into BLOCK_TS indicates the total number of bytes to transfer for every block 0h transfer. 16:0 RW Once the transfer starts (i.e. channel is enabled), the read-back value is the total number of bytes for which Read Commands have already been sent to the source. It doesn?t mean Bytes that are already in the FIFO. However, when the channel is disabled, the original programmed value will be reflected when reading this register. Theoretical Byte Size range is from 0 to (2^17 -1) = (128 KB - 1).

1.3.9 Source Status (SSTAT0)—Offset 820h

NOTE: SSTAT0 is for DMA Channel 0. The same register definition, SSTAT1, is available for Channel 1 at address 878h. SSTAT0 (CH0): offset 820h SSTAT1 (CH1): offset 878h After each block transfer completes, hardware can retrieve the source status information from the address pointed to by the contents of the SSTATARx register. This status information is then stored in the SSTATx register and written out to the SSTATx register location of the LLI before the start of the next block. Note : This register is a temporary placeholder for the source status information on its way to the SSTATx register location of the LLI. The source status information should be retrieved by software from the SSTATx register location of the LLI, and not by a read of this register over the DMA slave interface.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

332219-002 81 UART Interface (D30:F0/F1 and D25:F0)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 SSTAT

Bit Default & Field Name (ID): Description Range Access

SSTAT: Source status information retrieved by hardware from the address pointed to by the contents of the Source Status Address Register. This register is a temporary 0h 31:0 placeholder for the source status information on its way to the SSTATn register RW location of the LLI. The source status information should be retrieved by software from the SSTATn register location of the LLI, and not by a read of this register over the DMA slave interface.

1.3.10 Destination Status (DSTAT0)—Offset 828h

NOTE: DSTAT0 is for DMA Channel 0. The same register definition, DSTAT1, is available for Channel 1 at address 880h. DSTAT0 (CH0): offset 828h DSTAT1 (CH1): offset 880h After the completion of each block transfer, hardware can retrieve the destination status information from the address pointed to by the contents of the DSTATARx register. This status information is then stored in the DSTATx register and written out to the DSTATx register location of the LLI. Note : This register is a temporary placeholder for the destination status information on its way to the DSTATx register location of the LLI. The destination status information should be retrieved by software from the DSTATx register location of the LLI and not by a read of this register over the DMA slave interface.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 DSTAT

Bit Default & Field Name (ID): Description Range Access

DSTAT: Destination status information retrieved by hardware from the address pointed to by the contents of the Destination Status Address Register. This register is 0h a temporary placeholder for the destination status information on its way to the 31:0 RW DSTATn register location of the LLI. The destination status information should be retrieved by software from the DSTATn register location of the LLI and not by a read of this register over the DMA slave interface.

82 332219-002

UART Interface (D30:F0/F1 and D25:F0)

1.3.11 Source Status Address Low (SSTATAR_LO0)—Offset 830h

NOTE: SSTATAR_LO0 is for DMA Channel 0. The same register definition, SSTATAR_LO1, is available for Channel 1 at address 888h. SSTATAR_LO0(CH0): offset 830h SSTATAR_LO1(CH1): offset 888h After the completion of each block transfer, hardware can retrieve the source status information from the address pointed to by the contents of the SSTATARx register.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 SSTATAR_LO

Bit Default & Field Name (ID): Description Range Access

0h SSTATAR_LO: Pointer from where hardware can fetch the source status information, 31:0 which is registered in the SSTATn register and written out to the SSTATn register RW location of the LLI before the start of the next block.

1.3.12 Source Status Address High (SSTATAR_HI0)—Offset 834h

NOTE: SSTATAR_HI0 is for DMA Channel 0. The same register definition, SSTATAR_HI1, is available for Channel 1 at address 88Ch. SSTATAR_HI0(CH0): offset 834h SSTATAR_HI1(CH1): offset 88Ch After the completion of each block transfer, hardware can retrieve the source status information from the address pointed to by the contents of the SSTATARx register.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

332219-002 83 UART Interface (D30:F0/F1 and D25:F0)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 SSTATAR_HI

Bit Default & Field Name (ID): Description Range Access

0h SSTATAR_HI: Pointer from where hardware can fetch the source status information, 31:0 which is registered in the SSTATn register and written out to the SSTATn register RW location of the LLI before the start of the next block.

1.3.13 Destination Status Address Low (DSTATAR_LO0)—Offset 838h

NOTE: DSTATAR_LO0 is for DMA Channel 0. The same register definition, DSTATAR_LO1, is available for Channel 1 at address 890h. DSTATAR_LO0(CH0): offset 838h DSTATAR_LO1(CH1): offset 890h After the completion of each block transfer, hardware can retrieve the destination status information from the address pointed to by the contents of the DSTATARx register.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 DSTATAR_LO

Bit Default & Field Name (ID): Description Range Access

0h DSTATAR_LO: Pointer from where hardware can fetch the destination status 31:0 information, which is registered in the DSTATn register and written out to the DSTATn RW register location of the LLI before the start of the next block.

1.3.14 Destination Status Address High (DSTATAR_HI0)—Offset 83Ch

NOTE: DSTATAR_LO0 is for DMA Channel 0. The same register definition, DSTATAR_HI1, is available for Channel 1 at address 894h. DSTATAR_HI0(CH0): offset 83Ch

84 332219-002

UART Interface (D30:F0/F1 and D25:F0)

DSTATAR_HI1(CH1): offset 894h After the completion of each block transfer, hardware can retrieve the destination status information from the address pointed to by the contents of the DSTATARx register.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 DSTATAR_HI

Bit Default & Field Name (ID): Description Range Access

0h DSTATAR_HI: Pointer from where hardware can fetch the destination status 31:0 information, which is registered in the DSTATn register and written out to the DSTATn RW register location of the LLI before the start of the next block.

1.3.15 DMA Transfer Configuration Low (CFG_LO0)—Offset 840h

NOTE: CFG_LO0 is for DMA Channel 0. The same register definition, CFG_LO1, is available for Channel 1 at address 898h. CFG_LO0(CH0): offset 840h CFG_LO1(CH1): offset 898h This register contains fields that configure the DMA transfer. The channel configuration register remains fixed for all blocks of a multi-block transfer. This Register should be programmed to enabling the channel

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 203h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000001000000011 RSVD RSVD RSVD CH_SUSP CH_DRAIN ALL_NP_WR SS_UPD_EN DS_UPD_EN FIFO_EMPTY DST_OPT_BL SRC_OPT_BL DST_HS_POL SRC_HS_POL RELOAD_DST RELOAD_SRC CTL_HI_UPD_EN HSHAKE_NP_WR DST_BURST_ALIGN SRC_BURST_ALIGN

332219-002 85 UART Interface (D30:F0/F1 and D25:F0)

Bit Default & Field Name (ID): Description Range Access

0h RELOAD_DST: Automatic Destination Reload. The DARn register can be 31 automatically reloaded from its initial value at the end of every block for multi-block RW transfers. A new block transfer is then initiated.

0h RELOAD_SRC: Automatic Source Reload. The SARx register can be automatically 30 reloaded from its initial value at the end of every block for multi-block transfers. A RW new block transfer is then initiated.

0h 29:22 Reserved. RO

SRC_OPT_BL: Optimize Source Burst Length : 0h 0 = Writes will use only BL=1 or BL=(2 ^ SRC_MSIZE) 21 RW 1 = Writes will use (1 <= BL <= (2 ^ SRC_MSIZE)) *** This bit should be set to (0) if Source HW-Handshake is enabled

DST_OPT_BL: Optimize Destination Burst Length : 0h 0 = Writes will use only BL=1 or BL=(2 ^ DST_MSIZE) 20 RW 1 = Writes will use (1 <= BL <= (2 ^ DST_MSIZE)) *** This bit should be set to (0) if Destination HW-Handshake is enabled

0h SRC_HS_POL: Source Handshaking Interface Polarity. 19 0 = Active high RW 1 = Active low

0h DST_HS_POL: Destination Handshaking Interface Polarity. 18 0 = Active high RW 1 = Active low

0h 17:11 Reserved. RO

0h CH_DRAIN: Forces channel FIFO to drain while in suspension. This bit has effect 10 RW only when CH_SUSPEND ia asserted

FIFO_EMPTY: Indicates if there is data left in the channel FIFO. Can be used in 1h conjunction with CFGx.CH_SUSP to cleanly disable a channel. 9 RO 1 = Channel FIFO empty 0 = Channel FIFO not empty

CH_SUSP: Channel Suspend. Suspends all DMA data transfers from the source until this bit is cleared. There is no guarantee that the current transaction will complete. 0h Can also be used in conjunction with CFGx.FIFO_EMPTY to cleanly disable a channel 8 RW without losing any data. 0 = Not suspended. 1 = Suspend DMA transfer from the source.

SS_UPD_EN: Source Status Update Enable. Source status information is fetched 0h only from the location pointed to by the SSTATARn register, stored in the SSTATn 7 RW register and written out to the SSTATn location of the LLI if SS_UPD_EN is high. This bit is ignored if (LLP_EN == 0) or (LLP_WB_EN == 0)

DS_UPD_EN: Destination Status Update Enable. Destination status information is 0h 6 fetched only from the location pointed to by the DSTATARn register, stored in the RW DSTATn register and written out to the DSTATn location of the LLI if DS_UPD_EN is high. This bit is ignored if (LLP_EN == 0) or (LLP_WB_EN == 0)

0h CTL_HI_UPD_EN: CTL_HI Update Enable. If set, the CTL_HI register is written out 5 to the CTL_HIn location of the LLI. This bit is ignored if (LLP_EN == 0) or RW (LLP_WB_EN == 0)

0h 4 Reserved. RO

HSHAKE_NP_WR: 0x1 : Issues Non-Posted writes on HW-Handshake on DMA Write 0h Port 3 0x0 : Issues Posted writes on HW-Handshake on DMA Write Port (Except end-of-block RW writes which will be Non-Posted) This bit must be set to 1 for proper operation

86 332219-002

UART Interface (D30:F0/F1 and D25:F0)

Bit Default & Field Name (ID): Description Range Access

0h ALL_NP_WR: 0x1 : Forces ALL writes to be Non-Posted on DMA Write Port 2 0x0 : Non-Posted Writes will only be used at end of block transfers and in HW- RW Handshake (if HW_NP_WR=1); for all other cases, Posted Writes will be used.

1h SRC_BURST_ALIGN: 0x1 : SRC Burst Transfers are broken at a Burst Length 1 aligned boundary RW 0x0 : SRC Burst Transfers are not broken at a Burst Length aligned boundary

1h DST_BURST_ALIGN: 0x1 : DST Burst Transfers are broken at a Burst Length 0 aligned boundary RW 0x0 : DST Burst Transfers are not broken at a Burst Length aligned boundary

1.3.16 DMA Transfer Configuration High (CFG_HI0)—Offset 844h

NOTE: CFG_HI0 is for DMA Channel 0. The same register definition, CFG_HI1, is available for Channel 1 at address 89Ch. CFG_HI0(CH0): offset 844h CFG_HI1(CH1): offset 89Ch This register contains fields that configure the DMA transfer. The channel configuration register remains fixed for all blocks of a multi-block transfer. This Register should be programmed to enabling the channel

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD DST_PER SRC_PER RD_ISSUE_THD WR_ISSUE_THD

Bit Default & Field Name (ID): Description Range Access

0h 31:28 Reserved. RO

0h WR_ISSUE_THD: Write Issue Threshold. Used to relax the issue criterion for Writes. 27:18 Value ranges from 0 to (2^10-1 = 1023) but should not exceed maximum Write RW burst size = (2 ^ DST_MSIZE)*TW.

332219-002 87 UART Interface (D30:F0/F1 and D25:F0)

Bit Default & Field Name (ID): Description Range Access

0h RD_ISSUE_THD: Read Issue Threshold. Used to relax the issue criterion for Reads. 17:8 Value ranges from 0 to (2^10-1 = 1023) but should not exceed maximum Read burst RW size = (2 ^ SRC_MSIZE)*TW.

DST_PER: Destination Peripheral ID : Assigns a hardware handshaking interface (0 - 15) to the destination of channel n. The channel can then communicate with the 0h destination peripheral connected to that interface through the assigned hardware 7:4 handshaking interface. RW NOTE: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface.

SRC_PER: Source Peripheral ID : Assigns a hardware handshaking interface (0 - 15) to the source of channel n. The channel can then communicate with the source 0h peripheral connected to that interface through the assigned hardware handshaking 3:0 interface. RW NOTE: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface.

1.3.17 Source Gather (SGR0)—Offset 848h

NOTE: SGR0 is for DMA Channel 0. The same register definition, SGR1, is available for Channel 1 at address 8A0h. SGR0(CH0): offset 848h SGR1(CH1): offset 8A0h The Source Gather register contains two fields: Source gather count field (SGRx.SGC). Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH between successive gather intervals. This is defined as a gather boundary. Source gather interval field (SGRx.SGI). Specifies the source address increment/decrement in multiples of CTLx.SRC_TR_WIDTH on a gather boundary when gather mode is enabled for the source transfer. The CTLx.SINC field controls whether the address increments or decrements. When the CTLx.SINC field indicates a fixed-address control, then the address remains constant throughout the transfer and the SGRx register is ignored.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 SGI SGC

Bit Default & Field Name (ID): Description Range Access

0h SGC: Source gather count. Source contiguous transfer count between successive 31:20 RW gather boundaries.

0h SGI: Source gather interval. 19:0 RW

88 332219-002

UART Interface (D30:F0/F1 and D25:F0)

1.3.18 Destination Scatter (DSR0)—Offset 850h

NOTE: DSR0 is for DMA Channel 0. The same register definition, DSR1, is available for Channel 1 at address 8A8h. DSR0(CH0): offset 850h DSR1(CH1): offset 8A8h The Destination Scatter register contains two fields: Destination scatter count field (DSRx.DSC) . Specifies the number of contiguous destination transfers of CTLx.DST_TR_WIDTH between successive scatter boundaries. Destination scatter interval field (DSRx.DSI) . Specifies the destination address increment/decrement in multiples of CTLx.DST_TR_WIDTH on a scatter boundary when scatter mode is enabled for the destination transfer. The CTLx.DINC field controls whether the address increments or decrements. When the CTLx.DINC field indicates a fixed address control, then the address remains constant throughout the transfer and the DSRx register is ignored.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 DSI DSC

Bit Default & Field Name (ID): Description Range Access

0h DSC: Destination scatter count. Destination contiguous transfer count between 31:20 RW successive scatter boundaries.

0h DSI: Destination scatter interval. 19:0 RW

1.3.19 Raw Interrupt Status (RawTfr)—Offset AC0h

Interrupt events are stored in these Raw Interrupt Status registers before masking: RawBlock, RawDstTran, RawErr, RawSrcTran, and RawTfr. Each Raw Interrupt Status register has a bit allocated per channel, for example, RawTfr(2) is the Channel 2 raw transfer complete interrupt. Each bit in these registers is cleared by writing a 1 to the corresponding location in the ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran, ClearErr registers The following RAW registers are available in the DMA RawTfr - Raw Status for Transfer Interrupts RawBlock - Raw Status for Block Interrupts Register RawSrcTran - Raw Status for Source Transaction Interrupts Register RawDstTran - Raw Status for Destination Transaction Interrupts Register RawErr - Raw Status for Error Interrupts Register

Access Method

332219-002 89 UART Interface (D30:F0/F1 and D25:F0)

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RAW RSVD

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h RAW: Bit0 for channel 0 and bit 1 for channel 1. 1:0 RO

1.3.20 Raw Status for Block Interrupts (RawBlock)—Offset AC8h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RAW RSVD

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h RAW: Bit 0 for channel 0 and bit 1 for channel 1. 1:0 RO

1.3.21 Raw Status for Source Transaction Interrupts (RawSrcTran)—Offset AD0h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

90 332219-002

UART Interface (D30:F0/F1 and D25:F0)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RAW RSVD

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h RAW: Bit 0 for channel 0 and bit 1 for channel 1. 1:0 RO

1.3.22 Raw Status for Destination Transaction Interrupts (RawDstTran)—Offset AD8h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RAW RSVD

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h RAW: Bit 0 for channel 0 and bit 1 for channel 1. 1:0 RO

1.3.23 Raw Status for Error Interrupts (RawErr)—Offset AE0h

Interrupt events are stored in these Raw Interrupt Status registers before masking: RawBlock, RawDstTran, RawErr, RawSrcTran, and RawTfr. Each Raw Interrupt Status register has a bit allocated per channel, for example, RawTfr(2) is the Channel 2 raw transfer complete interrupt. Each bit in these registers is cleared by writing a 1 to the corresponding location in the ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran, ClearErr registers The following RAW registers are available in the DMA RawTfr - Raw Status for Transfer Interrupts RawBlock - Raw Status for Block Interrupts Register RawSrcTran - Raw Status for Source Transaction Interrupts Register RawDstTran - Raw Status for Destination Transaction Interrupts Register RawErr - Raw Status for Error Interrupts Register

332219-002 91 UART Interface (D30:F0/F1 and D25:F0)

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RAW RSVD

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h RAW: Bit 0 for channel 0 and bit 1 for channel 1. 1:0 RO

1.3.24 Interrupt Status (StatusTfr)—Offset AE8h

All interrupt events from all channels are stored in these Interrupt Status registers after masking: statusBlock, StatusDstTran, StatusErr, StatusSrcTran, and StatusTfr. Each Interrupt Status register has a bit allocated per channel, for example, StatusTfr(2) is the Channel 2 status transfer complete interrupt. The contents of these registers are used to generate the interrupt signals (int or int_n bus, depending on interrupt polarity) leaving the DMA.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD STATUS

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h STATUS: Bit 0 for channel 0 and bit 1 for channel 1. 1:0 RO

92 332219-002

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1.3.25 Status for Block Interrupts (StatusBlock)—Offset AF0h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD STATUS

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h STATUS: Bit 0 for channel 0 and bit 1 for channel 1. 1:0 RO

1.3.26 Status for Source Transaction Interrupts (StatusSrcTran)—Offset AF8h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD STATUS

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h STATUS: Bit 0 is for channel 0 and bit 1 is for channel 1. 1:0 RO

1.3.27 Status for Destination Transaction Interrupts (StatusDstTran)—Offset B00h

Access Method

332219-002 93 UART Interface (D30:F0/F1 and D25:F0)

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD STATUS

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h STATUS: Bit 0 is for channel 0 and bit 1 is for channel 1. 1:0 RO

1.3.28 Status for Error Interrupts (StatusErr)—Offset B08h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD STATUS

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h STATUS: Bit 0 is for channel 0 and bit 1 is for channel 1. 1:0 RO

1.3.29 Mask for Transfer Interrupts (MaskTfr)—Offset B10h

The contents of the Raw Status registers are masked with the contents of the Mask registers: MaskBlock, MaskDstTran, MaskErr, MaskSrcTran, and MaskTfr. Each Interrupt Mask register has a bit allocated per channel, for example, MaskTfr(2) is the mask bit for the Channel 2 transfer complete interrupt. When the source peripheral of DMA channel i is memory, then the source transaction complete interrupt, MaskSrcTran(i), must be masked to prevent an erroneous triggering of an interrupt on the int_combined signal. Similarly, when the destination peripheral of DMA channel i is

94 332219-002

UART Interface (D30:F0/F1 and D25:F0)

memory, then the destination transaction complete interrupt, MaskDstTran(i), must be masked to prevent an erroneous triggering of an interrupt on the int_combined(_n) signal. A channel INT_MASK bit will be written only if the corresponding mask write enable bit in the INT_MASK_WE field is asserted on the same OCP write transfer. This allows software to set a mask bit without performing a read-modified write operation. For example, writing hex 01x1 to the MaskTfr register writes a 1 into MaskTfr(0), while MaskTfr(7:1) remains unchanged. Writing hex 00xx leaves MaskTfr(7:0) unchanged. Writing a 1 to any bit in these registers unmasks the corresponding interrupt, thus allowing the DMA to set the appropriate bit in the Status registers and int_* port signals.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD INT_MASK INT_MASK_WE

Bit Default & Field Name (ID): Description Range Access

0h 31:10 Reserved. RO

0h INT_MASK_WE: 0 = write disabled 9:8 WO 1 = write enabled

0h 7:2 Reserved. RO

0h INT_MASK: 0-mask 1:0 RW 1-unmask

1.3.30 Mask for Block Interrupts (MaskBlock)—Offset B18h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

332219-002 95 UART Interface (D30:F0/F1 and D25:F0)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD INT_MASK INT_MASK_WE

Bit Default & Field Name (ID): Description Range Access

0h 31:10 Reserved. RO

0h INT_MASK_WE: 0 = write disabled 9:8 WO 1 = write enabled

0h 7:2 Reserved. RO

0h INT_MASK: 0-mask 1:0 RW 1-unmask

1.3.31 Mask for Source Transaction Interrupts (MaskSrcTran)— Offset B20h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD INT_MASK INT_MASK_WE

Bit Default & Field Name (ID): Description Range Access

0h 31:10 Reserved. RO

0h INT_MASK_WE: 0 = write disabled 9:8 WO 1 = write enabled

0h 7:2 Reserved. RO

0h INT_MASK: 0-mask 1:0 RW 1-unmask

96 332219-002

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1.3.32 Mask for Destination Transaction Interrupts (MaskDstTran)—Offset B28h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD INT_MASK INT_MASK_WE

Bit Default & Field Name (ID): Description Range Access

0h 31:10 Reserved. RO

0h INT_MASK_WE: 0 = write disabled 9:8 WO 1 = write enabled

0h 7:2 Reserved. RO

0h INT_MASK: 0-mask 1:0 RW 1-unmask

1.3.33 Mask for Error Interrupts (MaskErr)—Offset B30h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD INT_MASK INT_MASK_WE

332219-002 97 UART Interface (D30:F0/F1 and D25:F0)

Bit Default & Field Name (ID): Description Range Access

0h 31:10 Reserved. RO

0h INT_MASK_WE: 0 = write disabled 9:8 WO 1 = write enabled

0h 7:2 Reserved. RO

0h INT_MASK: 0-mask 1:0 RW 1-unmask

1.3.34 Clear for Transfer Interrupts (ClearTfr)—Offset B38h

Each bit in the Raw Status and Status registers is cleared on the same cycle by writing a 1 to the corresponding location in the Clear registers: ClearBlock, ClearDstTran, ClearErr, ClearSrcTran, and ClearTfr. Each Interrupt Clear register has a bit allocated per channel, for example, ClearTfr(2) is the clear bit for the Channel 2 transfer complete interrupt. Writing a 0 has no effect. These registers are not readable.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD CLEAR

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h CLEAR: 0 = no effect 1:0 WO 1 = clear interrupt

1.3.35 Clear for Block Interrupts (ClearBlock)—Offset B40h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

98 332219-002

UART Interface (D30:F0/F1 and D25:F0)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD CLEAR

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h CLEAR: 0 = no effect 1:0 WO 1 = clear interrupt

1.3.36 Clear for Source Transaction Interrupts (ClearSrcTran)— Offset B48h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD CLEAR

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h CLEAR: 0 = no effect 1:0 WO 1 = clear interrupt

1.3.37 Clear for Destination Transaction Interrupts (ClearDstTran)—Offset B50h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

332219-002 99 UART Interface (D30:F0/F1 and D25:F0)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD CLEAR

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h CLEAR: 0 = no effect 1:0 WO 1 = clear interrupt

1.3.38 Clear for Error Interrupts (ClearErr)—Offset B58h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD CLEAR

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h CLEAR: 0 = no effect 1:0 WO 1 = clear interrupt

1.3.39 Combined Status register (StatusInt)—Offset B60h

The contents of each of the five Status registers StatusTfr, StatusBlock, StatusSrcTran, StatusDstTran,StatusErr is ORed to produce a single bit for each interrupt type in the Combined Status register (StatusInt). This register is read-only.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

100 332219-002

UART Interface (D30:F0/F1 and D25:F0)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 TFR ERR DSTT SRCT RSVD BLOCK

Bit Default & Field Name (ID): Description Range Access

0h 31:5 Reserved. RO

0h ERR: OR of the contents of StatusErr register. 4 RO

0h DSTT: OR of the contents of StatusDst register. 3 RO

0h SRCT: OR of the contents of StatusSrcTran register 2 RO

0h BLOCK: OR of the contents of StatusBlock register. 1 RO

0h TFR: OR of the contents of StatusTfr register. 0 RO

1.3.40 DMA Configuration (DmaCfgReg)—Offset B98h

This register is used to enable the DMA, which must be done before any channel activity can begin. If the global channel enable bit is cleared while any channel is still active, then DmaCfgReg.DMA_EN still returns 1 to indicate that there are channels still active until hardware has terminated all activity on all channels, at which point the DmaCfgReg.DMA_EN bit returns 0.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD DMA_EN

Bit Default & Field Name (ID): Description Range Access

0h 31:1 Reserved. RO

0h DMA_EN: 0 = DMA Disabled 0 RW 1 = DMA Enabled

332219-002 101 UART Interface (D30:F0/F1 and D25:F0)

1.3.41 DMA Channel Enable (ChEnReg)—Offset BA0h

This is the DMA Channel Enable Register. If software needs to set up a new channel, then it can read this register in order to find out which channels are currently inactive, it can then enable an inactive channel with the required priority. All bits of this register are cleared to 0 when the global DMA channel enable bit, DmaCfgReg(0), is 0. When the global channel enable bit is 0, then a write to the ChEnReg register is ignored and a read will always read back 0. The channel enable bit, ChEnReg.CH_EN, is written only if the corresponding channel write enable bit, ChEnReg.CH_EN_WE, is asserted on the same OCP write transfer. For example, writing hex 01x1 writes a 1 into ChEnReg(0), while ChEnReg(7:1) remains unchanged. Writing hex 00xx leaves ChEnReg(7:0) unchanged. Note that a read-modified write is not required.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

0 0 0000000000000000000000000000000 0 RSVDRSVD CH_EN_WECH_EN

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h CH_EN_WE: Channel enable write enable. 1:0 WO

0h -1:2 Reserved. RO

CH_EN: Enables/Disables the channel. Setting this bit enables a channel, clearing this bit disables the channel. 0 = Disable the Channel 0h 1 = Enable the Channel 1:0 RW The ChEnReg.CH_EN bit is automatically cleared by hardware to disable the channel after the last OCP transfer of the DMA transfer to the destination has completed. Software can therefore poll this bit to determine when this channel is free for a new DMA transfer.

§ §

102 332219-002

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2 Generic SPI Interface (D30:F2)

2.1 Generic SPI PCI Configuration Registers Summary

Table 2-1. Summary of Generic SPI PCI Configuration Registers

Offset Offset Register Name (ID)—Offset Default Value Start End

9D298086h / LP 9D2A8086h / LP 0h 3h Device ID and Vendor ID Register (DEVVENDID)—Offset 0h A1298086h / H A12A8086h / H

4h 7h Status and Command (STATUSCOMMAND)—Offset 4h 100000h

8h Bh Revision ID and Class Code (REVCLASSCODE)—Offset 8h 118000XXh

Cache Line Latency Header and BIST (CLLATHEADERBIST)—Offset Ch Fh 0h Ch

10h 13h Base Address Register (BAR)—Offset 10h 0h

14h 17h Base Address Register High (BAR_HIGH)—Offset 14h 0h

18h 1Bh Base Address Register 1 (BAR1)—Offset 18h 0h

1Ch 1Fh Base Address Register1 High (BAR1_HIGH)—Offset 1Ch 0h

2Ch 2Fh Subsystem Vendor and Subsystem ID (SUBSYSTEMID)—Offset 2Ch 0h

Expansion ROM base address (EXPANSION_ROM_BASEADDR)— 30h 33h 0h Offset 30h

34h 37h Capabilities Pointer (CAPABILITYPTR)—Offset 34h 80h

3Ch 3Fh Interrupt Register (INTERRUPTREG)—Offset 3Ch 100h

80h 83h PowerManagement Capability ID (POWERCAPID)—Offset 80h 00030001h

84h 87h PME Control and Status (PMECTRLSTATUS)—Offset 84h 8h

2.1.1 Device ID and Vendor ID Register (DEVVENDID)—Offset 0h

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000001000000010000110 DEVICEID VENDORID

332219-002 103 Generic SPI Interface (D30:F2)

Bit Default & Field Name (ID): Description Range Access

9D29h / LP Device Identification (DEVICEID): This is a 16-bit value assigned to the controller 9D2Ah / LP 31:16 A129h / H A12Ah / H RO

8086h Vendor Identification (VENDORID) 15:0 RO Identifies the manufacturer of the device.

2.1.2 Status and Command (STATUSCOMMAND)—Offset 4h

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 2

Default: 100000h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000100000000000000000000 RTA BME MSE RMA RSVD RSVD RSVD RSVD CAPLIST Reserved0 Reserved1 INTR_STATUS SERR_ENABLE INTR_DISABLE

Bit Default & Field Name (ID): Description Range Access

0h Reserved 31:30 RO

0h Received Master Abort (RMA): If the completion status received from is UR, this 29 RW/1C bit is set. S/W writes a ‘1’ to this bit to clear it.

0h Received Target Abort (RTA): If the completion status received is CA, this bit is 28 RW/1C set. S/W writes a ‘1’ to this bit to clear it.

0h Reserved 27:21 RO

1h CAPLIST 20 RO

Interrupt Status (INTR_STATUS): This bit reflects state of interrupt in the device. 0h Only when the Interrupt Disable bit in the command register is a 0 and this Interrupt 19 Status bit is a 1, will the device’s/function’s interrupt message be sent. RO Setting the Interrupt Disable bit to a 1 has no effect on the state of this bit. This bit reflects Legacy interrupt status.

0h 18:11 Reserved. RO

0h Interrupt Disable (INTR_DISABLE): Setting this bit disables INTx assertion. The 10 RW interrupt disabled is legacy INTx# interrupt.

0h 9 Reserved. RO

104 332219-002

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Bit Default & Field Name (ID): Description Range Access

0h SERR# Enable (SERR_ENABLE): Not implemented 8 RW

0h 7:3 Reserved. RO

0h Bus Master Enable (BME) 2 RW

0h Memory Space Enable (MSE): 1 0 = Disables memory mapped Configuration space. RW 1 = Enables memory mapped Configuration space.

0h 0 Reserved. RO

2.1.3 Revision ID and Class Code (REVCLASSCODE)—Offset 8h

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RID CLASS_CODES

Bit Default & Field Name (ID): Description Range Access

0h Class Codes (CLASS_CODES): The register is read-only and is used to identify the 31:8 RO generic function of the device.

0h Revision ID (RID): Indicates stepping of the host controller. Refer to Device and 7:0 RO Revision ID table in Vol1 of the EDS for specific value.

2.1.4 Cache Line Latency Header and BIST (CLLATHEADERBIST)—Offset Ch

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

332219-002 105 Generic SPI Interface (D30:F2)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD LATTIMER MULFNDEV HEADERTYPE CACHELINE_SIZE

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h Multi Function Device (MULFNDEV): 23 0 = Single Function Device RO 1 = Multi Function device

0h Header Type (HEADERTYPE): Implements Type 0 Configuration header. 22:16 RO

0h Latency Timer (LATTIMER) 15:8 RO

0h Cache Line Size (CACHELINE_SIZE) 7:0 RW

2.1.5 Base Address Register (BAR)—Offset 10h

Bits [31:12] indicate the Base Address register. Power-up software can determine how much address space the Interface Module requires by writing a value of all ones to the register and then reading the value back. The register returns zeros in all don't-care address bits, effectively specifying the address space required.

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 TYPE BASEADDR PREFETCHABLE SIZEINDICATOR MESSAGE_SPACE

106 332219-002

Generic SPI Interface (D30:F2)

Bit Default & Field Name (ID): Description Range Access

0h Base Address (BASEADDR): Provides system memory base address for the 31:12 RW controller.

0h SIZEINDICATOR 11:4 RO

0h Prefetchable (PREFETCHABLE): Indicates that this BAR is not prefetchable. 3 RO

0h Type (TYPE): 00 indicates BAR lies in 32bit address range 2:1 RO 10 Indicates BAR lies in 64 bit address range

0h Memory Space Indicator (MESSAGE_SPACE): ‘0’ Indicates this BAR is present in 0 RO the memory space.

2.1.6 Base Address Register High (BAR_HIGH)—Offset 14h

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 BASEADDR_HIGH

Bit Default & Field Name (ID): Description Range Access

0h Base Address High (BASEADDR_HIGH) 31:0 RW

2.1.7 Base Address Register 1 (BAR1)—Offset 18h

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

332219-002 107 Generic SPI Interface (D30:F2)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 TYPE1 BASEADDR1 PREFETCHABLE1 SIZEINDICATOR1 MESSAGE_SPACE1

Bit Default & Field Name (ID): Description Range Access

0h BASEADDR1 31:12 RW

0h SIZEINDICATOR1 11:4 RO

0h Prefetchable (PREFETCHABLE1): Indicates that this BAR is not prefetchable. 3 RO

0h Type (TYPE1): 2:1 00 indicates BAR lies in 32bit address range RO 10 Indicates BAR lies in 64 bit address range.

0h MESSAGE_SPACE1 0 RO

2.1.8 Base Address Register1 High (BAR1_HIGH)—Offset 1Ch

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 BASEADDR1_HIGH

Bit Default & Field Name (ID): Description Range Access

0h BASEADDR1_HIGH 31:0 RW

108 332219-002

Generic SPI Interface (D30:F2)

2.1.9 Subsystem Vendor and Subsystem ID (SUBSYSTEMID)— Offset 2Ch

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 SUBSYSTEMID SUBSYSTEMVENDORID

Bit Default & Field Name (ID): Description Range Access

0h Subsystem ID (SUBSYSTEMID): The register, in combination with the Subsystem 31:16 Vendor ID register make it possible for the operating environment to distinguish one RW/O subsystem from the other. This register is a Read Write Once type register.

0h Subsystem Vendor ID (SUBSYSTEMVENDORID): The register, in combination 15:0 with the Subsystem ID register, enables the operating environment to distinguish one RW/O subsystem from the other. This register is a Read Write Once register.

2.1.10 Expansion ROM base address (EXPANSION_ROM_BASEADDR)—Offset 30h

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 EXPANSION_ROM_BASE

332219-002 109 Generic SPI Interface (D30:F2)

Bit Default & Field Name (ID): Description Range Access

0h Expansion ROM Base (EXPANSION_ROM_BASE) 31:0 RO Value of 0 indicates no support for Expansion ROM.

2.1.11 Capabilities Pointer (CAPABILITYPTR)—Offset 34h

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 2

Default: 80h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000010000000 Reserved0 CAPPTR_POWER

Bit Default & Field Name (ID): Description Range Access

0h Reserved 31:8 RO

80h Capability Pointer (CAPPTR_POWER): Indicates what the next capability is. This 7:0 RO capability points to the PM Capability (0x80) structure.

2.1.12 Interrupt Register (INTERRUPTREG)—Offset 3Ch

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 2

Default: 100h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000100000000 RSVD INTPIN INTLINE MAX_LAT MIN_GNT

110 332219-002

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Bit Default & Field Name (ID): Description Range Access

0h Max Latency (MAX_LAT): Value of 0 indicates device has no major requirements 31:24 RO for the settings of latency timers

0h Min Latency (MIN_GNT): Value of 0 indicates device has no major requirements 23:16 RO for the settings of latency timers

0h 15:12 Reserved. RO

1h Interrupt Pin (INTPIN) 11:8 RO

0h Interrupt Line (INTLINE): Used to communicate to software the interrupt line that 7:0 RW the interrupt pin is connected to.

2.1.13 PowerManagement Capability ID (POWERCAPID)—Offset 80h

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 2

Default: 48030001h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000110000000000000001 RSVD NXTCAP VERSION POWER_CAP PMESUPPORT

Bit Default & Field Name (ID): Description Range Access

0h PME Support (PMESUPPORT) 31:27 RO

0h 26:19 Reserved. RO

3h VERSION: Indicates support for Revision 1.2 of the PCI Power Management 18:16 RO Specification

0h Next Capability (NXTCAP): Points to the next capability structure. This points to 15:8 RO NULL.

1h Power Management Capability (POWER_CAP): Indicates power management 7:0 RO capability.

2.1.14 PME Control and Status (PMECTRLSTATUS)—Offset 84h

Access Method

332219-002 111 Generic SPI Interface (D30:F2)

Type: CFG Register Device: 30 (Size: 32 bits) Function: 2

Default: 8h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000001000 RSVD RSVD POWERSTATE NO_SOFT_RESET

Bit Default & Field Name (ID): Description Range Access

0h 31:4 Reserved. RO

1h No Soft Reset (NO_SOFT_RESET): When set, this bit indicates that devices 3 transitioning from D3hot to D0 because of PowerState commands do not perform an RO internal reset. Configuration Context is preserved.

0h 2 Reserved. RO

Power State (POWERSTATE): This field is used both to determine the current power state and to set a new power state. The values are: 00 = D0 state 0h 11 = D3HOT state 1:0 RW Others = Reserved Notes: If software attempts to write a value of 01b or 10b in to this field,the data is discarded and no state change occurs. When in the D3HOT states, interrupts are blocked.

2.2 Generic SPI (GSPI) Memory Mapped Registers Summary

Table 2-2. Summary of Generic SPI (GSPI) Memory Mapped Registers

Offset Offset Default Register Name (ID)—Offset Start End Value

0h 3h SSP (GSPI) Control Register 0 (SSCR0)—Offset 0h 0h

4h 7h SSP (GSPI) Control Register 1 (SSCR1)—Offset 4h 0h

8h Bh SSP (GSPI) Status Register (SSSR)—Offset 8h 4h

10h 13h SSP (GSPI) Data (SSDR)—Offset 10h 0h

28h 2Bh SSP (GSPI) Time Out (SSTO)—Offset 28h 0h

44h 47h SPI Transmit FIFO (SITF)—Offset 44h 0h

48h 4Bh SPI Receive FIFO (SIRF)—Offset 48h 0h

2.2.1 SSP (GSPI) Control Register 0 (SSCR0)—Offset 0h

All bits must be set to the preferred value before enabling the Enhanced SSP. Note that Writes to reserved bits must be zeroes, and Read values of these bits is undetermined.

112 332219-002

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Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 FRF TIM RIM SSE ECS ACS SCR NCS DSS MOD EDSS RSVD

Bit Default & Field Name (ID): Description Range Access

0h MOD (MOD): Mode Set to 0 - Normal SSP Mode : Full Duplex Serial peripheral 31 interface. RW 1 = reserved

0h ACS (ACS): Audio Clock Select 0 - Clock selection is determined by the NCS and ECS 30 RW bits 1 - reserved

0h Reserved 29 RW

0h 28:24 Reserved. RO

TIM (TIM): Transmit FIFO Under Run Interrupt Mask When set, this bit will mask the Transmit FIFO Under Run (TUR) event from 0h generating an SSP interrupt. The SSSR status register will still indicate that an TUR 23 event has occurred. This bit can be written to at any time (before or after SSP is RW enabled). 0 = Transmit FIFO Under Run(TUR) events will generate an SSP interrupt 1 = TUR events will be masked

RIM (RIM): Receive FIFO Over Run Interrupt Mask When set, this bit will mask the Receive FIFO Over Run (ROR) event from generating 0h an SSP interrupt. The SSSR status register will still indicate that an ROR event has 22 RW occurred. This bit can be written to at any time (before or after SSP is enabled) 0 = receive FIFO Over Run(ROR) events will generate an SSP interrupt 1 = ROR events will be masked

NCS (NCS): Network Clock Select The SSCR0.NCS bit in conjunction with 0h 21 SSCR0.ECS determines which clock is used. RW 0 - Clock selection is determined by ECS bit 1 – Reserved

EDSS (EDSS): Extended Data Size Select The 1-bit extended field is used in conjunction with the data size select SSCR0.DSS bits to select the size of the data 0h 20 transmitted and received by the Enhanced SSP. RW 0 = A zero is prepended to the DSS value which sets the DSS range from 4-16 bits 1 = A one is pre-appended to the DSS value which sets the DSS range from 17-32 bits

0h SCR (SCR): Serial Clock Rate Value (0 to 4095) used to generate transmission rate 19:8 RW of SSP. Serial bit rate = SSP clock/(SCR+1), where SCR is decimal integer.

0h SSE (SSE): Synchronous Serial Port Enable 0 - SSP operation disabled 1 - SSP 7 RW operation enabled

332219-002 113 Generic SPI Interface (D30:F2)

Bit Default & Field Name (ID): Description Range Access

ECS (ECS): External Clock Select: 0 = use On-chip clock (output of M/N Divider) to produce the SSP's serial clock (SSPSCLK). Selects the use of the the output of the M/ 0h N Divider (MBAR0 + 0x800, CLOCK_PARAMS) to create the SSP's serial clock 6 (SSPCLK) RW Note: Setting M=N=1 will provide a pass through of the M/N Divider of the serial clock. See SCR for Serial Clock Rate generation. 1 = Reserved

0h FRF (FRF): Frame Format Set to 00 - Motorola Serial Peripheral Interface (SPI) 5:4 RW 01 - 10 = reserved

0h DSS (DSS): Data Size Select With EDSS as MSB, value+1 gives data size. Values 4 3:0 RW to 32 allowed.

2.2.2 SSP (GSPI) Control Register 1 (SSCR1)—Offset 4h

The Enhanced SSP Control 1 registers contain bit fields that control various SSP functions. Bits must be set to the preferred value before enabling the Enhanced SSP. Note that Writes to reserved bits should be zeroes, and Read value of these bits are undetermined.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 TIE IFS RIE SPH SPO TSRE RSRE RSVD RSVD TRAIL TINTE RWOT

Bit Default & Field Name (ID): Description Range Access

0h Reserved 31 RW

0h Reserved 30 RW

0h Reserved 29:24

0h RWOT (RWOT): Receive With Out Transmit 23 0 = Transmit/Receive mode RW 1 = Receive without transmit mode

0h TRAIL (TRAIL): Trailing Byte 22 0 = Processor based, trailing bytes are handled by processor RW 1 - DMA based, trailing bytes are handled by DMA

0h TSRE (TSRE): Transmit Service Request Enable 21 0 = DMA Service Request is disabled RW 1 = DMA Service Request is enabled

0h RSRE (RSRE): Receive Service Request Enable 20 0 = DMA Service Request is disabled RW 1 = DMA Service Request is enabled

114 332219-002

Generic SPI Interface (D30:F2)

Bit Default & Field Name (ID): Description Range Access

0h TINTE (TINTE): Receiver Time-out Interrupt Enable 0 - Receiver Time-out 19 RW interrupts are disabled 1 - Receiver Time-out interrupts are enabled

0h Reserved 18 RW

0h 17 Reserved. RO

0h IFS (IFS): Invert Frame Signal 0 = Frame signal (Chip Select) is active low 16 RW 1 = Frame signal (Chip Select) is active high

0h R 15 RW

0h Reserved 14 RW

0h 13:6 Reserved. RO

0h Reserved 5 RW

SPH (SPH): Motorola SPI SSPSCLK phase setting 0h 0 = SSPSCLK is inactive one sycle at the start of a frame and cycle at the end of a 4 frame RW 1 = SSPSCLK is inactive for one half cycle at the start of a frame and one cycle at the end of a frame

0h SPO (SPO): Motorola SPI SSPSCLK polarity setting 3 0 = The inactive or idle state of SSPSCLK is low RW 1 = The inactive or idle state of SSPSCLK is high

0h Reserved 2 RW

0h TIE (TIE): Transmit FIFO Interrupt Enable 1 0 = Transmit FIFO level interrupt is disabled RW 1 = Transmit FIFO level interrupt is enabled

0h RIE (RIE): Receive FIFO Interrupt Enable 0 0 = Receive FIFO level interrupt is disabled RW 1 = Receive FIFO level interrupt is enabled

2.2.3 SSP (GSPI) Status Register (SSSR)—Offset 8h

The Enhanced SSP Status registers contain bits that signal overrun errors as well as the Transmit and Receive FIFO service requests. Each of these hardware-detected events signals an Interrupt request to the Interrupt controller. The Status register also contains flags that indicate when the Enhanced SSP is actively transmitting data, when the Transmit FIFO is not full, and when the Receive FIFO is not empty. One Interrupt signal is sent to the Interrupt Controller for each SSP. These events can cause an Interrupt: End-of-Chain, Receiver Time-out, Peripheral Trailing Byte, Receive FIFO overrun, Receive FIFO request, and Transmit FIFO request.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 4h

332219-002 115 Generic SPI Interface (D30:F2)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000100 TFS TNF RFS BSY TUR RNE ROR PINT TINT RSVD RSVD RSVD

Bit Default & Field Name (ID): Description Range Access

0h 31:22 Reserved. RO

TUR (TUR): Transmit FIFO Under Run 0h 0 = Transmit FIFO has not experienced an under run 21 RW1C 1 = Attempted read from the transmit FIFO when the FIFO was empty, request interrupt

0h Reserved 20 RW1C

0h TINT (TINT): Receiver Time-out Interrupt 19 0 = No receiver time-out pending RW1C 1 = Receiver time-out pending

0h PINT (PINT): Peripheral Trailing Byte Interrupt 18 0 - No peripheral trailing byte interrupt pending RW1C 1 - Peripheral trailing byte interrupt pending

0h 17:8 Reserved. RO

0h ROR (ROR): Receive FIFO Overrun 7 0 = Receive FIFO has not experienced an overrun RW1C 1 = Attempted data write to full receive FIFO, request interrupt

0h RFS (RFS): Receive FIFO Service Request 6 0 = Receive FIFO level is at or below RFT threshold (RFT), or SSP disabled RO 1 = Receive FIFO level exceeds RFT threshold (RFT), request interrupt

TFS (TFS): Transmit FIFO Service Request 0h 0 = Transmit FIFO level exceeds the Low Water Mark Transmit FIFO (SITF.LWMTF), or 5 SSP disabled RO 1 = Transmit FIFO level is at or below the Low Water Mark Transmit FIFO (SITF.LWMTF), request interrupt

0h BSY (BSY): SSP Busy 4 0 = SSP is idle or disabled RO 1 = SSP currently transmitting or receiving a frame

0h RNE (RNE): Receive FIOF Not Empty 3 0 = Receive FIFO is empty RO 1 = Receive FIFO is not empty

1h TNF (TNF): Transmit FIFO Not Full 2 0 = Transmit FIFO is full RO 1 = Transmit FIFO is not full

0h 1:0 Reserved. RO

2.2.4 SSP (GSPI) Data (SSDR)—Offset 10h

The Enhanced SSP Data registers are single address locations that Read-Write data transfers can access.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

116 332219-002

Generic SPI Interface (D30:F2)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 DATA

Bit Default & Field Name (ID): Description Range Access

0h DATA (DATA): Data word to be written to/read from transmit/receive FIFO 31:0 RO

2.2.5 SSP (GSPI) Time Out (SSTO)—Offset 28h

The Enhanced SSP Time-Out registers have single bit fields that specify the time-out value used to signal a period of inactivity within the Receive FIFO. Note that Writes to reserved bits must be zeroes, and Read value of these bits are undetermined.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD TIMEOUT

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

TIMEOUT (TIMEOUT): Timeout Value Is the value that defines the timeout interval for the rcv FIFO. The Interval is given by TIMEOUT/Parallel (Bus) Clock Frequency. When the number of samples in the Receive FIFO is less than rcv FIFO trigger threshold level, and no additional data is received, the Timeout timer will decrement. 0h The time-out timer is reset after a new sample is received. 23:0 In DMA Mode of operation this value needs to be set when the Rcv FIFO Trigger RW Threshold is greater than 1 Rcv FIFO Entry (the required MSize (Single Burst) for SSP DMA peripheral transfers) When in PIO mode of operation this value needs to be set when the total transfer size is not a even divison of the Rcv FIFO trigger threshold level. Is such a case the TIMEOUT value is calculated to be greater than the time to transfer the FIFO Entry size at the desired Bit Rate.

2.2.6 SPI Transmit FIFO (SITF)—Offset 44h

The SPI Transmit FIFO register is for writing the water mark for the SPI transmit FIFO and also for reading the number of entries in the SPI transmit FIFO

Access Method

332219-002 117 Generic SPI Interface (D30:F2)

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD RSVD SITFL LWMTF HWMTF

Bit Default & Field Name (ID): Description Range Access

0h 31:22 Reserved. RO

0h SITFL (SITFL): SPI Transmit FIFO Level Number of entries in SPI Transmit FIFO. 21:16 RO

0h 15:14 Reserved. RO

LWMTF (LWMTF): Low Water Mark Transmit FIFO. Set the low water mark of the 0h SPI transmit FIFO. 13:8 6’b000000 = 1 entry RW through 6’b111111 = 64 entries

0h 7:6 Reserved. RO

HWMTF (HWMTF): High Water Mark Transmit FIFO. Set the high water mark of the 0h SPI transmit FIFO. 5:0 6’b000000 = 1 entry RW through 6’b111111 = 64 entries

2.2.7 SPI Receive FIFO (SIRF)—Offset 48h

The SPI Receive FIFO register is for writing the water mark for the SPI receive FIFO and also for reading the number of entries in the SPI receive FIFO

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD SIRFL WMRF

118 332219-002

Generic SPI Interface (D30:F2)

Bit Default & Field Name (ID): Description Range Access

0h 31:14 Reserved. RO

0h SIRFL (SIRFL): SPI Receive FIFO Level Number of entries in SPI Receive FIFO. 13:8 RO

0h 7:6 Reserved. RO

WMRF (WMRF): Water Mark Receive FIFO. Set the water mark of the SPI receive 0h FIFO. 5:0 6’b000000 = 1 entry RW through 6’b111111 = 64 entries

2.3 Generic SPI (GSPI) Additional Registers Summary

The registers in this section are memory mapped registers based on the BAR defined in PCI configuration space.

Table 2-3. Summary of Generic SPI (GSPI) Additional Registers

Offset Offset Default Register Name (ID)—Offset Start End Value

200h 203h CLOCKS (CLOCKS)—Offset 200h 0h

204h 207h RESETS (RESETS)—Offset 204h 0h

210h 213h ACTIVE LTR (ACTIVELTR_VALUE)—Offset 210h 800h

214h 217h Idle LTR Value (IDLELTR_VALUE)—Offset 214h 800h

218h 21Bh TX Bit Count (TX_BIT_COUNT)—Offset 218h 0h

21Ch 21Fh Rx Bit Count (RX_BIT_COUNT)—Offset 21Ch 0h

220h 223h reg_SSP_REG (SSP_REG)—Offset 220h 0h

224h 227h SPI CS CONTROL (SPI_CS_CONTROL)—Offset 224h 1000h

228h 22Bh SW SCRATCH [3:0] (SW_SCRATCH)—Offset 228h 0h

238h 23Bh Clock Gate (CLOCK_GATE)—Offset 238h 0h

240h 243h Remap Address Low (REMAP_ADDR_LO)—Offset 240h 0h

244h 247h Remap Address High (REMAP_ADDR_HI)—Offset 244h 0h

250h 253h Delay Rx Clock (DEL_RX_CLK)—Offset 250h 0h

2FCh 2FFh Capabilities (CAPABLITIES)—Offset 2FCh 1E20h

2.3.1 CLOCKS (CLOCKS)—Offset 200h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

332219-002 119 Generic SPI Interface (D30:F2)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 N_VAL M_VAL CLK_EN CLK_UPDATE

Bit Default & Field Name (ID): Description Range Access

Clock Update (CLK_UPDATE): Update the clock divider after seeing new m and n 0h values 31 RW 0 = No clock Update. 1 – Clock gets updated.

0h N_VAL (N_VAL): n value for the m over n divider 30:16 RW

0h M_Value (M_VAL): m value for the m over n divider. 15:1 RW

0h Clock Enable (CLK_EN): Clock Enable of the m over n divider 0 0 = Clock disabled RW 1 = Clock Enabled.

2.3.2 RESETS (RESETS)—Offset 204h

Software reset

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RESET RESET_DMA

120 332219-002

Generic SPI Interface (D30:F2)

Bit Default & Field Name (ID): Description Range Access

0h 31:3 Reserved. RO

0h DMA Reset (RESET_DMA): DMA Software Reset Control 2 0 = DMA is in reset (Reset Asserted) 1 = DMA is NOT at reset (Reset Released)

Host Controller reset (RESET): Used to reset the Host Controller by SW control. All SSP Configuration State and Operational State will be forced to the Default state. There is no timing requirement (SW can assert and de-assert in back to back 0h transactions) 1:0 00 = Host Controller is in reset (Reset Asserted) 01 = Reserved 10 = Reserved 11 = Host Controller is NOT at reset (Reset Released)

2.3.3 ACTIVE LTR (ACTIVELTR_VALUE)—Offset 210h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 800h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000100000000000 RSVD RSVD SNOOP_VALUE non_snoop_value snoop_requirment snoop_latency_scale non_snoop_requirment non_snoop_latency_scale

Bit Default & Field Name (ID): Description Range Access

Non Snoop Requirment (non_snoop_requirment): If the Requirement (bit 15) is 0h clear, that indicates that the device has no LTR requirement for this type of traffic 31 (i.e. it can wait for service indefinitely). If the 10-bit latency value is zero it indicates RO that the device cannot tolerate any delay and needs the best possible service/ response time.

0h 30:29 Reserved. RO

Non-Snoop Latency Scale (non_snoop_latency_scale): Support for codes 010 0h (1us) or 011 (32us) for Snoop Latency Scale (1us -> 32ms total span) only. Writes to 28:26 RO this CSR which dont match those values will be dropped completely, next read will return previous value.

0h Non-Snoop Value (non_snoop_value): 10-bit latency value 25:16 RO

Snoop Requirement (snoop_requirment): If the Requirement (bit 15) is clear, 0h that indicates that the device has no LTR requirement for this type of traffic (i.e. it 15 can wait for service indefinitely). If the 10-bit latency value is zero it indicates that RW the device cannot tolerate any delay and needs the best possible service/response time.

332219-002 121 Generic SPI Interface (D30:F2)

Bit Default & Field Name (ID): Description Range Access

0h 14:13 Reserved. RO

Snoop Latency Scale (snoop_latency_scale): Support for codes 010 (1us) or 2h 011 (32us) for Snoop Latency Scale(1us -> 32ms total span) only. Writes to this CSR 12:10 RW which dont match those values will be dropped completely, next read will return previous value.

0h Snoop Value (SNOOP_VALUE): 10-bit latency value 9:0 RW

2.3.4 Idle LTR Value (IDLELTR_VALUE)—Offset 214h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 800h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000100000000000 RSVD RSVD snoop_value non_snoop_value snoop_requirment snoop_latency_scale non_snoop_requirment non_snoop_latency_scale

Bit Default & Field Name (ID): Description Range Access

Non Snoop Requirment (non_snoop_requirment): If the Requirement (bit 15) is 0h clear, that indicates that the device has no LTR requirement for this type of traffic 31 (i.e. it can wait for service indefinitely). If the 10-bit latency value is zero it indicates RO that the device cannot tolerate any delay and needs the best possible service/ response time.

0h 30:29 Reserved. RO

Non Snoop Latency Scale (non_snoop_latency_scale): Support for codes 010 0h (1us) or 011 (32us) for Snoop Latency Scale (1us -> 32ms total span) only. Writes to 28:26 RO this CSR which dont match those values will be dropped completely, next read will return previous value.

0h Non Snoop Value (non_snoop_value): 10-bit latency value 25:16 RO

Snoop Requirment (snoop_requirment): If the Requirement (bit 15) is clear, that 0h indicates that the device has no LTR requirement for this type of traffic (i.e. it can 15 RW wait for service indefinitely). If the 10-bit latency value is zero it indicates that the device cannot tolerate any delay and needs the best possible service/response time.

122 332219-002

Generic SPI Interface (D30:F2)

Bit Default & Field Name (ID): Description Range Access

0h 14:13 Reserved. RO

Snoop Latency Scale (snoop_latency_scale): Support for codes 010 (1us) or 2h 011 (32us) for Snoop Latency Scale(1us -> 32ms total span) only. Writes to this CSR 12:10 RW which dont match those values will be dropped completely, next read will return previous value.

0h Snoop Value (snoop_value): 10-bit latency value. 9:0

2.3.5 TX Bit Count (TX_BIT_COUNT)—Offset 218h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD tx_bit_count tx_count_overflow

Bit Default & Field Name (ID): Description Range Access

0h Tx Count Overflow (tx_count_overflow): 0 = Count valid 31 RO 1 = count overflow/invalid

0h 30:24 Reserved. RO

0h Tx Bit Count (tx_bit_count): 24-bit up-counter which counts the number of TX 23:0 RO bits on the Serial bus. The counter is forced to be cleared by software Read

2.3.6 Rx Bit Count (RX_BIT_COUNT)—Offset 21Ch

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

332219-002 123 Generic SPI Interface (D30:F2)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD rx_bit_count rx_count_overflow

Bit Default & Field Name (ID): Description Range Access

0h Rx Count Overflow (rx_count_overflow): 31 0 = count valid RO 1 = count overflow/invalid

0h 30:24 Reserved. RO

0h Rx Bit Count (rx_bit_count): 24-bit up-counter which counts the number of RX 23:0 RO Bits on the Serial bus. The counter is forced to be cleared by software Read

2.3.7 reg_SSP_REG (SSP_REG)—Offset 220h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD disable_ssp_dma_finish

Bit Default & Field Name (ID): Description Range Access

0h 31:1 Reserved. RO

Disable DMA Finish (disable_ssp_dma_finish): This bit needs to be set to 1 if 0h SPI is using DMA multi-Block Chaining and the SW driver does not plan to re-enable 0 the DMA manually after every Link List completion 1 = DMA finish Disabled Note: Required for multi-block transfer 0 – DMA finish not disabled.

124 332219-002

Generic SPI Interface (D30:F2)

2.3.8 SPI CS CONTROL (SPI_CS_CONTROL)—Offset 224h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 1000h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000001000000000000 RSVD RSVD RSVD cs_state cs_mode cs1_output_sel

Bit Default & Field Name (ID): Description Range Access

0h 31:13 Reserved. RO

1h Chip Select Polarity: 0 = low, 1 = high 12

0h 11:10 Reserved. RO

cs_output_sel (cs1_output_sel): These Bits select which SPI CS Signal is to be driven by the SSP Frame (CS). 0h 9:8 00 = SPI CS0 01 = Reserved 10 = Reserved 11= Reserved

0h 7:2 Reserved. RO

0h Chip Select State (cs_state): Manual SW control of SPI Chip Select (CS) 1 0 = CS is set to low 1 = CS is set to high

0h Chip Select Mode (cs_mode): SPI Chip Select Mode Section. 0 0 = HW Mode- CS is under SSP control 1 = SW Mode – CS is under SW Control using cs_state bit

2.3.9 SW SCRATCH [3:0] (SW_SCRATCH)—Offset 228h

NOTE: The same registers are available at the following offsets: SW SCRATCH 1: offset 22Ch SW SCRATCH 2: offset 230h SW SCRATCH 3: offset 234h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

332219-002 125 Generic SPI Interface (D30:F2)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 reg_SW_Scratch_0

Bit Default & Field Name (ID): Description Range Access

0h SW Scratch Pad (reg_SW_Scratch_0): Scratch Pad Register for SW to generate 31:0 RW Local DATA for DMA

2.3.10 Clock Gate (CLOCK_GATE)—Offset 238h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD sw_ip_clk_ctl sw_dma_clk_ctl

Bit Default & Field Name (ID): Description Range Access

0h 31:4 Reserved. RO

DMA Clock Control (sw_dma_clk_ctl): DMA Clock Control 0h 00 = Dyanamic Clock Gate Enable 3:2 01 = Reserved 10 = Force DMA Clock off 11 = Force DMA Clock on

Clock Control (sw_ip_clk_ctl): Clock Control 0h 00 = Dyanamic Clock Gate Enable 1:0 01 = Reserved 10 = Force Clocks off 11 = Force Clocks on

2.3.11 Remap Address Low (REMAP_ADDR_LO)—Offset 240h

Access Method

126 332219-002

Generic SPI Interface (D30:F2)

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 spi_remap_addr_low

Bit Default & Field Name (ID): Description Range Access

0h Remap Address Low (spi_remap_addr_low): Low 32 bits of BAR address read 31:0 RW by SW

2.3.12 Remap Address High (REMAP_ADDR_HI)—Offset 244h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 spi_remap_addr_high

Bit Default & Field Name (ID): Description Range Access

0h Remap Address High (spi_remap_addr_high): High 32 bits of BAR address read 31:0 RW by SW

2.3.13 Delay Rx Clock (DEL_RX_CLK)—Offset 250h

Access Method

332219-002 127 Generic SPI Interface (D30:F2)

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RX_CLK_SEL

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

Delayed Rx Clock Select (RX_CLK_SEL): 00 = The output of the internal (M/N and/or baud rate) clock divider is used as-is to clock in the receive data to the RxFIFO. 01 = An internally delayed version of the internal clock divider output is used to clock in the receive data to the RxFIFO. This allows some additional setup time on the PCH 0h side. 1:0 10 = The receive data is clocked on the subsequent negedge of the Tx clock, allowing RW a full cycle propagation delay on the platform. 11: The receive data is clocked on the subsequent negedge of the delayed Rx clock, maximizing the amount of delay allowed for capturing the receive data. Note: This capability is only supported for default SSP configuration with active high clocks (SSCR1.SPO = 0 and SSCR1.SPH = 0). Other combinations of SPO and SPH setting are not supported for non-zero settings of this field.

2.3.14 Capabilities (CAPABLITIES)—Offset 2FCh

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 1E20h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000001111000100000 RSVD iDMA_present instance_type cs_output_select instance_number

128 332219-002

Generic SPI Interface (D30:F2)

Bit Default & Field Name (ID): Description Range Access

0h 31:13 Reserved. RO

Fh CS Output Select (cs_output_select): 0 = Un connected ; 1 = connected 12:9 RO

0h DMA Present (iDMA_present): 8 0= DMA present RO 1= DMA not present

instance_type (instance_type): 2h 0000 = IC2 7:4 0001 = UART RO 0010 = SPI 0011 – 1111 = Reserved

0h Instance Number (instance_number): 3:0 0h: SPI0 RO 1h: SPI1

2.4 Generic SPI (GSPI) DMA Controller Registers Summary

Table 2-4. Summary of Generic SPI (GSPI) DMA Controller Registers

Offset Offset Default Register Name (ID)—Offset Start End Value

800h 803h DMA Transfer Source Address Low (SAR_LO0)—Offset 800h 0h

804h 807h DMA Transfer Source Address High (SAR_HI0)—Offset 804h 0h

808h 80Bh DMA Transfer Destination Address Low (DAR_LO0)—Offset 808h 0h

80Ch 80Fh DMA Transfer Destination Address High (DAR_HI0)—Offset 80Ch 0h

810h 813h Linked List Pointer Low (LLP_LO0)—Offset 810h 0h

814h 817h Linked List Pointer High (LLP_HI0)—Offset 814h 0h

818h 81Bh Control Register Low (CTL_LO0)—Offset 818h 0h

81Ch 81Fh Control Register High (CTL_HI0)—Offset 81Ch 0h

820h 823h Source Status (SSTAT0)—Offset 820h 0h

828h 82Bh Destination Status (DSTAT0)—Offset 828h 0h

830h 833h Source Status Address Low (SSTATAR_LO0)—Offset 830h 0h

834h 837h Source Status Address High (SSTATAR_HI0)—Offset 834h 0h

838h 83Bh Destination Status Address Low (DSTATAR_LO0)—Offset 838h 0h

83Ch 83Fh Destination Status Address High (DSTATAR_HI0)—Offset 83Ch 0h

840h 843h DMA Transfer Configuration Low (CFG_LO0)—Offset 840h 203h

844h 847h DMA Transfer Configuration High (CFG_HI0)—Offset 844h 0h

848h 84Bh Source Gather (SGR0)—Offset 848h 0h

850h 853h Destination Scatter (DSR0)—Offset 850h 0h

AC0h AC3h Raw Interrupt Status (RawTfr)—Offset AC0h 0h

AC8h ACBh Raw Status for Block Interrupts (RawBlock)—Offset AC8h 0h

AD0h AD3h Raw Status for Source Transaction Interrupts (RawSrcTran)—Offset AD0h 0h

Raw Status for Destination Transaction Interrupts (RawDstTran)—Offset AD8h ADBh 0h AD8h

AE0h AE3h Raw Status for Error Interrupts (RawErr)—Offset AE0h 0h

332219-002 129 Generic SPI Interface (D30:F2)

Table 2-4. Summary of Generic SPI (GSPI) DMA Controller Registers (Continued)

Offset Offset Default Register Name (ID)—Offset Start End Value

AE8h AEBh Interrupt Status (StatusTfr)—Offset AE8h 0h

AF0h AF3h Status for Block Interrupts (StatusBlock)—Offset AF0h 0h

AF8h AFBh Status for Source Transaction Interrupts (StatusSrcTran)—Offset AF8h 0h

Status for Destination Transaction Interrupts (StatusDstTran)—Offset B00h B03h 0h B00h

B08h B0Bh Status for Error Interrupts (StatusErr)—Offset B08h 0h

B10h B13h Mask for Transfer Interrupts (MaskTfr)—Offset B10h 0h

B18h B1Bh Mask for Block Interrupts (MaskBlock)—Offset B18h 0h

B20h B23h Mask for Source Transaction Interrupts (MaskSrcTran)—Offset B20h 0h

B28h B2Bh Mask for Destination Transaction Interrupts (MaskDstTran)—Offset B28h 0h

B30h B33h Mask for Error Interrupts (MaskErr)—Offset B30h 0h

B38h B3Bh Clear for Transfer Interrupts (ClearTfr)—Offset B38h 0h

B40h B43h Clear for Block Interrupts (ClearBlock)—Offset B40h 0h

B48h B4Bh Clear for Source Transaction Interrupts (ClearSrcTran)—Offset B48h 0h

B50h B53h Clear for Destination Transaction Interrupts (ClearDstTran)—Offset B50h 0h

B58h B5Bh Clear for Error Interrupts (ClearErr)—Offset B58h 0h

B60h B63h Combined Status register (StatusInt)—Offset B60h 0h

B98h B9Bh DMA Configuration (DmaCfgReg)—Offset B98h 0h

BA0h BA3h DMA Channel Enable (ChEnReg)—Offset BA0h 0h

2.4.1 DMA Transfer Source Address Low (SAR_LO0)—Offset 800h

NOTE: SAR_LO0 is for DMA Channel 0. The same register definition,SAR_LO1, is available for Channel 1 at address 858h. SAR_LO0 (CH0): offset 800h SAR_LO1 (CH1): offset 858h The starting source address is programmed by software before the DMA channel is enabled, or by an LLI update before the start of the DMA transfer. While the DMA transfer is in progress, this register is updated to reflect the source address of the current transfer.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 SAR_LO

130 332219-002

Generic SPI Interface (D30:F2)

Bit Default & Field Name (ID): Description Range Access

SAR_LO: Current Source Address of DMA transfer.

Updated after each source transfer. The SINC field in the CTL_LO[n]: Control Register determines whether the address increments or is left unchanged on every source transfer throughout the block transfer. When the channel is enabled (i.e. CH_EN is 1), the read back value will reflect the updated source transfer addresses. However, when the channel is disabled, the original programmed value will be reflected when reading this register.

It's important to notice the following: 1. Once the block transfer is in progress (i.e. when channel is enabled), the read- back value correlates with the OCP Read Address that one would see in an OCP tracker. 0h 2. If the read to this register comes during a block transfer, the LAST DMA Read 31:0 RW address sent on the OCP before the register read is what's reflected in the read-back value. 3. If the last DMA read was a burst read (i.e. burst length > 1), the read-back value reflects the first address of the burst read since this is what gets sent on the OCP fabric. 4. If the read to the register occurred after the whole block got transferred, then the channel gets disabled and the returned value would be the original programmed value. 5. Since the read-back value is OCP based, only DW aligned addresses will be reflected (i.e. OCP Byte-Enable values would not be reflected) 6. Based on the above remarks, this value should be used as pseudo DMA read progress indicator when the channel is enabled and not an absolute one.

Decrementing addresses are not supported.

2.4.2 DMA Transfer Source Address High (SAR_HI0)—Offset 804h

NOTE: SAR_HI0 is for DMA Channel 0. The same register definition, SAR_HI1, is available for Channel 1 at address 85Ch. SAR_HI0 (CH0): offset 804h SAR_HI1 (CH1): offset 85Ch The starting source address is programmed by software before the DMA channel is enabled, or by an LLI update before the start of the DMA transfer. While the DMA transfer is in progress, this register is updated to reflect the source address of the current transfer.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 SAR_HI

332219-002 131 Generic SPI Interface (D30:F2)

Bit Default & Field Name (ID): Description Range Access

SAR_HI: Current Source Address of DMA transfer.

Updated after each source transfer. The SINC field in the CTL_LO[n]: Control Register determines whether the address increments or is left unchanged on every source transfer throughout the block transfer. When the channel is enabled (i.e. CH_EN is 1), the read back value will reflect the updated source transfer addresses. However, when the channel is disabled, the original programmed value will be reflected when reading this register.

It's important to notice the following: 1. Once the block transfer is in progress (i.e. when channel is enabled), the read- back value correlates with the OCP Read Address that one would see in an OCP tracker. 0h 2. If the read to this register comes during a block transfer, the LAST DMA Read 31:0 RW address sent on the OCP before the register read is what's reflected in the read-back value. 3. If the last DMA read was a burst read (i.e. burst length > 1), the read-back value reflects the first address of the burst read since this is what gets sent on the OCP fabric. 4. If the read to the register occurred after the whole block got transferred, then the channel gets disabled and the returned value would be the original programmed value. 5. Since the read-back value is OCP based, only DW aligned addresses will be reflected (i.e. OCP Byte-Enable values would not be reflected) 6. Based on the above remarks, this value should be used as pseudo DMA read progress indicator when the channel is enabled and not an absolute one.

Decrementing addresses are not supported.

2.4.3 DMA Transfer Destination Address Low (DAR_LO0)—Offset 808h

NOTE: DAR_LO0 is for DMA Channel 0. The same register definition, DAR_LO1, is available for Channel 1 at address 860h. DAR_LO0 (CH0): offset 808h DAR_LO1 (CH1): offset 860h The starting destination address is programmed by software before the DMA channel is enabled, or by an LLI update before the start of the DMA transfer. While the DMA transfer is in progress, this register is updated to reflect the destination address of the current transfer.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 DAR_LO

132 332219-002

Generic SPI Interface (D30:F2)

Bit Default & Field Name (ID): Description Range Access

DAR_LO: Current Destination Address of DMA transfer.

Updated after each destination transfer. The DINC field in the CTL_LO[n]: Control Register determines whether the address increments or is left unchanged on every destination transfer throughout the block transfer. When the channel is enabled (i.e. CH_EN is 1), the read back value will reflect the updated destination transfer addresses. However, when the channel is disabled, the original programmed value will be reflected when reading this register.

It's important to notice the following: 1. Once the block transfer is in progress (i.e. when channel is enabled), the read- back value correlates with the OCP Write Address that one would see in an OCP tracker. 0h 2. If the read to this register comes during a block transfer, the LAST DMA Write 31:0 RW address sent on the OCP before the register read is what's reflected in the read-back value. 3. If the last DMA write was a burst write (i.e. burst length > 1), the read-back value reflects the first address of the burst write since this is what gets sent on the OCP fabric. 4. If the read to the register occurred after the whole block got transferred, then the channel gets disabled and the returned value would be the original programmed value. 5. Since the read-back value is OCP based, only DW aligned addresses will be reflected (i.e. OCP Byte-Enable values would not be reflected) 6. Based on the above remarks, this value should be used as pseudo DMA write progress indicator when the channel is enabled and not an absolute one.

Decrementing addresses are not supported.

2.4.4 DMA Transfer Destination Address High (DAR_HI0)— Offset 80Ch

NOTE: DAR_HI0 is for DMA Channel 0. The same register definition, DAR_HI1, is available for Channel 1 at address 864h. DAR_HI0 (CH0): offset 80Ch DAR_HI1 (CH1): offset 864h The starting destination address is programmed by software before the DMA channel is enabled, or by an LLI update before the start of the DMA transfer. While the DMA transfer is in progress, this register is updated to reflect the destination address of the current transfer.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 DAR_HI

332219-002 133 Generic SPI Interface (D30:F2)

Bit Default & Field Name (ID): Description Range Access

DAR_HI: Current Destination Address of DMA transfer.

Updated after each destination transfer. The DINC field in the CTL_LO[n]: Control Register determines whether the address increments or is left unchanged on every destination transfer throughout the block transfer. When the channel is enabled (i.e. CH_EN is 1), the read back value will reflect the updated destination transfer addresses. However, when the channel is disabled, the original programmed value will be reflected when reading this register.

It's important to notice the following: 1. Once the block transfer is in progress (i.e. when channel is enabled), the read- back value correlates with the OCP Write Address that one would see in an OCP tracker. 0h 2. If the read to this register comes during a block transfer, the LAST DMA Write 31:0 RW address sent on the OCP before the register read is what's reflected in the read-back value. 3. If the last DMA write was a burst write (i.e. burst length > 1), the read-back value reflects the first address of the burst write since this is what gets sent on the OCP fabric. 4. If the read to the register occurred after the whole block got transferred, then the channel gets disabled and the returned value would be the original programmed value. 5. Since the read-back value is OCP based, only DW aligned addresses will be reflected (i.e. OCP Byte-Enable values would not be reflected) 6. Based on the above remarks, this value should be used as pseudo DMA write progress indicator when the channel is enabled and not an absolute one.

Decrementing addresses are not supported.

2.4.5 Linked List Pointer Low (LLP_LO0)—Offset 810h

NOTE: LLP_LO0 is for DMA Channel 0. The same register definition, LLP_LO1, is available for Channel 1 at address 868h. LLP_LO0 (CH0): offset 810h LLP_LO1 (CH1): offset 868h The register needs to be programmed to point to the first Linked List Item (LLI) in memory prior to enabling the channel if block chaining is enabled.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 LOC RSVD

Bit Default & Field Name (ID): Description Range Access

LOC: Starting Address In Memory of next LLI if block chaining is enabled. Note that 0h 31:2 the two LSBs of the starting address are not stored because the address is assumed RW to be aligned to a 32-bit boundary. LLI accesses are always 32-bit accesses and cannot be changed or programmed to anything other than 32-bit.

0h 1:0 Reserved. RO

134 332219-002

Generic SPI Interface (D30:F2)

2.4.6 Linked List Pointer High (LLP_HI0)—Offset 814h

NOTE: LLP_HI0 is for DMA Channel 0. The same register definition, LLP_HI1, is available for Channel 1 at address 86Ch. LLP_HI0 (CH0): offset 814h LLP_LO1 (CH1): offset 86Ch The register needs to be programmed to point to the first Linked List Item (LLI) in memory prior to enabling the channel if block chaining is enabled.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 LOC RSVD

Bit Default & Field Name (ID): Description Range Access

LOC: Starting Address In Memory of next LLI if block chaining is enabled. Note that 0h the two LSBs of the starting address are not stored because the address is assumed 31:2 RW to be aligned to a 32-bit boundary. LLI accesses are always 32-bit accesses and cannot be changed or programmed to anything other than 32-bit.

0h 1:0 Reserved. RO

2.4.7 Control Register Low (CTL_LO0)—Offset 818h

NOTE: CTL_LO0 is for DMA Channel 0. The same register definition, CTL_LO1, is available for Channel 1 at address 870h. LLP_HI0 (CH0): offset 818h LLP_LO1 (CH1): offset 870h This register contains fields that control the DMA transfer. The CTL_HI register is part of the block descriptor (linked list item - LLI) when block chaining is enabled. It can be varied on a block-by-block basis within a DMA transfer when block chaining is enabled. If status write-back is enabled, CTL_HI is written to then control registers location of the LLI in system memory at the end of the block transfer.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

332219-002 135 Generic SPI Interface (D30:F2)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 SINC DINC RSVD RSVD RSVD RSVD RSVD TT_FC INT_EN SRC_MSIZE LLP_DST_EN LLP_SRC_EN DEST_MSIZE SRC_TR_WIDTH DST_TR_WIDTH SRC_GATHER_EN DST_SCATTER_EN

Bit Default & Field Name (ID): Description Range Access

0h 31:29 Reserved. RO

0h LLP_SRC_EN: Block chaining is enabled on the source side only if the LLP_SRC_EN 28 RW field is high and LLPn.LOC is non-zero and (LLP_EN == 1)

0h LLP_DST_EN: Block chaining is enabled on the destination side only if the 27 RW LLP_DST_EN field is high and LLPn.LOC is non-zero and (LLP_EN == 1)

0h 26:22 Reserved. RO

TT_FC: The following transfer types are supported. Memory to Memory (00) 0h 21:20 Memory to Peripheral (01) RW Peripheral to Memory (10) Peripheral to Peripheral (11) Flow Control is always assigned to the DMA.

0h 19 Reserved. RO

DST_SCATTER_EN: 0 = Scatter disabled 0h 1 = Scatter enabled 18 RW Scatter on the destination side is applicable only when the CTL_LOn.DINC bit indicates an incrementing address control.

SRC_GATHER_EN: 0 = Gather disabled 0h 1 = Gather enabled 17 RW Gather on the source side is applicable only when the CTL_LOn.SINC bit indicates an incrementing address control.

0h SRC_MSIZE: Number of data items, each of width CTL_LOn.SRC_TR_WIDTH, to be 16:14 RW read from the source.

0h DEST_MSIZE: Number of data items, each of width CTL_LOn.DST_TR_WIDTH, to be 13:11 RW written to the destination.

SINC: Indicates whether to increment or decrement the source address on every 0h source transfer. If the device is fetching data from a source peripheral FIFO with a 10 fixed address, then set this field to No change. RW 0 = Increment 1 = Fixed (No Change)

0h 9 Reserved. RO

DINC: Indicates whether to increment or decrement the destination address on 0h every destination transfer. If your device is writing data to a destination peripheral 8 FIFO with a fixed address, then set this field to No change. RW 0 = Increment 1 = Fixed (No change)

0h 7 Reserved. RO

136 332219-002

Generic SPI Interface (D30:F2)

Bit Default & Field Name (ID): Description Range Access

SRC_TR_WIDTH: BURST_SIZE = (2 ^ MSIZE) 0h 1. Transferred Bytes Per Burst = (BURST_SIZE * TR_WIDTH) 6:4 2. For incrementing addresses and (Transfer_Width < 4 Bytes), the MSIZE RW parameter is ignored since only single transactions are supported (due to OCP limitations)

DST_TR_WIDTH: Destination Transfer Width. BURST_SIZE = (2 ^ MSIZE) 0h 1.Transferred Bytes Per Burst = (BURST_SIZE * TR_WIDTH) 3:1 2.For incrementing addresses and (Transfer_Width < 4 Bytes), the MSIZE RW parameter is ignored since only single transactions are supported (due to OCP limitations)

0h INT_EN: Interrupt Enable Bit. If set, then all interrupt-generating sources are 0 RW enabled.

2.4.8 Control Register High (CTL_HI0)—Offset 81Ch

NOTE: CTL_HI0 is for DMA Channel 0. The same register definition, CTL_HI1, is available for Channel 1 at address 874h. CTL_HI0 (CH0): offset 81Ch CTL_HI1 (CH1): offset 874h This register contains fields that control the DMA transfer. The CTL_HI register is part of the block descriptor (linked list item - LLI) when block chaining is enabled. It can be varied on a block-by-block basis within a DMA transfer when block chaining is enabled.If status write-back is enabled, CTL_HI is written to then control registers location of the LLI in system memory at the end of the block transfer.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 DONE BLOCK_TS CH_CLASS CH_WEIGHT

Bit Default & Field Name (ID): Description Range Access

0h CH_CLASS: A Class of (N_CHNLS-1) is the highest priority, and 0 is the lowest. This 31:29 field must be programmed within 0 to (N_CHNLS-1). RW A programmed value outside this range will cause erroneous behavior.

332219-002 137 Generic SPI Interface (D30:F2)

Bit Default & Field Name (ID): Description Range Access

0h CH_WEIGHT 28:18 RW

DONE: If status write-back is enabled, the upper word of the control register, CTL_HIn, is written to the control register location of the Linked List Item (LLI) in

0h system memory at the end of the block transfer with the done bit set. 17 Software can poll the LLI CTL_HI.DONE bit to see when a block transfer is complete. RW The LLI CTL_HI.DONE bit should be cleared when the linked lists are set up in memory prior to enabling the channel. The DMA will not transfer the block if the DONE bit in the LLI is not cleared.

BLOCK_TS: Block Transfer Size (in Bytes). Since the DMA is always the flow controller, the user needs to write this field before the channel is enabled in order to indicate the block size. The number programmed into BLOCK_TS indicates the total number of bytes to transfer for every block 0h 16:0 transfer. RW Once the transfer starts (i.e. channel is enabled), the read-back value is the total number of bytes for which Read Commands have already been sent to the source. It doesn?t mean Bytes that are already in the FIFO. However, when the channel is disabled, the original programmed value will be reflected when reading this register. Theoretical Byte Size range is from 0 to (2^17 -1) = (128 KB - 1).

2.4.9 Source Status (SSTAT0)—Offset 820h

NOTE: SSTAT0 is for DMA Channel 0. The same register definition, SSTAT1, is available for Channel 1 at address 878h. SSTAT0 (CH0): offset 820h SSTAT1 (CH1): offset 878h After each block transfer completes, hardware can retrieve the source status information from the address pointed to by the contents of the SSTATARx register. This status information is then stored in the SSTATx register and written out to the SSTATx register location of the LLI before the start of the next block. Note : This register is a temporary placeholder for the source status information on its way to the SSTATx register location of the LLI. The source status information should be retrieved by software from the SSTATx register location of the LLI, and not by a read of this register over the DMA slave interface.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 SSTAT

Bit Default & Field Name (ID): Description Range Access

SSTAT: Source status information retrieved by hardware from the address pointed to by the contents of the Source Status Address Register. This register is a temporary 0h 31:0 placeholder for the source status information on its way to the SSTATn register RW location of the LLI. The source status information should be retrieved by software from the SSTATn register location of the LLI, and not by a read of this register over the DMA slave interface.

138 332219-002

Generic SPI Interface (D30:F2)

2.4.10 Destination Status (DSTAT0)—Offset 828h

NOTE: DSTAT0 is for DMA Channel 0. The same register definition, DSTAT1, is available for Channel 1 at address 880h. DSTAT0 (CH0): offset 828h DSTAT1 (CH1): offset 880h After the completion of each block transfer, hardware can retrieve the destination status information from the address pointed to by the contents of the DSTATARx register. This status information is then stored in the DSTATx register and written out to the DSTATx register location of the LLI. Note : This register is a temporary placeholder for the destination status information on its way to the DSTATx register location of the LLI. The destination status information should be retrieved by software from the DSTATx register location of the LLI and not by a read of this register over the DMA slave interface.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 DSTAT

Bit Default & Field Name (ID): Description Range Access

DSTAT: Destination status information retrieved by hardware from the address pointed to by the contents of the Destination Status Address Register. This register is 0h a temporary placeholder for the destination status information on its way to the 31:0 RW DSTATn register location of the LLI. The destination status information should be retrieved by software from the DSTATn register location of the LLI and not by a read of this register over the DMA slave interface.

2.4.11 Source Status Address Low (SSTATAR_LO0)—Offset 830h

NOTE: SSTATAR_LO0 is for DMA Channel 0. The same register definition, SSTATAR_LO1, is available for Channel 1 at address 888h. SSTATAR_LO0(CH0): offset 830h SSTATAR_LO1(CH1): offset 888h After the completion of each block transfer, hardware can retrieve the source status information from the address pointed to by the contents of the SSTATARx register.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

332219-002 139 Generic SPI Interface (D30:F2)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 SSTATAR_LO

Bit Default & Field Name (ID): Description Range Access

0h SSTATAR_LO: Pointer from where hardware can fetch the source status information, 31:0 which is registered in the SSTATn register and written out to the SSTATn register RW location of the LLI before the start of the next block.

2.4.12 Source Status Address High (SSTATAR_HI0)—Offset 834h

NOTE: SSTATAR_HI0 is for DMA Channel 0. The same register definition, SSTATAR_HI1, is available for Channel 1 at address 88Ch. SSTATAR_HI0(CH0): offset 834h SSTATAR_HI1(CH1): offset 88Ch After the completion of each block transfer, hardware can retrieve the source status information from the address pointed to by the contents of the SSTATARx register.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 SSTATAR_HI

Bit Default & Field Name (ID): Description Range Access

0h SSTATAR_HI: Pointer from where hardware can fetch the source status information, 31:0 which is registered in the SSTATn register and written out to the SSTATn register RW location of the LLI before the start of the next block.

2.4.13 Destination Status Address Low (DSTATAR_LO0)—Offset 838h

NOTE: DSTATAR_LO0 is for DMA Channel 0. The same register definition, DSTATAR_LO1, is available for Channel 1 at address 890h. DSTATAR_LO0(CH0): offset 838h DSTATAR_LO1(CH1): offset 890h

140 332219-002

Generic SPI Interface (D30:F2)

After the completion of each block transfer, hardware can retrieve the destination status information from the address pointed to by the contents of the DSTATARx register.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 DSTATAR_LO

Bit Default & Field Name (ID): Description Range Access

0h DSTATAR_LO: Pointer from where hardware can fetch the destination status 31:0 information, which is registered in the DSTATn register and written out to the DSTATn RW register location of the LLI before the start of the next block.

2.4.14 Destination Status Address High (DSTATAR_HI0)—Offset 83Ch

NOTE: DSTATAR_LO0 is for DMA Channel 0. The same register definition, DSTATAR_HI1, is available for Channel 1 at address 894h. DSTATAR_HI0(CH0): offset 83Ch DSTATAR_HI1(CH1): offset 894h After the completion of each block transfer, hardware can retrieve the destination status information from the address pointed to by the contents of the DSTATARx register.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 DSTATAR_HI

332219-002 141 Generic SPI Interface (D30:F2)

Bit Default & Field Name (ID): Description Range Access

0h DSTATAR_HI: Pointer from where hardware can fetch the destination status 31:0 information, which is registered in the DSTATn register and written out to the DSTATn RW register location of the LLI before the start of the next block.

2.4.15 DMA Transfer Configuration Low (CFG_LO0)—Offset 840h

NOTE: CFG_LO0 is for DMA Channel 0. The same register definition, CFG_LO1, is available for Channel 1 at address 898h. CFG_LO0(CH0): offset 840h CFG_LO1(CH1): offset 898h This register contains fields that configure the DMA transfer. The channel configuration register remains fixed for all blocks of a multi-block transfer. This Register should be programmed to enabling the channel

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 203h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000001000000011 RSVD RSVD RSVD CH_SUSP CH_DRAIN ALL_NP_WR SS_UPD_EN DS_UPD_EN FIFO_EMPTY DST_OPT_BL SRC_OPT_BL SRC_HS_POL DST_HS_POL RELOAD_DST RELOAD_SRC CTL_HI_UPD_EN HSHAKE_NP_WR DST_BURST_ALIGN SRC_BURST_ALIGN

Bit Default & Field Name (ID): Description Range Access

0h RELOAD_DST: Automatic Destination Reload. The DARn register can be 31 automatically reloaded from its initial value at the end of every block for multi-block RW transfers. A new block transfer is then initiated.

0h RELOAD_SRC: Automatic Source Reload. The SARx register can be automatically 30 reloaded from its initial value at the end of every block for multi-block transfers. A RW new block transfer is then initiated.

0h 29:22 Reserved. RO

SRC_OPT_BL: Optimize Source Burst Length : 0h 0 = Writes will use only BL=1 or BL=(2 ^ SRC_MSIZE) 21 RW 1 = Writes will use (1 <= BL <= (2 ^ SRC_MSIZE)) *** This bit should be set to (0) if Source HW-Handshake is enabled

DST_OPT_BL: Optimize Destination Burst Length : 0h 0 = Writes will use only BL=1 or BL=(2 ^ DST_MSIZE) 20 RW 1 = Writes will use (1 <= BL <= (2 ^ DST_MSIZE)) *** This bit should be set to (0) if Destination HW-Handshake is enabled

0h SRC_HS_POL: Source Handshaking Interface Polarity. 19 0 = Active high RW 1 = Active low

142 332219-002

Generic SPI Interface (D30:F2)

Bit Default & Field Name (ID): Description Range Access

0h DST_HS_POL: Destination Handshaking Interface Polarity. 18 0 = Active high RW 1 = Active low

0h 17:11 Reserved. RO

0h CH_DRAIN: Forces channel FIFO to drain while in suspension. This bit has effect 10 RW only when CH_SUSPEND is asserted

FIFO_EMPTY: Indicates if there is data left in the channel FIFO. Can be used in 1h conjunction with CFGx.CH_SUSP to cleanly disable a channel. 9 RO 1 = Channel FIFO empty 0 = Channel FIFO not empty

CH_SUSP: Channel Suspend. Suspends all DMA data transfers from the source until this bit is cleared. There is no guarantee that the current transaction will complete. 0h Can also be used in conjunction with CFGx.FIFO_EMPTY to cleanly disable a channel 8 RW without losing any data. 0 = Not suspended. 1 = Suspend DMA transfer from the source.

SS_UPD_EN: Source Status Update Enable. Source status information is fetched 0h only from the location pointed to by the SSTATARn register, stored in the SSTATn 7 RW register and written out to the SSTATn location of the LLI if SS_UPD_EN is high. This bit is ignored if (LLP_EN == 0) or (LLP_WB_EN == 0)

DS_UPD_EN: Destination Status Update Enable. Destination status information is 0h fetched only from the location pointed to by the DSTATARn register, stored in the 6 RW DSTATn register and written out to the DSTATn location of the LLI if DS_UPD_EN is high. This bit is ignored if (LLP_EN == 0) or (LLP_WB_EN == 0)

0h CTL_HI_UPD_EN: CTL_HI Update Enable. If set, the CTL_HI register is written out 5 to the CTL_HIn location of the LLI. This bit is ignored if (LLP_EN == 0) or RW (LLP_WB_EN == 0)

0h 4 Reserved. RO

HSHAKE_NP_WR: 0x1 : Issues Non-Posted writes on HW-Handshake on DMA Write 0h Port 3 0x0 : Issues Posted writes on HW-Handshake on DMA Write Port (Except end-of-block RW writes which will be Non-Posted) This bit must be set to 1 for proper operation

0h ALL_NP_WR: 0x1 : Forces ALL writes to be Non-Posted on DMA Write Port 2 0x0 : Non-Posted Writes will only be used at end of block transfers and in HW- RW Handshake (if HW_NP_WR=1); for all other cases, Posted Writes will be used.

1h SRC_BURST_ALIGN: 0x1 : SRC Burst Transfers are broken at a Burst Length 1 aligned boundary RW 0x0 : SRC Burst Transfers are not broken at a Burst Length aligned boundary

1h DST_BURST_ALIGN: 0x1 : DST Burst Transfers are broken at a Burst Length 0 aligned boundary RW 0x0 : DST Burst Transfers are not broken at a Burst Length aligned boundary.

2.4.16 DMA Transfer Configuration High (CFG_HI0)—Offset 844h

NOTE: CFG_HI0 is for DMA Channel 0. The same register definition, CFG_HI1, is available for Channel 1 at address 89Ch. CFG_HI0(CH0): offset 844h CFG_HI1(CH1): offset 89Ch This register contains fields that configure the DMA transfer. The channel configuration register remains fixed for all blocks of a multi-block transfer. This Register should be programmed to enabling the channel

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

332219-002 143 Generic SPI Interface (D30:F2)

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD DST_PER SRC_PER RD_ISSUE_THD WR_ISSUE_THD

Bit Default & Field Name (ID): Description Range Access

0h 31:28 Reserved. RO

0h WR_ISSUE_THD: Write Issue Threshold. Used to relax the issue criterion for Writes. 27:18 Value ranges from 0 to (2^10-1 = 1023) but should not exceed maximum Write RW burst size = (2 ^ DST_MSIZE)*TW.

0h RD_ISSUE_THD: Read Issue Threshold. Used to relax the issue criterion for Reads. 17:8 Value ranges from 0 to (2^10-1 = 1023) but should not exceed maximum Read burst RW size = (2 ^ SRC_MSIZE)*TW.

DST_PER: Destination Peripheral ID : Assigns a hardware handshaking interface (0 - 15) to the destination of channel n. The channel can then communicate with the 0h destination peripheral connected to that interface through the assigned hardware 7:4 handshaking interface. RW NOTE: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface.

SRC_PER: Source Peripheral ID : Assigns a hardware handshaking interface (0 - 15) to the source of channel n. The channel can then communicate with the source 0h peripheral connected to that interface through the assigned hardware handshaking 3:0 interface. RW NOTE: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface.

2.4.17 Source Gather (SGR0)—Offset 848h

NOTE: SGR0 is for DMA Channel 0. The same register definition, SGR1, is available for Channel 1 at address 8A0h. SGR0(CH0): offset 848h SGR1(CH1): offset 8A0h The Source Gather register contains two fields: Source gather count field (SGRx.SGC). Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH between successive gather intervals. This is defined as a gather boundary. Source gather interval field (SGRx.SGI). Specifies the source address increment/decrement in multiples of CTLx.SRC_TR_WIDTH on a gather boundary when gather mode is enabled for the source transfer. The CTLx.SINC field controls whether the address increments or decrements. When the CTLx.SINC field indicates a fixed-address control, then the address remains constant throughout the transfer and the SGRx register is ignored.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

144 332219-002

Generic SPI Interface (D30:F2)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 SGI SGC

Bit Default & Field Name (ID): Description Range Access

0h SGC 31:20 RW

0h SGI 19:0 RW

2.4.18 Destination Scatter (DSR0)—Offset 850h

NOTE: DSR0 is for DMA Channel 0. The same register definition, DSR1, is available for Channel 1 at address 8A8h. DSR0(CH0): offset 850h DSR1(CH1): offset 8A8h The Destination Scatter register contains two fields: Destination scatter count field (DSRx.DSC) . Specifies the number of contiguous destination transfers of CTLx.DST_TR_WIDTH between successive scatter boundaries. Destination scatter interval field (DSRx.DSI) . Specifies the destination address increment/decrement in multiples of CTLx.DST_TR_WIDTH on a scatter boundary when scatter mode is enabled for the destination transfer. The CTLx.DINC field controls whether the address increments or decrements. When the CTLx.DINC field indicates a fixed address control, then the address remains constant throughout the transfer and the DSRx register is ignored.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 DSI DSC

Bit Default & Field Name (ID): Description Range Access

0h DSC 31:20 RW

0h DSI 19:0 RW

2.4.19 Raw Interrupt Status (RawTfr)—Offset AC0h

Access Method

332219-002 145 Generic SPI Interface (D30:F2)

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RAW RSVD

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h RAW: Bit0 for channel 0 and bit 1 for channel 1. 1:0 RO

2.4.20 Raw Status for Block Interrupts (RawBlock)—Offset AC8h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RAW RSVD

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h RAW: Bit 0 for channel 0 and bit 1 for channel 1. 1:0 RO

2.4.21 Raw Status for Source Transaction Interrupts (RawSrcTran)—Offset AD0h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

146 332219-002

Generic SPI Interface (D30:F2)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RAW RSVD

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h RAW: Bit 0 for channel 0 and bit 1 for channel 1. 1:0 RO

2.4.22 Raw Status for Destination Transaction Interrupts (RawDstTran)—Offset AD8h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RAW RSVD

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h RAW: Bit 0 for channel 0 and bit 1 for channel 1. 1:0 RO

2.4.23 Raw Status for Error Interrupts (RawErr)—Offset AE0h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

332219-002 147 Generic SPI Interface (D30:F2)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RAW RSVD

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h RAW: Bit 0 for channel 0 and bit 1 for channel 1. 1:0 RO

2.4.24 Interrupt Status (StatusTfr)—Offset AE8h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD STATUS

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h STATUS: Bit 0 for channel 0 and bit 1 for channel 1. 1:0 RO

2.4.25 Status for Block Interrupts (StatusBlock)—Offset AF0h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

148 332219-002

Generic SPI Interface (D30:F2)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD STATUS

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h STATUS: Bit 0 for channel 0 and bit 1 for channel 1. 1:0 RO

2.4.26 Status for Source Transaction Interrupts (StatusSrcTran)—Offset AF8h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD STATUS

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h STATUS: Bit 0 is for channel 0 and bit 1 is for channel 1. 1:0 RO

2.4.27 Status for Destination Transaction Interrupts (StatusDstTran)—Offset B00h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

332219-002 149 Generic SPI Interface (D30:F2)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD STATUS

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h STATUS: Bit 0 is for channel 0 and bit 1 is for channel 1. 1:0 RO

2.4.28 Status for Error Interrupts (StatusErr)—Offset B08h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD STATUS

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h STATUS: Bit 0 is for channel 0 and bit 1 is for channel 1. 1:0 RO

2.4.29 Mask for Transfer Interrupts (MaskTfr)—Offset B10h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

150 332219-002

Generic SPI Interface (D30:F2)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD INT_MASK INT_MASK_WE

Bit Default & Field Name (ID): Description Range Access

0h 31:10 Reserved. RO

0h INT_MASK_WE: 0 = write disabled 9:8 WO 1 = write enabled

0h 7:2 Reserved. RO

0h INT_MASK: 0-mask 1:0 RW 1-unmask

2.4.30 Mask for Block Interrupts (MaskBlock)—Offset B18h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD INT_MASK INT_MASK_WE

Bit Default & Field Name (ID): Description Range Access

0h 31:10 Reserved. RO

0h INT_MASK_WE: 0 = write disabled 9:8 WO 1 = write enabled

0h 7:2 Reserved. RO

0h INT_MASK: 0-mask 1:0 RW 1-unmask

332219-002 151 Generic SPI Interface (D30:F2)

2.4.31 Mask for Source Transaction Interrupts (MaskSrcTran)— Offset B20h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD INT_MASK INT_MASK_WE

Bit Default & Field Name (ID): Description Range Access

0h 31:10 Reserved. RO

0h INT_MASK_WE: 0 = write disabled 9:8 WO 1 = write enabled

0h 7:2 Reserved. RO

0h INT_MASK: 0-mask 1:0 RW 1-unmask

2.4.32 Mask for Destination Transaction Interrupts (MaskDstTran)—Offset B28h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD INT_MASK INT_MASK_WE

152 332219-002

Generic SPI Interface (D30:F2)

Bit Default & Field Name (ID): Description Range Access

0h 31:10 Reserved. RO

0h INT_MASK_WE: 0 = write disabled 9:8 WO 1 = write enabled

0h 7:2 Reserved. RO

0h INT_MASK: 0-mask 1:0 RW 1-unmask

2.4.33 Mask for Error Interrupts (MaskErr)—Offset B30h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD INT_MASK INT_MASK_WE

Bit Default & Field Name (ID): Description Range Access

0h 31:10 Reserved. RO

0h INT_MASK_WE: 0 = write disabled 9:8 WO 1 = write enabled

0h 7:2 Reserved. RO

0h INT_MASK: 0-mask 1:0 RW 1-unmask

2.4.34 Clear for Transfer Interrupts (ClearTfr)—Offset B38h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

332219-002 153 Generic SPI Interface (D30:F2)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD CLEAR

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h CLEAR: 0 = no effect 1:0 WO 1 = clear interrupt

2.4.35 Clear for Block Interrupts (ClearBlock)—Offset B40h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD CLEAR

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h CLEAR: 0 = no effect 1:0 WO 1 = clear interrupt

2.4.36 Clear for Source Transaction Interrupts (ClearSrcTran)— Offset B48h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

154 332219-002

Generic SPI Interface (D30:F2)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD CLEAR

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h CLEAR: 0 = no effect 1:0 WO 1 = clear interrupt

2.4.37 Clear for Destination Transaction Interrupts (ClearDstTran)—Offset B50h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD CLEAR

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h CLEAR: 0 = no effect 1:0 WO 1 = clear interrupt

2.4.38 Clear for Error Interrupts (ClearErr)—Offset B58h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

332219-002 155 Generic SPI Interface (D30:F2)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD CLEAR

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h CLEAR: 0 = no effect 1:0 WO 1 = clear interrupt

2.4.39 Combined Status register (StatusInt)—Offset B60h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 TFR ERR DSTT SRCT RSVD BLOCK

Bit Default & Field Name (ID): Description Range Access

0h 31:5 Reserved. RO

0h ERR: OR of the contents of StatusErr register. 4 RO

0h DSTT: OR of the contents of StatusDst register. 3 RO

0h SRCT: OR of the contents of StatusSrcTran register 2 RO

0h BLOCK: OR of the contents of StatusBlock register. 1 RO

0h TFR: OR of the contents of StatusTfr register. 0 RO

2.4.40 DMA Configuration (DmaCfgReg)—Offset B98h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

156 332219-002

Generic SPI Interface (D30:F2)

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD DMA_EN

Bit Default & Field Name (ID): Description Range Access

0h 31:1 Reserved. RO

0h DMA_EN: 0 = DMA Disabled 0 RW 1 = DMA Enabled

2.4.41 DMA Channel Enable (ChEnReg)—Offset BA0h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 2

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD CH_EN CH_EN_WE

Bit Default & Field Name (ID): Description Range Access

0h 31:10 Reserved. RO

0h CH_EN_WE 9:8 WO

0h 7:2 Reserved. RO

CH_EN: Enables/Disables the channel. Setting this bit enables a channel, clearing this bit disables the channel. 0 = Disable the Channel 0h 1:0 1 = Enable the Channel RW The ChEnReg.CH_EN bit is automatically cleared by hardware to disable the channel after the last OCP transfer of the DMA transfer to the destination has completed. Software can therefore poll this bit to determine when this channel is free for a new DMA transfer.

332219-002 157 Generic SPI Interface (D30:F2)

§ §

158 332219-002

EMMC Interface (D30:F4)

3 EMMC Interface (D30:F4)

3.1 EMMC PCI Configuration Registers Summary

Table 3-1. Summary of EMMC PCI Configuration Registers

Offset Offset Default Register Name (ID)—Offset Start End Value

0h 3h Device & Vendor ID (VID_DID)—Offset 0h 9D2B8086h

4h 7h PCI Status & Command (STATUSCOMMAND)—Offset 4h 100000h

8h Bh Rev ID & Class Code (REVCLASSCODE)—Offset 8h 8050100h

Carche Line & Latency & Header Type & BIST (CLLATHEADERBIST)— Ch Fh 800000h Offset Ch

10h 13h Base Address Low (BAR0)—Offset 10h 4h

14h 17h Base Address Register high (BAR0_HIGH)—Offset 14h 0h

18h 1Bh Base Address Register1 (BAR1)—Offset 18h 4h

1Ch 1Fh (BAR1_HIGH)—Offset 1Ch 0h

2Ch 2Fh Subsystem Vendor ID (SUBSYSTEMID)—Offset 2Ch 0h

30h 33h (EXPANSION_ROM_BASEADDR)—Offset 30h 0h

34h 37h Capabilities Pointer (CAPABILITYPTR)—Offset 34h 80h

3Ch 3Fh (INTERRUPTREG)—Offset 3Ch 100h

80h 83h Power Management Capability ID Register (POWERCAPID)—Offset 80h 39001h

Power Management Control and Status Register (PMECTRLSTATUS)— 84h 87h 8h Offset 84h

B0h B3h General Purpose PCI RW Register1 (GEN_REGRW1)—Offset B0h 0h

B4h B7h General Purpose PCI RW Register2 (GEN_REGRW2)—Offset B4h 0h

B8h BBh General Purpose PCI RW Register3 (GEN_REGRW3)—Offset B8h 0h

BCh BFh General Purpose PCI RW Register4 (GEN_REGRW4)—Offset BCh 0h

C0h C3h General Input Register (GEN_INPUT_REG)—Offset C0h 0h

3.1.1 Device & Vendor ID (VID_DID)—Offset 0h

DEVICEVENDORID - Device ID and Vendor ID Register

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 4

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 VID DID

332219-002 159 EMMC Interface (D30:F4)

Bit Default & Field Name (ID): Description Range Access

9D2Bh Device ID (DID): Identifies the device. 31:16 RO

8086h Vendor ID (VID): Intel default value is 8086h 15:0 RO

3.1.2 PCI Status & Command (STATUSCOMMAND)—Offset 4h

STATUSCOMMAND- Status and Command

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 4

Default: 100000h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000100000000000000000000 RTA BME MSE RMA RSVD RSVD RSVD RSVD RSVD RSVD CAPLIST Reserved INTR_STATUS INTR_DISABLE

Bit Default & Field Name (ID): Description Range Access

0h 31:30 Reserved. RO

0h Received Master Abort (RMA): The software writes a 1 to this bit to clear it. 29 RW/1C

0h Received Target Abort (RTA): The software writes a 1 to this bit to clear it. 28 RW/1C

0h 27:21 Reserved. RO

1h Capabilities List (CAPLIST): Indicates that the controller contains a capabilities 20 pointer list. RO The first item is pointed to by looking at the configuration offset 34h.

0h Interrupt Status (INTR_STATUS): This bit reflects state of interrupt in the device. 19 Only when the Interrupt Disable bit in the command register is a 0 and this Interrupt RO Status bit is a 1, is the device/function interrupt message sent.

0h 18:11 Reserved. RO

0h Interrupt Disable (INTR_DISABLE): Setting this bit disables INTx assertion. 10 RW

0h 9 Reserved. RO

0h Reserved 8 RW

160 332219-002

EMMC Interface (D30:F4)

Bit Default & Field Name (ID): Description Range Access

0h 7:3 Reserved. RO

0h Bus Master Enable (BME): 0 = the Bridge does not generate any new upstream 2 transaction on IOSF as a master. RW Reset value of this bit is 0.

0h Memory Space Enable (MSE): MSE is part of the Type PCI configuration space each 1 device has. RW When disabled no downstream traffic from the bridge is available.

0h 0 Reserved. RO

3.1.3 Rev ID & Class Code (REVCLASSCODE)—Offset 8h

REVCLASSCODE - Revision ID and Class Code

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 4

Default: 8050100h

3 2 2 2 1 1 840 1 8 4 0 6 2

00001000000001010000000100000000 RID CLASS_CODES

Bit Default & Field Name (ID): Description Range Access

Class Code (CLASS_CODES): The Class Code register is read-only and is used to identify the generic function of the device, and in some cases, a specific register-level programming interface. The register is broken into 3 Byte-size fields. 80501h - The upper Byte (at offset 0Bh) is a base class code that broadly classifies the type 31:8 of function the device performs. RO - The middle Byte (at offset 0Ah) is a sub-class code that identifies more specifically the function of the device. - The lower Byte (at offset 09h) identifies a specific register-level programming interface (if any) so that device independent software can interact with the device. This register is tied to a strap at the top level.

0h Rev ID (RID): Revision ID identifies the revision of particular PCI device. 7:0 RO

3.1.4 Carche Line & Latency & Header Type & BIST (CLLATHEADERBIST)—Offset Ch

CLLATHEADERBIST - Cache Line Latency Header and BIST

Access Method

332219-002 161 EMMC Interface (D30:F4)

Type: CFG Register Device: 30 (Size: 32 bits) Function: 4

Default: 800000h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000100000000000000000000000 RSVD LATTIMER MULFNDEV HEADERTYPE CACHELINE_SIZE

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

1h Multi-Function Device (MULFNDEV): This bit is 0 or 1 depending upon the value 23 RO assigned o the top level strap

0h Header Type (HEADERTYPE): Implements Type 0 Configuration header. 22:16 RO

0h Latency Timer (LATTIMER): This register is implemented as R/W with default as 0. 15:8 RO

0h Cacheline Size (CACHELINE_SIZE): This register is implemented as R/W with 7:0 RW default as 0.

3.1.5 Base Address Low (BAR0)—Offset 10h

BAR -Base Address Register

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 4

Default: 4h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000100 MSI TYPE BASEADDR PREFETCHABLE SIZEINDICATOR

162 332219-002

EMMC Interface (D30:F4)

Bit Default & Field Name (ID): Description Range Access

0h BARL (BASEADDR): Base address of the memory space. 31:12 RW

0h Size Indicator (SIZEINDICATOR): Size Indicator Read Only. The size of this 11:4 RO register depends on the size of the memory space.

0h Prefetchable (PREFETCHABLE): Indicates that this BAR is not prefetchable. 3 RO

2h TYPE: If BAR_64b_EN is 0 then 00 indicates BAR lies in 32bit address range. 2:1 RO If BAR_64b_EN is 1 then 10 Indicates BAR lies in 64 bit address range.

0h Memory Space Indicator (MSI): 0 indicates this BAR is present in the memory 0 RO space.

3.1.6 Base Address Register high (BAR0_HIGH)—Offset 14h

This register is present on if BAR_64_EN is set as 1. This register enables 64-bit BARs. If BAR_64_EN is 0, then this register is RO.

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 4

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 BASEADDR_HIGH

Bit Default & Field Name (ID): Description Range Access

0h BARH (BASEADDR_HIGH): Base address of the OCP fabric memory space. 31:0 RW

3.1.7 Base Address Register1 (BAR1)—Offset 18h

Memory accesses to BAR1 region are aliased to the PCI configuration space. The BAR1 region is always 4K.

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 4

Default: 4h

332219-002 163 EMMC Interface (D30:F4)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000100 BAR1 TYPE1 BASEADDR1 PREFETCHABLE1 SIZEINDICATOR1

Bit Default & Field Name (ID): Description Range Access

0h Base Address Register1 (BASEADDR1): This field is present if BAR1 is enabled 31:12 RW through private configuration space.

0h SIZEBAR1 (SIZEINDICATOR1): Always is 0 as minimum size is 4K 11:4 RO

0h Prefetchable (PREFETCHABLE1): Indicates that this BAR is not prefetchable. 3 RO

2h TYPE (TYPE1): Always 0 as minimum size is 4K 2:1 RO

0h Base Address Register1 (BAR1): This field is present if BAR1 is enabled through 0 RO private configuration space.

3.1.8 (BAR1_HIGH)—Offset 1Ch

This register is present on if BAR_64_EN is set as 1. This register enables 64bit BARs. If BAR_64_EN is 0 then this register is RO.

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 4

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 BASEADDR1_HIGH

Bit Default & Field Name (ID): Description Range Access

0h BASEADDR1_HIGH: Base address of the OCP fabric memory space. 31:0 RW

164 332219-002

EMMC Interface (D30:F4)

3.1.9 Subsystem Vendor ID (SUBSYSTEMID)—Offset 2Ch

This register must be implemented for any function that can be instantiated more than once in a given system. The SVID register, in combination with the Subsystem ID register, enables the operating environment to distinguish one subsystem from the other. This register is a Read Write Once register

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 4

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 SUBSYSTEMID SUBSYSTEMVENDORID

Bit Default & Field Name (ID): Description Range Access

0h SUBSYSTEMID 31:16 RW/O

0h SUBSYSTEMVENDORID 15:0 RW/O

3.1.10 (EXPANSION_ROM_BASEADDR)—Offset 30h

EXPANSION ROM base address

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 4

Default: 0h

332219-002 165 EMMC Interface (D30:F4)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 EXPANSION_ROM_BASE

Bit Default & Field Name (ID): Description Range Access

0h EXPANSION_ROM_BASE: Value of all zeros indicates no support for Expansion 31:0 RO ROM.

3.1.11 Capabilities Pointer (CAPABILITYPTR)—Offset 34h

This capability points to the PM Capability (0x80) structure.

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 4

Default: 80h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000010000000 RSVD CAPPTR_POWER

Bit Default & Field Name (ID): Description Range Access

0h 31:8 Reserved. RO

80h CAPPTR_POWER 7:0 RO

3.1.12 (INTERRUPTREG)—Offset 3Ch

INTERRUPTREG - Interrupt Register

Access Method

166 332219-002

EMMC Interface (D30:F4)

Type: CFG Register Device: 30 (Size: 32 bits) Function: 4

Default: 100h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000100000000 RSVD INTPIN INTLINE MAX_LAT MIN_GNT

Bit Default & Field Name (ID): Description Range Access

0h Maximum Latency (MAX_LAT): Value of 0 indicates device has no major 31:24 RO requirements for the settings of latency timers

0h MIN_GNT: TBD 23:16 RO

0h 15:12 Reserved. RO

1h Interrupt Pin (INTPIN): Interrupt Pin Value in this register is reflected from the 11:8 IPIN value in the private configuration space. RO For a single function device, this ideally is INTA.

0h Interrupt Line (INTLINE): It is used to communicate to software, the interrupt line 7:0 RW to which the interrupt pin is connected.

3.1.13 Power Management Capability ID Register (POWERCAPID)—Offset 80h

POWERCAPID - PowerManagement Capability ID

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 4

Default: 39001h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000111001000000000001 RSVD NXTCAP VERSION POWER_CAP PMESUPPORT

332219-002 167 EMMC Interface (D30:F4)

Bit Default & Field Name (ID): Description Range Access

PME_Support (PMESUPPORT): This 5-bit field indicates the power states in which the function can assert the PME#. A value of 0b for any bit indicates that the function is not capable of asserting the

0h PME# signal in that power state. 31:27 bit 27 = 1: PME# can be asserted from D0 RO bit28 = 1: PME# can be asserted from D1. bit 29 = 1: PME# can be asserted from D2. bit30 = 1:PME# can be asserted from D3hot bit 31 = 1:PME# can be asserted from D3cold.

0h 26:19 Reserved. RO

3h Version (VERSION): Indicates support for Revision 1.2 of the PCI Power 18:16 RO Management Specification.

Next Capability (NXTCAP): Points to the next capability structure. This points to 90h NULL if either ENABLE_PCI_IDLE_CAP is 0 or if Disable PCI Device Idle capability bit 15:8 RO is set as 1 in the private space. Else this points to PCI Device Idle capability structure at offset 90h

1h Power Management Capability (POWER_CAP): Indicates this is power 7:0 RO management capability.

3.1.14 Power Management Control and Status Register (PMECTRLSTATUS)—Offset 84h

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 4

Default: 8h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000001000 RSVD RSVD RSVD RSVD PMESTATUS PMEENABLE POWERSTATE NO_SOFT_RESET

Bit Default & Field Name (ID): Description Range Access

0h 31:16 Reserved. RO

0h PME Status (PMESTATUS): 0: Software clears the bit by writing a 1 to it. 15 1: This bit is set when the PME# signal is asserted independent of the state of the RW/1C PME Enable bit (bit 8 in this register)

0h 14:9 Reserved. RO

0h PME Enable (PMEENABLE): 1: Enables the function to assert PME#. 8 RW 0: PME# message on Sideband is disabled.

0h 7:4 Reserved. RO

168 332219-002

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Bit Default & Field Name (ID): Description Range Access

1h NO_SOFT_RESET: This bit indicates that devices transitioning from D3hot to D0 3 because of Powerstate commands do not perform an internal reset. Configuration RO Context is preserved.

0h 2 Reserved. RO

Power State (POWERSTATE): This field is used both to determine the current 0h power state and to set a new power state. The values are: 1:0 RW 00 D0 state 11 D3HOT state

3.1.15 General Purpose PCI RW Register1 (GEN_REGRW1)— Offset B0h

General Purpose PCI Register

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 4

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 GEN_REG_RW1

Bit Default & Field Name (ID): Description Range Access

0h GEN_REG_RW1 31:0 RW

3.1.16 General Purpose PCI RW Register2 (GEN_REGRW2)— Offset B4h

General Purpose PCI Register

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 4

Default: 0h

332219-002 169 EMMC Interface (D30:F4)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 GEN_REG_RW2

Bit Default & Field Name (ID): Description Range Access

0h GEN_REG_RW2 31:0 RW

3.1.17 General Purpose PCI RW Register3 (GEN_REGRW3)— Offset B8h

General Purpose PCI Register.

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 4

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 GEN_REG_RW3

Bit Default & Field Name (ID): Description Range Access

0h GEN_REG_RW3 31:0 RW

3.1.18 General Purpose PCI RW Register4 (GEN_REGRW4)— Offset BCh

General Purpose PCI Register

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 4

Default: 0h

170 332219-002

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3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 GEN_REG_RW4

Bit Default & Field Name (ID): Description Range Access

0h GEN_REG_RW4 31:0 RW

3.1.19 General Input Register (GEN_INPUT_REG)—Offset C0h

General Purpose Input Register.

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 4

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 GEN_REG_INPUT_RW

Bit Default & Field Name (ID): Description Range Access

0h GEN_REG_INPUT_RW 31:0 RO

3.2 EMMC Memory Mapped Registers Summary

These registers are memory mapped based on BAR0 defined in PCI configuration space.

332219-002 171 EMMC Interface (D30:F4)

Table 3-2. Summary of EMMC Memory Mapped Registers

Offset Offset Register Name (ID)—Offset Default Value Start End

SDMA System Address Register/Argument2 Register 0h 3h 0h (sdmasysaddr)—Offset 0h

4h 5h Block Size Register (blocksize)—Offset 4h 0h

6h 7h Block Count Register (blockcount)—Offset 6h 0h

8h Bh Argument1 Register (argument1)—Offset 8h 0h

Ch Dh Transfer Mode Register (transfermode)—Offset Ch 0h

Eh Fh Command Register (command)—Offset Eh 0h

10h 13h Response Register (Reponse 0)—Offset 10h 0h

20h 23h Buffer Data Port Register (dataport)—Offset 20h 0h

24h 27h Present State Register (presentstate)—Offset 24h 0h

28h 28h Host Control 1 Register (hostcontrol1)—Offset 28h 0h

29h 29h Power Control Register (powercontrol)—Offset 29h 0h

2Ah 2Ah Block Gap Control Register (blockgapcontrol)—Offset 2Ah 80h

2Bh 2Bh Wakeup Control Register (wakeupcontrol)—Offset 2Bh 0h

2Ch 2Dh Clock Control Register (clockcontrol)—Offset 2Ch 0h

2Eh 2Eh Timeout Control Register (timeoutcontrol)—Offset 2Eh 0h

2Fh 2Fh Software Reset Register (softwarereset)—Offset 2Fh 0h

30h 31h Normal Interrupt Status Register (normalintrsts)—Offset 30h 0h

32h 33h Error Interrupt Status Register (errorintrsts)—Offset 32h 0h

Normal Interrupt Status Enable Register (normalintrstsena)— 34h 35h 0h Offset 34h

Error Interrupt Status Enable Register (errorintrstsena)— 36h 37h 0h Offset 36h

Normal Interrupt Signal Enable Register (normalintrsigena)— 38h 39h 0h Offset 38h

Error Interrupt Signal Enable Register (errorintrsigena)—Offset 3Ah 3Bh 0h 3Ah

Auto CMD12 Error Status Register (autocmderrsts)—Offset 3Ch 3Dh 0h 3Ch

3Eh 3Fh Host Control2 Register (hostcontrol2)—Offset 3Eh 0h

40h 47h Capabilities Register (capabilities)—Offset 40h 0h

Maximum Current Capabilities Register (maxcurrentcap)— 48h 4Fh 0h Offset 48h

Force Event REGISTER for AUTO CMD Error Status 50h 51h 0h (ForceEventforAUTOCMDErrorStatus)—Offset 50h

Force Event Register for Error Interrupt Status 52h 53h 0h (forceeventforerrintsts)—Offset 52h

54h 54h ADMA Error Status Register (admaerrsts)—Offset 54h 0h

ADMA System Address Register0&1 (admasysaddr01)—Offset 58h 5Bh 0h 58h

5Ch 5Dh ADMA System Address Register1 (admasysaddr2)—Offset 5Ch 0h

5Eh 5Fh ADMA System Address Register1 (admasysaddr3)—Offset 5Eh 0h

Preset Value Register for Initialization (Preset Value 0)—Offset 60h 61h 3h 60h

172 332219-002

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Table 3-2. Summary of EMMC Memory Mapped Registers (Continued)

Offset Offset Register Name (ID)—Offset Default Value Start End

Preset Value Register for Default Speed (Preset Value 1)— 62h 63h 0h Offset 62h

Preset Value Register for High Speed (Preset Value 2)—Offset 64h 65h 0h 64h

66h 67h Preset Value Register for SDR12 (Preset Value 3)—Offset 66h 0h

68h 69h Preset Value Register for SDR25 (Preset Value 4)—Offset 68h 0h

6Ah 6Bh Preset Value Register for SDR50 (Preset Value 5)—Offset 6Ah 0h

6Ch 6Dh Preset Value Register for SDR104 (Preset Value 6)—Offset 6Ch 0h

6Eh 6Fh Preset Value Register for DDR50 (Preset Value 7)—Offset 6Eh 0h

70h 73h Boot Timeout Control Register (boottimeoutcnt)—Offset 70h 0h

FCh FDh Slot Interrupt Status Register (slotintrsts)—Offset FCh 0h

Host Controller Version Register (hostcontrollerver)—Offset FEh FFh 1002h FEh

3.2.1 SDMA System Address Register/Argument2 Register (sdmasysaddr)—Offset 0h

This register contains concatinates reg_sdmasysaddrlo and reg_sdmasysaddrhi

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 4

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 sdma_sysaddress

Bit Default & Field Name (ID): Description Range Access

0h SDMA System Address Register/Argument2 Register (sdma_sysaddress): 31:0 This register contains the physical system memory address used for DMA transfers or the second argument for the Auto CMD23.

3.2.2 Block Size Register (blocksize)—Offset 4h

This register is used to configure the number of bytes in a data block

Access Method

332219-002 173 EMMC Interface (D30:F4)

Type: MEM Register Device: 30 (Size: 16 bits) Function: 4

Default: 0h

15 12 8 4 0

0000000000000000 RSVD xfer_blocksize sdma_bufboundary

Bit Default & Field Name (ID): Description Range Access

0h 15 Reserved. RO

Host DMA Buffer Size (sdma_bufboundary): To perform long DMA transfer, System Address register shall be updated at every system boundary during DMA transfer. These bits specify the size of contiguous buffer in the system memory. These bits shall support when the DMA Support in the Capabilities register is set to 1 and this function is active when the DMA Enable in the Transfer Mode register is set to 1. 0h 000b - 4KB(Detects A11 Carry out) 14:12 001b - 8KB(Detects A12 Carry out) 010b - 16KB(Detects A13 Carry out) 011b - 32KB(Detects A14 Carry out) 100b - 64KB(Detects A15 Carry out) 101b -128KB(Detects A16 Carry out) 110b - 256KB(Detects A17 Carry out) 111b - 512KB(Detects A18 Carry out)

Transfer Block Size (xfer_blocksize): This register specifies the block size for block data transfers for CMD17, CMD18, CMD24, CMD25, and CMD53. It can be accessed only if no transaction is executing. Read operations during transfer return an invalid value and write operations shall be ignored.

0h 0000h - No Data Transfer 11:0 0001h - 1 Byte 0002h - 2 Bytes 0003h - 3 Bytes 0004h - 4 Bytes 01FFh - 511 Bytes 0200h - 512 Bytes 0800h - 2048 Bytes

3.2.3 Block Count Register (blockcount)—Offset 6h

This register is enabled when Block Count Enable in the Transfer Mode register is set to 1 and is valid only for multiple block transfers. The HC decrements the block count after each block transfer and stops when the count reaches zero. 0000h - Stop Count 0001h - 1 block 0002h - 2 blocks FFFFh - 65535 blocks.

Access Method

Type: MEM Register Device: 30 (Size: 16 bits) Function: 4

174 332219-002

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Default: 0h

15 12 8 4 0

0000000000000000 xfer_blockcount

Bit Default & Field Name (ID): Description Range Access

0h xfer_blockcount (xfer_blockcount): This Register specifies Block Size for Data 15:0 Transfers

3.2.4 Argument1 Register (argument1)—Offset 8h

The SD/eMMC Command Argument is specified as bit39- 8 of Command-Format.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 4

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 command_argument1

Bit Default & Field Name (ID): Description Range Access

0h command_argument1 (command_argument1): The Command Argument is 31:0 specified as bit39-8 of Command-Format

3.2.5 Transfer Mode Register (transfermode)—Offset Ch

This register is used to control the operations of data transfers

Access Method

Type: MEM Register Device: 30 (Size: 16 bits) Function: 4

332219-002 175 EMMC Interface (D30:F4)

Default: 0h

15 12 8 4 0

0000000000000000 RSVD xfermode_blkcntena xfermode_multiblksel xfermode_dataxferdir xfermode_dmaenable xfermode_autocmdena

Bit Default & Field Name (ID): Description Range Access

0h 15:6 Reserved. RO

Multi / Single Block Select (xfermode_multiblksel): This bit enables multiple 0h block data transfers. 5 0 - Single Block 1 - Multiple Block.

Data Transfer Direction Select (xfermode_dataxferdir): This bit defines the 0h 4 direction of data transfers. 0 - Write (Host to Card) 1 - Read (Card to Host)

Auto CMD Enable (xfermode_autocmdena): This field determines use of auto

0h command functions 3:2 00b - Auto Command Disabled 01b - Auto CMD12 Enable 10b - Auto CMD23 Enable.

Block Count Enable (xfermode_blkcntena): This bit is used to enable the Block 0h count register, which is only relevant for multiple block transfers. When this bit is 0, 1 the Block Count register is disabled, which is useful in executing an infinite transfer. 0 - Disable 1 - Enable.

DMA Enable (xfermode_dmaenable): If this bit is set to 1, a DMA operation shall 0h begin when the HD writes to the upper byte of Command register (00Fh). 0 0 - Disable 1 - Enable.

3.2.6 Command Register (command)—Offset Eh

This register is used to program the Command for host controller

Access Method

Type: MEM Register Device: 30 (Size: 16 bits) Function: 4

Default: 0h

176 332219-002

EMMC Interface (D30:F4)

15 12 8 4 0

0000000000000000 RSVD RSVD command_cmdtype command_cmdindex command_crcchkena command_datapresent command_indexchkena command_responsetype

Bit Default & Field Name (ID): Description Range Access

0h 15:14 Reserved. RO

0h Command Index (command_cmdindex): This bit shall be set to the command 13:8 number (CMD0-63, ACMD0-63).

0h Command Type (command_cmdtype): There are three types of special 7:6 commands; Suspend, Resume and Abort. These bits shall bet set to 00b for all other commands.

0h Data Present Select (command_datapresent): This bit is set to 1 to indicate that 5 data is present and shall be transferred using the DAT line.

0h Command Index Check Enable (command_indexchkena): If this bit is set to 1, 4 the HC shall check the index field in the response to see if it has the same value as the command index.

0h Command CRC Check Enable (command_crcchkena): If this bit is set to 1, the 3 HC shall check the CRC field in the response.

0h 2 Reserved. RO

0h Response Type Select (command_responsetype): 00 - No Response 1:0 01 - Response length 136 10 - Response length 48.

3.2.7 Response Register (Reponse 0)—Offset 10h

The response registers contains the 128 bit response received from the External Device . The response registers are available at the following offset: Response Register 0: offset 0x010h Response Register 1: offset 0x012h Response Register 2: offset 0x014h Response Register 3: offset 0x016h Response Register 4: offset 0x018h Response Register 5: offset 0x01Ah Response Register 6: offset 0x01Ch Response Register 7: offset 0x01Eh.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 4

Default: 0h

332219-002 177 EMMC Interface (D30:F4)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 command_response

Bit Default & Field Name (ID): Description Range Access

0h command_response (command_response): R[] refers to a bit range within the 31:0 response data as transmitted on the SD Bus, REP[] refers to a bit

3.2.8 Buffer Data Port Register (dataport)—Offset 20h

The Host Controller Buffer can be accessed through this 32-bit Data Port Register.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 4

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 sdhcdmactrl_piobufrddata

Bit Default & Field Name (ID): Description Range Access

0h sdhcdmactrl_piobufrddata: The Host Controller Buffer can be accessed through 31:0 RW this 32-bit Data Port Register.

3.2.9 Present State Register (presentstate)—Offset 24h

The Host Driver can get status of the Host Controller from this 32-bit read-only register

Access Method

178 332219-002

EMMC Interface (D30:F4)

Type: MEM Register Device: 30 (Size: 32 bits) Function: 4

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD RSVD Re-Tune Data Activity Data sdif_wp_dsync sdif_cd_n_dsync sdif_cmdin_dsync sdif_dat7in_dsync sdif_dat6in_dsync sdif_dat5in_dsync sdif_dat4in_dsync sdif_dat3in_dsync sdif_dat2in_dsync sdif_dat1in_dsync sdif_dat0in_dsync presentstate_inhibitdat presentstate_inhibitcmd sdhcdmactrl_rdxferactive sdhcdmactrl_piobufrdena sdhcdmactrl_wrxferactive sdhcdmactrl_piobufwrena sdhccarddet_inserted_dsync sdhccarddet_statestable_dsync

Bit Default & Field Name (ID): Description Range Access

0h 31:29 Reserved. RO

0h DAT7 Line Signal Level (sdif_dat7in_dsync): This status is used to check DAT 28 RO line level to recover from errors, and for debugging.

0h DAT6 Line Signal Level (sdif_dat6in_dsync): This status is used to check DAT 27 RO line level to recover from errors, and for debugging.

0h DAT5 Line Signal Level (sdif_dat5in_dsync): This status is used to check DAT 26 RO line level to recover from errors, and for debugging.

0h DAT4 Line Signal Level (sdif_dat4in_dsync): This status is used to check DAT 25 RO line level to recover from errors, and for debugging.

0h CMD Line Signal Level (sdif_cmdin_dsync): This status is used to check CMD line 24 RO level to recover from errors, and for debugging

0h DAT3 Line Signal Level (sdif_dat3in_dsync): This status is used to check DAT 23 RO line level to recover from errors, and for debugging. This is

0h DAT2 Line Signal Level (sdif_dat2in_dsync): This status is used to check DAT 22 RO line level to recover from errors, and for debugging. This is

0h DAT1 Line Signal Level (sdif_dat1in_dsync): This status is used to check DAT 21 RO line level to recover from errors, and for debugging. This is

0h DAT0 Line Signal Level (sdif_dat0in_dsync): This status is used to check DAT 20 RO line level to recover from errors, and for debugging. This is

Write Protect Switch Pin Level (sdif_wp_dsync): The Write Protect Switch is 0h 19 supported for memory and combo cards. This bit reflects the SDWP# pin. 0 - Write RO protected (SDWP# = 0) 1 - Write enabled (SDWP# = 1).

Card Level Detect (sdif_cd_n_dsync): This bit reflects the inverse value of the 0h SDCD# pin. 18 RO 0 - No Card present (SDCD# = 1) 1 - Card present (SDCD# = 0).

332219-002 179 EMMC Interface (D30:F4)

Bit Default & Field Name (ID): Description Range Access

Card State Stable (sdhccarddet_statestable_dsync): This bit is used for testing. If it is 0, the Card Detect Pin Level is not stable. If this bit is set to 1, it means the 0h Card Detect Pin Level is stable. The Software Reset For All in the Software Reset 17 RO Register shall not affect this bit. 0 - Reset of Debouncing 1 - No Card or Inserted.

Card Inserted (sdhccarddet_inserted_dsync): This bit indicates whether a card 0h has been inserted. Changing from 0 to 1 generates a Card Insertion Interrupt in the 16 RO Normal Interrupt Status register and changing from 1 to 0 generates a Card Removal Interrupt in the Normal Interrupt Status register.

0h 15:12 Reserved. RO

Buffer Read Enable (sdhcdmactrl_piobufrdena): This status is used for non- DMA read transfers. This read only flag indicates that valid data exists in the host side buffer status. 0h If this bit is 1, readable data exists in the buffer. 11 A change of this bit from 1 to 0 occurs when all the block data is read from the buffer. RO A change of this bit from 0 to 1 occurs when all the block data is ready in the buffer and generates the Buffer Read Ready Interrupt. 0 - Read Disable 1 - Read Enable

Buffer Write Enable (sdhcdmactrl_piobufwrena): This status is used for non- 0h DMA write transfers. This read only flag indicates if space is available for write data. 10 RO If this bit is 1, data can be written to the buffer. A change of this bit from 1 to 0 occurs when all the block data is written to the buffer.

Read Transfer Active (sdhcdmactrl_rdxferactive): This status is used for detecting completion of a read transfer. This bit is set to 1 for either of the following conditions: • After the end bit of the read command • When writing a 1 to continue Request in the Block Gap Control register to restart a

0h read transfer. 9 This bit is cleared to 0 for either of the following conditions: RO • When the last data block as specified by block length is transferred to the system. • When all valid data blocks have been transferred to the system and no current block transfers are being sent as a result of the Stop At Block Gap Request set to 1. A transfer complete interrupt is generated when this bit changes to 0. 1 - Transferring data 0 - No valid data

Write Transfer Active (sdhcdmactrl_wrxferactive): This status indicates a write transfer is active. If this bit is 0, it means no valid write data exists in the HC. This bit is set in either of the following cases: • After the end bit of the write command. • When writing a 1 to Continue Request in the Block Gap Control register to restart a write transfer. This bit is cleared in either of the following cases: 0h 8 • After getting the CRC status of the last data block as specified by the transfer count RO (Single or Multiple) • After getting a CRC status of any block where data transmission is about to be stopped by a Stop At Block Gap Request. During a write transaction, a Block Gap Event interrupt is generated when this bit is changed to 0, as a result of the Stop At Block Gap Request being set. This status is useful for the HD in determining when to issue commands during write busy. 1 - transferring data 0 - No valid data

0h 7:4 Reserved. RO

Re-Tuning Request (Re-Tune): Host Controller may request Host Driver to execute re-tuning sequence by setting this bit when the data window is shifted by temperature drift and any issue receiving the correct data. This bit is cleared when a command is issued with setting Execute Tuning in the Host Control 2 register. Changing of this bit from 0 to 1 generates Re-Tuning Event. 0h This bit is cleared when a command is issued with setting Execute Tuning in the Host 3 RO Control 2 register. Changing of this bit from 0 to 1 generates Re-Tuning Event. Refer to Normal Interrupt registers for more detail. This bit isn't set to 1 if Sampling Clock Select in the Host Control 2 register is set to 0 (using fixed sampling clock). 1: Sampling clock needs re-tuning 0: Fixed or well tuned sampling clock

180 332219-002

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Bit Default & Field Name (ID): Description Range Access

0h DATA line Active (Data Activity): This bit indicates whether one of the DAT line on 2 RO SD bus is in use. 1 - DAT line active 0 - DAT line inactive

Command Inhibit (DAT) (presentstate_inhibitdat): This status bit is generated if either the DAT Line Active or the Read transfer Active is set to 1. If this bit is 0, it 0h indicates the HC can issue the next SD command. Commands with busy signal belong 1 RO to Command Inhibit (DAT). Changing from 1 to 0 generates a Transfer Complete interrupt in the Normal interrupt status register.

Command Inhibit (CMD) (presentstate_inhibitcmd): If this bit is 0, it indicates the CMD line is not in use and the HC can issue a SD command using the CMD line. This bit is set immediately after the Command register (00Fh) is written. This bit is cleared when the command response is received. Even if the Command Inhibit (DAT) is set to 1, Commands using only the CMD line can be issued if this bit is 0. Changing from 1 to 0 generates a Command complete 0h interrupt in the Normal Interrupt Status register. If the HC cannot issue the command 0 because of a command conflict error or because of Command Not Issued By Auto RO CMD12 Error, this bit shall remain 1 and the Command Complete is not set. Status issuing Auto CMD12 is not read from this bit. Auto CMD12 and Auto CMD23 consist of two responses. In this case, this bit is not cleared by the response of CMD12 or CMD23 but cleared by the response of a read/ write command. Status issuing Auto CMD12 is not read from this bit. So if a command is issued during Auto CMD12 operation, Host Controller shall manage to issue two commands: CMD12 and a command set by Command register.

3.2.10 Host Control 1 Register (hostcontrol1)—Offset 28h

This register is used to program DMA modes, LED Control, Data Transfer Width, High Speed Enable, Card detect test level and signal selection

Access Method

Type: MEM Register Device: 30 (Size: 8 bits) Function: 4

Default: 0h

74 0

00000000 hostctrl1_datawidth hostctrl1_ledcontrol hostctrl1_dmaselect hostctrl1_cdtestlevel hostctrl1_cdsigselect hostctrl1_extdatawidth hostctrl1_highspeedena

332219-002 181 EMMC Interface (D30:F4)

Bit Default & Field Name (ID): Description Range Access

Card Detect Signal Detection (hostctrl1_cdsigselect): This bit selects source for 0h 7 card detection. RW 1- The card detect test level is selected 0- SDCD# is selected (for normal use).

Card Detect Test Level (hostctrl1_cdtestlevel): This bit is enabled while the Card Detect Signal Selection is set to 1 and it indicates card inserted or not. 0h 6 Generates (card ins or card removal) interrupt when the normal int sts enable bit is RW set. 1 - Card Inserted 0 - No Card.

Extended Data Transfer Width (hostctrl1_extdatawidth): This bit controls 8-bit 0h bus width mode for embedded device. Support of this function is indicated in 8-bit 5 Support for Embedded Device in the Capabilities register. RW If a device supports 8-bit bus mode, this bit may be set to 1. If this bit is 0, bus width is controlled by Data Transfer Width in the Host Control 1 register.

DMA Select (hostctrl1_dmaselect): One of supported DMA modes can be selected. The host driver shall check support of DMA modes by referring the 0h Capabilities register. 4:3 00 - SDMA is selected RW 01 - 32-bit Address ADMA1 is selected 10 - 32-bit Address ADMA2 is selected 11 - 64-bit Address ADMA2 is selected.

High Speed Enable (hostctrl1_highspeedena): This bit is optional. Before setting this bit, the HD shall check the High Speed Support in the capabilities register. If this 0h 2 bit is set to 0 (default), the HC outputs CMD line and DAT lines at the falling edge of the SD clock (up to 25 MHz/ 20MHz for MMC). If this bit is set to 1, the HC outputs CMD line and DAT lines at the rising edge of the SD clock (up to 50 MHz for SD/52MHz for MMC)/ 208Mhz.

Data Transfer Width (hostctrl1_datawidth): This bit selects the data width of 0h 1 the HC. The HD shall select it to match the data width of the SD card. 1 - 4 bit mode 0 - 1 bit mode.

LED Control (hostctrl1_ledcontrol): This bit is used to caution the user not to remove the card while the SD card is being accessed. If the software is going to issue 0h 0 multiple SD commands, this bit can be set during all transactions. It is not necessary RW to change for each transaction. 1 - LED on 0 - LED off.

3.2.11 Power Control Register (powercontrol)—Offset 29h

This register is used to program the SD Bus power and voltage level

Access Method

Type: MEM Register Device: 30 (Size: 8 bits) Function: 4

Default: 0h

74 0

00000000 RSVD emmc_hwreset pwrctrl_sdbuspower pwrctrl_sdbusvoltage

182 332219-002

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Bit Default & Field Name (ID): Description Range Access

0h 7:5 Reserved. RO

eMMC HW Reset (emmc_hwreset): Hardware reset signal is generated for eMMC 0h 4 card when this bit is set RW '1' - Drives the hardware reset pin as ZERO (Active LOW to eMMC card) '0' - Deassert the hardware reset pin.

SD Bus Voltage Select (pwrctrl_sdbusvoltage): By setting these bits, the HC selects the voltage level for the SD card. Before setting this register, the HC shall 0h check the voltage support bits in the capabilities register. If unsupported voltage is 3:1 selected, the Host System shall not supply SD bus voltage RW 111b - 3.3 V 110b - 3.0 V 101b - 1.8 V.

SD Bus Power (pwrctrl_sdbuspower): Before setting this bit, the SD host driver 0h shall set SD Bus Voltage Select. If the HC detects the No Card State, this bit shall be 0 cleared. RW 1 - Power on 0 - Power off.

3.2.12 Block Gap Control Register (blockgapcontrol)—Offset 2Ah

This register is used to program the block gap request, read wait control and interrupt at block gap.

Access Method

Type: MEM Register Device: 30 (Size: 8 bits) Function: 4

Default: 80h

74 0

10000000 blkgapctrl_spimode blkgapctrl_continue blkgapctrl_interrupt blkgapctrl_rdwaitctrl blkgapctrl_bootenable blkgapctrl_bootackena blkgapctrl_altbootmode blkgapctrl_stopatblkgap

Bit Default & Field Name (ID): Description Range Access

Boot Acknowledge Check (blkgapctrl_bootackena): To check for the boot 1h 7 acknowledge in boot operation. RW 1 - wait for boot ack from eMMC card 0 - Will not wait for boot ack from eMMC card.

Alternate Boot Enable (blkgapctrl_altbootmode): To start boot code access in 0h alternative mode. 6 RW 1- To start alternate boot mode access 0 - To stop alternate boot mode access.

0h Boot Code Access (blkgapctrl_bootenable): To start boot code access 5 1- To start boot code access RW 0 - To stop boot code access

332219-002 183 EMMC Interface (D30:F4)

Bit Default & Field Name (ID): Description Range Access

0h SPI mode enable (blkgapctrl_spimode): SPI mode enable bit. 4 1- SPI mode RW 0 - SD mode

Interrupt at Block Gap (blkgapctrl_interrupt): This bit is valid only in 4-bit mode of the SDIO card and selects a sample point in the interrupt cycle. 0h 3 Setting to 1 enables interrupt detection at the block gap for a multiple block transfer. RW If the card cannot signal an interrupt during a multiple block transfer, this bit should be set to 0. When the HD detects an SD card insertion, it shall set this bit according to the CCCR of the card.

Read Wait Control (blkgapctrl_rdwaitctrl): The read wait function is optional for SDIO cards. If the card supports read wait, set this bit to enable use of the read wait protocol to stop read data using DAT[2] line. Otherwise the HC has to stop the SD 0h clock to hold read data, which restricts commands generation. When the HD detects 2 a card insertion, it shall set this bit according to the CCCR of the card. If the card RW does not support read wait, this bit shall never be set to 1 otherwise DAT line conflict may occur. If this bit is set to 0, Suspend / Resume cannot be supported 1 - Enable Read Wait Control 0 - Disable Read Wait Control

Continue Request (blkgapctrl_continue): This bit is used to restart a transaction which was stopped using the Stop At Block Gap Request. To cancel stop at the block gap, set Stop At block Gap Request to 0 and set this bit to restart the transfer. 0h 1 The HC automatically clears this bit in either of the following cases: RW 1) In the case of a read transaction, the DAT Line Active changes from 0 to 1 as a read transaction restarts. 2) In the case of a write transaction, the Write transfer active changes from 0 to 1 as the write transaction restarts.

Stop At Block Gap Request (blkgapctrl_stopatblkgap): This bit is used to stop 0h executing a transaction at the next block gap for non- DMA,SDMA and ADMA 0 transfers. Until the transfer complete is set to 1, indicating a transfer completion the RW HD shall leave this bit set to 1. Clearing both the Stop At Block Gap Request and Continue Request shall not cause the transaction to restart.

3.2.13 Wakeup Control Register (wakeupcontrol)—Offset 2Bh

This register is used to program the wakeup functionality.

Access Method

Type: MEM Register Device: 30 (Size: 8 bits) Function: 4

Default: 0h

74 0

00000000 RSVD wkupctrl_cardremoval wkupctrl_cardinsertion wkupctrl_cardinterrupt

184 332219-002

EMMC Interface (D30:F4)

Bit Default & Field Name (ID): Description Range Access

0h 7:3 Reserved. RO

Wakeup Event On SD Card Removal (wkupctrl_cardremoval): This bit enables 0h wakeup event via Card Removal assertion in the Normal Interrupt Status register. 2 FN_WUS (Wake up Support) in CIS does not affect this bit. RW 1 - Enable 0 – Disable.

Wakeup On Card Insertion (wkupctrl_cardinsertion): This bit enables wakeup 0h event via Card Insertion assertion in the Normal Interrupt Status register. FN_WUS 1 (Wake up Support) in CIS does not affect this bit. RW 1 - Enable 0 – Disable

Wakeup Event Enable On Card Interrupt (wkupctrl_cardinterrupt): This bit 0h enables wakeup event via Card Interrupt assertion in the Normal Interrupt Status 0 register. This bit can be set to 1 if FN_WUS (Wake Up Support) in CIS is set to 1. RW 1 - Enable 0 - Disable.

3.2.14 Clock Control Register (clockcontrol)—Offset 2Ch

This register is used to program the Clock frequency select, generator select, Clock enable,Internal Clock state fields.

Access Method

Type: MEM Register Device: 30 (Size: 16 bits) Function: 4

Default: 0h

15 12 8 4 0

0000000000000000 RSVD clkctrl_sdclkena clkctrl_intclkena clkctrl_clkgensel clkctrl_sdclkfreqsel clkctrl_sdclkfreqsel_upperbits sdhcclkgen_intclkstable_dsync

332219-002 185 EMMC Interface (D30:F4)

Bit Default & Field Name (ID): Description Range Access

SDCLK Frequency Select (clkctrl_sdclkfreqsel): This register is used to select the frequency of the SDCLK pin. The frequency is not programmed directly; rather this register holds the divisor of the Base Clock Frequency For SD clock in the capabilities register. Only the following settings are allowed. 80h - base clock divided by 256 40h - base clock divided by 128 0h 20h - base clock divided by 64 15:8 RW 10h - base clock divided by 32 08h - base clock divided by 16 04h - base clock divided by 8 02h - base clock divided by 4 01h - base clock divided by 2 00h - base clock(10MHz-63MHz) Setting 00h specifies the highest frequency of the SD Clock.

0h Upper Bits of SDCLK Frequency Select (clkctrl_sdclkfreqsel_upperbits): Bit 7:6 RW 07-06 is assigned to bit 09-08 of clock divider in SDCLK Frequency Select.

Clock Generator Select (clkctrl_clkgensel): This bit is used to select the clock generator mode in SDCLK Frequency Select. If the Programmable Clock Mode is supported (non-zero value is set to Clock Multiplier in the Capabilities register), this 0h bit attribute is RW, and if not supported,this bit attribute is RO and zero is read. This 5 bit depends on the setting of Preset Value Enable in the Host Control 2 register. If the RW Preset Value Enable = 0, this bit is set by Host Driver. If the Preset Value Enable = 1, this bit is automatically set to a value specified in one of Preset Value registers. 1: Programmable Clock Mode 0: Divided Clock Mode.

0h 4:3 Reserved. RO

0h SD Clock Enable (clkctrl_sdclkena): The HC shall stop SDCLK when writing this 2 RW bit to 0. SDCLK frequency Select can be changed when this bit is 0.

0h Internal Clock Stable (sdhcclkgen_intclkstable_dsync): This bit is set to 1 1 when SD clock is stable after writing to Internal Clock Enable in this register to 1. The RO SD Host Driver shall wait to set SD Clock Enable until this bit is set to 1.

Internal Clock Enable (clkctrl_intclkena): This bit is set to 0 when the HD is not 0h using the HC or the HC awaits a wakeup event. The HC should stop its internal clock 0 RW to go very low power state. 1 - Oscillate 0 - Stop.

3.2.15 Timeout Control Register (timeoutcontrol)—Offset 2Eh

This value determines the interval by which DAT line time-outs are detected. Refer to the Data Time-out Error in the Error Interrupt Status register for information on factors that dictate time-out generation. Time-out clock frequency will be generated by dividing the sd clock TMCLK by this value. When setting this register, prevent inadvertent time-out events by clearing the Data Time-out Error Status Enable (in the Error Interrupt Status Enable register) 1110 - TMCLK * 2^27 0001 - TMCLK * 2^14 0000 - TMCLK * 2^13.

Access Method

Type: MEM Register Device: 30 (Size: 8 bits) Function: 4

Default: 0h

186 332219-002

EMMC Interface (D30:F4)

74 0

00000000 RSVD timeout_ctrvalue

Bit Default & Field Name (ID): Description Range Access

0h 7:4 Reserved. RO

0h Data Timeout Counter Value (timeout_ctrvalue): This value determines the 3:0 RW interval by which DAT line time-outs are detected.

3.2.16 Software Reset Register (softwarereset)—Offset 2Fh

This register is used to program the software reset for data, command and for all.

Access Method

Type: MEM Register Device: 30 (Size: 8 bits) Function: 4

Default: 0h

74 0

00000000 RSVD swreset_for_all swreset_for_dat swreset_for_cmd

332219-002 187 EMMC Interface (D30:F4)

Bit Default & Field Name (ID): Description Range Access

0h 7:3 Reserved. RO

Software Reset for DAT Line (swreset_for_dat): Only part of data circuit is reset. The following registers and bits are cleared by this bit: Buffer Data Port Register - Buffer is cleared and initialized. Present State register - Buffer read Enable - Buffer write Enable - Read Transfer Active - Write Transfer Active 0h - DAT Line Active 2 RW - Command Inhibit (DAT) Block Gap Control register - Continue Request - Stop At Block Gap Request Normal Interrupt Status register - Buffer Read Ready - Buffer Write Ready - Block Gap Event - Transfer Complete 1 - Reset 0 - Work.

Software Reset for CMD Line (swreset_for_cmd): Only part of command circuit is reset. The following registers and bits are cleared by this bit: Present State register 0h - Command Inhibit (CMD) 1 RW Normal Interrupt Status register - Command Complete 1 - Reset 0 - Work.

Software Reset for All (swreset_for_all): This reset affects the entire HC except for the card detection circuit. Register bits of type ROC, RW, RW1C, RWAC are cleared to 0. During its initialization, the HD shall set this bit to 1 to reset the HC. The HC shall reset this bit to 0 when capabilities registers are valid and the HD can read 0h 0 them. Additional use of Software Reset For All may not affect the value of the RW Capabilities registers. If this bit is set to 1, the SD card shall reset itself and must be re initialized by the HD. 1 - Reset 0 - Work

3.2.17 Normal Interrupt Status Register (normalintrsts)—Offset 30h

This register gives the status of all the interrupts

Access Method

Type: MEM Register Device: 30 (Size: 16 bits) Function: 4

Default: 0h

188 332219-002

EMMC Interface (D30:F4)

15 12 8 4 0

0000000000000000 reg_errorintrsts normalintrsts_intc normalintrsts_inta normalintrsts_intb normalintrsts_cardintsts normalintrsts_cardinssts normalintrsts_rcvbootack normalintrsts_bufrdready normalintrsts_cardremsts normalintrsts_bufwrready normalintrsts_blkgapevent normalintrsts_xfercomplete normalintrsts_dmainterrupt normalintrsts_cmdcomplete normalintrsts_bootcomplete normalintrsts_retuningevent

Bit Default & Field Name (ID): Description Range Access

Error Interrupt (reg_errorintrsts): If any of the bits in the Error Interrupt Status 0h Register are set, then this bit is set. Therefore the HD can test for an error by 15 checking this bit first. RO 0 - No Error 1 – Error.

Boot terminate Interrupt (normalintrsts_bootcomplete): This status is set if 0h 14 the boot operation get terminated RW1C 0 - Boot operation is not terminated 1 - Boot operation is terminated.

Boot Acknowledge Rcv (normalintrsts_rcvbootack): This status is set if the 0h boot acknowledge is received from device. 13 RW1C 0 - Boot ack is not received 1 - Boot ack is received.

Re-Tuning Event (normalintrsts_retuningevent): This status is set if Re-Tuning Request in the Present State register changes from 0 to 1. Host Controller requests 0h Host Driver to perform re-tuning for next data transfer. Current data transfer (not 12 RO large block count) can be completed without retuning. 1 Re-Tuning should be performed 0 Re-Tuning is not required.

0h INT_C_ Status (normalintrsts_intc): This status is set if INT_C is enabled and 11 INT_C# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by RO resetting the INT_C interrupt factor.

0h INT_B_Status (normalintrsts_intb): This status is set if INT_B is enabled and 10 INT_B# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by RO resetting the INT_B interrupt factor.

0h INT_A Status (normalintrsts_inta): This status is set if INT_A is enabled and 9 INT_A# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by RO resetting the INT_A interrupt factor.

Card Interrupt (normalintrsts_cardintsts): In 1-bit mode, the HC shall detect the Card Interrupt without SD Clock to support wakeup. In 4-bit mode, the card 0h interrupt signal is sampled during the interrupt cycle, so there are some sample 8 delays between the interrupt signal from the card and the interrupt to the Host RO system. 0 - No Card Interrupt 1 - Generate Card Interrupt.

Card Removal (normalintrsts_cardremsts): This status is set if the Card Inserted in the Present State register changes from 1 to 0. When the HD writes this bit to 1 to 0h clear this status the status of the Card Inserted in the Present State register should 7 RW1C be confirmed. 0 - Card State Stable or Debouncing 1 - Card Removed.

0h Card Insertion (normalintrsts_cardinssts): This status is set if the Card Inserted 6 RW1C in the Present State register changes from 0 to 1.

0h Buffer Read Ready (normalintrsts_bufrdready): This status is set if the Buffer 5 Read Enable changes from 0 to 1.

0h Buffer Write Ready (normalintrsts_bufwrready): This status is set if the Buffer 4 RW1C Write Enable changes from 0 to 1.

332219-002 189 EMMC Interface (D30:F4)

Bit Default & Field Name (ID): Description Range Access

0h DMA Interrupt (normalintrsts_dmainterrupt): This status is set if the HC 3 RW1C detects the Host DMA Buffer Boundary in the Block Size Register.

0h Block Gap Event (normalintrsts_blkgapevent): If the Stop At Block Gap Request 2 RW1C in the Block Gap Control Register is set, this bit is set.

0h Transfer Complete (normalintrsts_xfercomplete): This bit is set when a read / 1 RW1C write transaction is completed.

Command Complete (normalintrsts_cmdcomplete): This bit is set when we get 0h the end bit of the command response (Except Auto CMD12 and Auto CMD23). 0 RW1C 0 - No Command Complete 1 - Command Complete

3.2.18 Error Interrupt Status Register (errorintrsts)—Offset 32h

This register gives the status of the error interrupts

Access Method

Type: MEM Register Device: 30 (Size: 16 bits) Function: 4

Default: 0h

15 12 8 4 0

0000000000000000 RSVD RSVD errorintrsts_hosterror errorintrsts_admaerror errorintrsts_cmdcrcerror errorintrsts_datacrcerror errorintrsts_currlimiterror errorintrsts_autocmderror errorintrsts_cmdindexerror errorintrsts_cmdendbiterror errorintrsts_dataendbiterror errorintrsts_cmdtimeouterror errorintrsts_datatimeouterror

Bit Default & Field Name (ID): Description Range Access

0h 15:13 Reserved. RO

Target Response Error (errorintrsts_hosterror): Occurs when detecting ERROR 0h 12 in DMA transaction 0 - no error 1 – error.

0h 11:10 Reserved. RO

ADMA Error (errorintrsts_admaerror): This bit is set when the Host Controller 0h detects errors during ADMA based data transfer. The state of the ADMA at an error 9 occurrence is saved in the ADMA Error Status Register. RW 1- Error 0- No error.

0h Auto CMD Error (errorintrsts_autocmderror): This bit is set when detecting that 8 RW one of the bits D00-D04 in Auto CMD Error Status register has changed from 0 to 1.

190 332219-002

EMMC Interface (D30:F4)

Bit Default & Field Name (ID): Description Range Access

0h Current Limit Error (errorintrsts_currlimiterror): By setting the SD Bus Power 7 RW bit in the Power Control Register, the HC is requested to supply power for the SD Bus.

Data End Bit Error (errorintrsts_dataendbiterror): Occurs when detecting 0 at 0h the end bit position of read data which uses the DAT line or the end bit position of the 6 CRC status. RW 0 - No Error 1 – Error.

Data CRC Error (errorintrsts_datacrcerror): Occurs when detecting CRC error 0h when transferring read data which uses the DAT line or when detecting the Write CRC 5 Status having a value of other than “010”. RW 0 - No Error 1 – Error.

Data Timeout Error (errorintrsts_datatimeouterror): Occurs when detecting one of following timeout conditions. 1. Busy Timeout for R1b, R5b type. 0h 4 2. Busy Timeout after Write CRC status RW 3. Write CRC status Timeout 4. Read Data Timeout 0 - No Error 1 – Timeout.

Command Index Error (errorintrsts_cmdindexerror): Occurs if a Command 0h Index error occurs in the Command Response. 3 RW 0 - No Error 1 – Error.

Command End Bit Error (errorintrsts_cmdendbiterror): Occurs when detecting 0h 2 that the end bit of a command response is 0. RW 0 - No Error 1 - End Bit Error Generated.

0h Command CRC Error (errorintrsts_cmdcrcerror): 0 - No Error 1 RW 1 - CRC Error Generated.

Command Timeout Error (errorintrsts_cmdtimeouterror): Occurs only if the no 0h response is returned within 64 SDCLK cycles from the end bit of the command. 0 RW 0 - No Error 1 – Timeout.

3.2.19 Normal Interrupt Status Enable Register (normalintrstsena)—Offset 34h

This register is used to enable the normal interrupt status register fields

Access Method

Type: MEM Register Device: 30 (Size: 16 bits) Function: 4

Default: 0h

332219-002 191 EMMC Interface (D30:F4)

15 12 8 4 0

0000000000000000 RSVD sdhcregset_cardintstsena sdhcregset_cardinsstsena sdhcregset_cardremstsena normalintrsts_enableregbit9 normalintrsts_enableregbit5 normalintrsts_enableregbit4 normalintrsts_enableregbit3 normalintrsts_enableregbit2 normalintrsts_enableregbit1 normalintrsts_enableregbit0 normalintrsts_enableregbit14 normalintrsts_enableregbit13 normalintrsts_enableregbit12 normalintrsts_enableregbit11 normalintrsts_enableregbit10

Bit Default & Field Name (ID): Description Range Access

0h 15 Reserved. RO

0h Boot terminate Interrupt enable (normalintrsts_enableregbit14): This status 14 is set if the boot operation gets terminated.>BR> 0 - Masked RW 1 – Enabled.

Boot ack rcv enable (normalintrsts_enableregbit13): This status is set if the 0h boot acknowledge is received from device. 13 RW 0 - Masked 1 – Enabled.

Re-Tuning Event Status Enable (normalintrsts_enableregbit12): This status is 0h 12 set if Re-Tuning Request in the Present State register changes from 0 to 1. 0 - Masked 1 – Enabled.

INT_C Status Enable (normalintrsts_enableregbit11): If this bit is set to 0, the 0h Host Controller shall clear the interrupt request to the System. The Host Driver may 11 RW clear this bit before servicing the INT_C and may set this bit again after all interrupt requests to INT_C pin are cleared to prevent inadvertent interrupts

INT_B Status Enable (normalintrsts_enableregbit10): If this bit is set to 0, the 0h Host Controller shall clear the interrupt request to the System. The Host Driver may 10 RW clear this bit before servicing the INT_B and may set this bit again after all interrupt requests to INT_B pin are cleared to prevent inadvertent interrupts.

INT_A Status Enable (normalintrsts_enableregbit9): If this bit is set to 0, the 0h 9 Host Controller shall clear the interrupt request to the System. The Host Driver may RW clear this bit before servicing the INT_A and may set this bit again after all interrupt requests to INT_A pin are cleared to prevent inadvertent interrupts.

0h Card Interrupt Status Enable (sdhcregset_cardintstsena): If this bit is set to 0, 8 the HC shall clear Interrupt request to the System. The Card Interrupt detection is RW stopped when this bit is cleared and restarted when this bit is set to 1.

0h Card Removal Status Enable (sdhcregset_cardremstsena): This status is set if 7 RW the Card Inserted in the Present State register changes from 1 to 0.

0h Card Insertion Status Enable (sdhcregset_cardinsstsena): This status is set if 6 RW the Card Inserted in the Present State register changes from 0 to 1.

0h Buffer Read Ready Status Enable (normalintrsts_enableregbit5): This status 5 RW is set if the Buffer Read Enable changes from 0 to 1.

0h Buffer Write Ready Status Enable (normalintrsts_enableregbit4): This status 4 RW is set if the Buffer Write Enable changes from 0 to 1.

0h DMA Interrupt Status Enable (normalintrsts_enableregbit3): This status is set 3 RW if the HC detects the Host DMA Buffer Boundary in the Block Size register.

192 332219-002

EMMC Interface (D30:F4)

Bit Default & Field Name (ID): Description Range Access

0h Block Gap Event Status Enable (normalintrsts_enableregbit2): If the Stop At 2 RW Block Gap Request in the BlockGap Control Register is set, this bit is set.

0h Transfer Complete Status Enable (normalintrsts_enableregbit1): This bit is 1 RW set when a read / write transaction is completed.

0h Command Complete Status Enable (normalintrsts_enableregbit0): This bit is 0 RW set when we get the end bit of the command response.

3.2.20 Error Interrupt Status Enable Register (errorintrstsena)— Offset 36h

This register is used to enable the Error Interrupt Status register fields.

Access Method

Type: MEM Register Device: 30 (Size: 16 bits) Function: 4

Default: 0h

15 12 8 4 0

0000000000000000 RSVD RSVD errorintrsts_enableregbit9 errorintrsts_enableregbit8 errorintrsts_enableregbit7 errorintrsts_enableregbit6 errorintrsts_enableregbit5 errorintrsts_enableregbit4 errorintrsts_enableregbit3 errorintrsts_enableregbit2 errorintrsts_enableregbit1 errorintrsts_enableregbit0 errorintrsts_enableregbit12 errorintrsts_enableregbit10

Bit Default & Field Name (ID): Description Range Access

0h 15:13 Reserved. RO

0h Target Response Error /Host Error Status Enable 12 (errorintrsts_enableregbit12): 0 - Masked 1 - Enabled

0h 11 Reserved. RO

0h Tuning error status enable (errorintrsts_enableregbit10): 0 - Masked 10 1 - Enabled

0h ADMA Error Status Enable (errorintrsts_enableregbit9): 0 - Masked 9 1 - Enabled

0h Auto CMD12 Error Status Enable (errorintrsts_enableregbit8): 0 - Masked 8 1 - Enabled

0h Current Limit Error Status Enable (errorintrsts_enableregbit7): 0 - Masked 7 1 - Enabled

332219-002 193 EMMC Interface (D30:F4)

Bit Default & Field Name (ID): Description Range Access

0h Data End Bit Error Status Enable (errorintrsts_enableregbit6): 0 - Masked 6 1 - Enabled

0h Data CRC Error Status Enable (errorintrsts_enableregbit5): 0 - Masked 5 1 - Enabled

0h Data Timeout Error Status Enable (errorintrsts_enableregbit4): 0 - Masked 4 1 - Enabled

0h Command Index Error Status Enable (errorintrsts_enableregbit3): 0 - 3 Masked 1 - Enabled

0h Command End Bit Error Status Enable (errorintrsts_enableregbit2): 0 - 2 Masked 1 - Enabled

0h Command CRC Error Status Enable (errorintrsts_enableregbit1): 0 - Masked 1 RW 1 - Enabled

0h Command Timeout Error Status Enable (errorintrsts_enableregbit0): 0 - 0 Masked RW 1 - Enabled

3.2.21 Normal Interrupt Signal Enable Register (normalintrsigena)—Offset 38h

This register is used to enable the Normal Interrupt Signal register. All the bits are RW, except for Reserved bits, and defined as follows: 0 - Masked 1 - Enabled.

Access Method

Type: MEM Register Device: 30 (Size: 16 bits) Function: 4

Default: 0h

15 12 8 4 0

0000000000000000 sdhcregset_cardintstsena sdhcregset_cardinsstsena sdhcregset_cardremstsena normalintrsts_enableregbit5 normalintrsts_enableregbit4 normalintrsts_enableregbit3 normalintrsts_enableregbit2 normalintrsts_enableregbit1 normalintrsts_enableregbit0 normalintrsts_enableregbit9 normalintrsts_enableregbit15 normalintrsts_enableregbit14 normalintrsts_enableregbit13 normalintrsts_enableregbit12 normalintrsts_enableregbit11 normalintrsts_enableregbit10

194 332219-002

EMMC Interface (D30:F4)

Bit Default & Field Name (ID): Description Range Access

0h normalintrsts_enableregbit15 (normalintrsts_enableregbit15): The HD 15 controls the error Interrupts using the Error Interrupt Signal Enable register.

0h Boot Terminate Interrupt Signal Enable (normalintrsts_enableregbit14): 14 Boot Terminate Interrupt Signal Enable

0h Boot ack rcv Signal Enable (normalintrsts_enableregbit13): Boot ack rcv 13 Signal Enable

0h Re-Tuning Event Signal Enable (normalintrsts_enableregbit12): Re-Tuning 12 Event Signal Enable

0h INT_C Signal Enable (normalintrsts_enableregbit11): INT_C Signal Enable 11

0h INT_B Signal Enable (normalintrsts_enableregbit10): INT_B Signal Enable 10

0h INT_A Signal Enable (normalintrsts_enableregbit9): INT_A Signal Enable 9

0h Card Interrupt Signal Enable (sdhcregset_cardintstsena): Card Interrupt 8 Signal Enable

0h Card Removal Signal Enable (sdhcregset_cardremstsena): Card Removal 7 Signal Enable

0h Card Insertion Signal Enable (sdhcregset_cardinsstsena): Card Insertion 6 Signal Enable

0h Buffer Read Ready Signal Enable (normalintrsts_enableregbit5): Buffer Read 5 Ready Signal Enable

0h Buffer Write Ready Signal Enable (normalintrsts_enableregbit4): Buffer Write 4 Ready Signal Enable

0h DMA Interrupt Signal Enable (normalintrsts_enableregbit3): DMA Interrupt 3 Signal Enable

0h Block Gap Event Signal Enable (normalintrsts_enableregbit2): Block Gap 2 Event Signal Enable

0h Transfer Complete Signal Enable (normalintrsts_enableregbit1): Transfer 1 Complete Signal Enable

0h Command Complete Signal Enable (normalintrsts_enableregbit0): Command 0 Complete Signal Enable

3.2.22 Error Interrupt Signal Enable Register (errorintrsigena)— Offset 3Ah

This register is used to enable the Normal Interrupt Signal register. All the bits are RW, except for Reserved bits, and defined as follows: 0 - Masked 1 - Enabled.

Access Method

Type: MEM Register Device: 30 (Size: 16 bits) Function: 4

Default: 0h

332219-002 195 EMMC Interface (D30:F4)

15 12 8 4 0

0000000000000000 RSVD RSVD errorintrsig_enableregbit9 errorintrsig_enableregbit8 errorintrsig_enableregbit7 errorintrsig_enableregbit6 errorintrsig_enableregbit5 errorintrsig_enableregbit4 errorintrsig_enableregbit3 errorintrsig_enableregbit2 errorintrsig_enableregbit1 errorintrsig_enableregbit0 errorintrsig_enableregbit12 errorintrsig_enableregbit10

Bit Default & Field Name (ID): Description Range Access

0h 15:13 Reserved. RO

0h errorintrsig_enableregbit12 (errorintrsig_enableregbit12): Target Response 12 Error Signal Enable

0h 11 Reserved. RO

0h errorintrsig_enableregbit10 (errorintrsig_enableregbit10): Tuning Error 10 Signal Enable

0h errorintrsig_enableregbit9 (errorintrsig_enableregbit9): ADMA Error Signal 9 Enable

0h errorintrsig_enableregbit8 (errorintrsig_enableregbit8): Auto CMD Error 8 Signal Enable

0h errorintrsig_enableregbit7 (errorintrsig_enableregbit7): Current Limit Error 7 Signal Enable

0h errorintrsig_enableregbit6 (errorintrsig_enableregbit6): Data End Bit Error 6 Signal Enable

0h errorintrsig_enableregbit5 (errorintrsig_enableregbit5): Data CRC Error 5 Signal Enable

0h errorintrsig_enableregbit4 (errorintrsig_enableregbit4): Data Timeout Error 4 Signal Enable

0h errorintrsig_enableregbit3 (errorintrsig_enableregbit3): Command Index 3 Error Signal Enable

0h errorintrsig_enableregbit2 (errorintrsig_enableregbit2): Command End Bit 2 Error Signal Enable

0h errorintrsig_enableregbit1 (errorintrsig_enableregbit1): Command CRC Error 1 Signal Enable

0h errorintrsig_enableregbit0 (errorintrsig_enableregbit0): Command Timeout 0 Error Signal Enable

3.2.23 Auto CMD12 Error Status Register (autocmderrsts)—Offset 3Ch

This register is used to indicate CMD12 response error of Auto CMD12 and CMD23 response error of Auto CMD 23

Access Method

196 332219-002

EMMC Interface (D30:F4)

Type: MEM Register Device: 30 (Size: 16 bits) Function: 4

Default: 0h

15 12 8 4 0

0000000000000000 RSVD RSVD autocmderrsts_crcerror autocmderrsts_nexterror autocmderrsts_indexerror autocmderrsts_endbiterror autocmderrsts_timeouterror autocmderrsts_notexecerror

Bit Default & Field Name (ID): Description Range Access

0h 15:8 Reserved. RO

Command Not Issued By Auto CMD12 Error (autocmderrsts_nexterror): Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 0h error(D04- D01) in this register. This bit is set to 0 when Auto CMD Error is generated 7 by Auto CMD23 0 – No Error 1 – Not Issued.

0h 6:5 Reserved. RO

Auto CMD Index Error (autocmderrsts_indexerror): Occurs if the Command 0h Index error occurs in response to a command. 4 0 – No Error 1 – Error

Auto CMD End Bit Error (autocmderrsts_endbiterror): Occurs when detecting 0h 3 that the end bit of command response is 0. RO 0 – No Error 1 – End Bit Error Generated.

Auto CMD CRC Error (autocmderrsts_crcerror): Occurs when detecting a CRC 0h error in the command response. 2 RO 0 – No Error 1 – CRC Error Generated.

Auto CMD Timeout Error (autocmderrsts_timeouterror): Occurs if the no 0h response is returned within 64 SDCLK cycles from the end bit of the command. If this 1 bit is set to 1, the other error status bits (D04 - D02) are meaningless. RO 0 - No Error 1 - Timeout.

Auto CMD12 not Executed (autocmderrsts_notexecerror): If memory multiple block data transfer is not started due to command error, this bit is not set because it 0h is not necessary to issue Auto CMD12. Setting this bit to 1 means the HC cannot 0 issue Auto CMD12 to stop memory multiple block transfer due to some error. 0 - Executed 1 - Not Executed.

3.2.24 Host Control2 Register (hostcontrol2)—Offset 3Eh

This register is used to program UHS Select Mode,UHS Select Mode,Driver Strength Select,Execute Tuning,Sampling Clock Select,Asynchronous Interrupt Enable and Preset value enable

332219-002 197 EMMC Interface (D30:F4)

Access Method

Type: MEM Register Device: 30 (Size: 16 bits) Function: 4

Default: 0h

15 12 8 4 0

0000000000000000 RSVD RSVD hostctrl2_executetuning hostctrl2_driverstrength hostctrl2_uhsmodeselect hostctrl2_asynchintrenable hostctrl2_samplingclkselect hostctrl2_1p8vsignallingena hostctrl2_presetvalueenable hostctrl2_driverstrength_bit2

Bit Default & Field Name (ID): Description Range Access

Preset Value Enable (hostctrl2_presetvalueenable): Host Controller Version 3.00 supports this bit. As the operating SDCLK frequency and I/O driver strength 0h depend on the Host System implementation, it is difficult to determine these 15 parameters in the Standard Host Driver. When Preset Value Enable is set to RW automatic. This bit enables the functions defined in the Preset Value registers. 1 Automatic Selection by Preset Value are Enabled 0 SDCLK and Driver Strength are controlled by Host Driver.

Asynchronous Interrupt Enable (hostctrl2_asynchintrenable): This bit can be 0h set to 1 if a card support asynchronous interrupt and Asynchronous Interrupt Support 14 is set to 1 in the Capabilities register. RW 0 – Disabled 1 – Enabled.

0h 13:10 Reserved. RO

0h Driver strength (hostctrl2_driverstrength_bit2): This is the programmed Drive 9 RW Strength output and it[2] of the sdhccore_drivestrength value.

0h 8 Reserved. RO

Sampling Clock Select (hostctrl2_samplingclkselect): This bit is set by tuning procedure when Execute Tuning is cleared. Writing 1 to this bit is meaningless and 0h 7 ignored. Setting 1 means that tuning is completed successfully and setting 0 means RW that tuning is failed. Controller is receiving response or a read data block. 0 - Fixed clock is used to sample data 1 - Tuned clock is used to sample data

Execute Tuning (hostctrl2_executetuning): This bit is set to 1 to start tuning procedure and automatically cleared when tuning procedure is completed. The result 0h of tuning is indicated to Sampling Clock Select. Tuning procedure is aborted by 6 RW writing 0 for more detail about tuning procedure. 0 - Not Tuned or Tuning Completed 1 - Execute Tuning.

198 332219-002

EMMC Interface (D30:F4)

Bit Default & Field Name (ID): Description Range Access

0h Driver Strength Select (hostctrl2_driverstrength): Host Controller output driver 5:4 RW in 1.8V signaling is selected by this bit. In 3.3V signaling, this field is not effective.

0h 1.8V Signaling Enable (hostctrl2_1p8vsignallingena): This bit controls voltage 3 regulator for I/O cell. 3.3V is supplied to the card regardless of signaling voltage. Setting this bit from 0 to 1 starts changing signal voltage from 3.3V to 1.8V.

UHS Mode Select (hostctrl2_uhsmodeselect): This field is used to select one of UHS-I modes and effective when 1.8V Signaling Enable is set to 1. Select in the Clock Control register and Driver Strength Select according to Preset Value registers. In this case, one of preset value registers is selected by this field. Host Driver needs to reset SD Clock Enable before changing this field to avoid 0h generating clock glitch. After setting this field, Host Driver sets SD Clock Enable 2:0 again. RW 000b - SDR12 001b - SDR25 010b - SDR50 011b - SDR104 100b - DDR50 101b - HS400

3.2.25 Capabilities Register (capabilities)—Offset 40h

This register provides the host driver with information specific to the host controller implementation. Please note, that the default values shown here assume no bypass of the capabilities register. In case software decides to bypass the default capabilities register values the reset values will present the bypassed value.

Access Method

Type: MEM Register Device: 30 (Size: 64 bits) Function: 4

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1 840 3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000 RSVD RSVD RSVD RSVD RSVD RSVD corecfg_slottype corecfg_spisupport corecfg_spiblkmode corecfg_baseclkfreq corecfg_8bitsupport corecfg_64bitsupport corecfg_sdmasupport corecfg_type4support corecfg_sdr50support corecfg_ddr50support corecfg_maxblklength corecfg_hs400support corecfg_timeoutclkunit corecfg_clockmultiplier corecfg_timeoutclkfreq corecfg_cdriversupport corecfg_sdr104support corecfg_adriversupport corecfg_ddriversupport corecfg_tuningforsdr50 corecfg_retuningmodes corecfg_1p8voltsupport corecfg_3p0voltsupport corecfg_3p3voltsupport corecfg_suspressupport corecfg_retuningtimercnt corecfg_highspeedsupport corecfg_asynchintrsupport

332219-002 199 EMMC Interface (D30:F4)

Bit Default & Field Name (ID): Description Range Access

HS 400 Support (corecfg_hs400support): This field indicates whether HS400 is 0h 63 supported or not. 0 –Not Supported 1 –Supported.

0h 62:58 Reserved. RO

SPI Block Mode (corecfg_spiblkmode): This field indicates whether SPI Block 0h Mode is supported or not. 57 0 –Not Supported 1 –Supported.

SPI Mode Support (corecfg_spisupport): This field indicates whether SPI Mode is 0h supported or not. 56 0 –Not Supported 1 –Supported

Clock Multiplier (corecfg_clockmultiplier): This field indicates clock multiplier value of programmable clock generator. Refer to Clock Control register. Setting 00h 0h means that Host Controller does not support programmable clock generator. 55:48 FFh Clock Multiplier M = 256 02h Clock Multiplier M = 3 01h Clock Multiplier M = 2 00h Clock Multiplier is Not Supported.

Re-tuning modes (corecfg_retuningmodes): This field defines the re-tuning capability of a Host Controller and how to manage the data transfer length and a Re- 0h 47:46 Tuning Timer by the Host Driver 00 - Mode1 01 - Mode2 10 - Mode3.

Use Tuning for SDR50 (corecfg_tuningforsdr50): If this bit is set to 1, this Host 0h Controller requires tuning to operate SDR50. (Tuning is always required to operate 45 SDR104.) 1 SDR50 requires tuning 0 SDR50 does not require tuning.

0h 44 Reserved. RO

0h Timer count for Re-Tuning (corecfg_retuningtimercnt): This field indicates an 43:40 initial value of the Re-Tuning Timer for Re-Tuning Mode 1 to 3.

Driver Type 4 Support (corecfg_type4support): This bit indicates support of 0h 39 Type 4 Driver. 1 Driver Type 4 is Supported 0 Driver Type 4 is Not Supported.

Driver Type D Support (corecfg_ddriversupport): This bit indicates support of 0h Driver Type D for 1.8 Signaling. 38 1 Driver Type D is Supported 0 Driver Type D is Not Supported.

Driver Type C Support (corecfg_cdriversupport): This bit indicates support of 0h 37 Driver Type C for 1.8 Signaling. 1 Driver Type C is Supported 0 Driver Type C is Not Supported.

Driver Type A Support (corecfg_adriversupport): This bit indicates support of 0h Driver Type A for 1.8 Signaling. 36 1 Driver Type A is Supported 0 Driver Type A is Not Supported.

0h 35 Reserved. RO

DDR50 Support (corecfg_ddr50support): This bit indicates whether DDR50 is 0h supported. 34 0 –Not Supported 1 –Supported.

SDR104 Support (corecfg_sdr104support): This bit indicates whether SDR104 is 0h 33 supported.SDR104 requires tuning. 0 –Not Supported 1 –Supported.

200 332219-002

EMMC Interface (D30:F4)

Bit Default & Field Name (ID): Description Range Access

SDR50 Support (corecfg_sdr50support): This bit indicates whether SDR50 is 0h supported. 32 0 –Not Supported 1 –Supported.

Slot Type (corecfg_slottype): This field indicates usage of a slot by a specific Host System. (A host controller register set is defined per slot.) Embedded slot for one 0h device (01b) means that only one on-removable device is connected to a SD bus slot. 31:30 Shared Bus Slot (10b) can be set if Host Controller supports Shared Bus Control register. The Standard Host Driver controls only a removable card or one embedded device is connected to a SD bus slot.

Asynchronous Interrupt Support (corecfg_asynchintrsupport): This bit 0h indicates whether the HC supports Asynchronous Interrupt 29 0 –Not Supported 1 –Supported.

64-bit System Bus Support (corecfg_64bitsupport): This bit indicates whether 0h 28 the HC supports 64bit System Bus 0 –Not Supported 1 –Supported.

0h 27 Reserved. RO

Voltage Support 1.8V (corecfg_1p8voltsupport): This bit indicates whether the 0h HC supports 1.8V. 26 0 –Not Supported 1 –Supported.

Voltage Support 3.0V (corecfg_3p0voltsupport): This bit indicates whether the 0h HC supports 3.0V. 25 0 –Not Supported 1 –Supported.

Voltage Support 3.3V (corecfg_3p3voltsupport): This bit indicates whether the 0h 24 HC supports 3.3V. RO 0 –Not Supported 1 –Supported.

Suspend / Resume Support (corecfg_suspressupport): This bit indicates 0h whether the HC supports Suspend/Resume functionality. 23 RO 0 –Not Supported 1 –Supported.

SDMA Support (corecfg_sdmasupport): This bit indicates whether the HC is 0h capable of using DMA to transfer data between system memory and the HC directly. 22 (SDMA Mode) RO 0 –Not Supported 1 –Supported

High Speed Support (corecfg_highspeedsupport): This bit indicates whether the 0h 21 HC and the Host System support High Speed mode. RO 0 –Not Supported 1 –Supported

0h 20:19 Reserved. RO

0h 8 Bit Support for Embedded Device (corecfg_8bitsupport): This bit indicates 18 RO whether the Host Controller is capable of using 8-bit bus width mode.

Max Block Length (corecfg_maxblklength): This value indicates the maximum block size that the HD can read and write to the buffer in the HC. The buffer shall 0h transfer this block size without wait cycles. Sizes can be defined as indicated below. 17:16 00 - 512 byte RO 01 - 1024 byte 10 - 2048 byte 11 - 4096 byte.

332219-002 201 EMMC Interface (D30:F4)

Bit Default & Field Name (ID): Description Range Access

Base Clock Frequency for SD Clock (corecfg_baseclkfreq): (1) 6-bit Base Clock Frequency This mode is supported by the Host Controller Version 1.00 and 2.00. Upper 2- bit is not effective and always 0. Unit values are1MHz. The supported clock range is 10MHz to 63MHz. 0011 1111b 63MHz 0h 0000 0010b 2MHz 15:8 RO 0000 0001b 1MHz (2) 8-bit Base Clock Frequency This mode is supported by the Host Controller Version 3.00. Unit values are 1MHz. The supported clock range is 10MHz to 255MHz. FFh 255MHz 02h 2MHz 01h 1MHz.

Timeout Clock Unit (corecfg_timeoutclkunit): This bit shows the unit of base 0h clock frequency used to detect Data Timeout Error. 7 RO 0 - KHz 1 - MHz.

0h 6 Reserved. RO

0h Timeout Clock Frequency (corecfg_timeoutclkfreq): This bit shows the base 5:0 clock frequency used to detect Data Timeout Error. RO Not 0 - 1Khz to 63Khz or 1Mhz to 63Mhz.

3.2.26 Maximum Current Capabilities Register (maxcurrentcap)— Offset 48h

This register indicates maximum current capability for each voltage

Access Method

Type: MEM Register Device: 30 (Size: 64 bits) Function: 4

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1 840 3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000 RSVD corecfg_maxcurrent1p8v corecfg_maxcurrent3p0v corecfg_maxcurrent3p3v

202 332219-002

EMMC Interface (D30:F4)

Bit Default & Field Name (ID): Description Range Access

0h 63:24 Reserved. RO

Maximum Current for 1.8V (corecfg_maxcurrent1p8v): 0 – Get value via another method 0h 1 – 4mA 23:16 2 – 8mA RO 3 – 12mA … 255 – 1020mA

Maximum Current for 3.0V (corecfg_maxcurrent3p0v): 0 – Get value via another method 0h 1 – 4mA 15:8 2 – 8mA RO 3 – 12mA … 255 – 1020mA

corecfg_maxcurrent3p3v (corecfg_maxcurrent3p3v): 0 – Get value via another method

0h 1 – 4mA 7:0 2 – 8mA RO 3 – 12mA … 255 – 1020mA

3.2.27 Force Event REGISTER for AUTO CMD Error Status (ForceEventforAUTOCMDErrorStatus)—Offset 50h

This register is not physically implemented, rather it is an address where Auto CMD Error Status register can be written.

Access Method

Type: MEM Register Device: 30 (Size: 16 bits) Function: 4

Default: 0h

15 12 8 4 0

0000000000000000 RSVD RSVD forceautocmdcrcerr forceautocmdnotexec forceautocmdindexerr forceautocmdendbiterr forceautocmdtimeouterr forcecmdnotissuedbyautocmd12err

332219-002 203 EMMC Interface (D30:F4)

Bit Default & Field Name (ID): Description Range Access

0h 15:8 Reserved. RO

forcecmdnotissuedbyautocmd12err (forcecmdnotissuedbyautocmd12err): 0h 7 Force Event for Command Not Issued by AUTO CMD12 Error RO 1 – Interrupt is generated 0 – No Interrupt

0h 6:5 Reserved. RO

forceautocmdindexerr (forceautocmdindexerr): Force Event for AUTO CMD 0h Index Error 4 RO 1 – Interrupt is generated 0 – No Interrupt

forceautocmdendbiterr (forceautocmdendbiterr): Force Event for AUTO CMD 0h End Bit Error 3 RO 1 – Interrupt is generated 0 – No Interrupt

0h forceautocmdcrcerr (forceautocmdcrcerr): Force Event for AUTO CMD Timeout 2 Error RO 1 – Interrupt is generated 0 – No Interrupt

forceautocmdtimeouterr (forceautocmdtimeouterr): Force Event for AUTO CMD 0h Timeout Error 1 RO 1 – Interrupt is generated 0 – No Interrupt

forceautocmdnotexec (forceautocmdnotexec): Force Event for AUTO CMD12 0h 0 Not Executed RO 1 – Interrupt is generated 0 – No Interrupt

3.2.28 Force Event Register for Error Interrupt Status (forceeventforerrintsts)—Offset 52h

This register is not physically implemented, rather it is an address where Error Interrupt Status register can be written.

Access Method

Type: MEM Register Device: 30 (Size: 16 bits) Function: 4

Default: 0h

15 12 8 4 0

0000000000000000 RSVD forceadmaerr forcedatcrcerr forcetuningerr forcecurrlimerr forcecmdcrcerr forceautocmderr forcedatendbiterr forcecmdindexerr forcecmdendbiterr forcedattimeouterr forcecmdtimeouterr

204 332219-002

EMMC Interface (D30:F4)

Bit Default & Field Name (ID): Description Range Access

0h 15:11 Reserved. RO

0h forcetuningerr (forcetuningerr): Force Event for Tuning Error 10 RO

0h forceadmaerr (forceadmaerr): Force Event for ADMA Error'0' no interrupt, '1' 9 RO interrupt generated

0h forceautocmderr (forceautocmderr): Force Event for Auto CMD Error '0' no 8 RO interrupt, '1' interrupt generated

0h forcecurrlimerr (forcecurrlimerr): Force Event for Current Limit Error '0' no 7 RO interrupt, '1' interrupt generated

0h forcedatendbiterr (forcedatendbiterr): Force Event for Data End Bit Error. '0' no 6 RO interrupt, '1' interrupt generated

0h forcedatcrcerr (forcedatcrcerr): Force Event for Data CRC Error 5 RO

0h forcedattimeouterr (forcedattimeouterr): Force Event for Data Timeout Error '0' 4 RO no interrupt, '1' interrupt generated

0h forcecmdindexerr (forcecmdindexerr): Force Event for Command Index Error 3 RO

0h forcecmdendbiterr (forcecmdendbiterr): Force Event for Command End Bit Error 2 RO '0' no interrupt, '1' interrupt generated

0h forcecmdcrcerr (forcecmdcrcerr): Force Event for Command CRC Error 1 RO

0h forcecmdtimeouterr (forcecmdtimeouterr): Force Event for CMD Timeout Error 0 RO '0' No interrupt, '1' interrupt generated

3.2.29 ADMA Error Status Register (admaerrsts)—Offset 54h

When the ADMA Error interrupt occur, this register holds the ADMA State in ADMA Error States field and ADMA System Address holds address around the error descriptor

Access Method

Type: MEM Register Device: 30 (Size: 8 bits) Function: 4

Default: 0h

332219-002 205 EMMC Interface (D30:F4)

74 0

00000000 RSVD admaerrsts_admaerrorstate admaerrsts_admalenmismatcherr

Bit Default & Field Name (ID): Description Range Access

0h 7:3 Reserved. RO

admaerrsts_admalenmismatcherr (admaerrsts_admalenmismatcherr): ADMA Length Mismatch Error This error occurs in the following 2 cases. While Block 0h Count Enable being set, the total data length specified by the Descriptor table is 2 different from that specified by the Block Count and Block Length. Total data length RO can not be divided by the block length. 1 - Error 0 - No error

admaerrsts_admaerrorstate (admaerrsts_admaerrorstate): This field indicates the state of ADMA when error is occurred during ADMA data transfer. This field never indicates "10" because ADMA never stops in this state. 0h D01 – D00 : ADMA Error State when error occurred Contents of SYS_SDR register. 1:0 RO 00 - ST_STOP (Stop DMA) Points to next of the error descriptor. 01 - ST_FDS (Fetch Descriptor) Points to the error descriptor 10 - Never set this state (Not used). 11 - ST_TFR (Transfer Data) Points to the next of the error descriptor

3.2.30 ADMA System Address Register0&1 (admasysaddr01)— Offset 58h

This register contains the physical address used for ADMA data transfer

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 4

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 adma_sysaddress0

206 332219-002

EMMC Interface (D30:F4)

Bit Default & Field Name (ID): Description Range Access

0h adma_sysaddress0 (adma_sysaddress0): This register holds byte address of 31:0 executing command of the Descriptor table.

3.2.31 ADMA System Address Register1 (admasysaddr2)—Offset 5Ch

This register contains the physical address used for ADMA data transfer

Access Method

Type: MEM Register Device: 30 (Size: 16 bits) Function: 4

Default: 0h

15 12 8 4 0

0000000000000000 adma_sysaddress2

Bit Default & Field Name (ID): Description Range Access

0h adma_sysaddress2 (adma_sysaddress2): This register holds byte address of 15:0 executing command of the Descriptor table.

3.2.32 ADMA System Address Register1 (admasysaddr3)—Offset 5Eh

This register contains the physical address used for ADMA data transfer

Access Method

Type: MEM Register Device: 30 (Size: 16 bits) Function: 4

Default: 0h

332219-002 207 EMMC Interface (D30:F4)

15 12 8 4 0

0000000000000000 adma_sysaddress3

Bit Default & Field Name (ID): Description Range Access

0h adma_sysaddress3 (adma_sysaddress3): This register holds byte address of 15:0 executing command of the Descriptor table.

3.2.33 Preset Value Register for Initialization (Preset Value 0)— Offset 60h

This register is used to read the SDCLK Frequency Select Value,Clock Generator Select Value,Driver Strength Select Value

Access Method

Type: MEM Register Device: 30 (Size: 16 bits) Function: 4

Default: 3h

15 12 8 4 0

0000000000000011 RSVD DriverStrengthSelectValue ClockGeneratorSelectValue SDCLKFrequencySelectValue

208 332219-002

EMMC Interface (D30:F4)

Bit Default & Field Name (ID): Description Range Access

DriverStrengthSelectValue (DriverStrengthSelectValue): Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V 0h signaling. 15:14 11b Driver Type D is Selected RO 10b Driver Type C is Selected 01b Driver Type A is Selected 00b Driver Type B is Selected

0h 13:11 Reserved. RO

ClockGeneratorSelectValue (ClockGeneratorSelectValue): This bit is effective 0h when Host Controller supports programmable clock generator. 10 RO 1: Programmable Clock Generator 0: Host Controller Ver2.00 Compatible Clock Generator

3h SDCLKFrequencySelectValue (SDCLKFrequencySelectValue): 10-bit preset 9:0 value to set SDCLK Frequency Select in the Clock Control Register is described by a RO host system.

3.2.34 Preset Value Register for Default Speed (Preset Value 1)— Offset 62h

Same description as Preset Value 0 register.

3.2.35 Preset Value Register for High Speed (Preset Value 2)— Offset 64h

Same description as Preset Value 0 register.

3.2.36 Preset Value Register for SDR12 (Preset Value 3)—Offset 66h

Same description as Preset Value 0 register.

3.2.37 Preset Value Register for SDR25 (Preset Value 4)—Offset 68h

Same description as Preset Value 0 register.

3.2.38 Preset Value Register for SDR50 (Preset Value 5)—Offset 6Ah

Same description as Preset Value 0 register.

3.2.39 Preset Value Register for SDR104 (Preset Value 6)—Offset 6Ch

Same description as Preset Value 0 register.

3.2.40 Preset Value Register for DDR50 (Preset Value 7)—Offset 6Eh

Same description as Preset Value 0 register.

332219-002 209 EMMC Interface (D30:F4)

3.2.41 Boot Timeout Control Register (boottimeoutcnt)—Offset 70h

This is used to program the boot timeout value counter

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 4

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 boot_timeoutcnt

Bit Default & Field Name (ID): Description Range Access

0h boot_timeoutcnt (boot_timeoutcnt): This value determines the interval by which 31:0 RW DAT line time-outs are detected during boot operation for eMMC card.

3.2.42 Slot Interrupt Status Register (slotintrsts)—Offset FCh

This register is used to read the interrupt signal for each slot.

Access Method

Type: MEM Register Device: 30 (Size: 16 bits) Function: 4

Default: 0h

15 12 8 4 0

0000000000000000 RSVD sdhchostif_slotintrsts

210 332219-002

EMMC Interface (D30:F4)

Bit Default & Field Name (ID): Description Range Access

0h 15:8 Reserved. RO

0h sdhchostif_slotintrsts (sdhchostif_slotintrsts): These status bits indicate the 7:0 logical OR of Interrupt signal and Wakeup signal for each slot.

3.2.43 Host Controller Version Register (hostcontrollerver)— Offset FEh

This register is used to read the vendor version number and specification version number

Access Method

Type: MEM Register Device: 30 (Size: 16 bits) Function: 4

Default: 1002h

15 12 8 4 0

0001000000000010 SDHC_VENVERNUM SpecificationVersionNumber

Bit Default & Field Name (ID): Description Range Access

10h SDHC_VENVERNUM (SDHC_VENVERNUM): This status is reserved for the vendor 15:8 RO version number.

2h SpecificationVersionNumber (SpecificationVersionNumber): This status 7:0 indicates the Host Controller Spec. Version. The upper and lower 4-bits indicate the RO version.

3.3 EMMC Additional Registers Summary

These registers are memory mapped based on BAR0 defined in PCI configuration space.

332219-002 211 EMMC Interface (D30:F4)

Table 3-3. Summary of EMMC Additional Registers

Offset Offset Default Register Name (ID)—Offset Start End Value

804h 807h Software LTR Value (SW_LTR_val)—Offset 804h 800h

808h 80Bh Auto LTR Value (Auto_LTR_val)—Offset 808h 800h

810h 813h Capabilities Bypass Capabilities Bypass (Cap_byps)—Offset 810h 0h

Capabilities Bypass 1 Capabilities Bypass 1 (Cap_byps_reg1)—Offset 814h 817h 3001EF3Ch 814h

Capabilities Bypass 2 Capabilities Bypass 2 (Cap_byps_reg2)—Offset 818h 81Bh 4004000h 818h

81Ch 81Fh (reg_D0i3)—Offset 81Ch 0h

820h 823h (Tx_CMD_dly)—Offset 820h 400h

824h 827h (Tx_DATA_dly_1)—Offset 824h A18h

828h 82Bh (Tx_DATA_dly_2)—Offset 828h 1C1C1C00h

82Ch 82Fh (Rx_CMD_Data_dly_1)—Offset 82Ch 1C1C1C00h

830h 833h (Rx_Strobe_Ctrl_Path)—Offset 830h 500h

834h 837h (Rx_CMD_Data_dly_2)—Offset 834h 181Ch

838h 83Bh (Master_Dll)—Offset 838h 1h

840h 843h (Auto_tuning)—Offset 840h 0h

3.3.1 Software LTR Value (SW_LTR_val)—Offset 804h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 4

Default: 800h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000100000000000 RSVD RSVD Snoop_value Snoop_Requirment Snoop_latency_scale

212 332219-002

EMMC Interface (D30:F4)

Bit Default & Field Name (ID): Description Range Access

0h 31:16 Reserved. RO

Snoop_Requirment: If the Requirement (bit 15) is clear, that indicates that the 0h 15 device has no LTR requirement for this type of traffic (i.e. it can wait for service RW indefinitely). If the 10-bit latency value is zero it indicates that the device cannot tolerate any delay and needs the best possible service/response time.

0h 14:13 Reserved. RO

2h Snoop_latency_scale: Support for codes 010 (1us) or 011 (32us) for Snoop 12:10 Latency Scale(1us -) 32ms total span) only. Writes to this CSR which dont match RW those values will be dropped completely, next read will return previous value.

0h Snoop_value: 10-bit latency value 9:0 RW

3.3.2 Auto LTR Value (Auto_LTR_val)—Offset 808h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 4

Default: 800h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000100000000000 RSVD RSVD Snoop_value Snoop_Requirment Snoop_latency_scale

Bit Default & Field Name (ID): Description Range Access

0h 31:16 Reserved. RO

Snoop_Requirment: If the Requirement (bit 15) is clear, that indicates that the 0h device has no LTR requirement for this type of traffic (i.e. it can wait for service 15 RW indefinitely). If the 10-bit latency value is zero it indicates that the device cannot tolerate any delay and needs the best possible service/response time.

0h 14:13 Reserved. RO

2h Snoop_latency_scale: Support for codes 010 (1us) or 011 (32us) for Snoop 12:10 Latency Scale(1us -) 32ms total span) only. Writes to this CSR which dont match RW those values will be dropped completely, next read will return previous value.

0h Snoop_value: 10-bit latency value 9:0 RW

332219-002 213 EMMC Interface (D30:F4)

3.3.3 Capabilities Bypass (Cap_byps)—Offset 810h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 4

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD Enable_Cap_Bypass

Bit Default & Field Name (ID): Description Range Access

0h 31:8 Reserved. RO

0h Enable_Cap_Bypass: 7:0 5Ah: Enable Capabilities Bypass.. RW All other: Capabilities Bypass Disable (using default values)

3.3.4 Capabilities Bypass 1 (Cap_byps_reg1)—Offset 814h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 4

Default: 3001EF3Ch

3 2 2 2 1 1 840 1 8 4 0 6 2

00110000000000011110111100111100 RSVD Slot_Type timer_count sdr50_support ddr50_support hs400_support SDMA_Support sdr104_support ADMA2_Support tuning_for_SDR50 Max_Burst_Length timeout_clock_unit SPI_mode_support timeout_clock_freq Voltage_Support_3V High_Speed_Support Voltage_Support_1_8V Voltage_Support_3_3V Sys_Addr_64bit_Support Async_Interrupt_Support Suspend_Resume_Support

214 332219-002

EMMC Interface (D30:F4)

Bit Default & Field Name (ID): Description Range Access

0h 31:30 Reserved. RO

1h hs400_support: 1: HS400 Mode Supported. 0: HS400 Mode NOT Supported 29 RW

1h timeout_clock_unit: 1â??b1 - to Select MHz Clock ,1â??b0 - to Select KHz Clock 28 RW

0h timeout_clock_freq: Timeout clock frequency 27:22 RW

0h SPI_mode_support: SPI Mode Support 1â??b1 â?? SPI Mode Supported ,1â??b0 21 RW â?? SPI Mode Not Supported

0h timer_count: Timer Count for Re-Tuning This is the Timer Count for Re-Tuning Timer 20:17 RW for Re-Tuning Mode 1 to 3. Setting to 4â??b0 disables Re-Tuning Timer

1h tuning_for_SDR50: Use Tuning for SDR50 1â??b1 â?? Use Tuning 1â??b0 â?? 16 RW Donâ??t use Tuning

1h ddr50_support: 1: DDR50 Mode Supported. 0: DDR50 Mode NOT Supported 15 RW

1h sdr104_support: 1: SDR104 Mode Supported. 0: SDR104 Mode NOT Supported 14 RW

1h sdr50_support: 1: SDR50 Mode Supported. 0: SDR50 Mode NOT Supported 13 RW

1h Slot_Type: 00 - Removable SD Card Slot. 01 - Embedded Slot for One Device. 10 - 12:11 RW Shared Bus Slot. 11 - Reserved

1h Async_Interrupt_Support: 1: Asynchronous Interrupt Supported. 0: 10 RW Asynchronous Interrupt NOT Supported

1h Sys_Addr_64bit_Support: 1 - Core supports 64-bit System Address Bus. 0 - Core 9 RW supports only 32-bit System Address Bus

1h Voltage_Support_1_8V: 1: 1.8V Supported. 0: 1.8V NOT Supported 8 RW

0h Voltage_Support_3V: 1: 3.0V Supported. 0: 3.0V NOT Supported 7 RW

0h Voltage_Support_3_3V: 1: 3.3V Supported. 0: 3.3V NOT Supported 6 RW

1h Suspend_Resume_Support: 1: Suspend/Resume Supported. 0: Suspend/Resume 5 RW NOT Supported

1h SDMA_Support: 1: SDMA mode Supported. 0: SDMA mode NOT Supported 4 RW

1h High_Speed_Support: 1: HIGH_SPEED mode Supported. 0: HIGH_SPEED mode 3 RW NOT Supported

1h ADMA2_Support: 1: ADMA2 mode Supported. 0: ADMA2 mode NOT Supported 2 RW

0h Max_Burst_Length: Maximum Block Length supported by the Core/Device. 00: 512 1:0 RW (Bytes). 01: 1024. 10: 2048. 11: Reserved

3.3.5 Capabilities Bypass 2 (Cap_byps_reg2)—Offset 818h

Access Method

332219-002 215 EMMC Interface (D30:F4)

Type: MEM Register Device: 30 (Size: 32 bits) Function: 4

Default: 4004000h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000100000000000100000000000000 RSVD RSVD RSVD tuning_dis driver_type_4 driver_type_A driver_type_C driver_type_D base_sd_clock tuning_count_val support_8_bit_embedded

Bit Default & Field Name (ID): Description Range Access

0h 31:27 Reserved. RO

20h Tuning_Count_Val: Tuning Count Value Configures the Number of Taps (Phases) of 26:21 the rxclk_in that is supported. The Tuning State machine uses this information to RW select one of the Taps (Phases) of the rxclk_in during the Tuning Procedure.

0h Tuning_Dis: Disable the 1.5x Tuning count when calculating total tuning count. The 20 internal tuning count will be set to the corecfg_Tuningcount when this signal is RW asserted

0h Driver_Type_4: Driver Type 4 Support 1 19 1: Supported RW 0: NOT Supported

0h Driver_Type_D: Driver Type D Support. 18 1: Supported[br] RW 0: NOT Supported

0h Driver_Type_C: Driver Type C Support 17 1: Supported[br] RW 0: NOT Supported

0h Driver_Type_A: Driver Type A Support 16 1: Supported[br] RW 0: NOT Supported

0h 15 Reserved. RO

1h support_8_bit_embedded: 8-bit Support for Embedded Device 14 1: Supported[br] RW 0: NOT Supported

0h 13:8 Reserved. RO

0h base_sd_clock: Base Clock Frequency for SD Clock 7:0 RW

3.3.6 (reg_D0i3)—Offset 81Ch

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 4

216 332219-002

EMMC Interface (D30:F4)

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 D0i3 RSVD RestoreRequired Cmd_In_Progress Interrupt_Request Interrupt_Req_Capable

Bit Default & Field Name (ID): Description Range Access

0h 31:5 Reserved. RO

0h Interrupt_Req_Capable: 4 0: HW not capable to issue in interrupt on command completion. RO 1: HW capable to issue an interrupt on command completion

0h RestoreRequired: When set (by HW), SW must restore state to the IP. The state 3 may have been lost due to a reset or full power lost. SW clears the bit by writing a 1. RO This bit will be set on initial power up.

0h D0i3: SW sets this bit to 1 to move the IP into the D0i3 state. Writing this bit to 0 will 2 RW return the IP to the fully active D0 state (D0i0).

0h Interrupt_Request: SW sets this bit to 1 to ask for an interrupt to be generated on 1 completion of the command. SW must clear or set this on each write to this register. RO Not supported in SCS!

Cmd_In_Progress: HW sets this bit on a 1->0 or 0->1 transition of bit [2]. While set, the other bits in this register are not valid and it is illegal for SW to write to any 0h bit in this register. When clear all the other bits in the register are valid and SW may 0 RO write to any bit. If Interrupt Request bit [1] was set for the current command, HW may clear this bit before the interrupt has been made visible to SW, since when SW actually handles

3.3.7 (Tx_CMD_dly)—Offset 820h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 4

Default: 400h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000010000000000 RSVD RSVD sdr_mode ddr_mode

332219-002 217 EMMC Interface (D30:F4)

Bit Default & Field Name (ID): Description Range Access

0h 31:15 Reserved. RO

4h ddr_mode: Tx CMD Delay (DDR Mode). 14:8 0 - 39: Select number of active delay elements. Each = 125pSec. RW 40 - 127: Reserved

0h 7 Reserved. RO

0h sdr_mode: Tx CMD Delay (SDR Mode). 6:0 0 - 39 : Select number of active delay elements. Each = 125pSec. RW 40 - 127 - Reserved

3.3.8 (Tx_DATA_dly_1)—Offset 824h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 4

Default: A18h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000101000011000 RSVD RSVD hs400_mode sdr104_hs200

Bit Default & Field Name (ID): Description Range Access

0h 31:15 Reserved. RO

Ah hs400_mode: Tx Data Delay (HS400 Mode). 14:8 0 - 78: Select number of active delay elements. Each = 125pSec. RW 79 - 127 - Reserved

0h 7 Reserved. RO

18h sdr104_hs200: Tx Data Delay (SDR104/HS200 Mode) 6:0 0-79 - Select the required delay, as a multiple of 125pSec. RW 80 - 127: Reserved

3.3.9 (Tx_DATA_dly_2)—Offset 828h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 4

Default: 1C1C1C00h

218 332219-002

EMMC Interface (D30:F4)

3 2 2 2 1 1 840 1 8 4 0 6 2

00011100000111000001110000000000 RSVD RSVD RSVD RSVD sdr50_mode ddr50_mode sdr25_hs50_mode sdr12_comp_mode

Bit Default & Field Name (ID): Description Range Access

0h 31 Reserved. RO

1Ch sdr50_mode: Tx Data Delay (SDR50 Mode) 30:24 0 - 79: Select the required delay, as a multiple of 125pSec. RW 80 - 127: Reserved

0h 23 Reserved. RO

1Ch ddr50_mode: Tx Data Delay (DDR50 Mode). 22:16 0 - 78: Select number of active delay elements. Each = 125pSec. RW 79 - 127 - Reserved

0h 15 Reserved. RO

1Ch sdr25_hs50_mode: Tx Data Delay (SDR25/HS50 Mode) 14:8 0 - 79: Select the required delay, as a multiple of 125pSec. RW 80 - 127: Reserved

0h 7 Reserved. RO

0h sdr12_comp_mode: Tx Data Delay (SDR12/Compatibility Mode) 6:0 0 - 79: Select the required delay, as a multiple of 125pSec. RW 80 - 127: Reserved

3.3.10 (Rx_CMD_Data_dly_1)—Offset 82Ch

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 4

Default: 1C1C1C00h

3 2 2 2 1 1 840 1 8 4 0 6 2

00011100000111000001110000000000 RSVD RSVD RSVD RSVD sdr25_hs50 sdr12_comp sdr50_mode ddr50_mode

332219-002 219 EMMC Interface (D30:F4)

Bit Default & Field Name (ID): Description Range Access

0h 31 Reserved. RO

1Ch sdr50_mode: Rx CMD + Data Delay (SDR50 Mode). 30:24 0 - 79: Select the required delay, as a multiple of 125pSec. RW 80 - 127: Reserved

0h 23 Reserved. RO

1Ch ddr50_mode: Rx CMD + Data Delay (DDR50 Mode). 22:16 0 - 78: Select number of active delay elements. Each = 125pSec. RW 79 - 127 - Reserved

0h 15 Reserved. RO

1Ch sdr25_hs50: Rx CMD + Data Delay (SDR25/HS50 Mode) 14:8 0 - 79: Select the required delay, as a multiple of 125pSec. RW 80 - 127: Reserved

0h 7 Reserved. RO

0h sdr12_comp: Rx CMD + Data Delay (SDR12/Compatibility Mode) 6:0 0 - 79: Select the required delay, as a multiple of 125pSec. RW 80 - 127: Reserved

3.3.11 (Rx_Strobe_Ctrl_Path)—Offset 830h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 4

Default: 500h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000010100000000 RSVD RSVD RSVD auto_tuning hs400_mode1 hs400_mode2

Bit Default & Field Name (ID): Description Range Access

0h 31:17 Reserved. RO

0h auto_tuning: Enable Auto Tuning for HS400 Strobe Path 16 0: Auto Tuning Disabled RW 1: Auto Tuning Enabled

0h 15 Reserved. RO

220 332219-002

EMMC Interface (D30:F4)

Bit Default & Field Name (ID): Description Range Access

5h hs400_mode1: Rx Strobe Delay DLL 1(HS400 Mode) 14:8 0 - 39: Select number of active delay elements. Each = 125pSec RW 40 - 63 - Reserved

0h 7 Reserved. RO

0h hs400_mode2: Rx Strobe Delay DLL 2(HS400 Mode) 6:0 0 - 39: Select number of active delay elements. Each = 125pSec RW 40 - 63 - Reserved

3.3.12 (Rx_CMD_Data_dly_2)—Offset 834h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 4

Default: 181Ch

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000001100000011100 RSVD RSVD RSVD path_pll clk_source cmd_data_sdr104_hs200

Bit Default & Field Name (ID): Description Range Access

0h 31:18 Reserved. RO

clk_source: Clock Source for Rx Path 00: Rx Clock after Output Buffer 0h 01: Rx Clock before Output Buffer 17:16 RW 10: Automatic Selection based on Working mode (HS 200 before buffer, all others after buffer) 11 - Reserved

0h 15:14 Reserved. RO

18h path_pll: Rx Path PLL #3 Delay value For Auto Tuning Mode 13:8 0 - 39: Select the required delay, as a multiple of 125pSec. RW 40 - 63: Reserved

0h 7 Reserved. RO

1Ch cmd_data_sdr104_hs200: Rx CMD + Data Delay (SDR104/HS200 Mode) 6:0 0 - 79: Select the required delay, as a multiple of 125pSec. RW 80 - 127: Reserved

332219-002 221 EMMC Interface (D30:F4)

3.3.13 (Master_Dll)—Offset 838h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 4

Default: 1h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000001 less more RSVD DLL_lock fine_code coarse_code SW_reset_dll Ctrl_of_Mst_DLL_Ref_Clk Master_DLL_Software_Ctrl

Bit Default & Field Name (ID): Description Range Access

0h 31:25 Reserved. RO

0h SW_reset_dll: SW reset for Master DLL 24 0: No SW Reset for Master DLL RO 1: Force Reset for Master DLL

0h DLL_lock: Master DLL Lock Indication 23 RO

0h coarse_code: Set coarse code to DLL. (only valid when Software control is Enabled) 22:8 RW

0h fine_code: Set fine code to DLL. (only valid when Software control is Enabled) 7:4 RW

0h less: Phase Detection Less Indication 3 RO/V

0h more: Phase Detector More Indication 2 RO/V

0h Master_DLL_Software_Ctrl: Master DLL Software Ctrl. 1 0: Master DLL Automatic Control (SW Control Disabled). RW 1: Master DLL Software Control Enabled

1h Ctrl_of_Mst_DLL_Ref_Clk: Ctrl of Master DLL Ref Clock. 0 - Clock is Disabled. 1 - 0 RW Clock is Enabled

3.3.14 (Auto_tuning)—Offset 840h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 4

Default: 0h

222 332219-002

EMMC Interface (D30:F4)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD Auto_tuning_val

Bit Default & Field Name (ID): Description Range Access

0h 31:5 Reserved. RO

0h Auto_tuning_val 4:0 RO

332219-002 223 EMMC Interface (D30:F4)

§ §

224 332219-002

SDXC (D30:F6)

4 SDXC (D30:F6)

4.1 SDXC PCI Configuration Registers Summary

Table 4-1. Summary of SDXC PCI Configuration Registers

Offset Offset Register Name (ID)—Offset Default Value Start End

0h 3h Device & Vendor ID (DEVVENDID)—Offset 0h 9D2D8086h / LP

4h 7h PCI Status & Command (STATUSCOMMAND)—Offset 4h 100000h

8h Bh Rev ID & Class Code (REVCLASSCODE)—Offset 8h 8050100h

Carche Line & Latency & Header Type & BIST (CLLATHEADERBIST)— Ch Fh 800000h Offset Ch

10h 13h Base Address Low (BAR0)—Offset 10h 4h

14h 17h Base Address Register high (BAR0_HIGH)—Offset 14h 0h

18h 1Bh Base Address Register1 (BAR1)—Offset 18h 4h

1Ch 1Fh (BAR1_HIGH)—Offset 1Ch 0h

2Ch 2Fh Subsystem Vendor ID (SUBSYSTEMID)—Offset 2Ch 0h

30h 33h (EXPANSION_ROM_BASEADDR)—Offset 30h 0h

34h 37h Capabilities Pointer (CAPABILITYPTR)—Offset 34h 80h

3Ch 3Fh (INTERRUPTREG)—Offset 3Ch 100h

Power Management Capability ID Register (POWERCAPID)—Offset 80h 83h 39001h 80h

Power Management Control and Status Register 84h 87h 8h (PMECTRLSTATUS)—Offset 84h

B0h B3h General Purpose PCI RW Register1 (GEN_REGRW1)—Offset B0h 0h

B4h B7h General Purpose PCI RW Register2 (GEN_REGRW2)—Offset B4h 0h

B8h BBh General Purpose PCI RW Register3 (GEN_REGRW3)—Offset B8h 0h

BCh BFh General Purpose PCI RW Register4 (GEN_REGRW4)—Offset BCh 0h

C0h C3h General Input Register (GEN_INPUT_REG)—Offset C0h 0h

4.1.1 Device & Vendor ID (DEVVENDID)—Offset 0h

DEVICEVENDORID - Device ID and Vendor ID Register

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 6

Default: 0h

332219-002 225 SDXC (D30:F6)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 DEVICEID VENDORID

Bit Default & Field Name (ID): Description Range Access

9D2Dh / LP Device ID (DEVICEID): Identifies the device. 31:16 RO

8086h Vendor ID (VENDORID): Intel default value is 8086h 15:0 RO

4.1.2 PCI Status & Command (STATUSCOMMAND)—Offset 4h

STATUSCOMMAND- Status and Command

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 6

Default: 100000h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000100000000000000000000 RTA BME MSE RMA RSVD RSVD RSVD RSVD RSVD RSVD CAPLIST INTR_STATUS SERR_ENABLE INTR_DISABLE

Bit Default & Field Name (ID): Description Range Access

0h 31:30 Reserved. RO

0h Received Master Abort (RMA): The software writes a 1 to this bit to clear it. 29 RW/1C

0h Received Target Abort (RTA): The software writes a 1 to this bit to clear it. 28 RW/1C

0h 27:21 Reserved. RO

1h Capabilities List (CAPLIST): Indicates that the controller contains a capabilities 20 pointer list. RO The first item is pointed to by looking at the configuration offset 34h.

0h Interrupt Status (INTR_STATUS): This bit reflects state of interrupt in the device. 19 Only when the Interrupt Disable bit in the command register is a 0 and this Interrupt RO Status bit is a 1, is the device/function interrupt message sent.

226 332219-002

SDXC (D30:F6)

Bit Default & Field Name (ID): Description Range Access

0h 18:11 Reserved. RO

0h Interrupt Disable (INTR_DISABLE): Setting this bit disables INTx assertion. 10 RW

0h 9 Reserved. RO

0h SERR_ENABLE 8 RW

0h 7:3 Reserved. RO

0h Bus Master Enable (BME): 0 = the Bridge does not generate any new upstream 2 transaction on IOSF as a master. RW Reset value of this bit is 0.

0h Memory Space Enable (MSE): MSE is part of the Type PCI configuration space 1 each device has. RW When disabled no downstream traffic from the bridge is available.

0h 0 Reserved. RO

4.1.3 Rev ID & Class Code (REVCLASSCODE)—Offset 8h

REVCLASSCODE - Revision ID and Class Code

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 6

Default: 8050100h

3 2 2 2 1 1 840 1 8 4 0 6 2

00001000000001010000000100000000 RID CLASS_CODES

Bit Default & Field Name (ID): Description Range Access

Class Code (CLASS_CODES): The Class Code register is read-only and is used to identify the generic function of the device, and in some cases, a specific register-level programming interface. The register is broken into 3 Byte-size fields. 80501h - The upper Byte (at offset 0Bh) is a base class code that broadly classifies the type 31:8 of function the device performs. RO - The middle Byte (at offset 0Ah) is a sub-class code that identifies more specifically the function of the device. - The lower Byte (at offset 09h) identifies a specific register-level programming interface (if any) so that device independent software can interact with the device. This register is tied to a strap at the top level.

0h Rev ID (RID): Revision ID identifies the revision of particular PCI device. 7:0 RO

332219-002 227 SDXC (D30:F6)

4.1.4 Carche Line & Latency & Header Type & BIST (CLLATHEADERBIST)—Offset Ch

CLLATHEADERBIST - Cache Line Latency Header and BIST

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 6

Default: 800000h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000100000000000000000000000 RSVD LATTIMER MULFNDEV HEADERTYPE CACHELINE_SIZE

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

1h Multi-Function Device (MULFNDEV): This bit is 0 or 1 depending upon the value 23 RO assigned o the top level strap

0h Header Type (HEADERTYPE): Implements Type 0 Configuration header. 22:16 RO

0h Latency Timer (LATTIMER): This register is implemented as R/W with default as 0. 15:8 RO

0h Cacheline Size (CACHELINE_SIZE): This register is implemented as R/W with 7:0 RW default as 0.

4.1.5 Base Address Low (BAR0)—Offset 10h

BAR -Base Address Register

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 6

Default: 4h

228 332219-002

SDXC (D30:F6)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000100 TYPE BASEADDR PREFETCHABLE SIZEINDICATOR MESSAGE_SPACE

Bit Default & Field Name (ID): Description Range Access

0h BARL (BASEADDR): Base address of the OCP fabric memory space. 31:12 RW

0h Size Indicator (SIZEINDICATOR): Size Indicator Read Only. The size of this 11:4 RO register depends on the size of the memory space.

0h Prefetchable (PREFETCHABLE): Indicates that this BAR is not prefetchable. 3 RO

2h TYPE: If BAR_64b_EN is 0 then 00 indicates BAR lies in 32bit address range. 2:1 RO If BAR_64b_EN is 1 then 10 Indicates BAR lies in 64 bit address range.

0h Memory Space Indicator (MESSAGE_SPACE): 0 indicates this BAR is present in 0 RO the memory space.

4.1.6 Base Address Register high (BAR0_HIGH)—Offset 14h

BAR -Base Address Register High

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 6

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 BASEADDR_HIGH

Bit Default & Field Name (ID): Description Range Access

0h BARH (BASEADDR_HIGH): Base address of the OCP fabric memory space. 31:0 RW

332219-002 229 SDXC (D30:F6)

4.1.7 Base Address Register1 (BAR1)—Offset 18h

BAR1 -Base Address Register1

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 6

Default: 4h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000100 TYPE1 BASEADDR1 PREFETCHABLE1 SIZEINDICATOR1 MESSAGE_SPACE1

Bit Default & Field Name (ID): Description Range Access

0h Base Address Register1 (BASEADDR1): This field is present if BAR1 is enabled 31:12 RW through private configuration space.

0h SIZEBAR1 (SIZEINDICATOR1): Always is 0 as minimum size is 4K 11:4 RO

0h Prefetchable (PREFETCHABLE1): Indicates that this BAR is not prefetchable. 3 RO

2h TYPE (TYPE1): Always 0 as minimum size is 4K 2:1 RO

0h Base Address Register1 (MESSAGE_SPACE1): This field is present if BAR1 is 0 RO enabled through private configuration space.

4.1.8 (BAR1_HIGH)—Offset 1Ch

BAR1 -Base Address Register1 High

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 6

Default: 0h

230 332219-002

SDXC (D30:F6)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 BASEADDR1_HIGH

Bit Default & Field Name (ID): Description Range Access

0h BASEADDR1_HIGH: Base address of the OCP fabric memory space. 31:0 RW

4.1.9 Subsystem Vendor ID (SUBSYSTEMID)—Offset 2Ch

SUBSYSTEMID -Subsystem Vendor and Subsystem ID

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 6

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 SUBSYSTEMID SUBSYSTEMVENDORID

Bit Default & Field Name (ID): Description Range Access

0h SUBSYSTEMID 31:16 RW/O

0h SUBSYSTEMVENDORID 15:0 RW/O

4.1.10 (EXPANSION_ROM_BASEADDR)—Offset 30h

EXPANSION ROM base address

Access Method

332219-002 231 SDXC (D30:F6)

Type: CFG Register Device: 30 (Size: 32 bits) Function: 6

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 EXPANSION_ROM_BASE

Bit Default & Field Name (ID): Description Range Access

0h EXPANSION_ROM_BASE: Value of all zeros indicates no support for Expansion 31:0 RO ROM.

4.1.11 Capabilities Pointer (CAPABILITYPTR)—Offset 34h

CAPABILITYPTR - Capabilities Pointer

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 6

Default: 80h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000010000000 RSVD CAPPTR_POWER

Bit Default & Field Name (ID): Description Range Access

0h 31:8 Reserved. RO

80h CAPPTR_POWER 7:0 RO

232 332219-002

SDXC (D30:F6)

4.1.12 (INTERRUPTREG)—Offset 3Ch

INTERRUPTREG - Interrupt Register

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 6

Default: 100h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000100000000 RSVD INTPIN INTLINE MAX_LAT MIN_GNT

Bit Default & Field Name (ID): Description Range Access

0h Maximum Latency (MAX_LAT): Value of 0 indicates device has no major 31:24 RO requirements for the settings of latency timers

0h MIN_GNT: TBD 23:16 RO

0h 15:12 Reserved. RO

1h Interrupt Pin (INTPIN): Interrupt Pin Value in this register is reflected from the 11:8 IPIN value in the private configuration space. RO For a single function device, this ideally is INTA.

0h Interrupt Line (INTLINE): It is used to communicate to software, the interrupt line 7:0 RW to which the interrupt pin is connected.

4.1.13 Power Management Capability ID Register (POWERCAPID)—Offset 80h

POWERCAPID - PowerManagement Capability ID

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 6

Default: 39001h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000111001000000000001 RSVD NXTCAP VERSION POWER_CAP PMESUPPORT

332219-002 233 SDXC (D30:F6)

Bit Default & Field Name (ID): Description Range Access

PME_Support (PMESUPPORT): This 5-bit field indicates the power states in which the function can assert the PME#. A value of 0b for any bit indicates that the function is not capable of asserting the

0h PME# signal in that power state. 31:27 bit 27 = 1: PME# can be asserted from D0 RO bit28 = 1: PME# can be asserted from D1. bit 29 = 1: PME# can be asserted from D2. bit30 = 1:PME# can be asserted from D3hot bit 31 = 1:PME# can be asserted from D3cold.

0h 26:19 Reserved. RO

3h Version (VERSION): Indicates support for Revision 1.2 of the PCI Power 18:16 RO Management Specification.

Next Capability (NXTCAP): Points to the next capability structure. This points to 90h NULL if either ENABLE_PCI_IDLE_CAP is 0 or if Disable PCI Device Idle capability bit 15:8 RO is set as 1 in the private space. Else this points to PCI Device Idle capability structure at offset 90h

1h Power Management Capability (POWER_CAP): Indicates this is power 7:0 RO management capability.

4.1.14 Power Management Control and Status Register (PMECTRLSTATUS)—Offset 84h

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 6

Default: 8h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000001000 RSVD RSVD RSVD RSVD PMESTATUS PMEENABLE POWERSTATE NO_SOFT_RESET

Bit Default & Field Name (ID): Description Range Access

0h 31:16 Reserved. RO

0h PME Status (PMESTATUS): 0: Software clears the bit by writing a 1 to it. 15 1: This bit is set when the PME# signal is asserted independent of the state of the RW/1C PME Enable bit (bit 8 in this register)

0h 14:9 Reserved. RO

0h PME Enable (PMEENABLE): 1: Enables the function to assert PME#. 8 RW 0: PME# message on Sideband is disabled.

0h 7:4 Reserved. RO

234 332219-002

SDXC (D30:F6)

Bit Default & Field Name (ID): Description Range Access

1h NO_SOFT_RESET: This bit indicates that devices transitioning from D3hot to D0 3 because of Powerstate commands do not perform an internal reset. Configuration RO Context is preserved.

0h 2 Reserved. RO

Power State (POWERSTATE): This field is used both to determine the current 0h power state and to set a new power state. The values are: 1:0 RW 00 D0 state 11 D3HOT state

4.1.15 General Purpose PCI RW Register1 (GEN_REGRW1)— Offset B0h

General Purpose Read Write Register1

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 6

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 GEN_REG_RW1

Bit Default & Field Name (ID): Description Range Access

0h GEN_REG_RW1 31:0 RW

4.1.16 General Purpose PCI RW Register2 (GEN_REGRW2)— Offset B4h

General Purpose Read Write Register2

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 6

Default: 0h

332219-002 235 SDXC (D30:F6)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 GEN_REG_RW2

Bit Default & Field Name (ID): Description Range Access

0h GEN_REG_RW2 31:0 RW

4.1.17 General Purpose PCI RW Register3 (GEN_REGRW3)— Offset B8h

General Purpose Read Write Register3

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 6

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 GEN_REG_RW3

Bit Default & Field Name (ID): Description Range Access

0h GEN_REG_RW3 31:0 RW

4.1.18 General Purpose PCI RW Register4 (GEN_REGRW4)— Offset BCh

General Purpose Read Write Register4

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 6

Default: 0h

236 332219-002

SDXC (D30:F6)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 GEN_REG_RW4

Bit Default & Field Name (ID): Description Range Access

0h GEN_REG_RW4 31:0 RW

4.1.19 General Input Register (GEN_INPUT_REG)—Offset C0h

General Purpose Input Register

Access Method

Type: CFG Register Device: 30 (Size: 32 bits) Function: 6

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 GEN_REG_INPUT_RW

Bit Default & Field Name (ID): Description Range Access

0h GEN_REG_INPUT_RW 31:0 RO

4.2 SDXC Memory Mapped Registers Summary

These registers are memory mapped based on BAR0 defined in PCI configuration space.

332219-002 237 SDXC (D30:F6)

Table 4-2. Summary of SDXC Memory Mapped Registers

Offset Offset Register Name (ID)—Offset Default Value Start End

SDMA System Address Register/Argument2 Register 0h 3h 0h (sdmasysaddr)—Offset 0h

4h 5h Block Size Register (blocksize)—Offset 4h 0h

6h 7h Block Count Register (blockcount)—Offset 6h 0h

8h Bh Argument1 Register (argument1)—Offset 8h 0h

Ch Dh Transfer Mode Register (transfermode)—Offset Ch 0h

Eh Fh Command Register (command)—Offset Eh 0h

10h 13h Response Register (Reponse 0)—Offset 10h 0h

20h 23h Buffer Data Port Register (dataport)—Offset 20h 0h

24h 27h Present State Register (presentstate)—Offset 24h 0h

28h 28h Host Control1 Register (hostcontrol1)—Offset 28h 0h

29h 29h PowerControl Register (powercontrol)—Offset 29h 0h

2Ah 2Ah Block Gap Control Register (blockgapcontrol)—Offset 2Ah 80h

2Bh 2Bh Wakeup Control Register (wakeupcontrol)—Offset 2Bh 0h

2Ch 2Dh Clock Control Register (clockcontrol)—Offset 2Ch 0h

2Eh 2Eh Timeout Control Register (timeoutcontrol)—Offset 2Eh 0h

2Fh 2Fh Software Reset Register (softwarereset)—Offset 2Fh 0h

30h 31h Normal Interrupt Status Register (normalintrsts)—Offset 30h 0h

32h 33h Error Interrupt Status (errorintrsts)—Offset 32h 0h

Normal Interrupt Status Enable Register (normalintrstsena)— 34h 35h 0h Offset 34h

Error Interrupt Status Enable Register (errorintrstsena)— 36h 37h 0h Offset 36h

Normal Interrupt Signal Enable Register (normalintrsigena)— 38h 39h 0h Offset 38h

Error Interrupt Signal Enable Register (errorintrsigena)—Offset 3Ah 3Bh 0h 3Ah

Auto CMD12 Error Status Register (autocmderrsts)—Offset 3Ch 3Dh 0h 3Ch

3Eh 3Fh Host Control 2 Register (hostcontrol2)—Offset 3Eh 0h

40h 47h Capabilities Register (capabilities)—Offset 40h 0h

Maximum Current Capabilities Register (maxcurrentcap)— 48h 4Fh 0h Offset 48h

Force Event REGISTER for AUTO CMD Error Status 50h 51h 0h (ForceEventforAUTOCMDErrorStatus)—Offset 50h

Force Event Register for Error Interrupt Status 52h 53h 0h (forceeventforerrintsts)—Offset 52h

54h 54h ADMA Error Status Register (admaerrsts)—Offset 54h 0h

ADMA System Address Register0&1 (admasysaddr01)—Offset 58h 5Bh 0h 58h

5Ch 5Dh ADMA System Address Register1 (admasysaddr2)—Offset 5Ch 0h

5Eh 5Fh ADMA System Address Register1 (admasysaddr3)—Offset 5Eh 0h

Preset Value Register for Initialization (Preset Value 0)—Offset 60h 61h 3h 60h

238 332219-002

SDXC (D30:F6)

Table 4-2. Summary of SDXC Memory Mapped Registers (Continued)

Offset Offset Register Name (ID)—Offset Default Value Start End

Preset Value Register for Default Speed (Preset Value 1)— 62h 63h 0h Offset 62h

Preset Value Register for High Speed (presetvalue2)—Offset 64h 65h 0h 64h

66h 67h Preset Value Register for SDR12 (presetvalue3)—Offset 66h 0h

68h 69h Preset Value Register for SDR25 (presetvalue4)—Offset 68h 0h

6Ah 6Bh Preset Value Register for SDR50 (presetvalue5)—Offset 6Ah 0h

6Ch 6Dh Preset Value Register for SDR104 (presetvalue6)—Offset 6Ch 0h

6Eh 6Fh Preset Value Register for DDR50 (presetvalue7)—Offset 6Eh 0h

FCh FDh Slot Interrupt Status Register (slotintrsts)—Offset FCh 0h

Host Controller Version Register (hostcontrollerver)—Offset FEh FFh 1002h FEh

4.2.1 SDMA System Address Register/Argument2 Register (sdmasysaddr)—Offset 0h

This register contains concatinates reg_sdmasysaddrlo and reg_sdmasysaddrhi

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 6

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 sdma_sysaddress

Bit Default & Field Name (ID): Description Range Access

0h sdma_sysaddress (sdma_sysaddress): refer to reg_sdmasysaddrlo and 31:0 reg_sdmasysaddrhi

4.2.2 Block Size Register (blocksize)—Offset 4h

This register is used to configure the number of bytes in a data block

Access Method

332219-002 239 SDXC (D30:F6)

Type: MEM Register Device: 30 (Size: 16 bits) Function: 6

Default: 0h

15 12 8 4 0

0000000000000000 RSVD xfer_blocksize sdma_bufboundary

Bit Default & Field Name (ID): Description Range Access

0h 15 Reserved. RO

Host DMA Buffer Size (sdma_bufboundary): To perform long DMA transfer, System Address register shall be updated at every system boundary during DMA transfer. These bits specify the size of contiguous buffer in the system memory. The DMA transfer shall wait at the every boundary specified by these fields and the HC generates the DMA Interrupt to request the HD to update the System Address register. These bits shall support when the DMA Support in the Capabilities register is set to 1 and this function is active when the DMA Enable in the Transfer Mode register 0h is set to 1. 14:12 RW 000b - 4KB(Detects A11 Carry out) 001b - 8KB(Detects A12 Carry out) 010b - 16KB(Detects A13 Carry out) 011b - 32KB(Detects A14 Carry out) 100b - 64KB(Detects A15 Carry out) 101b -128KB(Detects A16 Carry out) 110b - 256KB(Detects A17 Carry out) 111b - 512KB(Detects A18 Carry out)

Transfer Blocksize (xfer_blocksize): This register specifies the block size for block data transfers for CMD17, CMD18, CMD24, CMD25, and CMD53. It can be accessed only if no transaction is executing (i.e after a transaction has stopped). Read operations during transfer return an invalid value and write operations shall be ignored. 0000h - No Data Transfer

0h 0001h - 1 Byte 11:0 0002h - 2 Bytes RW 0003h - 3 Bytes 0004h - 4 Bytes ------01FFh - 511 Bytes 0200h - 512 Bytes ------0800h - 2048 Bytes

4.2.3 Block Count Register (blockcount)—Offset 6h

This register is used to configure the number of data blocks

Access Method

Type: MEM Register Device: 30 (Size: 16 bits) Function: 6

Default: 0h

240 332219-002

SDXC (D30:F6)

15 12 8 4 0

0000000000000000 xfer_blockcount

Bit Default & Field Name (ID): Description Range Access

xfer_blockcount (xfer_blockcount): This register is enabled when Block Count Enable in the Transfer Mode register is set to 1 and is valid only for multiple block transfers. The HC decrements the block count after each block transfer and stops when the count reaches zero. It can be accessed only if no transaction is executing (i.e. after a transaction has stopped). Read operations during transfer return an invalid value and write operations shall be ignored. 0h When saving transfer context as a result of Suspend command, the number of blocks 15:0 yet to be transferred can be determined by reading this register. When restoring transfer context prior to issuing a Resume command, the HD shall restore the previously save block count. 0000h - Stop Count 0001h - 1 block 0002h - 2 blocks ------FFFFh - 65535 blocks

4.2.4 Argument1 Register (argument1)—Offset 8h

This register contains concatinates argument1lo and argument1hi registers to result SD Command Argument

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 6

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 command_argument1

Bit Default & Field Name (ID): Description Range Access

0h command_argument1 (command_argument1): The SD/eMMC Command 31:0 RW Argument is specified as bit39-8 of Command-Format

332219-002 241 SDXC (D30:F6)

4.2.5 Transfer Mode Register (transfermode)—Offset Ch

This register is used to control the operations of data transfers

Access Method

Type: MEM Register Device: 30 (Size: 16 bits) Function: 6

Default: 0h

15 12 8 4 0

0000000000000000 RSVD xfermode_blkcntena xfermode_multiblksel xfermode_dataxferdir xfermode_dmaenable xfermode_autocmdena

Bit Default & Field Name (ID): Description Range Access

0h 15:6 Reserved. RO

Multi / Single Block Select (xfermode_multiblksel): This bit enables multiple 0h block data transfers. 5 RW 0 - Single Block 1 - Multiple Block.

Data Transfer Direction Select (xfermode_dataxferdir): This bit defines the 0h direction of data transfers. 4 RW 0 - Write (Host to Card) 1 - Read (Card to Host)

Auto CMD Enable (xfermode_autocmdena): This field determines use of auto command functions 0h 00b - Auto Command Disabled 3:2 RW 01b - Auto CMD12 Enable 10b - Auto CMD23 Enable 11b - Reserved

Block Count Enable (xfermode_blkcntena): This bit is used to enable the Block 0h count register, which is only relevant for multiple block transfers. When this bit is 0, 1 the Block Count register is disabled, which is useful in executing an infinite transfer. RW 0 - Disable 1 - Enable

DMA Enable (xfermode_dmaenable): DMA can be enabled only if DMA Support 0h bit in the Capabilities register is set. If this bit is set to 1, a DMA operation shall begin 0 when the HD writes to the upper byte of Command register (00Fh). RW 0 - Disable 1 - Enable

4.2.6 Command Register (command)—Offset Eh

This register is used to program the Command for host controller

Access Method

Type: MEM Register Device: 30 (Size: 16 bits) Function: 6

242 332219-002

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Default: 0h

15 12 8 4 0

0000000000000000 RSVD RSVD command_cmdtype command_cmdindex command_crcchkena command_datapresent command_indexchkena command_responsetype

Bit Default & Field Name (ID): Description Range Access

0h 15:14 Reserved. RO

0h command_cmdindex (command_cmdindex): This bit shall be set to the 13:8 command number (CMD0-63, ACMD0-63).

Command Type (command_cmdtype): There are three types of special commands. Suspend, Resume and Abort. These bits shall bet set to 00b for all other commands. Suspend Command If the Suspend command succeeds, the HC shall assume the SD Bus has been released and that it is possible to issue the next command which uses the DAT line. The host controller shall de-assert Read Wait for read transactions and stop checking busy for write transactions. The Interrupt cycle shall start, in 4-bit mode. If the Suspend command fails, the HC shall maintain its current state. and the HD shall restart the transfer by setting 0h Continue Request in the Block Gap Control Register. 7:6 RW Resume Command The HD re-starts the data transfer by restoring the registers in the range of 000- 00Dh. The HC shall check for busy before starting write transfers. Abort Command If this command is set when executing a read transfer, the HC shall stop reads to the buffer. If this command is set when executing a write transfer, the HC shall stop driving the DAT line. After issuing the Abort command, the HD should issue a software reset 00b - Normal 01b - Suspend 10b - Resume 11b - Abort

Data Present Select (command_datapresent): This bit is set to 1 to indicate that data is present and shall be transferred using the DAT line. If is set to 0 for the following: 0h 1. Commands using only CMD line(ex. CMD52) 5 2. Commands with no data transfer but using busy signal on DAT[0] line (R1b or R5b RW ex. CMD38) 3. Resume Command 0 - No Data Present 1 - Data Present

Command Index Check Enable (command_indexchkena): If this bit is set to 1, the HC shall check the index field in the response to see if it has the same value as 0h 4 the command index. If it is not, it is reported as a Command Index Error. If this bit is RW set to 0, the Index field is not checked. 0 - Disable 1 - Enable

332219-002 243 SDXC (D30:F6)

Bit Default & Field Name (ID): Description Range Access

Command CRC Check Enable (command_crcchkena): If this bit is set to 1, the 0h host controller shall check the CRC field in the response. If an error is detected, it is 3 reported as a Command CRC Error. If this bit is set to 0, the CRC field is not checked. RW 0 - Disable 1 – Enable

0h 2 Reserved. RO

command_responsetype (command_responsetype): Response Type Select: 0h 00 - No Response 1:0 01 - Response length 136 RW 10 - Response length 48 11 - Response length 48 check Busy after response

4.2.7 Response Register (Reponse 0)—Offset 10h

The response registers contains the 128 bit response received from the External Device. The response registers are available at the following offset: Response Register 0: offset 0x010h Response Register 1: offset 0x012h Response Register 2: offset 0x014h Response Register 3: offset 0x016h Response Register 4: offset 0x018h Response Register 5: offset 0x01Ah Response Register 6: offset 0x01Ch Response Register 7: offset 0x01Eh.

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 6

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 command_response

Bit Default & Field Name (ID): Description Range Access

0h command_response (command_response): R[] refers to a bit range within the 31:0 response data as transmitted on the SD Bus, REP[] refers to a bit

4.2.8 Buffer Data Port Register (dataport)—Offset 20h

This register is used to access internal buffer

244 332219-002

SDXC (D30:F6)

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 6

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 sdhcdmactrl_piobufrddata

Bit Default & Field Name (ID): Description Range Access

0h sdhcdmactrl_piobufrddata: The Host Controller Buffer can be accessed through 31:0 RW this 32-bit Data Port Register.

4.2.9 Present State Register (presentstate)—Offset 24h

The Host Driver can get status of the Host Controller from this 32-bit read-only register

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 6

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD RSVD sdif_wp_dsync sdif_cd_n_dsync sdif_cmdin_dsync sdif_dat7in_dsync sdif_dat6in_dsync sdif_dat5in_dsync sdif_dat4in_dsync sdif_dat3in_dsync sdif_dat2in_dsync sdif_dat1in_dsync sdif_dat0in_dsync presentstate_inhibitdat presentstate_inhibitcmd sdhcdmactrl_rdxferactive sdhcdmactrl_piobufrdena sdhcdmactrl_wrxferactive sdhcdmactrl_piobufwrena sdhcdmactrl_datalineactive sdhccarddet_inserted_dsync sdhcsdctrl_retuningreq_dsync sdhccarddet_statestable_dsync

332219-002 245 SDXC (D30:F6)

Bit Default & Field Name (ID): Description Range Access

0h 31:29 Reserved. RO

0h DAT7 Line Signal Level (sdif_dat7in_dsync): This status is used to check DAT 28 RO line level to recover from errors, and for debugging.

0h DAT6 Line Signal Level (sdif_dat6in_dsync): This status is used to check DAT 27 RO line level to recover from errors, and for debugging.

0h DAT5 Line Signal Level (sdif_dat5in_dsync): This status is used to check DAT 26 RO line level to recover from errors, and for debugging.

0h DAT4 Line Signal Level (sdif_dat4in_dsync): This status is used to check DAT 25 RO line level to recover from errors, and for debugging.

0h CMD Line Signal Level (sdif_cmdin_dsync): This status is used to check DAT line 24 RO level to recover from errors, and for debugging.

0h DAT3 Line Signal Level (sdif_dat3in_dsync): This status is used to check DAT 23 line level to recover from errors, and for debugging. This is

0h DAT2 Line Signal Level (sdif_dat2in_dsync): This status is used to check DAT 22 RO line level to recover from errors, and for debugging. This is

0h DAT1 Line Signal Level (sdif_dat1in_dsync): This status is used to check DAT 21 RO line level to recover from errors, and for debugging. This is

0h DAT0 Line Signal Level (sdif_dat0in_dsync): This status is used to check DAT 20 RO line level to recover from errors, and for debugging. This is

Write Protect Switch Pin Level (sdif_wp_dsync): The Write Protect Switch is 0h 19 supported for memory and combo cards. This bit reflects the SDWP# pin. 0 - Write RO protected (SDWP# = 0) 1 - Write enabled (SDWP# = 1).

Card Level Detect (sdif_cd_n_dsync): This bit reflects the inverse value of the 0h SDCD# pin. 18 RO 0 - No Card present (SDCD# = 1) 1 - Card present (SDCD# = 0).

Card State Stable (sdhccarddet_statestable_dsync): This bit is used for testing. If it is 0, the Card Detect Pin Level is not stable. If this bit is set to 1, it means the 0h Card Detect Pin Level is stable. The Software Reset For All in the Software Reset 17 RO Register shall not affect this bit. 0 - Reset of Debouncing 1 - No Card or Inserted.

Card Inserted (sdhccarddet_inserted_dsync): This bit indicates whether a card has been inserted. Changing from 0 to 1 generates a Card Insertion Interrupt in the Normal Interrupt Status register and changing from 1 to 0 generates a Card Removal Interrupt in the Normal Interrupt Status register. The Software Reset For All in the Software Reset 0h register shall not affect this bit. 16 RO If a Card is removed while its power is on and its clock is oscillating, the HC shall clear SD Bus Power in the Power Control register and SD Clock Enable in the Clock control register. In addition the HD should clear the HC by the Software Reset For All in Software register. The card detect is active regardless of the SD Bus Power. 0 - Reset or Debouncing or No Card 1 - Card Inserted

0h 15:12 Reserved. RO

Buffer Read Enable (sdhcdmactrl_piobufrdena): This status is used for non- DMA read transfers. This read only flag indicates that valid data exists in the host side buffer status. 0h If this bit is 1, readable data exists in the buffer. 11 A change of this bit from 1 to 0 occurs when all the block data is read from the buffer. RO A change of this bit from 0 to 1 occurs when all the block data is ready in the buffer and generates the Buffer Read Ready Interrupt. 0 - Read Disable 1 - Read Enable

0h sdhcdmactrl_piobufwrena (sdhcdmactrl_piobufwrena): This status is used for 10 non-DMA write transfers.This read only flag indicates if space is available for write data.

246 332219-002

SDXC (D30:F6)

Bit Default & Field Name (ID): Description Range Access

Read Transfer Active (sdhcdmactrl_rdxferactive): This status is used for detecting completion of a read transfer. This bit is set to 1 for either of the following conditions: • After the end bit of the read command • When writing a 1 to continue Request in the Block Gap Control register to restart a

0h read transfer. 9 This bit is cleared to 0 for either of the following conditions: RO • When the last data block as specified by block length is transferred to the system. • When all valid data blocks have been transferred to the system and no current block transfers are being sent as a result of the Stop At Block Gap Request set to 1. A transfer complete interrupt is generated when this bit changes to 0. 1 - Transferring data 0 - No valid data

Write Transfer Active (sdhcdmactrl_wrxferactive): This status indicates a write transfer is active. If this bit is 0, it means no valid write data exists in the HC. This bit is set in either of the following cases: • After the end bit of the write command. • When writing a 1 to Continue Request in the Block Gap Control register to restart a write transfer. This bit is cleared in either of the following cases: 0h • After getting the CRC status of the last data block as specified by the transfer count 8 RO (Single or Multiple) • After getting a CRC status of any block where data transmission is about to be stopped by a Stop At Block Gap Request. During a write transaction, a Block Gap Event interrupt is generated when this bit is changed to 0, as a result of the Stop At Block Gap Request being set. This status is useful for the HD in determining when to issue commands during write busy. 1 - transferring data 0 - No valid data

0h 7:4 Reserved. RO

sdhcsdctrl_retuningreq_dsync (sdhcsdctrl_retuningreq_dsync): Host Controller may request Host Driver to execute re-tuning sequence by setting this bit when the data window is shifted by temperature drift and any issue receiving the correct data. This bit is cleared when a command is issued with setting Execute Tuning in the Host Control 2 register. Changing of this bit from 0 to 1 generates Re- 0h Tuning Event. 3 This bit is cleared when a command is issued with setting Execute Tuning in the Host RO Control 2 register. Changing of this bit from 0 to 1 generates Re-Tuning Event. Refer to Normal Interrupt registers for more detail. This bit isn't set to 1 if Sampling Clock Select in the Host Control 2 register is set to 0 (using fixed sampling clock). 1: Sampling clock needs re-tuning 0: Fixed or well tuned sampling clock

0h DATA Line Active (sdhcdmactrl_datalineactive): This bit indicates whether one 2 RO of the DAT line on SD bus is in use. 1 - DAT line active 0 - DAT line inactive

Command Inhibit (DAT) (presentstate_inhibitdat): This status bit is generated if either the DAT Line Active or the Read transfer Active is set to 1. If this bit is 0, it indicates the HC can issue the next SD command. Commands with busy signal belong to Command Inhibit (DAT) (ex. R1b, R5b type). 0h 1 Changing from 1 to 0 generates a Transfer Complete interrupt in the Normal interrupt RO status register. Note: The SD Host Driver can save registers in the range of 000-00Dh for a suspend transaction after this bit has changed from 1 to 0. 1 - Cannot issue command which uses the DAT line 0 - Can issue command which uses the DAT line

Command Inhibit (CMD) (presentstate_inhibitcmd): If this bit is 0, it indicates the CMD line is not in use and the HC can issue a SD command using the CMD line. This bit is set immediately after the Command register (00Fh) is written. This bit is cleared when the command response is received. Even if the Command Inhibit (DAT) is set to 1, Commands using only the CMD line can be issued if this bit is 0. Changing from 1 to 0 generates a Command complete 0h interrupt in the Normal Interrupt Status register. If the HC cannot issue the command 0 because of a command conflict error or because of Command Not Issued By Auto RO CMD12 Error, this bit shall remain 1 and the Command Complete is not set. Status issuing Auto CMD12 is not read from this bit. Auto CMD12 and Auto CMD23 consist of two responses. In this case, this bit is not cleared by the response of CMD12 or CMD23 but cleared by the response of a read/ write command. Status issuing Auto CMD12 is not read from this bit. So if a command is issued during Auto CMD12 operation, Host Controller shall manage to issue two commands: CMD12 and a command set by Command register.

332219-002 247 SDXC (D30:F6)

4.2.10 Host Control1 Register (hostcontrol1)—Offset 28h

This register is used to program DMA modes, LED Control, Data Transfer Width, High Speed Enable, Card detect test level and signal selection

Access Method

Type: MEM Register Device: 30 (Size: 8 bits) Function: 6

Default: 0h

74 0

00000000 hostctrl1_datawidth hostctrl1_ledcontrol hostctrl1_dmaselect hostctrl1_cdtestlevel hostctrl1_cdsigselect hostctrl1_extdatawidth hostctrl1_highspeedena

Bit Default & Field Name (ID): Description Range Access

Card Detect Signal Detection (hostctrl1_cdsigselect): This bit selects source for 0h card detection. 7 RW 1- The card detect test level is selected 0- SDCD# is selected (for normal use).

Card Detect Test Level (hostctrl1_cdtestlevel): This bit is enabled while the Card Detect Signal Selection is set to 1 and it indicates card inserted or not. 0h Generates (card ins or card removal) interrupt when the normal int sts enable bit is 6 RW set. 1 - Card Inserted 0 - No Card.

Extended Data Transfer Width (hostctrl1_extdatawidth): This bit controls 8-bit 0h bus width mode for embedded device. Support of this function is indicated in 8-bit 5 Support for Embedded Device in the Capabilities register. RW If a device supports 8-bit bus mode, this bit may be set to 1. If this bit is 0, bus width is controlled by Data Transfer Width in the Host Control 1 register.

DMA Select (hostctrl1_dmaselect): One of supported DMA modes can be selected. The host driver shall check support of DMA modes by referring the 0h Capabilities register. 4:3 00 - SDMA is selected RW 01 - 32-bit Address ADMA1 is selected 10 - 32-bit Address ADMA2 is selected 11 - 64-bit Address ADMA2 is selected.

248 332219-002

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Bit Default & Field Name (ID): Description Range Access

High Speed Enable (hostctrl1_highspeedena): This bit is optional. Before setting this bit, the HD shall check the High Speed Support in the capabilities register. If this 0h bit is set to 0 (default), the HC outputs CMD line and DAT lines at the falling edge of 2 RW the SD clock (up to 25 MHz/ 20MHz for MMC). If this bit is set to 1, the HC outputs CMD line and DAT lines at the rising edge of the SD clock (up to 50 MHz for SD/52MHz for MMC)/ 208Mhz.

Data Transfer Width (hostctrl1_datawidth): This bit selects the data width of 0h the HC. The HD shall select it to match the data width of the SD card. 1 RW 1 - 4 bit mode 0 - 1 bit mode.

LED Control (hostctrl1_ledcontrol): This bit is used to caution the user not to remove the card while the SD card is being accessed. If the software is going to issue 0h multiple SD commands, this bit can be set during all transactions. It is not necessary 0 RW to change for each transaction. 1 - LED on 0 - LED off.

4.2.11 PowerControl Register (powercontrol)—Offset 29h

This register is used to program the SD Bus power and voltage level

Access Method

Type: MEM Register Device: 30 (Size: 8 bits) Function: 6

Default: 0h

74 0

00000000 RSVD emmc_hwreset pwrctrl_sdbuspower pwrctrl_sdbusvoltage

Bit Default & Field Name (ID): Description Range Access

0h 7:5 Reserved. RO

HW Reset (emmc_hwreset): Hardware reset signal is generated when this bit is 0h 4 set RW '1' - Drives the hardware reset pin as ZERO (Active LOW to eMMC card) '0' - Deassert the hardware reset pin.

SD Bus Voltage Select (pwrctrl_sdbusvoltage): By setting these bits, the HC selects the voltage level for the SD card. Before setting this register, the HC shall 0h check the voltage support bits in the capabilities register. If unsupported voltage is 3:1 selected, the Host System shall not supply SD bus voltage RW 111b - 3.3 V 110b - 3.0 V 101b - 1.8 V.

SD Bus Power (pwrctrl_sdbuspower): Before setting this bit, the SD host driver 0h shall set SD Bus Voltage Select. If the HC detects the No Card State, this bit shall be 0 cleared. RW 1 - Power on 0 - Power off.

332219-002 249 SDXC (D30:F6)

4.2.12 Block Gap Control Register (blockgapcontrol)—Offset 2Ah

This register is used to program the block gap request, read wait control and interrupt at block gap.

Access Method

Type: MEM Register Device: 30 (Size: 8 bits) Function: 6

Default: 80h

74 0

10000000 blkgapctrl_spimode blkgapctrl_continue blkgapctrl_interrupt blkgapctrl_rdwaitctrl blkgapctrl_bootenable blkgapctrl_bootackena blkgapctrl_altbootmode blkgapctrl_stopatblkgap

Bit Default & Field Name (ID): Description Range Access

Boot Acknowledge Check (blkgapctrl_bootackena): To check for the boot 1h acknowledge in boot operation. 7 RW 1 - wait for boot ack from the card 0 - Will not wait for boot ack from the card.

Alternate Boot Enable (blkgapctrl_altbootmode): To start boot code access in 0h alternative mode. 6 RW 1- To start alternate boot mode access 0 - To stop alternate boot mode access.

0h Boot Code Access (blkgapctrl_bootenable): To start boot code access 5 1- To start boot code access RW 0 - To stop boot code access

0h SPI mode enable (blkgapctrl_spimode): SPI mode enable bit. 4 1- SPI mode RW 0 - SD mode

Interrupt at Block Gap (blkgapctrl_interrupt): This bit is valid only in 4-bit mode of the SDIO card and selects a sample point in the interrupt cycle. 0h Setting to 1 enables interrupt detection at the block gap for a multiple block transfer. 3 RW If the SD card cannot signal an interrupt during a multiple block transfer, this bit should be set to 0. When the HD detects an SD card insertion, it shall set this bit according to the CCCR of the card.

250 332219-002

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Bit Default & Field Name (ID): Description Range Access

Read Wait Control (blkgapctrl_rdwaitctrl): The read wait function is optional for SDIO cards. If the card supports read wait, set this bit to enable use of the read wait protocol to stop read data using DAT[2] line. Otherwise the HC has to stop the SD 0h clock to hold read data, which restricts commands generation. When the HD detects 2 a card insertion, it shall set this bit according to the CCCR of the card. If the card RW does not support read wait, this bit shall never be set to 1 otherwise DAT line conflict may occur. If this bit is set to 0, Suspend / Resume cannot be supported 1 - Enable Read Wait Control 0 - Disable Read Wait Control

Continue Request (blkgapctrl_continue): This bit is used to restart a transaction which was stopped using the Stop At Block Gap Request. To cancel stop at the block gap, set Stop At block Gap Request to 0 and set this bit to restart the transfer. 0h The HC automatically clears this bit in either of the following cases: 1 RW 1) In the case of a read transaction, the DAT Line Active changes from 0 to 1 as a read transaction restarts. 2) In the case of a write transaction, the Write transfer active changes from 0 to 1 as the write transaction restarts.

Stop At Block Gap Request (blkgapctrl_stopatblkgap): This bit is used to stop 0h executing a transaction at the next block gap for non- DMA,SDMA and ADMA 0 transfers. Until the transfer complete is set to 1, indicating a transfer completion the RW HD shall leave this bit set to 1. Clearing both the Stop At Block Gap Request and Continue Request shall not cause the transaction to restart.

4.2.13 Wakeup Control Register (wakeupcontrol)—Offset 2Bh

This register is used to program the wakeup functionality.

Access Method

Type: MEM Register Device: 30 (Size: 8 bits) Function: 6

Default: 0h

74 0

00000000 RSVD wkupctrl_cardremoval wkupctrl_cardinsertion wkupctrl_cardinterrupt

Bit Default & Field Name (ID): Description Range Access

0h 7:3 Reserved. RO

332219-002 251 SDXC (D30:F6)

Bit Default & Field Name (ID): Description Range Access

Wakeup On SD Card Removal (wkupctrl_cardremoval): This bit enables 0h wakeup event via Card Removal assertion in the Normal Interrupt Status register. 2 FN_WUS (Wake up Support) in CIS does not affect this bit. RW 1 - Enable 0 – Disable.

Wakeup On SD Card Insertion (wkupctrl_cardinsertion): This bit enables 0h wakeup event via Card Insertion assertion in the Normal Interrupt Status register. 1 FN_WUS (Wake up Support) in CIS does not affect this bit. RW 1 - Enable 0 – Disable

Wakeup Event Enable On Card Interrupt (wkupctrl_cardinterrupt): This bit 0h enables wakeup event via Card Interrupt assertion in the Normal Interrupt Status 0 register. This bit can be set to 1 if FN_WUS (Wake Up Support) in CIS is set to 1. RW 1 - Enable 0 - Disable.

4.2.14 Clock Control Register (clockcontrol)—Offset 2Ch

This register is used to program the Clock frequency select, generator select, Clock enable, Internal Clock state fields.

Access Method

Type: MEM Register Device: 30 (Size: 16 bits) Function: 6

Default: 0h

15 12 8 4 0

0000000000000000 RSVD clkctrl_sdclkena clkctrl_intclkena clkctrl_clkgensel clkctrl_sdclkfreqsel clkctrl_sdclkfreqsel_upperbits sdhcclkgen_intclkstable_dsync

252 332219-002

SDXC (D30:F6)

Bit Default & Field Name (ID): Description Range Access

SDCLK Frequency Select (clkctrl_sdclkfreqsel): This register is used to select the frequency of the SDCLK pin. The frequency is not programmed directly; rather this register holds the divisor of the Base Clock Frequency For SD clock in the capabilities register. Only the following settings are allowed. 80h - base clock divided by 256 40h - base clock divided by 128 0h 20h - base clock divided by 64 15:8 RW 10h - base clock divided by 32 08h - base clock divided by 16 04h - base clock divided by 8 02h - base clock divided by 4 01h - base clock divided by 2 00h - base clock(10MHz-63MHz) Setting 00h specifies the highest frequency of the SD Clock.

0h Upper Bits of SDCLK Frequency Select (clkctrl_sdclkfreqsel_upperbits): Bit 7:6 RW 07-06 is assigned to bit 09-08 of clock divider in SDCLK Frequency Select

Clock Generator Select (clkctrl_clkgensel): This bit is used to select the clock generator mode in SDCLK Frequency Select. If the Programmable Clock Mode is supported (non-zero value is set to Clock Multiplier in the Capabilities register), this 0h bit attribute is RW, and if not supported,this bit attribute is RO and zero is read. This 5 bit depends on the setting of Preset Value Enable in the Host Control 2 register. If the RW Preset Value Enable = 0, this bit is set by Host Driver. If the Preset Value Enable = 1, this bit is automatically set to a value specified in one of Preset Value registers. 1: Programmable Clock Mode 0: Divided Clock Mode.

0h 4:3 Reserved. RO

0h SD Clock Enable (clkctrl_sdclkena): The HC shall stop SDCLK when writing this 2 RW bit to 0. SDCLK frequency Select can be changed when this bit is 0.

0h Internal Clock Stable (sdhcclkgen_intclkstable_dsync): This bit is set to 1 1 when SD clock is stable after writing to Internal Clock Enable in this register to 1. The RO SD Host Driver shall wait to set SD Clock Enable until this bit is set to 1.

Internal Clock Enable (clkctrl_intclkena): This bit is set to 0 when the HD is not 0h using the HC or the HC awaits a wakeup event. The HC should stop its internal clock 0 RW to go very low power state. 1 - Oscillate 0 - Stop.

4.2.15 Timeout Control Register (timeoutcontrol)—Offset 2Eh

This value determines the interval by which DAT line time-outs are detected. Refer to the Data Time-out Error in the Error Interrupt Status register for information on factors that dictate time-out generation. Time-out clock frequency will be generated by dividing the sd clock TMCLK by this value. When setting this register, prevent inadvertent time-out events by clearing the Data Time-out Error Status Enable (in the Error Interrupt Status Enable register) 1110 - TMCLK * 2^27 0001 - TMCLK * 2^14 0000 - TMCLK * 2^13.

Access Method

Type: MEM Register Device: 30 (Size: 8 bits) Function: 6

Default: 0h

332219-002 253 SDXC (D30:F6)

74 0

00000000 RSVD timeout_ctrvalue

Bit Default & Field Name (ID): Description Range Access

0h 7:4 Reserved. RO

0h Data Timeout Counter Value (timeout_ctrvalue): This value determines the 3:0 RW interval by which DAT line time-outs are detected.

4.2.16 Software Reset Register (softwarereset)—Offset 2Fh

This register is used to program the software reset for data, command and for all.

Access Method

Type: MEM Register Device: 30 (Size: 8 bits) Function: 6

Default: 0h

74 0

00000000 RSVD swreset_for_all swreset_for_dat swreset_for_cmd

254 332219-002

SDXC (D30:F6)

Bit Default & Field Name (ID): Description Range Access

0h 7:3 Reserved. RO

Software Reset for DAT Line (swreset_for_dat): Only part of data circuit is reset. The following registers and bits are cleared by this bit: Buffer Data Port Register - Buffer is cleared and initialized. Present State register - Buffer read Enable - Buffer write Enable - Read Transfer Active - Write Transfer Active 0h - DAT Line Active 2 RW - Command Inhibit (DAT) Block Gap Control register - Continue Request - Stop At Block Gap Request Normal Interrupt Status register - Buffer Read Ready - Buffer Write Ready - Block Gap Event - Transfer Complete 1 - Reset 0 - Work.

Software Reset for CMD Line (swreset_for_cmd): Only part of command circuit is reset. The following registers and bits are cleared by this bit: Present State register 0h - Command Inhibit (CMD) 1 RW Normal Interrupt Status register - Command Complete 1 - Reset 0 - Work.

SW Reset for All (swreset_for_all): This reset affects the entire HC except for the card detection circuit. Register bits of type ROC, RW, RW1C, RWAC are cleared to 0. During its initialization, the HD shall set this bit to 1 to reset the HC. The HC shall reset this bit to 0 when capabilities registers are valid and the HD can read them. 0h 0 Additional use of Software Reset For All may not affect the value of the Capabilities RW registers. If this bit is set to 1, the SD card shall reset itself and must be re initialized by the HD. 1 - Reset 0 - Work

4.2.17 Normal Interrupt Status Register (normalintrsts)—Offset 30h

This register gives the status of all the interrupts

Access Method

Type: MEM Register Device: 30 (Size: 16 bits) Function: 6

Default: 0h

332219-002 255 SDXC (D30:F6)

15 12 8 4 0

0000000000000000 reg_errorintrsts normalintrsts_intc normalintrsts_inta normalintrsts_intb normalintrsts_cardintsts normalintrsts_cardinssts normalintrsts_rcvbootack normalintrsts_bufrdready normalintrsts_cardremsts normalintrsts_bufwrready normalintrsts_blkgapevent normalintrsts_xfercomplete normalintrsts_dmainterrupt normalintrsts_cmdcomplete normalintrsts_bootcomplete normalintrsts_retuningevent

Bit Default & Field Name (ID): Description Range Access

Error Interrupt (reg_errorintrsts): If any of the bits in the Error Interrupt Status 0h Register are set, then this bit is set. Therefore the HD can test for an error by 15 checking this bit first. RO 0 - No Error 1 – Error.

Boot Terminate Interrupt (normalintrsts_bootcomplete): This status is set if 0h 14 the boot operation get terminated RW1C 0 - Boot operation is not terminated 1 - Boot operation is terminated.

Boot Ack Rcv (normalintrsts_rcvbootack): This status is set if the boot 0h acknowledge is received from device. 13 RW1C 0 - Boot ack is not received 1 - Boot ack is received.

Re-Tuning Event (normalintrsts_retuningevent): This status is set if Re-Tuning Request in the Present State register changes from 0 to 1. Host Controller requests 0h Host Driver to perform re-tuning for next data transfer. Current data transfer (not 12 RO large block count) can be completed without retuning. 1 Re-Tuning should be performed 0 Re-Tuning is not required.

0h INT_C Status (normalintrsts_intc): This status is set if INT_C is enabled and 11 RO INT_C# pin is in low level. It is cleared by resetting the INT_C interrupt factor.

0h INT_B Status (normalintrsts_intb): This status is set if INT_B is enabled and 10 RO INT_B# pin is in low level. It is cleared by resetting

0h INT_A Status (normalintrsts_inta): This status is set if INT_A is enabled and 9 RO INT_A# pin is in low level. It is cleared by resetting

Card Interrupt (normalintrsts_cardintsts): In 1-bit mode, the HC shall detect the Card Interrupt without SD Clock to support wakeup. 0h In 4-bit mode, the card interrupt signal is sampled during the interrupt cycle, so 8 there are some sample delays between the interrupt signal from the card and the RO interrupt to the Host system. 0 - No Card Interrupt 1 - Generate Card Interrupt.

Card Removal (normalintrsts_cardremsts): This status is set if the Card Inserted in the Present State register changes from 1 to 0. When the HD writes this bit to 1 to 0h clear this status the status of the Card Inserted in the Present State register should 7 RW1C be confirmed. 0 - Card State Stable or Debouncing 1 - Card Removed.

Card Insertion (normalintrsts_cardinssts): This status is set if the Card Inserted in the Present State register changes from 0 to 1. When the HD writes this bit to 1 to clear this status the status of the Card Inserted in 0h 6 the Present State register should be confirmed. RW1C Because the card detect may possibly be changed when the HD clear this bit an Interrupt event may not be generated. 0 - Card State Stable or Debouncing 1 - Card Inserted

256 332219-002

SDXC (D30:F6)

Bit Default & Field Name (ID): Description Range Access

Buffer Read Ready (normalintrsts_bufrdready): This status is set if the Buffer 0h Read Enable changes from 0 to 1. Buffer Read Ready is set to 1 for every CMD19 5 execution in tuning procedure. RW1C 0 - Not Ready to read Buffer. 1 - Ready to read Buffer

0h Buffer Write Ready (normalintrsts_bufwrready): This status is set if the Buffer 4 RW1C Write Enable changes from 0 to 1.

0h DMA Interrupt (normalintrsts_dmainterrupt): This status is set if the HC 3 RW1C detects the Host DMA Buffer Boundary in the Block Size regiser.

0h Block Gap Event (normalintrsts_blkgapevent): If the Stop At Block Gap Request 2 RW1C in the BlockGap Control Register is set, this bit is set.

0h Transfer Complete (normalintrsts_xfercomplete): This bit is set when a read / 1 RW1C write transaction is completed.

Command Complete (normalintrsts_cmdcomplete): This bit is set when we get 0h the end bit of the command response (Except Auto CMD12 and Auto CMD23). 0 RW1C 0 - No Command Complete 1 - Command Complete

4.2.18 Error Interrupt Status (errorintrsts)—Offset 32h

This register gives the status of the error interrupts

Access Method

Type: MEM Register Device: 30 (Size: 16 bits) Function: 6

Default: 0h

15 12 8 4 0

0000000000000000 RSVD RSVD errorintrsts_hosterror errorintrsts_admaerror errorintrsts_cmdcrcerror errorintrsts_datacrcerror errorintrsts_currlimiterror errorintrsts_autocmderror errorintrsts_cmdindexerror errorintrsts_cmdendbiterror errorintrsts_dataendbiterror errorintrsts_cmdtimeouterror errorintrsts_datatimeouterror

Bit Default & Field Name (ID): Description Range Access

0h 15:13 Reserved. RO

0h Target Response Error (errorintrsts_hosterror): Occurs when detecting Host 12 RW ERROR

0h 11:10 Reserved. RO

332219-002 257 SDXC (D30:F6)

Bit Default & Field Name (ID): Description Range Access

0h ADMA Error (errorintrsts_admaerror): This bit is set when the Host Controller 9 RW detects errors during ADMA based data transfer.

0h Auto CMD Error (errorintrsts_autocmderror): This bit is set when detecting that 8 RW one of the bits D00-D04 in Auto CMD Error Status register has changed from 0 to 1.

0h Current Limit Error (errorintrsts_currlimiterror): If this bit is 1, it means that 7 the HC is not supplying power to SD card due to some failure.Reading 0 means that RW the HC is supplying power and no error has occurred.

0h Data End Bit Error (errorintrsts_dataendbiterror): Occurs when detecting 0 at 6 the end bit position of read data which uses the DAT line or the end bit position of the RW CRC status.

0h Data CRC Error (errorintrsts_datacrcerror): Occurs when detecting CRC error 5 when transferring read data which uses the DAT line or when detecting the Write CRC RW Status having a value of other than â??010â??.

0h Data Timeout Error (errorintrsts_datatimeouterror): This status is set if Data 4 RW Timeout error occurs.

0h Command Index Error (errorintrsts_cmdindexerror): Occurs if a Command 3 RW Index error occurs in the Command Response.

0h Command End Bit Error (errorintrsts_cmdendbiterror): Occurs when detecting 2 RW that the end bit of a command response is 0.

0h Command CRC Error (errorintrsts_cmdcrcerror): This bit is set when Command 1 RW CRC Error is generated. '0' No Error, '1' CRC Error

0h Command Timeout Error (errorintrsts_cmdtimeouterror): This bit is set if no 0 RW response is returned within 64 SDCLK cycles from the end bit of the command.

4.2.19 Normal Interrupt Status Enable Register (normalintrstsena)—Offset 34h

This register is used to enable the normal interrupt status register fields

Access Method

Type: MEM Register Device: 30 (Size: 16 bits) Function: 6

Default: 0h

15 12 8 4 0

0000000000000000 RSVD sdhcregset_cardintstsena sdhcregset_cardinsstsena sdhcregset_cardremstsena normalintrsts_enableregbit5 normalintrsts_enableregbit4 normalintrsts_enableregbit3 normalintrsts_enableregbit2 normalintrsts_enableregbit1 normalintrsts_enableregbit0 normalintrsts_enableregbit9 normalintrsts_enableregbit14 normalintrsts_enableregbit13 normalintrsts_enableregbit12 normalintrsts_enableregbit11 normalintrsts_enableregbit10

258 332219-002

SDXC (D30:F6)

Bit Default & Field Name (ID): Description Range Access

0h 15 Reserved. RO

0h Boot Terminate Interrupt Enable (normalintrsts_enableregbit14): This status 14 RW is set if the boot operation gets terminated.

0h Boot Ack rcv Enable (normalintrsts_enableregbit13): This status is set if the 13 RW boot acknowledge is received from device.

0h Re-Tuning Event Status Enable (normalintrsts_enableregbit12): This status is 12 RW set if Re-Tuning Request in the Present State register changes from 0 to 1.

0h INT_C Status Enable (normalintrsts_enableregbit11): If this bit is set to 0, the 11 RW Host Controller shall clear the interrupt request to the System.

0h INT_B Status Enable (normalintrsts_enableregbit10): If this bit is set to 0, the 10 RW Host Controller shall clear the interrupt request to the System.

0h INT_A Status Enable (normalintrsts_enableregbit9): If this bit is set to 0, the 9 RW Host Controller shall clear the interrupt request to the System.

0h Card Interrupt Status Enable (sdhcregset_cardintstsena): If this bit is set to 0, 8 the HC shall clear Interrupt request to the System. The Card Interrupt detection is RW stopped when this bit is cleared and restarted when this bit is set to 1.

0h Card Removal Status Enable (sdhcregset_cardremstsena): This status is set if 7 RW the Card Inserted in the Present State register changes from 1 to 0.

0h Card Insertion Status Enable (sdhcregset_cardinsstsena): This status is set if 6 RW the Card Inserted in the Present State register changes from 0 to 1.

0h Buffer Read Ready Status Enable (normalintrsts_enableregbit5): This status 5 RW is set if the Buffer Read Enable changes from 0 to 1.

0h Buffer Write Ready Status Enable (normalintrsts_enableregbit4): This status 4 RW is set if the Buffer Write Enable changes from 0 to 1.

0h DMA Interrupt Status Enable (normalintrsts_enableregbit3): This status is set 3 RW if the HC detects the Host DMA Buffer Boundary in the Block Size regiser.

0h Block Gap Event Status Enable (normalintrsts_enableregbit2): If the Stop At 2 RW Block Gap Request in the BlockGap Control Register is set, this bit is set.

0h Transfer Complete Status Enable (normalintrsts_enableregbit1): This bit is 1 RW set when a read / write transaction is completed.

0h Command Complete Status Enable (normalintrsts_enableregbit0): This bit is 0 RW set when we get the end bit of the command response.

4.2.20 Error Interrupt Status Enable Register (errorintrstsena)— Offset 36h

This register is used to enable the Error Interrupt Status register fields. The register is RW except for the reserved bits which are RO.

Access Method

Type: MEM Register Device: 30 (Size: 16 bits) Function: 6

Default: 0h

332219-002 259 SDXC (D30:F6)

15 12 8 4 0

0000000000000000 RSVD RSVD errorintrsts_enableregbit9 errorintrsts_enableregbit8 errorintrsts_enableregbit7 errorintrsts_enableregbit6 errorintrsts_enableregbit5 errorintrsts_enableregbit4 errorintrsts_enableregbit3 errorintrsts_enableregbit2 errorintrsts_enableregbit1 errorintrsts_enableregbit0 errorintrsts_enableregbit12 errorintrsts_enableregbit10

Bit Default & Field Name (ID): Description Range Access

0h 15:13 Reserved. RO

0h Target Response Error /Host Error Status Enable 12 (errorintrsts_enableregbit12): 0 - Masked RW 1 - Enabled

0h 11 Reserved. RO

0h Tuning error status enable (errorintrsts_enableregbit10): 0 - Masked 10 RW 1 - Enabled

0h ADMA Error Status Enable (errorintrsts_enableregbit9): 0 - Masked 9 RW 1 - Enabled

0h Auto CMD12 Error Status Enable (errorintrsts_enableregbit8): 0 - Masked 8 RW 1 - Enabled

0h Current Limit Error Status Enable (errorintrsts_enableregbit7): 0 - Masked 7 RW 1 - Enabled

0h Data End Bit Error Status Enable (errorintrsts_enableregbit6): 0 - Masked 6 RW 1 - Enabled

0h Data CRC Error Status Enable (errorintrsts_enableregbit5): 0 - Masked 5 RW 1 - Enabled

0h Data Timeout Error Status Enable (errorintrsts_enableregbit4): 0 - Masked 4 RW 1 - Enabled

0h Command Index Error Status Enable (errorintrsts_enableregbit3): 0 - 3 Masked RW 1 - Enabled

0h Command End Bit Error Status Enable (errorintrsts_enableregbit2): 0 - 2 Masked RW 1 - Enabled

0h Command CRC Error Status Enable (errorintrsts_enableregbit1): 0 - Masked 1 RW 1 - Enabled

0h Command Timeout Error Status Enable (errorintrsts_enableregbit0): 0 - 0 Masked RW 1 - Enabled

260 332219-002

SDXC (D30:F6)

4.2.21 Normal Interrupt Signal Enable Register (normalintrsigena)—Offset 38h

This register is used to enable the Normal Interrupt Signal register. All the bits are RW, except for Reserved bits, and defined as follows: 0 - Masked 1 - Enabled.

Access Method

Type: MEM Register Device: 30 (Size: 16 bits) Function: 6

Default: 0h

15 12 8 4 0

0000000000000000 sdhcregset_cardintstsena sdhcregset_cardinsstsena sdhcregset_cardremstsena normalintrsts_enableregbit9 normalintrsts_enableregbit5 normalintrsts_enableregbit4 normalintrsts_enableregbit3 normalintrsts_enableregbit2 normalintrsts_enableregbit1 normalintrsts_enableregbit0 normalintrsts_enableregbit15 normalintrsts_enableregbit14 normalintrsts_enableregbit13 normalintrsts_enableregbit12 normalintrsts_enableregbit11 normalintrsts_enableregbit10

Bit Default & Field Name (ID): Description Range Access

0h normalintrsts_enableregbit15 (normalintrsts_enableregbit15): The HD shall 15 control error Interrupts using the Error Interrupt Signal Enable register.

0h normalintrsts_enableregbit14 (normalintrsts_enableregbit14): Boot 14 Terminate Interrupt Signal Enable

0h normalintrsts_enableregbit13 (normalintrsts_enableregbit13): Boot ack rcv 13 Signal Enable

0h normalintrsts_enableregbit12 (normalintrsts_enableregbit12): Re-Tuning 12 Event Signal Enable

0h normalintrsts_enableregbit11 (normalintrsts_enableregbit11): INT_C Signal 11 Enable

0h normalintrsts_enableregbit10 (normalintrsts_enableregbit10): INT_B Signal 10 Enable

0h normalintrsts_enableregbit9 (normalintrsts_enableregbit9): INT_A Signal 9 Enable

0h sdhcregset_cardintstsena (sdhcregset_cardintstsena): Card Interrupt Signal 8 Enable

0h sdhcregset_cardremstsena (sdhcregset_cardremstsena): Card Removal Signal 7 Enable

0h sdhcregset_cardinsstsena (sdhcregset_cardinsstsena): Card Insertion Signal 6 Enable

332219-002 261 SDXC (D30:F6)

Bit Default & Field Name (ID): Description Range Access

0h normalintrsts_enableregbit5 (normalintrsts_enableregbit5): Buffer Read 5 Ready Signal Enable

0h normalintrsts_enableregbit4 (normalintrsts_enableregbit4): Buffer Write 4 Ready Signal Enable

0h normalintrsts_enableregbit3 (normalintrsts_enableregbit3): DMA Interrupt 3 Signal Enable

0h normalintrsts_enableregbit2 (normalintrsts_enableregbit2): Block Gap Event 2 Signal Enable

0h normalintrsts_enableregbit1 (normalintrsts_enableregbit1): Transfer 1 Complete Signal Enable

0h normalintrsts_enableregbit0 (normalintrsts_enableregbit0): Command 0 Complete Signal Enable

4.2.22 Error Interrupt Signal Enable Register (errorintrsigena)— Offset 3Ah

This register is used to enable the Normal Interrupt Signal register. All the bits are RW, except for Reserved bits, and defined as follows: 0 - Masked 1 - Enabled.

Access Method

Type: MEM Register Device: 30 (Size: 16 bits) Function: 6

Default: 0h

15 12 8 4 0

0000000000000000 RSVD RSVD errorintrsig_enableregbit9 errorintrsig_enableregbit8 errorintrsig_enableregbit7 errorintrsig_enableregbit6 errorintrsig_enableregbit5 errorintrsig_enableregbit4 errorintrsig_enableregbit3 errorintrsig_enableregbit2 errorintrsig_enableregbit1 errorintrsig_enableregbit0 errorintrsig_enableregbit12 errorintrsig_enableregbit10

Bit Default & Field Name (ID): Description Range Access

0h 15:13 Reserved. RO

0h errorintrsig_enableregbit12 (errorintrsig_enableregbit12): Target Response 12 Error Signal Enable

0h 11 Reserved. RO

262 332219-002

SDXC (D30:F6)

Bit Default & Field Name (ID): Description Range Access

0h errorintrsig_enableregbit10 (errorintrsig_enableregbit10): Tuning Error 10 Signal Enable

0h errorintrsig_enableregbit9 (errorintrsig_enableregbit9): ADMA Error Signal 9 Enable

0h errorintrsig_enableregbit8 (errorintrsig_enableregbit8): Auto CMD Error 8 Signal Enable

0h errorintrsig_enableregbit7 (errorintrsig_enableregbit7): Current Limit Error 7 Signal Enable

0h errorintrsig_enableregbit6 (errorintrsig_enableregbit6): Data End Bit Error 6 Signal Enable

0h errorintrsig_enableregbit5 (errorintrsig_enableregbit5): Data CRC Error 5 Signal Enable

0h errorintrsig_enableregbit4 (errorintrsig_enableregbit4): Data Timeout Error 4 Signal Enable

0h errorintrsig_enableregbit3 (errorintrsig_enableregbit3): Command Index 3 Error Signal Enable

0h errorintrsig_enableregbit2 (errorintrsig_enableregbit2): Command End Bit 2 Error Signal Enable

0h errorintrsig_enableregbit1 (errorintrsig_enableregbit1): Command CRC Error 1 Signal Enable

0h errorintrsig_enableregbit0 (errorintrsig_enableregbit0): Command Timeout 0 Error Signal Enable

4.2.23 Auto CMD12 Error Status Register (autocmderrsts)—Offset 3Ch

This register is used to indicate CMD12 response error of Auto CMD12 and CMD23 response error of Auto CMD 23

Access Method

Type: MEM Register Device: 30 (Size: 16 bits) Function: 6

Default: 0h

15 12 8 4 0

0000000000000000 RSVD RSVD autocmderrsts_crcerror autocmderrsts_nexterror autocmderrsts_indexerror autocmderrsts_endbiterror autocmderrsts_timeouterror autocmderrsts_notexecerror

332219-002 263 SDXC (D30:F6)

Bit Default & Field Name (ID): Description Range Access

0h 15:8 Reserved. RO

Command Not Issued By Auto CMD12 Error (autocmderrsts_nexterror): Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 0h error(D04- D01) in this register. This bit is set to 0 when Auto CMD Error is generated 7 RO by Auto CMD23 0 – No Error 1 – Not Issued

0h 6:5 Reserved. RO

Auto CMD Index Error (autocmderrsts_indexerror): Occurs if the Command 0h Index error occurs in response to a command. 4 RO 0 – No Error 1 – Error

Auto CMD End Bit Error (autocmderrsts_endbiterror): Occurs when detecting 0h 3 that the end bit of command response is 0. RO 0 – No Error 1 – End Bit Error Generated

Auto CMD CRC Error (autocmderrsts_crcerror): Occurs when detecting a CRC 0h error in the command response. 2 RO 0 – No Error 1 – CRC Error Generated

Auto CMD Timeout Error (autocmderrsts_timeouterror): Occurs if the no 0h response is returned within 64 SDCLK cycles from the end bit of the command. 1 If this bit is set to 1, the other error status bits (D04 - D02) are meaningless. 0 - No RO Error 1 - Timeout.

Auto CMD12 not Executed (autocmderrsts_notexecerror): If memory multiple block data transfer is not started due to command error, this bit is not set because it 0h is not necessary to issue Auto CMD12. Setting this bit to 1 means the HC cannot 0 RO issue Auto CMD12 to stop memory multiple block transfer due to some error. 0 - Executed 1 - Not Executed.

4.2.24 Host Control 2 Register (hostcontrol2)—Offset 3Eh

This register is used to program UHS Select Mode,UHS Select Mode,Driver Strength Select,Execute Tuning,Sampling Clock Select,Asynchronous Interrupt Enable and Preset value enable

Access Method

Type: MEM Register Device: 30 (Size: 16 bits) Function: 6

Default: 0h

264 332219-002

SDXC (D30:F6)

15 12 8 4 0

0000000000000000 RSVD RSVD hostctrl2_executetuning hostctrl2_driverstrength hostctrl2_uhsmodeselect hostctrl2_asynchintrenable hostctrl2_samplingclkselect hostctrl2_1p8vsignallingena hostctrl2_presetvalueenable hostctrl2_driverstrength_bit2

Bit Default & Field Name (ID): Description Range Access

0h hostctrl2_presetvalueenable (hostctrl2_presetvalueenable): This bit enables 15 the functions defined in the Preset Value registers.

Asynchronous Interrupt Enable (hostctrl2_asynchintrenable): This bit can be 0h set to 1 if a card support asynchronous interrupt and Asynchronous Interrupt Support 14 is set to 1 in the Capabilities register. RW 0 – Disabled 1 – Enabled.

0h 13:10 Reserved. RO

0h Driver strength (hostctrl2_driverstrength_bit2): This is the programmed Drive 9 RW Strength output and it[2] of the sdhccore_drivestrength value.

0h 8 Reserved. RO

Sampling Clock Select (hostctrl2_samplingclkselect): This bit is set by tuning procedure when Execute Tuning is cleared. Writing 1 to this bit is meaningless and 0h ignored. Setting 1 means that tuning is completed successfully and setting 0 means 7 RW that tuning is failed. Controller is receiving response or a read data block. 0 - Fixed clock is used to sample data 1 - Tuned clock is used to sample data

Execute Tuning (hostctrl2_executetuning): This bit is set to 1 to start tuning procedure and automatically cleared when tuning procedure is completed. The result 0h of tuning is indicated to Sampling Clock Select. Tuning procedure is aborted by 6 RW writing 0 for more detail about tuning procedure. 0 - Not Tuned or Tuning Completed 1 - Execute Tuning.

0h Driver Strength Select (hostctrl2_driverstrength): Host Controller output driver 5:4 RW in 1.8V signaling is selected by this bit. In 3.3V signaling, this field is not effective.

0h 1.8V Signaling Enable (hostctrl2_1p8vsignallingena): This bit controls voltage 3 regulator for I/O cell. 3.3V is supplied to the card regardless of signaling voltage. RW Setting this bit from 0 to 1 starts changing signal voltage from 3.3V to 1.8V.

UHS Mode Select (hostctrl2_uhsmodeselect): This field is used to select one of UHS-I modes and effective when 1.8V Signaling Enable is set to 1. Select in the Clock Control register and Driver Strength Select according to Preset Value registers. In this case, one of preset value registers is selected by this field. Host Driver needs to reset SD Clock Enable before changing this field to avoid 0h generating clock glitch. After setting this field, Host Driver sets SD Clock Enable 2:0 again. RW 000b - SDR12 001b - SDR25 010b - SDR50 011b - SDR104 100b - DDR50 101b - HS400

332219-002 265 SDXC (D30:F6)

4.2.25 Capabilities Register (capabilities)—Offset 40h

This register provides the host driver with information specific to the host controller implementation. Please note, that the default values shown here assume no bypass of the capabilities register. In case software decides to bypass the default capabilities register values the reset values will present the bypassed value.

Access Method

Type: MEM Register Device: 30 (Size: 64 bits) Function: 6

Default: 0h

6 6 5 5 4 4 4 3 3 2 2 2 1 1 840 3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000 RSVD RSVD RSVD RSVD RSVD RSVD corecfg_slottype corecfg_spisupport corecfg_spiblkmode corecfg_baseclkfreq corecfg_8bitsupport corecfg_64bitsupport corecfg_sdmasupport corecfg_type4support corecfg_sdr50support corecfg_ddr50support corecfg_maxblklength corecfg_hs400support corecfg_timeoutclkunit corecfg_clockmultiplier corecfg_timeoutclkfreq corecfg_adma2support corecfg_cdriversupport corecfg_sdr104support corecfg_adriversupport corecfg_ddriversupport corecfg_tuningforsdr50 corecfg_retuningmodes corecfg_1p8voltsupport corecfg_3p0voltsupport corecfg_3p3voltsupport corecfg_suspressupport corecfg_retuningtimercnt corecfg_highspeedsupport corecfg_asynchintrsupport

Bit Default & Field Name (ID): Description Range Access

HS 400 Support (corecfg_hs400support): This field indicates whether HS400 is 0h supported or not. 63 RO 0 –Not Supported 1 –Supported

0h 62:58 Reserved. RO

SPI Block Mode (corecfg_spiblkmode): This field indicates whether SPI Block 0h 57 Mode is supported or not. RO 0 –Not Supported 1 –Supported

SPI Mode Support (corecfg_spisupport): This field indicates whether SPI Mode is 0h supported or not. 56 RO 0 –Not Supported 1 –Supported

0h Clock Multiplier (corecfg_clockmultiplier): This field indicates clock multiplier 55:48 value of programmable clock generator. Setting 00h means that Host Controller does RO not support programmable clock generator.

Re-tuning Modes (corecfg_retuningmodes): This field defines the re-tuning capability of a Host Controller and how to manage the data transfer length and a Re- Tuning Timer by the Host Driver 00 - Mode1 0h 01 - Mode2 47:46 RO 10 - Mode3 11 - Reserved There are two re-tuning timings: Re-Tuning Request and expiration of a Re-Tuning Timer. By receiving either timing, the Host Driver executes the re-tuning procedure just before a next command issue.

266 332219-002

SDXC (D30:F6)

Bit Default & Field Name (ID): Description Range Access

Use Tuning for SDR50 (corecfg_tuningforsdr50): If this bit is set to 1, this Host 0h Controller requires tuning to operate SDR50. (Tuning is always required to operate 45 SDR104.) RO 1 SDR50 requires tuning 0 SDR50 does not require tuning

0h 44 Reserved. RO

Timer count for Re-Tuning (corecfg_retuningtimercnt): This field indicates an initial value of the Re-Tuning Timer for Re-Tuning Mode 1 to 3. 0h - Get information via other source 1h = 1 seconds 2h = 2 seconds 0h 3h = 4 seconds 43:40 RO 4h = 8 seconds -- n = 2(n-1) seconds -- Bh = 1024 seconds Fh - Ch = Reserved

0h Driver Type 4 Support (corecfg_type4support): This bit indicates support of 39 RO Type 4 Driver.

0h Driver Type D Support (corecfg_ddriversupport): This bit indicates support of 38 RO Driver Type D for 1.8 Signaling.

0h Driver Type C Support (corecfg_cdriversupport): This bit indicates support of 37 RO Driver Type C for 1.8 Signaling.

0h Driver Type A Support (corecfg_adriversupport): This bit indicates support of 36 RO Driver Type A for 1.8 Signaling.

0h 35 Reserved. RO

0h DDR50 Support (corecfg_ddr50support): This bit indicates whether DDR50 is 34 RO supported.

0h SDR104 Support (corecfg_sdr104support): This bit indicates whether SDR104 is 33 RO supported.SDR104 requires tuning.

0h SDR50 Support (corecfg_sdr50support): This bit indicates whether SDR50 is 32 RO supported.

Slot Type (corecfg_slottype):

0h 00b Removable Card Slot 31:30 01b Embedded Slot for One Device RO 10b Shared Bus Slot 11b Reserved

0h Asynchronous Interrupt Support (corecfg_asynchintrsupport): Asynchronous 29 RO Interrupt Support

0h 64-bit System Bus Support (corecfg_64bitsupport): This bit indicates whether 28 RO the HC supports 64bit System Bus

0h 27 Reserved. RO

0h Voltage Support 1.8V (corecfg_1p8voltsupport): This bit indicates whether the 26 RO HC supports 1.8V.

0h Voltage Support 3.0V (corecfg_3p0voltsupport): This bit indicates whether the 25 RO HC supports 3.0V.

0h Voltage Support 3.3V (corecfg_3p3voltsupport): This bit indicates whether the 24 RO HC supports 3.3V.

0h Suspend / Resume Support (corecfg_suspressupport): This bit indicates 23 RO whether the HC supports Suspend/Resume functionality.

332219-002 267 SDXC (D30:F6)

Bit Default & Field Name (ID): Description Range Access

SDMA Support (corecfg_sdmasupport): This bit indicates whether the HC is 0h capable of using DMA to transfer data between system memory and the HC directly. 22 (SDMA Mode) RO 0 –Not Supported 1 –Supported

High Speed Support (corecfg_highspeedsupport): This bit indicates whether the 0h HC and the Host System support High Speed mode. 21 RO 0 –Not Supported 1 –Supported

0h 20 Reserved. RO

0h ADMA2 Support (corecfg_adma2support): ADMA2 not supported. Hardwired to 19 RO 0.

0h 8 Bit Support for Embedded Device (corecfg_8bitsupport): This bit indicates 18 RO whether the Host Controller is capable of using 8-bit bus width mode.

Max Block Length (corecfg_maxblklength): This value indicates the maximum block size that the HD can read and write to the buffer in the HC. The buffer shall 0h transfer this block size without wait cycles. Sizes can be defined as indicated below. 17:16 00 - 512 byte RO 01 - 1024 byte 10 - 2048 byte 11 - 4096 byte.

Base Clock Frequency for SD Clock (corecfg_baseclkfreq): (1) 6-bit Base Clock Frequency This mode is supported by the Host Controller Version 1.00 and 2.00. Upper 2- bit is not effective and always 0. Unit values are 1MHz. The supported clock range is 10MHz to 63MHz. 0011 1111b 63MHz 0h 15:8 0000 0010b 2MHz RO 0000 0001b 1MHz (2) 8-bit Base Clock Frequency This mode is supported by the Host Controller Version 3.00. Unit values are 1MHz. The supported clock range is 10MHz to 255MHz. FFh 255MHz 02h 2MHz 01h 1MHz.

Timeout Clock Unit (corecfg_timeoutclkunit): This bit shows the unit of base 0h 7 clock frequency used to detect Data Timeout Error. RO 0 - KHz 1 - MHz

0h 6 Reserved. RO

0h Timeout Clock Frequency (corecfg_timeoutclkfreq): This bit shows the base 5:0 clock frequency used to detect Data Timeout Error. RO Not 0 - 1Khz to 63Khz or 1Mhz to 63Mhz.

4.2.26 Maximum Current Capabilities Register (maxcurrentcap)— Offset 48h

This register indicates maximum current capability for each voltage

Access Method

Type: MEM Register Device: 30 (Size: 64 bits) Function: 6

Default: 0h

268 332219-002

SDXC (D30:F6)

6 6 5 5 4 4 4 3 3 2 2 2 1 1 840 3 0 6 2 8 4 0 6 2 8 4 0 6 2

0000000000000000000000000000000000000000000000000000000000000000 RSVD corecfg_maxcurrent1p8v corecfg_maxcurrent3p0v corecfg_maxcurrent3p3v

Bit Default & Field Name (ID): Description Range Access

0h 63:24 Reserved. RO

Maximum Current for 1.8V (corecfg_maxcurrent1p8v): Maximum Current for 3.3V 0 – Get value via another method 0h 23:16 1 – 4mA RO 2 – 8mA 3 – 12mA … 255 – 1020mA

Maximum Current for 3.0V (corecfg_maxcurrent3p0v): Maximum Current for 3.3V 0 – Get value via another method 0h 15:8 1 – 4mA RO 2 – 8mA 3 – 12mA … 255 – 1020mA

Maximum Current for 3.3V (corecfg_maxcurrent3p3v): Maximum Current for 3.3V 0 – Get value via another method 0h 7:0 1 – 4mA RO 2 – 8mA 3 – 12mA … 255 – 1020mA

4.2.27 Force Event REGISTER for AUTO CMD Error Status (ForceEventforAUTOCMDErrorStatus)—Offset 50h

All bits in this register are RO.

Access Method

Type: MEM Register Device: 30 (Size: 16 bits) Function: 6

Default: 0h

332219-002 269 SDXC (D30:F6)

15 12 8 4 0

0000000000000000 RSVD RSVD forceautocmdcrcerr forceautocmdnotexec forceautocmdindexerr forceautocmdendbiterr forceautocmdtimeouterr forcecmdnotissuedbyautocmd12err

Bit Default & Field Name (ID): Description Range Access

0h 15:8 Reserved. RO

0h forcecmdnotissuedbyautocmd12err (forcecmdnotissuedbyautocmd12err): 7 Force Event for Command Not Issued by AUTO CMD12 Error

0h 6:5 Reserved. RO

0h forceautocmdindexerr (forceautocmdindexerr): Force Event for AUTO CMD 4 Index Error

0h forceautocmdendbiterr (forceautocmdendbiterr): Force Event for AUTO CMD 3 End Bit Error

0h forceautocmdcrcerr (forceautocmdcrcerr): Force Event for AUTO CMD Timeout 2 Error

0h forceautocmdtimeouterr (forceautocmdtimeouterr): Force Event for AUTO CMD 1 Timeout Error

0h forceautocmdnotexec (forceautocmdnotexec): Force Event for AUTO CMD12 0 Not Executed

4.2.28 Force Event Register for Error Interrupt Status (forceeventforerrintsts)—Offset 52h

All bits in this register are RO.

Access Method

Type: MEM Register Device: 30 (Size: 16 bits) Function: 6

Default: 0h

270 332219-002

SDXC (D30:F6)

15 12 8 4 0

0000000000000000 RSVD forceadmaerr forcedatcrcerr forcetuningerr forcecurrlimerr forcecmdcrcerr forceautocmderr forcedatendbiterr forcecmdindexerr forcecmdendbiterr forcedattimeouterr forcecmdtimeouterr

Bit Default & Field Name (ID): Description Range Access

0h 15:11 Reserved. RO

0h forcetuningerr (forcetuningerr): Force Event for Tuning Error 10

0h forceadmaerr (forceadmaerr): Force Event for ADMA Error'0' no interrupt, '1' 9 interrupt generated

0h forceautocmderr (forceautocmderr): Force Event for Auto CMD Error '0' no 8 interrupt, '1' interrupt generated

0h forcecurrlimerr (forcecurrlimerr): Force Event for Current Limit Error '0' no 7 interrupt, '1' interrupt generated

0h forcedatendbiterr (forcedatendbiterr): Force Event for Data End Bit Error. '0' no 6 interrupt, '1' interrupt generated

0h forcedatcrcerr (forcedatcrcerr): Force Event for Data CRC Error 5

0h forcedattimeouterr (forcedattimeouterr): Force Event for Data Timeout Error '0' 4 no interrupt, '1' interrupt generated

0h forcecmdindexerr (forcecmdindexerr): Force Event for Command Index Error 3

0h forcecmdendbiterr (forcecmdendbiterr): Force Event for Command End Bit Error 2 '0' no interrupt, '1' interrupt generated

0h forcecmdcrcerr (forcecmdcrcerr): Force Event for Command CRC Error 1

0h forcecmdtimeouterr (forcecmdtimeouterr): Force Event for CMD Timeout Error 0 '0' No interrupt, '1' interrupt generated

4.2.29 ADMA Error Status Register (admaerrsts)—Offset 54h

All bits in this register are RO

Access Method

Type: MEM Register Device: 30 (Size: 8 bits) Function: 6

Default: 0h

332219-002 271 SDXC (D30:F6)

74 0

00000000 RSVD admaerrsts_admaerrorstate admaerrsts_admalenmismatcherr

Bit Default & Field Name (ID): Description Range Access

0h 7:3 Reserved. RO

0h admaerrsts_admalenmismatcherr (admaerrsts_admalenmismatcherr): 2 ADMA Length Mismatch Error

ADMA Error State (admaerrsts_admaerrorstate): This field indicates the state of ADMA when error is occurred during ADMA data transfer. This field never indicates "10" because ADMA never stops in this state.

0h D01 – D00 : ADMA Error State when error occurred Contents of SYS_SDR register 1:0 00 - ST_STOP (Stop DMA) RO Points to next of the error descriptor 01 - ST_FDS (Fetch Descriptor) Points to the error descriptor 10 - Never set this state (Not used) 11 - ST_TFR (Transfer Data) Points to the next of the error descriptor

4.2.30 ADMA System Address Register0&1 (admasysaddr01)— Offset 58h

This register contains the physical address used for ADMA data transfer

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 6

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 adma_sysaddress0

272 332219-002

SDXC (D30:F6)

Bit Default & Field Name (ID): Description Range Access

0h adma_sysaddress0 (adma_sysaddress0): This register holds byte address of 31:0 RW executing command of the Descriptor table.

4.2.31 ADMA System Address Register1 (admasysaddr2)—Offset 5Ch

This register contains the physical address used for ADMA data transfer

Access Method

Type: MEM Register Device: 30 (Size: 16 bits) Function: 6

Default: 0h

15 12 8 4 0

0000000000000000 adma_sysaddress2

Bit Default & Field Name (ID): Description Range Access

0h adma_sysaddress2 (adma_sysaddress2): This register holds byte address of 15:0 RW executing command of the Descriptor table.

4.2.32 ADMA System Address Register1 (admasysaddr3)—Offset 5Eh

This register contains the physical address used for ADMA data transfer

Access Method

Type: MEM Register Device: 30 (Size: 16 bits) Function: 6

Default: 0h

332219-002 273 SDXC (D30:F6)

15 12 8 4 0

0000000000000000 adma_sysaddress3

Bit Default & Field Name (ID): Description Range Access

0h adma_sysaddress3 (adma_sysaddress3): This register holds byte address of 15:0 RW executing command of the Descriptor table.

4.2.33 Preset Value Register for Initialization (Preset Value 0)— Offset 60h

All bits in this register are RO.

Access Method

Type: MEM Register Device: 30 (Size: 16 bits) Function: 6

Default: 3h

15 12 8 4 0

0000000000000011 RSVD DriverStrengthSelectValue ClockGeneratorSelectValue SDCLKFrequencySelectValue

Bit Default & Field Name (ID): Description Range Access

0h DriverStrengthSelectValue (DriverStrengthSelectValue): Driver Strength 15:14 Select Value

0h 13:11 Reserved. RO

0h ClockGeneratorSelectValue (ClockGeneratorSelectValue): This bit is effective 10 when Host Controller supports programmable clock

3h SDCLKFrequencySelectValue (SDCLKFrequencySelectValue): 10-bit preset 9:0 value to set SDCLK Frequency Select in the Clock Control Register is described by a host system.

274 332219-002

SDXC (D30:F6)

4.2.34 Preset Value Register for Default Speed (Preset Value 1)— Offset 62h

Same description as Preset Value 0 register.

4.2.35 Preset Value Register for High Speed (presetvalue2)— Offset 64h

Same description as Preset Value 0 register.

4.2.36 Preset Value Register for SDR12 (presetvalue3)—Offset 66h

Same description as Preset Value 0 register.

4.2.37 Preset Value Register for SDR25 (presetvalue4)—Offset 68h

Same description as Preset Value 0 register.

4.2.38 Preset Value Register for SDR50 (presetvalue5)—Offset 6Ah

Same description as Preset Value 0 register.

4.2.39 Preset Value Register for SDR104 (presetvalue6)—Offset 6Ch

Same description as Preset Value 0 register.

4.2.40 Preset Value Register for DDR50 (presetvalue7)—Offset 6Eh

Same description as Preset Value 0 register.

4.2.41 Slot Interrupt Status Register (slotintrsts)—Offset FCh

This register is used to read the interrupt signal for each slot.

Access Method

Type: MEM Register Device: 30 (Size: 16 bits) Function: 6

Default: 0h

332219-002 275 SDXC (D30:F6)

15 12 8 4 0

0000000000000000 RSVD sdhchostif_slotintrsts

Bit Default & Field Name (ID): Description Range Access

0h 15:8 Reserved. RO

0h sdhchostif_slotintrsts (sdhchostif_slotintrsts): These status bits indicate the 7:0 RO logical OR of Interrupt signal and Wakeup signal for each slot.

4.2.42 Host Controller Version Register (hostcontrollerver)— Offset FEh

This register is used to read the vendor version number and specification version number

Access Method

Type: MEM Register Device: 30 (Size: 16 bits) Function: 6

Default: 1002h

15 12 8 4 0

0001000000000010 SDHC_VENVERNUM SpecificationVersionNumber

Bit Default & Field Name (ID): Description Range Access

10h SDHC_VENVERNUM (SDHC_VENVERNUM): This status is reserved for the vendor 15:8 RO version number.

2h SpecificationVersionNumber (SpecificationVersionNumber): This status 7:0 indicates the Host Controller Spec. Version. The upper and lower 4-bits indicate the RO version.

276 332219-002

SDXC (D30:F6)

4.3 SDXC Additional Registers Summary

These registers are memory mapped based on BAR0 defined in PCI configuration space.

Table 4-3. Summary of SDXC Additional Registers

Offset Offset Default Register Name (ID)—Offset Start End Value

804h 807h Software LTR Value (SW_LTR_val)—Offset 804h 800h

808h 80Bh Auto LTR Value (Auto_LTR_val)—Offset 808h 800h

810h 813h (Cap_byps)—Offset 810h 0h

814h 817h (Cap_byps_reg1)—Offset 814h 3001EF3Ch

818h 81Bh (Cap_byps_reg2)—Offset 818h 4004000h

81Ch 81Fh (reg_D0i3)—Offset 81Ch 0h

820h 823h (Tx_CMD_dly)—Offset 820h 400h

824h 827h (Tx_DATA_dly_1)—Offset 824h A18h

828h 82Bh (Tx_DATA_dly_2)—Offset 828h 1C1C1C00h

82Ch 82Fh (Rx_CMD_Data_dly_1)—Offset 82Ch 1C1C1C00h

830h 833h (Rx_Strobe_Ctrl_Path)—Offset 830h 500h

834h 837h (Rx_CMD_Data_dly_2)—Offset 834h 181Ch

838h 83Bh (Master_Dll)—Offset 838h 1h

840h 843h (Auto_tuning)—Offset 840h 0h

4.3.1 Software LTR Value (SW_LTR_val)—Offset 804h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 6

Default: 800h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000100000000000 RSVD RSVD Snoop_value Snoop_Requirment Snoop_latency_scale

332219-002 277 SDXC (D30:F6)

Bit Default & Field Name (ID): Description Range Access

0h 31:16 Reserved. RO

Snoop_Requirment: If the Requirement (bit 15) is clear, that indicates that the 0h 15 device has no LTR requirement for this type of traffic (i.e. it can wait for service RW indefinitely). If the 10-bit latency value is zero it indicates that the device cannot tolerate any delay and needs the best possible service/response time.

0h 14:13 Reserved. RO

2h Snoop_latency_scale: Support for codes 010 (1us) or 011 (32us) for Snoop 12:10 Latency Scale(1us -) 32ms total span) only. Writes to this CSR which dont match RW those values will be dropped completely, next read will return previous value.

0h Snoop_value: 10-bit latency value 9:0 RW

4.3.2 Auto LTR Value (Auto_LTR_val)—Offset 808h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 6

Default: 800h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000100000000000 RSVD RSVD Snoop_value Snoop_Requirment Snoop_latency_scale

Bit Default & Field Name (ID): Description Range Access

0h 31:16 Reserved. RO

Snoop_Requirment: If the Requirement (bit 15) is clear, that indicates that the 0h device has no LTR requirement for this type of traffic (i.e. it can wait for service 15 RW indefinitely). If the 10-bit latency value is zero it indicates that the device cannot tolerate any delay and needs the best possible service/response time.

0h 14:13 Reserved. RO

2h Snoop_latency_scale: Support for codes 010 (1us) or 011 (32us) for Snoop 12:10 Latency Scale(1us -) 32ms total span) only. Writes to this CSR which dont match RW those values will be dropped completely, next read will return previous value.

0h Snoop_value: 10-bit latency value 9:0 RW

278 332219-002

SDXC (D30:F6)

4.3.3 (Cap_byps)—Offset 810h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 6

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD Enable_Cap_Bypass

Bit Default & Field Name (ID): Description Range Access

0h 31:8 Reserved. RO

0h Enable_Cap_Bypass: 8â??h5A â?? Enable Capabilities Bypass. All other â?? 7:0 RW Capabilities Bypass Disable (using default values)

4.3.4 (Cap_byps_reg1)—Offset 814h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 6

Default: 3001EF3Ch

3 2 2 2 1 1 840 1 8 4 0 6 2

00110000000000011110111100111100 RSVD Slot_Type timer_count sdr50_support ddr50_support hs400_support SDMA_Support sdr104_support ADMA2_Support tuning_for_SDR50 Max_Burst_Length timeout_clock_unit SPI_mode_support timeout_clock_freq Voltage_Support_3V High_Speed_Support Voltage_Support_1_8V Voltage_Support_3_3V Sys_Addr_64bit_Support Async_Interrupt_Support Suspend_Resume_Support

332219-002 279 SDXC (D30:F6)

Bit Default & Field Name (ID): Description Range Access

0h 31:30 Reserved. RO

1h hs400_support: 1: HS400 Mode Supported. 0: HS400 Mode NOT Supported 29 RW

1h timeout_clock_unit: 1â??b1 - to Select MHz Clock ,1â??b0 - to Select KHz Clock 28 RW

0h timeout_clock_freq: Timeout clock frequency 27:22 RW

0h SPI_mode_support: SPI Mode Support 1â??b1 â?? SPI Mode Supported ,1â??b0 21 RW â?? SPI Mode Not Supported

0h timer_count: Timer Count for Re-Tuning This is the Timer Count for Re-Tuning Timer 20:17 RW for Re-Tuning Mode 1 to 3. Setting to 4â??b0 disables Re-Tuning Timer

1h tuning_for_SDR50: Use Tuning for SDR50 1â??b1 â?? Use Tuning 1â??b0 â?? 16 RW Donâ??t use Tuning

1h ddr50_support: 1: DDR50 Mode Supported. 0: DDR50 Mode NOT Supported 15 RW

1h sdr104_support: 1: SDR104 Mode Supported. 0: SDR104 Mode NOT Supported 14 RW

1h sdr50_support: 1: SDR50 Mode Supported. 0: SDR50 Mode NOT Supported 13 RW

1h Slot_Type: 00 - Removable SD Card Slot. 01 - Embedded Slot for One Device. 10 - 12:11 RW Shared Bus Slot. 11 - Reserved

1h Async_Interrupt_Support: 1: Asynchronous Interrupt Supported. 0: 10 RW Asynchronous Interrupt NOT Supported

1h Sys_Addr_64bit_Support: 1 - Core supports 64-bit System Address Bus. 0 - Core 9 RW supports only 32-bit System Address Bus

1h Voltage_Support_1_8V: 1: 1.8V Supported. 0: 1.8V NOT Supported 8 RW

0h Voltage_Support_3V: 1: 3.0V Supported. 0: 3.0V NOT Supported 7 RW

0h Voltage_Support_3_3V: 1: 3.3V Supported. 0: 3.3V NOT Supported 6 RW

1h Suspend_Resume_Support: 1: Suspend/Resume Supported. 0: Suspend/Resume 5 RW NOT Supported

1h SDMA_Support: 1: SDMA mode Supported. 0: SDMA mode NOT Supported 4 RW

1h High_Speed_Support: 1: HIGH_SPEED mode Supported. 0: HIGH_SPEED mode 3 RW NOT Supported

1h ADMA2_Support: 1: ADMA2 mode Supported. 0: ADMA2 mode NOT Supported 2 RW

0h Max_Burst_Length: Maximum Block Length supported by the Core/Device. 00: 512 1:0 RW (Bytes). 01: 1024. 10: 2048. 11: Reserved

4.3.5 (Cap_byps_reg2)—Offset 818h

Access Method

280 332219-002

SDXC (D30:F6)

Type: MEM Register Device: 30 (Size: 32 bits) Function: 6

Default: 4004000h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000100000000000100000000000000 RSVD RSVD RSVD tuning_dis driver_type_4 driver_type_A driver_type_C driver_type_D base_sd_clock tuning_count_val support_8_bit_embedded

Bit Default & Field Name (ID): Description Range Access

0h 31:27 Reserved. RO

20h tuning_count_val: Tuning Count Value Configures the Number of Taps (Phases) of 26:21 the rxclk_in that is supported. The Tuning State machine uses this information to RW select one of the Taps (Phases) of the rxclk_in during the Tuning Procedure.

0h tuning_dis: Disable the 1.5x Tuning count when calculating total tuning count. The 20 internal tuning count will be set to the corecfg_Tuningcount when this signal is RW asserted

0h driver_type_4: Driver Type 4 Support 1â??b1 â?? Supported 1â??b0 â?? NOT 19 RW Supported

0h driver_type_D: Driver Type D Support 1â??b1 â?? Supported 1â??b0 â?? NOT 18 RW Supported

0h driver_type_C: Driver Type C Support 1â??b1 â?? Supported 1â??b0 â?? NOT 17 RW Supported

0h driver_type_A: Driver Type A Support 1â??b1 â?? Supported 1â??b0 â?? NOT 16 RW Supported

0h 15 Reserved. RO

1h support_8_bit_embedded: 8-bit Support for Embedded Device 1â??b1 â?? 14 RW Supported 1â??b0 â?? NOT Supported

0h 13:8 Reserved. RO

0h base_sd_clock: Base Clock Frequency for SD Clock 7:0 RW

4.3.6 (reg_D0i3)—Offset 81Ch

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 6

Default: 0h

332219-002 281 SDXC (D30:F6)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 D0i3 RSVD RestoreRequired Cmd_In_Progress Interrupt_Request Interrupt_Req_Capable

Bit Default & Field Name (ID): Description Range Access

0h 31:5 Reserved. RO

0h Interrupt_Req_Capable: 0 â?? HW not capable to issue in interrupt on command 4 RO completion. 1 â?? HW capable to issue an interrupt on command completion

0h RestoreRequired: When set (by HW), SW must restore state to the IP. The state 3 may have been lost due to a reset or full power lost. SW clears the bit by writing a 1. RO This bit will be set on initial power up.

0h D0i3: SW sets this bit to 1 to move the IP into the D0i3 state. Writing this bit to 0 will 2 RW return the IP to the fully active D0 state (D0i0).

0h Interrupt_Request: SW sets this bit to 1 to ask for an interrupt to be generated on 1 completion of the command. SW must clear or set this on each write to this register. RO Not supported in SCS!

Cmd_In_Progress: HW sets this bit on a 1->0 or 0->1 transition of bit [2]. While set, the other bits in this register are not valid and it is illegal for SW to write to any 0h bit in this register. When clear all the other bits in the register are valid and SW may 0 RO write to any bit. If Interrupt Request bit [1] was set for the current command, HW may clear this bit before the interrupt has been made visible to SW, since when SW actually handles

4.3.7 (Tx_CMD_dly)—Offset 820h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 6

Default: 400h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000010000000000 RSVD RSVD sdr_mode ddr_mode

282 332219-002

SDXC (D30:F6)

Bit Default & Field Name (ID): Description Range Access

0h 31:15 Reserved. RO

4h ddr_mode: Tx CMD Delay (DDR Mode). 0 â?? 39 â?? Select number of active delay 14:8 RW elements. Each = 125pSec. 40 â?? 127 â?? Reserved

0h 7 Reserved. RO

0h sdr_mode: Tx CMD Delay (SDR Mode). 0 â?? 39 â?? Select number of active delay 6:0 RW elements. Each = 125pSec. 40 â?? 127 - Reserved

4.3.8 (Tx_DATA_dly_1)—Offset 824h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 6

Default: A18h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000101000011000 RSVD RSVD hs400_mode sdr104_hs200

Bit Default & Field Name (ID): Description Range Access

0h 31:15 Reserved. RO

Ah hs400_mode: Tx Data Delay (HS400 Mode). 0 â?? 78 â?? Select number of active 14:8 RW delay elements. Each = 125pSec. 79 â?? 127 - Reserved

0h 7 Reserved. RO

18h sdr104_hs200: Tx Data Delay (SDR104/HS200 Mode) 0-79 - Select the required 6:0 RW delay, as a multiple of 125pSec.80 â?? 127 â?? Reserved

4.3.9 (Tx_DATA_dly_2)—Offset 828h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 6

Default: 1C1C1C00h

332219-002 283 SDXC (D30:F6)

3 2 2 2 1 1 840 1 8 4 0 6 2

00011100000111000001110000000000 RSVD RSVD RSVD RSVD sdr50_mode ddr50_mode sdr25_hs50_mode sdr12_comp_mode

Bit Default & Field Name (ID): Description Range Access

0h 31 Reserved. RO

1Ch sdr50_mode: Tx Data Delay (SDR50 Mode) 0-79 - Select the required delay, as a 30:24 RW multiple of 125pSec. 80 â?? 127 â?? Reserved

0h 23 Reserved. RO

1Ch ddr50_mode: Tx Data Delay (DDR50 Mode). 0 â?? 78 â?? Select number of active 22:16 RW delay elements. Each = 125pSec. 79 â?? 127 - Reserved

0h 15 Reserved. RO

1Ch sdr25_hs50_mode: Tx Data Delay (SDR25/HS50 Mode)0-79 - Select the required 14:8 RW delay, as a multiple of 125pSec.80 â?? 127 â?? Reserved

0h 7 Reserved. RO

0h sdr12_comp_mode: Tx Data Delay (SDR12/Compatibility Mode) 0-79 - Select the 6:0 RW required delay, as a multiple of 125pSec.80 â?? 127 â?? Reserved

4.3.10 (Rx_CMD_Data_dly_1)—Offset 82Ch

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 6

Default: 1C1C1C00h

3 2 2 2 1 1 840 1 8 4 0 6 2

00011100000111000001110000000000 RSVD RSVD RSVD RSVD sdr25_hs50 sdr12_comp sdr50_mode ddr50_mode

284 332219-002

SDXC (D30:F6)

Bit Default & Field Name (ID): Description Range Access

0h 31 Reserved. RO

1Ch sdr50_mode: Rx CMD + Data Delay (SDR50 Mode). 30:24 0-79: Select the required delay, as a multiple of 125pSec. RW 80-127: Reserved

0h 23 Reserved. RO

1Ch ddr50_mode: Rx CMD + Data Delay (DDR50 Mode). 22:16 0-78: Select number of active delay elements. Each = 125pSec. RW 79-127: Reserved

0h 15 Reserved. RO

1Ch sdr25_hs50: Rx CMD + Data Delay (SDR25/HS50 Mode) 14:8 0-79: Select the required delay, as a multiple of 125pSec. RW 80-127: Reserved

0h 7 Reserved. RO

0h sdr12_comp: Rx CMD + Data Delay (SDR12/Compatibility Mode) 6:0 0-79: Select the required delay, as a multiple of 125pSec. RW 80-127: Reserved

4.3.11 (Rx_Strobe_Ctrl_Path)—Offset 830h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 6

Default: 500h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000010100000000 RSVD RSVD RSVD auto_tuning hs400_mode1 hs400_mode2

Bit Default & Field Name (ID): Description Range Access

0h 31:17 Reserved. RO

0h auto_tuning: Enable Auto Tuning for HS400 Strobe Path 0 â?? Auto Tuning Disabled 16 RW 1 â?? Auto Tuning Enabled

0h 15 Reserved. RO

332219-002 285 SDXC (D30:F6)

Bit Default & Field Name (ID): Description Range Access

5h hs400_mode1: Rx Strobe Delay DLL 1(HS400 Mode) 0 â?? 39 â?? Select number of 14:8 RW active delay elements. Each = 125pSec 0 â?? 63 - Reserved

0h 7 Reserved. RO

0h hs400_mode2: Rx Strobe Delay DLL 2(HS400 Mode) 0 â?? 39 â?? Select number of 6:0 RW active delay elements. Each = 125pSec 40 â?? 63 - Reserved

4.3.12 (Rx_CMD_Data_dly_2)—Offset 834h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 6

Default: 181Ch

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000001100000011100 RSVD RSVD RSVD path_pll clk_source cmd_data_sdr104_hs200

Bit Default & Field Name (ID): Description Range Access

0h 31:18 Reserved. RO

0h clk_source: Clock Source for Rx Path 00 â?? Rx Clock after Output Buffer 01 â?? Rx 17:16 Clock before Output Buffer 10 â?? Automatic Selection based on Working mode (HS RW 200 before buffer, all others after buffer) 11 - Reserved

0h 15:14 Reserved. RO

18h path_pll: Rx Path PLL #3 Delay value For Auto Tuning Mode 0-39 - Select the 13:8 RW required delay, as a multiple of 125pSec.40 â?? 63 â?? Reserved

0h 7 Reserved. RO

1Ch cmd_data_sdr104_hs200: Rx CMD + Data Delay (SDR104/HS200 Mode) 6:0 0-79: Select the required delay, as a multiple of 125pSec. RW 80-127: Reserved

4.3.13 (Master_Dll)—Offset 838h

Access Method

286 332219-002

SDXC (D30:F6)

Type: MEM Register Device: 30 (Size: 32 bits) Function: 6

Default: 1h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000001 less more RSVD DLL_lock fine_code coarse_code SW_reset_dll Ctrl_of_Mst_DLL_Ref_Clk Master_DLL_Software_Ctrl

Bit Default & Field Name (ID): Description Range Access

0h 31:25 Reserved. RO

0h SW_reset_dll: SW reset for Master DLL 0 â?? No SW Reset for Master DLL 1 â?? 24 RO Force Reset for Master DLL

0h DLL_lock: Master DLL Lock Indication 23 RO

0h coarse_code: Set coarse code to DLL. (only valid when Software control is Enabled) 22:8 RW

0h fine_code: Set fine code to DLL. (only valid when Software control is Enabled) 7:4 RW

0h less: Phase Detection Less Indication 3 RO/V

0h more: Phase Detector More Indication 2 RO/V

0h Master_DLL_Software_Ctrl: Master DLL Software Ctrl. 0 â?? Master DLL 1 RW Automatic Control (SW Control Disabled). 1 â?? Master DLL Software Control Enabled

1h Ctrl_of_Mst_DLL_Ref_Clk: Ctrl of Master DLL Ref Clock. 0 - Clock is Disabled. 1 - 0 RW Clock is Enabled

4.3.14 (Auto_tuning)—Offset 840h

Access Method

Type: MEM Register Device: 30 (Size: 32 bits) Function: 6

Default: 0h

332219-002 287 SDXC (D30:F6)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD Auto_tuning_val

Bit Default & Field Name (ID): Description Range Access

0h 31:5 Reserved. RO

0h Auto_tuning_val 4:0 RO

§ §

288 332219-002

I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

5 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

5.1 I2C PCI Configuration Registers Summary

Table 5-1. Summary of I2C PCI Configuration Registers

Offset Offset Register Name (ID)—Offset Default Value Start End

9D608086h / LP 9D618086h / LP 9D628086h / LP 9D638086h / LP 9D648086h / LP 0h 3h Device ID and Vendor ID Register (DEVVENDID)—Offset 0h 9D658086h / LP A1608086h / H A1618086h / H A1628086h / H A1638086h / H

4h 7h Status and Command (STATUSCOMMAND)—Offset 4h 100000h

8h Bh Revision ID and Class Code (REVCLASSCODE)—Offset 8h 0h

Cache Line Latency Header and BIST (CLLATHEADERBIST)—Offset Ch Fh 0h Ch

10h 13h Base Address Register (BAR)—Offset 10h 0h

14h 17h Base Address Register High (BAR_HIGH)—Offset 14h 0h

18h 1Bh Base Address Register 1 (BAR1)—Offset 18h 0h

1Ch 1Fh Base Address Register1 High (BAR1_HIGH)—Offset 1Ch 0h

Subsystem Vendor and Subsystem ID (SUBSYSTEMID)—Offset 2Ch 2Fh 0h 2Ch

Expansion ROM Base Address (EXPANSION_ROM_BASEADDR)— 30h 33h 0h Offset 30h

34h 37h Capabilities Pointer (CAPABILITYPTR)—Offset 34h 80h

3Ch 3Fh Interrupt Register (INTERRUPTREG)—Offset 3Ch 100h

80h 83h PowerManagement Capability ID (POWERCAPID)—Offset 80h 48030001h

84h 87h PME Control and Status (PMECTRLSTATUS)—Offset 84h 8h

PCI Device Idle Capability Record (PCIDEVIDLE_CAP_RECORD)— 90h 93h F0140009h Offset 90h

SW LTR Update MMIO Location Register 98h 9Bh 0h (D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h

Device IDLE pointer register (DEVICE_IDLE_POINTER_REG)— 9Ch 9Fh 0h Offset 9Ch

A0h A3h Device PG Config (D0I3_MAX_POW_LAT_PG_CONFIG)—Offset A0h 800h

5.1.1 Device ID and Vendor ID Register (DEVVENDID)—Offset 0h

Access Method

332219-002 289 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

Type: CFG Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 DEVICEID VENDORID

Bit Default & Field Name (ID): Description Range Access

9D60h / LP Device ID (DEVICEID): This is a 16-bit value assigned to the controller 9D61h / LP 9D62h / LP 9D63h / LP 9D64h / LP 31:16 9D65h / LP A160h / H A161h / H A162h / H A163h / H RO

8086h Vendor ID (VENDORID) 15:0 RO

5.1.2 Status and Command (STATUSCOMMAND)—Offset 4h

Access Method

Type: CFG Register Device: 21 (Size: 32 bits) Function: 0

Default: 100000h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000100000000000000000000 RTA BME MSE RMA RSVD RSVD RSVD RSVD RSVD RSVD CAPLIST INTR_STATUS SERR_ENABLE INTR_DISABLE

290 332219-002

I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

Bit Default & Field Name (ID): Description Range Access

0h 31:30 Reserved. RO

0h RMA: If the completion status received from is UR, this bit is set. S/W writes a ‘1’ to 29 RW/1C this bit to clear it.

0h Received Target Abort (RTA): If the completion status received is CA, this bit is 28 RW/1C set. S/W writes a ‘1’ to this bit to clear it.

0h 27:21 Reserved. RO

1h Capabilities List (CAPLIST): Indicates that the controller contains a capabilities 20 RO pointer list. The first item is pointed to by looking at configuration offset 34h.

Interrrupt Status (INTR_STATUS): This bit reflects state of interrupt in the 0h device. Only when the Interrupt Disable bit in the command register is a 0 and this 19 Interrupt Status bit is a 1, will the device’s/function’s interrupt message be sent. RO Setting the Interrupt Disable bit to a 1 has no effect on the state of this bit. This bit reflects Legacy interrupt status.

0h 18:11 Reserved. RO

0h Interrupt Disable (INTR_DISABLE): Setting this bit disables INTx assertion. The 10 RW interrupt disabled is legacy INTx# interrupt.

0h 9 Reserved. RO

0h SERR# Enable (SERR_ENABLE): Not implemented 8 RW

0h 7:3 Reserved. RO

0h Bus Master Enable (BME) 2 RW

0h Memory Space Enable (MSE): 0 = Disables memory mapped Configuration space. 1 RW 1 = Enables memory mapped Configuration space.

0h 0 Reserved. RO

5.1.3 Revision ID and Class Code (REVCLASSCODE)—Offset 8h

Access Method

Type: CFG Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RID CLASS_CODES

332219-002 291 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

Bit Default & Field Name (ID): Description Range Access

0h Class Codes (CLASS_CODES): The register is read-only and is used to identify the 31:8 RO generic function of the device.

0h Revision ID (RID): Indicates stepping of the host controller. Refer to Device and 7:0 RO Revision ID table in Vol1 of the EDS for specific value.

5.1.4 Cache Line Latency Header and BIST (CLLATHEADERBIST)—Offset Ch

Access Method

Type: CFG Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD LATTIMER MULFNDEV HEADERTYPE CACHELINE_SIZE

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h Multi Function Device (MULFNDEV): 0 = Single Function Device 23 RO 1 = Multi Function device

0h HEADERTYPE: Implements Type 0 Configuration header. 22:16 RO

0h Latency Timer (LATTIMER) 15:8 RO

0h CACHELINE_SIZE: Cache Line Size 7:0 RW

5.1.5 Base Address Register (BAR)—Offset 10h

Bits [31:12] indicate the Base Address register. Power-up software can determine how much address space the Interface Module requires by writing a value of all ones to the register and then reading the value back. The register returns zeros in all don't-care address bits, effectively specifying the address space required.

Access Method

Type: CFG Register Device: 21 (Size: 32 bits) Function: 0

292 332219-002

I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 TYPE BASEADDR PREFETCHABLE SIZEINDICATOR MESSAGE_SPACE

Bit Default & Field Name (ID): Description Range Access

0h Base Address (BASEADDR): Provides system memory base address for the 31:12 RW controller.

0h Size Indicator (SIZEINDICATOR) 11:4 RO

0h Prefetchable (PREFETCHABLE): Indicates that this BAR is not prefetchable. 3 RO

0h Type (TYPE): 00 indicates BAR lies in 32bit address range 2:1 RO 10 Indicates BAR lies in 64 bit address range

0h Memory Space Indicator (MESSAGE_SPACE): ‘0’ Indicates this BAR is present in 0 RO the memory space.

5.1.6 Base Address Register High (BAR_HIGH)—Offset 14h

Access Method

Type: CFG Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 BASEADDR_HIGH

Bit Default & Field Name (ID): Description Range Access

0h Base Address High (BASEADDR_HIGH) 31:0 RW

332219-002 293 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

5.1.7 Base Address Register 1 (BAR1)—Offset 18h

Access Method

Type: CFG Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 TYPE1 BASEADDR1 PREFETCHABLE1 SIZEINDICATOR1 MESSAGE_SPACE1

Bit Default & Field Name (ID): Description Range Access

0h Base Address Register1 (BASEADDR1): This field is present if BAR1 is enabled. 31:12 RW

0h Size Indicator (SIZEINDICATOR1): Always will be zero as minimum size is 4K. 11:4 RO

0h Prefetchable (PREFETCHABLE1): Indicates that this BAR is not prefetchable. 3 RO

0h Type (TYPE1): 00 indicates BAR lies in 32bit address range 2:1 RO 10 Indicates BAR lies in 64 bit address range.

0h MESSAGE_SPACE1 0 RO

5.1.8 Base Address Register1 High (BAR1_HIGH)—Offset 1Ch

Access Method

Type: CFG Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 BASEADDR1_HIGH

294 332219-002

I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

Bit Default & Field Name (ID): Description Range Access

0h Base Address High 1 (BASEADDR1_HIGH) 31:0 RW

5.1.9 Subsystem Vendor and Subsystem ID (SUBSYSTEMID)— Offset 2Ch

Access Method

Type: CFG Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 SUBSYSTEMID SUBSYSTEMVENDORID

Bit Default & Field Name (ID): Description Range Access

0h Subsystem ID (SUBSYSTEMID): The register, in combination with the Subsystem 31:16 Vendor ID register make it possible for the operating environment to distinguish one RW/O subsystem from the other. This register is a Read Write Once type register.

0h Subsystem Vendor ID (SUBSYSTEMVENDORID): The register, in combination 15:0 with the Subsystem ID register, enables the operating environment to distinguish one RW/O subsystem from the other. This register is a Read Write Once register.

5.1.10 Expansion ROM Base Address (EXPANSION_ROM_BASEADDR)—Offset 30h

Access Method

Type: CFG Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

332219-002 295 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 EXPANSION_ROM_BASE

Bit Default & Field Name (ID): Description Range Access

0h Expansion ROM Base (EXPANSION_ROM_BASE): Value of 0 indicates no support 31:0 RO for Expansion ROM.

5.1.11 Capabilities Pointer (CAPABILITYPTR)—Offset 34h

Access Method

Type: CFG Register Device: 21 (Size: 32 bits) Function: 0

Default: 80h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000010000000 RSVD CAPPTR_POWER

Bit Default & Field Name (ID): Description Range Access

0h 31:8 Reserved. RO

80h Capabilities Pointer (CAPPTR_POWER): Indicates what the next capability is. 7:0 RO This capability points to the PM Capability (0x80) structure.

5.1.12 Interrupt Register (INTERRUPTREG)—Offset 3Ch

Access Method

Type: CFG Register Device: 21 (Size: 32 bits) Function: 0

Default: 100h

296 332219-002

I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000100000000 RSVD INTPIN INTLINE MAX_LAT MIN_GNT

Bit Default & Field Name (ID): Description Range Access

0h Max Latency (MAX_LAT): Value of 0 indicates device has no major requirements 31:24 RO for the settings of latency timers

0h Min Latency (MIN_GNT): Value of 0 indicates device has no major requirements 23:16 RO for the settings of latency timers

0h 15:12 Reserved. RO

1h Interrupt Pin (INTPIN) 11:8 RO

0h Interrupt Line (INTLINE): Used to communicate to software the interrupt line that 7:0 RW the interrupt pin is connected to.

5.1.13 PowerManagement Capability ID (POWERCAPID)—Offset 80h

Access Method

Type: CFG Register Device: 21 (Size: 32 bits) Function: 0

Default: 48030001h

3 2 2 2 1 1 840 1 8 4 0 6 2

01001000000000110000000000000001 RSVD NXTCAP VERSION POWER_CAP PMESUPPORT

Bit Default & Field Name (ID): Description Range Access

9h PME Support (PMESUPPORT) 31:27 RO

0h 26:19 Reserved. RO

332219-002 297 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

Bit Default & Field Name (ID): Description Range Access

3h Version (VERSION): Indicates support for Revision 1.2 of the PCI Power 18:16 RO Management Specification

0h Next Capability (NXTCAP): Points to the next capability structure. This points to 15:8 RO NULL.

1h Power Management Capability (POWER_CAP): Indicates power management 7:0 RO capability.

5.1.14 PME Control and Status (PMECTRLSTATUS)—Offset 84h

Access Method

Type: CFG Register Device: 21 (Size: 32 bits) Function: 0

Default: 8h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000001000 RSVD RSVD POWERSTATE NO_SOFT_RESET

Bit Default & Field Name (ID): Description Range Access

0h 31:4 Reserved. RO

1h No Soft Reset (NO_SOFT_RESET): When set, this bit indicates that devices 3 transitioning from D3hot to D0 because of PowerState commands do not perform an RO internal reset. Configuration Context is preserved.

0h 2 Reserved. RO

Power State (POWERSTATE): This field is used both to determine the current power state and to set a new power state. The values are: 00 = D0 state 0h 1:0 11 = D3HOT state RW Others = Reserved Notes: If software attempts to write a value of 01b or 10b in to this field,the data is discarded and no state change occurs. When in the D3HOT states, interrupts are blocked.

5.1.15 PCI Device Idle Capability Record (PCIDEVIDLE_CAP_RECORD)—Offset 90h

Access Method

Type: CFG Register Device: 21 (Size: 32 bits) Function: 0

298 332219-002

I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

Default: F0140009h

3 2 2 2 1 1 840 1 8 4 0 6 2

11110000000101000000000000001001 CAPID REVID NEXT_CAP VEND_CAP CAP_LENGTH

Bit Default & Field Name (ID): Description Range Access

Fh Vendor Capability (VEND_CAP): Indicates this is Vendor Specific capability. 31:28 RO

0h Revision ID (REVID): Revision ID of capability structure 27:24 RO

14h Length (CAP_LENGTH): Indicates the number of bytes in the capability structure. 23:16 RO

0h Next Capability (NEXT_CAP): Points to the next capability structure. This points to 15:8 RO NULL.

9h Capability ID (CAPID) 7:0 RO

5.1.16 SW LTR Update MMIO Location Register (D0I3_CONTROL_SW_LTR_MMIO_REG)—Offset 98h

Access Method

Type: CFG Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 SW_LAT_VALID SW_LAT_BAR_NUM SW_LAT_DWORD_OFFSET

332219-002 299 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

Bit Default & Field Name (ID): Description Range Access

Location Pointer Offset (SW_LAT_DWORD_OFFSET): This register contains the 0h 31:4 location pointer to the SW LTR register in MMIO space, as an offset from the specified RO BAR. The value of this register is a don’t care, if the Valid bit is not set.

0h BAR Number (SW_LAT_BAR_NUM): Indicates that the SW LTR update MMIO 3:1 RO location is always at BAR0.

0h Valid (SW_LAT_VALID) 0 RO

5.1.17 Device IDLE pointer register (DEVICE_IDLE_POINTER_REG)—Offset 9Ch

Access Method

Type: CFG Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 VALID BAR_NUM DWORD_OFFSET

Bit Default & Field Name (ID): Description Range Access

0h DevIdle Pointer (DWORD_OFFSET): This register contains the location pointer to 31:4 the DevIdle register in MMIO space, as an offset from the specified BAR. The value of RO this register is a don’t care, if the Valid bit is not set.

0h BAR_NUM: Indicates that the DevIdle update MMIO location is always at BAR0 3:1 RO

0h Valid (VALID): 0= not valid 0 RO 1= valid

5.1.18 Device PG Config (D0I3_MAX_POW_LAT_PG_CONFIG)— Offset A0h

Access Method

Type: CFG Register Device: 21 (Size: 32 bits) Function: 0

Default: 800h

300 332219-002

I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000100000000000 PGE RSVD RSVD PMCRE I3_ENABLE POW_LAT_SCALE POW_LAT_VALUE

Bit Default & Field Name (ID): Description Range Access

0h 31:19 Reserved. RO

0h Power Gate Enable (PGE): If clear, then the controller will never request a PG. If 18 set, then the controller may request PG when proper conditions are met. Note: This RW Bit must be set by BIOs for PG to function

0h I3 Enable (I3_ENABLE): If ‘1’, then the function will power gate when idle and the 17 RW DevIdle register (DevIdleC[2] = ‘1’) is set.

0h PMC Request Enable (PMCRE): If this bit is set to ‘1’, the function will power gate 16 RW when idle.

0h 15:13 Reserved. RO

2h Power On Latercy Scale (POW_LAT_SCALE): Support for codes 010 (1us) or 011 12:10 (32us) for Exit Latency Scale (1us - 32ms total span) only. This value is written by RW/O BIOS to communicate to the Driver.

0h Power On Latency Value (POW_LAT_VALUE): This value is written by BIOS to 9:0 RW/O communicate to the Driver.

5.2 I2C Memory Mapped Registers Summary

Table 5-2. Summary of I2C Memory Mapped Registers

Offset Offset Default Register Name (ID)—Offset Start End Value

0h 3h I2C Control (IC_CON)—Offset 0h 77h

4h 7h I2C Target Address (IC_TAR)—Offset 4h 1055h

Ch Fh I2C High Speed Master Mode Code Address (IC_HS_MADDR)—Offset Ch 1h

10h 13h I2C Rx/Tx Data Buffer and Command (IC_DATA_CMD)—Offset 10h 0h

Standard Speed I2C Clock SCL High Count (IC_SS_SCL_HCNT)—Offset 14h 17h 1F4h 14h

Standard Speed I2C Clock SCL Low Count (IC_SS_SCL_LCNT)—Offset 18h 1Bh 24Ch 18h

1Ch 1Fh Fast Speed I2C Clock SCL High Count (IC_FS_SCL_HCNT)—Offset 1Ch 4Bh

20h 23h Fast Speed I2C Clock SCL Low Count (IC_FS_SCL_LCNT)—Offset 20h A3h

2Ch 2Fh I2C Interrupt Status (IC_INTR_STAT)—Offset 2Ch 0h

30h 33h I2C Interrupt Mask (IC_INTR_MASK)—Offset 30h 8FFh

34h 37h I2C Raw Interrupt Status (IC_RAW_INTR_STAT)—Offset 34h 0h

38h 3Bh I2C Receive FIFO Threshold (IC_RX_TL)—Offset 38h 0h

3Ch 3Fh I2C Transmit FIFO Threshold (IC_TX_TL)—Offset 3Ch 0h

332219-002 301 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

Table 5-2. Summary of I2C Memory Mapped Registers (Continued)

Offset Offset Default Register Name (ID)—Offset Start End Value

40h 43h Clear Combined and Individual Interrupt (IC_CLR_INTR)—Offset 40h 0h

44h 47h Clear RX_UNDER Interrupt (IC_CLR_RX_UNDER)—Offset 44h 0h

48h 4Bh Clear RX_OVER Interrupt (IC_CLR_RX_OVER)—Offset 48h 0h

4Ch 4Fh Clear TX_OVER Interrupt (IC_CLR_TX_OVER)—Offset 4Ch 0h

50h 53h Clear RD_REQ Interrupt (IC_CLR_RD_REQ)—Offset 50h 0h

54h 57h Clear TX_ABRT Interrupt (IC_CLR_TX_ABRT)—Offset 54h 0h

58h 5Bh Clear RX_DONE Interrupt (IC_CLR_RX_DONE)—Offset 58h 0h

5Ch 5Fh Clear ACTIVITY Interrupt (IC_CLR_ACTIVITY)—Offset 5Ch 0h

60h 63h Clear STOP_DET Interrupt (IC_CLR_STOP_DET)—Offset 60h 0h

64h 67h Clear START_DET Interrupt (IC_CLR_START_DET)—Offset 64h 0h

68h 6Bh Clear GEN_CALL Interrupt (IC_CLR_GEN_CALL)—Offset 68h 0h

6Ch 6Fh I2C Enable (IC_ENABLE)—Offset 6Ch 0h

70h 73h I2C Status (IC_STATUS)—Offset 70h 6h

74h 77h I2C Transmit FIFO Level (IC_TXFLR)—Offset 74h 0h

78h 7Bh I2C Receive FIFO Level (IC_RXFLR)—Offset 78h 0h

7Ch 7Fh I2C SDA Hold Time Length (IC_SDA_HOLD)—Offset 7Ch 1h

80h 83h I2C Transmit Abort Source (IC_TX_ABRT_SOURCE)—Offset 80h 0h

88h 8Bh DMA Control (IC_DMA_CR)—Offset 88h 0h

8Ch 8Fh DMA Transmit Data Level (IC_DMA_TDLR)—Offset 8Ch 0h

90h 93h I2C Receive Data Level (IC_DMA_RDLR)—Offset 90h 0h

98h 9Bh I2C ACK General Call (IC_ACK_GENERAL_CALL)—Offset 98h 1h

9Ch 9Fh I2C Enable Status (IC_ENABLE_STATUS)—Offset 9Ch 0h

A0h A3h I2C SS and FS Spike Suppression Limit (IC_FS_SPKLEN)—Offset A0h 7h

A8h ABh Clear RESTART_DET Interrupt (IC_CLR_RESTRART_DET)—Offset A8h 0h

5.2.1 I2C Control (IC_CON)—Offset 0h

This register can be written only when the I2C is disabled, which corresponds to the IC_ENABLE register being set to 0. Writes at other times have no effect.

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 77h

302 332219-002

I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000001110111 RSVD RSVD RSVD SPEED MASTER_MODE IC_RESTART_EN TX_EMPTY_CTRL IC_SLAVE_DISABLE IC_10BITADDR_MASTER_rd_only

Bit Default & Field Name (ID): Description Range Access

0h 31:9 Reserved. RO

0h TX_EMPTY_CTRL (TX_EMPTY_CTRL): This bit controls the generation of the 8 RW TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register.

0h 7 Reserved. RO

IC_SLAVE_DISABLE (IC_SLAVE_DISABLE): This bit controls whether I2C has its slave disabled. If this bit is set (slave is disabled), the function only works as a

1h master and does not perform any action that requires a slave. 6 0:Reserved RW 1: slave is disabled NOTE: For Master Device Configuration Software must ensure that this bit is set to 1, and bit 0 must also be set to 1. Else this will result in configuration error

IC_RESTART_EN (IC_RESTART_EN): Determines whether RESTART conditions may be sent when I2C is acting as a master. 0: Restart disable 1: Restart enable When the RESTART is disabled, the IP is incapable of performing the following functions:

1h • Sending a START BYTE 5 • Performing any high-speed mode operation RO • Performing direction changes in combined format mode • Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register.

IC_10BITADDR_MASTER (IC_10BITADDR_MASTER_rd_only): Identifies if I2C 1h 4 operates in 7 or 10 bit addressing. RO 0: 7-bit addressing 1: 10-bit addressing

0h 3 Reserved. RO

SPEED (SPEED): These bits control at which speed the I2C operates. 3h 01: standard mode (0 to 100 kbit/s) 2:1 RW 10: fast mode (400 kbit/s) Others: reserved

MASTER_MODE (MASTER_MODE): This bit controls whether I2C master is enabled. 1h 0 = Reserved 0 RW 1 = Master Enabled Note: For Master Device Configuration Software must ensure that this bit is set to 1, and bit 6 must also be set to 1. Else this will result in configuration error.

332219-002 303 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

5.2.2 I2C Target Address (IC_TAR)—Offset 4h

The register should only be updated when the I2C is not enabled (IC_ENABLE=0) or No Master mode operations are active (IC_STATUS[5] = 0 and IC_CON[0] = 1 and IC_STATUS[2] = 1).

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 1055h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000001000001010101 RSVD IC_TAR SPECIAL GC_OR_START IC_10BITADDR_MASTER

Bit Default & Field Name (ID): Description Range Access

0h 31:13 Reserved. RO

IC_10BITADDR_MASTER (IC_10BITADDR_MASTER): This bit controls whether 1h the I2C starts its transfers in 7-or 10-bit addressing mode when acting as a master. 12 RW 0: 7 bit addressing 1: 10-bit addressing

SPECIAL (SPECIAL): This bit indicates whether software performs a General Call or 0h START BYTE command. 11 RW 0: ignore bit 10 GC_OR_START and use IC_TAR normally. 1: perform special I2C command as specified in GC_OR_START bit

GC_OR_START (GC_OR_START): If bit 11 (SPECIAL) is set to 1, then this bit indicates whether a General Call or START byte command is to be performed by the I2C. 0h 0: General Call Address – after issuing a General Call, only writes may be performed. 10 RW Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The I2C remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. 1: START BYTE

IC_TAR (IC_TAR): This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the 55h CPU needs to write only once into these bits. 9:0 Note: If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are RW shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave.

5.2.3 I2C High Speed Master Mode Code Address (IC_HS_MADDR)—Offset Ch

I2C High Speed Master Mode Code Address Register. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE register being set to 0. Writes at other times have no effect

304 332219-002

I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 1h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000001 RSVD IC_HS_MAR

Bit Default & Field Name (ID): Description Range Access

0h 31:3 Reserved. RO

IC_HS_MAR (IC_HS_MAR): This bit field holds the value of the I2C HS mode master code. HS-mode master codes are reserved 8-bit codes (00001xxx) that are 1h not used for slave addressing or other purposes. Each master has its unique master 2:0 code; up to eight highspeed mode masters can be present on the same I2C bus RW system. Valid values are from 0 to 7. This register goes away and becomes read-only returning 0s if the IC_MAX_SPEED_MODE configuration parameter is set to either Standard (1) or Fast (2).

5.2.4 I2C Rx/Tx Data Buffer and Command (IC_DATA_CMD)— Offset 10h

This register is used by the processor to write to when filling the Tx FIFO and to read from when retrieving bytes form Tx FIFO. In order for the I2C controller to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise, the controller will stop acknowledging.

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 DAT CMD STOP RSVD RESTART

332219-002 305 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

Bit Default & Field Name (ID): Description Range Access

0h 31:11 Reserved. RO

RESTART (RESTART): This bit controls whether a RESTART is issued before the byte is sent or received. 0h 1: a RESTART is issued before the data is sent/received (according to the value of 10 CMD), regardless of whether or not the transfer direction is changing from the RW previous command. 0: a RESTART is issued only if the transfer direction is changing from the previous command

STOP (STOP): This bit controls whether a STOP is issued after the byte is sent or received. 1: STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by 0h issuing a START and arbitrating for the bus. 9 RW 0: STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO.

CMD (CMD): This bit controls whether a read or a write is performed. 1 = Read. 0 = Write 0h When programming this bit, note the following: attempting to perform a read 8 operation after a General Call command has been sent results in a TX_ABRT interrupt RW (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a “1” is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs.

DAT (DAT): This register contains the data to be transmitted or received on the I2C 0h bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are 7:0 RW ignored by the I2C. However, when you read this register, these bits return the value of data received on the I2C interface.

5.2.5 Standard Speed I2C Clock SCL High Count (IC_SS_SCL_HCNT)—Offset 14h

This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE register being set to 0. Writes at other times have no effect.

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 1F4h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000111110100 RSVD IC_SS_SCL_HCNT

306 332219-002

I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

Bit Default & Field Name (ID): Description Range Access

0h 31:16 Reserved. RO

1F4h IC_SS_SCL_HCNT (IC_SS_SCL_HCNT): This register sets the SCL clock high- 15:0 period count for standard speed. The value of the registers should be within the RW range {6, 65525}

5.2.6 Standard Speed I2C Clock SCL Low Count (IC_SS_SCL_LCNT)—Offset 18h

This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE register being set to 0. Writes at other times have no effect.

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 24Ch

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000001001001100 RSVD IC_SS_SCL_LCNT

Bit Default & Field Name (ID): Description Range Access

0h 31:16 Reserved. RO

24Ch IC_SS_SCL_LCNT (IC_SS_SCL_LCNT): Standard Speed I2C Clock SCL Low Count 15:0 RW Register. The register value should always be >= 8

5.2.7 Fast Speed I2C Clock SCL High Count (IC_FS_SCL_HCNT)— Offset 1Ch

This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE register being set to 0. Writes at other times have no effect.

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 4Bh

332219-002 307 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000001001011 RSVD IC_FS_SCL_HCNT

Bit Default & Field Name (ID): Description Range Access

0h 31:16 Reserved. RO

4Bh IC_FS_SCL_HCNT (IC_FS_SCL_HCNT): This register sets the SCL clock high- 15:0 period count for fast speed. It is used in high-speed mode to send the Master Code RW and START BYTE or General CALL. The minimum value of this field is 6.

5.2.8 Fast Speed I2C Clock SCL Low Count (IC_FS_SCL_LCNT)— Offset 20h

This register must be set before any I2C bus transaction can take place to ensure proper I/O timing.

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: A3h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000010100011 RSVD IC_FS_SCL_LCNT

Bit Default & Field Name (ID): Description Range Access

0h 31:16 Reserved. RO

IC_FS_SCL_LCNT (IC_FS_SCL_LCNT): This register sets the SCL clock low period A3h count for fast speed. It is used in high-speed mode to send the Master Code and 15:0 RW START BYTE or General CALL. The register should be programmed with a minimum value of 8.

308 332219-002

I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

5.2.9 I2C Interrupt Status (IC_INTR_STAT)—Offset 2Ch

Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD R_RX_FULL R_TX_ABRT R_TX_OVER R_ACTIVITY R_RX_OVER R_TX_EMPTY R_GEN_CALL R_STOP_DET R_RX_UNDER R_START_DET R_MST_ON_HOLD

Bit Default & Field Name (ID): Description Range Access

0h 31:14 Reserved. RO

0h R_MST_ON_HOLD (R_MST_ON_HOLD): Indicates whether a master is holding 13 the bus and the TX FIFO is empty. Enabled only when I2C_DYNAMIC_TAR_UPDATE = RO 1 and IC_EMPTYFIFO_HOLD_MASTER_EN = 1

0h 12 Reserved. RO

0h R_GEN_CALL (R_GEN_CALL): Set only when a General Call address is received 11 and it is acknowledged. It stays set until it is cleared either by disabling the controller RO or when the processor reads bit 0 of the IC_CLR_GEN_CALL register

0h R_START_DET (R_START_DET): Indicates whether a START or RESTART condition 10 RO has occurred on the I2C interface

0h R_STOP_DET (R_STOP_DET): Indicates whether a STOP condition has occurred on 9 RO the I2C interface.

R_ACTIVITY (R_ACTIVITY): This bit captures the controller activity and stays set until it is cleared. There are four ways to clear it: 1. Disabling the controller, 2. 0h 8 Reading the IC_CLR_ACTIVITY register, 3. Reading the IC_CLR_INTR register, 4. RO System reset Note: Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the controller is idle, this bit remains set until cleared, indicating that there was activity on the bus.

0h Reserved 7 RO

R_TX_ABRT (R_TX_ABRT): This bit indicates if the controler, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. 0h When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why 6 the transmit abort takes places. NOTE: The controller flushes/resets/empties the TX RO FIFO whenever this bit is set. The TX FIFO remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the TX FIFO is then ready to accept more data bytes.

0h Reserved 5 RO

332219-002 309 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

Bit Default & Field Name (ID): Description Range Access

R_TX_EMPTY (R_TX_EMPTY): The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or 0h below the threshold value set in the IC_TX_TL register and the transmission of the 4 address/data from the internal shift register for the most recently popped command RO is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in reset. Then the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0.

0h R_TX_OVER (R_TX_OVER): Set during transmit if the transmit buffer is filled to 3 IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by RO writing to the IC_DATA_CMD register.

R_RX_FULL (R_RX_FULL): Set when the receive buffer reaches or goes above the 0h RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware 2 when buffer level goes below the threshold. RO NOTE: If IC_RX_FULL_HLD_BUS_EN=1, then the RX_OVER interrupt is never set to 1, because the criteria to set this interrupt are never met.

R_RX_OVER (R_RX_OVER): Set if the receive buffer is completely filled to 0h IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C 1 RO device. The controller acknowledges this, but any data bytes received after the FIFO is full are lost.

0h R_RX_UNDER (R_RX_UNDER): Set if the processor attempts to read the receive 0 RO buffer when it is empty by reading from the IC_DATA_CMD register.

5.2.10 I2C Interrupt Mask (IC_INTR_MASK)—Offset 30h

These bits mask their corresponding interrupt status bits in the IC_INTR_STAT register

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 8FFh

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000100011111111 RSVD RSVD M_RD_REQ M_RX_FULL M_TX_ABRT M_TX_OVER M_ACTIVITY M_RX_OVER M_RX_DONE M_TX_EMPTY M_GEN_CALL M_STOP_DET M_RX_UNDER M_START_DET M_MST_ON_HOLD

310 332219-002

I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

Bit Default & Field Name (ID): Description Range Access

0h 31:14 Reserved. RO

0h M_MST_ON_HOLD (M_MST_ON_HOLD) 13 RW

0h 12 Reserved. RO

1h M_GEN_CALL (M_GEN_CALL) 11 RW

0h M_START_DET (M_START_DET) 10 RW

0h M_STOP_DET (M_STOP_DET) 9 RW

0h M_ACTIVITY (M_ACTIVITY) 8 RW

1h M_RX_DONE (M_RX_DONE) 7 RW

1h M_TX_ABRT (M_TX_ABRT) 6 RW

1h M_RD_REQ (M_RD_REQ) 5 RW

1h M_TX_EMPTY (M_TX_EMPTY) 4 RW

1h M_TX_OVER (M_TX_OVER) 3 RW

1h M_RX_FULL (M_RX_FULL) 2 RW

1h M_RX_OVER (M_RX_OVER) 1 RW

1h M_RX_UNDER (M_RX_UNDER) 0 RW

5.2.11 I2C Raw Interrupt Status (IC_RAW_INTR_STAT)—Offset 34h

Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the controller

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

332219-002 311 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD RD_REQ RX_FULL TX_ABRT TX_OVER ACTIVITY RX_OVER RX_DONE TX_EMPTY GEN_CALL STOP_DET RX_UNDER START_DET MST_ON_HOLD

Bit Default & Field Name (ID): Description Range Access

0h 31:14 Reserved. RO

0h MST_ON_HOLD (MST_ON_HOLD): Same as in reg_IC_INTR_STAT 13 RO

0h 12 Reserved. RO

0h GEN_CALL (GEN_CALL): Same as in reg_IC_INTR_STAT 11 RO

0h START_DET (START_DET): Same as in reg_IC_INTR_STAT 10 RO

0h STOP_DET (STOP_DET): Same as in reg_IC_INTR_STAT 9 RO

0h ACTIVITY (ACTIVITY): Same as in reg_IC_INTR_STAT 8 RO

0h RX_DONE (RX_DONE): Same as in reg_IC_INTR_STAT 7 RO

0h TX_ABRT (TX_ABRT): Same as in reg_IC_INTR_STAT 6 RO

0h RD_REQ (RD_REQ): Same as in reg_IC_INTR_STAT 5 RO

0h TX_EMPTY (TX_EMPTY): Same as in reg_IC_INTR_STAT 4 RO

0h TX_OVER (TX_OVER): Same as in reg_IC_INTR_STAT 3 RO

0h RX_FULL (RX_FULL): Same as in reg_IC_INTR_STAT 2 RO

0h RX_OVER (RX_OVER): Same as in reg_IC_INTR_STAT 1 RO

0h RX_UNDER (RX_UNDER): Same as in reg_IC_INTR_STAT 0 RO

5.2.12 I2C Receive FIFO Threshold (IC_RX_TL)—Offset 38h

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

312 332219-002

I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RX_TL

Bit Default & Field Name (ID): Description Range Access

0h 31:8 Reserved. RO

RX_TL (RX_TL): Receive FIFO Threshold Level. Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-0x3F. (Values > 0x3F are set to depth of the buffer). 0h A value of 0 sets the threshold for 1 entry, and a value of 63 sets the threshold for 64 7:0 RW entries. WARNING: When operating with DMA, the Watermark for I2C RX fifo must be programmed to be equal to M-Size (burst size) of the DMA; Any other programming value will put controller at risk of a deadlock.

5.2.13 I2C Transmit FIFO Threshold (IC_TX_TL)—Offset 3Ch

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD TX_TL

Bit Default & Field Name (ID): Description Range Access

0h 31:8 Reserved. RO

TX_TL (TX_TL): Controls the level of entries (or below) that trigger the TX_EMPTY 0h interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-0x3F, (Values > 7:0 RW 0x3F are set to depth of the buffer). A value of 0 sets the threshold for 1 entry, and a value of 63 sets the threshold for 64 entries.

5.2.14 Clear Combined and Individual Interrupt (IC_CLR_INTR)— Offset 40h

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

332219-002 313 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD CLR_INTR

Bit Default & Field Name (ID): Description Range Access

0h 31:1 Reserved. RO

CLR_INTR (CLR_INTR): Read this register to clear the combined interrupt, all 0h 0 individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear RO hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.

5.2.15 Clear RX_UNDER Interrupt (IC_CLR_RX_UNDER)—Offset 44h

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD CLR_RX_UNDER

Bit Default & Field Name (ID): Description Range Access

0h 31:1 Reserved. RO

0h CLR_RX_UNDER (CLR_RX_UNDER): Read this register to clear the RX_UNDER 0 RO interrupt (bit 0) of the IC_RAW_INTR_STAT register.

5.2.16 Clear RX_OVER Interrupt (IC_CLR_RX_OVER)—Offset 48h

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

314 332219-002

I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD CLR_RX_OVER

Bit Default & Field Name (ID): Description Range Access

0h 31:1 Reserved. RO

0h CLR_RX_OVER (CLR_RX_OVER): Read this register to clear the RX_OVER 0 RO interrupt (bit 1) of the IC_RAW_INTR_STAT register.

5.2.17 Clear TX_OVER Interrupt (IC_CLR_TX_OVER)—Offset 4Ch

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD CLR_TX_OVER

Bit Default & Field Name (ID): Description Range Access

0h 31:1 Reserved. RO

0h CLR_TX_OVER (CLR_TX_OVER): Read this register to clear the TX_OVER interrupt 0 RO (bit 3) of the IC_RAW_INTR_STAT register.

5.2.18 Clear RD_REQ Interrupt (IC_CLR_RD_REQ)—Offset 50h

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

332219-002 315 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD CLR_RD_REQ

Bit Default & Field Name (ID): Description Range Access

0h 31:1 Reserved. RO

0h CLR_RD_REQ (CLR_RD_REQ): Read this register to clear the RD_REQ interrupt 0 RO (bit 5) of the IC_RAW_INTR_STAT register.

5.2.19 Clear TX_ABRT Interrupt (IC_CLR_TX_ABRT)—Offset 54h

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD CLR_TX_ABRT

Bit Default & Field Name (ID): Description Range Access

0h 31:1 Reserved. RO

CLR_TX_ABRT (CLR_TX_ABRT): Read this register to clear the TX_ABRT interrupt 0h (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. 0 This also releases the TX FIFO from the flushed/reset state, allowing more writes to RO the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE

5.2.20 Clear RX_DONE Interrupt (IC_CLR_RX_DONE)—Offset 58h

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

316 332219-002

I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD CLR_RX_DONE

Bit Default & Field Name (ID): Description Range Access

0h 31:1 Reserved. RO

0h CLR_RX_DONE (CLR_RX_DONE): Read this register to clear the RX_DONE 0 RO interrupt (bit 7) of the IC_RAW_INTR_STAT register.

5.2.21 Clear ACTIVITY Interrupt (IC_CLR_ACTIVITY)—Offset 5Ch

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD CLR_ACTIVITY

Bit Default & Field Name (ID): Description Range Access

0h 31:1 Reserved. RO

CLR_ACTIVITY (CLR_ACTIVITY): Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, 0h 0 the ACTIVITY interrupt bit continues to be set. It is automatically cleared by RO hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register.

5.2.22 Clear STOP_DET Interrupt (IC_CLR_STOP_DET)—Offset 60h

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

332219-002 317 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD CLR_STOP_DET

Bit Default & Field Name (ID): Description Range Access

0h 31:1 Reserved. RO

0h CLR_STOP_DET (CLR_STOP_DET): Read this register to clear the STOP_DET 0 RO interrupt (bit 9) of the IC_RAW_INTR_STAT register.

5.2.23 Clear START_DET Interrupt (IC_CLR_START_DET)—Offset 64h

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD CLR_START_DET

Bit Default & Field Name (ID): Description Range Access

0h 31:1 Reserved. RO

0h CLR_START_DET (CLR_START_DET): Read this register to clear the START_DET 0 RO interrupt (bit 10) of the IC_RAW_INTR_STAT register.

5.2.24 Clear GEN_CALL Interrupt (IC_CLR_GEN_CALL)—Offset 68h

Access Method

318 332219-002

I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD CLR_GEN_CALL

Bit Default & Field Name (ID): Description Range Access

0h 31:1 Reserved. RO

0h CLR_GEN_CALL (CLR_GEN_CALL): Read this register to clear the GEN_CALL 0 RO interrupt (bit 11) of IC_RAW_INTR_STAT register.

5.2.25 I2C Enable (IC_ENABLE)—Offset 6Ch

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD ABORT ENABLE

332219-002 319 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h ABORT (ABORT): Sofware can abort I2C transfer by setting this bit. Hw will clear 1 this ABORT bit once the STOP has been detected

ENABLE (ENABLE): Controls whether the controller is enabled. 0: Disables I2C controller(TX and RX FIFOs are held in an erased state) 1: Enables I2C controller. Software can disable the controller while it is active. However, it is important that care be taken to ensure that the controller is disabled properly. When the controller is 0h disabled, the following occurs: 0 -The TX FIFO and RX FIFO get flushed. RW -Status bits in the IC_INTR_STAT register are still active until the controller goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the controller stops the current transfer at the end of the current byte and does not acknowledge the transfer.

5.2.26 I2C Status (IC_STATUS)—Offset 70h

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 6h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000110 TFE RFF TFNF RFNE RSVD ACTIVITY MST_ACTIVITY

Bit Default & Field Name (ID): Description Range Access

0h 31:6 Reserved. RO

Master Activity Status (MST_ACTIVITY): When the Master state machine is not 0h 5 in the IDLE state, this bit is set. RO 0: Master is in IDLE state 1: Master is not in IDLE

Receive FIFO Completely Full (RFF): When the receive FIFO is completely full, 0h this bit is set. When the receive FIFO contains one or more empty location, this bit is 4 cleared. RO 0: Receive FIFO is not full 1: Receive FIFO is full

Receive FIFO Not Empty (RFNE): This bit is set when the receive FIFO contains 0h one or more entries; it is cleared when the receive FIFO is empty. 3 RO 0: Receive FIFO is empty 1: Receive FIFO is not empty

320 332219-002

I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

Bit Default & Field Name (ID): Description Range Access

Transmit FIFO Completely Empty (TFE): When the transmit FIFO is completely 1h empty, this bit is set. When it contains one or more valid entries, this bit is cleared. 2 This bit field does not request an interrupt. RO 0: Transmit FIFO is not empty 1: Transmit FIFO is empty

Transmit FIFO Not Full (TFNF): Set when the transmit FIFO contains one or more 1h empty locations, and is cleared when the FIFO is full. 1 RO 0: Transmit FIFO is full 1: Transmit FIFO is not full

0h ACTIVITY (ACTIVITY): I2C Activity Status 0 RO

5.2.27 I2C Transmit FIFO Level (IC_TXFLR)—Offset 74h

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD TXFLR

Bit Default & Field Name (ID): Description Range Access

0h 31:9 Reserved. RO

0h Transmit FIFO Level (TXFLR): Contains the number of valid data entries in the 8:0 RO transmit FIFO.

5.2.28 I2C Receive FIFO Level (IC_RXFLR)—Offset 78h

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RXFLR

332219-002 321 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

Bit Default & Field Name (ID): Description Range Access

0h 31:9 Reserved. RO

0h Receive FIFO Level (RXFLR): Receive FIFO Level. Contains the number of valid 8:0 RO data entries in the receive FIFO.

5.2.29 I2C SDA Hold Time Length (IC_SDA_HOLD)—Offset 7Ch

This register controls the amount of hold time on the SDA signal after a negative edge of SCL, in units of 10 MHz. The value programmed must be greater than the minimum hold time in each mode for the value to be implemented—one cycle in master mode. Writes to this register succeed only when IC_ENABLE=0. The programmed SDA hold time cannot exceed at any time the duration of the low part of SCL. Therefore, the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the SCL period measured in ic_clk cycles (10 MHz).

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 1h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000001 RSVD IC_SDA_HOLD

Bit Default & Field Name (ID): Description Range Access

0h 31:16 Reserved. RO

1h IC_SDA_HOLD (IC_SDA_HOLD): Sets the required SDA hold time in units of ic_clk 15:0 RW period.

5.2.30 I2C Transmit Abort Source (IC_TX_ABRT_SOURCE)— Offset 80h

This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in

322 332219-002

I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted.

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD ARB_LOST TX_FLUSH_CNT ABRT_USER_ABRT ABRT_HS_ACKDET ABRT_SLVRD_INTX ABRT_MASTER_DIS ABRT_GCALL_READ ABRT_HS_NORSTRT ABRT_GCALL_NOACK ABRT_SBYTE_ACKDET ABRT_TXDATA_NOACK ABRT_SBYTE_NORSTRT ABRT_10ADDR2_NOACK ABRT_10ADDR1_NOACK ABRT_7B_ADDR_NOACK ABRT_10B_RD_NORSTRT

Bit Default & Field Name (ID): Description Range Access

0h TX_FLUSH_CNT (TX_FLUSH_CNT): This field preserves the TXFLR value prior to 31:24 RO the last TX_ABRT event. It is cleared whenever I2C is disabled.

0h 23:17 Reserved. RO

0h ABRT_USER_ABRT (ABRT_USER_ABRT): Master has detected the user initiated 16 RO transfer abort (IC_ENABLE[1])

0h ABRT_SLVRD_INTX (ABRT_SLVRD_INTX) 15 RO

0h Reserved 14 RO

0h Reserved 13 RO

0h ARB_LOST (ARB_LOST): 1: Master has lost arbitration, or if 12 RO IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration.

0h ABRT_MASTER_DIS (ABRT_MASTER_DIS): 1: User tries to initiate a Master 11 RO operation with the Master mode disabled.

0h ABRT_10B_RD_NORSTRT (ABRT_10B_RD_NORSTRT): 1: The restart is 10 disabled (IC_RESTART_EN bit (IC_CON[5]) = 0) and the master sends a read RO command in 10-bit addressing mode.

ABRT_SBYTE_NORSTRT (ABRT_SBYTE_NORSTRT): 1: The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) = 0) and the user is trying to send a START Byte. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart 0h must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or 9 the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the RO ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets re- asserted.

332219-002 323 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

Bit Default & Field Name (ID): Description Range Access

0h ABRT_HS_NORSTRT (ABRT_HS_NORSTRT): 1: The restart is disabled 8 (IC_RESTART_EN bit (IC_CON[5]) = 0) and the user is trying to use the master to RO transfer data in High Speed mode.

0h ABRT_SBYTE_ACKDET (ABRT_SBYTE_ACKDET): 1: Master has sent a START 7 RO Byte and the START Byte was acknowledged (wrong behavior).

0h ABRT_HS_ACKDET (ABRT_HS_ACKDET): 1: Master is in High Speed mode and 6 RO the High Speed Master code was acknowledged (wrong behavior).

0h ABRT_GCALL_READ (ABRT_GCALL_READ): 1: Controller in master mode sent a 5 General Call but the user programmed the byte following the General Call to be a RO read from the bus (IC_DATA_CMD[9] is set to 1).

0h ABRT_GCALL_NOACK (ABRT_GCALL_NOACK): 1: controller in master mode sent 4 RO a General Call and no slave on the bus acknowledged the General Call.

ABRT_TXDATA_NOACK (ABRT_TXDATA_NOACK): 1: This is a master-mode only 0h 3 bit. Master has received an acknowledgement for the address, but when it sent data RO byte(s) following the address, it did not receive an acknowledge from the remote slave(s).

0h ABRT_10ADDR2_NOACK (ABRT_10ADDR2_NOACK): 1: Master is in 10-bit 2 address mode and the second address byte of the 10-bit address was not RO acknowledged by any slave.

0h ABRT_10ADDR1_NOACK (ABRT_10ADDR1_NOACK): 1: Master is in 10-bit 1 RO address mode and the first 10-bit address byte was not acknowledged by any slave.

0h ABRT_7B_ADDR_NOACK (ABRT_7B_ADDR_NOACK): 1: Master is in 7-bit 0 RO addressing mode and the address sent was not acknowledged by any slave.

5.2.31 DMA Control (IC_DMA_CR)—Offset 88h

This register is only valid when the controller is configured with a set of DMA Controller interface signals (IC_HAS_DMA = 1). When the controller is not configured for DMA operation, this register does not exist and writing to the register’s address has no effect and reading from this register address will return zero. The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE.

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD TDMAE RDMAE

324 332219-002

I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

Transmit DMA Enable (TDMAE): This bit enables/disables the transmit FIFO DMA 0h 1 channel. RW 0 = Transmit DMA disabled 1 = Transmit DMA enabled

Receive DMA Enable (RDMAE): This bit enables/disables the receive FIFO DMA 0h channel. 0 RW 0 = Receive DMA disabled 1 = Receive DMA enabled

5.2.32 DMA Transmit Data Level (IC_DMA_TDLR)—Offset 8Ch

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD DMATDL

Bit Default & Field Name (ID): Description Range Access

0h 31:8 Reserved. RO

Transmit Data Level (DMATDL): This bit field controls the level at which a DMA 0h request is made by the transmit logic. It is equal to the watermark level; that is, the 7:0 RW dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1.

5.2.33 I2C Receive Data Level (IC_DMA_RDLR)—Offset 90h

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD DMARDL

332219-002 325 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

Bit Default & Field Name (ID): Description Range Access

0h 31:8 Reserved. RO

DMARDL (DMARDL): This bit field controls the level at which a DMA request is 0h made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is 7:0 generated when the number of valid data entries in the receive FIFO is equal to or RW more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO.

5.2.34 I2C ACK General Call (IC_ACK_GENERAL_CALL)—Offset 98h

The register controls whether the controller responds with a ACK or NACK when it receives an I2C General Call address.

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 1h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000001 RSVD ACK_GEN_CALL

Bit Default & Field Name (ID): Description Range Access

0h 31:1 Reserved. RO

1h ACK_GEN_CALL (ACK_GEN_CALL): When set to 1, the controller responds with a 0 ACK when it receives a General Call. When set to 0, the controller does not generate RW General Call interrupts

5.2.35 I2C Enable Status (IC_ENABLE_STATUS)—Offset 9Ch

The register is used to report the hardware status when the IC_ENABLE register is set from 1 to 0; that is, when the controller is disabled. If IC_ENABLE has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1. If IC_ENABLE has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as ‘0’. When IC_ENABLE has been written with ‘0,’ a delay occurs for bit 0 to be read as ‘0’ because disabling the controller depends on I2C bus activities.

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

326 332219-002

I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD IC_EN

Bit Default & Field Name (ID): Description Range Access

0h 31:1 Reserved. RO

0h I2C Enable Status (IC_EN): When read as 1, the controller is deemed to be in an 0 RO enabled state. When read as 0, the controller is deemed completely inactive.

5.2.36 I2C SS and FS Spike Suppression Limit (IC_FS_SPKLEN)— Offset A0h

This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS or FS modes. The relevant I2C requirement is tSP as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1.

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 7h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000111 RSVD IC_FS_SPKLEN

Bit Default & Field Name (ID): Description Range Access

0h 31:8 Reserved. RO

IC_FS_SPKLEN (IC_FS_SPKLEN): This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that are 7h filtered out by the spike suppression logic. 7:0 This register can be written only when the I2C interface is disabled, which RW corresponds to the IC_ENABLE register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 2 being set.

332219-002 327 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

5.2.37 Clear RESTART_DET Interrupt (IC_CLR_RESTRART_DET)— Offset A8h

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD IC_CLR_RESTART_DET

Bit Default & Field Name (ID): Description Range Access

0h 31:1 Reserved. RO

0h IC_CLR_RESTART_DET (IC_CLR_RESTART_DET): Read this register to clear the 0 RESTART_DET interrupt (bit 12) of the IC_RAW_INTR_STAT register. RO This register is present only when IC_SLV_RESTART_DET_EN = 1.

5.3 I2C Additional Registers Summary

The registers in this section are memory-mapped registers based on the BAR defined in PCH Configuration space.

Table 5-3. Summary of I2C Additional Registers

Offset Offset Default Register Name (ID)—Offset Start End Value

204h 207h Soft Reset (RESETS)—Offset 204h 0h

210h 213h Active LTR (ACTIVELTR_VALUE)—Offset 210h 800h

214h 217h Idle LTR (IDLELTR_VALUE)—Offset 214h 800h

218h 21Bh TX Ack Count (TX_ACK_COUNT)—Offset 218h 0h

21Ch 21Fh RX ACK Count (RX_BYTE_COUNT)—Offset 21Ch 0h

Interrupt Status for Tx Complete (TX_COMPLETE_INTR_STAT)—Offset 220h 223h 0h 220h

224h 227h Tx Complete Interrupt Clear (TX_COMPLETE_INTR_CLR)—Offset 224h 0h

228h 22Bh SW Scratch Register 0 (SW_SCRATCH_0)—Offset 228h 0h

22Ch 22Fh SW Scratch Register 1 (SW_SCRATCH_1)—Offset 22Ch 0h

230h 233h SW Scratch Register 2 (SW_SCRATCH_2)—Offset 230h 0h

234h 237h SW Scratch Register 3 (SW_SCRATCH_3)—Offset 234h 0h

328 332219-002

I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

Table 5-3. Summary of I2C Additional Registers (Continued)

Offset Offset Default Register Name (ID)—Offset Start End Value

238h 23Bh Clock Gate (CLOCK_GATE)—Offset 238h 0h

240h 243h Remap Address Low (REMAP_ADDR_LO)—Offset 240h 0h

244h 247h Remap Address High (REMAP_ADDR_HI)—Offset 244h 0h

2FCh 2FFh Capabilities (CAPABLITIES)—Offset 2FCh 0h

5.3.1 Soft Reset (RESETS)—Offset 204h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RESET_I2C RESET_DMA

Bit Default & Field Name (ID): Description Range Access

0h 31:3 Reserved. RO

0h DMA Software Reset Control (RESET_DMA): DMA Software Reset Control 2 0 – DMA is in reset (Reset Asserted) RW 1 – DMA is NOT at reset (Reset Released)

I2C Host Controller Reset (RESET_I2C): Used to reset the I2C Host Controller by SW control. All I2C Configuration State and Operational State will be forced to the Default state. There is no timing requirement (SW can assert and de-assert in back to back transactions). This reset does NOT impact the I2C level settings by BIOS, the PCI configuration 0h header information, DMA channel configuration and interrupt assignment/mapping/ 1:0 RW etc. Driver should re-initialize registers related to Driver context following an I2C host controller reset. 00 = I2C Host Controller is in reset (Reset Asserted) 01 = Reserved 10 = Reserved 11 = I2C Host Controller is NOT at reset (Reset Released)

5.3.2 Active LTR (ACTIVELTR_VALUE)—Offset 210h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 800h

332219-002 329 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000100000000000 RSVD RSVD snoop_value non_snoop_value snoop_requirment non_snoop_requirment non_snoop_latency_scale i2c_sw_ltr_snoop_scale_reg_12_10

Bit Default & Field Name (ID): Description Range Access

Non-Snoop Requirement (non_snoop_requirment): If the Requirement (bit 15) 0h is clear, that indicates that the device has no LTR requirement for this type of traffic 31 (i.e. it can wait for service indefinitely). If the 10-bit latency value is zero it indicates RO that the device cannot tolerate any delay and needs the best possible service/ response time.

0h 30:29 Reserved. RO

Non-Snoop Latency Scale (non_snoop_latency_scale): Support for codes 010 0h 28:26 (1us) or 011 (32us) for Snoop Latency Scale (1us -> 32ms total span) only. Writes to RO this CSR which don't match those values will be dropped completely, next read will return previous value.

0h Non-Snoop Value (non_snoop_value): 10-bit latency value 25:16 RO

Snoop Requirement (snoop_requirment): If the Requirement (bit 15) is clear, 0h that indicates that the device has no LTR requirement for this type of traffic (i.e. it 15 can wait for service indefinitely). If the 10-bit latency value is zero it indicates that RW the device cannot tolerate any delay and needs the best possible service/response time.

0h 14:13 Reserved. RO

Snoop Latency Scale (i2c_sw_ltr_snoop_scale_reg_12_10): Support for codes 2h 010 (1us) or 011 (32us) for Snoop Latency Scale(1us -> 32ms total span) only. 12:10 Writes to this CSR which don't match those values will be dropped completely, next read will return previous value.

0h Snoop Value (snoop_value): 10-bit latency value 9:0 RW

5.3.3 Idle LTR (IDLELTR_VALUE)—Offset 214h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 800h

330 332219-002

I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000100000000000 RSVD RSVD snoop_value non_snoop_value snoop_requirment snoop_latency_scale non_snoop_requirment non_snoop_latency_scale

Bit Default & Field Name (ID): Description Range Access

Non-Snoop Requirement (non_snoop_requirment): If the Requirement (bit 15) 0h is clear, that indicates that the device has no LTR requirement for this type of traffic 31 (i.e. it can wait for service indefinitely). If the 10-bit latency value is zero it indicates RO that the device cannot tolerate any delay and needs the best possible service/ response time.

0h 30:29 Reserved. RO

Non-Snoop Latency Scale (non_snoop_latency_scale): Support for codes 010 0h (1us) or 011 (32us) for Snoop Latency Scale (1us -> 32ms total span) only. Writes to 28:26 RO this CSR which don't match those values will be dropped completely, next read will return previous value.

0h Non-Snoop Value (non_snoop_value): 10-bit latency value 25:16 RO

Snoop Requirement (snoop_requirment): If the Requirement (bit 15) is clear, 0h that indicates that the device has no LTR requirement for this type of traffic (i.e. it 15 can wait for service indefinitely). If the 10-bit latency value is zero it indicates that RW the device cannot tolerate any delay and needs the best possible service/response time.

0h 14:13 Reserved. RO

Snoop Latency Scale (snoop_latency_scale): Support for codes 010 (1us) or 2h 12:10 011 (32us) for Snoop Latency Scale(1us -> 32ms total span) only. Writes to this CSR RW which don't match those values will be dropped completely, next read will return previous value.

0h Snoop Value (snoop_value): 10-bit latency value 9:0 RW

5.3.4 TX Ack Count (TX_ACK_COUNT)—Offset 218h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

332219-002 331 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD tx_ack_count tx_ack_count_overflow

Bit Default & Field Name (ID): Description Range Access

0h Tx Count Overflow (tx_ack_count_overflow): Tx_count_overflow 31 0= count valid RO 1= count overflow/invalid

0h 30:24 Reserved. RO

0h TX Ack Count (tx_ack_count): 24-bit up-counter which counts the number of TX 23:0 ACKs on the I2C bus. RO The Counter is forced to be cleared by software Read.

5.3.5 RX ACK Count (RX_BYTE_COUNT)—Offset 21Ch

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD rx_ack_count rx_ack_count_overflow

Bit Default & Field Name (ID): Description Range Access

0h RX ACK Count Overflow (rx_ack_count_overflow): Rx ACK count_overflow 31 0= count valid RO 1= count overflow/invalid

0h 30:24 Reserved. RO

0h Rx ACK Count (rx_ack_count): 24-bit readable (MMIO) up-counter which counts 23:0 the number of RX bytes received on the I2C bus. RO The Counter is forced to be cleared by software Read

332 332219-002

I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

5.3.6 Interrupt Status for Tx Complete (TX_COMPLETE_INTR_STAT)—Offset 220h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD tx_intr_stat tx_intr_stat_mask

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h TX completion interrupt Mask (tx_intr_stat_mask): 0 = Unmask 1 RW 1= Mask

0h Tx Completion Interrupt (tx_intr_stat): 0 = Low 0 RO 1 = High

5.3.7 Tx Complete Interrupt Clear (TX_COMPLETE_INTR_CLR)— Offset 224h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD i2c_tx_complete_intr_clr_0

332219-002 333 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

Bit Default & Field Name (ID): Description Range Access

0h 31:1 Reserved. RO

0h TX completion interrupt Clear (i2c_tx_complete_intr_clr_0): Read this 0 RO register to clear the TX_COMPLETE_INTR_STAT register

5.3.8 SW Scratch Register 0 (SW_SCRATCH_0)—Offset 228h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 SW_Scratch_0

Bit Default & Field Name (ID): Description Range Access

0h SW Scratch Reg 0 (SW_Scratch_0): Scratch Pad Register for SW to generated 31:0 RW Local CMD or DATA for DMA

5.3.9 SW Scratch Register 1 (SW_SCRATCH_1)—Offset 22Ch

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 SW_Scratch_1

334 332219-002

I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

Bit Default & Field Name (ID): Description Range Access

0h SW Scratch Register 1 (SW_Scratch_1): Scratch Pad Register for SW to 31:0 RW generated Local CMD or DATA for DMA.

5.3.10 SW Scratch Register 2 (SW_SCRATCH_2)—Offset 230h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 SW_Scratch_2

Bit Default & Field Name (ID): Description Range Access

0h SW Scratch Register 2 (SW_Scratch_2): Scratch Pad Register for SW to 31:0 RW generated Local CMD or DATA for DMA

5.3.11 SW Scratch Register 3 (SW_SCRATCH_3)—Offset 234h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 SW_Scratch_3

Bit Default & Field Name (ID): Description Range Access

0h SW Scratch Register 3 (SW_Scratch_3): Scratch Pad Register for SW to 31:0 RW generated Local CMD or DATA for DMA

332219-002 335 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

5.3.12 Clock Gate (CLOCK_GATE)—Offset 238h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD sw_ip_clk_ctl sw_dma_clk_ctl

Bit Default & Field Name (ID): Description Range Access

0h 31:4 Reserved. RO

DMA Clock Control (sw_dma_clk_ctl): 00 = Dyanamic Clock Gate Enable 0h 01 = Reserved 3:2 RW 10 = Force DMA Clock off 11 = Force DMA Clock on

Controller Clock Control (sw_ip_clk_ctl): 00 = Dynamic Clock Gate Enable 0h 01 = Reserved 1:0 RW 10 = Force Clocks off 11 = Force Clocks on

5.3.13 Remap Address Low (REMAP_ADDR_LO)—Offset 240h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 i2c_remap_addr_lo_reg

336 332219-002

I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

Bit Default & Field Name (ID): Description Range Access

0h Remap Address Low (i2c_remap_addr_lo_reg): Must be programmed to the 31:0 same value as low 32 bits (0x 010 BAR Low) RW Note: Must be programed for all I2C controllers configurations (DMA or PIO only)

5.3.14 Remap Address High (REMAP_ADDR_HI)—Offset 244h

i2c remap address hi register

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 i2c_remap_addr_hi

Bit Default & Field Name (ID): Description Range Access

0h Remap Address High (i2c_remap_addr_hi): Must be programmed to the same 31:0 RW value as low 32 bits (0x 014 BAR High)

5.3.15 Capabilities (CAPABLITIES)—Offset 2FCh

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD iDMA_present instance_type serial_clk_freq instance_number

332219-002 337 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

Bit Default & Field Name (ID): Description Range Access

0h 31:10 Reserved. RO

0h Serial Clock Frequency (serial_clk_freq): 0 indicates 120 MHz clock. 9 RO

0h DMA Present (iDMA_present): 8 0= DMA present RO 1= DMA not present

Instant Type (instance_type): 0h 0000 = IC2 7:4 0001 = UART RO 0010 = SPI 0011 – 1111 = Reserved

Instant Number (instance_number): 0h: I2C0 0h 1h: I2C1 3:0 RO 2h: I2C2 ... 5h: I2C5[br

5.4 I2C DMA Controller Registers Summary

Table 5-4. Summary of I2C DMA Controller Registers

Offset Offset Default Register Name (ID)—Offset Start End Value

800h 803h DMA Transfer Source Address Low (SAR_LO0)—Offset 800h 0h

804h 807h DMA Transfer Source Address High (SAR_HI0)—Offset 804h 0h

808h 80Bh DMA Transfer Destination Address Low (DAR_LO0)—Offset 808h 0h

80Ch 80Fh DMA Transfer Destination Address High (DAR_HI0)—Offset 80Ch 0h

810h 813h Linked List Pointer Low (LLP_LO0)—Offset 810h 0h

814h 817h Linked List Pointer High (LLP_HI0)—Offset 814h 0h

818h 81Bh Control Register Low (CTL_LO0)—Offset 818h 0h

81Ch 81Fh Control Register High (CTL_HI0)—Offset 81Ch 0h

820h 823h Source Status (SSTAT0)—Offset 820h 0h

828h 82Bh Destination Status (DSTAT0)—Offset 828h 0h

830h 833h Source Status Address Low (SSTATAR_LO0)—Offset 830h 0h

834h 837h Source Status Address High (SSTATAR_HI0)—Offset 834h 0h

838h 83Bh Destination Status Address Low (DSTATAR_LO0)—Offset 838h 0h

83Ch 83Fh Destination Status Address High (DSTATAR_HI0)—Offset 83Ch 0h

840h 843h DMA Transfer Configuration Low (CFG_LO0)—Offset 840h 203h

844h 847h DMA Transfer Configuration High (CFG_HI0)—Offset 844h 0h

848h 84Bh Source Gather (SGR0)—Offset 848h 0h

850h 853h Destination Scatter (DSR0)—Offset 850h 0h

AC0h AC3h Raw Interrupt Status (RawTfr)—Offset AC0h 0h

AC8h ACBh Raw Status for Block Interrupts (RawBlock)—Offset AC8h 0h

AD0h AD3h Raw Status for Source Transaction Interrupts (RawSrcTran)—Offset AD0h 0h

Raw Status for Destination Transaction Interrupts (RawDstTran)—Offset AD8h ADBh 0h AD8h

338 332219-002

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Table 5-4. Summary of I2C DMA Controller Registers (Continued)

Offset Offset Default Register Name (ID)—Offset Start End Value

AE0h AE3h Raw Status for Error Interrupts (RawErr)—Offset AE0h 0h

AE8h AEBh Interrupt Status (StatusTfr)—Offset AE8h 0h

AF0h AF3h Status for Block Interrupts (StatusBlock)—Offset AF0h 0h

AF8h AFBh Status for Source Transaction Interrupts (StatusSrcTran)—Offset AF8h 0h

Status for Destination Transaction Interrupts (StatusDstTran)—Offset B00h B03h 0h B00h

B08h B0Bh Status for Error Interrupts (StatusErr)—Offset B08h 0h

B10h B13h Mask for Transfer Interrupts (MaskTfr)—Offset B10h 0h

B18h B1Bh Mask for Block Interrupts (MaskBlock)—Offset B18h 0h

B20h B23h Mask for Source Transaction Interrupts (MaskSrcTran)—Offset B20h 0h

B28h B2Bh Mask for Destination Transaction Interrupts (MaskDstTran)—Offset B28h 0h

B30h B33h Mask for Error Interrupts (MaskErr)—Offset B30h 0h

B38h B3Bh Clear for Transfer Interrupts (ClearTfr)—Offset B38h 0h

B40h B43h Clear for Block Interrupts (ClearBlock)—Offset B40h 0h

B48h B4Bh Clear for Source Transaction Interrupts (ClearSrcTran)—Offset B48h 0h

B50h B53h Clear for Destination Transaction Interrupts (ClearDstTran)—Offset B50h 0h

B58h B5Bh Clear for Error Interrupts (ClearErr)—Offset B58h 0h

B60h B63h Combined Status register (StatusInt)—Offset B60h 0h

B98h B9Bh DMA Configuration (DmaCfgReg)—Offset B98h 0h

BA0h BA3h DMA Channel Enable (ChEnReg)—Offset BA0h 0h

5.4.1 DMA Transfer Source Address Low (SAR_LO0)—Offset 800h

NOTE: SAR_LO0 is for DMA Channel 0. The same register definition,SAR_LO1, is available for Channel 1 at address 858h. SAR_LO0 (CH0): offset 800h SAR_LO1 (CH1): offset 858h The starting source address is programmed by software before the DMA channel is enabled, or by an LLI update before the start of the DMA transfer. While the DMA transfer is in progress, this register is updated to reflect the source address of the current transfer.

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

332219-002 339 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 SAR_LO

Bit Default & Field Name (ID): Description Range Access

SAR_LO: Current Source Address of DMA transfer.

Updated after each source transfer. The SINC field in the CTL_LO[n]: Control Register determines whether the address increments or is left unchanged on every source transfer throughout the block transfer. When the channel is enabled (i.e. CH_EN is 1), the read back value will reflect the updated source transfer addresses. However, when the channel is disabled, the original programmed value will be reflected when reading this register.

It's important to notice the following: 1. Once the block transfer is in progress (i.e. when channel is enabled), the read- back value correlates with the OCP Read Address that one would see in an OCP tracker. 0h 2. If the read to this register comes during a block transfer, the LAST DMA Read 31:0 RW address sent on the OCP before the register read is what's reflected in the read-back value. 3. If the last DMA read was a burst read (i.e. burst length > 1), the read-back value reflects the first address of the burst read since this is what gets sent on the OCP fabric. 4. If the read to the register occurred after the whole block got transferred, then the channel gets disabled and the returned value would be the original programmed value. 5. Since the read-back value is OCP based, only DW aligned addresses will be reflected (i.e. OCP Byte-Enable values would not be reflected) 6. Based on the above remarks, this value should be used as pseudo DMA read progress indicator when the channel is enabled and not an absolute one.

Decrementing addresses are not supported.

5.4.2 DMA Transfer Source Address High (SAR_HI0)—Offset 804h

NOTE: SAR_HI0 is for DMA Channel 0. The same register definition, SAR_HI1, is available for Channel 1 at address 85Ch. SAR_HI0 (CH0): offset 804h SAR_HI1 (CH1): offset 85Ch The starting source address is programmed by software before the DMA channel is enabled, or by an LLI update before the start of the DMA transfer. While the DMA transfer is in progress, this register is updated to reflect the source address of the current transfer.

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

340 332219-002

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3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 SAR_HI

Bit Default & Field Name (ID): Description Range Access

SAR_HI: Current Source Address of DMA transfer.

Updated after each source transfer. The SINC field in the CTL_LO[n]: Control Register determines whether the address increments or is left unchanged on every source transfer throughout the block transfer. When the channel is enabled (i.e. CH_EN is 1), the read back value will reflect the updated source transfer addresses. However, when the channel is disabled, the original programmed value will be reflected when reading this register.

It's important to notice the following: 1. Once the block transfer is in progress (i.e. when channel is enabled), the read- back value correlates with the OCP Read Address that one would see in an OCP tracker. 0h 2. If the read to this register comes during a block transfer, the LAST DMA Read 31:0 RW address sent on the OCP before the register read is what's reflected in the read-back value. 3. If the last DMA read was a burst read (i.e. burst length > 1), the read-back value reflects the first address of the burst read since this is what gets sent on the OCP fabric. 4. If the read to the register occurred after the whole block got transferred, then the channel gets disabled and the returned value would be the original programmed value. 5. Since the read-back value is OCP based, only DW aligned addresses will be reflected (i.e. OCP Byte-Enable values would not be reflected) 6. Based on the above remarks, this value should be used as pseudo DMA read progress indicator when the channel is enabled and not an absolute one.

Decrementing addresses are not supported

5.4.3 DMA Transfer Destination Address Low (DAR_LO0)—Offset 808h

NOTE: DAR_LO0 is for DMA Channel 0. The same register definition, DAR_LO1, is available for Channel 1 at address 860h. DAR_LO0 (CH0): offset 808h DAR_LO1 (CH1): offset 860h The starting destination address is programmed by software before the DMA channel is enabled, or by an LLI update before the start of the DMA transfer. While the DMA transfer is in progress, this register is updated to reflect the destination address of the current transfer.

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

332219-002 341 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 DAR_LO

Bit Default & Field Name (ID): Description Range Access

DAR_LO: Current Destination Address of DMA transfer.

Updated after each destination transfer. The DINC field in the CTL_LO[n]: Control Register determines whether the address increments or is left unchanged on every destination transfer throughout the block transfer. When the channel is enabled (i.e. CH_EN is 1), the read back value will reflect the updated destination transfer addresses. However, when the channel is disabled, the original programmed value will be reflected when reading this register.

It's important to notice the following: 1. Once the block transfer is in progress (i.e. when channel is enabled), the read- back value correlates with the OCP Write Address that one would see in an OCP tracker. 0h 2. If the read to this register comes during a block transfer, the LAST DMA Write 31:0 RW address sent on the OCP before the register read is what's reflected in the read-back value. 3. If the last DMA write was a burst write (i.e. burst length > 1), the read-back value reflects the first address of the burst write since this is what gets sent on the OCP fabric. 4. If the read to the register occurred after the whole block got transferred, then the channel gets disabled and the returned value would be the original programmed value. 5. Since the read-back value is OCP based, only DW aligned addresses will be reflected (i.e. OCP Byte-Enable values would not be reflected) 6. Based on the above remarks, this value should be used as pseudo DMA write progress indicator when the channel is enabled and not an absolute one.

Decrementing addresses are not supported

5.4.4 DMA Transfer Destination Address High (DAR_HI0)— Offset 80Ch

NOTE: DAR_HI0 is for DMA Channel 0. The same register definition, DAR_HI1, is available for Channel 1 at address 864h. DAR_HI0 (CH0): offset 80Ch DAR_HI1 (CH1): offset 864h The starting destination address is programmed by software before the DMA channel is enabled, or by an LLI update before the start of the DMA transfer. While the DMA transfer is in progress, this register is updated to reflect the destination address of the current transfer.

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

342 332219-002

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3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 DAR_HI

Bit Default & Field Name (ID): Description Range Access

DAR_HI: Current Destination Address of DMA transfer.

Updated after each destination transfer. The DINC field in the CTL_LO[n]: Control Register determines whether the address increments or is left unchanged on every destination transfer throughout the block transfer. When the channel is enabled (i.e. CH_EN is 1), the read back value will reflect the updated destination transfer addresses. However, when the channel is disabled, the original programmed value will be reflected when reading this register.

It's important to notice the following: 1. Once the block transfer is in progress (i.e. when channel is enabled), the read- back value correlates with the OCP Write Address that one would see in an OCP tracker. 0h 2. If the read to this register comes during a block transfer, the LAST DMA Write 31:0 RW address sent on the OCP before the register read is what's reflected in the read-back value. 3. If the last DMA write was a burst write (i.e. burst length > 1), the read-back value reflects the first address of the burst write since this is what gets sent on the OCP fabric. 4. If the read to the register occurred after the whole block got transferred, then the channel gets disabled and the returned value would be the original programmed value. 5. Since the read-back value is OCP based, only DW aligned addresses will be reflected (i.e. OCP Byte-Enable values would not be reflected) 6. Based on the above remarks, this value should be used as pseudo DMA write progress indicator when the channel is enabled and not an absolute one.

Decrementing addresses are not supported

5.4.5 Linked List Pointer Low (LLP_LO0)—Offset 810h

NOTE: LLP_LO0 is for DMA Channel 0. The same register definition, LLP_LO1, is available for Channel 1 at address 868h. LLP_LO0 (CH0): offset 810h LLP_LO1 (CH1): offset 868h The register needs to be programmed to point to the first Linked List Item (LLI) in memory prior to enabling the channel if block chaining is enabled.

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 LOC RSVD

332219-002 343 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

Bit Default & Field Name (ID): Description Range Access

LOC (LOC): Starting Address In Memory of next LLI if block chaining is enabled. 0h 31:2 Note that the two LSBs of the starting address are not stored because the address is RW assumed to be aligned to a 32-bit boundary. LLI accesses are always 32-bit accesses and cannot be changed or programmed to anything other than 32-bit.

0h 1:0 Reserved. RO

5.4.6 Linked List Pointer High (LLP_HI0)—Offset 814h

NOTE: LLP_HI0 is for DMA Channel 0. The same register definition, LLP_HI1, is available for Channel 1 at address 86Ch. LLP_HI0 (CH0): offset 814h LLP_LO1 (CH1): offset 86Ch The register needs to be programmed to point to the first Linked List Item (LLI) in memory prior to enabling the channel if block chaining is enabled.

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 LOC RSVD

Bit Default & Field Name (ID): Description Range Access

LOC (LOC): Starting Address In Memory of next LLI if block chaining is enabled. 0h Note that the two LSBs of the starting address are not stored because the address is 31:2 RW assumed to be aligned to a 32-bit boundary. LLI accesses are always 32-bit accesses and cannot be changed or programmed to anything other than 32-bit.

0h 1:0 Reserved. RO

5.4.7 Control Register Low (CTL_LO0)—Offset 818h

NOTE: CTL_LO0 is for DMA Channel 0. The same register definition, CTL_LO1, is available for Channel 1 at address 870h. LLP_HI0 (CH0): offset 818h LLP_LO1 (CH1): offset 870h This register contains fields that control the DMA transfer. The CTL_HI register is part of the block descriptor (linked list item - LLI) when block chaining is enabled. It can be varied on a block-by-block basis within a DMA transfer when block chaining is enabled. If status write-back is enabled, CTL_HI is written to then control registers location of the LLI in system memory at the end of the block transfer.

Access Method

344 332219-002

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Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 SINC DINC RSVD RSVD RSVD RSVD RSVD TT_FC INT_EN SRC_MSIZE LLP_DST_EN LLP_SRC_EN DEST_MSIZE DST_TR_WIDTH SRC_TR_WIDTH SRC_GATHER_EN DST_SCATTER_EN

Bit Default & Field Name (ID): Description Range Access

0h 31:29 Reserved. RO

0h LLP Source Enable (LLP_SRC_EN): Block chaining is enabled on the source side 28 RW only if the LLP_SRC_EN field is high and LLPn.LOC is non-zero and (LLP_EN == 1)

0h LLP Destination Enable (LLP_DST_EN): Block chaining is enabled on the 27 destination side only if the LLP_DST_EN field is high and LLPn.LOC is non-zero and RW (LLP_EN == 1)

0h 26:22 Reserved. RO

Transfer Type and Flow Control (TT_FC): The following transfer types are supported.

0h Memory to Memory (00) 21:20 Memory to Peripheral (01) RW Peripheral to Memory (10) Peripheral to Peripheral (11) Flow Control is always assigned to the DMA.

0h 19 Reserved. RO

Destination Scatter Enable (DST_SCATTER_EN): 0 = Scatter disabled

0h 1 = Scatter enabled 18 RW Scatter on the destination side is applicable only when the CTL_LOn.DINC bit indicates an incrementing address control.

Source Gather Enable (SRC_GATHER_EN): 0 = Gather disabled

0h 1 = Gather enabled 17 RW Gather on the source side is applicable only when the CTL_LOn.SINC bit indicates an incrementing address control.

0h Source Burst Transaction Length (SRC_MSIZE): Number of data items, each of 16:14 RW width CTL_LOn.SRC_TR_WIDTH, to be read from the source.

0h Destination Burst Transaction Length (DEST_MSIZE): Number of data items, 13:11 RW each of width CTL_LOn.DST_TR_WIDTH, to be written to the destination.

Source Address Increment (SINC): Indicates whether to increment or decrement 0h the source address on every source transfer. If the device is fetching data from a 10 source peripheral FIFO with a fixed address, then set this field to No change. RW 0 = Increment 1 = Fixed (No Change)

0h 9 Reserved. RO

332219-002 345 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

Bit Default & Field Name (ID): Description Range Access

Destination Address Increment (DINC): Indicates whether to increment or decrement the destination address on every destination transfer. If your device is 0h writing data to a destination peripheral FIFO with a fixed address, then set this field 8 RW to No change. 0 = Increment 1 = Fixed (No change)

0h 7 Reserved. RO

Source Transfer Width (SRC_TR_WIDTH): BURST_SIZE = (2 ^ MSIZE)

0h 1. Transferred Bytes Per Burst = (BURST_SIZE * TR_WIDTH) 6:4 2. For incrementing addresses and (Transfer_Width < 4 Bytes), the MSIZE RW parameter is ignored since only single transactions are supported (due to OCP limitations)

Destination Transfer Width (DST_TR_WIDTH): Destination Transfer Width. BURST_SIZE = (2 ^ MSIZE) 0h 3:1 1.Transferred Bytes Per Burst = (BURST_SIZE * TR_WIDTH) RW 2.For incrementing addresses and (Transfer_Width < 4 Bytes), the MSIZE parameter is ignored since only single transactions are supported (due to OCP limitations)

0h Interrupt Enable (INT_EN): Interrupt Enable Bit. If set, then all interrupt- 0 RW generating sources are enabled.

5.4.8 Control Register High (CTL_HI0)—Offset 81Ch

NOTE: CTL_HI0 is for DMA Channel 0. The same register definition, CTL_HI1, is available for Channel 1 at address 874h. CTL_HI0 (CH0): offset 81Ch CTL_HI1 (CH1): offset 874h This register contains fields that control the DMA transfer. The CTL_HI register is part of the block descriptor (linked list item - LLI) when block chaining is enabled. It can be varied on a block-by-block basis within a DMA transfer when block chaining is enabled.If status write-back is enabled, CTL_HI is written to then control registers location of the LLI in system memory at the end of the block transfer.

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD DONE BLOCK_TS CH_CLASS

346 332219-002

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Bit Default & Field Name (ID): Description Range Access

0h Channel Class (CH_CLASS): A Class of (N_CHNLS-1) is the highest priority, and 0 31:29 is the lowest. This field must be programmed within 0 to (N_CHNLS-1). RW A programmed value outside this range will cause erroneous behavior.

0h 28:18 Reserved. RO

DONE (DONE): If status write-back is enabled, the upper word of the control register, CTL_HIn, is written to the control register location of the Linked List Item

0h (LLI) in system memory at the end of the block transfer with the done bit set. 17 Software can poll the LLI CTL_HI.DONE bit to see when a block transfer is complete. RW The LLI CTL_HI.DONE bit should be cleared when the linked lists are set up in memory prior to enabling the channel. The DMA will not transfer the block if the DONE bit in the LLI is not cleared.

Block Transfer Size (BLOCK_TS): Block Transfer Size (in Bytes). Since the DMA is always the flow controller, the user needs to write this field before the channel is enabled in order to indicate the block size. The number programmed into BLOCK_TS indicates the total number of bytes to transfer for every block 0h 16:0 transfer. RW Once the transfer starts (i.e. channel is enabled), the read-back value is the total number of bytes for which Read Commands have already been sent to the source. It doesn?t mean Bytes that are already in the FIFO. However, when the channel is disabled, the original programmed value will be reflected when reading this register. Theoretical Byte Size range is from 0 to (2^17 -1) = (128 KB - 1).

5.4.9 Source Status (SSTAT0)—Offset 820h

NOTE: SSTAT0 is for DMA Channel 0. The same register definition, SSTAT1, is available for Channel 1 at address 878h. SSTAT0 (CH0): offset 820h SSTAT1 (CH1): offset 878h After each block transfer completes, hardware can retrieve the source status information from the address pointed to by the contents of the SSTATARx register. This status information is then stored in the SSTATx register and written out to the SSTATx register location of the LLI before the start of the next block. Note : This register is a temporary placeholder for the source status information on its way to the SSTATx register location of the LLI. The source status information should be retrieved by software from the SSTATx register location of the LLI, and not by a read of this register over the DMA slave interface.

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 SSTAT

332219-002 347 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

Bit Default & Field Name (ID): Description Range Access

Source Status (SSTAT): Source status information retrieved by hardware from the address pointed to by the contents of the Source Status Address Register. This 0h register is a temporary placeholder for the source status information on its way to the 31:0 RW SSTATn register location of the LLI. The source status information should be retrieved by software from the SSTATn register location of the LLI, and not by a read of this register over the DMA slave interface.

5.4.10 Destination Status (DSTAT0)—Offset 828h

NOTE: DSTAT0 is for DMA Channel 0. The same register definition, DSTAT1, is available for Channel 1 at address 880h. DSTAT0 (CH0): offset 828h DSTAT1 (CH1): offset 880h After the completion of each block transfer, hardware can retrieve the destination status information from the address pointed to by the contents of the DSTATARx register. This status information is then stored in the DSTATx register and written out to the DSTATx register location of the LLI. Note : This register is a temporary placeholder for the destination status information on its way to the DSTATx register location of the LLI. The destination status information should be retrieved by software from the DSTATx register location of the LLI and not by a read of this register over the DMA slave interface.

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 DSTAT

Bit Default & Field Name (ID): Description Range Access

Destination Status (DSTAT): Destination status information retrieved by hardware from the address pointed to by the contents of the Destination Status Address 0h 31:0 Register. This register is a temporary placeholder for the destination status RW information on its way to the DSTATn register location of the LLI. The destination status information should be retrieved by software from the DSTATn register location of the LLI and not by a read of this register over the DMA slave interface.

5.4.11 Source Status Address Low (SSTATAR_LO0)—Offset 830h

NOTE: SSTATAR_LO0 is for DMA Channel 0. The same register definition, SSTATAR_LO1, is available for Channel 1 at address 888h. SSTATAR_LO0(CH0): offset 830h SSTATAR_LO1(CH1): offset 888h After the completion of each block transfer, hardware can retrieve the source status information from the address pointed to by the contents of the SSTATARx register.

Access Method

348 332219-002

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Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 SSTATAR_LO

Bit Default & Field Name (ID): Description Range Access

0h Source Status Address (SSTATAR_LO): Pointer from where hardware can fetch 31:0 the source status information, which is registered in the SSTATn register and written RW out to the SSTATn register location of the LLI before the start of the next block.

5.4.12 Source Status Address High (SSTATAR_HI0)—Offset 834h

NOTE: SSTATAR_HI0 is for DMA Channel 0. The same register definition, SSTATAR_HI1, is available for Channel 1 at address 88Ch. SSTATAR_HI0(CH0): offset 834h SSTATAR_HI1(CH1): offset 88Ch After the completion of each block transfer, hardware can retrieve the source status information from the address pointed to by the contents of the SSTATARx register.

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 SSTATAR_HI

Bit Default & Field Name (ID): Description Range Access

0h Source Status Address (SSTATAR_HI): Pointer from where hardware can fetch 31:0 the source status information, which is registered in the SSTATn register and written RW out to the SSTATn register location of the LLI before the start of the next block.

332219-002 349 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

5.4.13 Destination Status Address Low (DSTATAR_LO0)—Offset 838h

NOTE: DSTATAR_LO0 is for DMA Channel 0. The same register definition, DSTATAR_LO1, is available for Channel 1 at address 890h. DSTATAR_LO0(CH0): offset 838h DSTATAR_LO1(CH1): offset 890h After the completion of each block transfer, hardware can retrieve the destination status information from the address pointed to by the contents of the DSTATARx register.

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 DSTATAR_LO

Bit Default & Field Name (ID): Description Range Access

Destination Status Address (DSTATAR_LO): Pointer from where hardware can 0h 31:0 fetch the destination status information, which is registered in the DSTATn register RW and written out to the DSTATn register location of the LLI before the start of the next block.

5.4.14 Destination Status Address High (DSTATAR_HI0)—Offset 83Ch

NOTE: DSTATAR_LO0 is for DMA Channel 0. The same register definition, DSTATAR_HI1, is available for Channel 1 at address 894h. DSTATAR_HI0(CH0): offset 83Ch DSTATAR_HI1(CH1): offset 894h After the completion of each block transfer, hardware can retrieve the destination status information from the address pointed to by the contents of the DSTATARx register.

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

350 332219-002

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3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 DSTATAR_HI

Bit Default & Field Name (ID): Description Range Access

Destination Status Address (DSTATAR_HI): Pointer from where hardware can 0h 31:0 fetch the destination status information, which is registered in the DSTATn register RW and written out to the DSTATn register location of the LLI before the start of the next block.

5.4.15 DMA Transfer Configuration Low (CFG_LO0)—Offset 840h

NOTE: CFG_LO0 is for DMA Channel 0. The same register definition, CFG_LO1, is available for Channel 1 at address 898h. CFG_LO0(CH0): offset 840h CFG_LO1(CH1): offset 898h This register contains fields that configure the DMA transfer. The channel configuration register remains fixed for all blocks of a multi-block transfer. This Register should be programmed to enabling the channel

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 203h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000001000000011 RSVD RSVD RSVD CH_SUSP CH_DRAIN ALL_NP_WR SS_UPD_EN DS_UPD_EN FIFO_EMPTY DST_OPT_BL SRC_OPT_BL DST_HS_POL SRC_HS_POL RELOAD_DST RELOAD_SRC CTL_HI_UPD_EN HSHAKE_NP_WR DST_BURST_ALIGN SRC_BURST_ALIGN

Bit Default & Field Name (ID): Description Range Access

0h RELOAD_DST: Automatic Destination Reload. The DARn register can be 31 automatically reloaded from its initial value at the end of every block for multi-block RW transfers. A new block transfer is then initiated.

0h RELOAD_SRC: Automatic Source Reload. The SARx register can be automatically 30 reloaded from its initial value at the end of every block for multi-block transfers. A RW new block transfer is then initiated.

0h 29:22 Reserved. RO

332219-002 351 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

Bit Default & Field Name (ID): Description Range Access

SRC_OPT_BL: Optimize Source Burst Length : 0h 0 = Writes will use only BL=1 or BL=(2 ^ SRC_MSIZE) 21 RW 1 = Writes will use (1 <= BL <= (2 ^ SRC_MSIZE)) *** This bit should be set to (0) if Source HW-Handshake is enabled

DST_OPT_BL: Optimize Destination Burst Length : 0h 20 0 = Writes will use only BL=1 or BL=(2 ^ DST_MSIZE) RW 1 = Writes will use (1 <= BL <= (2 ^ DST_MSIZE)) *** This bit should be set to (0) if Destination HW-Handshake is enabled

0h SRC_HS_POL: Source Handshaking Interface Polarity. 19 0 = Active high RW 1 = Active low

0h DST_HS_POL: Destination Handshaking Interface Polarity. 18 0 = Active high RW 1 = Active low

0h 17:11 Reserved. RO

0h CH_DRAIN: Forces channel FIFO to drain while in suspension. This bit has effect 10 RW only when CH_SUSPEND ia asserted

FIFO_EMPTY: Indicates if there is data left in the channel FIFO. Can be used in 1h conjunction with CFGx.CH_SUSP to cleanly disable a channel. 9 RO 1 = Channel FIFO empty 0 = Channel FIFO not empty

CH_SUSP: Channel Suspend. Suspends all DMA data transfers from the source until this bit is cleared. There is no guarantee that the current transaction will complete. 0h Can also be used in conjunction with CFGx.FIFO_EMPTY to cleanly disable a channel 8 RW without losing any data. 0 = Not suspended. 1 = Suspend DMA transfer from the source.

SS_UPD_EN: Source Status Update Enable. Source status information is fetched 0h only from the location pointed to by the SSTATARn register, stored in the SSTATn 7 RW register and written out to the SSTATn location of the LLI if SS_UPD_EN is high. This bit is ignored if (LLP_EN == 0) or (LLP_WB_EN == 0)

DS_UPD_EN: Destination Status Update Enable. Destination status information is 0h 6 fetched only from the location pointed to by the DSTATARn register, stored in the RW DSTATn register and written out to the DSTATn location of the LLI if DS_UPD_EN is high. This bit is ignored if (LLP_EN == 0) or (LLP_WB_EN == 0)

0h CTL_HI_UPD_EN: CTL_HI Update Enable. If set, the CTL_HI register is written out 5 to the CTL_HIn location of the LLI. This bit is ignored if (LLP_EN == 0) or RW (LLP_WB_EN == 0)

0h 4 Reserved. RO

HSHAKE_NP_WR: 0x1 : Issues Non-Posted writes on HW-Handshake on DMA Write

0h Port 3 0x0 : Issues Posted writes on HW-Handshake on DMA Write Port (Except end-of-block RW writes which will be Non-Posted) This bit must be set to 1 for proper operation

0h ALL_NP_WR: 0x1 : Forces ALL writes to be Non-Posted on DMA Write Port 2 0x0 : Non-Posted Writes will only be used at end of block transfers and in HW- RW Handshake (if HW_NP_WR=1); for all other cases, Posted Writes will be used.

1h SRC_BURST_ALIGN: 0x1 : SRC Burst Transfers are broken at a Burst Length 1 aligned boundary RW 0x0 : SRC Burst Transfers are not broken at a Burst Length aligned boundary

1h DST_BURST_ALIGN: 0x1 : DST Burst Transfers are broken at a Burst Length 0 aligned boundary RW 0x0 : DST Burst Transfers are not broken at a Burst Length aligned boundary

5.4.16 DMA Transfer Configuration High (CFG_HI0)—Offset 844h

NOTE: CFG_HI0 is for DMA Channel 0. The same register definition, CFG_HI1, is available for Channel 1 at address 89Ch. CFG_HI0(CH0): offset 844h

352 332219-002

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CFG_HI1(CH1): offset 89Ch This register contains fields that configure the DMA transfer. The channel configuration register remains fixed for all blocks of a multi-block transfer. This Register should be programmed to enabling the channel

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD DST_PER SRC_PER RD_ISSUE_THD WR_ISSUE_THD

Bit Default & Field Name (ID): Description Range Access

0h 31:28 Reserved. RO

0h WR_ISSUE_THD: Write Issue Threshold. Used to relax the issue criterion for Writes. 27:18 Value ranges from 0 to (2^10-1 = 1023) but should not exceed maximum Write RW burst size = (2 ^ DST_MSIZE)*TW.

0h RD_ISSUE_THD: Read Issue Threshold. Used to relax the issue criterion for Reads. 17:8 Value ranges from 0 to (2^10-1 = 1023) but should not exceed maximum Read burst RW size = (2 ^ SRC_MSIZE)*TW.

DST_PER: Destination Peripheral ID : Assigns a hardware handshaking interface (0 - 15) to the destination of channel n. The channel can then communicate with the 0h destination peripheral connected to that interface through the assigned hardware 7:4 handshaking interface. RW NOTE: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface.

SRC_PER: Source Peripheral ID : Assigns a hardware handshaking interface (0 - 15) to the source of channel n. The channel can then communicate with the source 0h peripheral connected to that interface through the assigned hardware handshaking 3:0 interface. RW NOTE: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface.

5.4.17 Source Gather (SGR0)—Offset 848h

NOTE: SGR0 is for DMA Channel 0. The same register definition, SGR1, is available for Channel 1 at address 8A0h. SGR0(CH0): offset 848h SGR1(CH1): offset 8A0h The Source Gather register contains two fields: Source gather count field (SGRx.SGC). Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH between successive gather intervals. This is defined as a gather boundary. Source gather interval field (SGRx.SGI). Specifies the source address increment/decrement in multiples of CTLx.SRC_TR_WIDTH on a gather boundary when gather mode is enabled

332219-002 353 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

for the source transfer. The CTLx.SINC field controls whether the address increments or decrements. When the CTLx.SINC field indicates a fixed-address control, then the address remains constant throughout the transfer and the SGRx register is ignored.

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 SGI SGC

Bit Default & Field Name (ID): Description Range Access

0h SGC (SGC): Source gather count. Source contiguous transfer count between 31:20 RW successive gather boundaries.

0h SGI (SGI): Source gather interval. 19:0 RW

5.4.18 Destination Scatter (DSR0)—Offset 850h

NOTE: DSR0 is for DMA Channel 0. The same register definition, DSR1, is available for Channel 1 at address 8A8h. DSR0(CH0): offset 850h DSR1(CH1): offset 8A8h The Destination Scatter register contains two fields: Destination scatter count field (DSRx.DSC) . Specifies the number of contiguous destination transfers of CTLx.DST_TR_WIDTH between successive scatter boundaries. Destination scatter interval field (DSRx.DSI) . Specifies the destination address increment/decrement in multiples of CTLx.DST_TR_WIDTH on a scatter boundary when scatter mode is enabled for the destination transfer. The CTLx.DINC field controls whether the address increments or decrements. When the CTLx.DINC field indicates a fixed address control, then the address remains constant throughout the transfer and the DSRx register is ignored.

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 DSI DSC

354 332219-002

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Bit Default & Field Name (ID): Description Range Access

0h DSC (DSC): Destination scatter count. Destination contiguous transfer count 31:20 RW between successive scatter boundaries.

0h DSI (DSI): Destination scatter interval. 19:0 RW

5.4.19 Raw Interrupt Status (RawTfr)—Offset AC0h

Interrupt events are stored in these Raw Interrupt Status registers before masking: RawBlock, RawDstTran, RawErr, RawSrcTran, and RawTfr. Each Raw Interrupt Status register has a bit allocated per channel, for example, RawTfr(2) is the Channel 2 raw transfer complete interrupt. Each bit in these registers is cleared by writing a 1 to the corresponding location in the ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran, ClearErr registers The following RAW registers are available in the DMA RawTfr - Raw Status for Transfer Interrupts RawBlock - Raw Status for Block Interrupts Register RawSrcTran - Raw Status for Source Transaction Interrupts Register RawDstTran - Raw Status for Destination Transaction Interrupts Register RawErr - Raw Status for Error Interrupts Register

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RAW RSVD

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h Raw Interrupt Status (RAW): Bit0 for channel 0 and bit 1 for channel 1. 1:0 RO

5.4.20 Raw Status for Block Interrupts (RawBlock)—Offset AC8h

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

332219-002 355 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RAW RSVD

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h Raw interrupt status (RAW): Bit 0 for channel 0 and bit 1 for channel 1. 1:0 RO

5.4.21 Raw Status for Source Transaction Interrupts (RawSrcTran)—Offset AD0h

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RAW RSVD

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h Raw interrupt status (RAW): Bit 0 for channel 0 and bit 1 for channel 1. 1:0 RO

5.4.22 Raw Status for Destination Transaction Interrupts (RawDstTran)—Offset AD8h

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

356 332219-002

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3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RAW RSVD

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h RAW: Bit 0 for channel 0 and bit 1 for channel 1. 1:0 RO

5.4.23 Raw Status for Error Interrupts (RawErr)—Offset AE0h

Interrupt events are stored in these Raw Interrupt Status registers before masking: RawBlock, RawDstTran, RawErr, RawSrcTran, and RawTfr. Each Raw Interrupt Status register has a bit allocated per channel, for example, RawTfr(2) is the Channel 2 raw transfer complete interrupt. Each bit in these registers is cleared by writing a 1 to the corresponding location in the ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran, ClearErr registers The following RAW registers are available in the DMA RawTfr - Raw Status for Transfer Interrupts RawBlock - Raw Status for Block Interrupts Register RawSrcTran - Raw Status for Source Transaction Interrupts Register RawDstTran - Raw Status for Destination Transaction Interrupts Register RawErr - Raw Status for Error Interrupts Register

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RAW RSVD

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h Raw Interrupt Status (RAW): Bit 0 for channel 0 and bit 1 for channel 1. 1:0 RO

332219-002 357 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

5.4.24 Interrupt Status (StatusTfr)—Offset AE8h

All interrupt events from all channels are stored in these Interrupt Status registers after masking: statusBlock, StatusDstTran, StatusErr, StatusSrcTran, and StatusTfr. Each Interrupt Status register has a bit allocated per channel, for example, StatusTfr(2) is the Channel 2 status transfer complete interrupt. The contents of these registers are used to generate the interrupt signals (int or int_n bus, depending on interrupt polarity) leaving the DMA.

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD STATUS

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h Interrupt Status (STATUS): Bit 0 for channel 0 and bit 1 for channel 1. 1:0 RO

5.4.25 Status for Block Interrupts (StatusBlock)—Offset AF0h

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD STATUS

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Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h Interrupt status (STATUS): Bit 0 for channel 0 and bit 1 for channel 1. 1:0 RO

5.4.26 Status for Source Transaction Interrupts (StatusSrcTran)—Offset AF8h

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD STATUS

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h Interrupt status (STATUS): Bit 0 is for channel 0 and bit 1 is for channel 1. 1:0 RO

5.4.27 Status for Destination Transaction Interrupts (StatusDstTran)—Offset B00h

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD STATUS

332219-002 359 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h Interrupt status (STATUS): Bit 0 is for channel 0 and bit 1 is for channel 1. 1:0 RO

5.4.28 Status for Error Interrupts (StatusErr)—Offset B08h

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD STATUS

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h Interrupt status (STATUS): Bit 0 is for channel 0 and bit 1 is for channel 1. 1:0 RO

5.4.29 Mask for Transfer Interrupts (MaskTfr)—Offset B10h

The contents of the Raw Status registers are masked with the contents of the Mask registers: MaskBlock, MaskDstTran, MaskErr, MaskSrcTran, and MaskTfr. Each Interrupt Mask register has a bit allocated per channel, for example, MaskTfr(2) is the mask bit for the Channel 2 transfer complete interrupt. When the source peripheral of DMA channel i is memory, then the source transaction complete interrupt, MaskSrcTran(i), must be masked to prevent an erroneous triggering of an interrupt on the int_combined signal. Similarly, when the destination peripheral of DMA channel i is memory, then the destination transaction complete interrupt, MaskDstTran(i), must be masked to prevent an erroneous triggering of an interrupt on the int_combined(_n) signal. A channel INT_MASK bit will be written only if the corresponding mask write enable bit in the INT_MASK_WE field is asserted on the same OCP write transfer. This allows software to set a mask bit without performing a read-modified write operation. For example, writing hex 01x1 to the MaskTfr register writes a 1 into MaskTfr(0), while MaskTfr(7:1) remains unchanged. Writing hex 00xx leaves MaskTfr(7:0) unchanged. Writing a 1 to any bit in these registers unmasks the corresponding interrupt, thus allowing the DMA to set the appropriate bit in the Status registers and int_* port signals.

Access Method

360 332219-002

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Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD INT_MASK INT_MASK_WE

Bit Default & Field Name (ID): Description Range Access

0h 31:10 Reserved. RO

0h Interrupt Mask Write Enable (INT_MASK_WE): 0 = write disabled 9:8 WO 1 = write enabled

0h 7:2 Reserved. RO

0h Interrupt mask (INT_MASK): 0-mask 1:0 RW 1-unmask

5.4.30 Mask for Block Interrupts (MaskBlock)—Offset B18h

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD INT_MASK INT_MASK_WE

332219-002 361 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

Bit Default & Field Name (ID): Description Range Access

0h 31:10 Reserved. RO

0h Interrupt Mask Write Enable (INT_MASK_WE): 0 = write disabled 9:8 WO 1 = write enabled

0h 7:2 Reserved. RO

0h Interrupt mask (INT_MASK): 0-mask 1:0 RW 1-unmask

5.4.31 Mask for Source Transaction Interrupts (MaskSrcTran)— Offset B20h

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD INT_MASK INT_MASK_WE

Bit Default & Field Name (ID): Description Range Access

0h 31:10 Reserved. RO

0h Interrupt Mask Write Enable (INT_MASK_WE): 0 = write disabled 9:8 WO 1 = write enabled

0h 7:2 Reserved. RO

0h Interrupt mask (INT_MASK): 0-mask 1:0 RW 1-unmask

5.4.32 Mask for Destination Transaction Interrupts (MaskDstTran)—Offset B28h

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

362 332219-002

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3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD INT_MASK INT_MASK_WE

Bit Default & Field Name (ID): Description Range Access

0h 31:10 Reserved. RO

0h Interrupt Mask Write Enable (INT_MASK_WE): 0 = write disabled 9:8 WO 1 = write enabled

0h 7:2 Reserved. RO

0h Interrupt mask (INT_MASK): 0-mask 1:0 RW 1-unmask

5.4.33 Mask for Error Interrupts (MaskErr)—Offset B30h

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD INT_MASK INT_MASK_WE

Bit Default & Field Name (ID): Description Range Access

0h 31:10 Reserved. RO

0h Interrupt Mask Write Enable (INT_MASK_WE): 0 = write disabled 9:8 WO 1 = write enabled

0h 7:2 Reserved. RO

0h Interrupt mask (INT_MASK): 0-mask 1:0 RW 1-unmask

332219-002 363 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

5.4.34 Clear for Transfer Interrupts (ClearTfr)—Offset B38h

Each bit in the Raw Status and Status registers is cleared on the same cycle by writing a 1 to the corresponding location in the Clear registers: ClearBlock, ClearDstTran, ClearErr, ClearSrcTran, and ClearTfr. Each Interrupt Clear register has a bit allocated per channel, for example, ClearTfr(2) is the clear bit for the Channel 2 transfer complete interrupt. Writing a 0 has no effect. These registers are not readable.

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD CLEAR

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h Interrupt Clear (CLEAR): 0 = no effect 1:0 WO 1 = clear interrupt

5.4.35 Clear for Block Interrupts (ClearBlock)—Offset B40h

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD CLEAR

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h Interrupt Clear (CLEAR): 0 = no effect 1:0 WO 1 = clear interrupt

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5.4.36 Clear for Source Transaction Interrupts (ClearSrcTran)— Offset B48h

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD CLEAR

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h Interrupt clear (CLEAR): 0 = no effect 1:0 WO 1 = clear interrupt

5.4.37 Clear for Destination Transaction Interrupts (ClearDstTran)—Offset B50h

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD CLEAR

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h Interrupt Clear (CLEAR): 0 = no effect 1:0 WO 1 = clear interrupt

5.4.38 Clear for Error Interrupts (ClearErr)—Offset B58h

Access Method

332219-002 365 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD CLEAR

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

0h Interrupt clear (CLEAR): 0 = no effect 1:0 WO 1 = clear interrupt

5.4.39 Combined Status register (StatusInt)—Offset B60h

The contents of each of the five Status registers StatusTfr, StatusBlock, StatusSrcTran, StatusDstTran,StatusErr is ORed to produce a single bit for each interrupt type in the Combined Status register (StatusInt). This register is read-only.

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 TFR ERR DSTT SRCT RSVD BLOCK

Bit Default & Field Name (ID): Description Range Access

0h 31:5 Reserved. RO

0h ERR (ERR): OR of the contents of StatusErr register. 4 RO

0h DSTT (DSTT): OR of the contents of StatusDst register. 3 RO

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Bit Default & Field Name (ID): Description Range Access

0h SRCT (SRCT): OR of the contents of StatusSrcTran register 2 RO

0h Block (BLOCK): OR of the contents of StatusBlock register. 1 RO

0h TFR (TFR): OR of the contents of StatusTfr register. 0 RO

5.4.40 DMA Configuration (DmaCfgReg)—Offset B98h

This register is used to enable the DMA, which must be done before any channel activity can begin. If the global channel enable bit is cleared while any channel is still active, then DmaCfgReg.DMA_EN still returns 1 to indicate that there are channels still active until hardware has terminated all activity on all channels, at which point the DmaCfgReg.DMA_EN bit returns 0.

Access Method

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD DMA_EN

Bit Default & Field Name (ID): Description Range Access

0h 31:1 Reserved. RO

0h DMA Enable (DMA_EN): 0 = DMA Disabled 0 RW 1 = DMA Enabled

5.4.41 DMA Channel Enable (ChEnReg)—Offset BA0h

This is the DMA Channel Enable Register. If software needs to set up a new channel, then it can read this register in order to find out which channels are currently inactive, it can then enable an inactive channel with the required priority. All bits of this register are cleared to 0 when the global DMA channel enable bit, DmaCfgReg(0), is 0. When the global channel enable bit is 0, then a write to the ChEnReg register is ignored and a read will always read back 0. The channel enable bit, ChEnReg.CH_EN, is written only if the corresponding channel write enable bit, ChEnReg.CH_EN_WE, is asserted on the same OCP write transfer. For example, writing hex 01x1 writes a 1 into ChEnReg(0), while ChEnReg(7:1) remains unchanged. Writing hex 00xx leaves ChEnReg(7:0) unchanged. Note that a read-modified write is not required.

Access Method

332219-002 367 I2C Interface (D25: F0/F1, D21:F0/F1/F2/F3)

Type: MEM Register Device: 21 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD CH_EN CH_EN_WE

Bit Default & Field Name (ID): Description Range Access

0h 31:10 Reserved. RO

0h CH_EN_WE: Channel enable write enable. 9:8 WO

0h 7:2 Reserved. RO

Channel Enable (CH_EN): Enables/Disables the channel. Setting this bit enables a channel, clearing this bit disables the channel. 0 = Disable the Channel 0h 1 = Enable the Channel 1:0 RW The ChEnReg.CH_EN bit is automatically cleared by hardware to disable the channel after the last OCP transfer of the DMA transfer to the destination has completed. Software can therefore poll this bit to determine when this channel is free for a new DMA transfer.

§ §

368 332219-002

GPIO for SKL PCH-H

6 GPIO for SKL PCH-H

6.1 GPIO Community 0 Registers Summary

Community 0 Registers are for GPP_A and GPP_B groups.

Table 6-1. Summary of GPIO Community 0 Registers

Offset Offset Default Register Name (ID)—Offset Start End Value

8h Bh Family Base Address (FAMBAR)—Offset 8h 300h

Ch Fh Pad Base Address (PADBAR)—Offset Ch 400h

10h 13h Miscellaneous Configuration (MISCCFG)—Offset 10h 43200h

20h 23h Pad Ownership (PAD_OWN_GPP_A_0)—Offset 20h 0h

24h 27h Pad Ownership (PAD_OWN_GPP_A_1)—Offset 24h 0h

28h 2Bh Pad Ownership (PAD_OWN_GPP_A_2)—Offset 28h 0h

30h 33h Pad Ownership (PAD_OWN_GPP_B_0)—Offset 30h 0h

34h 37h Pad Ownership (PAD_OWN_GPP_B_1)—Offset 34h 0h

38h 3Bh Pad Ownership (PAD_OWN_GPP_B_2)—Offset 38h 0h

A0h A3h Pad Configuration Lock (PADCFGLOCK_GPP_A)—Offset A0h 0h

A4h A7h Pad Configuration Lock (PADCFGLOCKTX_GPP_A)—Offset A4h 0h

A8h ABh Pad Configuration Lock (PADCFGLOCK_GPP_B)—Offset A8h 0h

ACh AFh Pad Configuration Lock (PADCFGLOCKTX_GPP_B)—Offset ACh 0h

D0h D3h Host Software Pad Ownership (HOSTSW_OWN_GPP_A)—Offset D0h 0h

D4h D7h Host Software Pad Ownership (HOSTSW_OWN_GPP_B)—Offset D4h 0h

100h 103h GPI Interrupt Status (GPI_IS_GPP_A)—Offset 100h 0h

104h 107h GPI Interrupt Status (GPI_IS_GPP_B)—Offset 104h 0h

120h 123h GPI Interrupt Enable (GPI_IE_GPP_A)—Offset 120h 0h

124h 127h GPI Interrupt Enable (GPI_IE_GPP_B)—Offset 124h 0h

140h 143h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A)—Offset 140h 0h

144h 147h GPI General Purpose Events Status (GPI_GPE_STS_GPP_B)—Offset 144h 0h

160h 163h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A)—Offset 160h 0h

164h 167h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_B)—Offset 164h 0h

184h 187h SMI Status (GPI_SMI_STS_GPP_B)—Offset 184h 0h

1A4h 1A7h SMI Enable (GPI_SMI_EN_GPP_B)—Offset 1A4h 0h

1C4h 1C7h NMI Status (GPI_NMI_STS_GPP_B)—Offset 1C4h 0h

1E4h 1E7h NMI Enable (GPI_NMI_EN_GPP_B)—Offset 1E4h 0h

4400xx00h See 400h 403h Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_0)—Offset 400h Register for xx value

404h 407h Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_0)—Offset 404h 18h

332219-002 369 GPIO for SKL PCH-H

Table 6-1. Summary of GPIO Community 0 Registers (Continued)

Offset Offset Default Register Name (ID)—Offset Start End Value

4400xx00h See 408h 40Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_1)—Offset 408h Register for xx value

40Ch 40Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_1)—Offset 40Ch See register

4400xx00h See 410h 413h Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_2)—Offset 410h Register for xx value

414h 417h Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_2)—Offset 414h See register

4400xx00h See 418h 41Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_3)—Offset 418h Register for xx value

41Ch 41Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_3)—Offset 41Ch See register

4400xx00h See 420h 423h Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_4)—Offset 420h Register for xx value

424h 427h Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_4)—Offset 424h See register

4400xx00h See 428h 42Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_5)—Offset 428h Register for xx value

42Ch 42Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_5)—Offset 42Ch See register

4400xx00h See 430h 433h Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_6)—Offset 430h Register for xx value

434h 437h Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_6)—Offset 434h See register

4400xx00h See 438h 43Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_7)—Offset 438h Register for xx value

43Ch 43Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_7)—Offset 43Ch See register

4400xx00h See 440h 443h Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_8)—Offset 440h Register for xx value

444h 447h Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_8)—Offset 444h See register

4400xx00h See 448h 44Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_9)—Offset 448h Register for xx value

44Ch 44Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_9)—Offset 44Ch See register

4400xx00h See 450h 453h Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_10)—Offset 450h Register for xx value

454h 457h Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_10)—Offset 454h See register

4400xx00h See 458h 45Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_11)—Offset 458h Register for xx value

370 332219-002

GPIO for SKL PCH-H

Table 6-1. Summary of GPIO Community 0 Registers (Continued)

Offset Offset Default Register Name (ID)—Offset Start End Value

45Ch 45Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_11)—Offset 45Ch See register

4400xx00h See 460h 463h Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_12)—Offset 460h Register for xx value

464h 467h Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_12)—Offset 464h See register

4400xx00h See 468h 46Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_13)—Offset 468h Register for xx value

46Ch 46Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_13)—Offset 46Ch See register

4400xx00h See 470h 473h Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_14)—Offset 470h Register for xx value

474h 477h Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_14)—Offset 474h See register

4400xx00h See 478h 47Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_15)—Offset 478h Register for xx value

47Ch 47Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_15)—Offset 47Ch See register

4400xx00h See 480h 483h Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_16)—Offset 480h Register for xx value

484h 487h Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_16)—Offset 484h See register

4400xx00h See 488h 48Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_17)—Offset 488h Register for xx value

48Ch 48Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_17)—Offset 48Ch See register

4400xx00h See 490h 493h Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_18)—Offset 490h Register for xx value

494h 497h Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_18)—Offset 494h See register

4400xx00h See 498h 49Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_19)—Offset 498h Register for xx value

49Ch 49Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_19)—Offset 49Ch See register

4400xx00h See 4A0h 4A3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_20)—Offset 4A0h Register for xx value

4A4h 4A7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_20)—Offset 4A4h See register

4400xx00h See 4A8h 4ABh Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_21)—Offset 4A8h Register for xx value

4ACh 4AFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_21)—Offset 4ACh See register

332219-002 371 GPIO for SKL PCH-H

Table 6-1. Summary of GPIO Community 0 Registers (Continued)

Offset Offset Default Register Name (ID)—Offset Start End Value

4400xx00h See 4B0h 4B3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_22)—Offset 4B0h Register for xx value

4B4h 4B7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_22)—Offset 4B4h See register

4400xx00h See 4B8h 4BBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_23)—Offset 4B8h Register for xx value

4BCh 4BFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_23)—Offset 4BCh See register

4400xx00h See 4C0h 4C3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_0)—Offset 4C0h Register for xx value

4C4h 4C7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_0)—Offset 4C4h See register

4400xx00h See 4C8h 4CBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_1)—Offset 4C8h Register for xx value

4CCh 4CFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_1)—Offset 4CCh See register

4400xx00h See 4D0h 4D3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_2)—Offset 4D0h Register for xx value

4D4h 4D7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_2)—Offset 4D4h See register

4400xx00h See 4D8h 4DBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_3)—Offset 4D8h Register for xx value

4DCh 4DFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_3)—Offset 4DCh See register

4400xx00h See 4E0h 4E3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_4)—Offset 4E0h Register for xx value

4E4h 4E7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_4)—Offset 4E4h See register

4400xx00h See 4E8h 4EBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_5)—Offset 4E8h Register for xx value

4ECh 4EFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_5)—Offset 4ECh See register

4400xx00h See 4F0h 4F3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_6)—Offset 4F0h Register for xx value

4F4h 4F7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_6)—Offset 4F4h See register

4400xx00h See 4F8h 4FBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_7)—Offset 4F8h Register for xx value

4FCh 4FFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_7)—Offset 4FCh See register

4400xx00h See 500h 503h Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_8)—Offset 500h Register for xx value

372 332219-002

GPIO for SKL PCH-H

Table 6-1. Summary of GPIO Community 0 Registers (Continued)

Offset Offset Default Register Name (ID)—Offset Start End Value

504h 507h Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_8)—Offset 504h See register

4400xx00h See 508h 50Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_9)—Offset 508h Register for xx value

50Ch 50Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_9)—Offset 50Ch See register

4400xx00h See 510h 513h Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_10)—Offset 510h Register for xx value

514h 517h Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_10)—Offset 514h See register

4400xx00h See 518h 51Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_11)—Offset 518h Register for xx value

51Ch 51Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_11)—Offset 51Ch See register

4400xx00h See 520h 523h Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_12)—Offset 520h Register for xx value

524h 527h Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_12)—Offset 524h See register

4400xx00h See 528h 52Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_13)—Offset 528h Register for xx value

52Ch 52Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_13)—Offset 52Ch See register

4400xx00h See 530h 533h Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_14)—Offset 530h Register for xx value

534h 537h Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_14)—Offset 534h See register

4400xx00h See 538h 53Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_15)—Offset 538h Register for xx value

53Ch 53Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_15)—Offset 53Ch See register

4400xx00h See 540h 543h Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_16)—Offset 540h Register for xx value

544h 547h Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_16)—Offset 544h See register

4400xx00h See 548h 54Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_17)—Offset 548h Register for xx value

54Ch 54Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_17)—Offset 54Ch See register

4400xx00h See 550h 553h Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_18)—Offset 550h Register for xx value

554h 557h Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_18)—Offset 554h See register

332219-002 373 GPIO for SKL PCH-H

Table 6-1. Summary of GPIO Community 0 Registers (Continued)

Offset Offset Default Register Name (ID)—Offset Start End Value

4400xx00h See 558h 55Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_19)—Offset 558h Register for xx value

55Ch 55Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_19)—Offset 55Ch See register

4400xx00h See 560h 563h Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_20)—Offset 560h Register for xx value

564h 567h Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_20)—Offset 564h See register

4400xx00h See 568h 56Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_21)—Offset 568h Register for xx value

56Ch 56Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_21)—Offset 56Ch See register

4400xx00h See 570h 573h Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_22)—Offset 570h Register for xx value

574h 577h Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_22)—Offset 574h See register

4400xx00h See 578h 57Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_23)—Offset 578h Register for xx value

57Ch 57Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_23)—Offset 57Ch See register

6.1.1 Family Base Address (FAMBAR)—Offset 8h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 300h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000001100000000 RSVD FAMBAR

Bit Default & Field Name (ID): Description Range Access

0h 31:16 Reserved. RO

Family Base Address (FAMBAR): This field provides the starting byte-align 300h address of Family0 register sets. It is meant for software to discover from where the 15:0 RO very first Family register (i.e. Family0 register) starts to compute the next Families address offsets.

374 332219-002

GPIO for SKL PCH-H

6.1.2 Pad Base Address (PADBAR)—Offset Ch

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 400h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000010000000000 RSVD PADBAR

Bit Default & Field Name (ID): Description Range Access

0h 31:16 Reserved. RO

400h Pad Base Address (PADBAR): This field provides the starting byte-align address of 15:0 Pad0 register sets. It is meant for software to discover from where the very first Pad RO register (i.e. Pad0 register) starts to compute the next Pad address offsets.

6.1.3 Miscellaneous Configuration (MISCCFG)—Offset 10h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 43200h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000001000011001000000000 RSVD RSVD RSVD GPDLCGEN GPDPCGEN GPE0_DW2 GPE0_DW1 GPE0_DW0 GPIO_DRIVER_IRQ_ROUTE

332219-002 375 GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h 31:20 Reserved. RO

GPIO Group to GPE_DW0 assignment encoding (GPE0_DW2): This register assigns a specific GPIO Group to the ACPI GPE0[95:64]. The selected GPIO group will be mapped to lower bits of the GPE register 0h = GPP_A[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 1h = GPP_B[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 4h 2h = GPP_C[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 19:16 3h = GPP_D[23:0] mapped to GPE[87:64]; GPE[95:88] not used. RW 4h = GPP_E[12:0] mapped to GPE[76:64]; GPE[95:77] not used. 5h = GPP_F[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 6h = GPP_G[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 7h = GPP_H[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 8h = GPP_I[10:0] mapped to GPE[74:64]; GPE[95:75] not used. 9h = GPD[11:0] mapped to GPE[75:64]; GPE[95:76] not used.

GPIO Group to GPE_DW0 assignment encoding (GPE0_DW1): This register assigns a specific GPIO Group to the ACPI GPE0[63:32]. The selected GPIO group will be mapped to lower bits of the GPE register 0h = GPP_A[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 1h = GPP_B[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 3h 2h = GPP_C[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 15:12 3h = GPP_D[23:0] mapped to GPE[55:32]; GPE[63:56] not used. RW 4h = GPP_E[12:0] mapped to GPE[44:32]; GPE[63:45] not used. 5h = GPP_F[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 6h = GPP_G[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 7h = GPP_H[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 8h = GPP_I[10:0] mapped to GPE[42:32]; GPE[63:43] not used. 9h = GPD[11:0] mapped to GPE[43:32]; GPE[63:44] not used.

GPIO Group to GPE_DW0 assignment encoding (GPE0_DW0): This register assigns a specific GPIO Group to the ACPI GPE0[31:0]. The selected GPIO group will be mapped to lower bits of the GPE register 0h = GPP_A[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 1h = GPP_B[23:0] mapped to GPE[23:0]; GPE[31:24] not used.

2h 2h = GPP_C[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 11:8 3h = GPP_D[23:0] mapped to GPE[23:0]; GPE[31:24] not used. RW 4h = GPP_E[12:0] mapped to GPE[12:0]; GPE[31:13] not used. 5h = GPP_F[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 6h = GPP_G[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 7h = GPP_H[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 8h = GPP_I[10:0] mapped to GPE[10:0]; GPE[31:11] not used. 9h = GPD[11:0] mapped to GPE[11:0]; GPE[31:12] not used.

0h 7:4 Reserved. RO

GPIO Driver IRQ Route (GPIO_DRIVER_IRQ_ROUTE): Specifies the APIC IRQ 0h globally for all pads within the current community (GPI_IS with corresponding GPI_IE 3 enable). RW 0 = IRQ14 1 = IRQ15

0h 2 Reserved. RO

GPIO Dynamic Partition Clock Gating Enable (GPDPCGEN): Specifies whether 0h the GPIO Community should take part in partition clock gating 1 RW 0 = Disable participation in dynamic partition clock gating 1 = Enable participation in dynamic partition clock gating

GPIO Dynamic Local Clock Gating Enable (GPDLCGEN): Specifies whether the 0h GPIO Community should perform local clock gating. 0 RW 0 = Disable dynamic local clock gating 1 = Enable dynamic local clock gating

6.1.4 Pad Ownership (PAD_OWN_GPP_A_0)—Offset 20h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

376 332219-002

GPIO for SKL PCH-H

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD PAD_OWN_GPP_A_7 PAD_OWN_GPP_A_6 PAD_OWN_GPP_A_5 PAD_OWN_GPP_A_4 PAD_OWN_GPP_A_3 PAD_OWN_GPP_A_2 PAD_OWN_GPP_A_1 PAD_OWN_GPP_A_0

Bit Default & Field Name (ID): Description Range Access

0h 31:30 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_A_7): Same description as bit 0, except that 29:28 RO the bit field applies to GPP_A7.

0h 27:26 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_A_6): Same description as bit 0, except that 25:24 RO the bit field applies to GPP_A6.

0h 23:22 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_A_5): Same description as bit 0, except that 21:20 RO the bit field applies to GPP_A5.

0h 19:18 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_A_4): Same description as bit 0, except that 17:16 RO the bit field applies to GPP_A4.

0h 15:14 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_A_3): Same description as bit 0, except that 13:12 RO the bit field applies to GPP_A3.

0h 11:10 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_A_2): Same description as bit 0, except that 9:8 RO the bit field applies to GPP_A2.

0h 7:6 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_A_1): Same description as bit 0, except that 5:4 RO the bit field applies to GPP_A1.

0h 3:2 Reserved. RO

Pad Ownership (PAD_OWN_GPP_A_0): 00 = Host GPIO ACPI Mode or GPIO Driver Mode. Host software (ACPI or GPIO Driver) has ownership of the pad. In Host GPIO Driver Mode (refer to HOSTSW_OWN), GPIO input event update is limited to 0h GPI_STS update only. Otherwise in Host ACPI Mode, updates are limited to 1:0 RO GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. 01 = ME GPIO Mode. ME has ownership of the pad. 10 = ISH GPIO Mode.ME has ownership of the pad 11 = Reserved

332219-002 377 GPIO for SKL PCH-H

6.1.5 Pad Ownership (PAD_OWN_GPP_A_1)—Offset 24h

Same description as PAD_OWN_GPP_A_0, except that this register is for GPP_A[15:8]

6.1.6 Pad Ownership (PAD_OWN_GPP_A_2)—Offset 28h

Same description as PAD_OWN_GPP_A_0, except that this register is for GPP_A[23:16]

6.1.7 Pad Ownership (PAD_OWN_GPP_B_0)—Offset 30h

Same description as PAD_OWN_GPP_A_0, except that this register is for GPP_B[7:0]

6.1.8 Pad Ownership (PAD_OWN_GPP_B_1)—Offset 34h

Same description as PAD_OWN_GPP_A_0, except that this register is for GPP_B[15:8]

6.1.9 Pad Ownership (PAD_OWN_GPP_B_2)—Offset 38h

Same description as PAD_OWN_GPP_A_0, except that this register is for GPP_B[23:16]

6.1.10 Pad Configuration Lock (PADCFGLOCK_GPP_A)—Offset A0h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD PADCFGLOCK_GPP_A_9 PADCFGLOCK_GPP_A_8 PADCFGLOCK_GPP_A_7 PADCFGLOCK_GPP_A_6 PADCFGLOCK_GPP_A_5 PADCFGLOCK_GPP_A_4 PADCFGLOCK_GPP_A_3 PADCFGLOCK_GPP_A_2 PADCFGLOCK_GPP_A_1 PADCFGLOCK_GPP_A_0 PADCFGLOCK_GPP_A_23 PADCFGLOCK_GPP_A_22 PADCFGLOCK_GPP_A_21 PADCFGLOCK_GPP_A_20 PADCFGLOCK_GPP_A_19 PADCFGLOCK_GPP_A_18 PADCFGLOCK_GPP_A_17 PADCFGLOCK_GPP_A_16 PADCFGLOCK_GPP_A_15 PADCFGLOCK_GPP_A_14 PADCFGLOCK_GPP_A_13 PADCFGLOCK_GPP_A_12 PADCFGLOCK_GPP_A_11 PADCFGLOCK_GPP_A_10

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h Pad Config Lock (PADCFGLOCK_GPP_A_23): Applied to GPP_A23. Same 23 RW description as PADCFGLOCK_GPP_A_0

0h Pad Config Lock (PADCFGLOCK_GPP_A_22): Applied to GPP_A22. Same 22 RW description as PADCFGLOCK_GPP_A_0

378 332219-002

GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h Pad Config Lock (PADCFGLOCK_GPP_A_21): Applied to GPP_A21. Same 21 RW description as PADCFGLOCK_GPP_A_0

0h Pad Config Lock (PADCFGLOCK_GPP_A_20): Applied to GPP_A20. Same 20 RW description as PADCFGLOCK_GPP_A_0

0h Pad Config Lock (PADCFGLOCK_GPP_A_19): Applied to GPP_A19. Same 19 RW description as PADCFGLOCK_GPP_A_0

0h Pad Config Lock (PADCFGLOCK_GPP_A_18): Applied to GPP_A18. Same 18 RW description as PADCFGLOCK_GPP_A_0

0h Pad Config Lock (PADCFGLOCK_GPP_A_17): Applied to GPP_A17. Same 17 RW description as PADCFGLOCK_GPP_A_0

0h Pad Config Lock (PADCFGLOCK_GPP_A_16): Applied to GPP_A16. Same 16 RW description as PADCFGLOCK_GPP_A_0

0h Pad Config Lock (PADCFGLOCK_GPP_A_15): Applied to GPP_A15. Same 15 RW description as PADCFGLOCK_GPP_A_0

0h Pad Config Lock (PADCFGLOCK_GPP_A_14): Applied to GPP_A14. Same 14 RW description as PADCFGLOCK_GPP_A_0

0h Pad Config Lock (PADCFGLOCK_GPP_A_13): Applied to GPP_A13. Same 13 RW description as PADCFGLOCK_GPP_A_0

0h Pad Config Lock (PADCFGLOCK_GPP_A_12): Applied to GPP_A12. Same 12 RW description as PADCFGLOCK_GPP_A_0

0h Pad Config Lock (PADCFGLOCK_GPP_A_11): Applied to GPP_A11. Same 11 RW description as PADCFGLOCK_GPP_A_0

0h Pad Config Lock (PADCFGLOCK_GPP_A_10): Applied to GPP_A10. Same 10 RW description as PADCFGLOCK_GPP_A_0

0h Pad Config Lock (PADCFGLOCK_GPP_A_9): Applied to GPP_A9. Same 9 RW description as PADCFGLOCK_GPP_A_0

0h Pad Config Lock (PADCFGLOCK_GPP_A_8): Applied to GPP_A8. Same 8 RW description as PADCFGLOCK_GPP_A_0

0h Pad Config Lock (PADCFGLOCK_GPP_A_7): Applied to GPP_A7. Same 7 RW description as PADCFGLOCK_GPP_A_0

0h Pad Config Lock (PADCFGLOCK_GPP_A_6): Applied to GPP_A6. Same 6 RW description as PADCFGLOCK_GPP_A_0

0h Pad Config Lock (PADCFGLOCK_GPP_A_5): Applied to GPP_A5. Same 5 RW description as PADCFGLOCK_GPP_A_0

0h Pad Config Lock (PADCFGLOCK_GPP_A_4): Applied to GPP_A4. Same 4 RW description as PADCFGLOCK_GPP_A_0

0h Pad Config Lock (PADCFGLOCK_GPP_A_3): Applied to GPP_A3. Same 3 RW description as PADCFGLOCK_GPP_A_0

332219-002 379 GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h Pad Config Lock (PADCFGLOCK_GPP_A_2): Applied to GPP_A2. Same 2 RW description as PADCFGLOCK_GPP_A_0

0h Pad Config Lock (PADCFGLOCK_GPP_A_1): Applied to GPP_A1. Same 1 RW description as PADCFGLOCK_GPP_A_0

Pad Config Lock (PADCFGLOCK_GPP_A_0): Pad Configuration Lock locks specific register fields in the GPP specific registers from being configured. The registers affected become Read-Only and software writes to these registers have no effect. 0 = Unlock 1 = Lock the following register fields as read-only (RO): 0h - Pad Configuration registers (exclude GPIOTXState) 0 RW - GPI_NMI_EN Register (if implemented) - GPI_SMI_EN Register (if implemented) - GPI_GPE_EN Register (if implemented) When PadCfgLock is written from a '1' to a '0' (unlock), a synchronous SMI# is generated if enabled. This ensures that only SMM code can change the above GPIO registers after the lockdown.

6.1.11 Pad Configuration Lock (PADCFGLOCKTX_GPP_A)—Offset A4h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD PADCFGLOCKTX_GPP_A_9 PADCFGLOCKTX_GPP_A_8 PADCFGLOCKTX_GPP_A_7 PADCFGLOCKTX_GPP_A_6 PADCFGLOCKTX_GPP_A_5 PADCFGLOCKTX_GPP_A_4 PADCFGLOCKTX_GPP_A_3 PADCFGLOCKTX_GPP_A_2 PADCFGLOCKTX_GPP_A_1 PADCFGLOCKTX_GPP_A_0 PADCFGLOCKTX_GPP_A_23 PADCFGLOCKTX_GPP_A_22 PADCFGLOCKTX_GPP_A_21 PADCFGLOCKTX_GPP_A_20 PADCFGLOCKTX_GPP_A_19 PADCFGLOCKTX_GPP_A_18 PADCFGLOCKTX_GPP_A_17 PADCFGLOCKTX_GPP_A_16 PADCFGLOCKTX_GPP_A_15 PADCFGLOCKTX_GPP_A_14 PADCFGLOCKTX_GPP_A_13 PADCFGLOCKTX_GPP_A_12 PADCFGLOCKTX_GPP_A_11 PADCFGLOCKTX_GPP_A_10

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_23): Applied to GPP_A23. 23 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_22): Applied to GPP_A22. 22 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_21): Applied to GPP_A21. 21 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_20): Applied to GPP_A20. 20 RW Same description as PADCFGLOCKTX_GPP_A_0

380 332219-002

GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_19): Applied to GPP_A19. 19 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_18): Applied to GPP_A18. 18 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_17): Applied to GPP_A17. 17 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_16): Applied to GPP_A16. 16 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_15): Applied to GPP_A15. 15 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_14): Applied to GPP_A14. 14 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_13): Applied to GPP_A13. 13 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_12): Applied to GPP_A12. 12 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_11): Applied to GPP_A11. 11 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_10): Applied to GPP_A10. 10 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_9): Applied to GPP_A9. 9 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_8): Applied to GPP_A8. 8 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_7): Applied to GPP_A7. 7 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_6): Applied to GPP_A6. 6 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_5): Applied to GPP_A5. 5 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_4): Applied to GPP_A4. 4 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_3): Applied to GPP_A3. 3 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_2): Applied to GPP_A2. 2 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_1): Applied to GPP_A1. 1 RW Same description as PADCFGLOCKTX_GPP_A_0

Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_0): PadCfgLockTx locks the GPIOTxState bit from being configured. The GPIOTxState register becomes Read- Only and software writes to the register have no effect. 0h 0 = Unlock 0 RW 1 = Locks the Pad Configuration GPIOTXState field as read-only (RO) When PadCfgLockTx is written from a '1' to a '0' (unlock), a synchronous SMI# is generated if enabled. This ensures that only SMM code can change the above GPIO registers after the lockdown.

332219-002 381 GPIO for SKL PCH-H

6.1.12 Pad Configuration Lock (PADCFGLOCK_GPP_B)—Offset A8h

Same description as PADCFGLOCK_GPP_A register, except this register applies to GPP_B[23:0].

6.1.13 Pad Configuration Lock (PADCFGLOCKTX_GPP_B)—Offset ACh

Same description as PADCFGLOCKTX_GPP_A register, except that this register applies to GPP_B[23:0].

6.1.14 Host Software Pad Ownership (HOSTSW_OWN_GPP_A)— Offset D0h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD HOSTSW_OWN_GPP_A_9 HOSTSW_OWN_GPP_A_8 HOSTSW_OWN_GPP_A_7 HOSTSW_OWN_GPP_A_6 HOSTSW_OWN_GPP_A_5 HOSTSW_OWN_GPP_A_4 HOSTSW_OWN_GPP_A_3 HOSTSW_OWN_GPP_A_2 HOSTSW_OWN_GPP_A_1 HOSTSW_OWN_GPP_A_0 HOSTSW_OWN_GPP_A_23 HOSTSW_OWN_GPP_A_22 HOSTSW_OWN_GPP_A_21 HOSTSW_OWN_GPP_A_20 HOSTSW_OWN_GPP_A_19 HOSTSW_OWN_GPP_A_18 HOSTSW_OWN_GPP_A_17 HOSTSW_OWN_GPP_A_16 HOSTSW_OWN_GPP_A_15 HOSTSW_OWN_GPP_A_14 HOSTSW_OWN_GPP_A_13 HOSTSW_OWN_GPP_A_12 HOSTSW_OWN_GPP_A_11 HOSTSW_OWN_GPP_A_10

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h HostSW_Own (HOSTSW_OWN_GPP_A_23): Applied to GPP_A23. Same 23 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_22): Applied to GPP_A22. Same 22 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_21): Applied to GPP_A21. Same 21 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_20): Applied to GPP_A20. Same 20 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_19): Applied to GPP_A19. Same 19 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_18): Applied to GPP_A18. Same 18 RW description as bit 0.

382 332219-002

GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h HostSW_Own (HOSTSW_OWN_GPP_A_17): Applied to GPP_A17. Same 17 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_16): Applied to GPP_A16. Same 16 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_15): Applied to GPP_A15. Same 15 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_14): Applied to GPP_A14. Same 14 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_13): Applied to GPP_A13. Same 13 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_12): Applied to GPP_A12. Same 12 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_11): Applied to GPP_A11. Same 11 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_10): Applied to GPP_A10. Same 10 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_9): Applied to GPP_A9. Same description 9 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_8): Applied to GPP_A8. Same description 8 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_7): Applied to GPP_A7. Same description 7 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_6): Applied to GPP_A6. Same description 6 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_5): Applied to GPP_A5. Same description 5 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_4): Applied to GPP_A4. Same description 4 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_3): Applied to GPP_A3. Same description 3 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_2): Applied to GPP_A2. Same description 2 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_1): Applied to GPP_A1. Same description 1 RW as bit 0.

HostSW_Own (HOSTSW_OWN_GPP_A_0): This register determines the appropriate host status bit update when a pad is under host ownership. 0h 0 = ACPI Mode. GPIO input event updates are limited to GPI_GPE_STS, 0 RW GPI_NMI_STS and/or GPI_SMI_STS. GPI_STS update is masked. 1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked.

6.1.15 Host Software Pad Ownership (HOSTSW_OWN_GPP_B)— Offset D4h

Same description as HOSTSW_OWN_GPP_A register, except that this register applies to GPP_B[23:0].

6.1.16 GPI Interrupt Status (GPI_IS_GPP_A)—Offset 100h

Access Method

332219-002 383 GPIO for SKL PCH-H

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_INT_STS_GPP_A_9 GPI_INT_STS_GPP_A_8 GPI_INT_STS_GPP_A_7 GPI_INT_STS_GPP_A_6 GPI_INT_STS_GPP_A_5 GPI_INT_STS_GPP_A_4 GPI_INT_STS_GPP_A_3 GPI_INT_STS_GPP_A_2 GPI_INT_STS_GPP_A_1 GPI_INT_STS_GPP_A_0 GPI_INT_STS_GPP_A_23 GPI_INT_STS_GPP_A_22 GPI_INT_STS_GPP_A_21 GPI_INT_STS_GPP_A_20 GPI_INT_STS_GPP_A_19 GPI_INT_STS_GPP_A_18 GPI_INT_STS_GPP_A_17 GPI_INT_STS_GPP_A_16 GPI_INT_STS_GPP_A_15 GPI_INT_STS_GPP_A_14 GPI_INT_STS_GPP_A_13 GPI_INT_STS_GPP_A_12 GPI_INT_STS_GPP_A_11 GPI_INT_STS_GPP_A_10

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_23): Applied to GPP_A23. Same 23 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_22): Applied to GPP_A22. Same 22 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_21): Applied to GPP_A21. Same 21 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_20): Applied to GPP_A20. Same 20 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_19): Applied to GPP_A19. Same 19 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_18): Applied to GPP_A18. Same 18 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_17): Applied to GPP_A17. Same 17 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_16): Applied to GPP_A16. Same 16 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_15): Applied to GPP_A15. Same 15 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_14): Applied to GPP_A14. Same 14 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_13): Applied to GPP_A13. Same 13 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_12): Applied to GPP_A12. Same 12 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_11): Applied to GPP_A11. Same 11 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_10): Applied to GPP_A10. Same 10 RW1C description as bit 0.

384 332219-002

GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_9): Applied to GPP_A9. Same 9 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_8): Applied to GPP_A8. Same 8 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_7): Applied to GPP_A7. Same 7 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_6): Applied to GPP_A6. Same 6 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_5): Applied to GPP_A5. Same 5 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_4): Applied to GPP_A4. Same 4 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_3): Applied to GPP_A3. Same 3 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_2): Applied to GPP_A2. Same 2 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_1): Applied to GPP_A1. Same 1 RW1C description as bit 0.

GPI Interrupt Status (GPI_INT_STS_GPP_A_0): GPI Interrupt Status (GPI_INT_STS) This bit is set to ‘1’ by hardware when either an edge or a level event is detected (See RxEdCfg RxInv) on pad and all the following conditions are true: 0h - The corresponding pad is used in GPIO input mode 0 RW1C - HOSTSW_OWN = 1 (i.e. Host GPIO Driver Mode). Writing a value of 1 will clear the bit while writing a value of 0 has no effect. 0 = No interrupt 1 = Interrupt asserts The state of GPI_INT_EN[x] does not prevent the setting of GPI_INT_STS[x].

6.1.17 GPI Interrupt Status (GPI_IS_GPP_B)—Offset 104h

Same description as GPI_IS_GPP_A register, except that this register applies to GPP_B[23:0].

6.1.18 GPI Interrupt Enable (GPI_IE_GPP_A)—Offset 120h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

332219-002 385 GPIO for SKL PCH-H

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_INT_EN_GPP_A_9 GPI_INT_EN_GPP_A_8 GPI_INT_EN_GPP_A_7 GPI_INT_EN_GPP_A_6 GPI_INT_EN_GPP_A_5 GPI_INT_EN_GPP_A_4 GPI_INT_EN_GPP_A_3 GPI_INT_EN_GPP_A_2 GPI_INT_EN_GPP_A_1 GPI_INT_EN_GPP_A_0 GPI_INT_EN_GPP_A_23 GPI_INT_EN_GPP_A_22 GPI_INT_EN_GPP_A_21 GPI_INT_EN_GPP_A_20 GPI_INT_EN_GPP_A_19 GPI_INT_EN_GPP_A_18 GPI_INT_EN_GPP_A_17 GPI_INT_EN_GPP_A_16 GPI_INT_EN_GPP_A_15 GPI_INT_EN_GPP_A_14 GPI_INT_EN_GPP_A_13 GPI_INT_EN_GPP_A_12 GPI_INT_EN_GPP_A_11 GPI_INT_EN_GPP_A_10

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_23): Applied to GPP_A23. Same 23 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_22): Applied to GPP_A22. Same 22 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_21): Applied to GPP_A21. Same 21 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_20): Applied to GPP_A20. Same 20 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_19): Applied to GPP_A19. Same 19 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_18): Applied to GPP_A18. Same 18 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_17): Applied to GPP_A17. Same 17 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_16): Applied to GPP_A16. Same 16 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_15): Applied to GPP_A15. Same 15 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_14): Applied to GPP_A14. Same 14 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_13): Applied to GPP_A13. Same 13 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_12): Applied to GPP_A12. Same 12 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_11): Applied to GPP_A11. Same 11 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_10): Applied to GPP_A10. Same 10 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_9): Applied to GPP_A9. Same 9 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_8): Applied to GPP_A8. Same 8 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_7): Applied to GPP_A7. Same 7 RW description as bit 0.

386 332219-002

GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_6): Applied to GPP_A6. Same 6 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_5): Applied to GPP_A5. Same 5 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_4): Applied to GPP_A3. Same 4 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_3): Applied to GPP_A3. Same 3 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_2): Applied to GPP_A2. Same 2 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_1): Applied to GPP_A1. Same 1 RW description as bit 0.

GPI Interrupt Enable (GPI_INT_EN_GPP_A_0): This bit is used to enable/ 0h disable the generation of APIC interrupt when the corresponding GPI_INT_STS bit is 0 set. RW 0 = disable interrupt generation 1 = enable interrupt generation

6.1.19 GPI Interrupt Enable (GPI_IE_GPP_B)—Offset 124h

Same description as GPI_IE_GPP_A register, except that this register is for GPP_B[23:0].

6.1.20 GPI General Purpose Events Status (GPI_GPE_STS_GPP_A)—Offset 140h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_GPE_STS_GPP_A_9 GPI_GPE_STS_GPP_A_8 GPI_GPE_STS_GPP_A_7 GPI_GPE_STS_GPP_A_6 GPI_GPE_STS_GPP_A_5 GPI_GPE_STS_GPP_A_4 GPI_GPE_STS_GPP_A_3 GPI_GPE_STS_GPP_A_2 GPI_GPE_STS_GPP_A_1 GPI_GPE_STS_GPP_A_0 GPI_GPE_STS_GPP_A_23 GPI_GPE_STS_GPP_A_22 GPI_GPE_STS_GPP_A_21 GPI_GPE_STS_GPP_A_20 GPI_GPE_STS_GPP_A_19 GPI_GPE_STS_GPP_A_18 GPI_GPE_STS_GPP_A_17 GPI_GPE_STS_GPP_A_16 GPI_GPE_STS_GPP_A_15 GPI_GPE_STS_GPP_A_14 GPI_GPE_STS_GPP_A_13 GPI_GPE_STS_GPP_A_12 GPI_GPE_STS_GPP_A_11 GPI_GPE_STS_GPP_A_10

332219-002 387 GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_23): Applied to 23 RW1C GPP_A23. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_22): Applied to 22 RW1C GPP_A22. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_21): Applied to 21 RW1C GPP_A21. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_20): Applied to 20 RW1C GPP_A20. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_19): Applied to 19 RW1C GPP_A19. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_18): Applied to 18 RW1C GPP_A18. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_17): Applied to 17 RW1C GPP_A17. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_16): Applied to 16 RW1C GPP_A16. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_15): Applied to 15 RW1C GPP_A15. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_14): Applied to 14 RW1C GPP_A14. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_13): Applied to 13 RW1C GPP_A13. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_12): Applied to 12 RW1C GPP_A12. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_11): Applied to 11 RW1C GPP_A11. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_10): Applied to 10 RW1C GPP_A10. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_9): Applied to 9 RW1C GPP_A9. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_8): Applied to 8 RW1C GPP_A8. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_7): Applied to 7 RW1C GPP_A7. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_6): Applied to 6 RW1C GPP_A6. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_5): Applied to 5 RW1C GPP_A5. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_4): Applied to 4 RW1C GPP_A4. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_3): Applied to 3 RW1C GPP_A3. Same description as bit 0.

388 332219-002

GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_2): Applied to 2 RW1C GPP_A2. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_1): Applied to 1 RW1C GPP_A1. Same description as bit 0.

GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_0): These bits are set any time the corresponding GPIO pad is set up as an input, under host ownership and the corresponding GPIO signal is high(or low if the corresponding RXINV bit is set). 0h If the corresponding enable bit is set in the GPI_GPE_EN register, then when the 0 GPI_GPE_STS bit is set: RW1C - If the system is in an S3-S5 state, the event will also wake the system. - If the system is in an S0 state (or upon waking back to an S0 state), an SCI will be caused, depending on the GPIRoutSCI bit for the corresponding pad. These bits are sticky bits and are cleared by writing a 1 back to this bit position. The state of GPI_GPE_EN does not prevent the setting of GPI_GPE_STS.

6.1.21 GPI General Purpose Events Status (GPI_GPE_STS_GPP_B)—Offset 144h

Same description as PI_GPE_STS_GPP_A register, except that this is for GPP_B[23:0].

6.1.22 GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A)—Offset 160h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_GPE_EN_GPP_A_9 GPI_GPE_EN_GPP_A_8 GPI_GPE_EN_GPP_A_7 GPI_GPE_EN_GPP_A_6 GPI_GPE_EN_GPP_A_5 GPI_GPE_EN_GPP_A_4 GPI_GPE_EN_GPP_A_3 GPI_GPE_EN_GPP_A_2 GPI_GPE_EN_GPP_A_1 GPI_GPE_EN_GPP_A_0 GPI_GPE_EN_GPP_A_23 GPI_GPE_EN_GPP_A_22 GPI_GPE_EN_GPP_A_21 GPI_GPE_EN_GPP_A_20 GPI_GPE_EN_GPP_A_19 GPI_GPE_EN_GPP_A_18 GPI_GPE_EN_GPP_A_17 GPI_GPE_EN_GPP_A_16 GPI_GPE_EN_GPP_A_15 GPI_GPE_EN_GPP_A_14 GPI_GPE_EN_GPP_A_13 GPI_GPE_EN_GPP_A_12 GPI_GPE_EN_GPP_A_11 GPI_GPE_EN_GPP_A_10

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_23): Applied to 23 RW GPP_A23. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_22): Applied to 22 RW GPP_A22. Same description as bit 0.

332219-002 389 GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_21): Applied to 21 RW GPP_A21. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_20): Applied to 20 RW GPP_A20. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_19): Applied to 19 RW GPP_A19. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_18): Applied to 18 RW GPP_A18. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_17): Applied to 17 RW GPP_A17. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_16): Applied to 16 RW GPP_A16. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_15): Applied to 15 RW GPP_A15. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_14): Applied to 14 RW GPP_A14. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_13): Applied to 13 RW GPP_A13. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_12): Applied to 12 RW GPP_A12. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_11): Applied to 11 RW GPP_A11. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_10): Applied to 10 RW GPP_A10. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_9): Applied to 9 RW GPP_A9. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_8): Applied to 8 RW GPP_A8. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_7): Applied to 7 RW GPP_A7. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_6): Applied to 6 RW GPP_A6. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_5): Applied to 5 RW GPP_A5. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_4): Applied to 4 RW GPP_A4. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_3): Applied to 3 RW GPP_A3. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_2): Applied to 2 RW GPP_A2. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_1): Applied to 1 RW GPP_A1. Same description as bit 0.

GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_0): This bit is used to enable/disable the generation of GPE to cause SCI and/or wake when the 0h corresponding GPI_GPE_STS bit is set. 0 0 = disable GPE generation RW 1 = enable GPE generation Note: The pad must also be routed for GPE functionality in order for GPE to be generated, i.e. the corresponding GPIRoutSCI must be set to ‘1’.

390 332219-002

GPIO for SKL PCH-H

6.1.23 GPI General Purpose Events Enable (GPI_GPE_EN_GPP_B)—Offset 164h

Same description as PI_GPI_GPE_EN_GPP_A register, except that this is for GPP_B[23:0].

6.1.24 SMI Status (GPI_SMI_STS_GPP_B)—Offset 184h

Register bits in this register are implemented for GPP_B signals that have SMI capability only. Other bits are reserved and RO.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD RSVD RSVD GPI_SMI_STS_GPP_B_23 GPI_SMI_STS_GPP_B_20 GPI_SMI_STS_GPP_B_14

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h GPI SMI Status (GPI_SMI_STS_GPP_B_23): Same description as bit 14. 23 RW1C

0h 22:21 Reserved. RO

0h GPI SMI Status (GPI_SMI_STS_GPP_B_20): Same description as bit 14. 20 RW1C

332219-002 391 GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h 19:15 Reserved. RO

GPI SMI Status (GPI_SMI_STS_GPP_B_14): This bit is set to 1 by hardware when a level event (See RxEdCfg,RxInv) is detected, and all the following conditions are true: - The corresponding pad is used in GPIO input mode - The corresponding PAD_OWN[2:0] is ‘000’ (i.e. ACPI GPIO Mode). If the following conditions are true, then an SMI will be generated if the 0h GPI_SMI_STS bit is set: 14 RW1C 1. The corresponding bit in the GPI_SMI_EN register is set 2. The corresponding pad’s GPIROUTSMI is set Writing a value of 1 will clear the bit while writing a value of 0 has no effect. 0 = There is no SMI event 1 = There is an SMI event The state of GPI_SMI_EN does not prevent the setting of GPI_SMI_STS. Defaults for these bits are dependent on the state of the GPI pads.

0h 13:0 Reserved. RO

6.1.25 SMI Enable (GPI_SMI_EN_GPP_B)—Offset 1A4h

Register bits in this register are implemented for GPP_B signals that have SMI capability only. Other bits are reserved and RO.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD RSVD RSVD GPI_SMI_EN_GPP_B_23 GPI_SMI_EN_GPP_B_20 GPI_SMI_EN_GPP_B_14

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h GPI SMI Enable (GPI_SMI_EN_GPP_B_23): Same description as bit 14. 23 RW

0h 22:21 Reserved. RO

0h GPI SMI Enable (GPI_SMI_EN_GPP_B_20): Same description as bit 14. 20 RW

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Bit Default & Field Name (ID): Description Range Access

0h 19:15 Reserved. RO

GPI SMI Enable (GPI_SMI_EN_GPP_B_14): This bit is used to enable/disable the generation of SMI when the corresponding GPI_SMI_STS bit is set. The pad must also be routed for SMI functionality in order for SMI to be generated, i.e. the 0h corresponding GPIROUTSMI must be set to 1. 14 0 = disable SMI generation RW 1 = enable SMI generation Note: Each of the bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. E.g. if the PadCfgLock of pad0 is 1, bit0 of this bit is locked down to read-only.

0h 13:0 Reserved. RO

6.1.26 NMI Status (GPI_NMI_STS_GPP_B)—Offset 1C4h

Register bits in this register are implemented for GPP_B signals that have NMI capability only. Other bits are reserved and RO.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD RSVD RSVD GPI_NMI_STS_GPP_B_23 GPI_NMI_STS_GPP_B_20 GPI_NMI_STS_GPP_B_14

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h GPI NMI Status (GPI_NMI_STS_GPP_B_23): Same description as bit 14. 23 RW1C

0h 22:21 Reserved. RO

0h GPI NMI Status (GPI_NMI_STS_GPP_B_20): Same description as bit 14. 20 RW1C

332219-002 393 GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h 19:15 Reserved. RO

GPI NMI Status (GPI_NMI_STS_GPP_B_14): This bit is set to 1 by hardware when an edge event is detected (See RxEdCfg, RxInv) on pad and all the following conditions are true: - The corresponding pad is used in GPIO input mode (PMode) 0h - The corresponding GPIONMIRout is set to 1, i.e. programmed to route as NMI 14 RW1C - The corresponding GPIOOwn[2:0] is ‘000’ (i.e. ACPI GPIO Mode). - The corresponding GPI_NMI_EN is set Writing a value of 1 will clear the bit while writing a value of 0 has no effect. 0 = There is no NMI event 1 = There is an NMI event

0h 13:0 Reserved. RO

6.1.27 NMI Enable (GPI_NMI_EN_GPP_B)—Offset 1E4h

Register bits in this register are implemented for GPP_B signals that have NMI capability only. Other bits are reserved and RO.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD RSVD RSVD GPI_NMI_EN_GPP_B_23 GPI_NMI_EN_GPP_B_20 GPI_NMI_EN_GPP_B_14

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h GPI NMI Enable (GPI_NMI_EN_GPP_B_23): Same description as bit 14. 23 RW

0h 22:21 Reserved. RO

0h GPI NMI Enable (GPI_NMI_EN_GPP_B_20): Same description as bit 14. 20 RW

394 332219-002

GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h 19:15 Reserved. RO

GPI NMI Enable (GPI_NMI_EN_GPP_B_14): This bit is used to enable/disable the generation of NMI when the corresponding GPI_NMI_STS bit is set and its GPIROUTNMI is set. 0h 14 0 = disable NMI generation RW 1 = enable NMI generation Each bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. E.g. if the PadCfgLock of pad0 is ‘1’, bit0 of this bit is locked down to read-only.

0h 13:0 Reserved. RO

6.1.28 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_0)— Offset 400h

This register applies to GPP_A0.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 4400xx00h

3 2 2 2 1 1 840 1 8 4 0 6 2

01000100000000000000001100000000 RSVD RSVD RSVD RSVD RSVD RXINV PMODE2 PMODE1 PMODE0 RXRAW1 RXEVCFG GPIOTXDIS GPIORXDIS PADRSTCFG GPIROUTSCI GPIROUTSMI RXPADSTSEL GPIROUTNMI GPIOTXSTATE GPIORXSTATE GPIROUTIOXAPIC

Bit Default & Field Name (ID): Description Range Access

Pad Reset Config (PADRSTCFG): This register controls which reset is used to reset GPIO pad register fields in PAD_CFG_DW0 and PAD_CFG_DW1 registers. This register can be used for Sx isolation of the associated signal if needed. 1h 00 = RSMRST# 31:30 01 = Host deep reset. This reset occurs when a host reset (with or without power RW cycle) is initiated or a global reset is initiated, except that the reset does not assert when in S3/S4/S5. 10 = PLTRST# 11 = Reserved

RX Pad State Select (RXPADSTSEL): Determines from which node the RX pad state for native function should be taken from. This field only affects the pad state 0h value being fanned out to native function(s) and is not meaningful if the pad is in 29 RW GPIO mode (i.e. Pad Mode = 0). 0 = Raw RX pad state directly from RX buffer 1 = Internal RX pad state (subject to RXINV and PreGfRXSel settings)

RX Raw Override to '1' (RXRAW1): This bit determines if the selected pad state is being overridden to '1'. This field is only applicable when the RX buffer is configured 0h as an input in either GPIO Mode or native function mode. The override takes place at 28 RW the internal pad state directly from buffer and before the RXINV. 0 = No Override 1 = RX drive 1 internally

332219-002 395 GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h 27 Reserved. RO

RX Level/Edge Configuration (RXEVCFG): Determines if the internal RX pad state (synchronized, filtered vs non-filtered version as determined by PreGfRXSel, and is further subject to RXInv) should be passed on to the next logic stage as is, as a pulse, or level signal. This field does not affect the received pad state (to 2h GPIORXState or native functions) but how the interrupt or wake triggering events 26:25 RW should be delivered to the GPIO Community Controller . 0h = Level 1h = Edge 2h = Drive '0' 3h = Reserved (implement as setting 0h)

0h 24 Reserved. RO

RX Invert (RXINV): This bit determines if the selected pad state should go through the polarity inversion stage. This field is only applicable when the RX buffer is configured as an input in either GPIO Mode or native function mode. The polarity inversion takes place at the mux node of raw vs filtered or non-filtered RX pad state, 0h as determined by PreGfRXsel and RXPadStSel This bit does not affect GPIORXState. 23 During host ownership GPIO Mode, when this bit is set to '1', then the RX pad state is RW inverted as it is sent to the GPIO-to-IOxAPIC, GPE/SCI, SMI, NMI logic or GPI_IS[n] that is using it. This is used to allow active-low and active-high inputs to cause IRQ, SMI#, SCI or NMI. 0 = No inversion 1 = Inversion

0h 22:21 Reserved. RO

GPIO Input Route IOxAPIC (GPIROUTIOXAPIC): Determines if the pad can be routed to cause peripheral IRQ when configured in GPIO input mode. If the pad is not 0h configured in GPIO input mode, this field has no effect. 20 0 = Routing does not cause peripheral IRQ RW 1 = Routing can cause peripheral IRQ Note: This bit does not affect any interrupt status bit within GPIO, but is used as the last qualifier for the peripheral IRQ indication to the intended recipient(s).

GPIO Input Route SCI (GPIROUTSCI): Determines if the pad can be routed to cause SCI when configured in GPIO input mode. If the pad is not configured in GPIO 0h input mode, this field has no effect. 19 0 = Routing does not cause SCI. RW 1 = Routing can cause SCI Note: This bit does not affect any interrupt status bit within GPIO, but is used as the last qualifier for the GPE indication to the intended recipient(s).

GPIO Input Route SMI (GPIROUTSMI): Determines if the pad can be routed to cause SMI when configured in GPIO input mode. If the pad is not configured in GPIO input mode, this field has no effect. 0h 0 = Routing does not cause SMI. 18 RW 1 = Routing can cause SMI. Note: This bit does not affect any interrupt status bit within GPIO, but is used as the last qualifier for the SMI indication to the intended recipient(s). This bit only applies to a GPIO that has SMI capability. Otherwise, the bit is RO.

GPIO Input Route NMI (GPIROUTNMI): Determines if the pad can be routed to cause NMI when configured in GPIO input mode. If the pad is not configured in GPIO input mode, this field has no effect. 0 = Routing does not cause NMI. 0h 17 1 = Routing can cause NMI. RW Note: This bit also affects GPI_NMI_STS. If '0', GPI_NMI_STS is always clear. If '1', GPI_NMI_STS could be set (depending on GPIOOwn setting) when there is an event. Whether a NMI indication is generated and sent to the intended recipient(s) is also depending on the corresponding GPI_NMI_EN bit. This bit only applies to a GPIO that has NMI capability. Otherwise, the bit is RO.

0h 16:13 Reserved. RO

-- Pad Mode bit 2 (PMODE2): See Pad Mode Bit 0 description. 12 RW

-- Pad Mode bit 1 (PMODE1): See Pad Mode Bit 0 description. 11 RW

396 332219-002

GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

Pad Mode bit 0 (PMODE0): This bit is used in conjunction with Pad Mode bit 1 and 2 . This three-bit field determines whether the Pad is controlled by GPIO controller logic or one of the native functions muxed onto the Pad. 0h = GPIO control the Pad. 1h = native function 1, if applicable, controls the Pad

-- 2h = native function 2, if applicable, controls the Pad 10 3h = native function 3, if applicable, controls the Pad RW 4h = enable GPIO blink/PWM capability if applicable (note that not all GPIOs have blink/PWM capability) Dedicated (unmuxed) GPIO shall report RO of all 0’s in this register field If GPIO vs. native mode is configured via soft strap, this bit has no effect.

Default value is determined by the default functionality of the pad.

GPIO RX Disable (GPIORXDIS): 0 = Enable the input buffer (active low enable) of 1h the pad. 9 1 = Disable the input buffer of the pad. RW Notes: When the input buffer is disabled, the internal pad state is always driven to '0'.

1h GPIO TX Disable (GPIOTXDIS): 0 = Enable the output buffer (active low enable) 8 of the pad. RW 1 = Disable the output buffer of the pad; i.e. Hi-Z

0h 7:2 Reserved. RO

0h GPIO RX State (GPIORXSTATE): This is the current internal RX pad state after 1 RO Glitch Filter logic stage and is not affected by PMode and RXINV settings.

0h GPIO TX State (GPIOTXSTATE): 0 = Drive a level '0' to the TX output pad. 0 RW 1 = Drive a level '1' to the TX output pad

6.1.29 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_0)— Offset 404h

This register applies to GPP_A0.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 18h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000011000 TERM RSVD RSVD INTSEL

332219-002 397 GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h 31:14 Reserved. RO

Termination (TERM): The Pad Termination state defines the different weak pull-up and pull-down settings that are supported by the buffer. The settings for [13:10] correspond to: 0000: none 0010: 5k pd 0100: 20k pd 1000: none 1001: 1k pu 1011: 2k pu

0h 1010: 5k pu 13:10 1100: 20k pu RW 1101: 1k & 2k pu (in parallel) 1111: Native controller selected by Pad Mode controls the Termination All others reserved. If a reserved value is programmed, pad may malfunction. The setting of this field is applicable in all Pad Mode including GPIO. As each Pad Mode may require different termination and isolation, care must be taken in sw/fw in the transition with appropriate register programming. The actual transition sequence requirement may vary on case by case basis depending on the native functions involved. For example, before changing the pad from output to input direction, pu/pd settings should be programmed first to ensure the input does not float momentarily.

0h 9:8 Reserved. RO

Interrupt Select (INTSEL): The Interrupt Select defines which interrupt line driven from the GPIO Controller toggles when an interrupt is detected on this pad. 18h 0 = Interrupt Line 0 7:0 RO 1 = Interrupt Line 1 .... Up to the max IOxAPIC IRQ supported

6.1.30 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_1)— Offset 408h

This register applies to GPP_A1 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.31 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_1)— Offset 40Ch

This register applies to GPP_A1 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 19h

6.1.32 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_2)— Offset 410h

This register applies to GPP_A2 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.33 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_2)— Offset 414h

This register applies to GPP_A2 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 1Ah

398 332219-002

GPIO for SKL PCH-H

6.1.34 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_3)— Offset 418h

This register applies to GPP_A3 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.35 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_3)— Offset 41Ch

This register applies to GPP_A3 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 1Bh

6.1.36 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_4)— Offset 420h

This register applies to GPP_A4 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.37 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_4)— Offset 424h

This register applies to GPP_A4 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 1Ch

6.1.38 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_5)— Offset 428h

This register applies to GPP_A5 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.39 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_5)— Offset 42Ch

This register applies to GPP_A5 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 1Dh

6.1.40 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_6)— Offset 430h

This register applies to GPP_A6 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.41 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_6)— Offset 434h

This register applies to GPP_A6 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 1Eh

332219-002 399 GPIO for SKL PCH-H

6.1.42 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_7)— Offset 438h

This register applies to GPP_A7 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.43 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_7)— Offset 43Ch

This register applies to GPP_A7 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 1Fh

6.1.44 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_8)— Offset 440h

This register applies to GPP_A8 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.45 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_8)— Offset 444h

This register applies to GPP_A8 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 20h

6.1.46 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_9)— Offset 448h

This register applies to GPP_A9 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.47 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_9)— Offset 44Ch

This register applies to GPP_A9 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 21h

6.1.48 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_10)— Offset 450h

This register applies to GPP_A10 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.49 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_10)— Offset 454h

This register applies to GPP_A10 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 22h

400 332219-002

GPIO for SKL PCH-H

6.1.50 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_11)— Offset 458h

This register applies to GPP_A11 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.51 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_11)— Offset 45Ch

This register applies to GPP_A11 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 26h

6.1.52 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_12)— Offset 460h

This register applies to GPP_A12 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.53 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_12)— Offset 464h

This register applies to GPP_A12 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 23h

6.1.54 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_13)— Offset 468h

This register applies to GPP_A13 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.55 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_13)— Offset 46Ch

This register applies to GPP_A13 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 24h

6.1.56 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_14)— Offset 470h

This register applies to GPP_A14 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.57 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_14)— Offset 474h

This register applies to GPP_A14 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 25h

332219-002 401 GPIO for SKL PCH-H

6.1.58 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_15)— Offset 478h

This register applies to GPP_A15 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.59 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_15)— Offset 47Ch

This register applies to GPP_A15 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 27h

6.1.60 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_16)— Offset 480h

This register applies to GPP_A16 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.61 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_16)— Offset 484h

This register applies to GPP_A16 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 28h

6.1.62 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_17)— Offset 488h

This register applies to GPP_A17 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.63 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_17)— Offset 48Ch

This register applies to GPP_A17 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 29h

6.1.64 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_18)— Offset 490h

This register applies to GPP_A18 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.65 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_18)— Offset 494h

This register applies to GPP_A18 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 2Ah

402 332219-002

GPIO for SKL PCH-H

6.1.66 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_19)— Offset 498h

This register applies to GPP_A19 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.67 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_19)— Offset 49Ch

This register applies to GPP_A19 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 2Bh

6.1.68 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_20)— Offset 4A0h

This register applies to GPP_A20 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.69 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_20)— Offset 4A4h

This register applies to GPP_A20 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 2Ch

6.1.70 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_21)— Offset 4A8h

This register applies to GPP_A21 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.71 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_21)— Offset 4ACh

This register applies to GPP_A21 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 2Dh

6.1.72 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_22)— Offset 4B0h

This register applies to GPP_A22 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.73 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_22)— Offset 4B4h

This register applies to GPP_A22 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 2Eh

332219-002 403 GPIO for SKL PCH-H

6.1.74 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_23)— Offset 4B8h

This register applies to GPP_A23 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.75 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_23)— Offset 4BCh

This register applies to GPP_A23 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 2Fh

6.1.76 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_0)— Offset 4C0h

This register applies to GPP_B0 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.77 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_0)— Offset 4C4h

This register applies to GPP_B0 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 8'h30

6.1.78 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_1)— Offset 4C8h

This register applies to GPP_B1 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.79 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_1)— Offset 4CCh

This register applies to GPP_B1 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 31h

6.1.80 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_2)— Offset 4D0h

This register applies to GPP_B2 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.81 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_2)— Offset 4D4h

This register applies to GPP_B2 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 32h

404 332219-002

GPIO for SKL PCH-H

6.1.82 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_3)— Offset 4D8h

This register applies to GPP_B3 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.83 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_3)— Offset 4DCh

This register applies to GPP_B3 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 33h

6.1.84 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_4)— Offset 4E0h

This register applies to GPP_B4 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.85 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_4)— Offset 4E4h

This register applies to GPP_B4 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 34h

6.1.86 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_5)— Offset 4E8h

This register applies to GPP_B5 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.87 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_5)— Offset 4ECh

This register applies to GPP_B5 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 35h

6.1.88 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_6)— Offset 4F0h

This register applies to GPP_B6 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.89 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_6)— Offset 4F4h

This register applies to GPP_B6 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 36h

332219-002 405 GPIO for SKL PCH-H

6.1.90 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_7)— Offset 4F8h

This register applies to GPP_B7 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.91 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_7)— Offset 4FCh

This register applies to GPP_B7 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 37h

6.1.92 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_8)— Offset 500h

This register applies to GPP_B8 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.93 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_8)— Offset 504h

This register applies to GPP_B8 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 38h

6.1.94 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_9)— Offset 508h

This register applies to GPP_B9 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.95 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_9)— Offset 50Ch

This register applies to GPP_B9 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 39h

6.1.96 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_10)— Offset 510h

This register applies to GPP_B10 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.97 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_10)— Offset 514h

This register applies to GPP_B10 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 3Ah

406 332219-002

GPIO for SKL PCH-H

6.1.98 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_11)— Offset 518h

This register applies to GPP_B11 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.99 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_11)— Offset 51Ch

This register applies to GPP_B11 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 3Bh

6.1.100 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_12)— Offset 520h

This register applies to GPP_B12 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.101 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_12)— Offset 524h

This register applies to GPP_B12 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 3Ch

6.1.102 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_13)— Offset 528h

This register applies to GPP_B13 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.103 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_13)— Offset 52Ch

This register applies to GPP_B13 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 3Dh

6.1.104 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_14)— Offset 530h

This register applies to GPP_B14 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.105 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_14)— Offset 534h

This register applies to GPP_B14 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 3Eh

332219-002 407 GPIO for SKL PCH-H

6.1.106 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_15)— Offset 538h

This register applies to GPP_B15 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.107 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_15)— Offset 53Ch

This register applies to GPP_B15 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 3Fh

6.1.108 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_16)— Offset 540h

This register applies to GPP_B16 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.109 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_16)— Offset 544h

This register applies to GPP_B16 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 40h

6.1.110 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_17)— Offset 548h

This register applies to GPP_B17 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.111 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_17)— Offset 54Ch

This register applies to GPP_B17 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 41h

6.1.112 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_18)— Offset 550h

This register applies to GPP_B18 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.113 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_18)— Offset 554h

This register applies to GPP_B18 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 42h

408 332219-002

GPIO for SKL PCH-H

6.1.114 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_19)— Offset 558h

This register applies to GPP_B19 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.115 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_19)— Offset 55Ch

This register applies to GPP_B19 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 43h

6.1.116 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_20)— Offset 560h

This register applies to GPP_B20 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.117 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_20)— Offset 564h

This register applies to GPP_B20 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 44h

6.1.118 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_21)— Offset 568h

This register applies to GPP_B21 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.119 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_21)— Offset 56Ch

This register applies to GPP_B21 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 45h

6.1.120 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_22)— Offset 570h

This register applies to GPP_B22 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.121 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_22)— Offset 574h

This register applies to GPP_B22 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 46h

332219-002 409 GPIO for SKL PCH-H

6.1.122 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_23)— Offset 578h

This register applies to GPP_B23 and has the same description as PAD_CFG_DW0_GPP_A_0.

6.1.123 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_23)— Offset 57Ch

This register applies to GPP_B23 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 47h

6.2 GPIO Community 1 Registers Summary

Community 1 Registers are for GPP_C, GPP_D, GPP_E, GPP_F, GPP_G, and GPP_H groups.

Table 6-2. Summary of GPIO Community 1 Registers

Offset Offset Default Register Name (ID)—Offset Start End Value

8h Bh Family Base Address (FAMBAR)—Offset 8h 300h

Ch Fh Pad Base Address (PADBAR)—Offset Ch 400h

10h 13h Miscellaneous Configuration (MISCCFG)—Offset 10h 43200h

20h 23h Pad Ownership (PAD_OWN_GPP_C_0)—Offset 20h 0h

24h 27h Pad Ownership (PAD_OWN_GPP_C_1)—Offset 24h 0h

28h 2Bh Pad Ownership (PAD_OWN_GPP_C_2)—Offset 28h 0h

2Ch 2Fh Pad Ownership (PAD_OWN_GPP_D_0)—Offset 2Ch 0h

30h 33h Pad Ownership (PAD_OWN_GPP_D_1)—Offset 30h 0h

34h 37h Pad Ownership (PAD_OWN_GPP_D_2)—Offset 34h 0h

38h 3Bh Pad Ownership (PAD_OWN_GPP_E_0)—Offset 38h 0h

3Ch 3Fh Pad Ownership (PAD_OWN_GPP_E_1)—Offset 3Ch 0h

40h 43h Pad Ownership (PAD_OWN_GPP_F_0)—Offset 40h 0h

44h 47h Pad Ownership (PAD_OWN_GPP_F_1)—Offset 44h 0h

48h 4Bh Pad Ownership (PAD_OWN_GPP_F_2)—Offset 48h 0h

4Ch 4Fh Pad Ownership (PAD_OWN_GPP_G_0)—Offset 4Ch 0h

50h 53h Pad Ownership (PAD_OWN_GPP_G_1)—Offset 50h 0h

54h 57h Pad Ownership (PAD_OWN_GPP_G_2)—Offset 54h 0h

58h 5Bh Pad Ownership (PAD_OWN_GPP_H_0)—Offset 58h 0h

5Ch 5Fh Pad Ownership (PAD_OWN_GPP_H_1)—Offset 5Ch 0h

60h 63h Pad Ownership (PAD_OWN_GPP_H_2)—Offset 60h 0h

90h 93h Pad Configuration Lock (PADCFGLOCK_GPP_C_0)—Offset 90h 0h

94h 97h Pad Configuration Lock (PADCFGLOCKTX_GPP_C_0)—Offset 94h 0h

98h 9Bh Pad Configuration Lock (PADCFGLOCK_GPP_D_0)—Offset 98h 0h

9Ch 9Fh Pad Configuration Lock (PADCFGLOCKTX_GPP_D_0)—Offset 9Ch 0h

A0h A3h Pad Configuration Lock (PADCFGLOCK_GPP_E_0)—Offset A0h 0h

410 332219-002

GPIO for SKL PCH-H

Table 6-2. Summary of GPIO Community 1 Registers (Continued)

Offset Offset Default Register Name (ID)—Offset Start End Value

A4h A7h Pad Configuration Lock (PADCFGLOCKTX_GPP_E_0)—Offset A4h 0h

A8h ABh Pad Configuration Lock (PADCFGLOCK_GPP_F_0)—Offset A8h 0h

ACh AFh Pad Configuration Lock (PADCFGLOCKTX_GPP_F_0)—Offset ACh 0h

B0h B3h Pad Configuration Lock (PADCFGLOCK_GPP_G_0)—Offset B0h 0h

B4h B7h Pad Configuration Lock (PADCFGLOCKTX_GPP_G_0)—Offset B4h 0h

B8h BBh Pad Configuration Lock (PADCFGLOCK_GPP_H_0)—Offset B8h 0h

BCh BFh Pad Configuration Lock (PADCFGLOCKTX_GPP_H_0)—Offset BCh 0h

D0h D3h Host Software Pad Ownership (HOSTSW_OWN_GPP_C_0)—Offset D0h 0h

D4h D7h Host Software Pad Ownership (HOSTSW_OWN_GPP_D_0)—Offset D4h 0h

D8h DBh Host Software Pad Ownership (HOSTSW_OWN_GPP_E_0)—Offset D8h 0h

DCh DFh Host Software Pad Ownership (HOSTSW_OWN_GPP_F_0)—Offset DCh 0h

E0h E3h Host Software Pad Ownership (HOSTSW_OWN_GPP_G_0)—Offset E0h 0h

E4h E7h Host Software Pad Ownership (HOSTSW_OWN_GPP_H_0)—Offset E4h 0h

100h 103h GPI Interrupt Status (GPI_IS_GPP_C_0)—Offset 100h 0h

104h 107h GPI Interrupt Status (GPI_IS_GPP_D_0)—Offset 104h 0h

108h 10Bh GPI Interrupt Status (GPI_IS_GPP_E_0)—Offset 108h 0h

10Ch 10Fh GPI Interrupt Status (GPI_IS_GPP_F_0)—Offset 10Ch 0h

110h 113h GPI Interrupt Status (GPI_IS_GPP_G_0)—Offset 110h 0h

114h 117h GPI Interrupt Status (GPI_IS_GPP_H_0)—Offset 114h 0h

120h 123h GPI Interrupt Enable (GPI_IE_GPP_C_0)—Offset 120h 0h

124h 127h GPI Interrupt Enable (GPI_IE_GPP_D_0)—Offset 124h 0h

128h 12Bh GPI Interrupt Enable (GPI_IE_GPP_E_0)—Offset 128h 0h

12Ch 12Fh GPI Interrupt Enable (GPI_IE_GPP_F_0)—Offset 12Ch 0h

130h 133h GPI Interrupt Enable (GPI_IE_GPP_G_0)—Offset 130h 0h

134h 137h GPI Interrupt Enable (GPI_IE_GPP_H_0)—Offset 134h 0h

GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_0)—Offset 140h 143h 0h 140h

GPI General Purpose Events Status (GPI_GPE_STS_GPP_D_0)—Offset 144h 147h 0h 144h

GPI General Purpose Events Status (GPI_GPE_STS_GPP_E_0)—Offset 148h 14Bh 0h 148h

GPI General Purpose Events Status (GPI_GPE_STS_GPP_F_0)—Offset 14Ch 14Fh 0h 14Ch

GPI General Purpose Events Status (GPI_GPE_STS_GPP_G_0)—Offset 150h 153h 0h 150h

GPI General Purpose Events Status (GPI_GPE_STS_GPP_H_0)—Offset 154h 157h 0h 154h

GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_0)—Offset 160h 163h 0h 160h

GPI General Purpose Events Enable (GPI_GPE_EN_GPP_D_0)—Offset 164h 167h 0h 164h

GPI General Purpose Events Enable (GPI_GPE_EN_GPP_E_0)—Offset 168h 16Bh 0h 168h

332219-002 411 GPIO for SKL PCH-H

Table 6-2. Summary of GPIO Community 1 Registers (Continued)

Offset Offset Default Register Name (ID)—Offset Start End Value

GPI General Purpose Events Enable (GPI_GPE_EN_GPP_F_0)—Offset 16Ch 16Fh 0h 16Ch

GPI General Purpose Events Enable (GPI_GPE_EN_GPP_G_0)—Offset 170h 173h 0h 170h

GPI General Purpose Events Enable (GPI_GPE_EN_GPP_H_0)—Offset 174h 177h 0h 174h

180h 183h SMI Status (GPI_SMI_STS_GPP_C_0)—Offset 180h 0h

184h 187h SMI Status (GPI_SMI_STS_GPP_D_0)—Offset 184h 0h

188h 18Bh SMI Status (GPI_SMI_STS_GPP_E_0)—Offset 188h 0h

1A0h 1A3h SMI Enable (GPI_SMI_EN_GPP_C_0)—Offset 1A0h 0h

1A4h 1A7h SMI Enable (GPI_SMI_EN_GPP_D_0)—Offset 1A4h 0h

1A8h 1ABh SMI Enable (GPI_SMI_EN_GPP_E_0)—Offset 1A8h 0h

1C0h 1C3h NMI Status (GPI_NMI_STS_GPP_C_0)—Offset 1C0h 0h

1C4h 1C7h NMI Status (GPI_NMI_STS_GPP_D_0)—Offset 1C4h 0h

1C8h 1CBh NMI Status (GPI_NMI_STS_GPP_E_0)—Offset 1C8h 0h

1E0h 1E3h NMI Enable (GPI_NMI_EN_GPP_C_0)—Offset 1E0h 0h

1E4h 1E7h NMI Enable (GPI_NMI_EN_GPP_D_0)—Offset 1E4h 0h

1E8h 1EBh NMI Enable (GPI_NMI_EN_GPP_E_0)—Offset 1E8h 0h

204h 207h PWM Control (PWMC)—Offset 204h 0h

20Ch 20Fh GPIO Serial Blink Enable (GP_SER_BLINK)—Offset 20Ch 0h

210h 213h GPIO Serial Blink Command/Status (GP_SER_CMDSTS)—Offset 210h 0h

214h 217h GPIO Serial Blink Data (GP_SER_DATA)—Offset 214h 0h

21Ch 21Fh GSX Controller Capabilities (GSX_CAP)—Offset 21Ch 0h

220h 223h GSX Channel-0 Capabilities DW0 (GSX_C0CAP_DW0)—Offset 220h 0h

224h 227h GSX Channel-0 Capabilities DW1 (GSX_C0CAP_DW1)—Offset 224h 12000h

228h 22Bh GSX Channel-0 GP Input Level DW0 (GSX_C0GPILVL_DW0)—Offset 228h 0h

GSX Channel-0 GP Input Level DW1 (GSX_C0GPILVL_DW1)—Offset 22Ch 22Fh 0h 22Ch

GSX Channel-0 GP Output Level DW0 (GSX_C0GPOLVL_DW0)—Offset 230h 233h 0h 230h

GSX Channel-0 GP Output Level DW1 (GSX_C0GPOLVL_DW1)—Offset 234h 237h 0h 234h

238h 23Bh GSX Channel-0 Command (GSX_C0CMD)—Offset 238h 0h

23Ch 23Fh GSX Channel-0 Test Mode (GSX_C0TM)—Offset 23Ch 0h

400h 403h Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_0)—Offset 400h 44000300h

404h 407h Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_0)—Offset 404h 18h

408h 40Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_1)—Offset 408h 0h

40Ch 40Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_1)—Offset 40Ch 0h

410h 413h Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_2)—Offset 410h 0h

414h 417h Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_2)—Offset 414h 0h

418h 41Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_3)—Offset 418h 0h

41Ch 41Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_3)—Offset 41Ch 0h

412 332219-002

GPIO for SKL PCH-H

Table 6-2. Summary of GPIO Community 1 Registers (Continued)

Offset Offset Default Register Name (ID)—Offset Start End Value

420h 423h Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_4)—Offset 420h 0h

424h 427h Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_4)—Offset 424h 0h

428h 42Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_5)—Offset 428h 0h

42Ch 42Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_5)—Offset 42Ch 0h

430h 433h Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_6)—Offset 430h 0h

434h 437h Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_6)—Offset 434h 0h

438h 43Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_7)—Offset 438h 0h

43Ch 43Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_7)—Offset 43Ch 0h

440h 443h Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_8)—Offset 440h 0h

444h 447h Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_8)—Offset 444h 0h

448h 44Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_9)—Offset 448h 0h

44Ch 44Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_9)—Offset 44Ch 0h

450h 453h Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_10)—Offset 450h 0h

454h 457h Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_10)—Offset 454h 0h

458h 45Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_11)—Offset 458h 0h

45Ch 45Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_11)—Offset 45Ch 0h

460h 463h Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_12)—Offset 460h 0h

464h 467h Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_12)—Offset 464h 0h

468h 46Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_13)—Offset 468h 0h

46Ch 46Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_13)—Offset 46Ch 0h

470h 473h Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_14)—Offset 470h 0h

474h 477h Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_14)—Offset 474h 0h

478h 47Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_15)—Offset 478h 0h

47Ch 47Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_15)—Offset 47Ch 0h

480h 483h Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_16)—Offset 480h 0h

484h 487h Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_16)—Offset 484h 28h

488h 48Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_17)—Offset 488h 0h

48Ch 48Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_17)—Offset 48Ch 0h

490h 493h Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_18)—Offset 490h 0h

494h 497h Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_18)—Offset 494h 0h

498h 49Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_19)—Offset 498h 0h

49Ch 49Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_19)—Offset 49Ch 0h

4A0h 4A3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_20)—Offset 4A0h 0h

4A4h 4A7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_20)—Offset 4A4h 0h

4A8h 4ABh Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_21)—Offset 4A8h 0h

4ACh 4AFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_21)—Offset 4ACh 0h

4B0h 4B3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_22)—Offset 4B0h 0h

4B4h 4B7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_22)—Offset 4B4h 0h

4B8h 4BBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_23)—Offset 4B8h 0h

4BCh 4BFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_23)—Offset 4BCh 0h

332219-002 413 GPIO for SKL PCH-H

Table 6-2. Summary of GPIO Community 1 Registers (Continued)

Offset Offset Default Register Name (ID)—Offset Start End Value

4C0h 4C3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_0)—Offset 4C0h 0h

4C4h 4C7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_0)—Offset 4C4h 0h

4C8h 4CBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_1)—Offset 4C8h 0h

4CCh 4CFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_1)—Offset 4CCh 0h

4D0h 4D3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_2)—Offset 4D0h 0h

4D4h 4D7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_2)—Offset 4D4h 0h

4D8h 4DBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_3)—Offset 4D8h 0h

4DCh 4DFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_3)—Offset 4DCh 0h

4E0h 4E3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_4)—Offset 4E0h 0h

4E4h 4E7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_4)—Offset 4E4h 0h

4E8h 4EBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_5)—Offset 4E8h 0h

4ECh 4EFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_5)—Offset 4ECh 0h

4F0h 4F3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_6)—Offset 4F0h 0h

4F4h 4F7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_6)—Offset 4F4h 0h

4F8h 4FBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_7)—Offset 4F8h 0h

4FCh 4FFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_7)—Offset 4FCh 0h

500h 503h Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_8)—Offset 500h 0h

504h 507h Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_8)—Offset 504h 0h

508h 50Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_9)—Offset 508h 0h

50Ch 50Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_9)—Offset 50Ch 0h

510h 513h Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_10)—Offset 510h 0h

514h 517h Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_10)—Offset 514h 0h

518h 51Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_11)—Offset 518h 0h

51Ch 51Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_11)—Offset 51Ch 0h

520h 523h Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_12)—Offset 520h 0h

524h 527h Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_12)—Offset 524h 0h

528h 52Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_13)—Offset 528h 0h

52Ch 52Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_13)—Offset 52Ch 0h

530h 533h Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_14)—Offset 530h 0h

534h 537h Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_14)—Offset 534h 0h

538h 53Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_15)—Offset 538h 0h

53Ch 53Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_15)—Offset 53Ch 0h

540h 543h Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_16)—Offset 540h 0h

544h 547h Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_16)—Offset 544h 0h

548h 54Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_17)—Offset 548h 0h

54Ch 54Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_17)—Offset 54Ch 0h

550h 553h Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_18)—Offset 550h 0h

554h 557h Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_18)—Offset 554h 0h

558h 55Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_19)—Offset 558h 0h

55Ch 55Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_19)—Offset 55Ch 0h

414 332219-002

GPIO for SKL PCH-H

Table 6-2. Summary of GPIO Community 1 Registers (Continued)

Offset Offset Default Register Name (ID)—Offset Start End Value

560h 563h Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_20)—Offset 560h 0h

564h 567h Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_20)—Offset 564h 0h

568h 56Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_21)—Offset 568h 0h

56Ch 56Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_21)—Offset 56Ch 0h

570h 573h Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_22)—Offset 570h 0h

574h 577h Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_22)—Offset 574h 0h

578h 57Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_23)—Offset 578h 0h

57Ch 57Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_23)—Offset 57Ch 0h

580h 583h Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_0)—Offset 580h 0h

584h 587h Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_0)—Offset 584h 0h

588h 58Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_1)—Offset 588h 0h

58Ch 58Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_1)—Offset 58Ch 0h

590h 593h Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_2)—Offset 590h 0h

594h 597h Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_2)—Offset 594h 0h

598h 59Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_3)—Offset 598h 0h

59Ch 59Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_3)—Offset 59Ch 0h

5A0h 5A3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_4)—Offset 5A0h 0h

5A4h 5A7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_4)—Offset 5A4h 0h

5A8h 5ABh Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_5)—Offset 5A8h 0h

5ACh 5AFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_5)—Offset 5ACh 0h

5B0h 5B3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_6)—Offset 5B0h 0h

5B4h 5B7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_6)—Offset 5B4h 0h

5B8h 5BBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_7)—Offset 5B8h 0h

5BCh 5BFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_7)—Offset 5BCh 0h

5C0h 5C3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_8)—Offset 5C0h 0h

5C4h 5C7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_8)—Offset 5C4h 0h

5C8h 5CBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_9)—Offset 5C8h 0h

5CCh 5CFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_9)—Offset 5CCh 0h

5D0h 5D3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_10)—Offset 5D0h 0h

5D4h 5D7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_10)—Offset 5D4h 0h

5D8h 5DBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_11)—Offset 5D8h 0h

5DCh 5DFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_11)—Offset 5DCh 0h

5E0h 5E3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_12)—Offset 5E0h 0h

5E4h 5E7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_12)—Offset 5E4h 0h

5E8h 5EBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_0)—Offset 5E8h 0h

5ECh 5EFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_0)—Offset 5ECh 0h

5F0h 5F3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_1)—Offset 5F0h 0h

5F4h 5F7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_1)—Offset 5F4h 0h

5F8h 5FBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_2)—Offset 5F8h 0h

5FCh 5FFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_2)—Offset 5FCh 0h

332219-002 415 GPIO for SKL PCH-H

Table 6-2. Summary of GPIO Community 1 Registers (Continued)

Offset Offset Default Register Name (ID)—Offset Start End Value

600h 603h Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_3)—Offset 600h 0h

604h 607h Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_3)—Offset 604h 0h

608h 60Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_4)—Offset 608h 0h

60Ch 60Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_4)—Offset 60Ch 0h

610h 613h Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_5)—Offset 610h 0h

614h 617h Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_5)—Offset 614h 0h

618h 61Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_6)—Offset 618h 0h

61Ch 61Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_6)—Offset 61Ch 0h

620h 623h Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_7)—Offset 620h 0h

624h 627h Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_7)—Offset 624h 0h

628h 62Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_8)—Offset 628h 0h

62Ch 62Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_8)—Offset 62Ch 0h

630h 633h Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_9)—Offset 630h 0h

634h 637h Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_9)—Offset 634h 0h

638h 63Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_10)—Offset 638h 0h

63Ch 63Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_10)—Offset 63Ch 0h

640h 643h Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_11)—Offset 640h 0h

644h 647h Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_11)—Offset 644h 0h

648h 64Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_12)—Offset 648h 0h

64Ch 64Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_12)—Offset 64Ch 0h

650h 653h Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_13)—Offset 650h 0h

654h 657h Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_13)—Offset 654h 0h

658h 65Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_14)—Offset 658h 0h

65Ch 65Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_14)—Offset 65Ch 0h

660h 663h Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_15)—Offset 660h 0h

664h 667h Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_15)—Offset 664h 0h

668h 66Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_16)—Offset 668h 0h

66Ch 66Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_16)—Offset 66Ch 0h

670h 673h Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_17)—Offset 670h 0h

674h 677h Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_17)—Offset 674h 0h

678h 67Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_18)—Offset 678h 0h

67Ch 67Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_18)—Offset 67Ch 0h

680h 683h Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_19)—Offset 680h 0h

684h 687h Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_19)—Offset 684h 0h

688h 68Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_20)—Offset 688h 0h

68Ch 68Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_20)—Offset 68Ch 0h

690h 693h Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_21)—Offset 690h 0h

694h 697h Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_21)—Offset 694h 0h

698h 69Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_22)—Offset 698h 0h

69Ch 69Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_22)—Offset 69Ch 0h

416 332219-002

GPIO for SKL PCH-H

Table 6-2. Summary of GPIO Community 1 Registers (Continued)

Offset Offset Default Register Name (ID)—Offset Start End Value

6A0h 6A3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_23)—Offset 6A0h 0h

6A4h 6A7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_23)—Offset 6A4h 0h

6A8h 6ABh Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_0)—Offset 6A8h 0h

6ACh 6AFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_0)—Offset 6ACh 0h

6B0h 6B3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_1)—Offset 6B0h 0h

6B4h 6B7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_1)—Offset 6B4h 0h

6B8h 6BBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_2)—Offset 6B8h 0h

6BCh 6BFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_2)—Offset 6BCh 0h

6C0h 6C3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_3)—Offset 6C0h 0h

6C4h 6C7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_3)—Offset 6C4h 0h

6C8h 6CBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_4)—Offset 6C8h 0h

6CCh 6CFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_4)—Offset 6CCh 0h

6D0h 6D3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_5)—Offset 6D0h 0h

6D4h 6D7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_5)—Offset 6D4h 0h

6D8h 6DBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_6)—Offset 6D8h 0h

6DCh 6DFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_6)—Offset 6DCh 0h

6E0h 6E3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_7)—Offset 6E0h 0h

6E4h 6E7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_7)—Offset 6E4h 0h

6E8h 6EBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_8)—Offset 6E8h 0h

6ECh 6EFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_8)—Offset 6ECh 0h

6F0h 6F3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_9)—Offset 6F0h 0h

6F4h 6F7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_9)—Offset 6F4h 0h

6F8h 6FBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_10)—Offset 6F8h 0h

6FCh 6FFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_10)—Offset 6FCh 0h

700h 703h Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_11)—Offset 700h 0h

704h 707h Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_11)—Offset 704h 0h

708h 70Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_12)—Offset 708h 0h

70Ch 70Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_12)—Offset 70Ch 0h

710h 713h Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_13)—Offset 710h 0h

714h 717h Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_13)—Offset 714h 0h

718h 71Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_14)—Offset 718h 0h

71Ch 71Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_14)—Offset 71Ch 0h

720h 723h Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_15)—Offset 720h 0h

724h 727h Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_15)—Offset 724h 0h

728h 72Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_16)—Offset 728h 0h

72Ch 72Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_16)—Offset 72Ch 0h

730h 733h Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_17)—Offset 730h 0h

734h 737h Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_17)—Offset 734h 0h

738h 73Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_18)—Offset 738h 0h

73Ch 73Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_18)—Offset 73Ch 0h

332219-002 417 GPIO for SKL PCH-H

Table 6-2. Summary of GPIO Community 1 Registers (Continued)

Offset Offset Default Register Name (ID)—Offset Start End Value

740h 743h Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_19)—Offset 740h 0h

744h 747h Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_19)—Offset 744h 0h

748h 74Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_20)—Offset 748h 0h

74Ch 74Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_20)—Offset 74Ch 0h

750h 753h Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_21)—Offset 750h 0h

754h 757h Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_21)—Offset 754h 0h

758h 75Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_22)—Offset 758h 0h

75Ch 75Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_22)—Offset 75Ch 0h

760h 763h Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_23)—Offset 760h 0h

764h 767h Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_23)—Offset 764h 0h

768h 76Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_0)—Offset 768h 0h

76Ch 76Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_0)—Offset 76Ch 0h

770h 773h Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_1)—Offset 770h 0h

774h 777h Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_1)—Offset 774h 0h

778h 77Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_2)—Offset 778h 0h

77Ch 77Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_2)—Offset 77Ch 0h

780h 783h Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_3)—Offset 780h 0h

784h 787h Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_3)—Offset 784h 0h

788h 78Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_4)—Offset 788h 0h

78Ch 78Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_4)—Offset 78Ch 0h

790h 793h Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_5)—Offset 790h 0h

794h 797h Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_5)—Offset 794h 0h

798h 79Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_6)—Offset 798h 0h

79Ch 79Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_6)—Offset 79Ch 0h

7A0h 7A3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_7)—Offset 7A0h 0h

7A4h 7A7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_7)—Offset 7A4h 0h

7A8h 7ABh Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_8)—Offset 7A8h 0h

7ACh 7AFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_8)—Offset 7ACh 0h

7B0h 7B3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_9)—Offset 7B0h 0h

7B4h 7B7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_9)—Offset 7B4h 0h

7B8h 7BBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_10)—Offset 7B8h 0h

7BCh 7BFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_10)—Offset 7BCh 0h

7C0h 7C3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_11)—Offset 7C0h 0h

7C4h 7C7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_11)—Offset 7C4h 0h

7C8h 7CBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_12)—Offset 7C8h 0h

7CCh 7CFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_12)—Offset 7CCh 0h

7D0h 7D3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_13)—Offset 7D0h 0h

7D4h 7D7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_13)—Offset 7D4h 0h

7D8h 7DBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_14)—Offset 7D8h 0h

7DCh 7DFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_14)—Offset 7DCh 0h

418 332219-002

GPIO for SKL PCH-H

Table 6-2. Summary of GPIO Community 1 Registers (Continued)

Offset Offset Default Register Name (ID)—Offset Start End Value

7E0h 7E3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_15)—Offset 7E0h 0h

7E4h 7E7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_15)—Offset 7E4h 0h

7E8h 7EBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_16)—Offset 7E8h 0h

7ECh 7EFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_16)—Offset 7ECh 0h

7F0h 7F3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_17)—Offset 7F0h 0h

7F4h 7F7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_17)—Offset 7F4h 0h

7F8h 7FBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_18)—Offset 7F8h 0h

7FCh 7FFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_18)—Offset 7FCh 0h

800h 803h Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_19)—Offset 800h 0h

804h 807h Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_19)—Offset 804h 0h

808h 80Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_20)—Offset 808h 0h

80Ch 80Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_20)—Offset 80Ch 0h

810h 813h Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_21)—Offset 810h 0h

814h 817h Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_21)—Offset 814h 0h

818h 81Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_22)—Offset 818h 0h

81Ch 81Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_22)—Offset 81Ch 0h

820h 823h Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_23)—Offset 820h 0h

824h 827h Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_23)—Offset 824h 0h

6.2.1 Family Base Address (FAMBAR)—Offset 8h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 300h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000001100000000 RSVD FAMBAR

Bit Default & Field Name (ID): Description Range Access

0h 31:16 Reserved. RO

Family Base Address (FAMBAR): This field provides the starting byte-align 300h address of Family0 register sets. It is meant for software to discover from where the 15:0 RO very first Family register (i.e. Family0 register) starts to compute the next Families address offsets.

332219-002 419 GPIO for SKL PCH-H

6.2.2 Pad Base Address (PADBAR)—Offset Ch

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 400h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000010000000000 RSVD PADBAR

Bit Default & Field Name (ID): Description Range Access

0h 31:16 Reserved. RO

400h Pad Base Address (PADBAR): This field provides the starting byte-align address of 15:0 Pad0 register sets. It is meant for software to discover from where the very first Pad RO register (i.e. Pad0 register) starts to compute the next Pad address offsets.

6.2.3 Miscellaneous Configuration (MISCCFG)—Offset 10h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 43200h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000001000011001000000000 RSVD RSVD GPDLCGEN GPDPCGEN GPE0_DW2 GPE0_DW1 GPE0_DW0 GSXSLCGEN GPIO_DRIVER_IRQ_ROUTE

420 332219-002

GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h 31:20 Reserved. RO

GPIO Group to GPE_DW0 assignment encoding (GPE0_DW2): This register assigns a specific GPIO Group to the ACPI GPE0[95:64]. The selected GPIO group will be mapped to lower bits of the GPE register 0h = GPP_A[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 1h = GPP_B[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 4h 2h = GPP_C[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 19:16 3h = GPP_D[23:0] mapped to GPE[87:64]; GPE[95:88] not used. RW 4h = GPP_E[12:0] mapped to GPE[76:64]; GPE[95:77] not used. 5h = GPP_F[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 6h = GPP_G[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 7h = GPP_H[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 8h = GPP_I[10:0] mapped to GPE[74:64]; GPE[95:75] not used. 9h = GPD[11:0] mapped to GPE[75:64]; GPE[95:76] not used.

GPIO Group to GPE_DW0 assignment encoding (GPE0_DW1): This register assigns a specific GPIO Group to the ACPI GPE0[63:32]. The selected GPIO group will be mapped to lower bits of the GPE register 0h = GPP_A[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 1h = GPP_B[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 3h 2h = GPP_C[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 15:12 3h = GPP_D[23:0] mapped to GPE[55:32]; GPE[63:56] not used. RW 4h = GPP_E[12:0] mapped to GPE[44:32]; GPE[63:45] not used. 5h = GPP_F[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 6h = GPP_G[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 7h = GPP_H[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 8h = GPP_I[10:0] mapped to GPE[42:32]; GPE[63:43] not used. 9h = GPD[11:0] mapped to GPE[43:32]; GPE[63:44] not used.

GPIO Group to GPE_DW0 assignment encoding (GPE0_DW0): This register assigns a specific GPIO Group to the ACPI GPE0[31:0]. The selected GPIO group will be mapped to lower bits of the GPE register 0h = GPP_A[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 1h = GPP_B[23:0] mapped to GPE[23:0]; GPE[31:24] not used.

2h 2h = GPP_C[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 11:8 3h = GPP_D[23:0] mapped to GPE[23:0]; GPE[31:24] not used. RW 4h = GPP_E[12:0] mapped to GPE[12:0]; GPE[31:13] not used. 5h = GPP_F[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 6h = GPP_G[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 7h = GPP_H[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 8h = GPP_I[10:0] mapped to GPE[10:0]; GPE[31:11] not used. 9h = GPD[11:0] mapped to GPE[11:0]; GPE[31:12] not used.

0h 7:4 Reserved. RO

GPIO Driver IRQ Route (GPIO_DRIVER_IRQ_ROUTE): GPIO Driver 0h IRQ_ROUTE[1:0]: Specifies the APIC IRQ globally for all pads within the current 3 community (GPI_IS with corresponding GPI_IE enable). RW 0 = IRQ14 1 = IRQ15

GSX Static Local Clock Gating (GSXSLCGEN): GSX Static Local Clock Gating 0h (GSXSLCGEn) Specify whether the GSX controller should be statically clock gated for 2 RW power saving if it is not enabled (even though the capability is available). 0 = Disable dynamic local clock gating 1 = Enable dynamic local clock gating

GPIO Dynamic Partition Clock Gating Enable (GPDPCGEN): Specifies whether 0h the GPIO Community should take part in partition clock gating 1 RW 0 = Disable participation in dynamic partition clock gating 1 = Enable participation in dynamic partition clock gating

GPIO Dynamic Local Clock Gating Enable (GPDLCGEN): Specifies whether the 0h 0 GPIO Community should perform local clock gating. RW 0 = Disable dynamic local clock gating 1 = Enable dynamic local clock gating.

6.2.4 Pad Ownership (PAD_OWN_GPP_C_0)—Offset 20h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

332219-002 421 GPIO for SKL PCH-H

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD PAD_OWN_GPP_C_7 PAD_OWN_GPP_C_6 PAD_OWN_GPP_C_5 PAD_OWN_GPP_C_4 PAD_OWN_GPP_C_3 PAD_OWN_GPP_C_2 PAD_OWN_GPP_C_1 PAD_OWN_GPP_C_0

Bit Default & Field Name (ID): Description Range Access

0h 31:30 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_C_7): Same description as bit 0, except that 29:28 RO the bit field applies to GPP_C7.

0h 27:26 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_C_6): Same description as bit 0, except that 25:24 RO the bit field applies to GPP_C6.

0h 23:22 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_C_5): Same description as bit 0, except that 21:20 RO the bit field applies to GPP_C5.

0h 19:18 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_C_4): Same description as bit 0, except that 17:16 RO the bit field applies to GPP_C4.

0h 15:14 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_C_3): Same description as bit 0, except that 13:12 RO the bit field applies to GPP_C3.

0h 11:10 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_C_2): Same description as bit 0, except that 9:8 RO the bit field applies to GPP_C2.

0h 7:6 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_C_1): Same description as bit 0, except that 5:4 RO the bit field applies to GPP_C1.

0h 3:2 Reserved. RO

Pad Ownership (PAD_OWN_GPP_C_0): 00 = Host GPIO ACPI Mode or GPIO Driver Mode. Host software (ACPI or GPIO Driver) has ownership of the pad. In Host GPIO Driver Mode (refer to HOSTSW_OWN), GPIO input event update is limited to 0h GPI_STS update only. Otherwise in Host ACPI Mode, updates are limited to 1:0 RO GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. 01 = ME GPIO Mode. ME has ownership of the pad. 10 = ISH GPIO Mode.ME has ownership of the pad 11 = Reserved

422 332219-002

GPIO for SKL PCH-H

6.2.5 Pad Ownership (PAD_OWN_GPP_C_1)—Offset 24h

Same description as PAD_OWN_GPP_C_0, except that this register is for GPP_C[15:8]

6.2.6 Pad Ownership (PAD_OWN_GPP_C_2)—Offset 28h

Same description as PAD_OWN_GPP_C_0, except that this register is for GPP_C[23:16]

6.2.7 Pad Ownership (PAD_OWN_GPP_D_0)—Offset 2Ch

Same description as PAD_OWN_GPP_C_0, except that this register is for GPP_D[7:0]

6.2.8 Pad Ownership (PAD_OWN_GPP_D_1)—Offset 30h

Same description as PAD_OWN_GPP_C_0, except that this register is for GPP_D[15:8]

6.2.9 Pad Ownership (PAD_OWN_GPP_D_2)—Offset 34h

Same description as PAD_OWN_GPP_C_0, except that this register is for GPP_D[23:16]

6.2.10 Pad Ownership (PAD_OWN_GPP_E_0)—Offset 38h

Same description as PAD_OWN_GPP_C_0, except that this register is for GPP_E[7:0]

6.2.11 Pad Ownership (PAD_OWN_GPP_E_1)—Offset 3Ch

Same description as PAD_OWN_GPP_C_0, except that this register is for GPP_E[12:8]

6.2.12 Pad Ownership (PAD_OWN_GPP_F_0)—Offset 40h

Same description as PAD_OWN_GPP_C_0, except that this register is for GPP_F[7:0]

6.2.13 Pad Ownership (PAD_OWN_GPP_F_1)—Offset 44h

Same description as PAD_OWN_GPP_C_0, except that this register is for GPP_F[15:8]

6.2.14 Pad Ownership (PAD_OWN_GPP_F_2)—Offset 48h

Same description as PAD_OWN_GPP_C_0, except that this register is for GPP_F[23:16]

6.2.15 Pad Ownership (PAD_OWN_GPP_G_0)—Offset 4Ch

Same description as PAD_OWN_GPP_C_0, except that this register is for GPP_G[7:0]

6.2.16 Pad Ownership (PAD_OWN_GPP_G_1)—Offset 50h

Same description as PAD_OWN_GPP_C_0, except that this register is for GPP_G[15:8]

6.2.17 Pad Ownership (PAD_OWN_GPP_G_2)—Offset 54h

Same description as PAD_OWN_GPP_C_0, except that this register is for GPP_G[23:16]

332219-002 423 GPIO for SKL PCH-H

6.2.18 Pad Ownership (PAD_OWN_GPP_H_0)—Offset 58h

Same description as PAD_OWN_GPP_C_0, except that this register is for GPP_H[7:0]

6.2.19 Pad Ownership (PAD_OWN_GPP_H_1)—Offset 5Ch

Same description as PAD_OWN_GPP_C_0, except that this register is for GPP_H[15:8]

6.2.20 Pad Ownership (PAD_OWN_GPP_H_2)—Offset 60h

Same description as PAD_OWN_GPP_C_0, except that this register is for GPP_H[23:16]

6.2.21 Pad Configuration Lock (PADCFGLOCK_GPP_C_0)—Offset 90h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD PADCFGLOCK_GPP_C_9 PADCFGLOCK_GPP_C_8 PADCFGLOCK_GPP_C_7 PADCFGLOCK_GPP_C_6 PADCFGLOCK_GPP_C_5 PADCFGLOCK_GPP_C_4 PADCFGLOCK_GPP_C_3 PADCFGLOCK_GPP_C_2 PADCFGLOCK_GPP_C_1 PADCFGLOCK_GPP_C_0 PADCFGLOCK_GPP_C_23 PADCFGLOCK_GPP_C_22 PADCFGLOCK_GPP_C_21 PADCFGLOCK_GPP_C_20 PADCFGLOCK_GPP_C_19 PADCFGLOCK_GPP_C_18 PADCFGLOCK_GPP_C_17 PADCFGLOCK_GPP_C_16 PADCFGLOCK_GPP_C_15 PADCFGLOCK_GPP_C_14 PADCFGLOCK_GPP_C_13 PADCFGLOCK_GPP_C_12 PADCFGLOCK_GPP_C_11 PADCFGLOCK_GPP_C_10

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h Pad Config Lock (PADCFGLOCK_GPP_C_23): Applied to GPP_C23. Same 23 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_22): Applied to GPP_C22. Same 22 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_21): Applied to GPP_C21. Same 21 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_20): Applied to GPP_C20. Same 20 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_19): Applied to GPP_C19. Same 19 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_18): Applied to GPP_C18. Same 18 RW description as bit 0.

424 332219-002

GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h Pad Config Lock (PADCFGLOCK_GPP_C_17): Applied to GPP_C17. Same 17 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_16): Applied to GPP_C16. Same 16 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_15): Applied to GPP_C15. Same 15 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_14): Applied to GPP_C14. Same 14 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_13): Applied to GPP_C13. Same 13 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_12): Applied to GPP_C12. Same 12 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_11): Applied to GPP_C11. Same 11 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_10): Applied to GPP_C10. Same 10 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_9): Applied to GPP_C9. Same 9 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_8): Applied to GPP_C8. Same 8 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_7): Applied to GPP_C7. Same 7 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_6): Applied to GPP_C6. Same 6 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_5): Applied to GPP_C5. Same 5 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_4): Applied to GPP_C4. Same 4 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_3): Applied to GPP_C3. Same 3 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_2): Applied to GPP_C2. Same 2 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_1): Applied to GPP_C1. Same 1 RW description as bit 0.

Pad Config Lock (PADCFGLOCK_GPP_C_0): Pad Configuration Lock locks specific register fields in the GPP specific registers from being configured. The registers affected become Read-Only and software writes to these registers have no effect. 0 = Unlock 1 = Lock the following register fields as read-only (RO): 0h - Pad Configuration registers (exclude GPIOTXState) 0 RW - GPI_NMI_EN Register (if implemented) - GPI_SMI_EN Register (if implemented) - GPI_GPE_EN Register (if implemented) When PadCfgLock bit is written from a '1' to a '0' (unlock), a synchronous SMI# is generated if enabled. This ensures that only SMM code can change the above GPIO registers after the lockdown.

6.2.22 Pad Configuration Lock (PADCFGLOCKTX_GPP_C_0)— Offset 94h

Access Method

332219-002 425 GPIO for SKL PCH-H

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD PADCFGLOCKTX_GPP_C_9 PADCFGLOCKTX_GPP_C_8 PADCFGLOCKTX_GPP_C_7 PADCFGLOCKTX_GPP_C_6 PADCFGLOCKTX_GPP_C_5 PADCFGLOCKTX_GPP_C_4 PADCFGLOCKTX_GPP_C_3 PADCFGLOCKTX_GPP_C_2 PADCFGLOCKTX_GPP_C_1 PADCFGLOCKTX_GPP_C_0 PADCFGLOCKTX_GPP_C_23 PADCFGLOCKTX_GPP_C_22 PADCFGLOCKTX_GPP_C_21 PADCFGLOCKTX_GPP_C_20 PADCFGLOCKTX_GPP_C_19 PADCFGLOCKTX_GPP_C_18 PADCFGLOCKTX_GPP_C_17 PADCFGLOCKTX_GPP_C_16 PADCFGLOCKTX_GPP_C_15 PADCFGLOCKTX_GPP_C_14 PADCFGLOCKTX_GPP_C_13 PADCFGLOCKTX_GPP_C_12 PADCFGLOCKTX_GPP_C_11 PADCFGLOCKTX_GPP_C_10

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_23): Applied to GPP_C23. 23 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_22): Applied to GPP_C22. 22 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_21): Applied to GPP_C21. 21 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_20): Applied to GPP_C20. 20 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_19): Applied to GPP_C19. 19 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_18): Applied to GPP_C18. 18 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_17): Applied to GPP_C17. 17 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_16): Applied to GPP_C16. 16 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_15): Applied to GPP_C15. 15 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_14): Applied to GPP_C14. 14 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_13): Applied to GPP_C13. 13 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_12): Applied to GPP_C12. 12 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_11): Applied to GPP_C11. 11 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_10): Applied to GPP_C10. 10 RW Same description as bit 0.

426 332219-002

GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_9): Applied to GPP_C9. 9 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_8): Applied to GPP_C8. 8 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_7): Applied to GPP_C7. 7 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_6): Applied to GPP_C6. 6 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_5): Applied to GPP_C5. 5 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_4): Applied to GPP_C4. 4 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_3): Applied to GPP_C1. 3 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_2): Applied to GPP_C1. 2 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_1): Applied to GPP_C1. 1 RW Same description as bit 0.

Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_0): PadCfgLockTx locks the GPIOTxState bit from being configured. The GPIOTxState register becomes Read- Only and software writes to the register have no effect. 0h 0 0 = Unlock RW 1 = Locks the Pad Configuration GPIOTXState field as read-only (RO) When PadCfgLockTx is written from a '1' to a '0' (unlock), a synchronous SMI# is generated if enabled. This ensures that only SMM code can change the above GPIO registers after the lockdown.

6.2.23 Pad Configuration Lock (PADCFGLOCK_GPP_D_0)—Offset 98h

Same description as PADCFGLOCK_GPP_C_0 register, except this register applies to GPP_D group only.

6.2.24 Pad Configuration Lock (PADCFGLOCKTX_GPP_D_0)— Offset 9Ch

Same description as PADCFGLOCKTX_GPP_C_0 register, except this register applies to GPP_D group only.

6.2.25 Pad Configuration Lock (PADCFGLOCK_GPP_E_0)—Offset A0h

Same description as PADCFGLOCK_GPP_C_0 register, except this register applies to GPP_E group only.

6.2.26 Pad Configuration Lock (PADCFGLOCKTX_GPP_E_0)— Offset A4h

Same description as PADCFGLOCKTX_GPP_C_0 register, except this register applies to GPP_E group only.

332219-002 427 GPIO for SKL PCH-H

6.2.27 Pad Configuration Lock (PADCFGLOCK_GPP_F_0)—Offset A8h

Same description as PADCFGLOCK_GPP_C_0 register, except this register applies to GPP_F group only.

6.2.28 Pad Configuration Lock (PADCFGLOCKTX_GPP_F_0)— Offset ACh

Same description as PADCFGLOCKTX_GPP_C_0 register, except this register applies to GPP_F group only.

6.2.29 Pad Configuration Lock (PADCFGLOCK_GPP_G_0)—Offset B0h

Same description as PADCFGLOCK_GPP_C_0 register, except this register applies to GPP_G group only.

6.2.30 Pad Configuration Lock (PADCFGLOCKTX_GPP_G_0)— Offset B4h

Same description as PADCFGLOCKTX_GPP_C_0 register, except this register applies to GPP_G group only.

6.2.31 Pad Configuration Lock (PADCFGLOCK_GPP_H_0)—Offset B8h

Same description as PADCFGLOCK_GPP_C_0 register, except this register applies to GPP_H group only.

6.2.32 Pad Configuration Lock (PADCFGLOCKTX_GPP_H_0)— Offset BCh

Same description as PADCFGLOCKTX_GPP_C_0 register, except this register applies to GPP_H group only.

6.2.33 Host Software Pad Ownership (HOSTSW_OWN_GPP_C_0)—Offset D0h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

428 332219-002

GPIO for SKL PCH-H

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD HOSTSW_OWN_GPP_C_9 HOSTSW_OWN_GPP_C_8 HOSTSW_OWN_GPP_C_7 HOSTSW_OWN_GPP_C_6 HOSTSW_OWN_GPP_C_5 HOSTSW_OWN_GPP_C_4 HOSTSW_OWN_GPP_C_3 HOSTSW_OWN_GPP_C_2 HOSTSW_OWN_GPP_C_1 HOSTSW_OWN_GPP_C_0 HOSTSW_OWN_GPP_C_23 HOSTSW_OWN_GPP_C_22 HOSTSW_OWN_GPP_C_21 HOSTSW_OWN_GPP_C_20 HOSTSW_OWN_GPP_C_19 HOSTSW_OWN_GPP_C_18 HOSTSW_OWN_GPP_C_17 HOSTSW_OWN_GPP_C_16 HOSTSW_OWN_GPP_C_15 HOSTSW_OWN_GPP_C_14 HOSTSW_OWN_GPP_C_13 HOSTSW_OWN_GPP_C_12 HOSTSW_OWN_GPP_C_11 HOSTSW_OWN_GPP_C_10

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h HostSW_Own (HOSTSW_OWN_GPP_C_23): Applied to GPP_C23. Same 23 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_22): Applied to GPP_C22. Same 22 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_21): Applied to GPP_C21. Same 21 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_20): Applied to GPP_C20. Same 20 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_19): Applied to GPP_C19. Same 19 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_18): Applied to GPP_C8. Same 18 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_17): Applied to GPP_C17. Same 17 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_16): Applied to GPP_C16. Same 16 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_15): Applied to GPP_C15. Same 15 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_14): Applied to GPP_C14. Same 14 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_13): Applied to GPP_C13. Same 13 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_12): Applied to GPP_C12. Same 12 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_11): Applied to GPP_C11. Same 11 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_10): Applied to GPP_C10. Same 10 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_9): Applied to GPP_C9. Same description 9 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_8): Applied to GPP_C8. Same description 8 RW as bit 0.

332219-002 429 GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h HostSW_Own (HOSTSW_OWN_GPP_C_7): Applied to GPP_C7. Same description 7 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_6): Applied to GPP_C6. Same description 6 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_5): Applied to GPP_C5. Same description 5 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_4): Applied to GPP_C4. Same description 4 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_3): Applied to GPP_C3. Same description 3 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_2): Applied to GPP_C2. Same description 2 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_1): Applied to GPP_C1. Same description 1 RW as bit 0.

HostSW_Own (HOSTSW_OWN_GPP_C_0): This register determines the appropriate host status bit update when a pad is under host ownership. 0h 0 = ACPI Mode. GPIO input event updates are limited to GPI_GPE_STS, 0 RW GPI_NMI_STS and/or GPI_SMI_STS. GPI_STS update is masked. 1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked.

6.2.34 Host Software Pad Ownership (HOSTSW_OWN_GPP_D_0)—Offset D4h

Same description as HOSTSW_OWN_GPP_C_0 register, except that this register applies to GPP_D group only.

6.2.35 Host Software Pad Ownership (HOSTSW_OWN_GPP_E_0)—Offset D8h

Same description as HOSTSW_OWN_GPP_C_0 register, except that this register applies to GPP_E group only.

6.2.36 Host Software Pad Ownership (HOSTSW_OWN_GPP_F_0)—Offset DCh

Same description as HOSTSW_OWN_GPP_C_0 register, except that this register applies to GPP_F group only.

6.2.37 Host Software Pad Ownership (HOSTSW_OWN_GPP_G_0)—Offset E0h

Same description as HOSTSW_OWN_GPP_C_0 register, except that this register applies to GPP_G group only.

6.2.38 Host Software Pad Ownership (HOSTSW_OWN_GPP_H_0)—Offset E4h

Same description as HOSTSW_OWN_GPP_C_0 register, except that this register applies to GPP_H group only.

430 332219-002

GPIO for SKL PCH-H

6.2.39 GPI Interrupt Status (GPI_IS_GPP_C_0)—Offset 100h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_INT_STS_GPP_C_9 GPI_INT_STS_GPP_C_8 GPI_INT_STS_GPP_C_7 GPI_INT_STS_GPP_C_6 GPI_INT_STS_GPP_C_5 GPI_INT_STS_GPP_C_4 GPI_INT_STS_GPP_C_3 GPI_INT_STS_GPP_C_2 GPI_INT_STS_GPP_C_1 GPI_INT_STS_GPP_C_0 GPI_INT_STS_GPP_C_23 GPI_INT_STS_GPP_C_22 GPI_INT_STS_GPP_C_21 GPI_INT_STS_GPP_C_20 GPI_INT_STS_GPP_C_19 GPI_INT_STS_GPP_C_18 GPI_INT_STS_GPP_C_17 GPI_INT_STS_GPP_C_16 GPI_INT_STS_GPP_C_15 GPI_INT_STS_GPP_C_14 GPI_INT_STS_GPP_C_13 GPI_INT_STS_GPP_C_12 GPI_INT_STS_GPP_C_11 GPI_INT_STS_GPP_C_10

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_23): Applied to GPP_C23. Same 23 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_22): Applied to GPP_C22. Same 22 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_21): Applied to GPP_C21. Same 21 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_20): Applied to GPP_C20. Same 20 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_19): Applied to GPP_C19. Same 19 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_18): Applied to GPP_C18. Same 18 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_17): Applied to GPP_C17. Same 17 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_16): Applied to GPP_C16. Same 16 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_15): Applied to GPP_C15. Same 15 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_14): Applied to GPP_C14. Same 14 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_13): Applied to GPP_C13. Same 13 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_12): Applied to GPP_C12. Same 12 RW1C description as bit 0.

332219-002 431 GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_11): Applied to GPP_C11. Same 11 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_10): Applied to GPP_C10. Same 10 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_9): Applied to GPP_C9. Same 9 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_8): Applied to GPP_C8. Same 8 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_7): Applied to GPP_C7. Same 7 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_6): Applied to GPP_C6. Same 6 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_5): Applied to GPP_C5. Same 5 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_4): Applied to GPP_C4. Same 4 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_3): Applied to GPP_C3. Same 3 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_2): Applied to GPP_C2. Same 2 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_1): Applied to GPP_C1. Same 1 RW1C description as bit 0.

GPI Interrupt Status (GPI_INT_STS_GPP_C_0): This bit is set to ‘1’ by hardware when either an edge or a level event is detected (See RxEdCfg RxInv) on pad and all the following conditions are true: 0h - The corresponding pad is used in GPIO input mode 0 - HOSTSW_OWN = 1 (i.e. Host GPIO Driver Mode). RW1C Writing a value of 1 will clear the bit while writing a value of 0 has no effect. 0 = No interrupt 1 = Interrupt asserts The state of GPI_INT_EN[x] does not prevent the setting of GPI_INT_STS[x].

6.2.40 GPI Interrupt Status (GPI_IS_GPP_D_0)—Offset 104h

Same description as GPI_IS_GPP_C_0 register, except that this register applies to GPP_D group only.

6.2.41 GPI Interrupt Status (GPI_IS_GPP_E_0)—Offset 108h

Same description as GPI_IS_GPP_C_0 register, except that this register applies to GPP_E group only.

6.2.42 GPI Interrupt Status (GPI_IS_GPP_F_0)—Offset 10Ch

Same description as GPI_IS_GPP_C_0 register, except that this register applies to GPP_F group only.

6.2.43 GPI Interrupt Status (GPI_IS_GPP_G_0)—Offset 110h

Same description as GPI_IS_GPP_C_0 register, except that this register applies to GPP_G group only.

432 332219-002

GPIO for SKL PCH-H

6.2.44 GPI Interrupt Status (GPI_IS_GPP_H_0)—Offset 114h

Same description as GPI_IS_GPP_C_0 register, except that this register applies to GPP_H group only.

6.2.45 GPI Interrupt Enable (GPI_IE_GPP_C_0)—Offset 120h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_INT_EN_GPP_C_9 GPI_INT_EN_GPP_C_8 GPI_INT_EN_GPP_C_7 GPI_INT_EN_GPP_C_6 GPI_INT_EN_GPP_C_5 GPI_INT_EN_GPP_C_4 GPI_INT_EN_GPP_C_3 GPI_INT_EN_GPP_C_2 GPI_INT_EN_GPP_C_1 GPI_INT_EN_GPP_C_0 GPI_INT_EN_GPP_C_23 GPI_INT_EN_GPP_C_22 GPI_INT_EN_GPP_C_21 GPI_INT_EN_GPP_C_20 GPI_INT_EN_GPP_C_19 GPI_INT_EN_GPP_C_18 GPI_INT_EN_GPP_C_17 GPI_INT_EN_GPP_C_16 GPI_INT_EN_GPP_C_15 GPI_INT_EN_GPP_C_14 GPI_INT_EN_GPP_C_13 GPI_INT_EN_GPP_C_12 GPI_INT_EN_GPP_C_11 GPI_INT_EN_GPP_C_10

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_23): Applied to GPP_C23. Same 23 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_22): Applied to GPP_C22. Same 22 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_21): Applied to GPP_C21. Same 21 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_20): Applied to GPP_C20. Same 20 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_19): Applied to GPP_C19. Same 19 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_18): Applied to GPP_C18. Same 18 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_17): Applied to GPP_C17. Same 17 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_16): Applied to GPP_C16. Same 16 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_15): Applied to GPP_C15. Same 15 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_14): Applied to GPP_C14. Same 14 RW description as bit 0.

332219-002 433 GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_13): Applied to GPP_C13. Same 13 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_12): Applied to GPP_C12. Same 12 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_11): Applied to GPP_C11. Same 11 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_10): Applied to GPP_C10. Same 10 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_9): Applied to GPP_C9. Same 9 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_8): Applied to GPP_C8. Same 8 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_7): Applied to GPP_C7. Same 7 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_6): Applied to GPP_C6. Same 6 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_5): Applied to GPP_C5. Same 5 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_4): Applied to GPP_C4. Same 4 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_3): Applied to GPP_C3. Same 3 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_2): Applied to GPP_C2. Same 2 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_1): Applied to GPP_C1. Same 1 RW description as bit 0.

GPI Interrupt Enable (GPI_INT_EN_GPP_C_0): This bit is used to enable/ disable the generation of APIC interrupt when the corresponding GPI_INT_STS bit is 0h set. 0 RW 0 = disable interrupt generation 1 = enable interrupt generation Refer to GPI_IRQ_ROUTE for host GPIO Driver Mode interrupt routing.

6.2.46 GPI Interrupt Enable (GPI_IE_GPP_D_0)—Offset 124h

Same description as GPI_IE_GPP_C_0 register, except that this register is for GPP_D group only.

6.2.47 GPI Interrupt Enable (GPI_IE_GPP_E_0)—Offset 128h

Same description as GPI_IE_GPP_C_0 register, except that this register is for GPP_E group only.

6.2.48 GPI Interrupt Enable (GPI_IE_GPP_F_0)—Offset 12Ch

Same description as GPI_IE_GPP_C_0 register, except that this register is for GPP_F group only.

434 332219-002

GPIO for SKL PCH-H

6.2.49 GPI Interrupt Enable (GPI_IE_GPP_G_0)—Offset 130h

Same description as GPI_IE_GPP_C_0 register, except that this register is for GPP_G group only.

6.2.50 GPI Interrupt Enable (GPI_IE_GPP_H_0)—Offset 134h

Same description as GPI_IE_GPP_C_0 register, except that this register is for GPP_H group only.

6.2.51 GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_0)—Offset 140h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_GPE_STS_GPP_C_9 GPI_GPE_STS_GPP_C_8 GPI_GPE_STS_GPP_C_7 GPI_GPE_STS_GPP_C_6 GPI_GPE_STS_GPP_C_5 GPI_GPE_STS_GPP_C_4 GPI_GPE_STS_GPP_C_3 GPI_GPE_STS_GPP_C_2 GPI_GPE_STS_GPP_C_1 GPI_GPE_STS_GPP_C_0 GPI_GPE_STS_GPP_C_23 GPI_GPE_STS_GPP_C_22 GPI_GPE_STS_GPP_C_21 GPI_GPE_STS_GPP_C_20 GPI_GPE_STS_GPP_C_19 GPI_GPE_STS_GPP_C_18 GPI_GPE_STS_GPP_C_17 GPI_GPE_STS_GPP_C_16 GPI_GPE_STS_GPP_C_15 GPI_GPE_STS_GPP_C_14 GPI_GPE_STS_GPP_C_13 GPI_GPE_STS_GPP_C_12 GPI_GPE_STS_GPP_C_11 GPI_GPE_STS_GPP_C_10

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_23): Applied to 23 RW1C GPP_C23. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_22): Applied to 22 RW1C GPP_C22. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_21): Applied to 21 RW1C GPP_C21. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_20): Applied to 20 RW1C GPP_C20. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_19): Applied to 19 RW1C GPP_C19. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_18): Applied to 18 RW1C GPP_C18. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_17): Applied to 17 RW1C GPP_C17. Same description as bit 0.

332219-002 435 GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_16): Applied to 16 RW1C GPP_C16. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_15): Applied to 15 RW1C GPP_C15. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_14): Applied to 14 RW1C GPP_C14. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_13): Applied to 13 RW1C GPP_C13. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_12): Applied to 12 RW1C GPP_C12. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_11): Applied to 11 RW1C GPP_C11. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_10): Applied to 10 RW1C GPP_C10. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_9): Applied to 9 RW1C GPP_C9. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_8): Applied to 8 RW1C GPP_C8. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_7): Applied to 7 RW1C GPP_C7. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_6): Applied to 6 RW1C GPP_C6. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_5): Applied to 5 RW1C GPP_C5. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_4): Applied to 4 RW1C GPP_C4. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_3): Applied to 3 RW1C GPP_C3. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_2): Applied to 2 RW1C GPP_C2. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_1): Applied to 1 RW1C GPP_C1. Same description as bit 0.

GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_0): These bits are set any time the corresponding GPIO pad is set up as an input, under host ownership and the corresponding GPIO signal is high(or low if the corresponding RXINV bit is set). 0h If the corresponding enable bit is set in the GPI_GPE_EN register, then when the 0 GPI_GPE_STS bit is set: RW1C - If the system is in an S3-S5 state, the event will also wake the system. - If the system is in an S0 state (or upon waking back to an S0 state), an SCI will be caused, depending on the GPIRoutSCI bit for the corresponding pad. These bits are sticky bits and are cleared by writing a 1 back to this bit position. The state of GPI_GPE_EN does not prevent the setting of GPI_GPE_STS.

6.2.52 GPI General Purpose Events Status (GPI_GPE_STS_GPP_D_0)—Offset 144h

Same description as GPI_GPE_STS_GPP_C_0 register, except that this register is for GPP_D group only.

436 332219-002

GPIO for SKL PCH-H

6.2.53 GPI General Purpose Events Status (GPI_GPE_STS_GPP_E_0)—Offset 148h

Same description as GPI_GPE_STS_GPP_C_0 register, except that this register is for GPP_E group only.

6.2.54 GPI General Purpose Events Status (GPI_GPE_STS_GPP_F_0)—Offset 14Ch

Same description as GPI_GPE_STS_GPP_C_0 register, except that this register is for GPP_F group only.

6.2.55 GPI General Purpose Events Status (GPI_GPE_STS_GPP_G_0)—Offset 150h

Same description as GPI_GPE_STS_GPP_C_0 register, except that this register is for GPP_G group only.

6.2.56 GPI General Purpose Events Status (GPI_GPE_STS_GPP_H_0)—Offset 154h

Same description as GPI_GPE_STS_GPP_C_0 register, except that this register is for GPP_H group only.

6.2.57 GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_0)—Offset 160h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_GPE_EN_GPP_C_9 GPI_GPE_EN_GPP_C_8 GPI_GPE_EN_GPP_C_7 GPI_GPE_EN_GPP_C_6 GPI_GPE_EN_GPP_C_5 GPI_GPE_EN_GPP_C_4 GPI_GPE_EN_GPP_C_3 GPI_GPE_EN_GPP_C_2 GPI_GPE_EN_GPP_C_1 GPI_GPE_EN_GPP_C_0 GPI_GPE_EN_GPP_C_23 GPI_GPE_EN_GPP_C_22 GPI_GPE_EN_GPP_C_21 GPI_GPE_EN_GPP_C_20 GPI_GPE_EN_GPP_C_19 GPI_GPE_EN_GPP_C_18 GPI_GPE_EN_GPP_C_17 GPI_GPE_EN_GPP_C_16 GPI_GPE_EN_GPP_C_15 GPI_GPE_EN_GPP_C_14 GPI_GPE_EN_GPP_C_13 GPI_GPE_EN_GPP_C_12 GPI_GPE_EN_GPP_C_11 GPI_GPE_EN_GPP_C_10

332219-002 437 GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_23): Applied to 23 RW GPP_C23. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_22): Applied to 22 RW GPP_C22. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_21): Applied to 21 RW GPP_C21. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_20): Applied to 20 RW GPP_C20. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_19): Applied to 19 RW GPP_C19. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_18): Applied to 18 RW GPP_C18. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_17): Applied to 17 RW GPP_C17. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_16): Applied to 16 RW GPP_C16. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_15): Applied to 15 RW GPP_C15. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_14): Applied to 14 RW GPP_C14. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_13): Applied to 13 RW GPP_C13. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_12): Applied to 12 RW GPP_C12. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_11): Applied to 11 RW GPP_C11. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_10): Applied to 10 RW GPP_C10. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_9): Applied to 9 RW GPP_C9. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_8): Applied to 8 RW GPP_C8. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_7): Applied to 7 RW GPP_C7. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_6): Applied to 6 RW GPP_C6. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_5): Applied to 5 RW GPP_C5. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_4): Applied to 4 RW GPP_C4. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_3): Applied to 3 RW GPP_C3. Same description as bit 0.

438 332219-002

GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_2): Applied to 2 RW GPP_C2. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_1): Applied to 1 RW GPP_C1. Same description as bit 0.

GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_0): This bit is used to enable/disable the generation of GPE to cause SCI and/or wake when the

0h corresponding GPI_GPE_STS bit is set. 0 0 = disable GPE generation RW 1 = enable GPE generation Note: The pad must also be routed for GPE functionality in order for GPE to be generated, i.e. the corresponding GPIRoutSCI must be set to ‘1’.

6.2.58 GPI General Purpose Events Enable (GPI_GPE_EN_GPP_D_0)—Offset 164h

Same description as GPI_GPE_EN_GPP_C_0 register, except that this register is for GPP_D group only.

6.2.59 GPI General Purpose Events Enable (GPI_GPE_EN_GPP_E_0)—Offset 168h

Same description as GPI_GPE_EN_GPP_C_0 register, except that this register is for GPP_E group only.

6.2.60 GPI General Purpose Events Enable (GPI_GPE_EN_GPP_F_0)—Offset 16Ch

Same description as GPI_GPE_EN_GPP_C_0 register, except that this register is for GPP_F group only.

6.2.61 GPI General Purpose Events Enable (GPI_GPE_EN_GPP_G_0)—Offset 170h

Same description as GPI_GPE_EN_GPP_C_0 register, except that this register is for GPP_G group only.

6.2.62 GPI General Purpose Events Enable (GPI_GPE_EN_GPP_H_0)—Offset 174h

Same description as GPI_GPE_EN_GPP_C_0 register, except that this register is for GPP_H group only.

6.2.63 SMI Status (GPI_SMI_STS_GPP_C_0)—Offset 180h

Register bits in this register are implemented for GPP_C signals that have SMI capability only. Other bits are reserved and RO.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

332219-002 439 GPIO for SKL PCH-H

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD GPI_SMI_STS_GPP_C_23 GPI_SMI_STS_GPP_C_22

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h GPI SMI Status (GPI_SMI_STS_GPP_C_23): Same description as bit 22. 23 RW1C

GPI SMI Status (GPI_SMI_STS_GPP_C_22): This bit is set to 1 by hardware when a level event (See RxEdCfg,RxInv) is detected, and all the following conditions are true: - The corresponding pad is used in GPIO input mode - The corresponding PAD_OWN[2:0] is ‘000’ (i.e. ACPI GPIO Mode). If the following conditions are true, then an SMI will be generated if the 0h GPI_SMI_STS bit is set: 22 RW1C 1. The corresponding bit in the GPI_SMI_EN register is set 2. The corresponding pad’s GPIROUTSMI is set Writing a value of 1 will clear the bit while writing a value of 0 has no effect. 0 = There is no SMI event 1 = There is an SMI event The state of GPI_SMI_EN does not prevent the setting of GPI_SMI_STS. Defaults for these bits are dependent on the state of the GPI pads.

0h 21:0 Reserved. RO

6.2.64 SMI Status (GPI_SMI_STS_GPP_D_0)—Offset 184h

Register bits in this register are implemented for GPP_D signals that have SMI capability only. Other bits are reserved and RO.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

440 332219-002

GPIO for SKL PCH-H

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_SMI_STS_GPP_D_4 GPI_SMI_STS_GPP_D_3 GPI_SMI_STS_GPP_D_2 GPI_SMI_STS_GPP_D_1 GPI_SMI_STS_GPP_D_0

Bit Default & Field Name (ID): Description Range Access

0h 31:5 Reserved. RO

0h GPI SMI Status (GPI_SMI_STS_GPP_D_4): Same description as bit 0. 4 RW1C

0h GPI SMI Status (GPI_SMI_STS_GPP_D_3): Same description as bit 0. 3 RW1C

0h GPI SMI Status (GPI_SMI_STS_GPP_D_2): Same description as bit 0. 2 RW1C

0h GPI SMI Status (GPI_SMI_STS_GPP_D_1): Same description as bit 0. 1 RW1C

GPI SMI Status (GPI_SMI_STS_GPP_D_0): This bit is set to 1 by hardware when a level event (See RxEdCfg,RxInv) is detected, and all the following conditions are true: - The corresponding pad is used in GPIO input mode - The corresponding PAD_OWN[2:0] is ‘000’ (i.e. ACPI GPIO Mode). If the following conditions are true, then an SMI will be generated if the 0h GPI_SMI_STS bit is set: 0 RW1C 1. The corresponding bit in the GPI_SMI_EN register is set 2. The corresponding pad’s GPIROUTSMI is set Writing a value of 1 will clear the bit while writing a value of 0 has no effect. 0 = There is no SMI event 1 = There is an SMI event The state of GPI_SMI_EN does not prevent the setting of GPI_SMI_STS. Defaults for these bits are dependent on the state of the GPI pads.

6.2.65 SMI Status (GPI_SMI_STS_GPP_E_0)—Offset 188h

Register bits in this register are implemented for GPP_E signals that have SMI capability only. Other bits are reserved and RO.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

332219-002 441 GPIO for SKL PCH-H

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_SMI_STS_GPP_E_8 GPI_SMI_STS_GPP_E_7 GPI_SMI_STS_GPP_E_6 GPI_SMI_STS_GPP_E_5 GPI_SMI_STS_GPP_E_4 GPI_SMI_STS_GPP_E_3 GPI_SMI_STS_GPP_E_2 GPI_SMI_STS_GPP_E_1 GPI_SMI_STS_GPP_E_0

Bit Default & Field Name (ID): Description Range Access

0h 31:9 Reserved. RO

0h GPI SMI Status (GPI_SMI_STS_GPP_E_8): Same description as bit 0. 8 RW1C

0h GPI SMI Status (GPI_SMI_STS_GPP_E_7): Same description as bit 0. 7 RW1C

0h GPI SMI Status (GPI_SMI_STS_GPP_E_6): Same description as bit 0. 6 RW1C

0h GPI SMI Status (GPI_SMI_STS_GPP_E_5): Same description as bit 0. 5 RW1C

0h GPI SMI Status (GPI_SMI_STS_GPP_E_4): Same description as bit 0. 4 RW1C

0h GPI SMI Status (GPI_SMI_STS_GPP_E_3): Same description as bit 0. 3 RW1C

0h GPI SMI Status (GPI_SMI_STS_GPP_E_2): Same description as bit 0. 2 RW1C

0h GPI SMI Status (GPI_SMI_STS_GPP_E_1): Same description as bit 0. 1 RW1C

GPI SMI Status (GPI_SMI_STS_GPP_E_0): This bit is set to 1 by hardware when a level event (See RxEdCfg,RxInv) is detected, and all the following conditions are true: - The corresponding pad is used in GPIO input mode - The corresponding PAD_OWN[2:0] is ‘000’ (i.e. ACPI GPIO Mode). If the following conditions are true, then an SMI will be generated if the 0h GPI_SMI_STS bit is set: 0 RW1C 1. The corresponding bit in the GPI_SMI_EN register is set 2. The corresponding pad’s GPIROUTSMI is set Writing a value of 1 will clear the bit while writing a value of 0 has no effect. 0 = There is no SMI event 1 = There is an SMI event The state of GPI_SMI_EN does not prevent the setting of GPI_SMI_STS. Defaults for these bits are dependent on the state of the GPI pads.

6.2.66 SMI Enable (GPI_SMI_EN_GPP_C_0)—Offset 1A0h

Register bits in this register are implemented for GPP_C signals that have SMI capability only. Other bits are reserved and RO.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

442 332219-002

GPIO for SKL PCH-H

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD GPI_SMI_EN_GPP_C_23 GPI_SMI_EN_GPP_C_22

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h GPI SMI Enable (GPI_SMI_EN_GPP_C_23): Same description as bit 22. 23 RW

GPI SMI Enable (GPI_SMI_EN_GPP_C_22): This bit is used to enable/disable the generation of SMI when the corresponding GPI_SMI_STS bit is set. The pad must also be routed for SMI functionality in order for SMI to be generated, i.e. the 0h corresponding GPIROUTSMI must be set to 1. 22 0 = disable SMI generation RW 1 = enable SMI generation Note: Each of the bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. E.g. if the PadCfgLock of pad0 is 1, bit0 of this bit is locked down to read-only.

0h 21:0 Reserved. RO

6.2.67 SMI Enable (GPI_SMI_EN_GPP_D_0)—Offset 1A4h

Register bits in this register are implemented for GPP_D signals that have SMI capability only. Other bits are reserved and RO.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_SMI_EN_GPP_D_4 GPI_SMI_EN_GPP_D_3 GPI_SMI_EN_GPP_D_2 GPI_SMI_EN_GPP_D_1 GPI_SMI_EN_GPP_D_0

332219-002 443 GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h 31:5 Reserved. RO

0h GPI SMI Enable (GPI_SMI_EN_GPP_D_4): Same description as bit 0. 4 RW

0h GPI SMI Enable (GPI_SMI_EN_GPP_D_3): Same description as bit 0. 3 RW

0h GPI SMI Enable (GPI_SMI_EN_GPP_D_2): Same description as bit 0. 2 RW

0h GPI SMI Enable (GPI_SMI_EN_GPP_D_1): Same description as bit 0. 1 RW

GPI SMI Enable (GPI_SMI_EN_GPP_D_0): This bit is used to enable/disable the generation of SMI when the corresponding GPI_SMI_STS bit is set. The pad must also be routed for SMI functionality in order for SMI to be generated, i.e. the

0h corresponding GPIROUTSMI must be set to 1. 0 0 = disable SMI generation RW 1 = enable SMI generation Note: Each of the bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. E.g. if the PadCfgLock of pad0 is 1, bit0 of this bit is locked down to read-only.

6.2.68 SMI Enable (GPI_SMI_EN_GPP_E_0)—Offset 1A8h

Register bits in this register are implemented for GPP_E signals that have SMI capability only. Other bits are reserved and RO.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_SMI_EN_GPP_E_8 GPI_SMI_EN_GPP_E_7 GPI_SMI_EN_GPP_E_6 GPI_SMI_EN_GPP_E_5 GPI_SMI_EN_GPP_E_4 GPI_SMI_EN_GPP_E_3 GPI_SMI_EN_GPP_E_2 GPI_SMI_EN_GPP_E_1 GPI_SMI_EN_GPP_E_0

Bit Default & Field Name (ID): Description Range Access

0h 31:9 Reserved. RO

0h GPI SMI Enable (GPI_SMI_EN_GPP_E_8): Same description as bit 0. 8 RW

0h GPI SMI Enable (GPI_SMI_EN_GPP_E_7): Same description as bit 0. 7 RW

444 332219-002

GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h GPI SMI Enable (GPI_SMI_EN_GPP_E_6): Same description as bit 0. 6 RW

0h GPI SMI Enable (GPI_SMI_EN_GPP_E_5): Same description as bit 0. 5 RW

0h GPI SMI Enable (GPI_SMI_EN_GPP_E_4): Same description as bit 0. 4 RW

0h GPI SMI Enable (GPI_SMI_EN_GPP_E_3): Same description as bit 0. 3 RW

0h GPI SMI Enable (GPI_SMI_EN_GPP_E_2): Same description as bit 0. 2 RW

0h GPI SMI Enable (GPI_SMI_EN_GPP_E_1): Same description as bit 0. 1 RW

GPI SMI Enable (GPI_SMI_EN_GPP_E_0): This bit is used to enable/disable the generation of SMI when the corresponding GPI_SMI_STS bit is set. The pad must also be routed for SMI functionality in order for SMI to be generated, i.e. the 0h corresponding GPIROUTSMI must be set to 1. 0 0 = disable SMI generation RW 1 = enable SMI generation Note: Each of the bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. E.g. if the PadCfgLock of pad0 is 1, bit0 of this bit is locked down to read-only.

6.2.69 NMI Status (GPI_NMI_STS_GPP_C_0)—Offset 1C0h

Register bits in this register are implemented for GPP_C signals that have NMI capability only. Other bits are reserved and RO.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD GPI_NMI_STS_GPP_C_23 GPI_NMI_STS_GPP_C_22

332219-002 445 GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h GPI NMI Status (GPI_NMI_STS_GPP_C_23): Same description as bit 22. 23 RW1C

GPI NMI Status (GPI_NMI_STS_GPP_C_22): This bit is set to 1 by hardware when an edge event is detected (See RxEdCfg, RxInv) on pad and all the following conditions are true: - The corresponding pad is used in GPIO input mode (PMode) 0h 22 - The corresponding GPIONMIRout is set to 1, i.e. programmed to route as NMI RW1C - The corresponding GPIOOwn[2:0] is ‘000’ (i.e. ACPI GPIO Mode). - The corresponding GPI_NMI_EN is set Writing a value of 1 will clear the bit while writing a value of 0 has no effect. 0 = There is no NMI event 1 = There is an NMI event

0h 21:0 Reserved. RO

6.2.70 NMI Status (GPI_NMI_STS_GPP_D_0)—Offset 1C4h

Register bits in this register are implemented for GPP_D signals that have NMI capability only. Other bits are reserved and RO.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_NMI_STS_GPP_D_4 GPI_NMI_STS_GPP_D_3 GPI_NMI_STS_GPP_D_2 GPI_NMI_STS_GPP_D_1 GPI_NMI_STS_GPP_D_0

Bit Default & Field Name (ID): Description Range Access

0h 31:5 Reserved. RO

0h GPI NMI Status (GPI_NMI_STS_GPP_D_4): Same description as bit 0. 4 RW1C

0h GPI NMI Status (GPI_NMI_STS_GPP_D_3): Same description as bit 0. 3 RW1C

446 332219-002

GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h GPI NMI Status (GPI_NMI_STS_GPP_D_2): Same description as bit 0. 2 RW1C

0h GPI NMI Status (GPI_NMI_STS_GPP_D_1): Same description as bit 0. 1 RW1C

GPI NMI Status (GPI_NMI_STS_GPP_D_0): This bit is set to 1 by hardware when an edge event is detected (See RxEdCfg, RxInv) on pad and all the following conditions are true: - The corresponding pad is used in GPIO input mode (PMode) 0h - The corresponding GPIONMIRout is set to 1, i.e. programmed to route as NMI 0 RW1C - The corresponding GPIOOwn[2:0] is ‘000’ (i.e. ACPI GPIO Mode). - The corresponding GPI_NMI_EN is set Writing a value of 1 will clear the bit while writing a value of 0 has no effect. 0 = There is no NMI event 1 = There is an NMI event

6.2.71 NMI Status (GPI_NMI_STS_GPP_E_0)—Offset 1C8h

Register bits in this register are implemented for GPP_E signals that have NMI capability only. Other bits are reserved and RO.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_NMI_STS_GPP_E_8 GPI_NMI_STS_GPP_E_7 GPI_NMI_STS_GPP_E_6 GPI_NMI_STS_GPP_E_5 GPI_NMI_STS_GPP_E_4 GPI_NMI_STS_GPP_E_3 GPI_NMI_STS_GPP_E_2 GPI_NMI_STS_GPP_E_1 GPI_NMI_STS_GPP_E_0

Bit Default & Field Name (ID): Description Range Access

0h 31:9 Reserved. RO

0h GPI NMI Status (GPI_NMI_STS_GPP_E_8): Same description as bit 0. 8 RW1C

0h GPI NMI Status (GPI_NMI_STS_GPP_E_7): Same description as bit 0. 7 RW1C

0h GPI NMI Status (GPI_NMI_STS_GPP_E_6): Same description as bit 0. 6 RW1C

0h GPI NMI Status (GPI_NMI_STS_GPP_E_5): Same description as bit 0. 5 RW1C

332219-002 447 GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h GPI NMI Status (GPI_NMI_STS_GPP_E_4): Same description as bit 0. 4 RW1C

0h GPI NMI Status (GPI_NMI_STS_GPP_E_3): Same description as bit 0. 3 RW1C

0h GPI NMI Status (GPI_NMI_STS_GPP_E_2): Same description as bit 0. 2 RW1C

0h GPI NMI Status (GPI_NMI_STS_GPP_E_1): Same description as bit 0. 1 RW1C

GPI NMI Status (GPI_NMI_STS_GPP_E_0): This bit is set to 1 by hardware when an edge event is detected (See RxEdCfg, RxInv) on pad and all the following conditions are true: - The corresponding pad is used in GPIO input mode (PMode) 0h - The corresponding GPIONMIRout is set to 1, i.e. programmed to route as NMI 0 RW1C - The corresponding GPIOOwn[2:0] is ‘000’ (i.e. ACPI GPIO Mode). - The corresponding GPI_NMI_EN is set Writing a value of 1 will clear the bit while writing a value of 0 has no effect. 0 = There is no NMI event 1 = There is an NMI event

6.2.72 NMI Enable (GPI_NMI_EN_GPP_C_0)—Offset 1E0h

Register bits in this register are implemented for GPP_C signals that have NMI capability only. Other bits are reserved and RO.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD GPI_NMI_EN_GPP_C_23 GPI_NMI_EN_GPP_C_22

448 332219-002

GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h GPI NMI Enable (GPI_NMI_EN_GPP_C_23): Same description as bit 22. 23 RW

GPI NMI Enable (GPI_NMI_EN_GPP_C_22): This bit is used to enable/disable the generation of NMI when the corresponding GPI_NMI_STS bit is set and its GPIROUTNMI is set. 0h 0 = disable NMI generation 22 RW 1 = enable NMI generation Each bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. E.g. if the PadCfgLock of pad0 is ‘1’, bit0 of this bit is locked down to read-only.

0h 21:0 Reserved. RO

6.2.73 NMI Enable (GPI_NMI_EN_GPP_D_0)—Offset 1E4h

Register bits in this register are implemented for GPP_D signals that have NMI capability only. Other bits are reserved and RO.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_NMI_EN_GPP_D_4 GPI_NMI_EN_GPP_D_3 GPI_NMI_EN_GPP_D_2 GPI_NMI_EN_GPP_D_1 GPI_NMI_EN_GPP_D_0

Bit Default & Field Name (ID): Description Range Access

0h 31:5 Reserved. RO

0h GPI NMI Enable (GPI_NMI_EN_GPP_D_4): Same description as bit 0. 4 RW

0h GPI NMI Enable (GPI_NMI_EN_GPP_D_3): Same description as bit 0. 3 RW

332219-002 449 GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h GPI NMI Enable (GPI_NMI_EN_GPP_D_2): Same description as bit 0. 2 RW

0h GPI NMI Enable (GPI_NMI_EN_GPP_D_1): Same description as bit 0. 1 RW

GPI NMI Enable (GPI_NMI_EN_GPP_D_0): This bit is used to enable/disable the generation of NMI when the corresponding GPI_NMI_STS bit is set and its GPIROUTNMI is set. 0h 0 0 = disable NMI generation RW 1 = enable NMI generation Each bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. E.g. if the PadCfgLock of pad0 is ‘1’, bit0 of this bit is locked down to read-only.

6.2.74 NMI Enable (GPI_NMI_EN_GPP_E_0)—Offset 1E8h

Register bits in this register are implemented for GPP_E signals that have NMI capability only. Other bits are reserved and RO.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_NMI_EN_GPP_E_8 GPI_NMI_EN_GPP_E_7 GPI_NMI_EN_GPP_E_6 GPI_NMI_EN_GPP_E_5 GPI_NMI_EN_GPP_E_4 GPI_NMI_EN_GPP_E_3 GPI_NMI_EN_GPP_E_2 GPI_NMI_EN_GPP_E_1 GPI_NMI_EN_GPP_E_0

Bit Default & Field Name (ID): Description Range Access

0h 31:9 Reserved. RO

0h GPI NMI Enable (GPI_NMI_EN_GPP_E_8): Same description as bit 0. 8 RW

0h GPI NMI Enable (GPI_NMI_EN_GPP_E_7): Same description as bit 0. 7 RW

0h GPI NMI Enable (GPI_NMI_EN_GPP_E_6): Same description as bit 0. 6 RW

0h GPI NMI Enable (GPI_NMI_EN_GPP_E_5): Same description as bit 0. 5 RW

0h GPI NMI Enable (GPI_NMI_EN_GPP_E_4): Same description as bit 0. 4 RW

450 332219-002

GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h GPI NMI Enable (GPI_NMI_EN_GPP_E_3): Same description as bit 0. 3 RW

0h GPI NMI Enable (GPI_NMI_EN_GPP_E_2): Same description as bit 0. 2 RW

0h GPI NMI Enable (GPI_NMI_EN_GPP_E_1): Same description as bit 0. 1 RW

GPI NMI Enable (GPI_NMI_EN_GPP_E_0): NMI enable This bit is used to enable/ disable the generation of NMI when the corresponding GPI_NMI_STS bit is set and its GPIROUTNMI is set. 0h 0 0 = disable NMI generation RW 1 = enable NMI generation Each bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. E.g. if the PadCfgLock of pad0 is ‘1’, bit0 of this bit is locked down to read-only.

6.2.75 PWM Control (PWMC)—Offset 204h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 EN SWUP BASEUNIT ONTIMEDIV

Bit Default & Field Name (ID): Description Range Access

0h Enable (EN): 0 = Disable PWM Output 31 RW 1 = Enable PWM Output

Software Update (SWUP): Indication that there is an update to PWM settings pending. SW sets this bit to 1 when updating the PWM_base_unit or 0h 30 PWM_on_time_divisor fields. The PWM module will apply the new settings at the end RW of the current cycle and reset this bit. 0 = No updates pending 1 = Update pending

0h Base Unit (BASEUNIT): Unsigned 8 integer bits, 14 fraction bits. Used to determine 29:8 RW PWM output frequency. The PWM base frequency for SPT is 32.768 KHz.

0h On Time Divisor (ONTIMEDIV): On Time Divisor (OnTimeDiv) PWM duty cycle = 7:0 RW PWM_on-time_divisor/256.

6.2.76 GPIO Serial Blink Enable (GP_SER_BLINK)—Offset 20Ch

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

332219-002 451 GPIO for SKL PCH-H

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GP_SER_BLINK

Bit Default & Field Name (ID): Description Range Access

0h 31:5 Reserved. RO

GP SER BLINK (GP_SER_BLINK): The setting of this bit has no effect if the corresponding GPIO is programmed as an input, if the corresponding GPIO has the PWM enabled, or if Serial Blink capability does not exist. This bit should be set to a 1 before output buffer is enabled. When set to a ‘0’, the corresponding GPIO will function normally. This bit should be set to a 1 while the corresponding PMode bit is set to 0h (GPIO Mode). Setting the PMode bit to other value (non-GPIO Mode) after the GP_SER_BLINK bit ensures PCH will not drive a 1 on the pin as an output. When this corresponding bit is set to a 1 and the pin is configured to output mode, 0h the serial blink capability is enabled and the programmed message is serialized out 4:0 RW through an open-drain buffer configuration. The value of the corresponding GPIOTxState bit remains unchanged and does not impact the serial blink capability in any way. Writes to this register have no effect when the corresponding pin is configured in native mode and the read value returned is undefined. Bit0 = GPP_D0 Bit1 = GPP_D1 Bit2 = GPP_D2 Bit3 = GPP_D3 Bit4 = GPP_D4

6.2.77 GPIO Serial Blink Command/Status (GP_SER_CMDSTS)— Offset 210h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 GO DLS DRS BUSY RSVD RSVD RSVD_2

452 332219-002

GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

Data Length Select (DLS): This read/write field determines the number of bytes to serialize on GPIO 0h 00: Serialize bits 7:0 of GP_GB_DATA (1 byte) 23:22 01: Serialize bits 15:0 of GP_GB_DATA (2 bytes) RW 10: Undefined - Software must not write this value 11: Serialize bits 31:0 of GP_GB_DATA (4 bytes) Software should not modify the value in this register unless the Busy bit

Data Rate Select (DRS): Data Rate Select (DRS): This read/write field selects the 0h number of 333.34ns (4 clock periods 12MHz clock) time intervals to count between 21:16 Manchester data transitions. The default of 8h results in a 2666.67 ns minimum time RW between transitions. A value of 0h in this register produces undefined behavior. Software should not modify the value in this register unless the Busy bit is clear.

0h 15:9 Reserved. RO

0h Busy (BUSY): Busy: This read-only status bit is the hardware indication that a 8 serialization is in progress. Hardware sets this bit to 1 based on the Go bit being set. RO Hardware clears this bit when the Go bit is cleared by the hardware.

0h Reserved (RSVD_2) 7:1 RO

Go (GO): Go: This bit is set to 1 by software to start the serialization process. 0h 0 Hardware clears the bit after the serialized data is sent. Writes of 0 to this register RW have no effect. Software should not write this bit to 1 unless the Busy status bit is cleared.

6.2.78 GPIO Serial Blink Data (GP_SER_DATA)—Offset 214h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 GP_GB_DATA

Bit Default & Field Name (ID): Description Range Access

GP Serial Blink Data (GP_GB_DATA): GP_GB_DATA This read-write register 0h contains the data serialized out. The number of bits shifted out is selected through 31:0 RW the DLS field in the GP_GB_CMDSTS register. This register should not be modified by software when the Busy bit is set.

6.2.79 GSX Controller Capabilities (GSX_CAP)—Offset 21Ch

Access Method

332219-002 453 GPIO for SKL PCH-H

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 NC RSVD

Bit Default & Field Name (ID): Description Range Access

0h 31:4 Reserved. RO

0h Number of Channels (NC): Number of Channels (NC): This is a zero-based 3:0 RO number. Each channel is capable of input and output GPIO.

6.2.80 GSX Channel-0 Capabilities DW0 (GSX_C0CAP_DW0)— Offset 220h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 NIN RSVD NOUT

Bit Default & Field Name (ID): Description Range Access

0h 31:10 Reserved. RO

Number of Output Expanders (NOUT): Number of Output Expanders (NOUT) 0h BIOS programs this field to indicate number of output expander components which 9:5 corresponds to multiple of CxGPO in byte granularity. This field is 1-based ('00001' RWO means 1 output expander which produces 8 bits of CxGPO). If this channel does not have output, this register shall be written with value of '00000'.

Number of Input Expanders (NIN): Number of Input Expanders (NIN) BIOS programs this field to indicate number of input expander components which 0h corresponds to multiple of CxGPO. This field is 1-based ('00001' means 1 input 4:0 RWO expander which produces 8 bits of CxGPI). If this channel does not have input, this register shall be written with value of '00000'. Typically, the combine total value of supported NOUT+NIN <= 8.

454 332219-002

GPIO for SKL PCH-H

6.2.81 GSX Channel-0 Capabilities DW1 (GSX_C0CAP_DW1)— Offset 224h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 12000h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000010010000000000000 RSVD SCLKR SCLKR_D

Bit Default & Field Name (ID): Description Range Access

0h 31:26 Reserved. RO

SCLK Rate(SCLKR) (SCLKR): SCLK Rate(SCLKR) Toggle rate of GSXSCLK. SCLKR and SCLKRD are BCD encoded. The SCLKR represent MHz rate as a whole number, 12h and SCLKR_D represent the decimal number. Example: GSXSCLK toggle rate of 25:12 16KHz would be represented as SCLKR=000h and SCLKR_D=016h. GSXSCLK RO/V typically is 15.625 12MHz or less to support long routing to multiple expanders, i.e. SCLKR=012h015h and SCLKR_D=000h625h. In the case, when ALTSCLK is '1', SCLKR and SCLKR_D shall reflect 3MHz

0h SCLK Rate Decimal (SCLKR_D): SCLK Rate Decimal (SCLKR_D): Refer to SCLKR 11:0 RO/V description.

6.2.82 GSX Channel-0 GP Input Level DW0 (GSX_C0GPILVL_DW0)—Offset 228h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 GPILVL_DW0

332219-002 455 GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

GPI Level DW0[31:0] (GPILVL_DW0): GPI Level DW0[31:0] (GPILVL_DW0) BIOS or software read returns the value of the CxGPI received over the GSX channel. GPILVL_DW0[y] corresponds to CxGPI[y] where y falls within [31:0] range. 0h CGPILVL_DW0[0] contains the first bit being serially shifted in during an atomic input 31:0 serialization process. Hardware serialization process shifts in each bit of CxGPI value RO in ascending order from [bit 0] to [((NIN*8)-1)'s MSB bit]. This register is updated by hardware on bit by bit basis. During the input serialization process, when a bit is serially shifted in based on SCLK toggle rate, the corresponding register bit is updated by hardware.

6.2.83 GSX Channel-0 GP Input Level DW1 (GSX_C0GPILVL_DW1)—Offset 22Ch

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 GPILVL_DW1

Bit Default & Field Name (ID): Description Range Access

0h GPI Level DW1[31:0] (GPILVL_DW1): GPI Level DW1[31:0] (GPILVL_DW1) 31:0 Refer to CxGPILVL_DW0 register description. GPILVL_DW1[y] corresponds to RO CxGPI[y] where y is within [63:32] range.

6.2.84 GSX Channel-0 GP Output Level DW0 (GSX_C0GPOLVL_DW0)—Offset 230h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 GPOLVL_DW0

456 332219-002

GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

GPO Level DW0[31:0] (GPOLVL_DW0): GPO Level[31:0] (GPOLVL_DW0) BIOS or software writes to this field to program the value of each output bit that will be sent in the serialization process. GPOLVL_DW0[y] corresponds to CxGPO[y] where y 0h within CxGPO[31:0] range. GPOLVL_DW0[0] is the last bit in this register to be 31:0 RW shifted out serially. Hardware serialization process shifts out each bit of CxGPOLVL_DW1 & CxGPOLVL_DW0 in descending order from [((NOUT*8)-1)'s MSB bit] to [bit 0]. Depending on CxCAP.NOUT, unused byte(s) of CxGPOLVL_DW1 and/or CxGPOLVL_DW0 is not serialized out.

6.2.85 GSX Channel-0 GP Output Level DW1 (GSX_C0GPOLVL_DW1)—Offset 234h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 GPOLVL_DW1

Bit Default & Field Name (ID): Description Range Access

0h GPO Level DW1[31:0] (GPOLVL_DW1): GPO Level DW1[31:0] (GPOLVL_DW1) 31:0 Refer to CxGPOLVL_DW0 register description. GPOLVL_DW1[y] corresponds to RW CxGPO[y] where y is within CxGPO[63:32] range.

6.2.86 GSX Channel-0 Command (GSX_C0CMD)—Offset 238h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 ST BSY RUN RSVD IOERST

332219-002 457 GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h 31:4 Reserved. RO

Input and Output Expander Reset Sequence (IOERST): Input and Output Expander Reset Sequence (IOERST) Software writes '1' to this bit to cause a reset sequence that brings both input and output expander into a default state. Serialization process will be able to begin at default bit position again. Specifically: 0h 3 GSXSRESET# going to output expanders is asserted while GSXSLOAD shall be held in RW1S '0' logic state such that any stale pin state previously latched into input expanders is being reloaded. The serialization thereafter can start from default bit position. Hardware automatically clears the bit to zero after the process above has been completed. Software shall have both ST and RUN bit equal to '0' when setting IOERST to '1'.

Running (RUN): Running (RUN) This bit reflects the status of the serialization 0h process. A '1' indicates that the serialization process is in progress. When software 2 RO clears the ST bit, software shall poll on RUN bit to be '0' before software can write '1' to ST bit again.

Busy (BSY): Busy (BSY) Software reads this field to determine if the serialization of most recently updated GPOLVL_DW1 and/or GPOLVL_DW0 content has been completely serialized out on the GSX. H/w sets this bit when either GPOLVL_DW1 or GPOLVL_DW0 is written to. Hardware will automatically clear the bit to'0' after all of the newly written value of GPOLVL_DW1 and/or GPOLVL_DW0 bits have been serialized out at least once. This allows software a method to ensure no collapsing of any particular CxGPO[y] bit during a back to back software update of GPOLVL_DW0 0h or GPOLVL_DW1. Software may reprogram the GPOLVL_DW1 and/or GPOLVL_DW0 at 1 RO any time irrespective of state of BSY bit if intermediate software update being collapsed is not a concern. Irrespective of the state of BSY bit, hardware serialization process walks thru each bit of GPOLVL_DW1 & GPOLVL_DW0 from bit[63] to bit[0] in descending order. Example: if hardware serialization is in the midst of serializing out CxGPO[3] and software updates GPOLVL_DW0, hardware serialization will serialize out the updated value of GPOLVL_DW0[2 to 0] as CxGPO[2:0]. Then hardware will serialize out the updated value of GPOLVL_DW1[MSB to 0] and so on (assuming >4 output expanders case).

Start (ST): Start (ST) This bit is set to 1 by software to start the serialization process. Software should not write this bit to 1 unless: ? the Busy status bit is 0h cleared, and ? the CxCAP has been programmed. Also refer to the CxGPILVL(U) 0 description if default input value is desired. Once this bit is set to 1, the serialization RW processes for input and output are running continuously. If software clears the ST bit to '0', hardware shall stop the serialization process at a convenient time but at atomic boundary. Note: Clearing Start bit does not trigger GSXSRESET# to be asserted.

6.2.87 GSX Channel-0 Test Mode (GSX_C0TM)—Offset 23Ch

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 BBE RSVD RSVD ALTSCLK BBGSCLK BBGSXSLOAD BBGSXSDOUT BBGSXSRESETB

458 332219-002

GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h 31:13 Reserved. RO

0h Bit-bang GSXSRESET# (BBGSXSRESETB): Bit-bang GSXSRESET# 12 RW (BBGSXSRESETB) This bit allows software to directly bit bang the GSXSRESET#.

0h Bit-bang GSXSLOAD (BBGSXSLOAD): Bit-bang GSXSLOAD (BBGSXSLOAD) This 11 RW bit allows software to directly bit bang the GSXSLOAD.

0h Bit-bang GSXSDOUT (BBGSXSDOUT): Bit-bang GSXSDOUT (BBGSXSDOUT) This 10 RW bit allows software to directly bit bang the GSXSDOUT.

0h Bit-bang GSXSCLK (BBGSCLK): Bit-bang GSXSCLK (BBGSCLK) This bit allows 9 RW software to directly bit bang the GSXSCLK.

0h Bit-bang Enable (BBE): Bit-bang Enable (BBE) When this bit is '1', the bit-bang 8 mode is enable and the CxTM.BBGSXS* register bits are directly controlling the GSX RW pins.

0h 7:1 Reserved. RO

Alternate SCLK Rate (ALTSCLK): This test mode allows slower toggle rate of the 0h GSX channel. 0 RW 0: default value of SCLKR.SCLKR_D 1: default value of SCLKR.SCLKR_D divide by 4

6.2.88 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_0)— Offset 400h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 44000300h

3 2 2 2 1 1 840 1 8 4 0 6 2

01000100000000000000001100000000 RSVD RSVD RSVD RSVD RSVD RXINV PMODE2 PMODE1 PMODE0 RXRAW1 RXEVCFG GPIOTXDIS GPIORXDIS PADRSTCFG GPIROUTSCI GPIROUTSMI RXPADSTSEL GPIROUTNMI GPIOTXSTATE GPIORXSTATE GPIROUTIOXAPIC

332219-002 459 GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

Pad Reset Config (PADRSTCFG): This register controls which reset is used to reset GPIO pad register fields in PAD_CFG_DW0 and PAD_CFG_DW1 registers. This register can be used for Sx isolation of the associated signal if needed.

1h 00 = RSMRST# 31:30 01 = Host deep reset. This reset occurs when a host reset (with or without power RW cycle) is initiated or a global reset is initiated, except that the reset does not assert when in S3/S4/S5. 10 = PLTRST# 11 = Reserved

RX Pad State Select (RXPADSTSEL): Determines from which node the RX pad state for native function should be taken from. This field only affects the pad state 0h value being fanned out to native function(s) and is not meaningful if the pad is in 29 RW GPIO mode (i.e. Pad Mode = 0). 0 = Raw RX pad state directly from RX buffer 1 = Internal RX pad state (subject to RXINV and PreGfRXSel settings)

RX Raw Override to '1' (RXRAW1): This bit determines if the selected pad state is being overridden to '1'. This field is only applicable when the RX buffer is configured 0h 28 as an input in either GPIO Mode or native function mode. The override takes place at RW the internal pad state directly from buffer and before the RXINV. 0 = No Override 1 = RX drive 1 internally

0h 27 Reserved. RO

RX Level/Edge Configuration (RXEVCFG): Determines if the internal RX pad state (synchronized, filtered vs non-filtered version as determined by PreGfRXSel, and is further subject to RXInv) should be passed on to the next logic stage as is, as a pulse, or level signal. This field does not affect the received pad state (to 2h 26:25 GPIORXState or native functions) but how the interrupt or wake triggering events RW should be delivered to the GPIO Community Controller . 0h = Level 1h = Edge 2h = Drive '0' 3h = Reserved (implement as setting 0h)

0h 24 Reserved. RO

RX Invert (RXINV): This bit determines if the selected pad state should go through the polarity inversion stage. This field is only applicable when the RX buffer is configured as an input in either GPIO Mode or native function mode. The polarity inversion takes place at the mux node of raw vs filtered or non-filtered RX pad state,

0h as determined by PreGfRXsel and RXPadStSel This bit does not affect GPIORXState. 23 During host ownership GPIO Mode, when this bit is set to '1', then the RX pad state is RW inverted as it is sent to the GPIO-to-IOxAPIC, GPE/SCI, SMI, NMI logic or GPI_IS[n] that is using it. This is used to allow active-low and active-high inputs to cause IRQ, SMI#, SCI or NMI. 0 = No inversion 1 = Inversion

0h 22:21 Reserved. RO

GPIO Input Route IOxAPIC (GPIROUTIOXAPIC): Determines if the pad can be routed to cause peripheral IRQ when configured in GPIO input mode. If the pad is not

0h configured in GPIO input mode, this field has no effect. 20 0 = Routing does not cause peripheral IRQ RW 1 = Routing can cause peripheral IRQ Note: This bit does not affect any interrupt status bit within GPIO, but is used as the last qualifier for the peripheral IRQ indication to the intended recipient(s).

GPIO Input Route SCI (GPIROUTSCI): Determines if the pad can be routed to cause SCI when configured in GPIO input mode. If the pad is not configured in GPIO 0h input mode, this field has no effect. 19 0 = Routing does not cause SCI. RW 1 = Routing can cause SCI Note: This bit does not affect any interrupt status bit within GPIO, but is used as the last qualifier for the GPE indication to the intended recipient(s).

GPIO Input Route SMI (GPIROUTSMI): Determines if the pad can be routed to cause SMI when configured in GPIO input mode. If the pad is not configured in GPIO input mode, this field has no effect. 0h 0 = Routing does not cause SMI. 18 RW 1 = Routing can cause SMI. Note: This bit does not affect any interrupt status bit within GPIO, but is used as the last qualifier for the SMI indication to the intended recipient(s). This bit only applies to a GPIO that has SMI capability. Otherwise, the bit is RO.

460 332219-002

GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

GPIO Input Route NMI (GPIROUTNMI): Determines if the pad can be routed to cause NMI when configured in GPIO input mode. If the pad is not configured in GPIO input mode, this field has no effect. 0 = Routing does not cause NMI. 0h 1 = Routing can cause NMI. 17 RW Note: This bit also affects GPI_NMI_STS. If '0', GPI_NMI_STS is always clear. If '1', GPI_NMI_STS could be set (depending on GPIOOwn setting) when there is an event. Whether a NMI indication is generated and sent to the intended recipient(s) is also depending on the corresponding GPI_NMI_EN bit. This bit only applies to a GPIO that has NMI capability. Otherwise, the bit is RO.

0h 16:13 Reserved. RO

0h Pad Mode bit 2 (PMODE2): See Pad Mode bit 0 description. 12 RW

0h Pad Mode bit 1 (PMODE1): See Pad Mode bit 0 description. 11 RW

Pad Mode bit 0 (PMODE0): This bit is used in conjunction with Pad Mode bit 1 and 2 . This three-bit field determines whether the Pad is controlled by GPIO controller logic or one of the native functions muxed onto the Pad. 0h = GPIO control the Pad. 1h = native function 1, if applicable, controls the Pad 0h 2h = native function 2, if applicable, controls the Pad 10 3h = native function 3, if applicable, controls the Pad RW 4h = enable GPIO blink/PWM capability if applicable (note that not all GPIOs have blink/PWM capability) Dedicated (unmuxed) GPIO shall report RO of all 0’s in this register field If GPIO vs. native mode is configured via soft strap, this bit has no effect.

Default value is determined by the default functionality of the pad.

GPIO RX Disable (GPIORXDIS): 0 = Enable the input buffer (active low enable) of

1h the pad. 9 1 = Disable the input buffer of the pad. RW Notes: When the input buffer is disabled, the internal pad state is always driven to '0'.

1h GPIO TX Disable (GPIOTXDIS): 0 = Enable the output buffer (active low enable) 8 of the pad. RW 1 = Disable the output buffer of the pad; i.e. Hi-Z

0h 7:2 Reserved. RO

0h GPIO RX State (GPIORXSTATE): This is the current internal RX pad state after 1 RO Glitch Filter logic stage and is not affected by PMode and RXINV settings.

0h GPIO TX State (GPIOTXSTATE): 0 = Drive a level '0' to the TX output pad. 0 RW 1 = Drive a level '1' to the TX output pad.

6.2.89 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_0)— Offset 404h

This register applies to GPP_C0.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 18h

332219-002 461 GPIO for SKL PCH-H

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000011000 TERM RSVD RSVD INTSEL

Bit Default & Field Name (ID): Description Range Access

0h 31:14 Reserved. RO

Termination (TERM): The Pad Termination state defines the different weak pull-up and pull-down settings that are supported by the buffer. The settings for [13:10] correspond to: 0000: none 0010: 5k pd 0100: 20k pd 1000: none 1001: 1k pu 1011: 2k pu 0h 1010: 5k pu 13:10 1100: 20k pu RW 1101: 1k & 2k pu (in parallel) 1111: Native controller selected by Pad Mode controls the Termination All others reserved. If a reserved value is programmed, pad may malfunction. The setting of this field is applicable in all Pad Mode including GPIO. As each Pad Mode may require different termination and isolation, care must be taken in sw/fw in the transition with appropriate register programming. The actual transition sequence requirement may vary on case by case basis depending on the native functions involved. For example, before changing the pad from output to input direction, pu/pd settings should be programmed first to ensure the input does not float momentarily.

0h 9:8 Reserved. RO

Interrupt Select (INTSEL): The Interrupt Select defines which interrupt line driven from the GPIO Controller toggles when an interrupt is detected on this pad. 18h 0 = Interrupt Line 0 7:0 RO 1 = Interrupt Line 1 .... Up to the max IOxAPIC IRQ supported

6.2.90 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_1)— Offset 408h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.91 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_1)— Offset 40Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 19h

6.2.92 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_2)— Offset 410h

Same description as PAD_CFG_DW0_GPP_C_0

462 332219-002

GPIO for SKL PCH-H

6.2.93 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_2)— Offset 414h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 1Ah

6.2.94 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_3)— Offset 418h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.95 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_3)— Offset 41Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 1Bh

6.2.96 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_4)— Offset 420h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.97 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_4)— Offset 424h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 1Ch

6.2.98 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_5)— Offset 428h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.99 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_5)— Offset 42Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 1Dh

6.2.100 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_6)— Offset 430h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.101 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_6)— Offset 434h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 1Eh

332219-002 463 GPIO for SKL PCH-H

6.2.102 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_7)— Offset 438h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.103 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_7)— Offset 43Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 1Fh

6.2.104 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_8)— Offset 440h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.105 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_8)— Offset 444h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 20h

6.2.106 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_9)— Offset 448h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.107 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_9)— Offset 44Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 21h

6.2.108 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_10)— Offset 450h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.109 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_10)— Offset 454h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 22h

6.2.110 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_11)— Offset 458h

Same description as PAD_CFG_DW0_GPP_C_0

464 332219-002

GPIO for SKL PCH-H

6.2.111 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_11)— Offset 45Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 23h

6.2.112 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_12)— Offset 460h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.113 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_12)— Offset 464h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 24h

6.2.114 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_13)— Offset 468h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.115 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_13)— Offset 46Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 25h

6.2.116 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_14)— Offset 470h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.117 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_14)— Offset 474h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 26h

6.2.118 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_15)— Offset 478h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.119 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_15)— Offset 47Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 27h

332219-002 465 GPIO for SKL PCH-H

6.2.120 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_16)— Offset 480h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.121 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_16)— Offset 484h

Note that this register definition also applies to GPP_C[19:17], GPP_D4, GPP_D23, GPP_H[9:0], and GPP_H[22:19].

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 28h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000101000 TERM RSVD RSVD RSVD INTSEL CFIOPADCFG_PADTOL

Bit Default & Field Name (ID): Description Range Access

0h 31:26 Reserved. RO

0h Pad Voltage Tolarance (CFIOPADCFG_PADTOL): 25 0 = pad is 3.3V tolerance (Supplied pad voltage is 3.3V) RW 1 = pad is 1.8V tolerance (Supplied pad voltage is 3.3V).

0h 24:14 Reserved. RO

466 332219-002

GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

Termination (TERM): The Pad Termination state defines the different weak pull-up and pull-down settings that are supported by the buffer. The settings for [13:10] correspond to: 0000: none 0010: 5k pd 0100: 20k pd 1000: none 1001: 1k pu 1011: 2k pu 0h 1010: 5k pu 13:10 RO 1100: 20k pu 1101: 1k & 2k (in parallel) pu All others reserved. If a reserved value is programmed, pad may malfunction. The setting of this field is applicable in all Pad Mode including GPIO. As each Pad Mode may require different termination and isolation, care must be taken in sw/fw in the transition with appropriate register programming. The actual transition sequence requirement may vary on case by case basis depending on the native functions involved. For example, before changing the pad from output to input direction, pu/pd settings should be programmed first to ensure the input does not float momentarily.

0h 9:8 Reserved. RO

Interrupt Select (INTSEL): The Interrupt Select defines which interrupt line driven from the GPIO Controller toggles when an interrupt is detected on this pad. 28h 0 = Interrupt Line 0 7:0 RO 1 = Interrupt Line 1 .... Up to the max IOxAPIC IRQ supported

6.2.122 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_17)— Offset 488h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.123 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_17)— Offset 48Ch

Same description as PAD_CFG_DW1_GPP_C_16 Exception: The default value of the INTSEL bit field in this register is : 29h

6.2.124 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_18)— Offset 490h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.125 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_18)— Offset 494h

Same description as PAD_CFG_DW1_GPP_C_16 Exception: The default value of the INTSEL bit field in this register is : 2Ah

6.2.126 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_19)— Offset 498h

Same description as PAD_CFG_DW0_GPP_C_0

332219-002 467 GPIO for SKL PCH-H

6.2.127 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_19)— Offset 49Ch

Same description as PAD_CFG_DW1_GPP_C_16 Exception: The default value of the INTSEL bit field in this register is : 2Bh

6.2.128 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_20)— Offset 4A0h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.129 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_20)— Offset 4A4h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 2Ch

6.2.130 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_21)— Offset 4A8h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.131 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_21)— Offset 4ACh

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 2Dh

6.2.132 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_22)— Offset 4B0h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.133 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_22)— Offset 4B4h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 2Eh

6.2.134 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_23)— Offset 4B8h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.135 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_23)— Offset 4BCh

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 2Fh

468 332219-002

GPIO for SKL PCH-H

6.2.136 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_0)— Offset 4C0h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.137 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_0)— Offset 4C4h

Same description as PAD_CFG_DW1_GPP_C_0

6.2.138 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_1)— Offset 4C8h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.139 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_1)— Offset 4CCh

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 31h

6.2.140 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_2)— Offset 4D0h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.141 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_2)— Offset 4D4h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 32h

6.2.142 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_3)— Offset 4D8h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.143 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_3)— Offset 4DCh

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 33h

6.2.144 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_4)— Offset 4E0h

Same description as PAD_CFG_DW0_GPP_C_0

332219-002 469 GPIO for SKL PCH-H

6.2.145 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_4)— Offset 4E4h

Same description as PAD_CFG_DW1_GPP_C_16 Exception: The default value of the INTSEL bit field in this register is : 34h

6.2.146 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_5)— Offset 4E8h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.147 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_5)— Offset 4ECh

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 35h

6.2.148 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_6)— Offset 4F0h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.149 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_6)— Offset 4F4h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 36h

6.2.150 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_7)— Offset 4F8h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.151 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_7)— Offset 4FCh

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 37h

6.2.152 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_8)— Offset 500h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.153 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_8)— Offset 504h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 38h

470 332219-002

GPIO for SKL PCH-H

6.2.154 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_9)— Offset 508h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.155 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_9)— Offset 50Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 39h

6.2.156 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_10)— Offset 510h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.157 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_10)— Offset 514h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 3Ah

6.2.158 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_11)— Offset 518h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.159 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_11)— Offset 51Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 3Bh

6.2.160 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_12)— Offset 520h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.161 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_12)— Offset 524h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 3Ch

6.2.162 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_13)— Offset 528h

Same description as PAD_CFG_DW0_GPP_C_0

332219-002 471 GPIO for SKL PCH-H

6.2.163 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_13)— Offset 52Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 3Dh

6.2.164 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_14)— Offset 530h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.165 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_14)— Offset 534h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 3Eh

6.2.166 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_15)— Offset 538h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.167 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_15)— Offset 53Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 3Fh

6.2.168 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_16)— Offset 540h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.169 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_16)— Offset 544h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 40h

6.2.170 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_17)— Offset 548h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.171 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_17)— Offset 54Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 41h

472 332219-002

GPIO for SKL PCH-H

6.2.172 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_18)— Offset 550h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.173 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_18)— Offset 554h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 42h

6.2.174 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_19)— Offset 558h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.175 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_19)— Offset 55Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 43h

6.2.176 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_20)— Offset 560h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.177 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_20)— Offset 564h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 44h

6.2.178 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_21)— Offset 568h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.179 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_21)— Offset 56Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 45h

6.2.180 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_22)— Offset 570h

Same description as PAD_CFG_DW0_GPP_C_0

332219-002 473 GPIO for SKL PCH-H

6.2.181 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_22)— Offset 574h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 46h

6.2.182 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_23)— Offset 578h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.183 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_23)— Offset 57Ch

Same description as PAD_CFG_DW1_GPP_C_16 Exception: The default value of the INTSEL bit field in this register is : 47h

6.2.184 Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_0)— Offset 580h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.185 Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_0)— Offset 584h

Same description as PAD_CFG_DW1_GPP_C_0

6.2.186 Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_1)— Offset 588h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.187 Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_1)— Offset 58Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 49h

6.2.188 Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_2)— Offset 590h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.189 Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_2)— Offset 594h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 4Ah

474 332219-002

GPIO for SKL PCH-H

6.2.190 Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_3)— Offset 598h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.191 Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_3)— Offset 59Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 4Bh

6.2.192 Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_4)— Offset 5A0h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.193 Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_4)— Offset 5A4h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 4Ch

6.2.194 Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_5)— Offset 5A8h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.195 Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_5)— Offset 5ACh

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 4Dh

6.2.196 Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_6)— Offset 5B0h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.197 Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_6)— Offset 5B4h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 4Eh

6.2.198 Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_7)— Offset 5B8h

Same description as PAD_CFG_DW0_GPP_C_0

332219-002 475 GPIO for SKL PCH-H

6.2.199 Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_7)— Offset 5BCh

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 4Fh

6.2.200 Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_8)— Offset 5C0h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.201 Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_8)— Offset 5C4h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 50h

6.2.202 Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_9)— Offset 5C8h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.203 Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_9)— Offset 5CCh

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 51h

6.2.204 Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_10)— Offset 5D0h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.205 Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_10)— Offset 5D4h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 52h

6.2.206 Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_11)— Offset 5D8h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.207 Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_11)— Offset 5DCh

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 53h

476 332219-002

GPIO for SKL PCH-H

6.2.208 Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_12)— Offset 5E0h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.209 Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_12)— Offset 5E4h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 54h

6.2.210 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_0)— Offset 5E8h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.211 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_0)— Offset 5ECh

Same description as PAD_CFG_DW1_GPP_C_0

6.2.212 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_1)— Offset 5F0h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.213 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_1)— Offset 5F4h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 56h

6.2.214 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_2)— Offset 5F8h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.215 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_2)— Offset 5FCh

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 57h

6.2.216 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_3)— Offset 600h

Same description as PAD_CFG_DW0_GPP_C_0

332219-002 477 GPIO for SKL PCH-H

6.2.217 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_3)— Offset 604h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 58h

6.2.218 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_4)— Offset 608h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.219 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_4)— Offset 60Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 59h

6.2.220 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_5)— Offset 610h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.221 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_5)— Offset 614h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 5Ah

6.2.222 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_6)— Offset 618h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.223 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_6)— Offset 61Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 5Bh

6.2.224 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_7)— Offset 620h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.225 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_7)— Offset 624h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 5Ch

478 332219-002

GPIO for SKL PCH-H

6.2.226 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_8)— Offset 628h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.227 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_8)— Offset 62Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 5Dh

6.2.228 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_9)— Offset 630h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.229 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_9)— Offset 634h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 5Eh

6.2.230 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_10)— Offset 638h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.231 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_10)— Offset 63Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 5Fh

6.2.232 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_11)— Offset 640h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.233 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_11)— Offset 644h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 60h

6.2.234 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_12)— Offset 648h

Same description as PAD_CFG_DW0_GPP_C_0

332219-002 479 GPIO for SKL PCH-H

6.2.235 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_12)— Offset 64Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 61h

6.2.236 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_13)— Offset 650h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.237 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_13)— Offset 654h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 62h

6.2.238 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_14)— Offset 658h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.239 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_14)— Offset 65Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 63h

6.2.240 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_15)— Offset 660h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.241 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_15)— Offset 664h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 64h

6.2.242 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_16)— Offset 668h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.243 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_16)— Offset 66Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 65h

480 332219-002

GPIO for SKL PCH-H

6.2.244 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_17)— Offset 670h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.245 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_17)— Offset 674h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 66h

6.2.246 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_18)— Offset 678h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.247 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_18)— Offset 67Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 67h

6.2.248 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_19)— Offset 680h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.249 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_19)— Offset 684h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 68h

6.2.250 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_20)— Offset 688h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.251 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_20)— Offset 68Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 69h

6.2.252 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_21)— Offset 690h

Same description as PAD_CFG_DW0_GPP_C_0

332219-002 481 GPIO for SKL PCH-H

6.2.253 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_21)— Offset 694h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 6Ah

6.2.254 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_22)— Offset 698h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.255 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_22)— Offset 69Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 6Bh

6.2.256 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_23)— Offset 6A0h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.257 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_23)— Offset 6A4h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 6Ch

6.2.258 Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_0)— Offset 6A8h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.259 Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_0)— Offset 6ACh

Same description as PAD_CFG_DW1_GPP_C_0

6.2.260 Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_1)— Offset 6B0h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.261 Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_1)— Offset 6B4h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 6Eh

482 332219-002

GPIO for SKL PCH-H

6.2.262 Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_2)— Offset 6B8h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.263 Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_2)— Offset 6BCh

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 6Fh

6.2.264 Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_3)— Offset 6C0h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.265 Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_3)— Offset 6C4h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 70h

6.2.266 Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_4)— Offset 6C8h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.267 Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_4)— Offset 6CCh

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 71h

6.2.268 Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_5)— Offset 6D0h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.269 Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_5)— Offset 6D4h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 72h

6.2.270 Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_6)— Offset 6D8h

Same description as PAD_CFG_DW0_GPP_C_0

332219-002 483 GPIO for SKL PCH-H

6.2.271 Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_6)— Offset 6DCh

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 73h

6.2.272 Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_7)— Offset 6E0h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.273 Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_7)— Offset 6E4h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 74h

6.2.274 Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_8)— Offset 6E8h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.275 Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_8)— Offset 6ECh

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 75h

6.2.276 Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_9)— Offset 6F0h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.277 Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_9)— Offset 6F4h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 76h

6.2.278 Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_10)— Offset 6F8h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.279 Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_10)— Offset 6FCh

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 77h

484 332219-002

GPIO for SKL PCH-H

6.2.280 Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_11)— Offset 700h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.281 Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_11)— Offset 704h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 00h

6.2.282 Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_12)— Offset 708h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.283 Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_12)— Offset 70Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 00h

6.2.284 Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_13)— Offset 710h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.285 Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_13)— Offset 714h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 00h

6.2.286 Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_14)— Offset 718h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.287 Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_14)— Offset 71Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 00h

6.2.288 Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_15)— Offset 720h

Same description as PAD_CFG_DW0_GPP_C_0

332219-002 485 GPIO for SKL PCH-H

6.2.289 Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_15)— Offset 724h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 00h

6.2.290 Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_16)— Offset 728h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.291 Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_16)— Offset 72Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 00h

6.2.292 Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_17)— Offset 730h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.293 Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_17)— Offset 734h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 00h

6.2.294 Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_18)— Offset 738h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.295 Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_18)— Offset 73Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 00h

6.2.296 Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_19)— Offset 740h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.297 Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_19)— Offset 744h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 00h

486 332219-002

GPIO for SKL PCH-H

6.2.298 Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_20)— Offset 748h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.299 Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_20)— Offset 74Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 00h

6.2.300 Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_21)— Offset 750h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.301 Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_21)— Offset 754h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 00h

6.2.302 Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_22)— Offset 758h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.303 Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_22)— Offset 75Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 00h

6.2.304 Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_23)— Offset 760h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.305 Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_23)— Offset 764h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 00h

6.2.306 Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_0)— Offset 768h

Same description as PAD_CFG_DW0_GPP_C_0

332219-002 487 GPIO for SKL PCH-H

6.2.307 Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_0)— Offset 76Ch

Same description as PAD_CFG_DW1_GPP_C_16 Exception: The default value of the INTSEL bit field in this register is : 00h

6.2.308 Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_1)— Offset 770h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.309 Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_1)— Offset 774h

Same description as PAD_CFG_DW1_GPP_C_16 Exception: The default value of the INTSEL bit field in this register is : 00h

6.2.310 Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_2)— Offset 778h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.311 Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_2)— Offset 77Ch

Same description as PAD_CFG_DW1_GPP_C_16 Exception: The default value of the INTSEL bit field in this register is : 00h

6.2.312 Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_3)— Offset 780h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.313 Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_3)— Offset 784h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 00h

6.2.314 Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_4)— Offset 788h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.315 Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_4)— Offset 78Ch

Same description as PAD_CFG_DW1_GPP_C_16 Exception: The default value of the INTSEL bit field in this register is : 00h

488 332219-002

GPIO for SKL PCH-H

6.2.316 Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_5)— Offset 790h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.317 Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_5)— Offset 794h

Same description as PAD_CFG_DW1_GPP_C_16 Exception: The default value of the INTSEL bit field in this register is : 00h

6.2.318 Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_6)— Offset 798h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.319 Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_6)— Offset 79Ch

Same description as PAD_CFG_DW1_GPP_C_16 Exception: The default value of the INTSEL bit field in this register is : 00h

6.2.320 Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_7)— Offset 7A0h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.321 Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_7)— Offset 7A4h

Same description as PAD_CFG_DW1_GPP_C_16 Exception: The default value of the INTSEL bit field in this register is : 00h

6.2.322 Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_8)— Offset 7A8h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.323 Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_8)— Offset 7ACh

Same description as PAD_CFG_DW1_GPP_C_16 Exception: The default value of the INTSEL bit field in this register is : 00h

6.2.324 Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_9)— Offset 7B0h

Same description as PAD_CFG_DW0_GPP_C_0

332219-002 489 GPIO for SKL PCH-H

6.2.325 Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_9)— Offset 7B4h

Same description as PAD_CFG_DW1_GPP_C_16 Exception: The default value of the INTSEL bit field in this register is : 00h

6.2.326 Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_10)— Offset 7B8h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.327 Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_10)— Offset 7BCh

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 00h

6.2.328 Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_11)— Offset 7C0h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.329 Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_11)— Offset 7C4h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 00h

6.2.330 Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_12)— Offset 7C8h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.331 Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_12)— Offset 7CCh

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 00h

6.2.332 Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_13)— Offset 7D0h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.333 Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_13)— Offset 7D4h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 00h

490 332219-002

GPIO for SKL PCH-H

6.2.334 Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_14)— Offset 7D8h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.335 Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_14)— Offset 7DCh

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 00h

6.2.336 Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_15)— Offset 7E0h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.337 Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_15)— Offset 7E4h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 00h

6.2.338 Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_16)— Offset 7E8h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.339 Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_16)— Offset 7ECh

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 00h

6.2.340 Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_17)— Offset 7F0h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.341 Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_17)— Offset 7F4h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 00h

6.2.342 Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_18)— Offset 7F8h

Same description as PAD_CFG_DW0_GPP_C_0

332219-002 491 GPIO for SKL PCH-H

6.2.343 Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_18)— Offset 7FCh

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 00h

6.2.344 Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_19)— Offset 800h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.345 Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_19)— Offset 804h

Same description as PAD_CFG_DW1_GPP_C_16 Exception: The default value of the INTSEL bit field in this register is : 00h

6.2.346 Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_20)— Offset 808h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.347 Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_20)— Offset 80Ch

Same description as PAD_CFG_DW1_GPP_C_16 Exception: The default value of the INTSEL bit field in this register is : 00h

6.2.348 Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_21)— Offset 810h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.349 Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_21)— Offset 814h

Same description as PAD_CFG_DW1_GPP_C_16 Exception: The default value of the INTSEL bit field in this register is : 00h

6.2.350 Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_22)— Offset 818h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.351 Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_22)— Offset 81Ch

Same description as PAD_CFG_DW1_GPP_C_16 Exception: The default value of the INTSEL bit field in this register is : 00h

492 332219-002

GPIO for SKL PCH-H

6.2.352 Pad Configuration DW0 (PAD_CFG_DW0_GPP_H_23)— Offset 820h

Same description as PAD_CFG_DW0_GPP_C_0

6.2.353 Pad Configuration DW1 (PAD_CFG_DW1_GPP_H_23)— Offset 824h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 00h

6.3 GPIO Community 2 Registers Summary

Community 2 Registers are for GPP_DSW group.

Table 6-3. Summary of GPIO Community 2 Registers

Offset Offset Default Register Name (ID)—Offset Start End Value

8h Bh Family Base Address (FAMBAR)—Offset 8h 300h

Ch Fh Pad Base Address (PADBAR)—Offset Ch 400h

10h 13h Miscellaneous Configuration (MISCCFG)—Offset 10h 43200h

20h 23h Pad Ownership (PAD_OWN_GPD_0)—Offset 20h 0h

24h 27h Pad Ownership (PAD_OWN_GPD_1)—Offset 24h 0h

A0h A3h Pad Configuration Lock (PADCFGLOCK_GPD_0)—Offset A0h 0h

A4h A7h Pad Configuration Lock (PADCFGLOCKTX_GPD_0)—Offset A4h 0h

D0h D3h Host Software Pad Ownership (HOSTSW_OWN_GPD_0)—Offset D0h 0h

100h 103h GPI Interrupt Status (GPI_IS_GPD_0)—Offset 100h 0h

120h 123h GPI Interrupt Enable (GPI_IE_GPD_0)—Offset 120h 0h

GPI General Purpose Events Status (GPI_GPE_STS_GPD_0)—Offset 140h 143h 0h 140h

160h 163h GPI General Purpose Events Enable (GPI_GPE_EN_GPD_0)—Offset 160h 0h

400xx00h 400h 403h Pad Configuration DW0 (PAD_CFG_DW0_GPD_0)—Offset 400h See register for xx value

404h 407h Pad Configuration DW1 (PAD_CFG_DW1_GPD_0)—Offset 404h 50h

400xx00h 408h 40Bh Pad Configuration DW0 (PAD_CFG_DW0_GPD_1)—Offset 408h See register for xx value

40Ch 40Fh Pad Configuration DW1 (PAD_CFG_DW1_GPD_1)—Offset 40Ch See register

400xx00h 410h 413h Pad Configuration DW0 (PAD_CFG_DW0_GPD_2)—Offset 410h See register for xx value

414h 417h Pad Configuration DW1 (PAD_CFG_DW1_GPD_2)—Offset 414h See register

400xx00h 418h 41Bh Pad Configuration DW0 (PAD_CFG_DW0_GPD_3)—Offset 418h See register for xx value

41Ch 41Fh Pad Configuration DW1 (PAD_CFG_DW1_GPD_3)—Offset 41Ch See register

400xx00h 420h 423h Pad Configuration DW0 (PAD_CFG_DW0_GPD_4)—Offset 420h See register for xx value

332219-002 493 GPIO for SKL PCH-H

Table 6-3. Summary of GPIO Community 2 Registers (Continued)

Offset Offset Default Register Name (ID)—Offset Start End Value

424h 427h Pad Configuration DW1 (PAD_CFG_DW1_GPD_4)—Offset 424h See register

400xx00h 428h 42Bh Pad Configuration DW0 (PAD_CFG_DW0_GPD_5)—Offset 428h See register for xx value

42Ch 42Fh Pad Configuration DW1 (PAD_CFG_DW1_GPD_5)—Offset 42Ch See register

400xx00h 430h 433h Pad Configuration DW0 (PAD_CFG_DW0_GPD_6)—Offset 430h See register for xx value

434h 437h Pad Configuration DW1 (PAD_CFG_DW1_GPD_6)—Offset 434h See register

400xx00h 438h 43Bh Pad Configuration DW0 (PAD_CFG_DW0_GPD_7)—Offset 438h See register for xx value

43Ch 43Fh Pad Configuration DW1 (PAD_CFG_DW1_GPD_7)—Offset 43Ch See register

400xx00h 440h 443h Pad Configuration DW0 (PAD_CFG_DW0_GPD_8)—Offset 440h See register for xx value

444h 447h Pad Configuration DW1 (PAD_CFG_DW1_GPD_8)—Offset 444h See register

400xx00h 448h 44Bh Pad Configuration DW0 (PAD_CFG_DW0_GPD_9)—Offset 448h See register for xx value

44Ch 44Fh Pad Configuration DW1 (PAD_CFG_DW1_GPD_9)—Offset 44Ch See register

400xx00h 450h 453h Pad Configuration DW0 (PAD_CFG_DW0_GPD_10)—Offset 450h See register for xx value

454h 457h Pad Configuration DW1 (PAD_CFG_DW1_GPD_10)—Offset 454h See register

400xx00h 458h 45Bh Pad Configuration DW0 (PAD_CFG_DW0_GPD_11)—Offset 458h See register for xx value

45Ch 45Fh Pad Configuration DW1 (PAD_CFG_DW1_GPD_11)—Offset 45Ch See register

6.3.1 Family Base Address (FAMBAR)—Offset 8h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 300h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000001100000000 RSVD FAMBAR

494 332219-002

GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h 31:16 Reserved. RO

Family Base Address (FAMBAR): This field provides the starting byte-align 300h 15:0 address of Family0 register sets. It is meant for software to discover from where the RO very first Family register (i.e. Family0 register) starts to compute the next Families address offsets.

6.3.2 Pad Base Address (PADBAR)—Offset Ch

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 400h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000010000000000 RSVD PADBAR

Bit Default & Field Name (ID): Description Range Access

0h 31:16 Reserved. RO

400h Pad Base Address (PADBAR): This field provides the starting byte-align address of 15:0 Pad0 register sets. It is meant for software to discover from where the very first Pad RO register (i.e. Pad0 register) starts to compute the next Pad address offsets.

6.3.3 Miscellaneous Configuration (MISCCFG)—Offset 10h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 43200h

332219-002 495 GPIO for SKL PCH-H

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000001000011001000000000 RSVD RSVD RSVD GPDLCGEN GPDPCGEN GPE0_DW2 GPE0_DW1 GPE0_DW0 GPIO_DRIVER_IRQ_ROUTE

Bit Default & Field Name (ID): Description Range Access

0h 31:20 Reserved. RO

GPIO Group to GPE_DW0 assignment encoding (GPE0_DW2): This register assigns a specific GPIO Group to the ACPI GPE0[95:64]. The selected GPIO group will be mapped to lower bits of the GPE register 0h = GPP_A[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 1h = GPP_B[23:0] mapped to GPE[87:64]; GPE[95:88] not used.

4h 2h = GPP_C[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 19:16 3h = GPP_D[23:0] mapped to GPE[87:64]; GPE[95:88] not used. RW 4h = GPP_E[12:0] mapped to GPE[76:64]; GPE[95:77] not used. 5h = GPP_F[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 6h = GPP_G[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 7h = GPP_H[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 8h = GPP_I[10:0] mapped to GPE[74:64]; GPE[95:75] not used. 9h = GPD[11:0] mapped to GPE[75:64]; GPE[95:76] not used.

GPIO Group to GPE_DW0 assignment encoding (GPE0_DW1): This register assigns a specific GPIO Group to the ACPI GPE0[63:32]. The selected GPIO group will be mapped to lower bits of the GPE register 0h = GPP_A[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 1h = GPP_B[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 3h 2h = GPP_C[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 15:12 3h = GPP_D[23:0] mapped to GPE[55:32]; GPE[63:56] not used. RW 4h = GPP_E[12:0] mapped to GPE[44:32]; GPE[63:45] not used. 5h = GPP_F[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 6h = GPP_G[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 7h = GPP_H[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 8h = GPP_I[10:0] mapped to GPE[42:32]; GPE[63:43] not used. 9h = GPD[11:0] mapped to GPE[43:32]; GPE[63:44] not used.

GPIO Group to GPE_DW0 assignment encoding (GPE0_DW0): This register assigns a specific GPIO Group to the ACPI GPE0[31:0]. The selected GPIO group will be mapped to lower bits of the GPE register 0h = GPP_A[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 1h = GPP_B[23:0] mapped to GPE[23:0]; GPE[31:24] not used.

2h 2h = GPP_C[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 11:8 3h = GPP_D[23:0] mapped to GPE[23:0]; GPE[31:24] not used. RW 4h = GPP_E[12:0] mapped to GPE[12:0]; GPE[31:13] not used. 5h = GPP_F[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 6h = GPP_G[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 7h = GPP_H[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 8h = GPP_I[10:0] mapped to GPE[10:0]; GPE[31:11] not used. 9h = GPD[11:0] mapped to GPE[11:0]; GPE[31:12] not used.

0h 7:4 Reserved. RO

GPIO Driver IRQ Route (GPIO_DRIVER_IRQ_ROUTE): GPIO Driver 0h IRQ_ROUTE[1:0]: Specifies the APIC IRQ globally for all pads within the current 3 community (GPI_IS with corresponding GPI_IE enable). RW 0 = IRQ14 1 = IRQ15

496 332219-002

GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h 2 Reserved. RO

GPIO Dynamic Partition Clock Gating Enable (GPDPCGEN): Specifies whether 0h the GPIO Community should take part in partition clock gating 1 RW 0 = Disable participation in dynamic partition clock gating 1 = Enable participation in dynamic partition clock gating.

GPIO Dynamic Local Clock Gating Enable (GPDLCGEN): Specifies whether the 0h 0 GPIO Community should perform local clock gating. RW 0 = Disable dynamic local clock gating 1 = Enable dynamic local clock gating

6.3.4 Pad Ownership (PAD_OWN_GPD_0)—Offset 20h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD PAD_OWN_GPD_7 PAD_OWN_GPD_6 PAD_OWN_GPD_5 PAD_OWN_GPD_4 PAD_OWN_GPD_3 PAD_OWN_GPD_2 PAD_OWN_GPD_1 PAD_OWN_GPD_0

Bit Default & Field Name (ID): Description Range Access

0h 31:30 Reserved. RO

0h Pad Ownership (PAD_OWN_GPD_7): Same description as bit 0, except that the 29:28 RO bit field applies to GPD_7.

0h 27:26 Reserved. RO

0h Pad Ownership (PAD_OWN_GPD_6): Same description as bit 0, except that the 25:24 RO bit field applies to GPD_6.

0h 23:22 Reserved. RO

0h Pad Ownership (PAD_OWN_GPD_5): Same description as bit 0, except that the 21:20 RO bit field applies to GPD_5.

0h 19:18 Reserved. RO

0h Pad Ownership (PAD_OWN_GPD_4): Same description as bit 0, except that the 17:16 RO bit field applies to GPD_4.

0h 15:14 Reserved. RO

332219-002 497 GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h Pad Ownership (PAD_OWN_GPD_3): Same description as bit 0, except that the 13:12 RO bit field applies to GPD_3.

0h 11:10 Reserved. RO

0h Pad Ownership (PAD_OWN_GPD_2): Same description as bit 0, except that the 9:8 RO bit field applies to GPD_2.

0h 7:6 Reserved. RO

0h Pad Ownership (PAD_OWN_GPD_1): Same description as bit 0, except that the 5:4 RO bit field applies to GPD_1.

0h 3:2 Reserved. RO

Pad Ownership (PAD_OWN_GPD_0): 00 = Host GPIO ACPI Mode or GPIO Driver Mode. Host software (ACPI or GPIO Driver) has ownership of the pad. In Host GPIO Driver Mode (refer to HOSTSW_OWN), GPIO input event update is limited to GPI_STS 0h 1:0 update only. Otherwise in Host ACPI Mode, updates are limited to GPI_GPE_STS, RO GPI_NMI_STS and/or GPI_SMI_STS. 01 = ME GPIO Mode. ME has ownership of the pad. 10 = ISH GPIO Mode.ME has ownership of the pad 11 = Reserved

6.3.5 Pad Ownership (PAD_OWN_GPD_1)—Offset 24h

6.3.6 Pad Configuration Lock (PADCFGLOCK_GPD_0)—Offset A0h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD PADCFGLOCK_GPD_9 PADCFGLOCK_GPD_8 PADCFGLOCK_GPD_7 PADCFGLOCK_GPD_6 PADCFGLOCK_GPD_5 PADCFGLOCK_GPD_4 PADCFGLOCK_GPD_3 PADCFGLOCK_GPD_2 PADCFGLOCK_GPD_1 PADCFGLOCK_GPD_0 PADCFGLOCK_GPD_11 PADCFGLOCK_GPD_10

498 332219-002

GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h 31:12 Reserved. RO

0h Pad Config Lock (PADCFGLOCK_GPD_11): Applied to GPD_11. Same description 11 RW as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPD_10): Applied to GPD_2. Same description 10 RW as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPD_9): Applied to GPD_2. Same description as 9 RW bit 0.

0h Pad Config Lock (PADCFGLOCK_GPD_8): Applied to GPD_8. Same description as 8 RW bit 0.

0h Pad Config Lock (PADCFGLOCK_GPD_7): Applied to GPD_7. Same description as 7 RW bit 0.

0h Pad Config Lock (PADCFGLOCK_GPD_6): Applied to GPD_6. Same description as 6 RW bit 0.

0h Pad Config Lock (PADCFGLOCK_GPD_5): Applied to GPD_5. Same description as 5 RW bit 0.

0h Pad Config Lock (PADCFGLOCK_GPD_4): Applied to GPD_4. Same description as 4 RW bit 0.

0h Pad Config Lock (PADCFGLOCK_GPD_3): Applied to GPD_3. Same description as 3 RW bit 0.

0h Pad Config Lock (PADCFGLOCK_GPD_2): Applied to GPD_2. Same description as 2 RW bit 0.

0h Pad Config Lock (PADCFGLOCK_GPD_1): Applied to GPD_2. Same description as 1 RW bit 0.

Pad Config Lock (PADCFGLOCK_GPD_0): Pad Configuration Lock locks specific register fields in the GPP specific registers from being configured. The registers affected become Read-Only and software writes to these registers have no effect. 0 = Unlock 1 = Lock the following register fields as read-only (RO): 0h - Pad Configuration registers (exclude GPIOTXState) 0 RW - GPI_NMI_EN Register (if implemented) - GPI_SMI_EN Register (if implemented) - GPI_GPE_EN Register (if implemented) When PadCfgLock is written from a '1' to a '0' (unlock), a synchronous SMI# is generated if enabled. This ensures that only SMM code can change the above GPIO registers after the lockdown.

6.3.7 Pad Configuration Lock (PADCFGLOCKTX_GPD_0)—Offset A4h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

332219-002 499 GPIO for SKL PCH-H

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD PADCFGLOCKTX_GPD_9 PADCFGLOCKTX_GPD_8 PADCFGLOCKTX_GPD_7 PADCFGLOCKTX_GPD_6 PADCFGLOCKTX_GPD_5 PADCFGLOCKTX_GPD_4 PADCFGLOCKTX_GPD_3 PADCFGLOCKTX_GPD_2 PADCFGLOCKTX_GPD_1 PADCFGLOCKTX_GPD_0 PADCFGLOCKTX_GPD_11 PADCFGLOCKTX_GPD_10

Bit Default & Field Name (ID): Description Range Access

0h 31:12 Reserved. RO

0h Pad Config Lock TXState (PADCFGLOCKTX_GPD_11): Applied to GPD_11. Same 11 RW description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPD_10): Applied to GPD_10. Same 10 RW description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPD_9): Applied to GPD_9. Same 9 RW description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPD_8): Applied to GPD_8. Same 8 RW description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPD_7): Applied to GPD_7. Same 7 RW description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPD_6): Applied to GPD_6. Same 6 RW description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPD_5): Applied to GPD_5. Same 5 RW description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPD_4): Applied to GPD_4. Same 4 RW description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPD_3): Applied to GPD_3. Same 3 RW description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPD_2): Applied to GPD_2. Same 2 RW description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPD_1): Applied to GPD_1. Same 1 RW description as bit 0.

Pad Config Lock TXState (PADCFGLOCKTX_GPD_0): PadCfgLockTx locks the GPIOTxState bit from being configured. The GPIOTxState register becomes Read- Only and software writes to the register have no effect. 0h 0 = Unlock 0 RW 1 = Locks the Pad Configuration GPIOTXState field as read-only (RO) When PadCfgLockTx is written from a '1' to a '0' (unlock), a synchronous SMI# is generated if enabled. This ensures that only SMM code can change the above GPIO registers after the lockdown.

6.3.8 Host Software Pad Ownership (HOSTSW_OWN_GPD_0)— Offset D0h

Access Method

500 332219-002

GPIO for SKL PCH-H

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD HOSTSW_OWN_GPD_9 HOSTSW_OWN_GPD_8 HOSTSW_OWN_GPD_7 HOSTSW_OWN_GPD_6 HOSTSW_OWN_GPD_5 HOSTSW_OWN_GPD_4 HOSTSW_OWN_GPD_3 HOSTSW_OWN_GPD_2 HOSTSW_OWN_GPD_1 HOSTSW_OWN_GPD_0 HOSTSW_OWN_GPD_11 HOSTSW_OWN_GPD_10

Bit Default & Field Name (ID): Description Range Access

0h 31:12 Reserved. RO

0h HostSW_Own (HOSTSW_OWN_GPD_11): Applied to GPD_11. Same description 11 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPD_10): Applied to GPD_10. Same description 10 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPD_9): Applied to GPD_9. Same description as 9 RW bit 0.

0h HostSW_Own (HOSTSW_OWN_GPD_8): Applied to GPD_8. Same description as 8 RW bit 0.

0h HostSW_Own (HOSTSW_OWN_GPD_7): Applied to GPD_7. Same description as 7 RW bit 0.

0h HostSW_Own (HOSTSW_OWN_GPD_6): Applied to GPD_6. Same description as 6 RW bit 0.

0h HostSW_Own (HOSTSW_OWN_GPD_5): Applied to GPD_5. Same description as 5 RW bit 0.

0h HostSW_Own (HOSTSW_OWN_GPD_4): Applied to GPD_4. Same description as 4 RW bit 0.

0h HostSW_Own (HOSTSW_OWN_GPD_3): Applied to GPD_3. Same description as 3 RW bit 0.

0h HostSW_Own (HOSTSW_OWN_GPD_2): Applied to GPD_2. Same description as 2 RW bit 0.

0h HostSW_Own (HOSTSW_OWN_GPD_1): Applied to GPD_1. Same description as 1 RW bit 0.

HostSW_Own (HOSTSW_OWN_GPD_0): This register determines the appropriate host status bit update when a pad is under host ownership. 0h 0 = ACPI Mode. GPIO input event updates are limited to GPI_GPE_STS, 0 RW GPI_NMI_STS and/or GPI_SMI_STS. GPI_STS update is masked. 1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked.

332219-002 501 GPIO for SKL PCH-H

6.3.9 GPI Interrupt Status (GPI_IS_GPD_0)—Offset 100h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_INT_STS_GPD_9 GPI_INT_STS_GPD_8 GPI_INT_STS_GPD_7 GPI_INT_STS_GPD_6 GPI_INT_STS_GPD_5 GPI_INT_STS_GPD_4 GPI_INT_STS_GPD_3 GPI_INT_STS_GPD_2 GPI_INT_STS_GPD_1 GPI_INT_STS_GPD_0 GPI_INT_STS_GPD_11 GPI_INT_STS_GPD_10

Bit Default & Field Name (ID): Description Range Access

0h 31:12 Reserved. RO

0h GPI Interrupt Status (GPI_INT_STS_GPD_11): Applied to GPD_11. Same 11 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPD_10): Applied to GPD_10. Same 10 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPD_9): Applied to GPD_9. Same 9 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPD_8): Applied to GPD_8. Same 8 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPD_7): Applied to GPD_7. Same 7 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPD_6): Applied to GPD_6. Same 6 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPD_5): Applied to GPD_5. Same 5 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPD_4): Applied to GPD_4. Same 4 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPD_3): Applied to GPD_3. Same 3 RW1C description as bit 0.

502 332219-002

GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h GPI Interrupt Status (GPI_INT_STS_GPD_2): Applied to GPD_2. Same 2 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPD_1): Applied to GPD_1. Same 1 RW1C description as bit 0.

GPI Interrupt Status (GPI_INT_STS_GPD_0): GPI Interrupt Status (GPI_INT_STS) This bit is set to ‘1’ by hardware when either an edge or a level event is detected (See RxEdCfg RxInv) on pad and all the following conditions are true: 0h - The corresponding pad is used in GPIO input mode 0 RW1C - HOSTSW_OWN = 1 (i.e. Host GPIO Driver Mode). Writing a value of 1 will clear the bit while writing a value of 0 has no effect. 0 = No interrupt 1 = Interrupt asserts The state of GPI_INT_EN does not prevent the setting of GPI_INT_STS.

6.3.10 GPI Interrupt Enable (GPI_IE_GPD_0)—Offset 120h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_INT_EN_GPD_9 GPI_INT_EN_GPD_8 GPI_INT_EN_GPD_7 GPI_INT_EN_GPD_6 GPI_INT_EN_GPD_5 GPI_INT_EN_GPD_4 GPI_INT_EN_GPD_3 GPI_INT_EN_GPD_2 GPI_INT_EN_GPD_1 GPI_INT_EN_GPD_0 GPI_INT_EN_GPD_11 GPI_INT_EN_GPD_10

Bit Default & Field Name (ID): Description Range Access

0h 31:12 Reserved. RO

0h GPI Interrupt Enable (GPI_INT_EN_GPD_11): Applied to GPD_11. Same 11 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPD_10): Applied to GPD_10. Same 10 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPD_9): Applied to GPD_9. Same 9 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPD_8): Applied to GPD_8. Same 8 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPD_7): Applied to GPD_7. Same 7 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPD_6): Applied to GPD_6. Same 6 RW description as bit 0.

332219-002 503 GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h GPI Interrupt Enable (GPI_INT_EN_GPD_5): Applied to GPD_5. Same 5 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPD_4): Applied to GPD_4. Same 4 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPD_3): Applied to GPD_3. Same 3 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPD_2): Applied to GPD_2. Same 2 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPD_1): Applied to GPD_1. Same 1 RW description as bit 0.

GPI Interrupt Enable (GPI_INT_EN_GPD_0): This bit is used to enable/disable 0h the generation of APIC interrupt when the corresponding GPI_INT_STS bit is set. 0 0 = disable interrupt generation RW 1 = enable interrupt generation Refer to GPI_IRQ_ROUTE for host GPIO Driver Mode interrupt routing.

6.3.11 GPI General Purpose Events Status (GPI_GPE_STS_GPD_0)—Offset 140h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_GPE_STS_GPD_9 GPI_GPE_STS_GPD_8 GPI_GPE_STS_GPD_7 GPI_GPE_STS_GPD_6 GPI_GPE_STS_GPD_5 GPI_GPE_STS_GPD_4 GPI_GPE_STS_GPD_3 GPI_GPE_STS_GPD_2 GPI_GPE_STS_GPD_1 GPI_GPE_STS_GPD_0 GPI_GPE_STS_GPD_11 GPI_GPE_STS_GPD_10

Bit Default & Field Name (ID): Description Range Access

0h 31:12 Reserved. RO

0h GPI General Purpose Events Status (GPI_GPE_STS_GPD_11): Applied to 11 RW1C GPD_11. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPD_10): Applied to 10 RW1C GPD_10. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPD_9): Applied to 9 RW1C GPD_9. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPD_8): Applied to 8 RW1C GPD_8. Same description as bit 0.

504 332219-002

GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h GPI General Purpose Events Status (GPI_GPE_STS_GPD_7): Applied to 7 RW1C GPD_7. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPD_6): Applied to 6 RW1C GPD_6. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPD_5): Applied to 5 RW1C GPD_5. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPD_4): Applied to 4 RW1C GPD_4. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPD_3): Applied to 3 RW1C GPD_3. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPD_2): Applied to 2 RW1C GPD_2. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPD_1): Applied to 1 RW1C GPD_1. Same description as bit 0.

GPI General Purpose Events Status (GPI_GPE_STS_GPD_0): These bits are set any time the corresponding GPIO pad is set up as an input, under host ownership and the corresponding GPIO signal is high(or low if the corresponding RXINV bit is set). If the corresponding enable bit is set in the GPI_GPE_EN register, then when the 0h GPI_GPE_STS bit is set: 0 RW1C - If the system is in an S3-S5 state, the event will also wake the system. - If the system is in an S0 state (or upon waking back to an S0 state), an SCI will be caused, depending on the GPIRoutSCI bit for the corresponding pad. These bits are sticky bits and are cleared by writing a 1 back to this bit position. The state of GPI_GPE_EN does not prevent the setting of GPI_GPE_STS.

6.3.12 GPI General Purpose Events Enable (GPI_GPE_EN_GPD_0)—Offset 160h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_GPE_EN_GPD_9 GPI_GPE_EN_GPD_8 GPI_GPE_EN_GPD_7 GPI_GPE_EN_GPD_6 GPI_GPE_EN_GPD_5 GPI_GPE_EN_GPD_4 GPI_GPE_EN_GPD_3 GPI_GPE_EN_GPD_2 GPI_GPE_EN_GPD_1 GPI_GPE_EN_GPD_0 GPI_GPE_EN_GPD_11 GPI_GPE_EN_GPD_10

332219-002 505 GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h 31:12 Reserved. RO

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPD_11): Applied to 11 RW GPD_11. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPD_10): Applied to 10 RW GPD_10. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPD_9): Applied to GPD_9. 9 RW Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPD_8): Applied to GPD_8. 8 RW Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPD_7): Applied to GPD_7. 7 RW Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPD_6): Applied to GPD_6. 6 RW Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPD_5): Applied to GPD_5. 5 RW Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPD_4): Applied to GPD_4. 4 RW Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPD_3): Applied to GPD_3. 3 RW Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPD_2): Applied to GPD_2. 2 RW Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPD_1): Applied to GPD_1. 1 RW Same description as bit 0.

GPI General Purpose Events Enable (GPI_GPE_EN_GPD_0): This bit is used to enable/disable the generation of GPE to cause SCI and/or wake when the 0h corresponding GPI_GPE_STS bit is set. 0 0 = disable GPE generation RW 1 = enable GPE generation Note: The pad must also be routed for GPE functionality in order for GPE to be generated, i.e. the corresponding GPIRoutSCI must be set to ‘1’.

6.3.13 Pad Configuration DW0 (PAD_CFG_DW0_GPD_0)—Offset 400h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 400xx00h

506 332219-002

GPIO for SKL PCH-H

3 2 2 2 1 1 840 1 8 4 0 6 2

00000100000000000000001100000000 RSVD RSVD RSVD RSVD RSVD RXINV PMODE2 PMODE1 PMODE0 RXRAW1 RXEVCFG GPIOTXDIS GPIORXDIS PADRSTCFG GPIROUTSCI GPIROUTSMI RXPADSTSEL GPIROUTNMI GPIOTXSTATE GPIORXSTATE GPIROUTIOXAPIC

Bit Default & Field Name (ID): Description Range Access

Pad Reset Config (PADRSTCFG): This register controls which reset is used to reset GPIO pad register fields in PAD_CFG_DW0 and PAD_CFG_DW1 registers. This register can be used for Sx isolation of the associated signal if needed.

0h 00 = DSW_PWROK 31:30 01 = Host deep reset. This reset occurs when a host reset (with or without power RW cycle) is initiated or a global reset is initiated, except that the reset does not assert when in S3/S4/S5. 10 = PLTRST# 11 = RSMRST#

RX Pad State Select (RXPADSTSEL): Determines from which node the RX pad state for native function should be taken from. This field only affects the pad state 0h value being fanned out to native function(s) and is not meaningful if the pad is in 29 RW GPIO mode (i.e. Pad Mode = 0). 0 = Raw RX pad state directly from RX buffer 1 = Internal RX pad state (subject to RXINV and PreGfRXSel settings)

RX Raw Override to '1' (RXRAW1): This bit determines if the selected pad state is being overridden to '1'. This field is only applicable when the RX buffer is configured 0h 28 as an input in either GPIO Mode or native function mode. The override takes place at RW the internal pad state directly from buffer and before the RXINV. 0 = No Override 1 = RX drive 1 internally

0h 27 Reserved. RO

RX Level/Edge Configuration (RXEVCFG): Determines if the internal RX pad state (synchronized, filtered vs non-filtered version as determined by PreGfRXSel, and is further subject to RXInv) should be passed on to the next logic stage as is, as a pulse, or level signal. This field does not affect the received pad state (to 2h 26:25 GPIORXState or native functions) but how the interrupt or wake triggering events RW should be delivered to the GPIO Community Controller . 0h = Level 1h = Edge 2h = Drive '0' 3h = Reserved (implement as setting 0h)

0h 24 Reserved. RO

RX Invert (RXINV): This bit determines if the selected pad state should go through the polarity inversion stage. This field is only applicable when the RX buffer is configured as an input in either GPIO Mode or native function mode. The polarity inversion takes place at the mux node of raw vs filtered or non-filtered RX pad state, 0h as determined by PreGfRXsel and RXPadStSel This bit does not affect GPIORXState. 23 During host ownership GPIO Mode, when this bit is set to '1', then the RX pad state is RW inverted as it is sent to the GPIO-to-IOxAPIC, GPE/SCI, SMI, NMI logic or GPI_IS[n] that is using it. This is used to allow active-low and active-high inputs to cause IRQ, SMI#, SCI or NMI. 0 = No inversion 1 = Inversion

0h 22:21 Reserved. RO

GPIO Input Route IOxAPIC (GPIROUTIOXAPIC): Determines if the pad can be routed to cause peripheral IRQ when configured in GPIO input mode. If the pad is not

0h configured in GPIO input mode, this field has no effect. 20 0 = Routing does not cause peripheral IRQ RW 1 = Routing can cause peripheral IRQ Note: This bit does not affect any interrupt status bit within GPIO, but is used as the last qualifier for the peripheral IRQ indication to the intended recipient(s).

332219-002 507 GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

GPIO Input Route SCI (GPIROUTSCI): Determines if the pad can be routed to cause SCI when configured in GPIO input mode. If the pad is not configured in GPIO

0h input mode, this field has no effect. 19 0 = Routing does not cause SCI. RW 1 = Routing can cause SCI Note: This bit does not affect any interrupt status bit within GPIO, but is used as the last qualifier for the GPE indication to the intended recipient(s).

GPIO Input Route SMI (GPIROUTSMI): Determines if the pad can be routed to cause SMI when configured in GPIO input mode. If the pad is not configured in GPIO input mode, this field has no effect. 0h 0 = Routing does not cause SMI. 18 RO 1 = Routing can cause SMI. Note: This bit does not affect any interrupt status bit within GPIO, but is used as the last qualifier for the SMI indication to the intended recipient(s). This bit only applies to a GPIO that has SMI capability. Otherwise, the bit is RO.

GPIO Input Route NMI (GPIROUTNMI): Determines if the pad can be routed to cause NMI when configured in GPIO input mode. If the pad is not configured in GPIO input mode, this field has no effect. 0 = Routing does not cause NMI. 0h 17 1 = Routing can cause NMI. RW Note: This bit also affects GPI_NMI_STS. If '0', GPI_NMI_STS is always clear. If '1', GPI_NMI_STS could be set (depending on GPIOOwn setting) when there is an event. Whether a NMI indication is generated and sent to the intended recipient(s) is also depending on the corresponding GPI_NMI_EN bit. This bit only applies to a GPIO that has NMI capability. Otherwise, the bit is RO.

0h 16:13 Reserved. RO

-- Pad Mode bit 2 (PMODE2): See description of Pad Mode bit 0. 12 RW

-- Pad Mode bit 1 (PMODE1): See description of Pad Mode bit 0. 11 RW

Pad Mode bit 0 (PMODE0): This bit is used in conjunction with Pad Mode bit 1 and 2. This three-bit field determines whether the Pad is controlled by GPIO controller logic or one of the native functions muxed onto the Pad. 0h = GPIO control the Pad. 1h = native function 1, if applicable, controls the Pad -- 2h = native function 2, if applicable, controls the Pad 10 3h = native function 3, if applicable, controls the Pad RW 4h = enable GPIO blink/PWM capability if applicable (note that not all GPIOs have blink/PWM capability) Dedicated (unmuxed) GPIO shall report RO of all 0’s in this register field If GPIO vs. native mode is configured via soft strap, this bit has no effect.

Default value is determined by the default functionality of the pad.

GPIO RX Disable (GPIORXDIS): 0 = Enable the input buffer (active low enable) of 1h the pad. 9 1 = Disable the input buffer of the pad. RW Notes: When the input buffer is disabled, the internal pad state is always driven to '0'.

1h GPIO TX Disable (GPIOTXDIS): 0 = Enable the output buffer (active low enable) 8 of the pad. RW 1 = Disable the output buffer of the pad; i.e. Hi-Z

0h 7:2 Reserved. RO

0h GPIO RX State (GPIORXSTATE): This is the current internal RX pad state after 1 RO Glitch Filter logic stage and is not affected by PMode and RXINV settings.

0h GPIO TX State (GPIOTXSTATE): 0 = Drive a level '0' to the TX output pad. 0 RW 1 = Drive a level '1' to the TX output pad

6.3.14 Pad Configuration DW1 (PAD_CFG_DW1_GPD_0)—Offset 404h

Access Method

508 332219-002

GPIO for SKL PCH-H

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 50h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000001010000 TERM RSVD RSVD INTSEL

Bit Default & Field Name (ID): Description Range Access

0h 31:14 Reserved. RO

Termination (TERM): The Pad Termination state defines the different weak pull-up and pull-down settings that are supported by the buffer. The settings for [13:10] correspond to: 0000: none 0010: 5k pd 0100: 20k pd 1000: none 1001: 1k pu 1011: 2k pu

0h 1010: 5k pu 13:10 1100: 20k pu RW 1101: 1k & 2k pu (in parallel) 1111: Native controller selected by Pad Mode controls the Termination All others reserved. If a reserved value is programmed, pad may malfunction. The setting of this field is applicable in all Pad Mode including GPIO. As each Pad Mode may require different termination and isolation, care must be taken in sw/fw in the transition with appropriate register programming. The actual transition sequence requirement may vary on case by case basis depending on the native functions involved. For example, before changing the pad from output to input direction, pu/pd settings should be programmed first to ensure the input does not float momentarily.

0h 9:8 Reserved. RO

Interrupt Select (INTSEL): The Interrupt Select defines which interrupt line driven from the GPIO Controller toggles when an interrupt is detected on this pad. 50h 0 = Interrupt Line 0 7:0 RO 1 = Interrupt Line 1 .... Up to the max IOxAPIC IRQ supported

6.3.15 Pad Configuration DW0 (PAD_CFG_DW0_GPD_1)—Offset 408h

Same description as PAD_CFG_DW0_GPD_0.

6.3.16 Pad Configuration DW1 (PAD_CFG_DW1_GPD_1)—Offset 40Ch

Same description as PAD_CFG_DW1_GPD_0. Exception: The default value of the INTSEL bit field in this register is: 51h

6.3.17 Pad Configuration DW0 (PAD_CFG_DW0_GPD_2)—Offset 410h

Same description as PAD_CFG_DW0_GPD_0.

332219-002 509 GPIO for SKL PCH-H

6.3.18 Pad Configuration DW1 (PAD_CFG_DW1_GPD_2)—Offset 414h

Same description as PAD_CFG_DW1_GPD_0. Exception: The default value of the INTSEL bit field in this register is: 52h

6.3.19 Pad Configuration DW0 (PAD_CFG_DW0_GPD_3)—Offset 418h

Same description as PAD_CFG_DW0_GPD_0.

6.3.20 Pad Configuration DW1 (PAD_CFG_DW1_GPD_3)—Offset 41Ch

Same description as PAD_CFG_DW1_GPD_0. Exception: The default value of the INTSEL bit field in this register is : 53h

6.3.21 Pad Configuration DW0 (PAD_CFG_DW0_GPD_4)—Offset 420h

Same description as PAD_CFG_DW0_GPD_0.

6.3.22 Pad Configuration DW1 (PAD_CFG_DW1_GPD_4)—Offset 424h

Same description as PAD_CFG_DW1_GPD_0. Exception: The default value of the INTSEL bit field in this register is: 54h

6.3.23 Pad Configuration DW0 (PAD_CFG_DW0_GPD_5)—Offset 428h

Same description as PAD_CFG_DW0_GPD_0.

6.3.24 Pad Configuration DW1 (PAD_CFG_DW1_GPD_5)—Offset 42Ch

Same description as PAD_CFG_DW1_GPD_0. Exception: The default value of the INTSEL bit field in this register is: 55h

6.3.25 Pad Configuration DW0 (PAD_CFG_DW0_GPD_6)—Offset 430h

Same description as PAD_CFG_DW0_GPD_0.

6.3.26 Pad Configuration DW1 (PAD_CFG_DW1_GPD_6)—Offset 434h

Same description as PAD_CFG_DW1_GPD_0. Exception: The default value of the INTSEL bit field in this register is: 56h

510 332219-002

GPIO for SKL PCH-H

6.3.27 Pad Configuration DW0 (PAD_CFG_DW0_GPD_7)—Offset 438h

Same description as PAD_CFG_DW0_GPD_0.

6.3.28 Pad Configuration DW1 (PAD_CFG_DW1_GPD_7)—Offset 43Ch

Same description as PAD_CFG_DW1_GPD_0. Exception: The default value of the INTSEL bit field in this register is: 57h

6.3.29 Pad Configuration DW0 (PAD_CFG_DW0_GPD_8)—Offset 440h

Same description as PAD_CFG_DW0_GPD_0.

6.3.30 Pad Configuration DW1 (PAD_CFG_DW1_GPD_8)—Offset 444h

Same description as PAD_CFG_DW1_GPD_0. Exception: The default value of the INTSEL bit field in this register is: 58h

6.3.31 Pad Configuration DW0 (PAD_CFG_DW0_GPD_9)—Offset 448h

Same description as PAD_CFG_DW0_GPD_0.

6.3.32 Pad Configuration DW1 (PAD_CFG_DW1_GPD_9)—Offset 44Ch

Same description as PAD_CFG_DW1_GPD_0. Exception: The default value of the INTSEL bit field in this register is: 59h

6.3.33 Pad Configuration DW0 (PAD_CFG_DW0_GPD_10)—Offset 450h

Same description as PAD_CFG_DW0_GPD_0.

6.3.34 Pad Configuration DW1 (PAD_CFG_DW1_GPD_10)—Offset 454h

Same description as PAD_CFG_DW1_GPD_0. Exception: The default value of the INTSEL bit field in this register is: 5Ah

6.3.35 Pad Configuration DW0 (PAD_CFG_DW0_GPD_11)—Offset 458h

Same description as PAD_CFG_DW0_GPD_0.

332219-002 511 GPIO for SKL PCH-H

6.3.36 Pad Configuration DW1 (PAD_CFG_DW1_GPD_11)—Offset 45Ch

Same description as PAD_CFG_DW1_GPD_0. Exception: The default value of the INTSEL bit field in this register is: 5Bh

6.4 GPIO Community 3 Registers Summary

Community 3 Registers are for GPP_I group.

Table 6-4. Summary of GPIO Community 3 Registers

Offset Offset Default Register Name (ID)—Offset Start End Value

4h 7h Capability List Register (CAP_LIST_0)—Offset 4h 0h

8h Bh Family Base Address (FAMBAR)—Offset 8h 300h

Ch Fh Pad Base Address (PADBAR)—Offset Ch 400h

10h 13h Miscellaneous Configuration (MISCCFG)—Offset 10h 43200h

20h 23h Pad Ownership (PAD_OWN_GPP_I_0)—Offset 20h 0h

24h 27h Pad Ownership (PAD_OWN_GPP_I_1)—Offset 24h 0h

90h 93h Pad Configuration Lock (PADCFGLOCK_GPP_I_0)—Offset 90h 0h

94h 97h Pad Configuration Lock (PADCFGLOCKTX_GPP_I_0)—Offset 94h 0h

D0h D3h Host Software Pad Ownership (HOSTSW_OWN_GPP_I_0)—Offset D0h 0h

100h 103h GPI Interrupt Status (GPI_IS_GPP_I_0)—Offset 100h 0h

120h 123h GPI Interrupt Enable (GPI_IE_GPP_I_0)—Offset 120h 0h

GPI General Purpose Events Status (GPI_GPE_STS_GPP_I_0)—Offset 140h 143h 0h 140h

GPI General Purpose Events Enable (GPI_GPE_EN_GPP_I_0)—Offset 160h 163h 0h 160h

180h 183h SMI Status (GPI_SMI_STS_GPP_I_0)—Offset 180h 0h

1A0h 1A3h SMI Enable (GPI_SMI_EN_GPP_I_0)—Offset 1A0h 0h

1C0h 1C3h NMI Status (GPI_NMI_STS_GPP_I_0)—Offset 1C0h 0h

1E0h 1E3h NMI Enable (GPI_NMI_EN_GPP_I_0)—Offset 1E0h 0h

4000xx00h 400h 403h Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_0)—Offset 400h See register for xx value

404h 407h Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_0)—Offset 404h 0h

408h 40Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_1)—Offset 408h 0h

4000xx00h 40Ch 40Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_1)—Offset 40Ch See register for xx value

410h 413h Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_2)—Offset 410h 0h

4000xx00h 414h 417h Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_2)—Offset 414h See register for xx value

418h 41Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_3)—Offset 418h 0h

4000xx00h 41Ch 41Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_3)—Offset 41Ch See register for xx value

420h 423h Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_4)—Offset 420h 0h

512 332219-002

GPIO for SKL PCH-H

Table 6-4. Summary of GPIO Community 3 Registers (Continued)

Offset Offset Default Register Name (ID)—Offset Start End Value

4000xx00h 424h 427h Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_4)—Offset 424h See register for xx value

428h 42Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_5)—Offset 428h 0h

4000xx00h 42Ch 42Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_5)—Offset 42Ch See register for xx value

430h 433h Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_6)—Offset 430h 0h

4000xx00h 434h 437h Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_6)—Offset 434h See register for xx value

438h 43Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_7)—Offset 438h 0h

4000xx00h 43Ch 43Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_7)—Offset 43Ch See register for xx value

440h 443h Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_8)—Offset 440h 0h

4000xx00h 444h 447h Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_8)—Offset 444h See register for xx value

448h 44Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_9)—Offset 448h 0h

4000xx00h 44Ch 44Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_9)—Offset 44Ch See register for xx value

450h 453h Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_10)—Offset 450h 0h

4000xx00h 454h 457h Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_10)—Offset 454h See register for xx value

6.4.1 Capability List Register (CAP_LIST_0)—Offset 4h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 CapID RSVD_0 NxtCapLPtr

332219-002 513 GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h Reserved (RSVD_0) 31:24 RO

0h Capability Identification (CapID): Capability Identification (CapID) A unique 23:16 identification for the current capability. A value of 0 is reserved, and must not be RO used by any capability. Note: This field is always 0 for the first Capability List register.

Next Capability List Pointer (NxtCapLPtr): Next Capability List Pointer 0h (NxtCapLPtr) Specify the DW-aligned Pointer/Address to the next item in this 15:0 RO capabilities list and must be 0 if there is no capability at all or this is the last capability in the list.

6.4.2 Family Base Address (FAMBAR)—Offset 8h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 300h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000001100000000 RSVD_0 FAMBAR

Bit Default & Field Name (ID): Description Range Access

0h Reserved (RSVD_0) 31:16 RO

Family Base Address (FAMBAR): This field provides the starting byte-align 300h address of Family0 register sets. It is meant for software to discover from where the 15:0 RO very first Family register (i.e. Family0 register) starts to compute the next Families address offsets.

6.4.3 Pad Base Address (PADBAR)—Offset Ch

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 400h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000010000000000 RSVD_0 PADBAR

514 332219-002

GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h Reserved (RSVD_0) 31:16 RO

400h Pad Base Address (PADBAR): This field provides the starting byte-align address of 15:0 Pad0 register sets. It is meant for software to discover from where the very first Pad RO register (i.e. Pad0 register) starts to compute the next Pad address offsets.

6.4.4 Miscellaneous Configuration (MISCCFG)—Offset 10h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 43200h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000001000011001000000000 RSVD RSVD GPDLCGEN GPDPCGEN GPE0_DW2 GPE0_DW1 GPE0_DW0 GSXSLCGEN GPIO_DRIVER_IRQ_ROUTE

Bit Default & Field Name (ID): Description Range Access

0h 31:20 Reserved. RO

GPIO Group to GPE_DW0 assignment encoding (GPE0_DW2): This register assigns a specific GPIO Group to the ACPI GPE0[95:64]. The selected GPIO group will be mapped to lower bits of the GPE register 0h = GPP_A[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 1h = GPP_B[23:0] mapped to GPE[87:64]; GPE[95:88] not used.

4h 2h = GPP_C[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 19:16 3h = GPP_D[23:0] mapped to GPE[87:64]; GPE[95:88] not used. RW 4h = GPP_E[12:0] mapped to GPE[76:64]; GPE[95:77] not used. 5h = GPP_F[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 6h = GPP_G[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 7h = GPP_H[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 8h = GPP_I[10:0] mapped to GPE[74:64]; GPE[95:75] not used. 9h = GPD[11:0] mapped to GPE[75:64]; GPE[95:76] not used.

GPIO Group to GPE_DW0 assignment encoding (GPE0_DW1): This register assigns a specific GPIO Group to the ACPI GPE0[63:32]. The selected GPIO group will be mapped to lower bits of the GPE register 0h = GPP_A[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 1h = GPP_B[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 3h 2h = GPP_C[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 15:12 3h = GPP_D[23:0] mapped to GPE[55:32]; GPE[63:56] not used. RW 4h = GPP_E[12:0] mapped to GPE[44:32]; GPE[63:45] not used. 5h = GPP_F[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 6h = GPP_G[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 7h = GPP_H[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 8h = GPP_I[10:0] mapped to GPE[42:32]; GPE[63:43] not used. 9h = GPD[11:0] mapped to GPE[43:32]; GPE[63:44] not used.

332219-002 515 GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

GPIO Group to GPE_DW0 assignment encoding (GPE0_DW0): This register assigns a specific GPIO Group to the ACPI GPE0[31:0]. The selected GPIO group will be mapped to lower bits of the GPE register 0h = GPP_A[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 1h = GPP_B[23:0] mapped to GPE[23:0]; GPE[31:24] not used.

2h 2h = GPP_C[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 11:8 3h = GPP_D[23:0] mapped to GPE[23:0]; GPE[31:24] not used. RW 4h = GPP_E[12:0] mapped to GPE[12:0]; GPE[31:13] not used. 5h = GPP_F[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 6h = GPP_G[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 7h = GPP_H[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 8h = GPP_I[10:0] mapped to GPE[10:0]; GPE[31:11] not used. 9h = GPD[11:0] mapped to GPE[11:0]; GPE[31:12] not used.

0h 7:4 Reserved. RO

GPIO Driver IRQ Route (GPIO_DRIVER_IRQ_ROUTE): GPIO Driver 0h IRQ_ROUTE[1:0]: Specifies the APIC IRQ globally for all pads within the current 3 community (GPI_IS with corresponding GPI_IE enable). RW 0 = IRQ14 1 = IRQ15

GSX Static Local Clock Gating (GSXSLCGEN): Specifies whether the GSX 0h controller should be statically clock gated for power saving if it is not enabled (even 2 though the capability is available). RW 0 = Disable dynamic local clock gating 1 = Enable dynamic local clock gating.

GPIO Dynamic Partition Clock Gating Enable (GPDPCGEN): Specifies whether 0h 1 the GPIO Community should take part in partition clock gating RW 0 = Disable participation in dynamic partition clock gating 1 = Enable participation in dynamic partition clock gating.

GPIO Dynamic Local Clock Gating Enable (GPDLCGEN): Specifies whether the 0h GPIO Community should perform local clock gating. 0 RW 0 = Disable dynamic local clock gating 1 = Enable dynamic local clock gating.

6.4.5 Pad Ownership (PAD_OWN_GPP_I_0)—Offset 20h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD PAD_OWN_GPP_I_7 PAD_OWN_GPP_I_6 PAD_OWN_GPP_I_5 PAD_OWN_GPP_I_4 PAD_OWN_GPP_I_3 PAD_OWN_GPP_I_2 PAD_OWN_GPP_I_1 PAD_OWN_GPP_I_0

516 332219-002

GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h 31:30 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_I_7): Same description as bit 0, except that 29:28 RO the bit field applies to GPP_I7.

0h 27:26 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_I_6): Same description as bit 0, except that 25:24 RO the bit field applies to GPP_I6.

0h 23:22 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_I_5): Same description as bit 0, except that 21:20 RO the bit field applies to GPP_I5.

0h 19:18 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_I_4): Same description as bit 0, except that 17:16 RO the bit field applies to GPP_I4.

0h 15:14 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_I_3): Same description as bit 0, except that 13:12 RO the bit field applies to GPP_I3.

0h 11:10 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_I_2): Same description as bit 0, except that 9:8 RO the bit field applies to GPP_I2.

0h 7:6 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_I_1): Same description as bit 0, except that 5:4 RO the bit field applies to GPP_I1.

0h 3:2 Reserved. RO

Pad Ownership (PAD_OWN_GPP_I_0): 00 = Host GPIO ACPI Mode or GPIO Driver Mode. Host software (ACPI or GPIO Driver) has ownership of the pad. In Host GPIO Driver Mode (refer to HOSTSW_OWN), GPIO input event update is limited to 0h GPI_STS update only. Otherwise in Host ACPI Mode, updates are limited to 1:0 RO GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. 01 = ME GPIO Mode. ME has ownership of the pad. 10 = ISH GPIO Mode.ME has ownership of the pad 11 = Reserved

6.4.6 Pad Ownership (PAD_OWN_GPP_I_1)—Offset 24h

Same description as PAD_OWN_GPP_I_0, except that this register is for GPP_I[10:8]

6.4.7 Pad Configuration Lock (PADCFGLOCK_GPP_I_0)—Offset 90h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

332219-002 517 GPIO for SKL PCH-H

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD PADCFGLOCK_GPP_I_9 PADCFGLOCK_GPP_I_8 PADCFGLOCK_GPP_I_7 PADCFGLOCK_GPP_I_6 PADCFGLOCK_GPP_I_5 PADCFGLOCK_GPP_I_4 PADCFGLOCK_GPP_I_3 PADCFGLOCK_GPP_I_2 PADCFGLOCK_GPP_I_1 PADCFGLOCK_GPP_I_0 PADCFGLOCK_GPP_I_10

Bit Default & Field Name (ID): Description Range Access

0h 31:11 Reserved. RO

0h Pad Config Lock (PADCFGLOCK_GPP_I_10): Applied to GPP_I10. Same 10 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_I_9): Applied to GPP_I9. Same description 9 RW as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_I_8): Applied to GPP_I8. Same description 8 RW as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_I_7): Applied to GPP_I7. Same description 7 RW as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_I_6): Applied to GPP_I6. Same description 6 RW as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_I_5): Applied to GPP_I5. Same description 5 RW as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_I_4): Applied to GPP_I4. Same description 4 RW as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_I_3): Applied to GPP_I3. Same description 3 RW as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_I_2): Applied to GPP_I2. Same description 2 RW as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_I_1): Applied to GPP_I1. Same description 1 RW as bit 0.

Pad Config Lock (PADCFGLOCK_GPP_I_0): Pad Configuration Lock locks specific register fields in the GPP specific registers from being configured. The registers affected become Read-Only and software writes to these registers have no effect. 0 = Unlock 1 = Lock the following register fields as read-only (RO): 0h 0 - Pad Configuration registers (exclude GPIOTXState) RW - GPI_NMI_EN Register (if implemented) - GPI_SMI_EN Register (if implemented) - GPI_GPE_EN Register (if implemented) When PadCfgLock is written from a '1' to a '0' (unlock), a synchronous SMI# is generated if enabled. This ensures that only SMM code can change the above GPIO registers after the lockdown.

6.4.8 Pad Configuration Lock (PADCFGLOCKTX_GPP_I_0)— Offset 94h

Access Method

518 332219-002

GPIO for SKL PCH-H

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD PADCFGLOCKTX_GPP_I_9 PADCFGLOCKTX_GPP_I_8 PADCFGLOCKTX_GPP_I_7 PADCFGLOCKTX_GPP_I_6 PADCFGLOCKTX_GPP_I_5 PADCFGLOCKTX_GPP_I_4 PADCFGLOCKTX_GPP_I_3 PADCFGLOCKTX_GPP_I_2 PADCFGLOCKTX_GPP_I_1 PADCFGLOCKTX_GPP_I_0 PADCFGLOCKTX_GPP_I_10

Bit Default & Field Name (ID): Description Range Access

0h 31:11 Reserved. RO

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_I_10): Applied to GPP_I10. 10 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_I_9): Applied to GPP_I9. Same 9 RW description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_I_8): Applied to GPP_I8. Same 8 RW description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_I_7): Applied to GPP_I7. Same 7 RW description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_I_6): Applied to GPP_I6. Same 6 RW description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_I_5): Applied to GPP_I5. Same 5 RW description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_I_4): Applied to GPP_I4. Same 4 RW description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_I_3): Applied to GPP_I3. Same 3 RW description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_I_2): Applied to GPP_I2. Same 2 RW description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_I_1): Applied to GPP_I1. Same 1 RW description as bit 0.

Pad Config Lock TXState (PADCFGLOCKTX_GPP_I_0): PadCfgLockTx locks the GPIOTxState bit from being configured. The GPIOTxState register becomes Read- Only and software writes to the register have no effect. 0h 0 = Unlock 0 RW 1 = Locks the Pad Configuration GPIOTXState field as read-only (RO) When PadCfgLockTx is written from a '1' to a '0' (unlock), a synchronous SMI# is generated if enabled. This ensures that only SMM code can change the above GPIO registers after the lockdown.

332219-002 519 GPIO for SKL PCH-H

6.4.9 Host Software Pad Ownership (HOSTSW_OWN_GPP_I_0)—Offset D0h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD HOSTSW_OWN_GPP_I_9 HOSTSW_OWN_GPP_I_8 HOSTSW_OWN_GPP_I_7 HOSTSW_OWN_GPP_I_6 HOSTSW_OWN_GPP_I_5 HOSTSW_OWN_GPP_I_4 HOSTSW_OWN_GPP_I_3 HOSTSW_OWN_GPP_I_2 HOSTSW_OWN_GPP_I_1 HOSTSW_OWN_GPP_I_0 HOSTSW_OWN_GPP_I_10

Bit Default & Field Name (ID): Description Range Access

0h 31:11 Reserved. RO

0h HostSW_Own (HOSTSW_OWN_GPP_I_10): Applied to GPP_I10. Same 10 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_I_9): Applied to GPP_I9. Same description 9 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_I_8): Applied to GPP_I8. Same description 8 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_I_7): Applied to GPP_I7. Same description 7 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_I_6): Applied to GPP_I6. Same description 6 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_I_5): Applied to GPP_I5. Same description 5 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_I_4): Applied to GPP_I4. Same description 4 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_I_3): Applied to GPP_I3. Same description 3 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_I_2): Applied to GPP_I2. Same description 2 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_I_1): Applied to GPP_I1. Same description 1 RW as bit 0.

HostSW_Own (HOSTSW_OWN_GPP_I_0): This register determines the appropriate host status bit update when a pad is under host ownership. 0h 0 0 = ACPI Mode. GPIO input event updates are limited to GPI_GPE_STS, RW GPI_NMI_STS and/or GPI_SMI_STS. GPI_STS update is masked. 1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked.

520 332219-002

GPIO for SKL PCH-H

6.4.10 GPI Interrupt Status (GPI_IS_GPP_I_0)—Offset 100h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_INT_STS_GPP_I_9 GPI_INT_STS_GPP_I_8 GPI_INT_STS_GPP_I_7 GPI_INT_STS_GPP_I_6 GPI_INT_STS_GPP_I_5 GPI_INT_STS_GPP_I_4 GPI_INT_STS_GPP_I_3 GPI_INT_STS_GPP_I_2 GPI_INT_STS_GPP_I_1 GPI_INT_STS_GPP_I_0 GPI_INT_STS_GPP_I_10

Bit Default & Field Name (ID): Description Range Access

0h 31:11 Reserved. RO

0h GPI Interrupt Status (GPI_INT_STS_GPP_I_10): Applied to GPP_I10. Same 10 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_I_9): Applied to GPP_I9. Same 9 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_I_8): Applied to GPP_I8. Same 8 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_I_7): Applied to GPP_I7. Same 7 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_I_6): Applied to GPP_I6. Same 6 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_I_5): Applied to GPP_I5. Same 5 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_I_4): Applied to GPP_I4. Same 4 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_I_3): Applied to GPP_I3. Same 3 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_I_2): Applied to GPP_I2. Same 2 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_I_1): Applied to GPP_I1. Same 1 RW1C description as bit 0.

GPI Interrupt Status (GPI_INT_STS_GPP_I_0): This register determines the appropriate host status bit update when a pad is under host ownership. 0h 0 = ACPI Mode. GPIO input event updates are limited to GPI_GPE_STS, 0 RW1C GPI_NMI_STS and/or GPI_SMI_STS. GPI_STS update is masked. 1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked.

332219-002 521 GPIO for SKL PCH-H

6.4.11 GPI Interrupt Enable (GPI_IE_GPP_I_0)—Offset 120h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_INT_EN_GPP_I_9 GPI_INT_EN_GPP_I_8 GPI_INT_EN_GPP_I_7 GPI_INT_EN_GPP_I_6 GPI_INT_EN_GPP_I_5 GPI_INT_EN_GPP_I_4 GPI_INT_EN_GPP_I_3 GPI_INT_EN_GPP_I_2 GPI_INT_EN_GPP_I_1 GPI_INT_EN_GPP_I_0 GPI_INT_EN_GPP_I_10

Bit Default & Field Name (ID): Description Range Access

0h 31:11 Reserved. RO

0h GPI Interrupt Enable (GPI_INT_EN_GPP_I_10): Applied to GPP_I10. Same 10 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_I_9): Applied to GPP_I9. Same 9 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_I_8): Applied to GPP_I8. Same 8 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_I_7): Applied to GPP_I7. Same 7 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_I_6): Applied to GPP_I6. Same 6 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_I_5): Applied to GPP_I5. Same 5 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_I_4): Applied to GPP_I4. Same 4 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_I_3): Applied to GPP_I3. Same 3 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_I_2): Applied to GPP_I2. Same 2 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_I_1): Applied to GPP_I1. Same 1 RW description as bit 0.

GPI Interrupt Enable (GPI_INT_EN_GPP_I_0): This bit is used to enable/ disable the generation of APIC interrupt when the corresponding GPI_INT_STS bit is 0h set. 0 RW 0 = disable interrupt generation 1 = enable interrupt generation Refer to GPI_IRQ_ROUTE for host GPIO Driver Mode interrupt routing.

522 332219-002

GPIO for SKL PCH-H

6.4.12 GPI General Purpose Events Status (GPI_GPE_STS_GPP_I_0)—Offset 140h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_GPE_STS_GPP_I_9 GPI_GPE_STS_GPP_I_8 GPI_GPE_STS_GPP_I_7 GPI_GPE_STS_GPP_I_6 GPI_GPE_STS_GPP_I_5 GPI_GPE_STS_GPP_I_4 GPI_GPE_STS_GPP_I_3 GPI_GPE_STS_GPP_I_2 GPI_GPE_STS_GPP_I_1 GPI_GPE_STS_GPP_I_0 GPI_GPE_STS_GPP_I_10

Bit Default & Field Name (ID): Description Range Access

0h 31:11 Reserved. RO

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_I_10): Applied to 10 RW1C GPP_I10. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_I_9): Applied to 9 RW1C GPP_I9. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_I_8): Applied to 8 RW1C GPP_I8. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_I_7): Applied to 7 RW1C GPP_I7. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_I_6): Applied to 6 RW1C GPP_I6. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_I_5): Applied to 5 RW1C GPP_I5. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_I_4): Applied to 4 RW1C GPP_I4. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_I_3): Applied to 3 RW1C GPP_I3. Same description as bit 0.

332219-002 523 GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_I_2): Applied to 2 RW1C GPP_I2. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_I_1): Applied to 1 RW1C GPP_I1. Same description as bit 0.

GPI General Purpose Events Status (GPI_GPE_STS_GPP_I_0): These bits are set any time the corresponding GPIO pad is set up as an input, under host ownership and the corresponding GPIO signal is high(or low if the corresponding RXINV bit is set). 0h If the corresponding enable bit is set in the GPI_GPE_EN register, then when the 0 GPI_GPE_STS bit is set: RW1C - If the system is in an S3-S5 state, the event will also wake the system. - If the system is in an S0 state (or upon waking back to an S0 state), an SCI will be caused, depending on the GPIRoutSCI bit for the corresponding pad. These bits are sticky bits and are cleared by writing a 1 back to this bit position. The state of GPI_GPE_EN does not prevent the setting of GPI_GPE_STS.

6.4.13 GPI General Purpose Events Enable (GPI_GPE_EN_GPP_I_0)—Offset 160h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_GPE_EN_GPP_I_9 GPI_GPE_EN_GPP_I_8 GPI_GPE_EN_GPP_I_7 GPI_GPE_EN_GPP_I_6 GPI_GPE_EN_GPP_I_5 GPI_GPE_EN_GPP_I_4 GPI_GPE_EN_GPP_I_3 GPI_GPE_EN_GPP_I_2 GPI_GPE_EN_GPP_I_1 GPI_GPE_EN_GPP_I_0 GPI_GPE_EN_GPP_I_10

Bit Default & Field Name (ID): Description Range Access

0h 31:11 Reserved. RO

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_I_10): Applied to 10 RW GPP_I10. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_I_9): Applied to 9 RW GPP_I9. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_I_8): Applied to 8 RW GPP_I8. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_I_7): Applied to 7 RW GPP_I7. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_I_6): Applied to 6 RW GPP_I6. Same description as bit 0.

524 332219-002

GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_I_5): Applied to 5 RW GPP_I5. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_I_4): Applied to 4 RW GPP_I4. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_I_3): Applied to 3 RW GPP_I3. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_I_2): Applied to 2 RW GPP_I2. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_I_1): Applied to 1 RW GPP_I1. Same description as bit 0.

GPI General Purpose Events Enable (GPI_GPE_EN_GPP_I_0): This bit is used to enable/disable the generation of GPE to cause SCI and/or wake when the

0h corresponding GPI_GPE_STS bit is set. 0 0 = disable GPE generation RW 1 = enable GPE generation Note: The pad must also be routed for GPE functionality in order for GPE to be generated, i.e. the corresponding GPIRoutSCI must be set to ‘1’.

6.4.14 SMI Status (GPI_SMI_STS_GPP_I_0)—Offset 180h

Register bits in this register are implemented for GPP_I signals that have SMI capability only. Other bits are reserved and RO.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_SMI_STS_GPP_I_3 GPI_SMI_STS_GPP_I_2 GPI_SMI_STS_GPP_I_1 GPI_SMI_STS_GPP_I_0

Bit Default & Field Name (ID): Description Range Access

0h 31:4 Reserved. RO

0h GPI SMI Status (GPI_SMI_STS_GPP_I_3): Applied to GPP_I3. Same description 3 RW1C as bit 0.

332219-002 525 GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h GPI SMI Status (GPI_SMI_STS_GPP_I_2): Applied to GPP_I2. Same description 2 RW1C as bit 0.

0h GPI SMI Status (GPI_SMI_STS_GPP_I_1): Applied to GPP_I1. Same description 1 RW1C as bit 0.

GPI SMI Status (GPI_SMI_STS_GPP_I_0): This bit is set to 1 by hardware when a level event (See RxEdCfg,RxInv) is detected, and all the following conditions are true: - The corresponding pad is used in GPIO input mode - The corresponding PAD_OWN[2:0] is ‘000’ (i.e. ACPI GPIO Mode). 0h If the following conditions are true, then an SMI will be generated if the 0 GPI_SMI_STS bit is set: RW1C 1. The corresponding bit in the GPI_SMI_EN register is set 2. The corresponding pad’s GPIROUTSMI is set Writing a value of 1 will clear the bit while writing a value of 0 has no effect. 0 = There is no SMI event 1 = There is an SMI event The state of GPI_SMI_EN does not prevent the setting of GPI_SMI_STS. Defaults for these bits are dependent on the state of the GPI pads.

6.4.15 SMI Enable (GPI_SMI_EN_GPP_I_0)—Offset 1A0h

Register bits in this register are implemented for GPP_I signals that have SMI capability only. Other bits are reserved and RO.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_SMI_EN_GPP_I_3 GPI_SMI_EN_GPP_I_2 GPI_SMI_EN_GPP_I_1 GPI_SMI_EN_GPP_I_0

Bit Default & Field Name (ID): Description Range Access

0h 31:4 Reserved. RO

0h GPI SMI Enable (GPI_SMI_EN_GPP_I_3): Applied to GPP_I3. Same description 3 RW as bit 0.

526 332219-002

GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h GPI SMI Enable (GPI_SMI_EN_GPP_I_2): Applied to GPP_I2. Same description 2 RW as bit 0.

0h GPI SMI Enable (GPI_SMI_EN_GPP_I_1): Applied to GPP_I1. Same description 1 RW as bit 0.

GPI SMI Enable (GPI_SMI_EN_GPP_I_0): This bit is used to enable/disable the generation of SMI when the corresponding GPI_SMI_STS bit is set. The pad must also be routed for SMI functionality in order for SMI to be generated, i.e. the 0h corresponding GPIROUTSMI must be set to '1'. 0 0 = disable SMI generation RW 1 = enable SMI generation Note: Each of the bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. E.g. if the PadCfgLock of pad0 is '1', bit0 of this bit is locked down to read-only.

6.4.16 NMI Status (GPI_NMI_STS_GPP_I_0)—Offset 1C0h

Register bits in this register are implemented for GPP_I signals that have NMI capability only. Other bits are reserved and RO.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_NMI_STS_GPP_I_3 GPI_NMI_STS_GPP_I_2 GPI_NMI_STS_GPP_I_1 GPI_NMI_STS_GPP_I_0

Bit Default & Field Name (ID): Description Range Access

0h 31:4 Reserved. RO

0h GPI NMI Status (GPI_NMI_STS_GPP_I_3): Applied to GPP_I3. Same description 3 RW1C as bit 0.

332219-002 527 GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h GPI NMI Status (GPI_NMI_STS_GPP_I_2): Applied to GPP_I2. Same description 2 RW1C as bit 0.

0h GPI NMI Status (GPI_NMI_STS_GPP_I_1): Applied to GPP_I1. Same description 1 RW1C as bit 0.

GPI NMI Status (GPI_NMI_STS_GPP_I_0): This bit is set to 1 by hardware when an edge event is detected (See RxEdCfg, RxInv) on pad and all the following conditions are true: - The corresponding pad is used in GPIO input mode (PMode) 0h - The corresponding GPIONMIRout is set to 1, i.e. programmed to route as NMI 0 RW1C - The corresponding GPIOOwn[2:0] is ‘000’ (i.e. ACPI GPIO Mode). - The corresponding GPI_NMI_EN is set Writing a value of 1 will clear the bit while writing a value of 0 has no effect. 0 = There is no NMI event 1 = There is an NMI event

6.4.17 NMI Enable (GPI_NMI_EN_GPP_I_0)—Offset 1E0h

Register bits in this register are implemented for GPP_I signals that have NMI capability only. Other bits are reserved and RO.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_NMI_EN_GPP_I_3 GPI_NMI_EN_GPP_I_2 GPI_NMI_EN_GPP_I_1 GPI_NMI_EN_GPP_I_0

Bit Default & Field Name (ID): Description Range Access

0h 31:4 Reserved. RO

0h GPI NMI Enable (GPI_NMI_EN_GPP_I_3): Applied to GPP_I3. Same description 3 RW as bit 0.

528 332219-002

GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h GPI NMI Enable (GPI_NMI_EN_GPP_I_2): Applied to GPP_I2. Same description 2 RW as bit 0.

0h GPI NMI Enable (GPI_NMI_EN_GPP_I_1): Applied to GPP_I1. Same description 1 RW as bit 0.

GPI NMI Enable (GPI_NMI_EN_GPP_I_0): This bit is used to enable/disable the generation of NMI when the corresponding GPI_NMI_STS bit is set and its GPIROUTNMI is set. 0h 0 0 = disable NMI generation RW 1 = enable NMI generation Each bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. E.g. if the PadCfgLock of pad0 is ‘1’, bit0 of this bit is locked down to read-only.

6.4.18 Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_0)— Offset 400h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 4000xx00h

3 2 2 2 1 1 840 1 8 4 0 6 2

01000000000000000000001100000000 RSVD RSVD RSVD RSVD RXINV PMODE2 PMODE1 PMODE0 GPIOTXDIS GPIORXDIS PADRSTCFG GPIROUTSCI GPIROUTSMI GPIROUTNMI GPIOTXSTATE GPIORXSTATE GPIROUTIOXAPIC

Bit Default & Field Name (ID): Description Range Access

Pad Reset Config (PADRSTCFG): This register controls which reset is used to reset GPIO pad register fields in PAD_CFG_DW0 and PAD_CFG_DW1 registers. This register can be used for Sx isolation of the associated signal if needed.

1h 00 = RSMRST# 31:30 01 = Host deep reset. This reset occurs when a host reset (with or without power RW cycle) is initiated or a global reset is initiated, except that the reset does not assert when in S3/S4/S5. 10 = PLTRST# 11 = Reserved

0h 29:24 Reserved. RO

RX Invert (RXINV): This bit determines if the selected pad state should go through the polarity inversion stage. This field is only applicable when the RX buffer is configured as an input in either GPIO Mode or native function mode. The polarity inversion takes place at the mux node of raw vs filtered or non-filtered RX pad state, 0h as determined by PreGfRXsel and RXPadStSel This bit does not affect GPIORXState. 23 During host ownership GPIO Mode, when this bit is set to '1', then the RX pad state is RW inverted as it is sent to the GPIO-to-IOxAPIC, GPE/SCI, SMI, NMI logic or GPI_IS[n] that is using it. This is used to allow active-low and active-high inputs to cause IRQ, SMI#, SCI or NMI. 0 = No inversion 1 = Inversion

332219-002 529 GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h 22:21 Reserved. RO

GPIO Input Route IOxAPIC (GPIROUTIOXAPIC): Determines if the pad can be routed to cause peripheral IRQ when configured in GPIO input mode. If the pad is not

0h configured in GPIO input mode, this field has no effect. 20 0 = Routing does not cause peripheral IRQ RW 1 = Routing can cause peripheral IRQ Note: This bit does not affect any interrupt status bit within GPIO, but is used as the last qualifier for the peripheral IRQ indication to the intended recipient(s).

GPIO Input Route SCI (GPIROUTSCI): Determines if the pad can be routed to cause SCI when configured in GPIO input mode. If the pad is not configured in GPIO 0h input mode, this field has no effect. 19 0 = Routing does not cause SCI. RW 1 = Routing can cause SCI Note: This bit does not affect any interrupt status bit within GPIO, but is used as the last qualifier for the GPE indication to the intended recipient(s).

GPIO Input Route SMI (GPIROUTSMI): Determines if the pad can be routed to cause SMI when configured in GPIO input mode. If the pad is not configured in GPIO input mode, this field has no effect. 0h 0 = Routing does not cause SMI. 18 RW 1 = Routing can cause SMI. Note: This bit does not affect any interrupt status bit within GPIO, but is used as the last qualifier for the SMI indication to the intended recipient(s). This bit only applies to a GPIO that has SMI capability. Otherwise, the bit is RO.

GPIO Input Route NMI (GPIROUTNMI): Determines if the pad can be routed to cause NMI when configured in GPIO input mode. If the pad is not configured in GPIO input mode, this field has no effect. 0 = Routing does not cause NMI. 0h 1 = Routing can cause NMI. 17 RW Note: This bit also affects GPI_NMI_STS. If '0', GPI_NMI_STS is always clear. If '1', GPI_NMI_STS could be set (depending on GPIOOwn setting) when there is an event. Whether a NMI indication is generated and sent to the intended recipient(s) is also depending on the corresponding GPI_NMI_EN bit. This bit only applies to a GPIO that has NMI capability. Otherwise, the bit is RO.

0h 16:13 Reserved. RO

xx Pad Mode bit 2 (PMODE2): See Pad Mode bit 0 description. 12 RW

xx Pad Mode bit 1 (PMODE1): See Pad Mode bit 0 description. 11 RW

Pad Mode bit 0 (PMODE0): This bit is used in conjunction with Pad Mode bit 1 and 2 . This three-bit field determines whether the Pad is controlled by GPIO controller logic or one of the native functions muxed onto the Pad. 0h = GPIO control the Pad. 1h = native function 1, if applicable, controls the Pad xx 2h = native function 2, if applicable, controls the Pad 10 3h = native function 3, if applicable, controls the Pad RW 4h = enable GPIO blink/PWM capability if applicable (note that not all GPIOs have blink/PWM capability) Dedicated (unmuxed) GPIO shall report RO of all 0’s in this register field If GPIO vs. native mode is configured via soft strap, this bit has no effect.

Default value is determined by the default functionality of the pad.

GPIO RX Disable (GPIORXDIS): 0 = Enable the input buffer (active low enable) of

1h the pad. 9 1 = Disable the input buffer of the pad. RW Notes: When the input buffer is disabled, the internal pad state is always driven to '0'.

1h GPIO TX Disable (GPIOTXDIS): 0 = Enable the output buffer (active low enable) 8 of the pad. RW 1 = Disable the output buffer of the pad; i.e. Hi-Z

530 332219-002

GPIO for SKL PCH-H

Bit Default & Field Name (ID): Description Range Access

0h 7:2 Reserved. RO

0h GPIO RX State (GPIORXSTATE): This is the current internal RX pad state after 1 RO Glitch Filter logic stage and is not affected by PMode and RXINV settings.

0h GPIO TX State (GPIOTXSTATE): 0 = Drive a level '0' to the TX output pad. 0 RW 1 = Drive a level '1' to the TX output pad

6.4.19 Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_0)— Offset 404h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 TERM RSVD RSVD INTSEL

Bit Default & Field Name (ID): Description Range Access

0h 31:14 Reserved. RO

Termination (TERM): The Pad Termination state defines the different weak pull-up and pull-down settings that are supported by the buffer. The settings for [13:10] correspond to: 0000: none 0010: 5k pd 0100: 20k pd 1000: none 1001: 1k pu 1011: 2k pu 0h 1010: 5k pu 13:10 1100: 20k pu RW 1101: 1k & 2k pu (in parallel) 1111: Native controller selected by Pad Mode controls the Termination All others reserved. If a reserved value is programmed, pad may malfunction. The setting of this field is applicable in all Pad Mode including GPIO. As each Pad Mode may require different termination and isolation, care must be taken in sw/fw in the transition with appropriate register programming. The actual transition sequence requirement may vary on case by case basis depending on the native functions involved. For example, before changing the pad from output to input direction, pu/pd settings should be programmed first to ensure the input does not float momentarily.

0h 9:8 Reserved. RO

Interrupt Select (INTSEL): The Interrupt Select indicates which interrupt line driven from the GPIO Controller toggles when an interrupt is detected on this pad. 0h 0 = Interrupt Line 0 7:0 RO 1 = Interrupt Line 1 .... Up to the max IOxAPIC IRQ supported

332219-002 531 GPIO for SKL PCH-H

6.4.20 Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_1)— Offset 408h

Same description as PAD_CFG_DW0_GPP_I_0.

6.4.21 Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_1)— Offset 40Ch

Same description as PAD_CFG_DW1_GPP_I_0. Exception: The default value of the INTSEL bit field in this register is : 00h

6.4.22 Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_2)— Offset 410h

Same description as PAD_CFG_DW0_GPP_I_0.

6.4.23 Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_2)— Offset 414h

Same description as PAD_CFG_DW1_GPP_I_0. Exception: The default value of the INTSEL bit field in this register is : 00h

6.4.24 Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_3)— Offset 418h

Same description as PAD_CFG_DW0_GPP_I_0.

6.4.25 Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_3)— Offset 41Ch

Same description as PAD_CFG_DW1_GPP_I_0. Exception: The default value of the INTSEL bit field in this register is : 00h

6.4.26 Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_4)— Offset 420h

Same description as PAD_CFG_DW0_GPP_I_0.

6.4.27 Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_4)— Offset 424h

Same description as PAD_CFG_DW1_GPP_I_0. Exception: The default value of the INTSEL bit field in this register is : 00h

6.4.28 Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_5)— Offset 428h

Same description as PAD_CFG_DW0_GPP_I_0.

532 332219-002

GPIO for SKL PCH-H

6.4.29 Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_5)— Offset 42Ch

Same description as PAD_CFG_DW1_GPP_I_0. Exception: The default value of the INTSEL bit field in this register is : 00h

6.4.30 Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_6)— Offset 430h

Same description as PAD_CFG_DW0_GPP_I_0.

6.4.31 Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_6)— Offset 434h

Same description as PAD_CFG_DW1_GPP_I_0. Exception: The default value of the INTSEL bit field in this register is : 00h

6.4.32 Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_7)— Offset 438h

Same description as PAD_CFG_DW0_GPP_I_0.

6.4.33 Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_7)— Offset 43Ch

Same description as PAD_CFG_DW1_GPP_I_0. Exception: The default value of the INTSEL bit field in this register is : 00h

6.4.34 Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_8)— Offset 440h

Same description as PAD_CFG_DW0_GPP_I_0.

6.4.35 Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_8)— Offset 444h

Same description as PAD_CFG_DW1_GPP_I_0. Exception: The default value of the INTSEL bit field in this register is : 00h

6.4.36 Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_9)— Offset 448h

Same description as PAD_CFG_DW0_GPP_I_0.

6.4.37 Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_9)— Offset 44Ch

Same description as PAD_CFG_DW1_GPP_I_0. Exception: The default value of the INTSEL bit field in this register is : 00h

332219-002 533 GPIO for SKL PCH-H

6.4.38 Pad Configuration DW0 (PAD_CFG_DW0_GPP_I_10)— Offset 450h

Same description as PAD_CFG_DW0_GPP_I_0.

6.4.39 Pad Configuration DW1 (PAD_CFG_DW1_GPP_I_10)— Offset 454h

Same description as PAD_CFG_DW1_GPP_I_0. Exception: The default value of the INTSEL bit field in this register is : 00h

§ §

534 332219-002

GPIO for SKL PCH-LP

7 GPIO for SKL PCH-LP

7.1 GPIO Community 0 Registers Summary

Community 0 Registers are for GPP_A and GPP_B groups.

Table 7-1. Summary of GPIO Community 0 Registers

Offset Offset Default Register Name (ID)—Offset Start End Value

8h Bh Family Base Address (FAMBAR)—Offset 8h 300h

Ch Fh Pad Base Address (PADBAR)—Offset Ch 400h

10h 13h Miscellaneous Configuration (MISCCFG)—Offset 10h 43200h

20h 23h Pad Ownership (PAD_OWN_GPP_A_0)—Offset 20h 0h

24h 27h Pad Ownership (PAD_OWN_GPP_A_1)—Offset 24h 0h

28h 2Bh Pad Ownership (PAD_OWN_GPP_A_2)—Offset 28h 0h

30h 33h Pad Ownership (PAD_OWN_GPP_B_0)—Offset 30h 0h

34h 37h Pad Ownership (PAD_OWN_GPP_B_1)—Offset 34h 0h

38h 3Bh Pad Ownership (PAD_OWN_GPP_B_2)—Offset 38h 0h

A0h A3h Pad Configuration Lock (PADCFGLOCK_GPP_A)—Offset A0h 0h

A4h A7h Pad Configuration Lock (PADCFGLOCKTX_GPP_A)—Offset A4h 0h

A8h ABh Pad Configuration Lock (PADCFGLOCK_GPP_B)—Offset A8h 0h

ACh AFh Pad Configuration Lock (PADCFGLOCKTX_GPP_B)—Offset ACh 0h

D0h D3h Host Software Pad Ownership (HOSTSW_OWN_GPP_A)—Offset D0h 0h

D4h D7h Host Software Pad Ownership (HOSTSW_OWN_GPP_B)—Offset D4h 0h

100h 103h GPI Interrupt Status (GPI_IS_GPP_A)—Offset 100h 0h

104h 107h GPI Interrupt Status (GPI_IS_GPP_B)—Offset 104h 0h

120h 123h GPI Interrupt Enable (GPI_IE_GPP_A)—Offset 120h 0h

124h 127h GPI Interrupt Enable (GPI_IE_GPP_B)—Offset 124h 0h

140h 143h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A)—Offset 140h 0h

144h 147h GPI General Purpose Events Status (GPI_GPE_STS_GPP_B)—Offset 144h 0h

160h 163h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A)—Offset 160h 0h

164h 167h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_B)—Offset 164h 0h

184h 187h SMI Status (GPI_SMI_STS_GPP_B)—Offset 184h 0h

1A4h 1A7h SMI Enable (GPI_SMI_EN_GPP_B)—Offset 1A4h 0h

1C4h 1C7h NMI Status (GPI_NMI_STS_GPP_B)—Offset 1C4h 0h

1E4h 1E7h NMI Enable (GPI_NMI_EN_GPP_B)—Offset 1E4h 0h

44000x00h 400h 403h Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_0)—Offset 400h See register for xx value

404h 407h Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_0)—Offset 404h 18h

44000x00h 408h 40Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_1)—Offset 408h See register for xx value

332219-002 535 GPIO for SKL PCH-LP

Table 7-1. Summary of GPIO Community 0 Registers (Continued)

Offset Offset Default Register Name (ID)—Offset Start End Value

40Ch 40Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_1)—Offset 40Ch See register

44000x00h 410h 413h Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_2)—Offset 410h See register for xx value

414h 417h Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_2)—Offset 414h See register

44000x00h 418h 41Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_3)—Offset 418h See register for xx value

41Ch 41Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_3)—Offset 41Ch See register

44000x00h 420h 423h Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_4)—Offset 420h See register for xx value

424h 427h Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_4)—Offset 424h See register

44000x00h 428h 42Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_5)—Offset 428h See register for xx value

42Ch 42Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_5)—Offset 42Ch See register

44000x00h 430h 433h Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_6)—Offset 430h See register for xx value

434h 437h Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_6)—Offset 434h See register

44000x00h 438h 43Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_7)—Offset 438h See register for xx value

43Ch 43Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_7)—Offset 43Ch See register

44000x00h 440h 443h Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_8)—Offset 440h See register for xx value

444h 447h Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_8)—Offset 444h See register

44000x00h 448h 44Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_9)—Offset 448h See register for xx value

44Ch 44Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_9)—Offset 44Ch See register

44000x00h 450h 453h Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_10)—Offset 450h See register for xx value

454h 457h Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_10)—Offset 454h See register

44000x00h 458h 45Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_11)—Offset 458h See register for xx value

45Ch 45Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_11)—Offset 45Ch See register

44000x00h 460h 463h Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_12)—Offset 460h See register for xx value

464h 467h Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_12)—Offset 464h See register

44000x00h 468h 46Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_13)—Offset 468h See register for xx value

46Ch 46Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_13)—Offset 46Ch See register

536 332219-002

GPIO for SKL PCH-LP

Table 7-1. Summary of GPIO Community 0 Registers (Continued)

Offset Offset Default Register Name (ID)—Offset Start End Value

44000x00h 470h 473h Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_14)—Offset 470h See register for xx value

474h 477h Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_14)—Offset 474h See register

44000x00h 478h 47Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_15)—Offset 478h See register for xx value

47Ch 47Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_15)—Offset 47Ch See register

44000x00h 480h 483h Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_16)—Offset 480h See register for xx value

484h 487h Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_16)—Offset 484h See register

44000x00h 488h 48Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_17)—Offset 488h See register for xx value

48Ch 48Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_17)—Offset 48Ch See register

44000x00h 490h 493h Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_18)—Offset 490h See register for xx value

494h 497h Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_18)—Offset 494h See register

44000x00h 498h 49Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_19)—Offset 498h See register for xx value

49Ch 49Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_19)—Offset 49Ch See register

44000x00h 4A0h 4A3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_20)—Offset 4A0h See register for xx value

4A4h 4A7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_20)—Offset 4A4h See register

44000x00h 4A8h 4ABh Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_21)—Offset 4A8h See register for xx value

4ACh 4AFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_21)—Offset 4ACh See register

44000x00h 4B0h 4B3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_22)—Offset 4B0h See register for xx value

4B4h 4B7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_22)—Offset 4B4h See register

44000x00h 4B8h 4BBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_23)—Offset 4B8h See register for xx value

4BCh 4BFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_23)—Offset 4BCh See register

44000x00h 4C0h 4C3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_0)—Offset 4C0h See register for xx value

4C4h 4C7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_0)—Offset 4C4h See register

44000x00h 4C8h 4CBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_1)—Offset 4C8h See register for xx value

4CCh 4CFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_1)—Offset 4CCh See register

44000x00h 4D0h 4D3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_2)—Offset 4D0h See register for xx value

332219-002 537 GPIO for SKL PCH-LP

Table 7-1. Summary of GPIO Community 0 Registers (Continued)

Offset Offset Default Register Name (ID)—Offset Start End Value

4D4h 4D7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_2)—Offset 4D4h See register

44000x00h 4D8h 4DBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_3)—Offset 4D8h See register for xx value

4DCh 4DFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_3)—Offset 4DCh See register

44000x00h 4E0h 4E3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_4)—Offset 4E0h See register for xx value

4E4h 4E7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_4)—Offset 4E4h See register

44000x00h 4E8h 4EBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_5)—Offset 4E8h See register for xx value

4ECh 4EFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_5)—Offset 4ECh See register

44000x00h 4F0h 4F3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_6)—Offset 4F0h See register for xx value

4F4h 4F7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_6)—Offset 4F4h See register

44000x00h 4F8h 4FBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_7)—Offset 4F8h See register for xx value

4FCh 4FFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_7)—Offset 4FCh See register

44000x00h 500h 503h Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_8)—Offset 500h See register for xx value

504h 507h Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_8)—Offset 504h See register

44000x00h 508h 50Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_9)—Offset 508h See register for xx value

50Ch 50Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_9)—Offset 50Ch See register

44000x00h 510h 513h Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_10)—Offset 510h See register for xx value

514h 517h Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_10)—Offset 514h See register

44000x00h 518h 51Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_11)—Offset 518h See register for xx value

51Ch 51Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_11)—Offset 51Ch See register

44000x00h 520h 523h Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_12)—Offset 520h See register for xx value

524h 527h Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_12)—Offset 524h See register

44000x00h 528h 52Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_13)—Offset 528h See register for xx value

52Ch 52Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_13)—Offset 52Ch See register

44000x00h 530h 533h Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_14)—Offset 530h See register for xx value

534h 537h Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_14)—Offset 534h See register

538 332219-002

GPIO for SKL PCH-LP

Table 7-1. Summary of GPIO Community 0 Registers (Continued)

Offset Offset Default Register Name (ID)—Offset Start End Value

44000x00h 538h 53Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_15)—Offset 538h See register for xx value

53Ch 53Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_15)—Offset 53Ch See register

44000x00h 540h 543h Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_16)—Offset 540h See register for xx value

544h 547h Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_16)—Offset 544h See register

44000x00h 548h 54Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_17)—Offset 548h See register for xx value

54Ch 54Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_17)—Offset 54Ch See register

44000x00h 550h 553h Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_18)—Offset 550h See register for xx value

554h 557h Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_18)—Offset 554h See register

44000x00h 558h 55Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_19)—Offset 558h See register for xx value

55Ch 55Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_19)—Offset 55Ch See register

44000x00h 560h 563h Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_20)—Offset 560h See register for xx value

564h 567h Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_20)—Offset 564h See register

44000x00h 568h 56Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_21)—Offset 568h See register for xx value

56Ch 56Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_21)—Offset 56Ch See register

44000x00h 570h 573h Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_22)—Offset 570h See register for xx value

574h 577h Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_22)—Offset 574h See register

44000x00h 578h 57Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_23)—Offset 578h See register for xx value

57Ch 57Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_23)—Offset 57Ch See register

7.1.1 Family Base Address (FAMBAR)—Offset 8h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 300h

332219-002 539 GPIO for SKL PCH-LP

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000001100000000 RSVD FAMBAR

Bit Default & Field Name (ID): Description Range Access

0h 31:16 Reserved. RO

Family Base Address (FAMBAR): This field provides the starting byte-align 300h address of Family0 register sets. It is meant for software to discover from where the 15:0 RO very first Family register (i.e. Family0 register) starts to compute the next Families address offsets.

7.1.2 Pad Base Address (PADBAR)—Offset Ch

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 400h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000010000000000 RSVD PADBAR

Bit Default & Field Name (ID): Description Range Access

0h 31:16 Reserved. RO

400h Pad Base Address (PADBAR): This field provides the starting byte-align address of 15:0 Pad0 register sets. It is meant for software to discover from where the very first Pad RO register (i.e. Pad0 register) starts to compute the next Pad address offsets.

7.1.3 Miscellaneous Configuration (MISCCFG)—Offset 10h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 43200h

540 332219-002

GPIO for SKL PCH-LP

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000001000011001000000000 RSVD RSVD RSVD GPDLCGEN GPDPCGEN GPE0_DW2 GPE0_DW1 GPE0_DW0 GPIO_DRIVER_IRQ_ROUTE

Bit Default & Field Name (ID): Description Range Access

0h 31:20 Reserved. RO

GPIO Group to GPE_DW0 assignment encoding (GPE0_DW2): This register assigns a specific GPIO Group to the ACPI GPE0[95:64]. The selected GPIO group will be mapped to lower bits of the GPE register 0h = GPP_A[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 4h 1h = GPP_B[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 19:16 2h = GPP_C[23:0] mapped to GPE[87:64]; GPE[95:88] not used. RW 3h = GPP_D[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 4h = GPP_E[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 5h = GPP_F[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 6h = GPP_G[7:0] mapped to GPE[51:64]; GPE[95:52] not used. 7h = GPD[11:0] mapped to GPE[75:64]; GPE[95:76] not used.

GPIO Group to GPE_DW0 assignment encoding (GPE0_DW1): This register assigns a specific GPIO Group to the ACPI GPE0[63:32]. The selected GPIO group will be mapped to lower bits of the GPE register 0h = GPP_A[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 3h 1h = GPP_B[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 15:12 2h = GPP_C[23:0] mapped to GPE[55:32]; GPE[63:56] not used. RW 3h = GPP_D[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 4h = GPP_E[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 5h = GPP_F[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 6h = GPP_G[7:0] mapped to GPE[39:32]; GPE[63:40] not used. 7h = GPD[11:0] mapped to GPE[43:32]; GPE[63:44] not used.

GPIO Group to GPE_DW0 assignment encoding (GPE0_DW0): This register assigns a specific GPIO Group to the ACPI GPE0[31:0]. The selected GPIO group will be mapped to lower bits of the GPE register 0h = GPP_A[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 2h 1h = GPP_B[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 11:8 2h = GPP_C[23:0] mapped to GPE[23:0]; GPE[31:24] not used. RW 3h = GPP_D[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 4h = GPP_E[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 5h = GPP_F[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 6h = GPP_G[7:0] mapped to GPE[7:0]; GPE[31:8] not used. 7h = GPD[11:0] mapped to GPE[11:0]; GPE[31:12] not used.

0h 7:4 Reserved. RO

GPIO Driver IRQ Route (GPIO_DRIVER_IRQ_ROUTE): Specifies the APIC IRQ 0h globally for all pads within the current community (GPI_IS with corresponding GPI_IE 3 enable). RW 0 = IRQ14 1 = IRQ15

332219-002 541 GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h 2 Reserved. RO

GPIO Dynamic Partition Clock Gating Enable (GPDPCGEN): Specifies whether 0h the GPIO Community should take part in partition clock gating 1 RW 0 = Disable participation in dynamic partition clock gating 1 = Enable participation in dynamic partition clock gating

GPIO Dynamic Local Clock Gating Enable (GPDLCGEN): Specifies whether the 0h 0 GPIO Community should perform local clock gating. RW 0 = Disable dynamic local clock gating 1 = Enable dynamic local clock gating

7.1.4 Pad Ownership (PAD_OWN_GPP_A_0)—Offset 20h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD PAD_OWN_GPP_A_7 PAD_OWN_GPP_A_6 PAD_OWN_GPP_A_5 PAD_OWN_GPP_A_4 PAD_OWN_GPP_A_3 PAD_OWN_GPP_A_2 PAD_OWN_GPP_A_1 PAD_OWN_GPP_A_0

Bit Default & Field Name (ID): Description Range Access

0h 31:30 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_A_7): Same description as bit 0, except that 29:28 RO the bit field applies to GPP_A7.

0h 27:26 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_A_6): Same description as bit 0, except that 25:24 RO the bit field applies to GPP_A6.

0h 23:22 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_A_5): Same description as bit 0, except that 21:20 RO the bit field applies to GPP_A5.

0h 19:18 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_A_4): Same description as bit 0, except that 17:16 RO the bit field applies to GPP_A4.

542 332219-002

GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h 15:14 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_A_3): Same description as bit 0, except that 13:12 RO the bit field applies to GPP_A3.

0h 11:10 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_A_2): Same description as bit 0, except that 9:8 RO the bit field applies to GPP_A2.

0h 7:6 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_A_1): Same description as bit 0, except that 5:4 RO the bit field applies to GPP_A1.

0h 3:2 Reserved. RO

Pad Ownership (PAD_OWN_GPP_A_0): 00 = Host GPIO ACPI Mode or GPIO Driver Mode. Host software (ACPI or GPIO Driver) has ownership of the pad. In Host GPIO Driver Mode (refer to HOSTSW_OWN), GPIO input event update is limited to 0h 1:0 GPI_STS update only. Otherwise in Host ACPI Mode, updates are limited to RO GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. 01 = ME GPIO Mode. ME has ownership of the pad. 10 = ISH GPIO Mode.ME has ownership of the pad 11 = Reserved

7.1.5 Pad Ownership (PAD_OWN_GPP_A_1)—Offset 24h

Same description as PAD_OWN_GPP_A_0, except that this register is for GPP_A[15:8]

7.1.6 Pad Ownership (PAD_OWN_GPP_A_2)—Offset 28h

Same description as PAD_OWN_GPP_A_0, except that this register is for GPP_A[23:16]

7.1.7 Pad Ownership (PAD_OWN_GPP_B_0)—Offset 30h

Same description as PAD_OWN_GPP_A_0, except that this register is for GPP_B[7:0]

7.1.8 Pad Ownership (PAD_OWN_GPP_B_1)—Offset 34h

Same description as PAD_OWN_GPP_A_0, except that this register is for GPP_B[15:8]

7.1.9 Pad Ownership (PAD_OWN_GPP_B_2)—Offset 38h

Same description as PAD_OWN_GPP_A_0, except that this register is for GPP_B[23:16]

7.1.10 Pad Configuration Lock (PADCFGLOCK_GPP_A)—Offset A0h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

332219-002 543 GPIO for SKL PCH-LP

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD PADCFGLOCK_GPP_A_9 PADCFGLOCK_GPP_A_8 PADCFGLOCK_GPP_A_7 PADCFGLOCK_GPP_A_6 PADCFGLOCK_GPP_A_5 PADCFGLOCK_GPP_A_4 PADCFGLOCK_GPP_A_3 PADCFGLOCK_GPP_A_2 PADCFGLOCK_GPP_A_1 PADCFGLOCK_GPP_A_0 PADCFGLOCK_GPP_A_23 PADCFGLOCK_GPP_A_22 PADCFGLOCK_GPP_A_21 PADCFGLOCK_GPP_A_20 PADCFGLOCK_GPP_A_19 PADCFGLOCK_GPP_A_18 PADCFGLOCK_GPP_A_17 PADCFGLOCK_GPP_A_16 PADCFGLOCK_GPP_A_15 PADCFGLOCK_GPP_A_14 PADCFGLOCK_GPP_A_13 PADCFGLOCK_GPP_A_12 PADCFGLOCK_GPP_A_11 PADCFGLOCK_GPP_A_10

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h Pad Config Lock (PADCFGLOCK_GPP_A_23): Applied to GPP_A23. Same 23 RW description as PADCFGLOCK_GPP_A_0

0h Pad Config Lock (PADCFGLOCK_GPP_A_22): Applied to GPP_A22. Same 22 RW description as PADCFGLOCK_GPP_A_0

0h Pad Config Lock (PADCFGLOCK_GPP_A_21): Applied to GPP_A21. Same 21 RW description as PADCFGLOCK_GPP_A_0

0h Pad Config Lock (PADCFGLOCK_GPP_A_20): Applied to GPP_A20. Same 20 RW description as PADCFGLOCK_GPP_A_0

0h Pad Config Lock (PADCFGLOCK_GPP_A_19): Applied to GPP_A19. Same 19 RW description as PADCFGLOCK_GPP_A_0

0h Pad Config Lock (PADCFGLOCK_GPP_A_18): Applied to GPP_A18. Same 18 RW description as PADCFGLOCK_GPP_A_0

0h Pad Config Lock (PADCFGLOCK_GPP_A_17): Applied to GPP_A17. Same 17 RW description as PADCFGLOCK_GPP_A_0

0h Pad Config Lock (PADCFGLOCK_GPP_A_16): Applied to GPP_A16. Same 16 RW description as PADCFGLOCK_GPP_A_0

0h Pad Config Lock (PADCFGLOCK_GPP_A_15): Applied to GPP_A15. Same 15 RW description as PADCFGLOCK_GPP_A_0

0h Pad Config Lock (PADCFGLOCK_GPP_A_14): Applied to GPP_A14. Same 14 RW description as PADCFGLOCK_GPP_A_0

0h Pad Config Lock (PADCFGLOCK_GPP_A_13): Applied to GPP_A13. Same 13 RW description as PADCFGLOCK_GPP_A_0

0h Pad Config Lock (PADCFGLOCK_GPP_A_12): Applied to GPP_A12. Same 12 RW description as PADCFGLOCK_GPP_A_0

0h Pad Config Lock (PADCFGLOCK_GPP_A_11): Applied to GPP_A11. Same 11 RW description as PADCFGLOCK_GPP_A_0

0h Pad Config Lock (PADCFGLOCK_GPP_A_10): Applied to GPP_A10. Same 10 RW description as PADCFGLOCK_GPP_A_0

0h Pad Config Lock (PADCFGLOCK_GPP_A_9): Applied to GPP_A9. Same 9 RW description as PADCFGLOCK_GPP_A_0

0h Pad Config Lock (PADCFGLOCK_GPP_A_8): Applied to GPP_A8. Same 8 RW description as PADCFGLOCK_GPP_A_0

544 332219-002

GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h Pad Config Lock (PADCFGLOCK_GPP_A_7): Applied to GPP_A7. Same 7 RW description as PADCFGLOCK_GPP_A_0

0h Pad Config Lock (PADCFGLOCK_GPP_A_6): Applied to GPP_A6. Same 6 RW description as PADCFGLOCK_GPP_A_0

0h Pad Config Lock (PADCFGLOCK_GPP_A_5): Applied to GPP_A5. Same 5 RW description as PADCFGLOCK_GPP_A_0

0h Pad Config Lock (PADCFGLOCK_GPP_A_4): Applied to GPP_A4. Same 4 RW description as PADCFGLOCK_GPP_A_0

0h Pad Config Lock (PADCFGLOCK_GPP_A_3): Applied to GPP_A3. Same 3 RW description as PADCFGLOCK_GPP_A_0

0h Pad Config Lock (PADCFGLOCK_GPP_A_2): Applied to GPP_A2. Same 2 RW description as PADCFGLOCK_GPP_A_0

0h Pad Config Lock (PADCFGLOCK_GPP_A_1): Applied to GPP_A1. Same 1 RW description as PADCFGLOCK_GPP_A_0

Pad Config Lock (PADCFGLOCK_GPP_A_0): Pad Configuration Lock locks specific register fields in the GPP specific registers from being configured. The registers affected become Read-Only and software writes to these registers have no effect. 0 = Unlock 1 = Lock the following register fields as read-only (RO): 0h - Pad Configuration registers (exclude GPIOTXState) 0 RW - GPI_NMI_EN Register (if implemented) - GPI_SMI_EN Register (if implemented) - GPI_GPE_EN Register (if implemented) When PadCfgLock is written from a '1' to a '0' (unlock), a synchronous SMI# is generated if enabled. This ensures that only SMM code can change the above GPIO registers after the lockdown.

7.1.11 Pad Configuration Lock (PADCFGLOCKTX_GPP_A)—Offset A4h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD PADCFGLOCKTX_GPP_A_9 PADCFGLOCKTX_GPP_A_8 PADCFGLOCKTX_GPP_A_7 PADCFGLOCKTX_GPP_A_6 PADCFGLOCKTX_GPP_A_5 PADCFGLOCKTX_GPP_A_4 PADCFGLOCKTX_GPP_A_3 PADCFGLOCKTX_GPP_A_2 PADCFGLOCKTX_GPP_A_1 PADCFGLOCKTX_GPP_A_0 PADCFGLOCKTX_GPP_A_23 PADCFGLOCKTX_GPP_A_22 PADCFGLOCKTX_GPP_A_21 PADCFGLOCKTX_GPP_A_20 PADCFGLOCKTX_GPP_A_19 PADCFGLOCKTX_GPP_A_18 PADCFGLOCKTX_GPP_A_17 PADCFGLOCKTX_GPP_A_16 PADCFGLOCKTX_GPP_A_15 PADCFGLOCKTX_GPP_A_14 PADCFGLOCKTX_GPP_A_13 PADCFGLOCKTX_GPP_A_12 PADCFGLOCKTX_GPP_A_11 PADCFGLOCKTX_GPP_A_10

332219-002 545 GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_23): Applied to GPP_A23. 23 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_22): Applied to GPP_A22. 22 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_21): Applied to GPP_A21. 21 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_20): Applied to GPP_A20. 20 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_19): Applied to GPP_A19. 19 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_18): Applied to GPP_A18. 18 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_17): Applied to GPP_A17. 17 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_16): Applied to GPP_A16. 16 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_15): Applied to GPP_A15. 15 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_14): Applied to GPP_A14. 14 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_13): Applied to GPP_A13. 13 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_12): Applied to GPP_A12. 12 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_11): Applied to GPP_A11. 11 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_10): Applied to GPP_A10. 10 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_9): Applied to GPP_A9. 9 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_8): Applied to GPP_A8. 8 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_7): Applied to GPP_A7. 7 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_6): Applied to GPP_A6. 6 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_5): Applied to GPP_A5. 5 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_4): Applied to GPP_A4. 4 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_3): Applied to GPP_A3. 3 RW Same description as PADCFGLOCKTX_GPP_A_0

546 332219-002

GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_2): Applied to GPP_A2. 2 RW Same description as PADCFGLOCKTX_GPP_A_0

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_1): Applied to GPP_A1. 1 RW Same description as PADCFGLOCKTX_GPP_A_0

Pad Config Lock TXState (PADCFGLOCKTX_GPP_A_0): PadCfgLockTx locks the GPIOTxState bit from being configured. The GPIOTxState register becomes Read- Only and software writes to the register have no effect. 0h 0 0 = Unlock RW 1 = Locks the Pad Configuration GPIOTXState field as read-only (RO) When PadCfgLockTx is written from a '1' to a '0' (unlock), a synchronous SMI# is generated if enabled. This ensures that only SMM code can change the above GPIO registers after the lockdown.

7.1.12 Pad Configuration Lock (PADCFGLOCK_GPP_B)—Offset A8h

Same description as PADCFGLOCK_GPP_A register, except this register applies to GPP_B[23:0].

7.1.13 Pad Configuration Lock (PADCFGLOCKTX_GPP_B)—Offset ACh

Same description as PADCFGLOCKTX_GPP_A register, except that this register applies to GPP_B[23:0].

7.1.14 Host Software Pad Ownership (HOSTSW_OWN_GPP_A)— Offset D0h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD HOSTSW_OWN_GPP_A_9 HOSTSW_OWN_GPP_A_8 HOSTSW_OWN_GPP_A_7 HOSTSW_OWN_GPP_A_6 HOSTSW_OWN_GPP_A_5 HOSTSW_OWN_GPP_A_4 HOSTSW_OWN_GPP_A_3 HOSTSW_OWN_GPP_A_2 HOSTSW_OWN_GPP_A_1 HOSTSW_OWN_GPP_A_0 HOSTSW_OWN_GPP_A_23 HOSTSW_OWN_GPP_A_22 HOSTSW_OWN_GPP_A_21 HOSTSW_OWN_GPP_A_20 HOSTSW_OWN_GPP_A_19 HOSTSW_OWN_GPP_A_18 HOSTSW_OWN_GPP_A_17 HOSTSW_OWN_GPP_A_16 HOSTSW_OWN_GPP_A_15 HOSTSW_OWN_GPP_A_14 HOSTSW_OWN_GPP_A_13 HOSTSW_OWN_GPP_A_12 HOSTSW_OWN_GPP_A_11 HOSTSW_OWN_GPP_A_10

332219-002 547 GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h HostSW_Own (HOSTSW_OWN_GPP_A_23): Applied to GPP_A23. Same 23 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_22): Applied to GPP_A22. Same 22 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_21): Applied to GPP_A21. Same 21 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_20): Applied to GPP_A20. Same 20 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_19): Applied to GPP_A19. Same 19 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_18): Applied to GPP_A18. Same 18 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_17): Applied to GPP_A17. Same 17 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_16): Applied to GPP_A16. Same 16 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_15): Applied to GPP_A15. Same 15 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_14): Applied to GPP_A14. Same 14 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_13): Applied to GPP_A13. Same 13 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_12): Applied to GPP_A12. Same 12 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_11): Applied to GPP_A11. Same 11 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_10): Applied to GPP_A10. Same 10 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_9): Applied to GPP_A9. Same description 9 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_8): Applied to GPP_A8. Same description 8 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_7): Applied to GPP_A7. Same description 7 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_6): Applied to GPP_A6. Same description 6 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_5): Applied to GPP_A5. Same description 5 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_4): Applied to GPP_A4. Same description 4 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_3): Applied to GPP_A3. Same description 3 RW as bit 0.

548 332219-002

GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h HostSW_Own (HOSTSW_OWN_GPP_A_2): Applied to GPP_A2. Same description 2 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_A_1): Applied to GPP_A1. Same description 1 RW as bit 0.

HostSW_Own (HOSTSW_OWN_GPP_A_0): This register determines the appropriate host status bit update when a pad is under host ownership. 0h 0 = ACPI Mode. GPIO input event updates are limited to GPI_GPE_STS, 0 RW GPI_NMI_STS and/or GPI_SMI_STS. GPI_STS update is masked. 1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked.

7.1.15 Host Software Pad Ownership (HOSTSW_OWN_GPP_B)— Offset D4h

Same description as HOSTSW_OWN_GPP_A register, except that this register applies to GPP_B[23:0].

7.1.16 GPI Interrupt Status (GPI_IS_GPP_A)—Offset 100h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_INT_STS_GPP_A_9 GPI_INT_STS_GPP_A_8 GPI_INT_STS_GPP_A_7 GPI_INT_STS_GPP_A_6 GPI_INT_STS_GPP_A_5 GPI_INT_STS_GPP_A_4 GPI_INT_STS_GPP_A_3 GPI_INT_STS_GPP_A_2 GPI_INT_STS_GPP_A_1 GPI_INT_STS_GPP_A_0 GPI_INT_STS_GPP_A_23 GPI_INT_STS_GPP_A_22 GPI_INT_STS_GPP_A_21 GPI_INT_STS_GPP_A_20 GPI_INT_STS_GPP_A_19 GPI_INT_STS_GPP_A_18 GPI_INT_STS_GPP_A_17 GPI_INT_STS_GPP_A_16 GPI_INT_STS_GPP_A_15 GPI_INT_STS_GPP_A_14 GPI_INT_STS_GPP_A_13 GPI_INT_STS_GPP_A_12 GPI_INT_STS_GPP_A_11 GPI_INT_STS_GPP_A_10

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_23): Applied to GPP_A23. Same 23 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_22): Applied to GPP_A22. Same 22 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_21): Applied to GPP_A21. Same 21 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_20): Applied to GPP_A20. Same 20 RW1C description as bit 0.

332219-002 549 GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_19): Applied to GPP_A19. Same 19 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_18): Applied to GPP_A18. Same 18 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_17): Applied to GPP_A17. Same 17 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_16): Applied to GPP_A16. Same 16 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_15): Applied to GPP_A15. Same 15 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_14): Applied to GPP_A14. Same 14 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_13): Applied to GPP_A13. Same 13 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_12): Applied to GPP_A12. Same 12 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_11): Applied to GPP_A11. Same 11 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_10): Applied to GPP_A10. Same 10 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_9): Applied to GPP_A9. Same 9 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_8): Applied to GPP_A8. Same 8 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_7): Applied to GPP_A7. Same 7 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_6): Applied to GPP_A6. Same 6 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_5): Applied to GPP_A5. Same 5 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_4): Applied to GPP_A4. Same 4 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_3): Applied to GPP_A3. Same 3 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_2): Applied to GPP_A2. Same 2 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_A_1): Applied to GPP_A1. Same 1 RW1C description as bit 0.

GPI Interrupt Status (GPI_INT_STS_GPP_A_0): GPI Interrupt Status (GPI_INT_STS) This bit is set to ‘1’ by hardware when either an edge or a level event is detected (See RxEdCfg RxInv) on pad and all the following conditions are true: 0h 0 - The corresponding pad is used in GPIO input mode RW1C - HOSTSW_OWN = 1 (i.e. Host GPIO Driver Mode). Writing a value of 1 will clear the bit while writing a value of 0 has no effect. 0 = No interrupt 1 = Interrupt asserts The state of GPI_INT_EN[x] does not prevent the setting of GPI_INT_STS[x].

550 332219-002

GPIO for SKL PCH-LP

7.1.17 GPI Interrupt Status (GPI_IS_GPP_B)—Offset 104h

Same description as GPI_IS_GPP_A register, except that this register applies to GPP_B[23:0].

7.1.18 GPI Interrupt Enable (GPI_IE_GPP_A)—Offset 120h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_INT_EN_GPP_A_9 GPI_INT_EN_GPP_A_8 GPI_INT_EN_GPP_A_7 GPI_INT_EN_GPP_A_6 GPI_INT_EN_GPP_A_5 GPI_INT_EN_GPP_A_4 GPI_INT_EN_GPP_A_3 GPI_INT_EN_GPP_A_2 GPI_INT_EN_GPP_A_1 GPI_INT_EN_GPP_A_0 GPI_INT_EN_GPP_A_23 GPI_INT_EN_GPP_A_22 GPI_INT_EN_GPP_A_21 GPI_INT_EN_GPP_A_20 GPI_INT_EN_GPP_A_19 GPI_INT_EN_GPP_A_18 GPI_INT_EN_GPP_A_17 GPI_INT_EN_GPP_A_16 GPI_INT_EN_GPP_A_15 GPI_INT_EN_GPP_A_14 GPI_INT_EN_GPP_A_13 GPI_INT_EN_GPP_A_12 GPI_INT_EN_GPP_A_11 GPI_INT_EN_GPP_A_10

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_23): Applied to GPP_A23. Same 23 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_22): Applied to GPP_A22. Same 22 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_21): Applied to GPP_A21. Same 21 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_20): Applied to GPP_A20. Same 20 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_19): Applied to GPP_A19. Same 19 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_18): Applied to GPP_A18. Same 18 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_17): Applied to GPP_A17. Same 17 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_16): Applied to GPP_A16. Same 16 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_15): Applied to GPP_A15. Same 15 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_14): Applied to GPP_A14. Same 14 RW description as bit 0.

332219-002 551 GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_13): Applied to GPP_A13. Same 13 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_12): Applied to GPP_A12. Same 12 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_11): Applied to GPP_A11. Same 11 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_10): Applied to GPP_A10. Same 10 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_9): Applied to GPP_A9. Same 9 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_8): Applied to GPP_A8. Same 8 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_7): Applied to GPP_A7. Same 7 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_6): Applied to GPP_A6. Same 6 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_5): Applied to GPP_A5. Same 5 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_4): Applied to GPP_A3. Same 4 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_3): Applied to GPP_A3. Same 3 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_2): Applied to GPP_A2. Same 2 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_A_1): Applied to GPP_A1. Same 1 RW description as bit 0.

GPI Interrupt Enable (GPI_INT_EN_GPP_A_0): This bit is used to enable/ 0h disable the generation of APIC interrupt when the corresponding GPI_INT_STS bit is 0 set. RW 0 = disable interrupt generation 1 = enable interrupt generation

7.1.19 GPI Interrupt Enable (GPI_IE_GPP_B)—Offset 124h

Same description as GPI_IE_GPP_A register, except that this register is for GPP_B[23:0].

7.1.20 GPI General Purpose Events Status (GPI_GPE_STS_GPP_A)—Offset 140h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

552 332219-002

GPIO for SKL PCH-LP

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_GPE_STS_GPP_A_9 GPI_GPE_STS_GPP_A_8 GPI_GPE_STS_GPP_A_7 GPI_GPE_STS_GPP_A_6 GPI_GPE_STS_GPP_A_5 GPI_GPE_STS_GPP_A_4 GPI_GPE_STS_GPP_A_3 GPI_GPE_STS_GPP_A_2 GPI_GPE_STS_GPP_A_1 GPI_GPE_STS_GPP_A_0 GPI_GPE_STS_GPP_A_23 GPI_GPE_STS_GPP_A_22 GPI_GPE_STS_GPP_A_21 GPI_GPE_STS_GPP_A_20 GPI_GPE_STS_GPP_A_19 GPI_GPE_STS_GPP_A_18 GPI_GPE_STS_GPP_A_17 GPI_GPE_STS_GPP_A_16 GPI_GPE_STS_GPP_A_15 GPI_GPE_STS_GPP_A_14 GPI_GPE_STS_GPP_A_13 GPI_GPE_STS_GPP_A_12 GPI_GPE_STS_GPP_A_11 GPI_GPE_STS_GPP_A_10

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_23): Applied to 23 RW1C GPP_A23. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_22): Applied to 22 RW1C GPP_A22. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_21): Applied to 21 RW1C GPP_A21. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_20): Applied to 20 RW1C GPP_A20. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_19): Applied to 19 RW1C GPP_A19. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_18): Applied to 18 RW1C GPP_A18. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_17): Applied to 17 RW1C GPP_A17. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_16): Applied to 16 RW1C GPP_A16. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_15): Applied to 15 RW1C GPP_A15. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_14): Applied to 14 RW1C GPP_A14. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_13): Applied to 13 RW1C GPP_A13. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_12): Applied to 12 RW1C GPP_A12. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_11): Applied to 11 RW1C GPP_A11. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_10): Applied to 10 RW1C GPP_A10. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_9): Applied to 9 RW1C GPP_A9. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_8): Applied to 8 RW1C GPP_A8. Same description as bit 0.

332219-002 553 GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_7): Applied to 7 RW1C GPP_A7. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_6): Applied to 6 RW1C GPP_A6. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_5): Applied to 5 RW1C GPP_A5. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_4): Applied to 4 RW1C GPP_A4. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_3): Applied to 3 RW1C GPP_A3. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_2): Applied to 2 RW1C GPP_A2. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_1): Applied to 1 RW1C GPP_A1. Same description as bit 0.

GPI General Purpose Events Status (GPI_GPE_STS_GPP_A_0): These bits are set any time the corresponding GPIO pad is set up as an input, under host ownership and the corresponding GPIO signal is high(or low if the corresponding RXINV bit is set). 0h If the corresponding enable bit is set in the GPI_GPE_EN register, then when the 0 GPI_GPE_STS bit is set: RW1C - If the system is in an S3-S5 state, the event will also wake the system. - If the system is in an S0 state (or upon waking back to an S0 state), an SCI will be caused, depending on the GPIRoutSCI bit for the corresponding pad. These bits are sticky bits and are cleared by writing a 1 back to this bit position. The state of GPI_GPE_EN does not prevent the setting of GPI_GPE_STS.

7.1.21 GPI General Purpose Events Status (GPI_GPE_STS_GPP_B)—Offset 144h

Same description as PI_GPE_STS_GPP_A register, except that this is for GPP_B[23:0].

7.1.22 GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A)—Offset 160h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_GPE_EN_GPP_A_9 GPI_GPE_EN_GPP_A_8 GPI_GPE_EN_GPP_A_7 GPI_GPE_EN_GPP_A_6 GPI_GPE_EN_GPP_A_5 GPI_GPE_EN_GPP_A_4 GPI_GPE_EN_GPP_A_3 GPI_GPE_EN_GPP_A_2 GPI_GPE_EN_GPP_A_1 GPI_GPE_EN_GPP_A_0 GPI_GPE_EN_GPP_A_23 GPI_GPE_EN_GPP_A_22 GPI_GPE_EN_GPP_A_21 GPI_GPE_EN_GPP_A_20 GPI_GPE_EN_GPP_A_19 GPI_GPE_EN_GPP_A_18 GPI_GPE_EN_GPP_A_17 GPI_GPE_EN_GPP_A_16 GPI_GPE_EN_GPP_A_15 GPI_GPE_EN_GPP_A_14 GPI_GPE_EN_GPP_A_13 GPI_GPE_EN_GPP_A_12 GPI_GPE_EN_GPP_A_11 GPI_GPE_EN_GPP_A_10

554 332219-002

GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_23): Applied to 23 RW GPP_A23. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_22): Applied to 22 RW GPP_A22. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_21): Applied to 21 RW GPP_A21. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_20): Applied to 20 RW GPP_A20. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_19): Applied to 19 RW GPP_A19. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_18): Applied to 18 RW GPP_A18. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_17): Applied to 17 RW GPP_A17. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_16): Applied to 16 RW GPP_A16. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_15): Applied to 15 RW GPP_A15. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_14): Applied to 14 RW GPP_A14. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_13): Applied to 13 RW GPP_A13. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_12): Applied to 12 RW GPP_A12. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_11): Applied to 11 RW GPP_A11. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_10): Applied to 10 RW GPP_A10. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_9): Applied to 9 RW GPP_A9. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_8): Applied to 8 RW GPP_A8. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_7): Applied to 7 RW GPP_A7. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_6): Applied to 6 RW GPP_A6. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_5): Applied to 5 RW GPP_A5. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_4): Applied to 4 RW GPP_A4. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_3): Applied to 3 RW GPP_A3. Same description as bit 0.

332219-002 555 GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_2): Applied to 2 RW GPP_A2. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_1): Applied to 1 RW GPP_A1. Same description as bit 0.

GPI General Purpose Events Enable (GPI_GPE_EN_GPP_A_0): This bit is used to enable/disable the generation of GPE to cause SCI and/or wake when the

0h corresponding GPI_GPE_STS bit is set. 0 0 = disable GPE generation RW 1 = enable GPE generation Note: The pad must also be routed for GPE functionality in order for GPE to be generated, i.e. the corresponding GPIRoutSCI must be set to ‘1’.

7.1.23 GPI General Purpose Events Enable (GPI_GPE_EN_GPP_B)—Offset 164h

Same description as PI_GPI_GPE_EN_GPP_A register, except that this is for GPP_B[23:0].

7.1.24 SMI Status (GPI_SMI_STS_GPP_B)—Offset 184h

Register bits in this register are implemented for GPP_B signals that have SMI capability only. Other bits are reserved and RO.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD RSVD RSVD GPI_SMI_STS_GPP_B_23 GPI_SMI_STS_GPP_B_20 GPI_SMI_STS_GPP_B_14

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h GPI SMI Status (GPI_SMI_STS_GPP_B_23): Same description as bit 14. 23 RW1C

0h 22:21 Reserved. RO

556 332219-002

GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h GPI SMI Status (GPI_SMI_STS_GPP_B_20): Same description as bit 14. 20 RW1C

0h 19:15 Reserved. RO

GPI SMI Status (GPI_SMI_STS_GPP_B_14): This bit is set to 1 by hardware when a level event (See RxEdCfg,RxInv) is detected, and all the following conditions are true: - The corresponding pad is used in GPIO input mode - The corresponding PAD_OWN[2:0] is ‘000’ (i.e. ACPI GPIO Mode). If the following conditions are true, then an SMI will be generated if the 0h GPI_SMI_STS bit is set: 14 RW1C 1. The corresponding bit in the GPI_SMI_EN register is set 2. The corresponding pad’s GPIROUTSMI is set Writing a value of 1 will clear the bit while writing a value of 0 has no effect. 0 = There is no SMI event 1 = There is an SMI event The state of GPI_SMI_EN does not prevent the setting of GPI_SMI_STS. Defaults for these bits are dependent on the state of the GPI pads.

0h 13:0 Reserved. RO

7.1.25 SMI Enable (GPI_SMI_EN_GPP_B)—Offset 1A4h

Register bits in this register are implemented for GPP_B signals that have SMI capability only. Other bits are reserved and RO.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD RSVD RSVD GPI_SMI_EN_GPP_B_23 GPI_SMI_EN_GPP_B_20 GPI_SMI_EN_GPP_B_14

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h GPI SMI Enable (GPI_SMI_EN_GPP_B_23): Same description as bit 14. 23 RW

0h 22:21 Reserved. RO

332219-002 557 GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h GPI SMI Enable (GPI_SMI_EN_GPP_B_20): Same description as bit 14. 20 RW

0h 19:15 Reserved. RO

GPI SMI Enable (GPI_SMI_EN_GPP_B_14): This bit is used to enable/disable the generation of SMI when the corresponding GPI_SMI_STS bit is set. The pad must also be routed for SMI functionality in order for SMI to be generated, i.e. the 0h corresponding GPIROUTSMI must be set to 1. 14 0 = disable SMI generation RW 1 = enable SMI generation Note: Each of the bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. E.g. if the PadCfgLock of pad0 is 1, bit0 of this bit is locked down to read-only.

0h 13:0 Reserved. RO

7.1.26 NMI Status (GPI_NMI_STS_GPP_B)—Offset 1C4h

Register bits in this register are implemented for GPP_B signals that have NMI capability only. Other bits are reserved and RO.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD RSVD RSVD GPI_NMI_STS_GPP_B_23 GPI_NMI_STS_GPP_B_20 GPI_NMI_STS_GPP_B_14

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h GPI NMI Status (GPI_NMI_STS_GPP_B_23): Same description as bit 14. 23 RW1C

0h 22:21 Reserved. RO

0h GPI NMI Status (GPI_NMI_STS_GPP_B_20): Same description as bit 14. 20 RW1C

558 332219-002

GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h 19:15 Reserved. RO

GPI NMI Status (GPI_NMI_STS_GPP_B_14): This bit is set to 1 by hardware when an edge event is detected (See RxEdCfg, RxInv) on pad and all the following conditions are true: - The corresponding pad is used in GPIO input mode (PMode) 0h - The corresponding GPIONMIRout is set to 1, i.e. programmed to route as NMI 14 RW1C - The corresponding GPIOOwn[2:0] is ‘000’ (i.e. ACPI GPIO Mode). - The corresponding GPI_NMI_EN is set Writing a value of 1 will clear the bit while writing a value of 0 has no effect. 0 = There is no NMI event 1 = There is an NMI event

0h 13:0 Reserved. RO

7.1.27 NMI Enable (GPI_NMI_EN_GPP_B)—Offset 1E4h

Register bits in this register are implemented for GPP_B signals that have NMI capability only. Other bits are reserved and RO.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD RSVD RSVD GPI_NMI_EN_GPP_B_23 GPI_NMI_EN_GPP_B_20 GPI_NMI_EN_GPP_B_14

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h GPI NMI Enable (GPI_NMI_EN_GPP_B_23): Same description as bit 14. 23 RW

0h 22:21 Reserved. RO

0h GPI NMI Enable (GPI_NMI_EN_GPP_B_20): Same description as bit 14. 20 RW

332219-002 559 GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h 19:15 Reserved. RO

GPI NMI Enable (GPI_NMI_EN_GPP_B_14): This bit is used to enable/disable the generation of NMI when the corresponding GPI_NMI_STS bit is set and its GPIROUTNMI is set. 0h 14 0 = disable NMI generation RW 1 = enable NMI generation Each bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. E.g. if the PadCfgLock of pad0 is ‘1’, bit0 of this bit is locked down to read-only.

0h 13:0 Reserved. RO

7.1.28 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_0)— Offset 400h

This register applies to GPP_A0.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 44000x00h

3 2 2 2 1 1 840 1 8 4 0 6 2

01000100000000000000001100000000 RSVD RSVD RSVD RSVD RSVD RXINV PMODE1 PMODE0 RXRAW1 RXEVCFG GPIOTXDIS GPIORXDIS PADRSTCFG GPIROUTSCI GPIROUTSMI RXPADSTSEL GPIROUTNMI GPIOTXSTATE GPIORXSTATE GPIROUTIOXAPIC

Bit Default & Field Name (ID): Description Range Access

Pad Reset Config (PADRSTCFG): This register controls which reset is used to reset GPIO pad register fields in PAD_CFG_DW0 and PAD_CFG_DW1 registers. This register can be used for Sx isolation of the associated signal if needed. 1h 00 = RSMRST# 31:30 01 = Host deep reset. This reset occurs when a host reset (with or without power RW cycle) is initiated or a global reset is initiated, except that the reset does not assert when in S3/S4/S5. 10 = PLTRST# 11 = Reserved

RX Pad State Select (RXPADSTSEL): Determines from which node the RX pad state for native function should be taken from. This field only affects the pad state 0h value being fanned out to native function(s) and is not meaningful if the pad is in 29 RW GPIO mode (i.e. Pad Mode = 0). 0 = Raw RX pad state directly from RX buffer 1 = Internal RX pad state (subject to RXINV and PreGfRXSel settings)

RX Raw Override to '1' (RXRAW1): This bit determines if the selected pad state is being overridden to '1'. This field is only applicable when the RX buffer is configured 0h as an input in either GPIO Mode or native function mode. The override takes place at 28 RW the internal pad state directly from buffer and before the RXINV. 0 = No Override 1 = RX drive 1 internally

560 332219-002

GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h 27 Reserved. RO

RX Level/Edge Configuration (RXEVCFG): Determines if the internal RX pad state (synchronized, filtered vs non-filtered version as determined by PreGfRXSel, and is further subject to RXInv) should be passed on to the next logic stage as is, as a pulse, or level signal. This field does not affect the received pad state (to 2h GPIORXState or native functions) but how the interrupt or wake triggering events 26:25 RW should be delivered to the GPIO Community Controller . 0h = Level 1h = Edge 2h = Drive '0' 3h = Reserved (implement as setting 0h)

0h 24 Reserved. RO

RX Invert (RXINV): This bit determines if the selected pad state should go through the polarity inversion stage. This field is only applicable when the RX buffer is configured as an input in either GPIO Mode or native function mode. The polarity inversion takes place at the mux node of raw vs filtered or non-filtered RX pad state, 0h as determined by PreGfRXsel and RXPadStSel This bit does not affect GPIORXState. 23 During host ownership GPIO Mode, when this bit is set to '1', then the RX pad state is RW inverted as it is sent to the GPIO-to-IOxAPIC, GPE/SCI, SMI, NMI logic or GPI_IS[n] that is using it. This is used to allow active-low and active-high inputs to cause IRQ, SMI#, SCI or NMI. 0 = No inversion 1 = Inversion

0h 22:21 Reserved. RO

GPIO Input Route IOxAPIC (GPIROUTIOXAPIC): Determines if the pad can be routed to cause peripheral IRQ when configured in GPIO input mode. If the pad is not 0h configured in GPIO input mode, this field has no effect. 20 0 = Routing does not cause peripheral IRQ RW 1 = Routing can cause peripheral IRQ Note: This bit does not affect any interrupt status bit within GPIO, but is used as the last qualifier for the peripheral IRQ indication to the intended recipient(s).

GPIO Input Route SCI (GPIROUTSCI): Determines if the pad can be routed to cause SCI when configured in GPIO input mode. If the pad is not configured in GPIO 0h input mode, this field has no effect. 19 0 = Routing does not cause SCI. RW 1 = Routing can cause SCI Note: This bit does not affect any interrupt status bit within GPIO, but is used as the last qualifier for the GPE indication to the intended recipient(s).

GPIO Input Route SMI (GPIROUTSMI): Determines if the pad can be routed to cause SMI when configured in GPIO input mode. If the pad is not configured in GPIO input mode, this field has no effect. 0h 0 = Routing does not cause SMI. 18 RW 1 = Routing can cause SMI. Note: This bit does not affect any interrupt status bit within GPIO, but is used as the last qualifier for the SMI indication to the intended recipient(s). This bit only applies to a GPIO that has SMI capability. Otherwise, the bit is RO.

GPIO Input Route NMI (GPIROUTNMI): Determines if the pad can be routed to cause NMI when configured in GPIO input mode. If the pad is not configured in GPIO input mode, this field has no effect. 0 = Routing does not cause NMI. 0h 17 1 = Routing can cause NMI. RW Note: This bit also affects GPI_NMI_STS. If '0', GPI_NMI_STS is always clear. If '1', GPI_NMI_STS could be set (depending on GPIOOwn setting) when there is an event. Whether a NMI indication is generated and sent to the intended recipient(s) is also depending on the corresponding GPI_NMI_EN bit. This bit only applies to a GPIO that has NMI capability. Otherwise, the bit is RO.

0h 16:12 Reserved. RO

-- Pad Mode bit 1 (PMODE1): See Pad Mode Bit 0 description. 11 RW

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Bit Default & Field Name (ID): Description Range Access

Pad Mode bit 0 (PMODE0): This bit is used in conjunction with Pad Mode bit 1. This two-bit field determines whether the Pad is controlled by GPIO controller logic or one of the native functions muxed onto the Pad. 0h = GPIO control the Pad. 1h = native function 1, if applicable, controls the Pad -- 2h = native function 2, if applicable, controls the Pad. Also used to enable the GPIO 10 RW blink (PWM) capability if applicable (note that not all GPIOs have the blink capability) 3h = native function 3, if applicable, controls the Pad Dedicated (unmuxed) GPIO shall report RO of all 0’s in this register field If GPIO vs. native mode is configured via soft strap, this bit has no effect.

Default value is determined by the default functionality of the pad.

GPIO RX Disable (GPIORXDIS): 0 = Enable the input buffer (active low enable) of

1h the pad. 9 1 = Disable the input buffer of the pad. RW Notes: When the input buffer is disabled, the internal pad state is always driven to '0'.

1h GPIO TX Disable (GPIOTXDIS): 0 = Enable the output buffer (active low enable) 8 of the pad. RW 1 = Disable the output buffer of the pad; i.e. Hi-Z

0h 7:2 Reserved. RO

0h GPIO RX State (GPIORXSTATE): This is the current internal RX pad state after 1 RO Glitch Filter logic stage and is not affected by PMode and RXINV settings.

0h GPIO TX State (GPIOTXSTATE): 0 = Drive a level '0' to the TX output pad. 0 RW 1 = Drive a level '1' to the TX output pad

7.1.29 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_0)— Offset 404h

This register applies to GPP_A0.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 18h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000011000 TERM RSVD RSVD INTSEL

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Bit Default & Field Name (ID): Description Range Access

0h 31:14 Reserved. RO

Termination (TERM): The Pad Termination state defines the different weak pull-up and pull-down settings that are supported by the buffer. The settings for [13:10] correspond to: 0000: none 0010: 5k pd 0100: 20k pd 1000: none 1001: 1k pu 1011: 2k pu

0h 1010: 5k pu 13:10 1100: 20k pu RW 1101: 1k & 2k pu (in parallel) 1111: Native controller selected by Pad Mode controls the Termination All others reserved. If a reserved value is programmed, pad may malfunction. The setting of this field is applicable in all Pad Mode including GPIO. As each Pad Mode may require different termination and isolation, care must be taken in sw/fw in the transition with appropriate register programming. The actual transition sequence requirement may vary on case by case basis depending on the native functions involved. For example, before changing the pad from output to input direction, pu/pd settings should be programmed first to ensure the input does not float momentarily.

0h 9:8 Reserved. RO

Interrupt Select (INTSEL): The Interrupt Select defines which interrupt line driven from the GPIO Controller toggles when an interrupt is detected on this pad. 18h 0 = Interrupt Line 0 7:0 RO 1 = Interrupt Line 1 .... Up to the max IOxAPIC IRQ supported

7.1.30 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_1)— Offset 408h

This register applies to GPP_A1 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.31 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_1)— Offset 40Ch

This register applies to GPP_A1 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 19h

7.1.32 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_2)— Offset 410h

This register applies to GPP_A2 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.33 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_2)— Offset 414h

This register applies to GPP_A2 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 1Ah

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7.1.34 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_3)— Offset 418h

This register applies to GPP_A3 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.35 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_3)— Offset 41Ch

This register applies to GPP_A3 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 1Bh

7.1.36 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_4)— Offset 420h

This register applies to GPP_A4 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.37 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_4)— Offset 424h

This register applies to GPP_A4 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 1Ch

7.1.38 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_5)— Offset 428h

This register applies to GPP_A5 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.39 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_5)— Offset 42Ch

This register applies to GPP_A5 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 1Dh

7.1.40 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_6)— Offset 430h

This register applies to GPP_A6 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.41 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_6)— Offset 434h

This register applies to GPP_A6 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 1Eh

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7.1.42 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_7)— Offset 438h

This register applies to GPP_A7 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.43 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_7)— Offset 43Ch

This register applies to GPP_A7 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 1Fh

7.1.44 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_8)— Offset 440h

This register applies to GPP_A8 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.45 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_8)— Offset 444h

This register applies to GPP_A8 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 20h

7.1.46 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_9)— Offset 448h

This register applies to GPP_A9 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.47 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_9)— Offset 44Ch

This register applies to GPP_A9 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 21h

7.1.48 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_10)— Offset 450h

This register applies to GPP_A10 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.49 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_10)— Offset 454h

This register applies to GPP_A10 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 22h

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7.1.50 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_11)— Offset 458h

This register applies to GPP_A11 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.51 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_11)— Offset 45Ch

This register applies to GPP_A11 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 26h

7.1.52 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_12)— Offset 460h

This register applies to GPP_A12 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.53 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_12)— Offset 464h

This register applies to GPP_A12 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 23h

7.1.54 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_13)— Offset 468h

This register applies to GPP_A13 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.55 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_13)— Offset 46Ch

This register applies to GPP_A13 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 24h

7.1.56 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_14)— Offset 470h

This register applies to GPP_A14 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.57 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_14)— Offset 474h

This register applies to GPP_A14 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 25h

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7.1.58 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_15)— Offset 478h

This register applies to GPP_A15 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.59 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_15)— Offset 47Ch

This register applies to GPP_A15 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 27h

7.1.60 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_16)— Offset 480h

This register applies to GPP_A16 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.61 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_16)— Offset 484h

This register applies to GPP_A16 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 28h

7.1.62 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_17)— Offset 488h

This register applies to GPP_A17 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.63 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_17)— Offset 48Ch

This register applies to GPP_A17 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 29h

7.1.64 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_18)— Offset 490h

This register applies to GPP_A18 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.65 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_18)— Offset 494h

This register applies to GPP_A18 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 2Ah

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7.1.66 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_19)— Offset 498h

This register applies to GPP_A19 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.67 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_19)— Offset 49Ch

This register applies to GPP_A19 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 2Bh

7.1.68 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_20)— Offset 4A0h

This register applies to GPP_A20 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.69 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_20)— Offset 4A4h

This register applies to GPP_A20 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 2Ch

7.1.70 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_21)— Offset 4A8h

This register applies to GPP_A21 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.71 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_21)— Offset 4ACh

This register applies to GPP_A21 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 2Dh

7.1.72 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_22)— Offset 4B0h

This register applies to GPP_A22 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.73 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_22)— Offset 4B4h

This register applies to GPP_A22 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 2Eh

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7.1.74 Pad Configuration DW0 (PAD_CFG_DW0_GPP_A_23)— Offset 4B8h

This register applies to GPP_A23 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.75 Pad Configuration DW1 (PAD_CFG_DW1_GPP_A_23)— Offset 4BCh

This register applies to GPP_A23 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 2Fh

7.1.76 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_0)— Offset 4C0h

This register applies to GPP_B0 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.77 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_0)— Offset 4C4h

This register applies to GPP_B0 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 8'h30

7.1.78 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_1)— Offset 4C8h

This register applies to GPP_B1 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.79 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_1)— Offset 4CCh

This register applies to GPP_B1 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 31h

7.1.80 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_2)— Offset 4D0h

This register applies to GPP_B2 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.81 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_2)— Offset 4D4h

This register applies to GPP_B2 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 32h

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7.1.82 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_3)— Offset 4D8h

This register applies to GPP_B3 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.83 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_3)— Offset 4DCh

This register applies to GPP_B3 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 33h

7.1.84 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_4)— Offset 4E0h

This register applies to GPP_B4 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.85 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_4)— Offset 4E4h

This register applies to GPP_B4 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 34h

7.1.86 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_5)— Offset 4E8h

This register applies to GPP_B5 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.87 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_5)— Offset 4ECh

This register applies to GPP_B5 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 35h

7.1.88 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_6)— Offset 4F0h

This register applies to GPP_B6 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.89 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_6)— Offset 4F4h

This register applies to GPP_B6 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 36h

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7.1.90 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_7)— Offset 4F8h

This register applies to GPP_B7 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.91 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_7)— Offset 4FCh

This register applies to GPP_B7 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 37h

7.1.92 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_8)— Offset 500h

This register applies to GPP_B8 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.93 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_8)— Offset 504h

This register applies to GPP_B8 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 38h

7.1.94 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_9)— Offset 508h

This register applies to GPP_B9 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.95 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_9)— Offset 50Ch

This register applies to GPP_B9 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 39h

7.1.96 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_10)— Offset 510h

This register applies to GPP_B10 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.97 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_10)— Offset 514h

This register applies to GPP_B10 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 3Ah

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7.1.98 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_11)— Offset 518h

This register applies to GPP_B11 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.99 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_11)— Offset 51Ch

This register applies to GPP_B11 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 3Bh

7.1.100 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_12)— Offset 520h

This register applies to GPP_B12 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.101 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_12)— Offset 524h

This register applies to GPP_B12 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 3Ch

7.1.102 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_13)— Offset 528h

This register applies to GPP_B13 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.103 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_13)— Offset 52Ch

This register applies to GPP_B13 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 3Dh

7.1.104 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_14)— Offset 530h

This register applies to GPP_B14 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.105 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_14)— Offset 534h

This register applies to GPP_B14 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 3Eh

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7.1.106 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_15)— Offset 538h

This register applies to GPP_B15 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.107 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_15)— Offset 53Ch

This register applies to GPP_B15 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 3Fh

7.1.108 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_16)— Offset 540h

This register applies to GPP_B16 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.109 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_16)— Offset 544h

This register applies to GPP_B16 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 40h

7.1.110 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_17)— Offset 548h

This register applies to GPP_B17 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.111 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_17)— Offset 54Ch

This register applies to GPP_B17 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 41h

7.1.112 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_18)— Offset 550h

This register applies to GPP_B18 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.113 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_18)— Offset 554h

This register applies to GPP_B18 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 42h

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7.1.114 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_19)— Offset 558h

This register applies to GPP_B19 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.115 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_19)— Offset 55Ch

This register applies to GPP_B19 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 43h

7.1.116 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_20)— Offset 560h

This register applies to GPP_B20 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.117 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_20)— Offset 564h

This register applies to GPP_B20 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 44h

7.1.118 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_21)— Offset 568h

This register applies to GPP_B21 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.119 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_21)— Offset 56Ch

This register applies to GPP_B21 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 45h

7.1.120 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_22)— Offset 570h

This register applies to GPP_B22 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.121 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_22)— Offset 574h

This register applies to GPP_B22 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 46h

574 332219-002

GPIO for SKL PCH-LP

7.1.122 Pad Configuration DW0 (PAD_CFG_DW0_GPP_B_23)— Offset 578h

This register applies to GPP_B23 and has the same description as PAD_CFG_DW0_GPP_A_0.

7.1.123 Pad Configuration DW1 (PAD_CFG_DW1_GPP_B_23)— Offset 57Ch

This register applies to GPP_B23 and has the same description as PAD_CFG_DW1_GPP_A_0. Exception: The default value of the INTSEL bit field in this register is : 47h

7.2 GPIO Community 1 Registers Summary

Community 1 Registers are for GPP_C and GPP_D, and GPP_E groups.

Table 7-2. Summary of GPIO Community 1 Registers

Offset Offset Default Register Name (ID)—Offset Start End Value

8h Bh Family Base Address (FAMBAR)—Offset 8h 300h

Ch Fh Pad Base Address (PADBAR)—Offset Ch 400h

10h 13h Miscellaneous Configuration (MISCCFG)—Offset 10h 43200h

20h 23h Pad Ownership (PAD_OWN_GPP_C_0)—Offset 20h 0h

24h 27h Pad Ownership (PAD_OWN_GPP_C_1)—Offset 24h 0h

28h 2Bh Pad Ownership (PAD_OWN_GPP_C_2)—Offset 28h 0h

30h 33h Pad Ownership (PAD_OWN_GPP_D_0)—Offset 30h 0h

34h 37h Pad Ownership (PAD_OWN_GPP_D_1)—Offset 34h 0h

38h 3Bh Pad Ownership (PAD_OWN_GPP_D_2)—Offset 38h 0h

40h 43h Pad Ownership (PAD_OWN_GPP_E_0)—Offset 40h 0h

44h 47h Pad Ownership (PAD_OWN_GPP_E_1)—Offset 44h 0h

48h 4Bh Pad Ownership (PAD_OWN_GPP_E_2)—Offset 48h 0h

A0h A3h Pad Configuration Lock (PADCFGLOCK_GPP_C)—Offset A0h 0h

A4h A7h Pad Configuration Lock (PADCFGLOCKTX_GPP_C)—Offset A4h 0h

A8h ABh Pad Configuration Lock (PADCFGLOCK_GPP_D)—Offset A8h 0h

ACh AFh Pad Configuration Lock (PADCFGLOCKTX_GPP_D)—Offset ACh 0h

B0h B3h Pad Configuration Lock (PADCFGLOCK_GPP_E)—Offset B0h 0h

B4h B7h Pad Configuration Lock (PADCFGLOCKTX_GPP_E)—Offset B4h 0h

D0h D3h Host Software Pad Ownership (HOSTSW_OWN_GPP_C)—Offset D0h 0h

D4h D7h Host Software Pad Ownership (HOSTSW_OWN_GPP_D)—Offset D4h 0h

D8h DBh Host Software Pad Ownership (HOSTSW_OWN_GPP_E)—Offset D8h 0h

100h 103h GPI Interrupt Status (GPI_IS_GPP_C)—Offset 100h 0h

104h 107h GPI Interrupt Status (GPI_IS_GPP_D)—Offset 104h 0h

108h 10Bh GPI Interrupt Status (GPI_IS_GPP_E)—Offset 108h 0h

120h 123h GPI Interrupt Enable (GPI_IE_GPP_C)—Offset 120h 0h

332219-002 575 GPIO for SKL PCH-LP

Table 7-2. Summary of GPIO Community 1 Registers (Continued)

Offset Offset Default Register Name (ID)—Offset Start End Value

124h 127h GPI Interrupt Enable (GPI_IE_GPP_D)—Offset 124h 0h

128h 12Bh GPI Interrupt Enable (GPI_IE_GPP_E)—Offset 128h 0h

140h 143h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C)—Offset 140h 0h

144h 147h GPI General Purpose Events Status (GPI_GPE_STS_GPP_D)—Offset 144h 0h

148h 14Bh GPI General Purpose Events Status (GPI_GPE_STS_GPP_E)—Offset 148h 0h

160h 163h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C)—Offset 160h 0h

164h 167h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_D)—Offset 164h 0h

168h 16Bh GPI General Purpose Events Enable (GPI_GPE_EN_GPP_E)—Offset 168h 0h

180h 183h SMI Status (GPI_SMI_STS_GPP_C)—Offset 180h 0h

184h 187h SMI Status (GPI_SMI_STS_GPP_D)—Offset 184h 0h

188h 18Bh SMI Status (GPI_SMI_STS_GPP_E)—Offset 188h 0h

1A0h 1A3h SMI Enable (GPI_SMI_EN_GPP_C)—Offset 1A0h 0h

1A4h 1A7h SMI Enable (GPI_SMI_EN_GPP_D)—Offset 1A4h 0h

1A8h 1ABh SMI Enable (GPI_SMI_EN_GPP_E)—Offset 1A8h 0h

1C0h 1C3h NMI Status (GPI_NMI_STS_GPP_C)—Offset 1C0h 0h

1C4h 1C7h NMI Status (GPI_NMI_STS_GPP_D)—Offset 1C4h 0h

1C8h 1CBh NMI Status (GPI_NMI_STS_GPP_E)—Offset 1C8h 0h

1E0h 1E3h NMI Enable (GPI_NMI_EN_GPP_C)—Offset 1E0h 0h

1E4h 1E7h NMI Enable (GPI_NMI_EN_GPP_D)—Offset 1E4h 0h

1E8h 1EBh NMI Enable (GPI_NMI_EN_GPP_E)—Offset 1E8h 0h

204h 207h PWM Control (PWMC)—Offset 204h 0h

20Ch 20Fh GPIO Serial Blink Enable (GP_SER_BLINK)—Offset 20Ch 0h

210h 213h GPIO Serial Blink Command/Status (GP_SER_CMDSTS)—Offset 210h 0h

214h 217h GPIO Serial Blink Data (GP_SER_DATA)—Offset 214h 0h

44000x00h 400h 403h Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_0)—Offset 400h See register for xx value

404h 407h Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_0)—Offset 404h 48h

44000x00h 408h 40Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_1)—Offset 408h See register for xx value

40Ch 40Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_1)—Offset 40Ch See register

44000x00h 410h 413h Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_2)—Offset 410h See register for xx value

414h 417h Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_2)—Offset 414h See register

44000x00h 418h 41Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_3)—Offset 418h See register for xx value

41Ch 41Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_3)—Offset 41Ch See register

44000x00h 420h 423h Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_4)—Offset 420h See register for xx value

424h 427h Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_4)—Offset 424h See register

576 332219-002

GPIO for SKL PCH-LP

Table 7-2. Summary of GPIO Community 1 Registers (Continued)

Offset Offset Default Register Name (ID)—Offset Start End Value

44000x00h 428h 42Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_5)—Offset 428h See register for xx value

42Ch 42Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_5)—Offset 42Ch See register

44000x00h 430h 433h Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_6)—Offset 430h See register for xx value

434h 437h Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_6)—Offset 434h See register

44000x00h 438h 43Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_7)—Offset 438h See register for xx value

43Ch 43Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_7)—Offset 43Ch See register

44000x00h 440h 443h Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_8)—Offset 440h See register for xx value

444h 447h Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_8)—Offset 444h See register

44000x00h 448h 44Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_9)—Offset 448h See register for xx value

44Ch 44Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_9)—Offset 44Ch See register

44000x00h 450h 453h Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_10)—Offset 450h See register for xx value

454h 457h Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_10)—Offset 454h See register

44000x00h 458h 45Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_11)—Offset 458h See register for xx value

45Ch 45Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_11)—Offset 45Ch See register

44000x00h 460h 463h Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_12)—Offset 460h See register for xx value

464h 467h Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_12)—Offset 464h See register

44000x00h 468h 46Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_13)—Offset 468h See register for xx value

46Ch 46Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_13)—Offset 46Ch See register

44000x00h 470h 473h Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_14)—Offset 470h See register for xx value

474h 477h Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_14)—Offset 474h See register

44000x00h 478h 47Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_15)—Offset 478h See register for xx value

47Ch 47Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_15)—Offset 47Ch See register

44000x00h 480h 483h Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_16)—Offset 480h See register for xx value

484h 487h Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_16)—Offset 484h See register

44000x00h 488h 48Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_17)—Offset 488h See register for xx value

332219-002 577 GPIO for SKL PCH-LP

Table 7-2. Summary of GPIO Community 1 Registers (Continued)

Offset Offset Default Register Name (ID)—Offset Start End Value

48Ch 48Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_17)—Offset 48Ch See register

44000x00h 490h 493h Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_18)—Offset 490h See register for xx value

494h 497h Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_18)—Offset 494h See register

44000x00h 498h 49Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_19)—Offset 498h See register for xx value

49Ch 49Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_19)—Offset 49Ch See register

44000x00h 4A0h 4A3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_20)—Offset 4A0h See register for xx value

4A4h 4A7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_20)—Offset 4A4h See register

44000x00h 4A8h 4ABh Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_21)—Offset 4A8h See register for xx value

4ACh 4AFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_21)—Offset 4ACh See register

44000x00h 4B0h 4B3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_22)—Offset 4B0h See register for xx value

4B4h 4B7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_22)—Offset 4B4h See register

44000x00h 4B8h 4BBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_23)—Offset 4B8h See register for xx value

4BCh 4BFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_23)—Offset 4BCh See register

44000x00h 4C0h 4C3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_0)—Offset 4C0h See register for xx value

4C4h 4C7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_0)—Offset 4C4h See register

44000x00h 4C8h 4CBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_1)—Offset 4C8h See register for xx value

4CCh 4CFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_1)—Offset 4CCh See register

44000x00h 4D0h 4D3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_2)—Offset 4D0h See register for xx value

4D4h 4D7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_2)—Offset 4D4h See register

44000x00h 4D8h 4DBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_3)—Offset 4D8h See register for xx value

4DCh 4DFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_3)—Offset 4DCh See register

44000x00h 4E0h 4E3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_4)—Offset 4E0h See register for xx value

4E4h 4E7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_4)—Offset 4E4h See register

44000x00h 4E8h 4EBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_5)—Offset 4E8h See register for xx value

4ECh 4EFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_5)—Offset 4ECh See register

578 332219-002

GPIO for SKL PCH-LP

Table 7-2. Summary of GPIO Community 1 Registers (Continued)

Offset Offset Default Register Name (ID)—Offset Start End Value

44000x00h 4F0h 4F3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_6)—Offset 4F0h See register for xx value

4F4h 4F7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_6)—Offset 4F4h See register

44000x00h 4F8h 4FBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_7)—Offset 4F8h See register for xx value

4FCh 4FFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_7)—Offset 4FCh See register

44000x00h 504h 507h Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_8)—Offset 504h See register for xx value

508h 50Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_9)—Offset 508h See register

44000x00h 50Ch 50Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_9)—Offset 50Ch See register for xx value

510h 513h Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_10)—Offset 510h See register

44000x00h 514h 517h Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_10)—Offset 514h See register for xx value

518h 51Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_11)—Offset 518h See register

44000x00h 51Ch 51Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_11)—Offset 51Ch See register for xx value

520h 523h Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_12)—Offset 520h See register

44000x00h 524h 527h Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_12)—Offset 524h See register for xx value

528h 52Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_13)—Offset 528h See register

44000x00h 52Ch 52Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_13)—Offset 52Ch See register for xx value

530h 533h Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_14)—Offset 530h See register

44000x00h 534h 537h Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_14)—Offset 534h See register for xx value

538h 53Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_15)—Offset 538h See register

44000x00h 53Ch 53Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_15)—Offset 53Ch See register for xx value

540h 543h Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_16)—Offset 540h See register

44000x00h 544h 547h Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_16)—Offset 544h See register for xx value

548h 54Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_17)—Offset 548h See register

44000x00h 54Ch 54Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_17)—Offset 54Ch See register for xx value

550h 553h Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_18)—Offset 550h See register

44000x00h 554h 557h Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_18)—Offset 554h See register for xx value

332219-002 579 GPIO for SKL PCH-LP

Table 7-2. Summary of GPIO Community 1 Registers (Continued)

Offset Offset Default Register Name (ID)—Offset Start End Value

558h 55Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_19)—Offset 558h See register

44000x00h 55Ch 55Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_19)—Offset 55Ch See register for xx value

560h 563h Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_20)—Offset 560h See register

44000x00h 564h 567h Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_20)—Offset 564h See register for xx value

568h 56Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_21)—Offset 568h See register

44000x00h 56Ch 56Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_21)—Offset 56Ch See register for xx value

570h 573h Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_22)—Offset 570h See register

44000x00h 574h 577h Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_22)—Offset 574h See register for xx value

578h 57Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_23)—Offset 578h See register

44000x00h 57Ch 57Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_23)—Offset 57Ch See register for xx value

580h 583h Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_0)—Offset 580h See register

44000x00h 584h 587h Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_0)—Offset 584h See register for xx value

588h 58Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_1)—Offset 588h See register

44000x00h 58Ch 58Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_1)—Offset 58Ch See register for xx value

590h 593h Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_2)—Offset 590h See register

44000x00h 594h 597h Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_2)—Offset 594h See register for xx value

598h 59Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_3)—Offset 598h See register

44000x00h 59Ch 59Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_3)—Offset 59Ch See register for xx value

5A0h 5A3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_4)—Offset 5A0h See register

44000x00h 5A4h 5A7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_4)—Offset 5A4h See register for xx value

5A8h 5ABh Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_5)—Offset 5A8h See register

44000x00h 5ACh 5AFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_5)—Offset 5ACh See register for xx value

5B0h 5B3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_6)—Offset 5B0h See register

44000x00h 5B4h 5B7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_6)—Offset 5B4h See register for xx value

5B8h 5BBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_7)—Offset 5B8h See register

580 332219-002

GPIO for SKL PCH-LP

Table 7-2. Summary of GPIO Community 1 Registers (Continued)

Offset Offset Default Register Name (ID)—Offset Start End Value

44000x00h 5BCh 5BFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_7)—Offset 5BCh See register for xx value

5C0h 5C3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_8)—Offset 5C0h See register

44000x00h 5C4h 5C7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_8)—Offset 5C4h See register for xx value

5C8h 5CBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_9)—Offset 5C8h See register

44000x00h 5CCh 5CFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_9)—Offset 5CCh See register for xx value

5D0h 5D3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_10)—Offset 5D0h See register

44000x00h 5D4h 5D7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_10)—Offset 5D4h See register for xx value

5D8h 5DBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_11)—Offset 5D8h See register

44000x00h 5DCh 5DFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_11)—Offset 5DCh See register for xx value

5E0h 5E3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_12)—Offset 5E0h See register

44000x00h 5E4h 5E7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_12)—Offset 5E4h See register for xx value

5E8h 5EBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_13)—Offset 5E8h See register

44000x00h 5ECh 5EFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_13)—Offset 5ECh See register for xx value

5F0h 5F3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_14)—Offset 5F0h See register

44000x00h 5F4h 5F7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_14)—Offset 5F4h See register for xx value

5F8h 5FBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_15)—Offset 5F8h See register

44000x00h 5FCh 5FFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_15)—Offset 5FCh See register for xx value

600h 603h Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_16)—Offset 600h See register

44000x00h 604h 607h Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_16)—Offset 604h See register for xx value

608h 60Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_17)—Offset 608h See register

44000x00h 60Ch 60Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_17)—Offset 60Ch See register for xx value

610h 613h Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_18)—Offset 610h See register

44000x00h 614h 617h Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_18)—Offset 614h See register for xx value

618h 61Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_19)—Offset 618h See register

44000x00h 61Ch 61Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_19)—Offset 61Ch See register for xx value

332219-002 581 GPIO for SKL PCH-LP

Table 7-2. Summary of GPIO Community 1 Registers (Continued)

Offset Offset Default Register Name (ID)—Offset Start End Value

620h 623h Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_20)—Offset 620h See register

44000x00h 624h 627h Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_20)—Offset 624h See register for xx value

628h 62Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_21)—Offset 628h See register

44000x00h 62Ch 62Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_21)—Offset 62Ch See register for xx value

630h 633h Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_22)—Offset 630h See register

44000x00h 634h 637h Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_22)—Offset 634h See register for xx value

638h 63Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_23)—Offset 638h See register

44000x00h 63Ch 63Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_23)—Offset 63Ch See register for xx value

7.2.1 Family Base Address (FAMBAR)—Offset 8h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 300h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000001100000000 RSVD FAMBAR

Bit Default & Field Name (ID): Description Range Access

0h 31:16 Reserved. RO

Family Base Address (FAMBAR): This field provides the starting byte-align 300h address of Family0 register sets. It is meant for software to discover from where the 15:0 RO very first Family register (i.e. Family0 register) starts to compute the next Families address offsets.

7.2.2 Pad Base Address (PADBAR)—Offset Ch

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 400h

582 332219-002

GPIO for SKL PCH-LP

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000010000000000 RSVD PADBAR

Bit Default & Field Name (ID): Description Range Access

0h 31:16 Reserved. RO

Pad Base Address (PADBAR): Pad Base Address (PADBAR) This field provides the 400h starting byte-align address of Pad0 register sets within a Community. It is meant for 15:0 RO software to discover from where the very first Pad register (i.e. Pad0 register) starts to compute the next Pad address offsets.

7.2.3 Miscellaneous Configuration (MISCCFG)—Offset 10h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 43200h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000001000011001000000000 RSVD RSVD RSVD GPDLCGEN GPDPCGEN GPE0_DW2 GPE0_DW1 GPE0_DW0 GPIO_DRIVER_IRQ_ROUTE

332219-002 583 GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h 31:20 Reserved. RO

GPIO Group to GPE_DW0 assignment encoding (GPE0_DW2): This register assigns a specific GPIO Group to the ACPI GPE0[95:64]. The selected GPIO group will be mapped to lower bits of the GPE register 0h = GPP_A[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 4h 1h = GPP_B[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 19:16 2h = GPP_C[23:0] mapped to GPE[87:64]; GPE[95:88] not used. RW 3h = GPP_D[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 4h = GPP_E[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 5h = GPP_F[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 6h = GPP_G[7:0] mapped to GPE[51:64]; GPE[95:52] not used. 7h = GPD[11:0] mapped to GPE[75:64]; GPE[95:76] not used.

GPIO Group to GPE_DW0 assignment encoding (GPE0_DW1): This register assigns a specific GPIO Group to the ACPI GPE0[63:32]. The selected GPIO group will be mapped to lower bits of the GPE register 0h = GPP_A[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 3h 1h = GPP_B[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 15:12 2h = GPP_C[23:0] mapped to GPE[55:32]; GPE[63:56] not used. RW 3h = GPP_D[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 4h = GPP_E[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 5h = GPP_F[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 6h = GPP_G[7:0] mapped to GPE[39:32]; GPE[63:40] not used. 7h = GPD[11:0] mapped to GPE[43:32]; GPE[63:44] not used.

GPIO Group to GPE_DW0 assignment encoding (GPE0_DW0): This register assigns a specific GPIO Group to the ACPI GPE0[31:0]. The selected GPIO group will be mapped to lower bits of the GPE register 0h = GPP_A[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 2h 1h = GPP_B[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 11:8 2h = GPP_C[23:0] mapped to GPE[23:0]; GPE[31:24] not used. RW 3h = GPP_D[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 4h = GPP_E[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 5h = GPP_F[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 6h = GPP_G[7:0] mapped to GPE[7:0]; GPE[31:8] not used. 7h = GPD[11:0] mapped to GPE[11:0]; GPE[31:12] not used.

0h 7:4 Reserved. RO

GPIO Driver IRQ Route (GPIO_DRIVER_IRQ_ROUTE): GPIO Driver 0h IRQ_ROUTE[1:0]: Specifies the APIC IRQ globally for all pads within the current 3 community (GPI_IS with corresponding GPI_IE enable). RW 0 = IRQ14 1 = IRQ15

0h 2 Reserved. RO

GPIO Dynamic Partition Clock Gating Enable (GPDPCGEN): Specifies whether 0h the GPIO Community should take part in partition clock gating 1 RW 0 = Disable participation in dynamic partition clock gating 1 = Enable participation in dynamic partition clock gating

GPIO Dynamic Local Clock Gating Enable (GPDLCGEN): Specifies whether the 0h GPIO Community should perform local clock gating. 0 RW 0 = Disable dynamic local clock gating 1 = Enable dynamic local clock gating

7.2.4 Pad Ownership (PAD_OWN_GPP_C_0)—Offset 20h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

584 332219-002

GPIO for SKL PCH-LP

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD PAD_OWN_GPP_C_7 PAD_OWN_GPP_C_6 PAD_OWN_GPP_C_5 PAD_OWN_GPP_C_4 PAD_OWN_GPP_C_3 PAD_OWN_GPP_C_2 PAD_OWN_GPP_C_1 PAD_OWN_GPP_C_0

Bit Default & Field Name (ID): Description Range Access

0h 31:30 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_C_7): Same description as bit 0, except that 29:28 RO the bit field applies to GPP_C7.

0h 27:26 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_C_6): Same description as bit 0, except that 25:24 RO the bit field applies to GPP_C6.

0h 23:22 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_C_5): Same description as bit 0, except that 21:20 RO the bit field applies to GPP_C5.

0h 19:18 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_C_4): Same description as bit 0, except that 17:16 RO the bit field applies to GPP_C4.

0h 15:14 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_C_3): Same description as bit 0, except that 13:12 RO the bit field applies to GPP_C3.

0h 11:10 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_C_2): Same description as bit 0, except that 9:8 RO the bit field applies to GPP_C2.

0h 7:6 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_C_1): Same description as bit 0, except that 5:4 RO the bit field applies to GPP_C1.

0h 3:2 Reserved. RO

Pad Ownership (PAD_OWN_GPP_C_0): 00 = Host GPIO ACPI Mode or GPIO Driver Mode. Host software (ACPI or GPIO Driver) has ownership of the pad. In Host GPIO Driver Mode (refer to HOSTSW_OWN), GPIO input event update is limited to 0h GPI_STS update only. Otherwise in Host ACPI Mode, updates are limited to 1:0 RO GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. 01 = ME GPIO Mode. ME has ownership of the pad. 10 = ISH GPIO Mode.ME has ownership of the pad 11 = Reserved

332219-002 585 GPIO for SKL PCH-LP

7.2.5 Pad Ownership (PAD_OWN_GPP_C_1)—Offset 24h

Same description as PAD_OWN_GPP_C_0, except that this register is for GPP_C[15:8]

7.2.6 Pad Ownership (PAD_OWN_GPP_C_2)—Offset 28h

Same description as PAD_OWN_GPP_C_0, except that this register is for GPP_C[23:16]

7.2.7 Pad Ownership (PAD_OWN_GPP_D_0)—Offset 30h

Same description as PAD_OWN_GPP_C_0, except that this register is for GPP_D[7:0]

7.2.8 Pad Ownership (PAD_OWN_GPP_D_1)—Offset 34h

Same description as PAD_OWN_GPP_C_0, except that this register is for GPP_D[15:8]

7.2.9 Pad Ownership (PAD_OWN_GPP_D_2)—Offset 38h

Same description as PAD_OWN_GPP_C_0, except that this register is for GPP_D[23:16]

7.2.10 Pad Ownership (PAD_OWN_GPP_E_0)—Offset 40h

Same description as PAD_OWN_GPP_C_0, except that this register is for GPP_E[7:0]

7.2.11 Pad Ownership (PAD_OWN_GPP_E_1)—Offset 44h

Same description as PAD_OWN_GPP_C_0, except that this register is for GPP_E[15:8]

7.2.12 Pad Ownership (PAD_OWN_GPP_E_2)—Offset 48h

Same description as PAD_OWN_GPP_C_0, except that this register is for GPP_E[23:16]

7.2.13 Pad Configuration Lock (PADCFGLOCK_GPP_C)—Offset A0h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

586 332219-002

GPIO for SKL PCH-LP

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD PADCFGLOCK_GPP_C_9 PADCFGLOCK_GPP_C_8 PADCFGLOCK_GPP_C_7 PADCFGLOCK_GPP_C_6 PADCFGLOCK_GPP_C_5 PADCFGLOCK_GPP_C_4 PADCFGLOCK_GPP_C_3 PADCFGLOCK_GPP_C_2 PADCFGLOCK_GPP_C_1 PADCFGLOCK_GPP_C_0 PADCFGLOCK_GPP_C_23 PADCFGLOCK_GPP_C_22 PADCFGLOCK_GPP_C_21 PADCFGLOCK_GPP_C_20 PADCFGLOCK_GPP_C_19 PADCFGLOCK_GPP_C_18 PADCFGLOCK_GPP_C_17 PADCFGLOCK_GPP_C_16 PADCFGLOCK_GPP_C_15 PADCFGLOCK_GPP_C_14 PADCFGLOCK_GPP_C_13 PADCFGLOCK_GPP_C_12 PADCFGLOCK_GPP_C_11 PADCFGLOCK_GPP_C_10

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h Pad Config Lock (PADCFGLOCK_GPP_C_23): Applied to GPP_C23. Same 23 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_22): Applied to GPP_C22. Same 22 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_21): Applied to GPP_C21. Same 21 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_20): Applied to GPP_C20. Same 20 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_19): Applied to GPP_C19. Same 19 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_18): Applied to GPP_C18. Same 18 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_17): Applied to GPP_C17. Same 17 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_16): Applied to GPP_C16. Same 16 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_15): Applied to GPP_C15. Same 15 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_14): Applied to GPP_C14. Same 14 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_13): Applied to GPP_C13. Same 13 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_12): Applied to GPP_C12. Same 12 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_11): Applied to GPP_C11. Same 11 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_10): Applied to GPP_C10. Same 10 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_9): Applied to GPP_C9. Same 9 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_8): Applied to GPP_C8. Same 8 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_7): Applied to GPP_C7. Same 7 RW description as bit 0.

332219-002 587 GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h Pad Config Lock (PADCFGLOCK_GPP_C_6): Applied to GPP_C6. Same 6 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_5): Applied to GPP_C5. Same 5 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_4): Applied to GPP_C4. Same 4 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_3): Applied to GPP_C3. Same 3 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_2): Applied to GPP_C2. Same 2 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_C_1): Applied to GPP_C1. Same 1 RW description as bit 0.

Pad Config Lock (PADCFGLOCK_GPP_C_0): Pad Configuration Lock locks specific register fields in the GPP specific registers from being configured. The registers affected become Read-Only and software writes to these registers have no effect. 0 = Unlock 1 = Lock the following register fields as read-only (RO): 0h - Pad Configuration registers (exclude GPIOTXState) 0 RW - GPI_NMI_EN Register (if implemented) - GPI_SMI_EN Register (if implemented) - GPI_GPE_EN Register (if implemented) When PadCfgLock is written from a '1' to a '0' (unlock), a synchronous SMI# is generated if enabled. This ensures that only SMM code can change the above GPIO registers after the lockdown.

7.2.14 Pad Configuration Lock (PADCFGLOCKTX_GPP_C)—Offset A4h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD PADCFGLOCKTX_GPP_C_9 PADCFGLOCKTX_GPP_C_8 PADCFGLOCKTX_GPP_C_7 PADCFGLOCKTX_GPP_C_6 PADCFGLOCKTX_GPP_C_5 PADCFGLOCKTX_GPP_C_4 PADCFGLOCKTX_GPP_C_3 PADCFGLOCKTX_GPP_C_2 PADCFGLOCKTX_GPP_C_1 PADCFGLOCKTX_GPP_C_0 PADCFGLOCKTX_GPP_C_23 PADCFGLOCKTX_GPP_C_22 PADCFGLOCKTX_GPP_C_21 PADCFGLOCKTX_GPP_C_20 PADCFGLOCKTX_GPP_C_19 PADCFGLOCKTX_GPP_C_18 PADCFGLOCKTX_GPP_C_17 PADCFGLOCKTX_GPP_C_16 PADCFGLOCKTX_GPP_C_15 PADCFGLOCKTX_GPP_C_14 PADCFGLOCKTX_GPP_C_13 PADCFGLOCKTX_GPP_C_12 PADCFGLOCKTX_GPP_C_11 PADCFGLOCKTX_GPP_C_10

588 332219-002

GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_23): Applied to GPP_C23. 23 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_22): Applied to GPP_C22. 22 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_21): Applied to GPP_C21. 21 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_20): Applied to GPP_C20. 20 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_19): Applied to GPP_C19. 19 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_18): Applied to GPP_C18. 18 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_17): Applied to GPP_C17. 17 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_16): Applied to GPP_C16. 16 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_15): Applied to GPP_C15. 15 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_14): Applied to GPP_C14. 14 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_13): Applied to GPP_C13. 13 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_12): Applied to GPP_C12. 12 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_11): Applied to GPP_C11. 11 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_10): Applied to GPP_C10. 10 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_9): Applied to GPP_C9. 9 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_8): Applied to GPP_C8. 8 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_7): Applied to GPP_C7. 7 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_6): Applied to GPP_C6. 6 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_5): Applied to GPP_C5. 5 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_4): Applied to GPP_C4. 4 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_3): Applied to GPP_C3. 3 RW Same description as bit 0.

332219-002 589 GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_2): Applied to GPP_C2. 2 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_1): Applied to GPP_C1. 1 RW Same description as bit 0.

Pad Config Lock TXState (PADCFGLOCKTX_GPP_C_0): PadCfgLockTx locks the GPIOTxState bit from being configured. The GPIOTxState register becomes Read- Only and software writes to the register have no effect. 0h 0 = Unlock 0 1 = Locks the Pad RW Configuration GPIOTXState field as read-only (RO) When PadCfgLockTx is written from a '1' to a '0' (unlock), a synchronous SMI# is generated if enabled. This ensures that only SMM code can change the above GPIO registers after the lockdown.

7.2.15 Pad Configuration Lock (PADCFGLOCK_GPP_D)—Offset A8h

Same description as PADCFGLOCK_GPP_C register, except that this is for GPP_D.

7.2.16 Pad Configuration Lock (PADCFGLOCKTX_GPP_D)—Offset ACh

Same description as PADCFGLOCKTX_GPP_C, except this register is for GPP_D

7.2.17 Pad Configuration Lock (PADCFGLOCK_GPP_E)—Offset B0h

Same description as PADCFGLOCK_GPP_C, except that this register is for GPP_E

7.2.18 Pad Configuration Lock (PADCFGLOCKTX_GPP_E)—Offset B4h

Same description as PADCFGLOCKTX_GPP_C, except that this register is for GPP_E

7.2.19 Host Software Pad Ownership (HOSTSW_OWN_GPP_C)— Offset D0h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

590 332219-002

GPIO for SKL PCH-LP

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD HOSTSW_OWN_GPP_C_9 HOSTSW_OWN_GPP_C_8 HOSTSW_OWN_GPP_C_7 HOSTSW_OWN_GPP_C_6 HOSTSW_OWN_GPP_C_5 HOSTSW_OWN_GPP_C_4 HOSTSW_OWN_GPP_C_3 HOSTSW_OWN_GPP_C_2 HOSTSW_OWN_GPP_C_1 HOSTSW_OWN_GPP_C_0 HOSTSW_OWN_GPP_C_23 HOSTSW_OWN_GPP_C_22 HOSTSW_OWN_GPP_C_21 HOSTSW_OWN_GPP_C_20 HOSTSW_OWN_GPP_C_19 HOSTSW_OWN_GPP_C_18 HOSTSW_OWN_GPP_C_17 HOSTSW_OWN_GPP_C_16 HOSTSW_OWN_GPP_C_15 HOSTSW_OWN_GPP_C_14 HOSTSW_OWN_GPP_C_13 HOSTSW_OWN_GPP_C_12 HOSTSW_OWN_GPP_C_11 HOSTSW_OWN_GPP_C_10

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h HostSW_Own (HOSTSW_OWN_GPP_C_23): Applied to GPP_C23. Same 23 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_22): Applied to GPP_C22. Same 22 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_21): Applied to GPP_C21. Same 21 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_20): Applied to GPP_C20. Same 20 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_19): Applied to GPP_C19. Same 19 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_18): Applied to GPP_C18. Same 18 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_17): Applied to GPP_C17. Same 17 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_16): Applied to GPP_C16. Same 16 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_15): Applied to GPP_C15. Same 15 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_14): Applied to GPP_C14. Same 14 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_13): Applied to GPP_C13. Same 13 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_12): Applied to GPP_C12. Same 12 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_11): Applied to GPP_C11. Same 11 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_10): Applied to GPP_C10. Same 10 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_9): Applied to GPP_C9. Same description 9 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_8): Applied to GPP_C8. Same description 8 RW as bit 0.

332219-002 591 GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h HostSW_Own (HOSTSW_OWN_GPP_C_7): Applied to GPP_C7. Same description 7 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_6): Applied to GPP_C6. Same description 6 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_5): Applied to GPP_C5. Same description 5 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_4): Applied to GPP_C4. Same description 4 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_3): Applied to GPP_C3. Same description 3 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_2): Applied to GPP_C2. Same description 2 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_C_1): Applied to GPP_C1. Same description 1 RW as bit 0.

HostSW_Own (HOSTSW_OWN_GPP_C_0): This register determines the appropriate host status bit update when a pad is under host ownership. 0h 0 = ACPI Mode. GPIO input event updates are limited to GPI_GPE_STS, 0 RW GPI_NMI_STS and/or GPI_SMI_STS. GPI_STS update is masked. 1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked.

7.2.20 Host Software Pad Ownership (HOSTSW_OWN_GPP_D)— Offset D4h

Same description as HOSTSW_OWN_GPP_C register, except that the register is for GPP_D.

7.2.21 Host Software Pad Ownership (HOSTSW_OWN_GPP_E)— Offset D8h

Same description as HOSTSW_OWN_GPP_C register, except that the register is for GPP_E.

7.2.22 GPI Interrupt Status (GPI_IS_GPP_C)—Offset 100h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

592 332219-002

GPIO for SKL PCH-LP

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_INT_STS_GPP_C_9 GPI_INT_STS_GPP_C_8 GPI_INT_STS_GPP_C_7 GPI_INT_STS_GPP_C_6 GPI_INT_STS_GPP_C_5 GPI_INT_STS_GPP_C_4 GPI_INT_STS_GPP_C_3 GPI_INT_STS_GPP_C_2 GPI_INT_STS_GPP_C_1 GPI_INT_STS_GPP_C_0 GPI_INT_STS_GPP_C_23 GPI_INT_STS_GPP_C_22 GPI_INT_STS_GPP_C_21 GPI_INT_STS_GPP_C_20 GPI_INT_STS_GPP_C_19 GPI_INT_STS_GPP_C_18 GPI_INT_STS_GPP_C_17 GPI_INT_STS_GPP_C_16 GPI_INT_STS_GPP_C_15 GPI_INT_STS_GPP_C_14 GPI_INT_STS_GPP_C_13 GPI_INT_STS_GPP_C_12 GPI_INT_STS_GPP_C_11 GPI_INT_STS_GPP_C_10

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_23): Applied to GPP_C23. Same 23 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_22): Applied to GPP_C22. Same 22 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_21): Applied to GPP_C21. Same 21 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_20): Applied to GPP_C20. Same 20 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_19): Applied to GPP_C19. Same 19 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_18): Applied to GPP_C18. Same 18 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_17): Applied to GPP_C17. Same 17 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_16): Applied to GPP_C16. Same 16 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_15): Applied to GPP_C15. Same 15 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_14): Applied to GPP_C14. Same 14 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_13): Applied to GPP_C13. Same 13 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_12): Applied to GPP_C12. Same 12 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_11): Applied to GPP_C11. Same 11 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_10): Applied to GPP_C10. Same 10 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_9): Applied to GPP_C9. Same 9 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_8): Applied to GPP_C8. Same 8 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_7): Applied to GPP_C7. Same 7 RW1C description as bit 0.

332219-002 593 GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_6): Applied to GPP_C6. Same 6 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_5): Applied to GPP_C5. Same 5 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_4): Applied to GPP_C4. Same 4 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_3): Applied to GPP_C3. Same 3 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_2): Applied to GPP_C2. Same 2 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_C_1): Applied to GPP_C1. Same 1 RW1C description as bit 0.

GPI Interrupt Status (GPI_INT_STS_GPP_C_0): This bit is set to ‘1’ by hardware when either an edge or a level event is detected (See RxEdCfg RxInv) on pad and all the following conditions are true: 0h - The corresponding pad is used in GPIO input mode 0 - HOSTSW_OWN = 1 (i.e. Host GPIO Driver Mode). RW1C Writing a value of 1 will clear the bit while writing a value of 0 has no effect. 0 = No interrupt 1 = Interrupt asserts The state of GPI_INT_EN does not prevent the setting of GPI_INT_STS.

7.2.23 GPI Interrupt Status (GPI_IS_GPP_D)—Offset 104h

Same description as GPI_IS_GPP_C register, except that the register is for GPP_D

7.2.24 GPI Interrupt Status (GPI_IS_GPP_E)—Offset 108h

Same description as GPI_IS_GPP_C, except that the register is for GPP_E

7.2.25 GPI Interrupt Enable (GPI_IE_GPP_C)—Offset 120h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_INT_EN_GPP_C_9 GPI_INT_EN_GPP_C_8 GPI_INT_EN_GPP_C_7 GPI_INT_EN_GPP_C_6 GPI_INT_EN_GPP_C_5 GPI_INT_EN_GPP_C_4 GPI_INT_EN_GPP_C_3 GPI_INT_EN_GPP_C_2 GPI_INT_EN_GPP_C_1 GPI_INT_EN_GPP_C_0 GPI_INT_EN_GPP_C_23 GPI_INT_EN_GPP_C_22 GPI_INT_EN_GPP_C_21 GPI_INT_EN_GPP_C_20 GPI_INT_EN_GPP_C_19 GPI_INT_EN_GPP_C_18 GPI_INT_EN_GPP_C_17 GPI_INT_EN_GPP_C_16 GPI_INT_EN_GPP_C_15 GPI_INT_EN_GPP_C_14 GPI_INT_EN_GPP_C_13 GPI_INT_EN_GPP_C_12 GPI_INT_EN_GPP_C_11 GPI_INT_EN_GPP_C_10

594 332219-002

GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_23): Applied to GPP_C23. Same 23 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_22): Applied to GPP_C22. Same 22 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_21): Applied to GPP_C21. Same 21 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_20): Applied to GPP_C20. Same 20 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_19): Applied to GPP_C19. Same 19 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_18): Applied to GPP_C18. Same 18 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_17): Applied to GPP_C17. Same 17 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_16): Applied to GPP_C16. Same 16 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_15): Applied to GPP_C15. Same 15 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_14): Applied to GPP_C14. Same 14 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_13): Applied to GPP_C13. Same 13 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_12): Applied to GPP_C12. Same 12 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_11): Applied to GPP_C11. Same 11 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_10): Applied to GPP_C10. Same 10 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_9): Applied to GPP_C9. Same 9 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_8): Applied to GPP_C8. Same 8 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_7): Applied to GPP_C7. Same 7 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_6): Applied to GPP_C6. Same 6 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_5): Applied to GPP_C5. Same 5 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_4): Applied to GPP_C4. Same 4 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_3): Applied to GPP_C3. Same 3 RW description as bit 0.

332219-002 595 GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_2): Applied to GPP_C2. Same 2 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_C_1): Applied to GPP_C1. Same 1 RW description as bit 0.

GPI Interrupt Enable (GPI_INT_EN_GPP_C_0): This bit is used to enable/ disable the generation of APIC interrupt when the corresponding GPI_INT_STS bit is 0h set. 0 RW 0 = disable interrupt generation 1 = enable interrupt generation Refer to GPI_IRQ_ROUTE for host GPIO Driver Mode interrupt routing.

7.2.26 GPI Interrupt Enable (GPI_IE_GPP_D)—Offset 124h

Same description as GPI_IE_GPP_C, except that this register is for GPP_D

7.2.27 GPI Interrupt Enable (GPI_IE_GPP_E)—Offset 128h

Same description as GPI_IE_GPP_C, except that this register is for GPP_E.

7.2.28 GPI General Purpose Events Status (GPI_GPE_STS_GPP_C)—Offset 140h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_GPE_STS_GPP_C_9 GPI_GPE_STS_GPP_C_8 GPI_GPE_STS_GPP_C_7 GPI_GPE_STS_GPP_C_6 GPI_GPE_STS_GPP_C_5 GPI_GPE_STS_GPP_C_4 GPI_GPE_STS_GPP_C_3 GPI_GPE_STS_GPP_C_2 GPI_GPE_STS_GPP_C_1 GPI_GPE_STS_GPP_C_0 GPI_GPE_STS_GPP_C_23 GPI_GPE_STS_GPP_C_22 GPI_GPE_STS_GPP_C_21 GPI_GPE_STS_GPP_C_20 GPI_GPE_STS_GPP_C_19 GPI_GPE_STS_GPP_C_18 GPI_GPE_STS_GPP_C_17 GPI_GPE_STS_GPP_C_16 GPI_GPE_STS_GPP_C_15 GPI_GPE_STS_GPP_C_14 GPI_GPE_STS_GPP_C_13 GPI_GPE_STS_GPP_C_12 GPI_GPE_STS_GPP_C_11 GPI_GPE_STS_GPP_C_10

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_23): Applied to 23 RW1C GPP_C23. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_22): Applied to 22 RW1C GPP_C22. Same description as bit 0.

596 332219-002

GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_21): Applied to 21 RW1C GPP_C21. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_20): Applied to 20 RW1C GPP_C20. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_19): Applied to 19 RW1C GPP_C19. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_18): Applied to 18 RW1C GPP_C18. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_17): Applied to 17 RW1C GPP_C17. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_16): Applied to 16 RW1C GPP_C16. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_15): Applied to 15 RW1C GPP_C15. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_14): Applied to 14 RW1C GPP_C14. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_13): Applied to 13 RW1C GPP_C13. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_12): Applied to 12 RW1C GPP_C12. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_11): Applied to 11 RW1C GPP_C11. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_10): Applied to 10 RW1C GPP_C10. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_9): Applied to 9 RW1C GPP_C9. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_8): Applied to 8 RW1C GPP_C8. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_7): Applied to 7 RW1C GPP_C7. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_6): Applied to 6 RW1C GPP_C6. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_5): Applied to 5 RW1C GPP_C5. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_4): Applied to 4 RW1C GPP_C4. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_3): Applied to 3 RW1C GPP_C3. Same description as bit 0.

332219-002 597 GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_2): Applied to 2 RW1C GPP_C2. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_1): Applied to 1 RW1C GPP_C1. Same description as bit 0.

GPI General Purpose Events Status (GPI_GPE_STS_GPP_C_0): These bits are set any time the corresponding GPIO pad is set up as an input, under host ownership and the corresponding GPIO signal is high(or low if the corresponding RXINV bit is set). If the corresponding enable bit is set in the GPI_GPE_EN register, then when the 0h GPI_GPE_STS bit is set: 0 RW1C - If the system is in an S3-S5 state, the event will also wake the system. - If the system is in an S0 state (or upon waking back to an S0 state), an SCI will be caused, depending on the GPIRoutSCI bit for the corresponding pad. These bits are sticky bits and are cleared by writing a 1 back to this bit position. The state of GPI_GPE_EN does not prevent the setting of GPI_GPE_STS.

7.2.29 GPI General Purpose Events Status (GPI_GPE_STS_GPP_D)—Offset 144h

Same description as GPI_GPE_STS_GPP_C, except that this register is for GPP_D.

7.2.30 GPI General Purpose Events Status (GPI_GPE_STS_GPP_E)—Offset 148h

Same description as GPI_GPE_STS_GPP_C, except that this register is for GPP_E.

7.2.31 GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C)—Offset 160h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_GPE_EN_GPP_C_9 GPI_GPE_EN_GPP_C_8 GPI_GPE_EN_GPP_C_7 GPI_GPE_EN_GPP_C_6 GPI_GPE_EN_GPP_C_5 GPI_GPE_EN_GPP_C_4 GPI_GPE_EN_GPP_C_3 GPI_GPE_EN_GPP_C_2 GPI_GPE_EN_GPP_C_1 GPI_GPE_EN_GPP_C_0 GPI_GPE_EN_GPP_C_23 GPI_GPE_EN_GPP_C_22 GPI_GPE_EN_GPP_C_21 GPI_GPE_EN_GPP_C_20 GPI_GPE_EN_GPP_C_19 GPI_GPE_EN_GPP_C_18 GPI_GPE_EN_GPP_C_17 GPI_GPE_EN_GPP_C_16 GPI_GPE_EN_GPP_C_15 GPI_GPE_EN_GPP_C_14 GPI_GPE_EN_GPP_C_13 GPI_GPE_EN_GPP_C_12 GPI_GPE_EN_GPP_C_11 GPI_GPE_EN_GPP_C_10

598 332219-002

GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_23): Applied to 23 RW GPP_C23. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_22): Applied to 22 RW GPP_C22. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_21): Applied to 21 RW GPP_C21. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_20): Applied to 20 RW GPP_C20. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_19): Applied to 19 RW GPP_C19. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_18): Applied to 18 RW GPP_C18. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_17): Applied to 17 RW GPP_C17. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_16): Applied to 16 RW GPP_C16. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_15): Applied to 15 RW GPP_C15. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_14): Applied to 14 RW GPP_C14. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_13): Applied to 13 RW GPP_C13. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_12): Applied to 12 RW GPP_C12. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_11): Applied to 11 RW GPP_C11. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_10): Applied to 10 RW GPP_C10. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_9): Applied to 9 RW GPP_C9. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_8): Applied to 8 RW GPP_C8. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_7): Applied to 7 RW GPP_C7. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_6): Applied to 6 RW GPP_C6. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_5): Applied to 5 RW GPP_C5. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_4): Applied to 4 RW GPP_C4. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_3): Applied to 3 RW GPP_C3. Same description as bit 0.

332219-002 599 GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_2): Applied to 2 RW GPP_C2. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_1): Applied to 1 RW GPP_C1. Same description as bit 0.

GPI General Purpose Events Enable (GPI_GPE_EN_GPP_C_0): This bit is used to enable/disable the generation of GPE to cause SCI and/or wake when the

0h corresponding GPI_GPE_STS bit is set. 0 0 = disable GPE generation RW 1 = enable GPE generation Note: The pad must also be routed for GPE functionality in order for GPE to be generated, i.e. the corresponding GPIRoutSCI must be set to '1'.

7.2.32 GPI General Purpose Events Enable (GPI_GPE_EN_GPP_D)—Offset 164h

Same description as GPI_GPE_EN_GPP_C, except that the register is for GPP_D.

7.2.33 GPI General Purpose Events Enable (GPI_GPE_EN_GPP_E)—Offset 168h

Same description as GPI_GPE_EN_GPP_C, except that the register is for GPP_E.

7.2.34 SMI Status (GPI_SMI_STS_GPP_C)—Offset 180h

Register bits in this register are implemented for GPP_C signals that have SMI capability only. Other bits are reserved and RO.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD GPI_SMI_STS_GPP_C_23 GPI_SMI_STS_GPP_C_22

600 332219-002

GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h GPI SMI Status (GPI_SMI_STS_GPP_C_23): Same description as bit 22. 23 RW1C

GPI SMI Status (GPI_SMI_STS_GPP_C_22): This bit is set to 1 by hardware when a level event (See RxEdCfg,RxInv) is detected, and all the following conditions are true: - The corresponding pad is used in GPIO input mode - The corresponding PAD_OWN[2:0] is ‘000’ (i.e. ACPI GPIO Mode). 0h If the following conditions are true, then an SMI will be generated if the 22 GPI_SMI_STS bit is set: RW1C 1. The corresponding bit in the GPI_SMI_EN register is set 2. The corresponding pad’s GPIROUTSMI is set Writing a value of 1 will clear the bit while writing a value of 0 has no effect. 0 = There is no SMI event 1 = There is an SMI event The state of GPI_SMI_EN does not prevent the setting of GPI_SMI_STS.

0h 21:0 Reserved. RO

7.2.35 SMI Status (GPI_SMI_STS_GPP_D)—Offset 184h

Register bits in this register are implemented for GPP_D signals that have SMI capability only. Other bits are reserved and RO.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_SMI_STS_GPP_D_4 GPI_SMI_STS_GPP_D_3 GPI_SMI_STS_GPP_D_2 GPI_SMI_STS_GPP_D_1 GPI_SMI_STS_GPP_D_0

Bit Default & Field Name (ID): Description Range Access

0h 31:5 Reserved. RO

0h GPI SMI Status (GPI_SMI_STS_GPP_D_4): Same description as bit 0. 4 RW1C

0h GPI SMI Status (GPI_SMI_STS_GPP_D_3): Same description as bit 0. 3 RW1C

332219-002 601 GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h GPI SMI Status (GPI_SMI_STS_GPP_D_2): Same description as bit 0. 2 RW1C

0h GPI SMI Status (GPI_SMI_STS_GPP_D_1): Same description as bit 0. 1 RW1C

GPI SMI Status (GPI_SMI_STS_GPP_D_0): This bit is set to 1 by hardware when a level event (See RxEdCfg,RxInv) is detected, and all the following conditions are true: - The corresponding pad is used in GPIO input mode - The corresponding PAD_OWN[2:0] is ‘000’ (i.e. ACPI GPIO Mode). 0h If the following conditions are true, then an SMI will be generated if the 0 GPI_SMI_STS bit is set: RW1C 1. The corresponding bit in the GPI_SMI_EN register is set 2. The corresponding pad’s GPIROUTSMI is set Writing a value of 1 will clear the bit while writing a value of 0 has no effect. 0 = There is no SMI event 1 = There is an SMI event The state of GPI_SMI_EN does not prevent the setting of GPI_SMI_STS.

7.2.36 SMI Status (GPI_SMI_STS_GPP_E)—Offset 188h

Register bits in this register are implemented for GPP_E signals that have SMI capability only. Other bits are reserved and RO.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_SMI_STS_GPP_E_8 GPI_SMI_STS_GPP_E_7 GPI_SMI_STS_GPP_E_6 GPI_SMI_STS_GPP_E_5 GPI_SMI_STS_GPP_E_4 GPI_SMI_STS_GPP_E_3 GPI_SMI_STS_GPP_E_2 GPI_SMI_STS_GPP_E_1 GPI_SMI_STS_GPP_E_0

Bit Default & Field Name (ID): Description Range Access

0h 31:9 Reserved. RO

0h GPI SMI Status (GPI_SMI_STS_GPP_E_8): Same description as bit 0. 8 RW1C

0h GPI SMI Status (GPI_SMI_STS_GPP_E_7): Same description as bit 0. 7 RW1C

0h GPI SMI Status (GPI_SMI_STS_GPP_E_6): Same description as bit 0. 6 RW1C

602 332219-002

GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h GPI SMI Status (GPI_SMI_STS_GPP_E_5): Same description as bit 0. 5 RW1C

0h GPI SMI Status (GPI_SMI_STS_GPP_E_4): Same description as bit 0. 4 RW1C

0h GPI SMI Status (GPI_SMI_STS_GPP_E_3): Same description as bit 0. 3 RW1C

0h GPI SMI Status (GPI_SMI_STS_GPP_E_2): Same description as bit 0. 2 RW1C

0h GPI SMI Status (GPI_SMI_STS_GPP_E_1): Same description as bit 0. 1 RW1C

GPI SMI Status (GPI_SMI_STS_GPP_E_0): This bit is set to 1 by hardware when a level event (See RxEdCfg,RxInv) is detected, and all the following conditions are true: - The corresponding pad is used in GPIO input mode - The corresponding PAD_OWN[2:0] is ‘000’ (i.e. ACPI GPIO Mode). 0h If the following conditions are true, then an SMI will be generated if the 0 GPI_SMI_STS bit is set: RW1C 1. The corresponding bit in the GPI_SMI_EN register is set 2. The corresponding pad’s GPIROUTSMI is set Writing a value of 1 will clear the bit while writing a value of 0 has no effect. 0 = There is no SMI event 1 = There is an SMI event The state of GPI_SMI_EN does not prevent the setting of GPI_SMI_STS.

7.2.37 SMI Enable (GPI_SMI_EN_GPP_C)—Offset 1A0h

Register bits in this register are implemented for GPP_C signals that have SMI capability only. Other bits are reserved and RO.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD GPI_SMI_EN_GPP_C_23 GPI_SMI_EN_GPP_C_22

332219-002 603 GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h GPI SMI Enable (GPI_SMI_EN_GPP_C_23): Same description as bit 22. 23 RW

GPI SMI Enable (GPI_SMI_EN_GPP_C_22): This bit is used to enable/disable the generation of SMI when the corresponding GPI_SMI_STS bit is set. The pad must also be routed for SMI functionality in order for SMI to be generated, i.e. the

0h corresponding GPIROUTSMI must be set to 1. 22 0 = disable SMI generation RW 1 = enable SMI generation Note: Each of the bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. E.g. if the PadCfgLock of pad0 is 1, bit0 of this bit is locked down to read-only.

0h 21:0 Reserved. RO

7.2.38 SMI Enable (GPI_SMI_EN_GPP_D)—Offset 1A4h

Register bits in this register are implemented for GPP_D signals that have SMI capability only. Other bits are reserved and RO.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_SMI_EN_GPP_D_4 GPI_SMI_EN_GPP_D_3 GPI_SMI_EN_GPP_D_2 GPI_SMI_EN_GPP_D_1 GPI_SMI_EN_GPP_D_0

Bit Default & Field Name (ID): Description Range Access

0h 31:5 Reserved. RO

0h GPI SMI Enable (GPI_SMI_EN_GPP_D_4): Same description as bit 0. 4 RW

0h GPI SMI Enable (GPI_SMI_EN_GPP_D_3): Same description as bit 0. 3 RW

604 332219-002

GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h GPI SMI Enable (GPI_SMI_EN_GPP_D_2): Same description as bit 0. 2 RW

0h GPI SMI Enable (GPI_SMI_EN_GPP_D_1): Same description as bit 0. 1 RW

GPI SMI Enable (GPI_SMI_EN_GPP_D_0): This bit is used to enable/disable the generation of SMI when the corresponding GPI_SMI_STS bit is set. The pad must also be routed for SMI functionality in order for SMI to be generated, i.e. the 0h corresponding GPIROUTSMI must be set to 1. 0 0 = disable SMI generation RW 1 = enable SMI generation Note: Each of the bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. E.g. if the PadCfgLock of pad0 is 1, bit0 of this bit is locked down to read-only.

7.2.39 SMI Enable (GPI_SMI_EN_GPP_E)—Offset 1A8h

Register bits in this register are implemented for GPP_E signals that have SMI capability only. Other bits are reserved and RO.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_SMI_EN_GPP_E_8 GPI_SMI_EN_GPP_E_7 GPI_SMI_EN_GPP_E_6 GPI_SMI_EN_GPP_E_5 GPI_SMI_EN_GPP_E_4 GPI_SMI_EN_GPP_E_3 GPI_SMI_EN_GPP_E_2 GPI_SMI_EN_GPP_E_1 GPI_SMI_EN_GPP_E_0

Bit Default & Field Name (ID): Description Range Access

0h 31:9 Reserved. RO

0h GPI SMI Enable (GPI_SMI_EN_GPP_E_8): Same description as bit 0. 8 RW

0h GPI SMI Enable (GPI_SMI_EN_GPP_E_7): Same description as bit 0. 7 RW

0h GPI SMI Enable (GPI_SMI_EN_GPP_E_6): Same description as bit 0. 6 RW

0h GPI SMI Enable (GPI_SMI_EN_GPP_E_5): Same description as bit 0. 5 RW

0h GPI SMI Enable (GPI_SMI_EN_GPP_E_4): Same description as bit 0. 4 RW

332219-002 605 GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h GPI SMI Enable (GPI_SMI_EN_GPP_E_3): Same description as bit 0. 3 RW

0h GPI SMI Enable (GPI_SMI_EN_GPP_E_2): Same description as bit 0. 2 RW

0h GPI SMI Enable (GPI_SMI_EN_GPP_E_1): Same description as bit 0. 1 RW

GPI SMI Enable (GPI_SMI_EN_GPP_E_0): This bit is used to enable/disable the generation of SMI when the corresponding GPI_SMI_STS bit is set. The pad must also be routed for SMI functionality in order for SMI to be generated, i.e. the 0h corresponding GPIROUTSMI must be set to 1. 0 0 = disable SMI generation RW 1 = enable SMI generation Note: Each of the bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. E.g. if the PadCfgLock of pad0 is 1, bit0 of this bit is locked down to read-only.

7.2.40 NMI Status (GPI_NMI_STS_GPP_C)—Offset 1C0h

Register bits in this register are implemented for GPP_C signals that have NMI capability only. Other bits are reserved and RO.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD GPI_NMI_STS_GPP_C_23 GPI_NMI_STS_GPP_C_22

606 332219-002

GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h GPI NMI Status (GPI_NMI_STS_GPP_C_23): Same description as bit 0. 23 RW1C

GPI NMI Status (GPI_NMI_STS_GPP_C_22): This bit is set to 1 by hardware when an edge event is detected (See RxEdCfg, RxInv) on pad and all the following conditions are true: - The corresponding pad is used in GPIO input mode (PMode) 0h - The corresponding GPIONMIRout is set to 1, i.e. programmed to route as NMI 22 - The corresponding GPIOOwn[2:0] is ‘000’ (i.e. ACPI GPIO Mode). RW1C - The corresponding GPI_NMI_EN is set Writing a value of 1 will clear the bit while writing a value of 0 has no effect. 0 = There is no NMI event 1 = There is an NMI event For pads which do not support NMI, the corresponding bit is read-only zero.

0h 21:0 Reserved. RO

7.2.41 NMI Status (GPI_NMI_STS_GPP_D)—Offset 1C4h

Register bits in this register are implemented for GPP_D signals that have NMI capability only. Other bits are reserved and RO.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_NMI_STS_GPP_D_4 GPI_NMI_STS_GPP_D_3 GPI_NMI_STS_GPP_D_2 GPI_NMI_STS_GPP_D_1 GPI_NMI_STS_GPP_D_0

Bit Default & Field Name (ID): Description Range Access

0h 31:5 Reserved. RO

0h GPI NMI Status (GPI_NMI_STS_GPP_D_4): Same description as bit 0. 4 RW1C

0h GPI NMI Status (GPI_NMI_STS_GPP_D_3): Same description as bit 0. 3 RW1C

332219-002 607 GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h GPI NMI Status (GPI_NMI_STS_GPP_D_2): Same description as bit 0. 2 RW1C

0h GPI NMI Status (GPI_NMI_STS_GPP_D_1): Same description as bit 0. 1 RW1C

GPI NMI Status (GPI_NMI_STS_GPP_D_0): This bit is set to 1 by hardware when an edge event is detected (See RxEdCfg, RxInv) on pad and all the following conditions are true: - The corresponding pad is used in GPIO input mode (PMode) 0h - The corresponding GPIONMIRout is set to 1, i.e. programmed to route as NMI 0 - The corresponding GPIOOwn[2:0] is ‘000’ (i.e. ACPI GPIO Mode). RW1C - The corresponding GPI_NMI_EN is set Writing a value of 1 will clear the bit while writing a value of 0 has no effect. 0 = There is no NMI event 1 = There is an NMI event For pads which do not support NMI, the corresponding bit is read-only zero.

7.2.42 NMI Status (GPI_NMI_STS_GPP_E)—Offset 1C8h

Register bits in this register are implemented for GPP_E signals that have NMI capability only. Other bits are reserved and RO.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_NMI_STS_GPP_E_8 GPI_NMI_STS_GPP_E_7 GPI_NMI_STS_GPP_E_6 GPI_NMI_STS_GPP_E_5 GPI_NMI_STS_GPP_E_4 GPI_NMI_STS_GPP_E_3 GPI_NMI_STS_GPP_E_2 GPI_NMI_STS_GPP_E_1 GPI_NMI_STS_GPP_E_0

Bit Default & Field Name (ID): Description Range Access

0h 31:9 Reserved. RO

0h GPI NMI Status (GPI_NMI_STS_GPP_E_8): Same description as bit 0. 8 RW1C

0h GPI NMI Status (GPI_NMI_STS_GPP_E_7): Same description as bit 0. 7 RW1C

0h GPI NMI Status (GPI_NMI_STS_GPP_E_6): Same description as bit 0. 6 RW1C

0h GPI NMI Status (GPI_NMI_STS_GPP_E_5): Same description as bit 0. 5 RW1C

608 332219-002

GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h GPI NMI Status (GPI_NMI_STS_GPP_E_4): Same description as bit 0. 4 RW1C

0h GPI NMI Status (GPI_NMI_STS_GPP_E_3): Same description as bit 0. 3 RW1C

0h GPI NMI Status (GPI_NMI_STS_GPP_E_2): Same description as bit 0. 2 RW1C

0h GPI NMI Status (GPI_NMI_STS_GPP_E_1): Same description as bit 0. 1 RW1C

GPI NMI Status (GPI_NMI_STS_GPP_E_0): This bit is set to 1 by hardware when an edge event is detected (See RxEdCfg, RxInv) on pad and all the following conditions are true: - The corresponding pad is used in GPIO input mode (PMode) 0h - The corresponding GPIONMIRout is set to 1, i.e. programmed to route as NMI 0 - The corresponding GPIOOwn[2:0] is ‘000’ (i.e. ACPI GPIO Mode). RW1C - The corresponding GPI_NMI_EN is set Writing a value of 1 will clear the bit while writing a value of 0 has no effect. 0 = There is no NMI event 1 = There is an NMI event For pads which do not support NMI, the corresponding bit is read-only zero.

7.2.43 NMI Enable (GPI_NMI_EN_GPP_C)—Offset 1E0h

Register bits in this register are implemented for GPP_C signals that have NMI capability only. Other bits are reserved and RO.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD GPI_NMI_EN_GPP_C_23 GPI_NMI_EN_GPP_C_22

332219-002 609 GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h GPI NMI Enable (GPI_NMI_EN_GPP_C_23): Same description as bit 22. 23 RW

GPI NMI Enable (GPI_NMI_EN_GPP_C_22): This bit is used to enable/disable the generation of NMI when the corresponding GPI_NMI_STS bit is set and its GPIROUTNMI is set.

0h 0 = disable NMI generation 22 1 = enable NMI generation RW Each bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. E.g. if the PadCfgLock of pad0 is ‘1’, bit0 of this bit is locked down to read-only. For pads which do not support NMI, the corresponding bit is read-only zero.

0h 21:0 Reserved. RO

7.2.44 NMI Enable (GPI_NMI_EN_GPP_D)—Offset 1E4h

Register bits in this register are implemented for GPP_D signals that have NMI capability only. Other bits are reserved and RO.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_NMI_EN_GPP_D_4 GPI_NMI_EN_GPP_D_3 GPI_NMI_EN_GPP_D_2 GPI_NMI_EN_GPP_D_1 GPI_NMI_EN_GPP_D_0

Bit Default & Field Name (ID): Description Range Access

0h 31:5 Reserved. RO

0h GPI NMI Enable (GPI_NMI_EN_GPP_D_4): Same description as bit 0. 4 RW

0h GPI NMI Enable (GPI_NMI_EN_GPP_D_3): Same description as bit 0. 3 RW

610 332219-002

GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h GPI NMI Enable (GPI_NMI_EN_GPP_D_2): Same description as bit 0. 2 RW

0h GPI NMI Enable (GPI_NMI_EN_GPP_D_1): Same description as bit 0. 1 RW

GPI NMI Enable (GPI_NMI_EN_GPP_D_0): This bit is used to enable/disable the generation of NMI when the corresponding GPI_NMI_STS bit is set and its GPIROUTNMI is set. 0h 0 = disable NMI generation 0 1 = enable NMI generation RW Each bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. E.g. if the PadCfgLock of pad0 is ‘1’, bit0 of this bit is locked down to read-only. For pads which do not support NMI, the corresponding bit is read-only zero.

7.2.45 NMI Enable (GPI_NMI_EN_GPP_E)—Offset 1E8h

Register bits in this register are implemented for GPP_E signals that have NMI capability only. Other bits are reserved and RO.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_NMI_EN_GPP_E_8 GPI_NMI_EN_GPP_E_7 GPI_NMI_EN_GPP_E_6 GPI_NMI_EN_GPP_E_5 GPI_NMI_EN_GPP_E_4 GPI_NMI_EN_GPP_E_3 GPI_NMI_EN_GPP_E_2 GPI_NMI_EN_GPP_E_1 GPI_NMI_EN_GPP_E_0

Bit Default & Field Name (ID): Description Range Access

0h 31:9 Reserved. RO

0h GPI NMI Enable (GPI_NMI_EN_GPP_E_8): Same description as bit 0. 8 RW

0h GPI NMI Enable (GPI_NMI_EN_GPP_E_7): Same description as bit 0. 7 RW

0h GPI NMI Enable (GPI_NMI_EN_GPP_E_6): Same description as bit 0. 6 RW

0h GPI NMI Enable (GPI_NMI_EN_GPP_E_5): Same description as bit 0. 5 RW

0h GPI NMI Enable (GPI_NMI_EN_GPP_E_4): Same description as bit 0. 4 RW

332219-002 611 GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h GPI NMI Enable (GPI_NMI_EN_GPP_E_3): Same description as bit 0. 3 RW

0h GPI NMI Enable (GPI_NMI_EN_GPP_E_2): Same description as bit 0. 2 RW

0h GPI NMI Enable (GPI_NMI_EN_GPP_E_1): Same description as bit 0. 1 RW

GPI NMI Enable (GPI_NMI_EN_GPP_E_0): This bit is used to enable/disable the generation of NMI when the corresponding GPI_NMI_STS bit is set and its GPIROUTNMI is set. 0h 0 = disable NMI generation 0 1 = enable NMI generation RW Each bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. E.g. if the PadCfgLock of pad0 is ‘1’, bit0 of this bit is locked down to read-only. For pads which do not support NMI, the corresponding bit is read-only zero.

7.2.46 PWM Control (PWMC)—Offset 204h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 EN SWUP BASEUNIT ONTIMEDIV

Bit Default & Field Name (ID): Description Range Access

0h Enable (EN): 0 = Disable PWM Output 31 RW 1 = Enable PWM Output

Software Update (SWUP): Indication that there is an update to PWM settings pending. SW sets this bit to 1 when updating the PWM_base_unit or 0h PWM_on_time_divisor fields. The PWM module will apply the new settings at the end 30 RW of the current cycle and reset this bit. 0 = No updates pending 1 = Update pending

0h Base Unit (BASEUNIT): Base Unit (BaseUnit) Base unit register. Unsigned 8 integer 29:8 bits, 14 fraction bits. Used to determine PWM output frequency. The PWM base RW frequency for SPT is 32.768 KHz.

0h On Time Divisor (ONTIMEDIV): PWM duty cycle = PWM_on-time_divisor/256 7:0 RW

7.2.47 GPIO Serial Blink Enable (GP_SER_BLINK)—Offset 20Ch

Access Method

612 332219-002

GPIO for SKL PCH-LP

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GP_SER_BLINK

Bit Default & Field Name (ID): Description Range Access

0h 31:5 Reserved. RO

GP SER BLINK (GP_SER_BLINK): The setting of this bit has no effect if the corresponding GPIO is programmed as an input, if the corresponding GPIO has the PWM enabled, or if Serial Blink capability does not exist. This bit should be set to a 1 before output buffer is enabled. When set to a ‘0’, the corresponding GPIO will function normally. This bit should be set to a 1 while the corresponding PMode bit is set to 0h (GPIO Mode). Setting the PMode bit to other value (non-GPIO Mode) after the GP_SER_BLINK bit ensures PCH will not drive a 1 on the pin as an output. When this corresponding bit is set to a 1 and the pin is configured to output mode, 0h the serial blink capability is enabled and the programmed message is serialized out 4:0 RW through an open-drain buffer configuration. The value of the corresponding GPIOTxState bit remains unchanged and does not impact the serial blink capability in any way. Writes to this register have no effect when the corresponding pin is configured in native mode and the read value returned is undefined. Bit0 = GPP_D0 Bit1 = GPP_D1 Bit2 = GPP_D2 Bit3 = GPP_D3 Bit4 = GPP_D4

7.2.48 GPIO Serial Blink Command/Status (GP_SER_CMDSTS)— Offset 210h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 GO DLS DRS BUSY RSVD RSVD RSVD

332219-002 613 GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

Data Length Select (DLS): This read/write field determines the number of bytes to serialize on GPIO 0h 00: Serialize bits 7:0 of GP_GB_DATA (1 byte) 23:22 01: Serialize bits 15:0 of GP_GB_DATA (2 bytes) RW 10: Undefined - Software must not write this value 11: Serialize bits 31:0 of GP_GB_DATA (4 bytes) Software should not modify the value in this register unless the Busy bit

Data Rate Select (DRS): Data Rate Select (DRS): This read/write field selects the 0h number of 333.34ns (4 clock periods 12MHz clock) time intervals to count between 21:16 Manchester data transitions. The default of 8h results in a 2666.67 ns minimum time RW between transitions. A value of 0h in this register produces undefined behavior. Software should not modify the value in this register unless the Busy bit is clear.

0h 15:9 Reserved. RO

0h Busy (BUSY): Busy: This read-only status bit is the hardware indication that a 8 serialization is in progress. Hardware sets this bit to 1 based on the Go bit being set. RO Hardware clears this bit when the Go bit is cleared by the hardware.

0h 7:1 Reserved. RO

Go (GO): Go: This bit is set to 1 by software to start the serialization process. 0h 0 Hardware clears the bit after the serialized data is sent. Writes of 0 to this register RW have no effect. Software should not write this bit to 1 unless the Busy status bit is cleared.

7.2.49 GPIO Serial Blink Data (GP_SER_DATA)—Offset 214h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 GP_GB_DATA

Bit Default & Field Name (ID): Description Range Access

GP Serial Blink Data (GP_GB_DATA): GP_GB_DATA This read-write register 0h contains the data serialized out. The number of bits shifted out is selected through 31:0 RW the DLS field in the GP_GB_CMDSTS register. This register should not be modified by software when the Busy bit is set.

7.2.50 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_0)— Offset 400h

Access Method

614 332219-002

GPIO for SKL PCH-LP

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 44000x00h

3 2 2 2 1 1 840 1 8 4 0 6 2

01000100000000000000001100000000 RSVD RSVD RSVD RSVD RXINV PMODE1 PMODE0 RXRAW1 RXEVCFG GPIOTXDIS GPIORXDIS PADRSTCFG RXTXENCFG GPIROUTSCI GPIROUTSMI RXPADSTSEL GPIROUTNMI GPIOTXSTATE GPIORXSTATE GPIROUTIOXAPIC

Bit Default & Field Name (ID): Description Range Access

Pad Reset Config (PADRSTCFG): This register controls which reset is used to reset GPIO pad register fields in PAD_CFG_DW0 and PAD_CFG_DW1 registers. This register can be used for Sx isolation of the associated signal if needed. 1h 00 = RSMRST# 31:30 01 = Host deep reset. This reset occurs when a host reset (with or without power RW cycle) is initiated or a global reset is initiated, except that the reset does not assert when in S3/S4/S5. 10 = PLTRST# 11 = Reserved

RX Pad State Select (RXPADSTSEL): Determines from which node the RX pad state for native function should be taken from. This field only affects the pad state 0h 29 value being fanned out to native function(s) and is not meaningful if the pad is in RW GPIO mode (i.e. Pad Mode = 0). 0 = Raw RX pad state directly from RX buffer 1 = Internal RX pad state (subject to RXINV and PreGfRXSel settings)

RX Raw Override to '1' (RXRAW1): This bit determines if the selected pad state is being overridden to '1'. This field is only applicable when the RX buffer is configured 0h as an input in either GPIO Mode or native function mode. The override takes place at 28 RW the internal pad state directly from buffer and before the RXINV. 0 = No Override 1 = RX drive 1 internally

0h 27 Reserved. RO

RX Level/Edge Configuration (RXEVCFG): Determines if the internal RX pad state (synchronized, filtered vs non-filtered version as determined by PreGfRXSel, and is further subject to RXInv) should be passed on to the next logic stage as is, as a pulse, or level signal. This field does not affect the received pad state (to 2h 26:25 GPIORXState or native functions) but how the interrupt or wake triggering events RW should be delivered to the GPIO Community Controller . 0h = Level 1h = Edge 2h = Drive '0' 3h = Reserved (implement as setting 0h)

0h 24 Reserved. RO

RX Invert (RXINV): This bit determines if the selected pad state should go through the polarity inversion stage. This field is only applicable when the RX buffer is configured as an input in either GPIO Mode or native function mode. The polarity inversion takes place at the mux node of raw vs filtered or non-filtered RX pad state,

0h as determined by PreGfRXsel and RXPadStSel This bit does not affect GPIORXState. 23 During host ownership GPIO Mode, when this bit is set to '1', then the RX pad state is RW inverted as it is sent to the GPIO-to-IOxAPIC, GPE/SCI, SMI, NMI logic or GPI_IS[n] that is using it. This is used to allow active-low and active-high inputs to cause IRQ, SMI#, SCI or NMI. 0 = No inversion 1 = Inversion

332219-002 615 GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

RX/TX Enable Config (RXTXENCFG): This controls the RX and TX buffer enables for the function selected by Pad Mode, but is not applicable when Pad Mode is 0 (i.e. GPIO mode). Hardware shall ensure GPIOTxDis and GPIORxDis are controlling the RX 0h 22:21 and TX buffers when this field is 0 and Pad Mode is 0. RO 00 = Function defined in Pad Mode controls TX and RX Enables 01 = Function controls TX Enable and RX Disabled with RX drive 0 internally 10 = Function controls TX Enable and RX Disabled with RX drive 1 internally 11 = Function controls TX Enabled and RX is always enabled

GPIO Input Route IOxAPIC (GPIROUTIOXAPIC): Determines if the pad can be routed to cause peripheral IRQ when configured in GPIO input mode. If the pad is not

0h configured in GPIO input mode, this field has no effect. 20 0 = Routing does not cause peripheral IRQ RW 1 = Routing can cause peripheral IRQ Note: This bit does not affect any interrupt status bit within GPIO, but is used as the last qualifier for the peripheral IRQ indication to the intended recipient(s).

GPIO Input Route SCI (GPIROUTSCI): Determines if the pad can be routed to cause SCI when configured in GPIO input mode. If the pad is not configured in GPIO 0h input mode, this field has no effect. 19 0 = Routing does not cause SCI. RW 1 = Routing can cause SCI Note: This bit does not affect any interrupt status bit within GPIO, but is used as the last qualifier for the GPE indication to the intended recipient(s).

GPIO Input Route SMI (GPIROUTSMI): Determines if the pad can be routed to cause SMI when configured in GPIO input mode. If the pad is not configured in GPIO input mode, this field has no effect. 0h 0 = Routing does not cause SMI. 18 RO 1 = Routing can cause SMI. Note: This bit does not affect any interrupt status bit within GPIO, but is used as the last qualifier for the SMI indication to the intended recipient(s). This bit only applies to a GPIO that has SMI capability. Otherwise, the bit is RO.

GPIO Input Route NMI (GPIROUTNMI): Determines if the pad can be routed to cause NMI when configured in GPIO input mode. If the pad is not configured in GPIO input mode, this field has no effect. 0 = Routing does not cause NMI. 0h 1 = Routing can cause NMI. 17 RO Note: This bit also affects GPI_NMI_STS. If '0', GPI_NMI_STS is always clear. If '1', GPI_NMI_STS could be set (depending on GPIOOwn setting) when there is an event. Whether a NMI indication is generated and sent to the intended recipient(s) is also depending on the corresponding GPI_NMI_EN bit. This bit only applies to a GPIO that has NMI capability. Otherwise, the bit is RO.

0h 16:12 Reserved. RO

-- Pad Mode bit 1 (PMODE1): See Pad Mode bit 0 description. 11 RW

Pad Mode bit 0 (PMODE0): This bit is used in conjunction with Pad Mode bit 1. This two-bit field determines whether the Pad is controlled by GPIO controller logic or one of the native functions muxed onto the Pad. 0h = GPIO control the Pad. 1h = native function 1, if applicable, controls the Pad -- 10 2h = native function 2, if applicable, controls the Pad. Also used to enable the GPIO RW blink (PWM) capability if applicable (note that not all GPIOs have the blink capability) 3h = native function 3, if applicable, controls the Pad Dedicated (unmuxed) GPIO shall report RO of all 0’s in this register field If GPIO vs. native mode is configured via soft strap, this bit has no effect.

Default value is determined by the default functionality of the pad.

GPIO RX Disable (GPIORXDIS): 0 = Enable the input buffer (active low enable) of 1h the pad. 9 1 = Disable the input buffer of the pad. RW Notes: When the input buffer is disabled, the internal pad state is always driven to '0'.

1h GPIO TX Disable (GPIOTXDIS): 0 = Enable the output buffer (active low enable) 8 of the pad. RW 1 = Disable the output buffer of the pad; i.e. Hi-Z

616 332219-002

GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h 7:2 Reserved. RO

0h GPIO RX State (GPIORXSTATE): This is the current internal RX pad state after 1 RO Glitch Filter logic stage and is not affected by PMode and RXINV settings.

0h GPIO TX State (GPIOTXSTATE): 0 = Drive a level '0' to the TX output pad. 0 RW 1 = Drive a level '1' to the TX output pad

7.2.51 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_0)— Offset 404h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 48h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000001001000 TERM RSVD RSVD INTSEL

Bit Default & Field Name (ID): Description Range Access

0h 31:14 Reserved. RO

Termination (TERM): The Pad Termination state defines the different weak pull-up and pull-down settings that are supported by the buffer. The settings for [13:10] correspond to: 0000: none 0010: 5k pd 0100: 20k pd 1000: none 1001: 1k pu 1011: 2k pu 0h 1010: 5k pu 13:10 1100: 20k pu RW 1101: 1k & 2k (in parallel) pu 1111: Native controller selected by Pad Mode controls the Termination All others reserved. If a reserved value is programmed, pad may malfunction. The setting of this field is applicable in all Pad Mode including GPIO. As each Pad Mode may require different termination and isolation, care must be taken in sw/fw in the transition with appropriate register programming. The actual transition sequence requirement may vary on case by case basis depending on the native functions involved. For example, before changing the pad from output to input direction, pu/pd settings should be programmed first to ensure the input does not float momentarily.

0h 9:8 Reserved. RO

Interrupt Select (INTSEL): The Interrupt Select defines which interrupt line driven from the GPIO Controller toggles when an interrupt is detected on this pad. 48h 0 = Interrupt Line 0 7:0 RO 1 = Interrupt Line 1 .... Up to the max IOxAPIC IRQ supported

332219-002 617 GPIO for SKL PCH-LP

7.2.52 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_1)— Offset 408h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.53 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_1)— Offset 40Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 49h

7.2.54 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_2)— Offset 410h

Same description as PAD_CFG_DW0_GPP_C_0

7.2.55 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_2)— Offset 414h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 4Ah

7.2.56 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_3)— Offset 418h

Same description as PAD_CFG_DW0_GPP_C_0

7.2.57 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_3)— Offset 41Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 4Bh

7.2.58 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_4)— Offset 420h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.59 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_4)— Offset 424h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 4Ch

7.2.60 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_5)— Offset 428h

Same description as PAD_CFG_DW0_GPP_C_0.

618 332219-002

GPIO for SKL PCH-LP

7.2.61 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_5)— Offset 42Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 4Dh

7.2.62 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_6)— Offset 430h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.63 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_6)— Offset 434h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 4Eh

7.2.64 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_7)— Offset 438h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.65 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_7)— Offset 43Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 4Fh

7.2.66 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_8)— Offset 440h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.67 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_8)— Offset 444h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 50h

7.2.68 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_9)— Offset 448h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.69 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_9)— Offset 44Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 51h

332219-002 619 GPIO for SKL PCH-LP

7.2.70 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_10)— Offset 450h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.71 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_10)— Offset 454h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 52h

7.2.72 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_11)— Offset 458h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.73 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_11)— Offset 45Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 53h

7.2.74 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_12)— Offset 460h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.75 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_12)— Offset 464h

Exception: The default value of the INTSEL bit field in this register is : 54h

7.2.76 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_13)— Offset 468h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.77 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_13)— Offset 46Ch

Exception: The default value of the INTSEL bit field in this register is : 55h

7.2.78 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_14)— Offset 470h

Same description as PAD_CFG_DW0_GPP_C_0.

620 332219-002

GPIO for SKL PCH-LP

7.2.79 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_14)— Offset 474h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 56h

7.2.80 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_15)— Offset 478h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.81 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_15)— Offset 47Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 57h

7.2.82 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_16)— Offset 480h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.83 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_16)— Offset 484h

Note that this register definition also applies to GPP_C[19:17], GPP_D[8:5], and GPP_D[14:13].

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 58h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000001011000 TERM RSVD RSVD RSVD INTSEL CFIOPADCFG_PADTOL

332219-002 621 GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h 31:26 Reserved. RO

0h Pad Voltage Tolerance (CFIOPADCFG_PADTOL): 0 = pad is 3.3V tolerance 25 (VccIO is 3.3V) RW 1 = pad is 1.8V tolerance (VccIO is 3.3V).

0h 24:14 Reserved. RO

Termination (TERM): The Pad Termination state defines the different weak pull-up and pull-down settings that are supported by the buffer. The settings for [13:10] correspond to: 0000: none 0010: 5k pd 0100: 20k pd 1000: none 1001: 1k pu 1011: 2k pu 0h 1010: 5k pu 13:10 RW 1100: 20k pu 1101: 1k & 2k (in parallel) pu All others reserved. If a reserved value is programmed, pad may malfunction. The setting of this field is applicable in all Pad Mode including GPIO. As each Pad Mode may require different termination and isolation, care must be taken in sw/fw in the transition with appropriate register programming. The actual transition sequence requirement may vary on case by case basis depending on the native functions involved. For example, before changing the pad from output to input direction, pu/pd settings should be programmed first to ensure the input does not float momentarily.

0h 9:8 Reserved. RO

Interrupt Select (INTSEL): The Interrupt Select defines which interrupt line driven from the GPIO Controller toggles when an interrupt is detected on this pad. 58h 0 = Interrupt Line 0 7:0 RO 1 = Interrupt Line 1 .... Up to the max IOxAPIC IRQ supported

7.2.84 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_17)— Offset 488h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.85 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_17)— Offset 48Ch

Same description as PAD_CFG_DW1_GPP_C_16 Exception: The default value of the INTSEL bit field in this register is : 59h

7.2.86 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_18)— Offset 490h

Same description as PAD_CFG_DW1_GPP_C_16

7.2.87 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_18)— Offset 494h

Same description as PAD_CFG_DW1_GPP_C_16 Exception: The default value of the INTSEL bit field in this register is : 5Ah

622 332219-002

GPIO for SKL PCH-LP

7.2.88 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_19)— Offset 498h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.89 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_19)— Offset 49Ch

Same description as PAD_CFG_DW1_GPP_C_16 Exception: The default value of the INTSEL bit field in this register is : 5Bh

7.2.90 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_20)— Offset 4A0h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.91 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_20)— Offset 4A4h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 5Ch

7.2.92 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_21)— Offset 4A8h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.93 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_21)— Offset 4ACh

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 5Dh

7.2.94 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_22)— Offset 4B0h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.95 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_22)— Offset 4B4h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 5Eh

7.2.96 Pad Configuration DW0 (PAD_CFG_DW0_GPP_C_23)— Offset 4B8h

Same description as PAD_CFG_DW0_GPP_C_0.

332219-002 623 GPIO for SKL PCH-LP

7.2.97 Pad Configuration DW1 (PAD_CFG_DW1_GPP_C_23)— Offset 4BCh

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 5Fh

7.2.98 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_0)— Offset 4C0h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.99 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_0)— Offset 4C4h

Same description as PAD_CFG_DW1_GPP_C_0

7.2.100 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_1)— Offset 4C8h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.101 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_1)— Offset 4CCh

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 61h

7.2.102 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_2)— Offset 4D0h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.103 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_2)— Offset 4D4h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 62h

7.2.104 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_3)— Offset 4D8h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.105 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_3)— Offset 4DCh

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 63h

624 332219-002

GPIO for SKL PCH-LP

7.2.106 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_4)— Offset 4E0h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.107 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_4)— Offset 4E4h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 64h

7.2.108 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_5)— Offset 4E8h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.109 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_5)— Offset 4ECh

Same description as PAD_CFG_DW1_GPP_C_16 Exception: The default value of the INTSEL bit field in this register is : 65h

7.2.110 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_6)— Offset 4F0h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.111 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_6)— Offset 4F4h

Same description as PAD_CFG_DW1_GPP_C_16 Exception: The default value of the INTSEL bit field in this register is : 66h

7.2.112 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_7)— Offset 4F8h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.113 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_7)— Offset 4FCh

Same description as PAD_CFG_DW1_GPP_C_16 Exception: The default value of the INTSEL bit field in this register is : 67h

7.2.114 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_8)— Offset 504h

Same description as PAD_CFG_DW1_GPP_C_16 Exception: The default value of the INTSEL bit field in this register is : 68h

332219-002 625 GPIO for SKL PCH-LP

7.2.115 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_9)— Offset 508h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.116 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_9)— Offset 50Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 69h

7.2.117 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_10)— Offset 510h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.118 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_10)— Offset 514h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 6Ah

7.2.119 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_11)— Offset 518h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.120 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_11)— Offset 51Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 6Bh

7.2.121 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_12)— Offset 520h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.122 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_12)— Offset 524h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 6Ch

7.2.123 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_13)— Offset 528h

Same description as PAD_CFG_DW0_GPP_C_0.

626 332219-002

GPIO for SKL PCH-LP

7.2.124 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_13)— Offset 52Ch

Same description as PAD_CFG_DW1_GPP_C_16 Exception: The default value of the INTSEL bit field in this register is : 6Dh

7.2.125 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_14)— Offset 530h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.126 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_14)— Offset 534h

Same description as PAD_CFG_DW1_GPP_C_16 Exception: The default value of the INTSEL bit field in this register is : 6Eh

7.2.127 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_15)— Offset 538h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.128 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_15)— Offset 53Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 6Fh

7.2.129 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_16)— Offset 540h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.130 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_16)— Offset 544h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 70h

7.2.131 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_17)— Offset 548h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.132 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_17)— Offset 54Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 71h

332219-002 627 GPIO for SKL PCH-LP

7.2.133 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_18)— Offset 550h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.134 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_18)— Offset 554h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 72h

7.2.135 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_19)— Offset 558h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.136 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_19)— Offset 55Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 73h

7.2.137 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_20)— Offset 560h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.138 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_20)— Offset 564h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 74h

7.2.139 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_21)— Offset 568h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.140 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_21)— Offset 56Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 75h

7.2.141 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_22)— Offset 570h

Same description as PAD_CFG_DW0_GPP_C_0.

628 332219-002

GPIO for SKL PCH-LP

7.2.142 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_22)— Offset 574h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 76h

7.2.143 Pad Configuration DW0 (PAD_CFG_DW0_GPP_D_23)— Offset 578h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.144 Pad Configuration DW1 (PAD_CFG_DW1_GPP_D_23)— Offset 57Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 77h

7.2.145 Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_0)— Offset 580h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.146 Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_0)— Offset 584h

Same description as PAD_CFG_DW1_GPP_C_0

7.2.147 Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_1)— Offset 588h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.148 Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_1)— Offset 58Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 19h

7.2.149 Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_2)— Offset 590h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.150 Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_2)— Offset 594h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 1Ah

332219-002 629 GPIO for SKL PCH-LP

7.2.151 Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_3)— Offset 598h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.152 Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_3)— Offset 59Ch

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 1Bh

7.2.153 Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_4)— Offset 5A0h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.154 Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_4)— Offset 5A4h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 1Ch

7.2.155 Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_5)— Offset 5A8h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.156 Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_5)— Offset 5ACh

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 1Dh

7.2.157 Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_6)— Offset 5B0h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.158 Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_6)— Offset 5B4h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 1Eh

7.2.159 Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_7)— Offset 5B8h

Same description as PAD_CFG_DW0_GPP_C_0.

630 332219-002

GPIO for SKL PCH-LP

7.2.160 Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_7)— Offset 5BCh

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 1Fh

7.2.161 Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_8)— Offset 5C0h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.162 Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_8)— Offset 5C4h

Same description as PAD_CFG_DW1_GPP_C_0 Exception: The default value of the INTSEL bit field in this register is : 20h

7.2.163 Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_9)— Offset 5C8h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.164 Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_9)— Offset 5CCh

Same description as PAD_CFG_DW0_GPP_C_0. Exception: The default value of the INTSEL bit field in this register is : 21h

7.2.165 Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_10)— Offset 5D0h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.166 Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_10)— Offset 5D4h

Same description as PAD_CFG_DW0_GPP_C_0. Exception: The default value of the INTSEL bit field in this register is : 22h

7.2.167 Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_11)— Offset 5D8h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.168 Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_11)— Offset 5DCh

Same description as PAD_CFG_DW0_GPP_C_0. Exception: The default value of the INTSEL bit field in this register is : 23h

332219-002 631 GPIO for SKL PCH-LP

7.2.169 Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_12)— Offset 5E0h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.170 Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_12)— Offset 5E4h

Same description as PAD_CFG_DW0_GPP_C_0. Exception: The default value of the INTSEL bit field in this register is : 24h

7.2.171 Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_13)— Offset 5E8h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.172 Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_13)— Offset 5ECh

Same description as PAD_CFG_DW0_GPP_C_0. Exception: The default value of the INTSEL bit field in this register is : 25h

7.2.173 Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_14)— Offset 5F0h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.174 Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_14)— Offset 5F4h

Same description as PAD_CFG_DW0_GPP_C_0. Exception: The default value of the INTSEL bit field in this register is : 26h

7.2.175 Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_15)— Offset 5F8h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.176 Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_15)— Offset 5FCh

Same description as PAD_CFG_DW0_GPP_C_0. Exception: The default value of the INTSEL bit field in this register is : 27h

7.2.177 Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_16)— Offset 600h

Same description as PAD_CFG_DW0_GPP_C_0.

632 332219-002

GPIO for SKL PCH-LP

7.2.178 Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_16)— Offset 604h

Same description as PAD_CFG_DW0_GPP_C_0. Exception: The default value of the INTSEL bit field in this register is : 28h

7.2.179 Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_17)— Offset 608h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.180 Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_17)— Offset 60Ch

Same description as PAD_CFG_DW0_GPP_C_0. Exception: The default value of the INTSEL bit field in this register is : 29h

7.2.181 Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_18)— Offset 610h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.182 Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_18)— Offset 614h

Same description as PAD_CFG_DW0_GPP_C_0. Exception: The default value of the INTSEL bit field in this register is : 2Ah

7.2.183 Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_19)— Offset 618h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.184 Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_19)— Offset 61Ch

Same description as PAD_CFG_DW0_GPP_C_0. Exception: The default value of the INTSEL bit field in this register is : 2Bh

7.2.185 Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_20)— Offset 620h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.186 Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_20)— Offset 624h

Same description as PAD_CFG_DW0_GPP_C_0. Exception: The default value of the INTSEL bit field in this register is : 2Ch

332219-002 633 GPIO for SKL PCH-LP

7.2.187 Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_21)— Offset 628h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.188 Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_21)— Offset 62Ch

Same description as PAD_CFG_DW0_GPP_C_0. Exception: The default value of the INTSEL bit field in this register is : 2Dh

7.2.189 Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_22)— Offset 630h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.190 Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_22)— Offset 634h

Same description as PAD_CFG_DW0_GPP_C_0. Exception: The default value of the INTSEL bit field in this register is : 2Eh

7.2.191 Pad Configuration DW0 (PAD_CFG_DW0_GPP_E_23)— Offset 638h

Same description as PAD_CFG_DW0_GPP_C_0.

7.2.192 Pad Configuration DW1 (PAD_CFG_DW1_GPP_E_23)— Offset 63Ch

Same description as PAD_CFG_DW0_GPP_C_0. Exception: The default value of the INTSEL bit field in this register is : 2Fh

7.3 GPIO Community 2 Registers Summary

Community 2 Registers are for GPP_DSW group.

Table 7-3. Summary of GPIO Community 2 Registers

Offset Offset Default Register Name (ID)—Offset Start End Value

8h Bh Family Base Address (FAMBAR)—Offset 8h 300h

Ch Fh Pad Base Address (PADBAR)—Offset Ch 400h

10h 13h Miscellaneous Configuration (MISCCFG)—Offset 10h 43200h

20h 23h Pad Ownership (PAD_OWN_GPD_0)—Offset 20h 0h

24h 27h Pad Ownership (PAD_OWN_GPD_1)—Offset 24h 0h

A0h A3h Pad Configuration Lock (PADCFGLOCK_GPD_0)—Offset A0h 0h

A4h A7h Pad Configuration Lock (PADCFGLOCKTX_GPD_0)—Offset A4h 0h

D0h D3h Host Software Pad Ownership (HOSTSW_OWN_GPD_0)—Offset D0h 0h

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Table 7-3. Summary of GPIO Community 2 Registers (Continued)

Offset Offset Default Register Name (ID)—Offset Start End Value

100h 103h GPI Interrupt Status (GPI_IS_GPD_0)—Offset 100h 0h

120h 123h GPI Interrupt Enable (GPI_IE_GPD_0)—Offset 120h 0h

GPI General Purpose Events Status (GPI_GPE_STS_GPD_0)—Offset 140h 143h 0h 140h

160h 163h GPI General Purpose Events Enable (GPI_GPE_EN_GPD_0)—Offset 160h 0h

4000x00h 400h 403h Pad Configuration DW0 (PAD_CFG_DW0_GPD_0)—Offset 400h See register for xx value

404h 407h Pad Configuration DW1 (PAD_CFG_DW1_GPD_0)—Offset 404h 50h

4000x00h 408h 40Bh Pad Configuration DW0 (PAD_CFG_DW0_GPD_1)—Offset 408h See register for xx value

40Ch 40Fh Pad Configuration DW1 (PAD_CFG_DW1_GPD_1)—Offset 40Ch See register

4000x00h 410h 413h Pad Configuration DW0 (PAD_CFG_DW0_GPD_2)—Offset 410h See register for xx value

414h 417h Pad Configuration DW1 (PAD_CFG_DW1_GPD_2)—Offset 414h See register

4000x00h 418h 41Bh Pad Configuration DW0 (PAD_CFG_DW0_GPD_3)—Offset 418h See register for xx value

41Ch 41Fh Pad Configuration DW1 (PAD_CFG_DW1_GPD_3)—Offset 41Ch See register

4000x00h 420h 423h Pad Configuration DW0 (PAD_CFG_DW0_GPD_4)—Offset 420h See register for xx value

424h 427h Pad Configuration DW1 (PAD_CFG_DW1_GPD_4)—Offset 424h See register

4000x00h 428h 42Bh Pad Configuration DW0 (PAD_CFG_DW0_GPD_5)—Offset 428h See register for xx value

42Ch 42Fh Pad Configuration DW1 (PAD_CFG_DW1_GPD_5)—Offset 42Ch See register

4000x00h 430h 433h Pad Configuration DW0 (PAD_CFG_DW0_GPD_6)—Offset 430h See register for xx value

434h 437h Pad Configuration DW1 (PAD_CFG_DW1_GPD_6)—Offset 434h See register

4000x00h 438h 43Bh Pad Configuration DW0 (PAD_CFG_DW0_GPD_7)—Offset 438h See register for xx value

43Ch 43Fh Pad Configuration DW1 (PAD_CFG_DW1_GPD_7)—Offset 43Ch See register

4000x00h 440h 443h Pad Configuration DW0 (PAD_CFG_DW0_GPD_8)—Offset 440h See register for xx value

444h 447h Pad Configuration DW1 (PAD_CFG_DW1_GPD_8)—Offset 444h See register

4000x00h 448h 44Bh Pad Configuration DW0 (PAD_CFG_DW0_GPD_9)—Offset 448h See register for xx value

44Ch 44Fh Pad Configuration DW1 (PAD_CFG_DW1_GPD_9)—Offset 44Ch See register

4000x00h 450h 453h Pad Configuration DW0 (PAD_CFG_DW0_GPD_10)—Offset 450h See register for xx value

332219-002 635 GPIO for SKL PCH-LP

Table 7-3. Summary of GPIO Community 2 Registers (Continued)

Offset Offset Default Register Name (ID)—Offset Start End Value

454h 457h Pad Configuration DW1 (PAD_CFG_DW1_GPD_10)—Offset 454h See register

4000x00h 458h 45Bh Pad Configuration DW0 (PAD_CFG_DW0_GPD_11)—Offset 458h See register for xx value

45Ch 45Fh Pad Configuration DW1 (PAD_CFG_DW1_GPD_11)—Offset 45Ch See register

7.3.1 Family Base Address (FAMBAR)—Offset 8h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 300h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000001100000000 RSVD FAMBAR

Bit Default & Field Name (ID): Description Range Access

0h 31:16 Reserved. RO

Family Base Address (FAMBAR): This field provides the starting byte-align 300h address of Family0 register sets. It is meant for software to discover from where the 15:0 RO very first Family register (i.e. Family0 register) starts to compute the next Families address offsets.

7.3.2 Pad Base Address (PADBAR)—Offset Ch

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 400h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000010000000000 RSVD PADBAR

636 332219-002

GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h 31:16 Reserved. RO

400h Pad Base Address (PADBAR): This field provides the starting byte-align address of 15:0 Pad0 register sets. It is meant for software to discover from where the very first Pad RO register (i.e. Pad0 register) starts to compute the next Pad address offsets.

7.3.3 Miscellaneous Configuration (MISCCFG)—Offset 10h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 43200h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000001000011001000000000 RSVD RSVD RSVD GPDLCGEN GPDPCGEN GPE0_DW2 GPE0_DW1 GPE0_DW0 GPIO_DRIVER_IRQ_ROUTE

Bit Default & Field Name (ID): Description Range Access

0h 31:20 Reserved. RO

GPIO Group to GPE_DW0 assignment encoding (GPE0_DW2): This register assigns a specific GPIO Group to the ACPI GPE0[95:64]. The selected GPIO group will be mapped to lower bits of the GPE register 0h = GPP_A[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 4h 1h = GPP_B[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 19:16 2h = GPP_C[23:0] mapped to GPE[87:64]; GPE[95:88] not used. RW 3h = GPP_D[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 4h = GPP_E[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 5h = GPP_F[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 6h = GPP_G[7:0] mapped to GPE[51:64]; GPE[95:52] not used. 7h = GPD[11:0] mapped to GPE[75:64]; GPE[95:76] not used.

GPIO Group to GPE_DW0 assignment encoding (GPE0_DW1): This register assigns a specific GPIO Group to the ACPI GPE0[63:32]. The selected GPIO group will be mapped to lower bits of the GPE register 0h = GPP_A[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 3h 1h = GPP_B[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 15:12 2h = GPP_C[23:0] mapped to GPE[55:32]; GPE[63:56] not used. RW 3h = GPP_D[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 4h = GPP_E[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 5h = GPP_F[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 6h = GPP_G[7:0] mapped to GPE[39:32]; GPE[63:40] not used. 7h = GPD[11:0] mapped to GPE[43:32]; GPE[63:44] not used.

332219-002 637 GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

GPIO Group to GPE_DW0 assignment encoding (GPE0_DW0): This register assigns a specific GPIO Group to the ACPI GPE0[31:0]. The selected GPIO group will be mapped to lower bits of the GPE register 0h = GPP_A[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 2h 1h = GPP_B[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 11:8 2h = GPP_C[23:0] mapped to GPE[23:0]; GPE[31:24] not used. RW 3h = GPP_D[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 4h = GPP_E[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 5h = GPP_F[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 6h = GPP_G[7:0] mapped to GPE[7:0]; GPE[31:8] not used. 7h = GPD[11:0] mapped to GPE[11:0]; GPE[31:12] not used.

0h 7:4 Reserved. RO

GPIO Driver IRQ Route (GPIO_DRIVER_IRQ_ROUTE): GPIO Driver 0h IRQ_ROUTE[1:0]: Specifies the APIC IRQ globally for all pads within the current 3 community (GPI_IS with corresponding GPI_IE enable). RW 0 = IRQ14 1 = IRQ15

0h 2 Reserved. RO

GPIO Dynamic Partition Clock Gating Enable (GPDPCGEN): Specifies whether 0h the GPIO Community should take part in partition clock gating 1 RW 0 = Disable participation in dynamic partition clock gating 1 = Enable participation in dynamic partition clock gating.

GPIO Dynamic Local Clock Gating Enable (GPDLCGEN): Specifies whether the 0h 0 GPIO Community should perform local clock gating. RW 0 = Disable dynamic local clock gating 1 = Enable dynamic local clock gating

7.3.4 Pad Ownership (PAD_OWN_GPD_0)—Offset 20h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD PAD_OWN_GPD_7 PAD_OWN_GPD_6 PAD_OWN_GPD_5 PAD_OWN_GPD_4 PAD_OWN_GPD_3 PAD_OWN_GPD_2 PAD_OWN_GPD_1 PAD_OWN_GPD_0

Bit Default & Field Name (ID): Description Range Access

0h 31:30 Reserved. RO

0h Pad Ownership (PAD_OWN_GPD_7): Same description as bit 0, except that the 29:28 RO bit field applies to GPD_7.

0h 27:26 Reserved. RO

638 332219-002

GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h Pad Ownership (PAD_OWN_GPD_6): Same description as bit 0, except that the 25:24 RO bit field applies to GPD_6.

0h 23:22 Reserved. RO

0h Pad Ownership (PAD_OWN_GPD_5): Same description as bit 0, except that the 21:20 RO bit field applies to GPD_5.

0h 19:18 Reserved. RO

0h Pad Ownership (PAD_OWN_GPD_4): Same description as bit 0, except that the 17:16 RO bit field applies to GPD_4.

0h 15:14 Reserved. RO

0h Pad Ownership (PAD_OWN_GPD_3): Same description as bit 0, except that the 13:12 RO bit field applies to GPD_3.

0h 11:10 Reserved. RO

0h Pad Ownership (PAD_OWN_GPD_2): Same description as bit 0, except that the 9:8 RO bit field applies to GPD_2.

0h 7:6 Reserved. RO

0h Pad Ownership (PAD_OWN_GPD_1): Same description as bit 0, except that the 5:4 RO bit field applies to GPD_1.

0h 3:2 Reserved. RO

Pad Ownership (PAD_OWN_GPD_0): 00 = Host GPIO ACPI Mode or GPIO Driver Mode. Host software (ACPI or GPIO Driver) has ownership of the pad. In Host GPIO Driver Mode (refer to HOSTSW_OWN), GPIO input event update is limited to GPI_STS 0h 1:0 update only. Otherwise in Host ACPI Mode, updates are limited to GPI_GPE_STS, RO GPI_NMI_STS and/or GPI_SMI_STS. 01 = ME GPIO Mode. ME has ownership of the pad. 10 = ISH GPIO Mode.ME has ownership of the pad 11 = Reserved

7.3.5 Pad Ownership (PAD_OWN_GPD_1)—Offset 24h

Same description as PAD_OWN_GPP_GPD_0, except that this register is for GPD[11:8]

7.3.6 Pad Configuration Lock (PADCFGLOCK_GPD_0)—Offset A0h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

332219-002 639 GPIO for SKL PCH-LP

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD PADCFGLOCK_GPD_9 PADCFGLOCK_GPD_8 PADCFGLOCK_GPD_7 PADCFGLOCK_GPD_6 PADCFGLOCK_GPD_5 PADCFGLOCK_GPD_4 PADCFGLOCK_GPD_3 PADCFGLOCK_GPD_2 PADCFGLOCK_GPD_1 PADCFGLOCK_GPD_0 PADCFGLOCK_GPD_11 PADCFGLOCK_GPD_10

Bit Default & Field Name (ID): Description Range Access

0h 31:12 Reserved. RO

0h Pad Config Lock (PADCFGLOCK_GPD_11): Applied to GPD_11. Same description 11 RW as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPD_10): Applied to GPD_2. Same description 10 RW as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPD_9): Applied to GPD_2. Same description as 9 RW bit 0.

0h Pad Config Lock (PADCFGLOCK_GPD_8): Applied to GPD_8. Same description as 8 RW bit 0.

0h Pad Config Lock (PADCFGLOCK_GPD_7): Applied to GPD_7. Same description as 7 RW bit 0.

0h Pad Config Lock (PADCFGLOCK_GPD_6): Applied to GPD_6. Same description as 6 RW bit 0.

0h Pad Config Lock (PADCFGLOCK_GPD_5): Applied to GPD_5. Same description as 5 RW bit 0.

0h Pad Config Lock (PADCFGLOCK_GPD_4): Applied to GPD_4. Same description as 4 RW bit 0.

0h Pad Config Lock (PADCFGLOCK_GPD_3): Applied to GPD_3. Same description as 3 RW bit 0.

0h Pad Config Lock (PADCFGLOCK_GPD_2): Applied to GPD_2. Same description as 2 RW bit 0.

0h Pad Config Lock (PADCFGLOCK_GPD_1): Applied to GPD_2. Same description as 1 RW bit 0.

Pad Config Lock (PADCFGLOCK_GPD_0): Pad Configuration Lock locks specific register fields in the GPP specific registers from being configured. The registers affected become Read-Only and software writes to these registers have no effect. 0 = Unlock 1 = Lock the following register fields as read-only (RO): 0h 0 - Pad Configuration registers (exclude GPIOTXState) RW - GPI_NMI_EN Register (if implemented) - GPI_SMI_EN Register (if implemented) - GPI_GPE_EN Register (if implemented) When PadCfgLock is written from a '1' to a '0' (unlock), a synchronous SMI# is generated if enabled. This ensures that only SMM code can change the above GPIO registers after the lockdown.

7.3.7 Pad Configuration Lock (PADCFGLOCKTX_GPD_0)—Offset A4h

Access Method

640 332219-002

GPIO for SKL PCH-LP

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD PADCFGLOCKTX_GPD_9 PADCFGLOCKTX_GPD_8 PADCFGLOCKTX_GPD_7 PADCFGLOCKTX_GPD_6 PADCFGLOCKTX_GPD_5 PADCFGLOCKTX_GPD_4 PADCFGLOCKTX_GPD_3 PADCFGLOCKTX_GPD_2 PADCFGLOCKTX_GPD_1 PADCFGLOCKTX_GPD_0 PADCFGLOCKTX_GPD_11 PADCFGLOCKTX_GPD_10

Bit Default & Field Name (ID): Description Range Access

0h 31:12 Reserved. RO

0h Pad Config Lock TXState (PADCFGLOCKTX_GPD_11): Applied to GPD_11. Same 11 RW description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPD_10): Applied to GPD_10. Same 10 RW description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPD_9): Applied to GPD_9. Same 9 RW description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPD_8): Applied to GPD_8. Same 8 RW description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPD_7): Applied to GPD_7. Same 7 RW description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPD_6): Applied to GPD_6. Same 6 RW description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPD_5): Applied to GPD_5. Same 5 RW description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPD_4): Applied to GPD_4. Same 4 RW description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPD_3): Applied to GPD_3. Same 3 RW description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPD_2): Applied to GPD_2. Same 2 RW description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPD_1): Applied to GPD_1. Same 1 RW description as bit 0.

Pad Config Lock TXState (PADCFGLOCKTX_GPD_0): PadCfgLockTx locks the GPIOTxState bit from being configured. The GPIOTxState register becomes Read- Only and software writes to the register have no effect. 0h 0 = Unlock 0 RW 1 = Locks the Pad Configuration GPIOTXState field as read-only (RO) When PadCfgLockTx is written from a '1' to a '0' (unlock), a synchronous SMI# is generated if enabled. This ensures that only SMM code can change the above GPIO registers after the lockdown.

332219-002 641 GPIO for SKL PCH-LP

7.3.8 Host Software Pad Ownership (HOSTSW_OWN_GPD_0)— Offset D0h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD HOSTSW_OWN_GPD_9 HOSTSW_OWN_GPD_8 HOSTSW_OWN_GPD_7 HOSTSW_OWN_GPD_6 HOSTSW_OWN_GPD_5 HOSTSW_OWN_GPD_4 HOSTSW_OWN_GPD_3 HOSTSW_OWN_GPD_2 HOSTSW_OWN_GPD_1 HOSTSW_OWN_GPD_0 HOSTSW_OWN_GPD_11 HOSTSW_OWN_GPD_10

Bit Default & Field Name (ID): Description Range Access

0h 31:12 Reserved. RO

0h HostSW_Own (HOSTSW_OWN_GPD_11): Applied to GPD_11. Same description 11 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPD_10): Applied to GPD_10. Same description 10 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPD_9): Applied to GPD_9. Same description as 9 RW bit 0.

0h HostSW_Own (HOSTSW_OWN_GPD_8): Applied to GPD_8. Same description as 8 RW bit 0.

0h HostSW_Own (HOSTSW_OWN_GPD_7): Applied to GPD_7. Same description as 7 RW bit 0.

0h HostSW_Own (HOSTSW_OWN_GPD_6): Applied to GPD_6. Same description as 6 RW bit 0.

0h HostSW_Own (HOSTSW_OWN_GPD_5): Applied to GPD_5. Same description as 5 RW bit 0.

0h HostSW_Own (HOSTSW_OWN_GPD_4): Applied to GPD_4. Same description as 4 RW bit 0.

0h HostSW_Own (HOSTSW_OWN_GPD_3): Applied to GPD_3. Same description as 3 RW bit 0.

642 332219-002

GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h HostSW_Own (HOSTSW_OWN_GPD_2): Applied to GPD_2. Same description as 2 RW bit 0.

0h HostSW_Own (HOSTSW_OWN_GPD_1): Applied to GPD_1. Same description as 1 RW bit 0.

HostSW_Own (HOSTSW_OWN_GPD_0): This register determines the appropriate host status bit update when a pad is under host ownership. 0h 0 = ACPI Mode. GPIO input event updates are limited to GPI_GPE_STS, 0 RW GPI_NMI_STS and/or GPI_SMI_STS. GPI_STS update is masked. 1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked.

7.3.9 GPI Interrupt Status (GPI_IS_GPD_0)—Offset 100h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_INT_STS_GPD_9 GPI_INT_STS_GPD_8 GPI_INT_STS_GPD_7 GPI_INT_STS_GPD_6 GPI_INT_STS_GPD_5 GPI_INT_STS_GPD_4 GPI_INT_STS_GPD_3 GPI_INT_STS_GPD_2 GPI_INT_STS_GPD_1 GPI_INT_STS_GPD_0 GPI_INT_STS_GPD_11 GPI_INT_STS_GPD_10

Bit Default & Field Name (ID): Description Range Access

0h 31:12 Reserved. RO

0h GPI Interrupt Status (GPI_INT_STS_GPD_11): Applied to GPD_11. Same 11 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPD_10): Applied to GPD_10. Same 10 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPD_9): Applied to GPD_9. Same 9 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPD_8): Applied to GPD_8. Same 8 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPD_7): Applied to GPD_7. Same 7 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPD_6): Applied to GPD_6. Same 6 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPD_5): Applied to GPD_5. Same 5 RW1C description as bit 0.

332219-002 643 GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h GPI Interrupt Status (GPI_INT_STS_GPD_4): Applied to GPD_4. Same 4 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPD_3): Applied to GPD_3. Same 3 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPD_2): Applied to GPD_2. Same 2 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPD_1): Applied to GPD_1. Same 1 RW1C description as bit 0.

GPI Interrupt Status (GPI_INT_STS_GPD_0): GPI Interrupt Status (GPI_INT_STS) This bit is set to ‘1’ by hardware when either an edge or a level event is detected (See RxEdCfg RxInv) on pad and all the following conditions are true: 0h - The corresponding pad is used in GPIO input mode 0 RW1C - HOSTSW_OWN = 1 (i.e. Host GPIO Driver Mode). Writing a value of 1 will clear the bit while writing a value of 0 has no effect. 0 = No interrupt 1 = Interrupt asserts The state of GPI_INT_EN does not prevent the setting of GPI_INT_STS.

7.3.10 GPI Interrupt Enable (GPI_IE_GPD_0)—Offset 120h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_INT_EN_GPD_9 GPI_INT_EN_GPD_8 GPI_INT_EN_GPD_7 GPI_INT_EN_GPD_6 GPI_INT_EN_GPD_5 GPI_INT_EN_GPD_4 GPI_INT_EN_GPD_3 GPI_INT_EN_GPD_2 GPI_INT_EN_GPD_1 GPI_INT_EN_GPD_0 GPI_INT_EN_GPD_11 GPI_INT_EN_GPD_10

Bit Default & Field Name (ID): Description Range Access

0h 31:12 Reserved. RO

0h GPI Interrupt Enable (GPI_INT_EN_GPD_11): Applied to GPD_11. Same 11 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPD_10): Applied to GPD_10. Same 10 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPD_9): Applied to GPD_9. Same 9 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPD_8): Applied to GPD_8. Same 8 RW description as bit 0.

644 332219-002

GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h GPI Interrupt Enable (GPI_INT_EN_GPD_7): Applied to GPD_7. Same 7 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPD_6): Applied to GPD_6. Same 6 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPD_5): Applied to GPD_5. Same 5 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPD_4): Applied to GPD_4. Same 4 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPD_3): Applied to GPD_3. Same 3 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPD_2): Applied to GPD_2. Same 2 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPD_1): Applied to GPD_1. Same 1 RW description as bit 0.

GPI Interrupt Enable (GPI_INT_EN_GPD_0): This bit is used to enable/disable 0h the generation of APIC interrupt when the corresponding GPI_INT_STS bit is set. 0 0 = disable interrupt generation RW 1 = enable interrupt generation Refer to GPI_IRQ_ROUTE for host GPIO Driver Mode interrupt routing.

7.3.11 GPI General Purpose Events Status (GPI_GPE_STS_GPD_0)—Offset 140h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_GPE_STS_GPD_9 GPI_GPE_STS_GPD_8 GPI_GPE_STS_GPD_7 GPI_GPE_STS_GPD_6 GPI_GPE_STS_GPD_5 GPI_GPE_STS_GPD_4 GPI_GPE_STS_GPD_3 GPI_GPE_STS_GPD_2 GPI_GPE_STS_GPD_1 GPI_GPE_STS_GPD_0 GPI_GPE_STS_GPD_11 GPI_GPE_STS_GPD_10

Bit Default & Field Name (ID): Description Range Access

0h 31:12 Reserved. RO

0h GPI General Purpose Events Status (GPI_GPE_STS_GPD_11): Applied to 11 RW1C GPD_11. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPD_10): Applied to 10 RW1C GPD_10. Same description as bit 0.

332219-002 645 GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h GPI General Purpose Events Status (GPI_GPE_STS_GPD_9): Applied to 9 RW1C GPD_9. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPD_8): Applied to 8 RW1C GPD_8. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPD_7): Applied to 7 RW1C GPD_7. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPD_6): Applied to 6 RW1C GPD_6. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPD_5): Applied to 5 RW1C GPD_5. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPD_4): Applied to 4 RW1C GPD_4. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPD_3): Applied to 3 RW1C GPD_3. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPD_2): Applied to 2 RW1C GPD_2. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPD_1): Applied to 1 RW1C GPD_1. Same description as bit 0.

GPI General Purpose Events Status (GPI_GPE_STS_GPD_0): These bits are set any time the corresponding GPIO pad is set up as an input, under host ownership and the corresponding GPIO signal is high(or low if the corresponding RXINV bit is set). If the corresponding enable bit is set in the GPI_GPE_EN register, then when the 0h GPI_GPE_STS bit is set: 0 RW1C - If the system is in an S3-S5 state, the event will also wake the system. - If the system is in an S0 state (or upon waking back to an S0 state), an SCI will be caused, depending on the GPIRoutSCI bit for the corresponding pad. These bits are sticky bits and are cleared by writing a 1 back to this bit position. The state of GPI_GPE_EN does not prevent the setting of GPI_GPE_STS.

7.3.12 GPI General Purpose Events Enable (GPI_GPE_EN_GPD_0)—Offset 160h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_GPE_EN_GPD_9 GPI_GPE_EN_GPD_8 GPI_GPE_EN_GPD_7 GPI_GPE_EN_GPD_6 GPI_GPE_EN_GPD_5 GPI_GPE_EN_GPD_4 GPI_GPE_EN_GPD_3 GPI_GPE_EN_GPD_2 GPI_GPE_EN_GPD_1 GPI_GPE_EN_GPD_0 GPI_GPE_EN_GPD_11 GPI_GPE_EN_GPD_10

646 332219-002

GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h 31:12 Reserved. RO

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPD_11): Applied to 11 RW GPD_11. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPD_10): Applied to 10 RW GPD_10. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPD_9): Applied to GPD_9. 9 RW Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPD_8): Applied to GPD_8. 8 RW Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPD_7): Applied to GPD_7. 7 RW Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPD_6): Applied to GPD_6. 6 RW Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPD_5): Applied to GPD_5. 5 RW Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPD_4): Applied to GPD_4. 4 RW Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPD_3): Applied to GPD_3. 3 RW Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPD_2): Applied to GPD_2. 2 RW Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPD_1): Applied to GPD_1. 1 RW Same description as bit 0.

GPI General Purpose Events Enable (GPI_GPE_EN_GPD_0): This bit is used to enable/disable the generation of GPE to cause SCI and/or wake when the 0h corresponding GPI_GPE_STS bit is set. 0 0 = disable GPE generation RW 1 = enable GPE generation Note: The pad must also be routed for GPE functionality in order for GPE to be generated, i.e. the corresponding GPIRoutSCI must be set to ‘1’.

7.3.13 Pad Configuration DW0 (PAD_CFG_DW0_GPD_0)—Offset 400h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 4000x00h

332219-002 647 GPIO for SKL PCH-LP

3 2 2 2 1 1 840 1 8 4 0 6 2

00000100000000000000001100000000 RSVD RSVD RSVD RSVD RSVD RXINV PMODE1 PMODE0 RXRAW1 RXEVCFG GPIOTXDIS GPIORXDIS PADRSTCFG GPIROUTSCI GPIROUTSMI RXPADSTSEL GPIROUTNMI GPIOTXSTATE GPIORXSTATE GPIROUTIOXAPIC

Bit Default & Field Name (ID): Description Range Access

Pad Reset Config (PADRSTCFG): This register controls which reset is used to reset GPIO pad register fields in PAD_CFG_DW0 and PAD_CFG_DW1 registers. This register can be used for Sx isolation of the associated signal if needed.

0h 00 = DSW_PWROK 31:30 01 = Host deep reset. This reset occurs when a host reset (with or without power RW cycle) is initiated or a global reset is initiated, except that the reset does not assert when in S3/S4/S5. 10 = PLTRST# 11 = RSMRST#

RX Pad State Select (RXPADSTSEL): Determines from which node the RX pad state for native function should be taken from. This field only affects the pad state 0h value being fanned out to native function(s) and is not meaningful if the pad is in 29 RW GPIO mode (i.e. Pad Mode = 0). 0 = Raw RX pad state directly from RX buffer 1 = Internal RX pad state (subject to RXINV and PreGfRXSel settings)

RX Raw Override to '1' (RXRAW1): This bit determines if the selected pad state is being overridden to '1'. This field is only applicable when the RX buffer is configured 0h 28 as an input in either GPIO Mode or native function mode. The override takes place at RW the internal pad state directly from buffer and before the RXINV. 0 = No Override 1 = RX drive 1 internally

0h 27 Reserved. RO

RX Level/Edge Configuration (RXEVCFG): Determines if the internal RX pad state (synchronized, filtered vs non-filtered version as determined by PreGfRXSel, and is further subject to RXInv) should be passed on to the next logic stage as is, as a pulse, or level signal. This field does not affect the received pad state (to 2h 26:25 GPIORXState or native functions) but how the interrupt or wake triggering events RW should be delivered to the GPIO Community Controller . 0h = Level 1h = Edge 2h = Drive '0' 3h = Reserved (implement as setting 0h)

0h 24 Reserved. RO

RX Invert (RXINV): This bit determines if the selected pad state should go through the polarity inversion stage. This field is only applicable when the RX buffer is configured as an input in either GPIO Mode or native function mode. The polarity inversion takes place at the mux node of raw vs filtered or non-filtered RX pad state, 0h as determined by PreGfRXsel and RXPadStSel This bit does not affect GPIORXState. 23 During host ownership GPIO Mode, when this bit is set to '1', then the RX pad state is RW inverted as it is sent to the GPIO-to-IOxAPIC, GPE/SCI, SMI, NMI logic or GPI_IS[n] that is using it. This is used to allow active-low and active-high inputs to cause IRQ, SMI#, SCI or NMI. 0 = No inversion 1 = Inversion

0h 22:21 Reserved. RO

GPIO Input Route IOxAPIC (GPIROUTIOXAPIC): Determines if the pad can be routed to cause peripheral IRQ when configured in GPIO input mode. If the pad is not

0h configured in GPIO input mode, this field has no effect. 20 0 = Routing does not cause peripheral IRQ RW 1 = Routing can cause peripheral IRQ Note: This bit does not affect any interrupt status bit within GPIO, but is used as the last qualifier for the peripheral IRQ indication to the intended recipient(s).

648 332219-002

GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

GPIO Input Route SCI (GPIROUTSCI): Determines if the pad can be routed to cause SCI when configured in GPIO input mode. If the pad is not configured in GPIO

0h input mode, this field has no effect. 19 0 = Routing does not cause SCI. RW 1 = Routing can cause SCI Note: This bit does not affect any interrupt status bit within GPIO, but is used as the last qualifier for the GPE indication to the intended recipient(s).

GPIO Input Route SMI (GPIROUTSMI): Determines if the pad can be routed to cause SMI when configured in GPIO input mode. If the pad is not configured in GPIO input mode, this field has no effect. 0h 0 = Routing does not cause SMI. 18 RO 1 = Routing can cause SMI. Note: This bit does not affect any interrupt status bit within GPIO, but is used as the last qualifier for the SMI indication to the intended recipient(s). This bit only applies to a GPIO that has SMI capability. Otherwise, the bit is RO.

GPIO Input Route NMI (GPIROUTNMI): Determines if the pad can be routed to cause NMI when configured in GPIO input mode. If the pad is not configured in GPIO input mode, this field has no effect. 0 = Routing does not cause NMI. 0h 17 1 = Routing can cause NMI. RW Note: This bit also affects GPI_NMI_STS. If '0', GPI_NMI_STS is always clear. If '1', GPI_NMI_STS could be set (depending on GPIOOwn setting) when there is an event. Whether a NMI indication is generated and sent to the intended recipient(s) is also depending on the corresponding GPI_NMI_EN bit. This bit only applies to a GPIO that has NMI capability. Otherwise, the bit is RO.

0h 16:12 Reserved. RO

-- Pad Mode bit 1 (PMODE1): See description of Pad Mode bit 0. 11 RW

Pad Mode bit 0 (PMODE0): This bit is used in conjunction with Pad Mode bit 1. This two-bit field determines whether the Pad is controlled by GPIO controller logic or one of the native functions muxed onto the Pad. 0h = GPIO control the Pad. 1h = native function 1, if applicable, controls the Pad -- 10 2h = native function 2, if applicable, controls the Pad. Also used to enable the GPIO RW blink (PWM) capability if applicable (note that not all GPIOs have the blink capability) 3h = native function 3, if applicable, controls the Pad Dedicated (unmuxed) GPIO shall report RO of all 0’s in this register field If GPIO vs. native mode is configured via soft strap, this bit has no effect.

Default value is determined by the default functionality of the pad.

GPIO RX Disable (GPIORXDIS): 0 = Enable the input buffer (active low enable) of 1h the pad. 9 1 = Disable the input buffer of the pad. RW Notes: When the input buffer is disabled, the internal pad state is always driven to '0'.

1h GPIO TX Disable (GPIOTXDIS): 0 = Enable the output buffer (active low enable) 8 of the pad. RW 1 = Disable the output buffer of the pad; i.e. Hi-Z

0h 7:2 Reserved. RO

0h GPIO RX State (GPIORXSTATE): This is the current internal RX pad state after 1 RO Glitch Filter logic stage and is not affected by PMode and RXINV settings.

0h GPIO TX State (GPIOTXSTATE): 0 = Drive a level '0' to the TX output pad. 0 RW 1 = Drive a level '1' to the TX output pad

7.3.14 Pad Configuration DW1 (PAD_CFG_DW1_GPD_0)—Offset 404h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

332219-002 649 GPIO for SKL PCH-LP

Default: 50h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000001010000 TERM RSVD RSVD INTSEL

Bit Default & Field Name (ID): Description Range Access

0h 31:14 Reserved. RO

Termination (TERM): The Pad Termination state defines the different weak pull-up and pull-down settings that are supported by the buffer. The settings for [13:10] correspond to: 0000: none 0010: 5k pd 0100: 20k pd 1000: none 1001: 1k pu 1011: 2k pu 0h 1010: 5k pu 13:10 1100: 20k pu RW 1101: 1k & 2k pu (in parallel) 1111: Native controller selected by Pad Mode controls the Termination All others reserved. If a reserved value is programmed, pad may malfunction. The setting of this field is applicable in all Pad Mode including GPIO. As each Pad Mode may require different termination and isolation, care must be taken in sw/fw in the transition with appropriate register programming. The actual transition sequence requirement may vary on case by case basis depending on the native functions involved. For example, before changing the pad from output to input direction, pu/pd settings should be programmed first to ensure the input does not float momentarily.

0h 9:8 Reserved. RO

Interrupt Select (INTSEL): The Interrupt Select defines which interrupt line driven from the GPIO Controller toggles when an interrupt is detected on this pad. 50h 0 = Interrupt Line 0 7:0 RO 1 = Interrupt Line 1 .... Up to the max IOxAPIC IRQ supported

7.3.15 Pad Configuration DW0 (PAD_CFG_DW0_GPD_1)—Offset 408h

Same description as PAD_CFG_DW0_GPD_0.

7.3.16 Pad Configuration DW1 (PAD_CFG_DW1_GPD_1)—Offset 40Ch

Same description as PAD_CFG_DW1_GPD_0. Exception: The default value of the INTSEL bit field in this register is: 51h

7.3.17 Pad Configuration DW0 (PAD_CFG_DW0_GPD_2)—Offset 410h

Same description as PAD_CFG_DW0_GPD_0.

650 332219-002

GPIO for SKL PCH-LP

7.3.18 Pad Configuration DW1 (PAD_CFG_DW1_GPD_2)—Offset 414h

Same description as PAD_CFG_DW1_GPD_0. Exception: The default value of the INTSEL bit field in this register is: 52h

7.3.19 Pad Configuration DW0 (PAD_CFG_DW0_GPD_3)—Offset 418h

Same description as PAD_CFG_DW0_GPD_0.

7.3.20 Pad Configuration DW1 (PAD_CFG_DW1_GPD_3)—Offset 41Ch

Same description as PAD_CFG_DW1_GPD_0. Exception: The default value of the INTSEL bit field in this register is : 53h

7.3.21 Pad Configuration DW0 (PAD_CFG_DW0_GPD_4)—Offset 420h

Same description as PAD_CFG_DW0_GPD_0.

7.3.22 Pad Configuration DW1 (PAD_CFG_DW1_GPD_4)—Offset 424h

Same description as PAD_CFG_DW1_GPD_0. Exception: The default value of the INTSEL bit field in this register is: 54h

7.3.23 Pad Configuration DW0 (PAD_CFG_DW0_GPD_5)—Offset 428h

Same description as PAD_CFG_DW0_GPD_0.

7.3.24 Pad Configuration DW1 (PAD_CFG_DW1_GPD_5)—Offset 42Ch

Same description as PAD_CFG_DW1_GPD_0. Exception: The default value of the INTSEL bit field in this register is: 55h

7.3.25 Pad Configuration DW0 (PAD_CFG_DW0_GPD_6)—Offset 430h

Same description as PAD_CFG_DW0_GPD_0.

7.3.26 Pad Configuration DW1 (PAD_CFG_DW1_GPD_6)—Offset 434h

Same description as PAD_CFG_DW1_GPD_0. Exception: The default value of the INTSEL bit field in this register is: 56h

332219-002 651 GPIO for SKL PCH-LP

7.3.27 Pad Configuration DW0 (PAD_CFG_DW0_GPD_7)—Offset 438h

Same description as PAD_CFG_DW0_GPD_0.

7.3.28 Pad Configuration DW1 (PAD_CFG_DW1_GPD_7)—Offset 43Ch

Same description as PAD_CFG_DW1_GPD_0. Exception: The default value of the INTSEL bit field in this register is: 57h

7.3.29 Pad Configuration DW0 (PAD_CFG_DW0_GPD_8)—Offset 440h

Same description as PAD_CFG_DW0_GPD_0.

7.3.30 Pad Configuration DW1 (PAD_CFG_DW1_GPD_8)—Offset 444h

Same description as PAD_CFG_DW1_GPD_0. Exception: The default value of the INTSEL bit field in this register is: 58h

7.3.31 Pad Configuration DW0 (PAD_CFG_DW0_GPD_9)—Offset 448h

Same description as PAD_CFG_DW0_GPD_0.

7.3.32 Pad Configuration DW1 (PAD_CFG_DW1_GPD_9)—Offset 44Ch

Same description as PAD_CFG_DW1_GPD_0. Exception: The default value of the INTSEL bit field in this register is: 59h

7.3.33 Pad Configuration DW0 (PAD_CFG_DW0_GPD_10)—Offset 450h

Same description as PAD_CFG_DW0_GPD_0.

7.3.34 Pad Configuration DW1 (PAD_CFG_DW1_GPD_10)—Offset 454h

Same description as PAD_CFG_DW1_GPD_0. Exception: The default value of the INTSEL bit field in this register is: 5Ah

7.3.35 Pad Configuration DW0 (PAD_CFG_DW0_GPD_11)—Offset 458h

Same description as PAD_CFG_DW0_GPD_0.

652 332219-002

GPIO for SKL PCH-LP

7.3.36 Pad Configuration DW1 (PAD_CFG_DW1_GPD_11)—Offset 45Ch

Same description as PAD_CFG_DW1_GPD_0. Exception: The default value of the INTSEL bit field in this register is: 5Bh

7.4 GPIO Community 3 Registers Summary

Community 3 Registers are for GPP_F and GPP_G groups.

Table 7-4. Summary of GPIO Community 3 Registers

Offset Offset Default Register Name (ID)—Offset Start End Value

8h Bh Family Base Address (FAMBAR)—Offset 8h 300h

Ch Fh Pad Base Address (PADBAR)—Offset Ch 400h

10h 13h Miscellaneous Configuration (MISCCFG)—Offset 10h 43200h

20h 23h Pad Ownership (PAD_OWN_GPP_F_0)—Offset 20h 0h

24h 27h Pad Ownership (PAD_OWN_GPP_F_1)—Offset 24h 0h

28h 2Bh Pad Ownership (PAD_OWN_GPP_F_2)—Offset 28h 0h

30h 33h Pad Ownership (PAD_OWN_GPP_G_0)—Offset 30h 0h

A0h A3h Pad Configuration Lock (PADCFGLOCK_GPP_F)—Offset A0h 0h

A4h A7h Pad Configuration Lock (PADCFGLOCKTX_GPP_F)—Offset A4h 0h

A8h ABh Pad Configuration Lock (PADCFGLOCK_GPP_G)—Offset A8h 0h

ACh AFh Pad Configuration Lock (PADCFGLOCKTX_GPP_G)—Offset ACh 0h

D0h D3h Host Software Pad Ownership (HOSTSW_OWN_GPP_F)—Offset D0h 0h

D4h D7h Host Software Pad Ownership (HOSTSW_OWN_GPP_G)—Offset D4h 0h

100h 103h GPI Interrupt Status (GPI_IS_GPP_F)—Offset 100h 0h

104h 107h GPI Interrupt Status (GPI_IS_GPP_G)—Offset 104h 0h

120h 123h GPI Interrupt Enable (GPI_IE_GPP_F)—Offset 120h 0h

124h 127h GPI Interrupt Enable (GPI_IE_GPP_G)—Offset 124h 0h

140h 143h GPI General Purpose Events Status (GPI_GPE_STS_GPP_F)—Offset 140h 0h

144h 147h GPI General Purpose Events Status (GPI_GPE_STS_GPP_G)—Offset 144h 0h

160h 163h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_F)—Offset 160h 0h

164h 167h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_G)—Offset 164h 0h

44000x00h 400h 403h Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_0)—Offset 400h See register for xx value

404h 407h Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_0)—Offset 404h 30h

44000x00h 408h 40Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_1)—Offset 408h See register for xx value

40Ch 40Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_1)—Offset 40Ch See register

44000x00h 410h 413h Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_2)—Offset 410h See register for xx value

414h 417h Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_2)—Offset 414h See register

332219-002 653 GPIO for SKL PCH-LP

Table 7-4. Summary of GPIO Community 3 Registers (Continued)

Offset Offset Default Register Name (ID)—Offset Start End Value

44000x00h 418h 41Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_3)—Offset 418h See register for xx value

41Ch 41Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_3)—Offset 41Ch See register

44000x00h 420h 423h Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_4)—Offset 420h See register for xx value

424h 427h Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_4)—Offset 424h See register

44000x00h 428h 42Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_5)—Offset 428h See register for xx value

42Ch 42Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_5)—Offset 42Ch See register

44000x00h 430h 433h Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_6)—Offset 430h See register for xx value

434h 437h Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_6)—Offset 434h See register

44000x00h 438h 43Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_7)—Offset 438h See register for xx value

43Ch 43Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_7)—Offset 43Ch See register

44000x00h 440h 443h Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_8)—Offset 440h See register for xx value

444h 447h Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_8)—Offset 444h See register

44000x00h 448h 44Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_9)—Offset 448h See register for xx value

44Ch 44Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_9)—Offset 44Ch See register

44000x00h 450h 453h Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_10)—Offset 450h See register for xx value

454h 457h Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_10)—Offset 454h See register

44000x00h 458h 45Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_11)—Offset 458h See register for xx value

45Ch 45Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_11)—Offset 45Ch See register

44000x00h 460h 463h Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_12)—Offset 460h See register for xx value

464h 467h Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_12)—Offset 464h See register

44000x00h 468h 46Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_13)—Offset 468h See register for xx value

46Ch 46Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_13)—Offset 46Ch See register

44000x00h 470h 473h Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_14)—Offset 470h See register for xx value

474h 477h Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_14)—Offset 474h See register

44000x00h 478h 47Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_15)—Offset 478h See register for xx value

654 332219-002

GPIO for SKL PCH-LP

Table 7-4. Summary of GPIO Community 3 Registers (Continued)

Offset Offset Default Register Name (ID)—Offset Start End Value

47Ch 47Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_15)—Offset 47Ch See register

44000x00h 480h 483h Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_16)—Offset 480h See register for xx value

484h 487h Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_16)—Offset 484h See register

44000x00h 488h 48Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_17)—Offset 488h See register for xx value

48Ch 48Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_17)—Offset 48Ch See register

44000x00h 490h 493h Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_18)—Offset 490h See register for xx value

494h 497h Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_18)—Offset 494h See register

44000x00h 498h 49Bh Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_19)—Offset 498h See register for xx value

49Ch 49Fh Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_19)—Offset 49Ch See register

44000x00h 4A0h 4A3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_20)—Offset 4A0h See register for xx value

4A4h 4A7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_20)—Offset 4A4h See register

44000x00h 4A8h 4ABh Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_21)—Offset 4A8h See register for xx value

4ACh 4AFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_21)—Offset 4ACh See register

44000x00h 4B0h 4B3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_22)—Offset 4B0h See register for xx value

4B4h 4B7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_22)—Offset 4B4h See register

44000x00h 4B8h 4BBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_23)—Offset 4B8h See register for xx value

4BCh 4BFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_23)—Offset 4BCh See register

44000x00h 4C4h 4C7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_0)—Offset 4C4h See register for xx value

4C8h 4CBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_1)—Offset 4C8h See register

44000x00h 4CCh 4CFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_1)—Offset 4CCh See register for xx value

4D0h 4D3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_2)—Offset 4D0h See register

44000x00h 4D4h 4D7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_2)—Offset 4D4h See register for xx value

4D8h 4DBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_3)—Offset 4D8h See register

44000x00h 4DCh 4DFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_3)—Offset 4DCh See register for xx value

4E0h 4E3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_4)—Offset 4E0h See register

332219-002 655 GPIO for SKL PCH-LP

Table 7-4. Summary of GPIO Community 3 Registers (Continued)

Offset Offset Default Register Name (ID)—Offset Start End Value

44000x00h 4E4h 4E7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_4)—Offset 4E4h See register for xx value

4E8h 4EBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_5)—Offset 4E8h See register

44000x00h 4ECh 4EFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_5)—Offset 4ECh See register for xx value

4F0h 4F3h Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_6)—Offset 4F0h See register

44000x00h 4F4h 4F7h Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_6)—Offset 4F4h See register for xx value

4F8h 4FBh Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_7)—Offset 4F8h See register

44000x00h 4FCh 4FFh Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_7)—Offset 4FCh See register for xx value

7.4.1 Family Base Address (FAMBAR)—Offset 8h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 300h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000001100000000 RSVD FAMBAR

Bit Default & Field Name (ID): Description Range Access

0h 31:16 Reserved. RO

Family Base Address (FAMBAR): Family Base Address (FAMBAR) This field 300h provides the starting byte-align address of Family0 register sets within a Community. 15:0 RO It is meant for software to discover from where the very first Family register (i.e. Family0 register) starts to compute the next Families address offsets.

7.4.2 Pad Base Address (PADBAR)—Offset Ch

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 400h

656 332219-002

GPIO for SKL PCH-LP

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000010000000000 RSVD PADBAR

Bit Default & Field Name (ID): Description Range Access

0h 31:16 Reserved. RO

400h Pad Base Address (PADBAR): This field provides the starting byte-align address of 15:0 Pad0 register sets. It is meant for software to discover from where the very first Pad RO register (i.e. Pad0 register) starts to compute the next Pad address offsets.

7.4.3 Miscellaneous Configuration (MISCCFG)—Offset 10h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 43200h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000001000011001000000000 RSVD RSVD RSVD GPDLCGEN GPDPCGEN GPE0_DW2 GPE0_DW1 GPE0_DW0 GPIO_DRIVER_IRQ_ROUTE

332219-002 657 GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h 31:20 Reserved. RO

GPIO Group to GPE_DW0 assignment encoding (GPE0_DW2): This register assigns a specific GPIO Group to the ACPI GPE0[95:64]. The selected GPIO group will be mapped to lower bits of the GPE register 0h = GPP_A[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 4h 1h = GPP_B[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 19:16 2h = GPP_C[23:0] mapped to GPE[87:64]; GPE[95:88] not used. RW 3h = GPP_D[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 4h = GPP_E[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 5h = GPP_F[23:0] mapped to GPE[87:64]; GPE[95:88] not used. 6h = GPP_G[7:0] mapped to GPE[51:64]; GPE[95:52] not used. 7h = GPD[11:0] mapped to GPE[75:64]; GPE[95:76] not used.

GPIO Group to GPE_DW0 assignment encoding (GPE0_DW1): This register assigns a specific GPIO Group to the ACPI GPE0[63:32]. The selected GPIO group will be mapped to lower bits of the GPE register 0h = GPP_A[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 3h 1h = GPP_B[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 15:12 2h = GPP_C[23:0] mapped to GPE[55:32]; GPE[63:56] not used. RW 3h = GPP_D[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 4h = GPP_E[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 5h = GPP_F[23:0] mapped to GPE[55:32]; GPE[63:56] not used. 6h = GPP_G[7:0] mapped to GPE[39:32]; GPE[63:40] not used. 7h = GPD[11:0] mapped to GPE[43:32]; GPE[63:44] not used.

GPIO Group to GPE_DW0 assignment encoding (GPE0_DW0): This register assigns a specific GPIO Group to the ACPI GPE0[31:0]. The selected GPIO group will be mapped to lower bits of the GPE register 0h = GPP_A[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 2h 1h = GPP_B[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 11:8 2h = GPP_C[23:0] mapped to GPE[23:0]; GPE[31:24] not used. RW 3h = GPP_D[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 4h = GPP_E[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 5h = GPP_F[23:0] mapped to GPE[23:0]; GPE[31:24] not used. 6h = GPP_G[7:0] mapped to GPE[7:0]; GPE[31:8] not used. 7h = GPD[11:0] mapped to GPE[11:0]; GPE[31:12] not used.

0h 7:4 Reserved. RO

GPIO Driver IRQ Route (GPIO_DRIVER_IRQ_ROUTE): GPIO Driver 0h IRQ_ROUTE[1:0]: Specifies the APIC IRQ globally for all pads within the current 3 community (GPI_IS with corresponding GPI_IE enable). RW 0 = IRQ14 1 = IRQ15

0h 2 Reserved. RO

GPIO Dynamic Partition Clock Gating Enable (GPDPCGEN): Specifies whether 0h the GPIO Community should take part in partition clock gating 1 RW 0 = Disable participation in dynamic partition clock gating 1 = Enable participation in dynamic partition clock gating.

GPIO Dynamic Local Clock Gating Enable (GPDLCGEN): Specifies whether the 0h GPIO Community should perform local clock gating. 0 RW 0 = Disable dynamic local clock gating 1 = Enable dynamic local clock gating.

7.4.4 Pad Ownership (PAD_OWN_GPP_F_0)—Offset 20h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

658 332219-002

GPIO for SKL PCH-LP

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD PAD_OWN_GPP_F_7 PAD_OWN_GPP_F_6 PAD_OWN_GPP_F_5 PAD_OWN_GPP_F_4 PAD_OWN_GPP_F_3 PAD_OWN_GPP_F_2 PAD_OWN_GPP_F_1 PAD_OWN_GPP_F_0

Bit Default & Field Name (ID): Description Range Access

0h 31:30 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_F_7): Same description as bit 0, except that 29:28 RO the bit field applies to GPP_F7.

0h 27:26 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_F_6): Same description as bit 0, except that 25:24 RO the bit field applies to GPP_F6.

0h 23:22 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_F_5): Same description as bit 0, except that 21:20 RO the bit field applies to GPP_F5.

0h 19:18 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_F_4): Same description as bit 0, except that 17:16 RO the bit field applies to GPP_F4.

0h 15:14 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_F_3): Same description as bit 0, except that 13:12 RO the bit field applies to GPP_F3.

0h 11:10 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_F_2): Same description as bit 0, except that 9:8 RO the bit field applies to GPP_F2.

0h 7:6 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_F_1): Same description as bit 0, except that 5:4 RO the bit field applies to GPP_F1.

0h 3:2 Reserved. RO

Pad Ownership (PAD_OWN_GPP_F_0): 00 = Host GPIO ACPI Mode or GPIO Driver Mode. Host software (ACPI or GPIO Driver) has ownership of the pad. In Host GPIO Driver Mode (refer to HOSTSW_OWN), GPIO input event update is limited to 0h GPI_STS update only. Otherwise in Host ACPI Mode, updates are limited to 1:0 RO GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. 01 = ME GPIO Mode. ME has ownership of the pad. 10 = ISH GPIO Mode.ME has ownership of the pad 11 = Reserved

332219-002 659 GPIO for SKL PCH-LP

7.4.5 Pad Ownership (PAD_OWN_GPP_F_1)—Offset 24h

Same description as PAD_OWN_GPP_F_0, except that this register is for GPP_F[15:8]

7.4.6 Pad Ownership (PAD_OWN_GPP_F_2)—Offset 28h

Same description as PAD_OWN_GPP_F_0, except that this register is for GPP_F[23:16]

7.4.7 Pad Ownership (PAD_OWN_GPP_G_0)—Offset 30h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD PAD_OWN_GPP_G_7 PAD_OWN_GPP_G_6 PAD_OWN_GPP_G_5 PAD_OWN_GPP_G_4 PAD_OWN_GPP_G_3 PAD_OWN_GPP_G_2 PAD_OWN_GPP_G_1 PAD_OWN_GPP_G_0

Bit Default & Field Name (ID): Description Range Access

0h 31:30 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_G_7): Same description as bit 0, except that 29:28 RO the bit field applies to GPP_G7.

0h 27:26 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_G_6): Same description as bit 0, except that 25:24 RO the bit field applies to GPP_G6.

0h 23:22 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_G_5): Same description as bit 0, except that 21:20 RO the bit field applies to GPP_G5.

0h 19:18 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_G_4): Same description as bit 0, except that 17:16 RO the bit field applies to GPP_G4.

0h 15:14 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_G_3): Same description as bit 0, except that 13:12 RO the bit field applies to GPP_G3.

660 332219-002

GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h 11:10 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_G_2): Same description as bit 0, except that 9:8 RO the bit field applies to GPP_G2.

0h 7:6 Reserved. RO

0h Pad Ownership (PAD_OWN_GPP_G_1): Same description as bit 0, except that 5:4 RO the bit field applies to GPP_G1.

0h 3:2 Reserved. RO

Pad Ownership (PAD_OWN_GPP_G_0): 00 = Host GPIO ACPI Mode or GPIO Driver Mode. Host software (ACPI or GPIO Driver) has ownership of the pad. In Host GPIO Driver Mode (refer to HOSTSW_OWN), GPIO input event update is limited to 0h 1:0 GPI_STS update only. Otherwise in Host ACPI Mode, updates are limited to RO GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. 01 = ME GPIO Mode. ME has ownership of the pad. 10 = ISH GPIO Mode.ME has ownership of the pad 11 = Reserved

7.4.8 Pad Configuration Lock (PADCFGLOCK_GPP_F)—Offset A0h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD PADCFGLOCK_GPP_F_9 PADCFGLOCK_GPP_F_8 PADCFGLOCK_GPP_F_7 PADCFGLOCK_GPP_F_6 PADCFGLOCK_GPP_F_5 PADCFGLOCK_GPP_F_4 PADCFGLOCK_GPP_F_3 PADCFGLOCK_GPP_F_2 PADCFGLOCK_GPP_F_1 PADCFGLOCK_GPP_F_0 PADCFGLOCK_GPP_F_23 PADCFGLOCK_GPP_F_22 PADCFGLOCK_GPP_F_21 PADCFGLOCK_GPP_F_20 PADCFGLOCK_GPP_F_19 PADCFGLOCK_GPP_F_18 PADCFGLOCK_GPP_F_17 PADCFGLOCK_GPP_F_16 PADCFGLOCK_GPP_F_15 PADCFGLOCK_GPP_F_14 PADCFGLOCK_GPP_F_13 PADCFGLOCK_GPP_F_12 PADCFGLOCK_GPP_F_11 PADCFGLOCK_GPP_F_10

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h Pad Config Lock (PADCFGLOCK_GPP_F_23): Applied to GPP_F23. Same 23 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_F_22): Applied to GPP_F22. Same 22 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_F_21): Applied to GPP_F21. Same 21 RW description as bit 0.

332219-002 661 GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h Pad Config Lock (PADCFGLOCK_GPP_F_20): Applied to GPP_F20. Same 20 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_F_19): Applied to GPP_F19. Same 19 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_F_18): Applied to GPP_F18. Same 18 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_F_17): Applied to GPP_F17. Same 17 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_F_16): Applied to GPP_F16. Same 16 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_F_15): Applied to GPP_F15. Same 15 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_F_14): Applied to GPP_F14. Same 14 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_F_13): Applied to GPP_F13. Same 13 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_F_12): Applied to GPP_F12. Same 12 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_F_11): Applied to GPP_F11. Same 11 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_F_10): Applied to GPP_F10. Same 10 RW description as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_F_9): Applied to GPP_F9. Same description 9 RW as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_F_8): Applied to GPP_F8. Same description 8 RW as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_F_7): Applied to GPP_F7. Same description 7 RW as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_F_6): Applied to GPP_F6. Same description 6 RW as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_F_5): Applied to GPP_F5. Same description 5 RW as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_F_4): Applied to GPP_F4. Same description 4 RW as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_F_3): Applied to GPP_F3. Same description 3 RW as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_F_2): Applied to GPP_F2. Same description 2 RW as bit 0.

0h Pad Config Lock (PADCFGLOCK_GPP_F_1): Applied to GPP_F1. Same description 1 RW as bit 0.

Pad Config Lock (PADCFGLOCK_GPP_F_0): Pad Configuration Lock locks specific register fields in the GPP specific registers from being configured. The registers affected become Read-Only and software writes to these registers have no effect. 0 = Unlock 1 = Lock the following register fields as read-only (RO): 0h - Pad Configuration registers (exclude GPIOTXState) 0 RW - GPI_NMI_EN Register (if implemented) - GPI_SMI_EN Register (if implemented) - GPI_GPE_EN Register (if implemented) When PadCfgLock is written from a '1' to a '0' (unlock), a synchronous SMI# is generated if enabled. This ensures that only SMM code can change the above GPIO registers after the lockdown.

662 332219-002

GPIO for SKL PCH-LP

7.4.9 Pad Configuration Lock (PADCFGLOCKTX_GPP_F)—Offset A4h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD PADCFGLOCKTX_GPP_F_9 PADCFGLOCKTX_GPP_F_8 PADCFGLOCKTX_GPP_F_7 PADCFGLOCKTX_GPP_F_6 PADCFGLOCKTX_GPP_F_5 PADCFGLOCKTX_GPP_F_4 PADCFGLOCKTX_GPP_F_3 PADCFGLOCKTX_GPP_F_2 PADCFGLOCKTX_GPP_F_1 PADCFGLOCKTX_GPP_F_0 PADCFGLOCKTX_GPP_F_23 PADCFGLOCKTX_GPP_F_22 PADCFGLOCKTX_GPP_F_21 PADCFGLOCKTX_GPP_F_20 PADCFGLOCKTX_GPP_F_19 PADCFGLOCKTX_GPP_F_18 PADCFGLOCKTX_GPP_F_17 PADCFGLOCKTX_GPP_F_16 PADCFGLOCKTX_GPP_F_15 PADCFGLOCKTX_GPP_F_14 PADCFGLOCKTX_GPP_F_13 PADCFGLOCKTX_GPP_F_12 PADCFGLOCKTX_GPP_F_11 PADCFGLOCKTX_GPP_F_10

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_F_23): Applied to GPP_F23. 23 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_F_22): Applied to GPP_F22. 22 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_F_21): Applied to GPP_F21. 21 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_F_20): Applied to GPP_F20. 20 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_F_19): Applied to GPP_F19. 19 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_F_18): Applied to GPP_F18. 18 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_F_17): Applied to GPP_F17. 17 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_F_16): Applied to GPP_F16. 16 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_F_15): Applied to GPP_F15. 15 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_F_14): Applied to GPP_F14. 14 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_F_13): Applied to GPP_F13. 13 RW Same description as bit 0.

332219-002 663 GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_F_12): Applied to GPP_F12. 12 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_F_11): Applied to GPP_F11. 11 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_F_10): Applied to GPP_F10. 10 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_F_9): Applied to GPP_F9. 9 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_F_8): Applied to GPP_F8. 8 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_F_7): Applied to GPP_F7. 7 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_F_6): Applied to GPP_F6. 6 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_F_5): Applied to GPP_F5. 5 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_F_4): Applied to GPP_F4. 4 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_F_3): Applied to GPP_F3. 3 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_F_2): Applied to GPP_F2. 2 RW Same description as bit 0.

0h Pad Config Lock TXState (PADCFGLOCKTX_GPP_F_1): Applied to GPP_F1. 1 RW Same description as bit 0.

Pad Config Lock TXState (PADCFGLOCKTX_GPP_F_0): PadCfgLockTx locks the GPIOTxState bit from being configured. The GPIOTxState register becomes Read- Only and software writes to the register have no effect. 0h 0 0 = Unlock RW 1 = Locks the Pad Configuration GPIOTXState field as read-only (RO) When PadCfgLockTx is written from a '1' to a '0' (unlock), a synchronous SMI# is generated if enabled. This ensures that only SMM code can change the above GPIO registers after the lockdown.

7.4.10 Pad Configuration Lock (PADCFGLOCK_GPP_G)—Offset A8h

Same definition as PADCFGLOCK_GPP_F register, except this register applies to GPP_G group (GPP_G[7:0]). Bits corresponding to unimplemented GPP_G are reserved.

7.4.11 Pad Configuration Lock (PADCFGLOCKTX_GPP_G)—Offset ACh

Same definition as PADCFGLOCKTX_GPP_F register, except this register applies to GPP_G group (GPP_G[7:0]). Bits corresponding to unimplemented GPP_G are reserved.

7.4.12 Host Software Pad Ownership (HOSTSW_OWN_GPP_F)— Offset D0h

Access Method

664 332219-002

GPIO for SKL PCH-LP

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD HOSTSW_OWN_GPP_F_9 HOSTSW_OWN_GPP_F_8 HOSTSW_OWN_GPP_F_7 HOSTSW_OWN_GPP_F_6 HOSTSW_OWN_GPP_F_5 HOSTSW_OWN_GPP_F_4 HOSTSW_OWN_GPP_F_3 HOSTSW_OWN_GPP_F_2 HOSTSW_OWN_GPP_F_1 HOSTSW_OWN_GPP_F_0 HOSTSW_OWN_GPP_F_23 HOSTSW_OWN_GPP_F_22 HOSTSW_OWN_GPP_F_21 HOSTSW_OWN_GPP_F_20 HOSTSW_OWN_GPP_F_19 HOSTSW_OWN_GPP_F_18 HOSTSW_OWN_GPP_F_17 HOSTSW_OWN_GPP_F_16 HOSTSW_OWN_GPP_F_15 HOSTSW_OWN_GPP_F_14 HOSTSW_OWN_GPP_F_13 HOSTSW_OWN_GPP_F_12 HOSTSW_OWN_GPP_F_11 HOSTSW_OWN_GPP_F_10

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h HostSW_Own (HOSTSW_OWN_GPP_F_23): Applied to GPP_F23. Same 23 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_F_22): Applied to GPP_F22. Same 22 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_F_21): Applied to GPP_F21. Same 21 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_F_20): Applied to GPP_F20. Same 20 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_F_19): Applied to GPP_F19. Same 19 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_F_18): Applied to GPP_F18. Same 18 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_F_17): Applied to GPP_F17. Same 17 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_F_16): Applied to GPP_F16. Same 16 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_F_15): Applied to GPP_F15. Same 15 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_F_14): Applied to GPP_F14. Same 14 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_F_13): Applied to GPP_F13. Same 13 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_F_12): Applied to GPP_F12. Same 12 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_F_11): Applied to GPP_F11. Same 11 RW description as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_F_10): Applied to GPP_F10. Same 10 RW description as bit 0.

332219-002 665 GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h HostSW_Own (HOSTSW_OWN_GPP_F_9): Applied to GPP_F9. Same description 9 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_F_8): Applied to GPP_F8. Same description 8 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_F_7): Applied to GPP_F7. Same description 7 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_F_6): Applied to GPP_F6. Same description 6 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_F_5): Applied to GPP_F5. Same description 5 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_F_4): Applied to GPP_F4. Same description 4 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_F_3): Applied to GPP_F3. Same description 3 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_F_2): Applied to GPP_F2. Same description 2 RW as bit 0.

0h HostSW_Own (HOSTSW_OWN_GPP_F_1): Applied to GPP_F1. Same description 1 RW as bit 0.

HostSW_Own (HOSTSW_OWN_GPP_F_0): This register determines the appropriate host status bit update when a pad is under host ownership. 0h 0 = ACPI Mode. GPIO input event updates are limited to GPI_GPE_STS, 0 RW GPI_NMI_STS and/or GPI_SMI_STS. GPI_STS update is masked. 1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked.

7.4.13 Host Software Pad Ownership (HOSTSW_OWN_GPP_G)— Offset D4h

Same definition as HOSTSW_OWN_GPP_F register, except this register applies to GPP_G group (GPP_G[7:0]). Bits corresponding to unimplemented GPP_G are reserved.

7.4.14 GPI Interrupt Status (GPI_IS_GPP_F)—Offset 100h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

666 332219-002

GPIO for SKL PCH-LP

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_INT_STS_GPP_F_9 GPI_INT_STS_GPP_F_8 GPI_INT_STS_GPP_F_7 GPI_INT_STS_GPP_F_6 GPI_INT_STS_GPP_F_5 GPI_INT_STS_GPP_F_4 GPI_INT_STS_GPP_F_3 GPI_INT_STS_GPP_F_2 GPI_INT_STS_GPP_F_1 GPI_INT_STS_GPP_F_0 GPI_INT_STS_GPP_F_23 GPI_INT_STS_GPP_F_22 GPI_INT_STS_GPP_F_21 GPI_INT_STS_GPP_F_20 GPI_INT_STS_GPP_F_19 GPI_INT_STS_GPP_F_18 GPI_INT_STS_GPP_F_17 GPI_INT_STS_GPP_F_16 GPI_INT_STS_GPP_F_15 GPI_INT_STS_GPP_F_14 GPI_INT_STS_GPP_F_13 GPI_INT_STS_GPP_F_12 GPI_INT_STS_GPP_F_11 GPI_INT_STS_GPP_F_10

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h GPI Interrupt Status (GPI_INT_STS_GPP_F_23): Applied to GPP_F23. Same 23 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_F_22): Applied to GPP_F22. Same 22 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_F_21): Applied to GPP_F21. Same 21 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_F_20): Applied to GPP_F20. Same 20 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_F_19): Applied to GPP_F19. Same 19 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_F_18): Applied to GPP_F18. Same 18 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_F_17): Applied to GPP_F17. Same 17 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_F_16): Applied to GPP_F16. Same 16 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_F_15): Applied to GPP_F15. Same 15 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_F_14): Applied to GPP_F14. Same 14 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_F_13): Applied to GPP_F13. Same 13 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_F_12): Applied to GPP_F12. Same 12 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_F_11): Applied to GPP_F11. Same 11 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_F_10): Applied to GPP_F10. Same 10 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_F_9): Applied to GPP_F9. Same 9 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_F_8): Applied to GPP_F8. Same 8 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_F_7): Applied to GPP_F7. Same 7 RW1C description as bit 0.

332219-002 667 GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h GPI Interrupt Status (GPI_INT_STS_GPP_F_6): Applied to GPP_F6. Same 6 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_F_5): Applied to GPP_F5. Same 5 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_F_4): Applied to GPP_F4. Same 4 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_F_3): Applied to GPP_F3. Same 3 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_F_2): Applied to GPP_F2. Same 2 RW1C description as bit 0.

0h GPI Interrupt Status (GPI_INT_STS_GPP_F_1): Applied to GPP_F1. Same 1 RW1C description as bit 0.

GPI Interrupt Status (GPI_INT_STS_GPP_F_0): This bit is set to ‘1’ by hardware when either an edge or a level event is detected (See RxEdCfg RxInv) on pad and all the following conditions are true: 0h - The corresponding pad is used in GPIO input mode 0 - HOSTSW_OWN = 1 (i.e. Host GPIO Driver Mode). RW1C Writing a value of 1 will clear the bit while writing a value of 0 has no effect. 0 = No interrupt 1 = Interrupt asserts The state of GPI_INT_EN does not prevent the setting of GPI_INT_STS.

7.4.15 GPI Interrupt Status (GPI_IS_GPP_G)—Offset 104h

Same definition as GPI_IS_GPP_F register, except this register applies to GPP_G group (GPP_G[7:0]). Bits corresponding to unimplemented GPP_G are reserved.

7.4.16 GPI Interrupt Enable (GPI_IE_GPP_F)—Offset 120h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_INT_EN_GPP_F_9 GPI_INT_EN_GPP_F_8 GPI_INT_EN_GPP_F_7 GPI_INT_EN_GPP_F_6 GPI_INT_EN_GPP_F_5 GPI_INT_EN_GPP_F_4 GPI_INT_EN_GPP_F_3 GPI_INT_EN_GPP_F_2 GPI_INT_EN_GPP_F_1 GPI_INT_EN_GPP_F_0 GPI_INT_EN_GPP_F_23 GPI_INT_EN_GPP_F_22 GPI_INT_EN_GPP_F_21 GPI_INT_EN_GPP_F_20 GPI_INT_EN_GPP_F_19 GPI_INT_EN_GPP_F_18 GPI_INT_EN_GPP_F_17 GPI_INT_EN_GPP_F_16 GPI_INT_EN_GPP_F_15 GPI_INT_EN_GPP_F_14 GPI_INT_EN_GPP_F_13 GPI_INT_EN_GPP_F_12 GPI_INT_EN_GPP_F_11 GPI_INT_EN_GPP_F_10

668 332219-002

GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h GPI Interrupt Enable (GPI_INT_EN_GPP_F_23): Applied to GPP_F23. Same 23 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_F_22): Applied to GPP_F22. Same 22 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_F_21): Applied to GPP_F21. Same 21 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_F_20): Applied to GPP_F20. Same 20 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_F_19): Applied to GPP_F19. Same 19 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_F_18): Applied to GPP_F18. Same 18 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_F_17): Applied to GPP_F17. Same 17 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_F_16): Applied to GPP_F16. Same 16 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_F_15): Applied to GPP_F15. Same 15 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_F_14): Applied to GPP_F14. Same 14 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_F_13): Applied to GPP_F13. Same 13 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_F_12): Applied to GPP_F12. Same 12 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_F_11): Applied to GPP_F11. Same 11 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_F_10): Applied to GPP_F10. Same 10 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_F_9): Applied to GPP_F9. Same 9 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_F_8): Applied to GPP_F8. Same 8 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_F_7): Applied to GPP_F7. Same 7 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_F_6): Applied to GPP_F6. Same 6 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_F_5): Applied to GPP_F5. Same 5 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_F_4): Applied to GPP_F4. Same 4 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_F_3): Applied to GPP_F3. Same 3 RW description as bit 0.

332219-002 669 GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h GPI Interrupt Enable (GPI_INT_EN_GPP_F_2): Applied to GPP_F2. Same 2 RW description as bit 0.

0h GPI Interrupt Enable (GPI_INT_EN_GPP_F_1): Applied to GPP_F1. Same 1 RW description as bit 0.

GPI Interrupt Enable (GPI_INT_EN_GPP_F_0): This bit is used to enable/ disable the generation of APIC interrupt when the corresponding GPI_INT_STS bit is 0h set. 0 RW 0 = disable interrupt generation 1 = enable interrupt generation Refer to GPI_IRQ_ROUTE for host GPIO Driver Mode interrupt routing.

7.4.17 GPI Interrupt Enable (GPI_IE_GPP_G)—Offset 124h

Same definition as GPI_IE_GPP_F register, except this register applies to GPP_G group (GPP_G[7:0]). Bits corresponding to unimplemented GPP_G are reserved.

7.4.18 GPI General Purpose Events Status (GPI_GPE_STS_GPP_F)—Offset 140h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_GPE_STS_GPP_F_9 GPI_GPE_STS_GPP_F_8 GPI_GPE_STS_GPP_F_7 GPI_GPE_STS_GPP_F_6 GPI_GPE_STS_GPP_F_5 GPI_GPE_STS_GPP_F_4 GPI_GPE_STS_GPP_F_3 GPI_GPE_STS_GPP_F_2 GPI_GPE_STS_GPP_F_1 GPI_GPE_STS_GPP_F_0 GPI_GPE_STS_GPP_F_23 GPI_GPE_STS_GPP_F_22 GPI_GPE_STS_GPP_F_21 GPI_GPE_STS_GPP_F_20 GPI_GPE_STS_GPP_F_19 GPI_GPE_STS_GPP_F_18 GPI_GPE_STS_GPP_F_17 GPI_GPE_STS_GPP_F_16 GPI_GPE_STS_GPP_F_15 GPI_GPE_STS_GPP_F_14 GPI_GPE_STS_GPP_F_13 GPI_GPE_STS_GPP_F_12 GPI_GPE_STS_GPP_F_11 GPI_GPE_STS_GPP_F_10

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_F_23): Applied to 23 RW1C GPP_F23. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_F_22): Applied to 22 RW1C GPP_F22. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_F_21): Applied to 21 RW1C GPP_F21. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_F_20): Applied to 20 RW1C GPP_F20. Same description as bit 0.

670 332219-002

GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_F_19): Applied to 19 RW1C GPP_F19. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_F_18): Applied to 18 RW1C GPP_F18. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_F_17): Applied to 17 RW1C GPP_F17. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_F_16): Applied to 16 RW1C GPP_F16. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_F_15): Applied to 15 RW1C GPP_F15. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_F_14): Applied to 14 RW1C GPP_F14. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_F_13): Applied to 13 RW1C GPP_F13. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_F_12): Applied to 12 RW1C GPP_F12. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_F_11): Applied to 11 RW1C GPP_F11. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_F_10): Applied to 10 RW1C GPP_F10. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_F_9): Applied to 9 RW1C GPP_F9. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_F_8): Applied to 8 RW1C GPP_F8. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_F_7): Applied to 7 RW1C GPP_F7. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_F_6): Applied to 6 RW1C GPP_F6. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_F_5): Applied to 5 RW1C GPP_F5. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_F_4): Applied to 4 RW1C GPP_F4. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_F_3): Applied to 3 RW1C GPP_F3. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_F_2): Applied to 2 RW1C GPP_F2. Same description as bit 0.

0h GPI General Purpose Events Status (GPI_GPE_STS_GPP_F_1): Applied to 1 RW1C GPP_F1. Same description as bit 0.

GPI General Purpose Events Status (GPI_GPE_STS_GPP_F_0): These bits are set any time the corresponding GPIO pad is set up as an input, under host ownership and the corresponding GPIO signal is high(or low if the corresponding RXINV bit is set). 0h If the corresponding enable bit is set in the GPI_GPE_EN register, then when the 0 GPI_GPE_STS bit is set: RW1C - If the system is in an S3-S5 state, the event will also wake the system. - If the system is in an S0 state (or upon waking back to an S0 state), an SCI will be caused, depending on the GPIRoutSCI bit for the corresponding pad. These bits are sticky bits and are cleared by writing a 1 back to this bit position. The state of GPI_GPE_EN does not prevent the setting of GPI_GPE_STS.

332219-002 671 GPIO for SKL PCH-LP

7.4.19 GPI General Purpose Events Status (GPI_GPE_STS_GPP_G)—Offset 144h

Same definition as GPI_GPE_STS_GPP_F register, except this register applies to GPP_G group (GPP_G[7:0]). Bits corresponding to unimplemented GPP_G are reserved.

7.4.20 GPI General Purpose Events Enable (GPI_GPE_EN_GPP_F)—Offset 160h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD GPI_GPE_EN_GPP_F_9 GPI_GPE_EN_GPP_F_8 GPI_GPE_EN_GPP_F_7 GPI_GPE_EN_GPP_F_6 GPI_GPE_EN_GPP_F_5 GPI_GPE_EN_GPP_F_4 GPI_GPE_EN_GPP_F_3 GPI_GPE_EN_GPP_F_2 GPI_GPE_EN_GPP_F_1 GPI_GPE_EN_GPP_F_0 GPI_GPE_EN_GPP_F_23 GPI_GPE_EN_GPP_F_22 GPI_GPE_EN_GPP_F_21 GPI_GPE_EN_GPP_F_20 GPI_GPE_EN_GPP_F_19 GPI_GPE_EN_GPP_F_18 GPI_GPE_EN_GPP_F_17 GPI_GPE_EN_GPP_F_16 GPI_GPE_EN_GPP_F_15 GPI_GPE_EN_GPP_F_14 GPI_GPE_EN_GPP_F_13 GPI_GPE_EN_GPP_F_12 GPI_GPE_EN_GPP_F_11 GPI_GPE_EN_GPP_F_10

Bit Default & Field Name (ID): Description Range Access

0h 31:24 Reserved. RO

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_F_23): Applied to 23 RW GPP_F23. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_F_22): Applied to 22 RW GPP_F22. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_F_21): Applied to 21 RW GPP_F21. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_F_20): Applied to 20 RW GPP_F20. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_F_19): Applied to 19 RW GPP_F19. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_F_18): Applied to 18 RW GPP_F18. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_F_17): Applied to 17 RW GPP_F17. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_F_16): Applied to 16 RW GPP_F16. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_F_15): Applied to 15 RW GPP_F15. Same description as bit 0.

672 332219-002

GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_F_14): Applied to 14 RW GPP_F14. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_F_13): Applied to 13 RW GPP_F13. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_F_12): Applied to 12 RW GPP_F12. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_F_11): Applied to 11 RW GPP_F11. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_F_10): Applied to 10 RW GPP_F10. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_F_9): Applied to 9 RW GPP_F9. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_F_8): Applied to 8 RW GPP_F8. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_F_7): Applied to 7 RW GPP_F7. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_F_6): Applied to 6 RW GPP_F6. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_F_5): Applied to 5 RW GPP_F5. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_F_4): Applied to 4 RW GPP_F4. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_F_3): Applied to 3 RW GPP_F3. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_F_2): Applied to 2 RW GPP_F2. Same description as bit 0.

0h GPI General Purpose Events Enable (GPI_GPE_EN_GPP_F_1): Applied to 1 RW GPP_F1. Same description as bit 0.

GPI General Purpose Events Enable (GPI_GPE_EN_GPP_F_0): This bit is used to enable/disable the generation of GPE to cause SCI and/or wake when the

0h corresponding GPI_GPE_STS bit is set. 0 0 = disable GPE generation RW 1 = enable GPE generation Note: The pad must also be routed for GPE functionality in order for GPE to be generated, i.e. the corresponding GPIRoutSCI must be set to ‘1’.

7.4.21 GPI General Purpose Events Enable (GPI_GPE_EN_GPP_G)—Offset 164h

Same definition as GPI_GPE_EN_GPP_F register, except this register applies to GPP_G group (GPP_G[7:0]). Bits corresponding to unimplemented GPP_G are reserved.

7.4.22 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_0)— Offset 400h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

332219-002 673 GPIO for SKL PCH-LP

Default: 44000x00h

3 2 2 2 1 1 840 1 8 4 0 6 2

01000100000000000000001100000000 RSVD RSVD RSVD RXINV PMODE1 PMODE0 RXRAW1 RXEVCFG GPIOTXDIS GPIORXDIS PADRSTCFG RXTXENCFG GPIROUTSCI PREGFRXSEL GPIROUTSMI RXPADSTSEL GPIROUTNMI GPIOTXSTATE GPIORXSTATE GPIROUTIOXAPIC

Bit Default & Field Name (ID): Description Range Access

Pad Reset Config (PADRSTCFG): This register controls which reset is used to reset GPIO pad register fields in PAD_CFG_DW0 and PAD_CFG_DW1 registers. This register can be used for Sx isolation of the associated signal if needed.

1h 00 = RSMRST# 31:30 01 = Host deep reset. This reset occurs when a host reset (with or without power RW cycle) is initiated or a global reset is initiated, except that the reset does not assert when in S3/S4/S5. 10 = PLTRST# 11 = Reserved

RX Pad State Select (RXPADSTSEL): Determines from which node the RX pad state for native function should be taken from. This field only affects the pad state 0h value being fanned out to native function(s) and is not meaningful if the pad is in 29 RW GPIO mode (i.e. Pad Mode = 0). 0 = Raw RX pad state directly from RX buffer 1 = Internal RX pad state (subject to RXINV and PreGfRXSel settings)

RX Raw Override to '1' (RXRAW1): This bit determines if the selected pad state is being overridden to '1'. This field is only applicable when the RX buffer is configured 0h 28 as an input in either GPIO Mode or native function mode. The override takes place at RW the internal pad state directly from buffer and before the RXINV. 0 = No Override 1 = RX drive 1 internally

0h 27 Reserved. RO

RX Level/Edge Configuration (RXEVCFG): Determines if the internal RX pad state (synchronized, filtered vs non-filtered version as determined by PreGfRXSel, and is further subject to RXInv) should be passed on to the next logic stage as is, as a pulse, or level signal. This field does not affect the received pad state (to 2h GPIORXState or native functions) but how the interrupt or wake triggering events 26:25 RW should be delivered to the GPIO Community Controller . 0h = Level 1h = Edge 2h = Drive '0' 3h = Reserved (implement as setting 0h)

Pre Glitch Filter Stage RX Pad State Select (PREGFRXSEL): Determines if the synchronized version of the raw RX pad state should be subjected to glitch filter or 0h not. This field is only applicable when the RX buffer is configured as an input and is 24 not disabled. RO 0 = Select synchronized, non filtered RX pad state 1 = Select synchronized, filtered RX pad state The selected RX pad state can be further subjected to polarity inversion through RXINV

RX Invert (RXINV): This bit determines if the selected pad state should go through the polarity inversion stage. This field is only applicable when the RX buffer is configured as an input in either GPIO Mode or native function mode. The polarity inversion takes place at the mux node of raw vs filtered or non-filtered RX pad state, 0h as determined by PreGfRXsel and RXPadStSel This bit does not affect GPIORXState. 23 During host ownership GPIO Mode, when this bit is set to '1', then the RX pad state is RW inverted as it is sent to the GPIO-to-IOxAPIC, GPE/SCI, SMI, NMI logic or GPI_IS[n] that is using it. This is used to allow active-low and active-high inputs to cause IRQ, SMI#, SCI or NMI. 0 = No inversion 1 = Inversion

674 332219-002

GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

RX/TX Enable Config (RXTXENCFG): This controls the RX and TX buffer enables for the function selected by Pad Mode, but is not applicable when Pad Mode is 0 (i.e. GPIO mode). Hardware shall ensure GPIOTxDis and GPIORxDis are controlling the RX 0h 22:21 and TX buffers when this field is 0 and Pad Mode is 0. RO 00 = Function defined in Pad Mode controls TX and RX Enables 01 = Function controls TX Enable and RX Disabled with RX drive 0 internally 10 = Function controls TX Enable and RX Disabled with RX drive 1 internally 11 = Function controls TX Enabled and RX is always enabled.

GPIO Input Route IOxAPIC (GPIROUTIOXAPIC): Determines if the pad can be routed to cause peripheral IRQ when configured in GPIO input mode. If the pad is not

0h configured in GPIO input mode, this field has no effect. 20 0 = Routing does not cause peripheral IRQ RW 1 = Routing can cause peripheral IRQ Note: This bit does not affect any interrupt status bit within GPIO, but is used as the last qualifier for the peripheral IRQ indication to the intended recipient(s).

GPIO Input Route SCI (GPIROUTSCI): Determines if the pad can be routed to cause SCI when configured in GPIO input mode. If the pad is not configured in GPIO 0h input mode, this field has no effect. 19 0 = Routing does not cause SCI. RW 1 = Routing can cause SCI Note: This bit does not affect any interrupt status bit within GPIO, but is used as the last qualifier for the GPE indication to the intended recipient(s).

GPIO Input Route SMI (GPIROUTSMI): Determines if the pad can be routed to cause SMI when configured in GPIO input mode. If the pad is not configured in GPIO 0h input mode, this field has no effect. 18 0 = Routing does not cause SMI. RO 1 = Routing can cause SMI. Note: This bit does not affect any interrupt status bit within GPIO, but is used as the last qualifier for the SMI indication to the intended recipient(s).

GPIO Input Route NMI (GPIROUTNMI): Determines if the pad can be routed to cause NMI when configured in GPIO input mode. If the pad is not configured in GPIO input mode, this field has no effect. 0h 0 = Routing does not cause NMI. 17 1 = Routing can cause NMI. RO Note: This bit also affects GPI_NMI_STS. If '0', GPI_NMI_STS is always clear. If '1', GPI_NMI_STS could be set (depending on GPIOOwn setting) when there is an event. Whether a NMI indication is generated and sent to the intended recipient(s) is also depending on the corresponding GPI_NMI_EN bit.

0h 16:12 Reserved. RO

-- Pad Mode bit 1 (PMODE1): See Pad Mode bit 0 description. 11 RW

Pad Mode bit 0 (PMODE0): This bit is used in conjunction with Pad Mode bit 1. This two-bit field determines whether the Pad is controlled by GPIO controller logic or one of the native functions muxed onto the Pad. 0h = GPIO control the Pad. 1h = native function 1, if applicable, controls the Pad -- 2h = native function 2, if applicable, controls the Pad. Also used to enable the GPIO 10 RW blink (PWM) capability if applicable (note that not all GPIOs have the blink capability) 3h = native function 3, if applicable, controls the Pad Dedicated (unmuxed) GPIO shall report RO of all 0’s in this register field If GPIO vs. native mode is configured via soft strap, this bit has no effect.

Default value is determined by the default functionality of the pad.

GPIO RX Disable (GPIORXDIS): 0 = Enable the input buffer (active low enable) of

1h the pad. 9 1 = Disable the input buffer of the pad. RW Notes: When the input buffer is disabled, the internal pad state is always driven to '0'.

1h GPIO TX Disable (GPIOTXDIS): 0 = Enable the output buffer (active low enable) 8 of the pad. RW 1 = Disable the output buffer of the pad; i.e. Hi-Z

332219-002 675 GPIO for SKL PCH-LP

Bit Default & Field Name (ID): Description Range Access

0h 7:2 Reserved. RO

0h GPIO RX State (GPIORXSTATE): This is the current internal RX pad state after 1 RO Glitch Filter logic stage and is not affected by PMode and RXINV settings.

0h GPIO TX State (GPIOTXSTATE): 0 = Drive a level '0' to the TX output pad. 0 RW 1 = Drive a level '1' to the TX output pad.

7.4.23 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_0)— Offset 404h

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 30h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000110000 TERM RSVD RSVD INTSEL

Bit Default & Field Name (ID): Description Range Access

0h 31:14 Reserved. RO

Termination (TERM): The Pad Termination state defines the different weak pull-up and pull-down settings that are supported by the buffer. The settings for [13:10] correspond to: 0000: none 0010: 5k pd 0100: 20k pd 1000: none 1001: 1k pu 1011: 2k pu 0h 1010: 5k pu 13:10 1100: 20k pu RW 1101: 1k & 2k pu (in parallel) 1111: Native controller selected by Pad Mode controls the Termination All others reserved. If a reserved value is programmed, pad may malfunction. The setting of this field is applicable in all Pad Mode including GPIO. As each Pad Mode may require different termination and isolation, care must be taken in sw/fw in the transition with appropriate register programming. The actual transition sequence requirement may vary on case by case basis depending on the native functions involved. For example, before changing the pad from output to input direction, pu/pd settings should be programmed first to ensure the input does not float momentarily.

0h 9:8 Reserved. RO

Interrupt Select (INTSEL): The Interrupt Select defines which interrupt line driven from the GPIO Controller toggles when an interrupt is detected on this pad. 30h 0 = Interrupt Line 0 7:0 RO 1 = Interrupt Line 1 .... Up to the max IOxAPIC IRQ supported

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7.4.24 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_1)— Offset 408h

Same description as PAD_CFG_DW0_GPP_F_0.

7.4.25 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_1)— Offset 40Ch

Same description as PAD_CFG_DW1_GPP_F_0. Exception: The default value of the INTSEL bit field in this register is : 31h

7.4.26 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_2)— Offset 410h

Same description as PAD_CFG_DW0_GPP_F_0.

7.4.27 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_2)— Offset 414h

Same description as PAD_CFG_DW1_GPP_F_0. Exception: The default value of the INTSEL bit field in this register is : 32h

7.4.28 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_3)— Offset 418h

Same description as PAD_CFG_DW0_GPP_F_0.

7.4.29 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_3)— Offset 41Ch

Same description as PAD_CFG_DW1_GPP_F_0. Exception: The default value of the INTSEL bit field in this register is : 33h

7.4.30 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_4)— Offset 420h

Same description as PAD_CFG_DW0_GPP_F_0.

7.4.31 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_4)— Offset 424h

Same description as PAD_CFG_DW1_GPP_F_0. Exception: The default value of the INTSEL bit field in this register is : 34h

7.4.32 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_5)— Offset 428h

Same description as PAD_CFG_DW0_GPP_F_0.

332219-002 677 GPIO for SKL PCH-LP

7.4.33 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_5)— Offset 42Ch

Same description as PAD_CFG_DW1_GPP_F_0. Exception: The default value of the INTSEL bit field in this register is : 35h

7.4.34 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_6)— Offset 430h

Same description as PAD_CFG_DW0_GPP_F_0.

7.4.35 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_6)— Offset 434h

Same description as PAD_CFG_DW1_GPP_F_0. Exception: The default value of the INTSEL bit field in this register is : 36h

7.4.36 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_7)— Offset 438h

Same description as PAD_CFG_DW0_GPP_F_0.

7.4.37 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_7)— Offset 43Ch

Same description as PAD_CFG_DW1_GPP_F_0. Exception: The default value of the INTSEL bit field in this register is : 37h

7.4.38 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_8)— Offset 440h

Same description as PAD_CFG_DW0_GPP_F_0.

7.4.39 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_8)— Offset 444h

Same description as PAD_CFG_DW1_GPP_F_0. Exception: The default value of the INTSEL bit field in this register is : 38h

7.4.40 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_9)— Offset 448h

Same description as PAD_CFG_DW0_GPP_F_0.

7.4.41 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_9)— Offset 44Ch

Same description as PAD_CFG_DW1_GPP_F_0. Exception: The default value of the INTSEL bit field in this register is : 39h

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7.4.42 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_10)— Offset 450h

Same description as PAD_CFG_DW0_GPP_F_0.

7.4.43 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_10)— Offset 454h

Same description as PAD_CFG_DW1_GPP_F_0. Exception: The default value of the INTSEL bit field in this register is : 3Ah

7.4.44 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_11)— Offset 458h

Same description as PAD_CFG_DW0_GPP_F_0.

7.4.45 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_11)— Offset 45Ch

Same description as PAD_CFG_DW1_GPP_F_0. Exception: The default value of the INTSEL bit field in this register is : 3Bh

7.4.46 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_12)— Offset 460h

Same description as PAD_CFG_DW0_GPP_F_0.

7.4.47 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_12)— Offset 464h

Same description as PAD_CFG_DW1_GPP_F_0. Exception: The default value of the INTSEL bit field in this register is : 3Ch

7.4.48 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_13)— Offset 468h

Same description as PAD_CFG_DW0_GPP_F_0.

7.4.49 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_13)— Offset 46Ch

Same description as PAD_CFG_DW1_GPP_F_0. Exception: The default value of the INTSEL bit field in this register is : 3Dh

7.4.50 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_14)— Offset 470h

Same description as PAD_CFG_DW0_GPP_F_0.

332219-002 679 GPIO for SKL PCH-LP

7.4.51 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_14)— Offset 474h

Same description as PAD_CFG_DW1_GPP_F_0. Exception: The default value of the INTSEL bit field in this register is : 3Eh

7.4.52 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_15)— Offset 478h

Same description as PAD_CFG_DW0_GPP_F_0.

7.4.53 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_15)— Offset 47Ch

Same description as PAD_CFG_DW1_GPP_F_0. Exception: The default value of the INTSEL bit field in this register is : 3Fh

7.4.54 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_16)— Offset 480h

Same description as PAD_CFG_DW0_GPP_F_0.

7.4.55 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_16)— Offset 484h

Same description as PAD_CFG_DW1_GPP_F_0. Exception: The default value of the INTSEL bit field in this register is : 40h

7.4.56 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_17)— Offset 488h

Same description as PAD_CFG_DW0_GPP_F_0.

7.4.57 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_17)— Offset 48Ch

Same description as PAD_CFG_DW1_GPP_F_0. Exception: The default value of the INTSEL bit field in this register is : 41h

7.4.58 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_18)— Offset 490h

Same description as PAD_CFG_DW0_GPP_F_0.

7.4.59 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_18)— Offset 494h

Same description as PAD_CFG_DW1_GPP_F_0. Exception: The default value of the INTSEL bit field in this register is : 42h

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7.4.60 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_19)— Offset 498h

Same description as PAD_CFG_DW0_GPP_F_0.

7.4.61 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_19)— Offset 49Ch

Same description as PAD_CFG_DW1_GPP_F_0. Exception: The default value of the INTSEL bit field in this register is : 43h

7.4.62 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_20)— Offset 4A0h

Same description as PAD_CFG_DW0_GPP_F_0.

7.4.63 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_20)— Offset 4A4h

Same description as PAD_CFG_DW1_GPP_F_0. Exception: The default value of the INTSEL bit field in this register is : 44h

7.4.64 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_21)— Offset 4A8h

Same description as PAD_CFG_DW0_GPP_F_0.

7.4.65 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_21)— Offset 4ACh

Same description as PAD_CFG_DW1_GPP_F_0. Exception: The default value of the INTSEL bit field in this register is : 45h

7.4.66 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_22)— Offset 4B0h

Same description as PAD_CFG_DW0_GPP_F_0.

7.4.67 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_22)— Offset 4B4h

Same description as PAD_CFG_DW0_GPP_F_0. Exception: The default value of the INTSEL bit field in this register is : 46h

7.4.68 Pad Configuration DW0 (PAD_CFG_DW0_GPP_F_23)— Offset 4B8h

Same description as PAD_CFG_DW0_GPP_F_0.

332219-002 681 GPIO for SKL PCH-LP

7.4.69 Pad Configuration DW1 (PAD_CFG_DW1_GPP_F_23)— Offset 4BCh

Same description as PAD_CFG_DW1_GPP_F_0. Exception: The default value of the INTSEL bit field in this register is : 47h

7.4.70 Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_0)— Offset 4C4h

Same description as PAD_CFG_DW1_GPP_F_0.

7.4.71 Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_1)— Offset 4C8h

Same description as PAD_CFG_DW0_GPP_F_0.

7.4.72 Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_1)— Offset 4CCh

Same description as PAD_CFG_DW1_GPP_F_0. Exception: The default value of the INTSEL bit field in this register is : 49h

7.4.73 Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_2)— Offset 4D0h

Same description as PAD_CFG_DW0_GPP_F_0.

7.4.74 Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_2)— Offset 4D4h

Same description as PAD_CFG_DW1_GPP_F_0. Exception: The default value of the INTSEL bit field in this register is : 4Ah

7.4.75 Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_3)— Offset 4D8h

Same description as PAD_CFG_DW0_GPP_F_0.

7.4.76 Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_3)— Offset 4DCh

Same description as PAD_CFG_DW1_GPP_F_0. Exception: The default value of the INTSEL bit field in this register is : 4Bh

7.4.77 Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_4)— Offset 4E0h

Same description as PAD_CFG_DW0_GPP_F_0.

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7.4.78 Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_4)— Offset 4E4h

Same description as PAD_CFG_DW1_GPP_F_0. Exception: The default value of the INTSEL bit field in this register is : 4Ch

7.4.79 Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_5)— Offset 4E8h

Same description as PAD_CFG_DW0_GPP_F_0.

7.4.80 Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_5)— Offset 4ECh

Same description as PAD_CFG_DW1_GPP_F_0. Exception: The default value of the INTSEL bit field in this register is : 4Dh

7.4.81 Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_6)— Offset 4F0h

Same description as PAD_CFG_DW0_GPP_F_0.

7.4.82 Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_6)— Offset 4F4h

Same description as PAD_CFG_DW1_GPP_F_0. Exception: The default value of the INTSEL bit field in this register is : 4Eh

7.4.83 Pad Configuration DW0 (PAD_CFG_DW0_GPP_G_7)— Offset 4F8h

Same description as PAD_CFG_DW0_GPP_F_0.

7.4.84 Pad Configuration DW1 (PAD_CFG_DW1_GPP_G_7)— Offset 4FCh

Same description as PAD_CFG_DW1_GPP_F_0. Exception: The default value of the INTSEL bit field in this register is : 4Fh

332219-002 683 GPIO for SKL PCH-LP

§ §

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8 SMBus Interface

8.1 SMBus Configuration Registers Summary

Table 8-1. Summary of SMBus Configuration Registers

Offset Offset Default Register Name (ID)—Offset Start End Value

0h 1h Vendor ID (VID)—Offset 0h 8086h

9D23h / LP 2h 3h Device ID (DID)—Offset 2h A123 / H

4h 5h Command (CMD)—Offset 4h 0h

6h 7h Device Status (DS)—Offset 6h 280h

8h 8h Revision ID (RID)—Offset 8h 0h

9h 9h Programming Interface (PI)—Offset 9h 0h

Ah Ah Sub Class Code (SCC)—Offset Ah 5h

Bh Bh Base Class Code (BCC)—Offset Bh Ch

10h 13h SMBus Memory Base Address_31_0 (SMBMBAR_31_0)—Offset 10h 4h

14h 17h SMBus Memory Base Address_63_32 (SMBMBAR_63_32)—Offset 14h 0h

20h 23h SMB Base Address (SBA)—Offset 20h 1h

2Ch 2Dh SVID (SVID)—Offset 2Ch 0h

2Eh 2Fh SID (SID)—Offset 2Eh 0h

3Ch 3Ch Interrupt Line (INTLN)—Offset 3Ch 0h

3Dh 3Dh Interrupt Pin (INTPN)—Offset 3Dh 1h

40h 40h Host Configuration (HCFG)—Offset 40h 0h

50h 53h TCO Base Address (TCOBASE)—Offset 50h 1h

54h 57h TCO Control (TCOCTL)—Offset 54h 0h

80h 83h SMBus Power Gating (SMBSM)—Offset 80h 40000h

8.1.1 Vendor ID (VID)—Offset 0h

Access Method

Type: CFG Register Device: 31 (Size: 16 bits) Function: 4

Default: 8086h

15 12 8 4 0

1000000010000110 VID

332219-002 685 SMBus Interface

Bit Default & Field Name (ID): Description Range Access

8086h Vendor ID (VID): Value indicates Intel as the vendor 15:0 RO

8.1.2 Device ID (DID)—Offset 2h

Access Method

Type: CFG Register Device: 31 (Size: 16 bits) Function: 4

Default: 9C22h

15 12 8 4 0

1001110000100010 DID

Bit Default & Field Name (ID): Description Range Access

9D23h / LP Device ID (DID): Indicates the value assigned to the PCH SMBus controller. 15:0 A123 / H RO

8.1.3 Command (CMD)—Offset 4h

Access Method

Type: CFG Register Device: 31 (Size: 16 bits) Function: 4

Default: 0h

15 12 8 4 0

0000000000000000 FBE PER SCE BME MSE WCC IOSE INTD RSVD PMWE SERRE VGAPS

Bit Default & Field Name (ID): Description Range Access

0h 15:11 Reserved. RO

0h Interrupt Disable (INTD): 1 = Disables SMBus to assert its PIRQB# signal. 10 RW Defaults to 0.

0h Fast Back to Back Enable (FBE): Reserved as 0. Read Only. 9 RW

0h SERR# Enable (SERRE): 1 = Enables SERR# generation 8 RW

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Bit Default & Field Name (ID): Description Range Access

0h Wait Cycle Control (WCC): Reserved as 0. Read Only. 7 RW

0h Parity Error Response (PER): 1 = Sets Detected Parity Error bit when parity error 6 RW is detected

0h VGA Palette Snoop (VGAPS): Reserved as 0. Read Only. 5 RW

0h Postable Memory Write Enable (PMWE): Reserved as 0. Read Only. 4 RW

0h Special Cycle Enable (SCE): Reserved as 0. Read Only. 3 RW

0h Bus Master Enable (BME): Reserved as 0. Read Only. 2 RW

0h Memory Space Enable (MSE): 1= Enables memory mapped config space. 1 RW

0h I/O Space Enable (IOSE): 1= enables access to the SM Bus I/O space registers as 0 RW defined by the Base Address Register.

8.1.4 Device Status (DS)—Offset 6h

Access Method

Type: CFG Register Device: 31 (Size: 16 bits) Function: 4

Default: 280h

15 12 8 4 0

0000001010000000 CLI RTA STA FBC SSE DPE UDF RMA INTS DEVT DPED RSVD C_66M

Bit Default & Field Name (ID): Description Range Access

0h Detected Parity Error (DPE): 1 = Parity error detected 15 RW/1C

0h Signaled System Error (SSE): 1 = System error detected 14 RW/1C

0h Received Master Abort (RMA): Reserved as 0. 13 RO

0h Received Target Abort (RTA): Reserved as '0'. 12 RO

0h Signaled Target-Abort Status (STA): Reserved as 0. 11 RO

DEVSEL# Timing Status (DEVT): This 2-bit field defines the timing for DEVSEL# 1h assertion. These read only bits indicate the Intel PCH's DEVSEL# timing when 10:9 RO performing a positive decode. Note: Intel PCH generates DEVSEL# with medium time.

332219-002 687 SMBus Interface

Bit Default & Field Name (ID): Description Range Access

0h Data Parity Error Detected (DPED): Reserved as 0. 8 RO

1h Fast Back-to-Back Capable (FBC): Reserved as '1'. 7 RO

0h User Definable Features (UDF): Reserved as 0. 6 RO

0h 66 MHz Capable (C_66M): Reserved as 0. 5 RO

0h Capabilities List Indicator (CLI): Hardwired to 0 because there are no capability 4 RO list structures in this function.

0h Interrupt Status (INTS): This bit indicates that an interrupt is pending. It is 3 RO independent from the state of the Interrupt Enable bit in the command register.

0h 2:0 Reserved. RO

8.1.5 Revision ID (RID)—Offset 8h

Access Method

Type: CFG Register Device: 31 (Size: 8 bits) Function: 4

Default: 0h

74 0

00000000 RID

Bit Default & Field Name (ID): Description Range Access

0h Revision ID (RID): Indicates stepping of the host controller. Refer to Device and 7:0 RO Revision ID table in Vol1 of the EDS for specific value.

8.1.6 Programming Interface (PI)—Offset 9h

Access Method

Type: CFG Register Device: 31 (Size: 8 bits) Function: 4

Default: 0h

74 0

00000000 PI

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Bit Default & Field Name (ID): Description Range Access

0h Programming Interface (PI): No programming interface defined. 7:0 RO

8.1.7 Sub Class Code (SCC)—Offset Ah

Access Method

Type: CFG Register Device: 31 (Size: 8 bits) Function: 4

Default: 5h

74 0

00000101 SCC

Bit Default & Field Name (ID): Description Range Access

5h Sub Class Code (SCC): A value of 05h indicates that this device is a SM Bus serial 7:0 RO controller.

8.1.8 Base Class Code (BCC)—Offset Bh

Access Method

Type: CFG Register Device: 31 (Size: 8 bits) Function: 4

Default: Ch

74 0

00001100 BCC

Bit Default & Field Name (ID): Description Range Access

Ch Base Class Code (BCC): A value of 0Ch indicates that this device is a serial 7:0 RO controller

8.1.9 SMBus Memory Base Address_31_0 (SMBMBAR_31_0)— Offset 10h

Access Method

Type: CFG Register Device: 31 (Size: 32 bits) Function: 4

332219-002 689 SMBus Interface

Default: 4h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000100 BA MSI PREF ADDRNG Hardwired_0

Bit Default & Field Name (ID): Description Range Access

0h Base Address (BA): Provides the 32 byte system memory base address for the 31:8 RW Intel PCH SMB logic.

0h Hardwired_0 (Hardwired_0): Hardwired to 0. 7:4 RO

0h Prefetchable (PREF): Hardwired to 0. Indicated that SMBMBAR is not pre- 3 RO fetchable

2h Address Range (ADDRNG): Indicates that this SMBMBAR can be located anywhere 2:1 RO in 64 bit address space

0h Memory Space Indicator (MSI): Indicates that the SMB logic is memory mapped. 0 RO

8.1.10 SMBus Memory Base Address_63_32 (SMBMBAR_63_32)—Offset 14h

Access Method

Type: CFG Register Device: 31 (Size: 32 bits) Function: 4

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 BA

Bit Default & Field Name (ID): Description Range Access

0h Base Address (BA): Bits 63-32 of SMbus Memory Base Address 31:0 RW

8.1.11 SMB Base Address (SBA)—Offset 20h

Access Method

Type: CFG Register Device: 31 (Size: 32 bits) Function: 4

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Default: 1h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000001 BA IOSI RSVD RSVD

Bit Default & Field Name (ID): Description Range Access

0h 31:16 Reserved. RO

0h Base Address (BA): Provides the 32 byte t system I/O base address for the SMB 15:5 RW logic.

0h 4:1 Reserved. RO

1h IO Space Indicator (IOSI): This read-only bit always is 1, indicating that the SMB 0 RO logic is I/O mapped.

8.1.12 SVID (SVID)—Offset 2Ch

Access Method

Type: CFG Register Device: 31 (Size: 16 bits) Function: 4

Default: 0h

15 12 8 4 0

0000000000000000 SVID

Bit Default & Field Name (ID): Description Range Access

SVID (SVID): BIOS sets the value in this register to identify the Subsystem Vendor 0h ID. The SMBus SVID register, in combination with the SMBus Subsystem ID register, 15:0 enables the operating system to distinguish each subsystem from the others. Note: RW/O The software can write to this register only once per core well reset. Writes should be done as a single 16-bit cycle.

8.1.13 SID (SID)—Offset 2Eh

Access Method

Type: CFG Register Device: 31 (Size: 16 bits) Function: 4

Default: 0h

332219-002 691 SMBus Interface

15 12 8 4 0

0000000000000000 SID

Bit Default & Field Name (ID): Description Range Access

SID (SID): BIOS can write to this register to identify the Subsystem ID. The SID 0h 15:0 register, in combination with the SVID, enable the operating system to distinguish RW/O each subsystem from other(s). Note: The software can write to this register only once per core well reset. Writes should be done as a single 16-bit cycle.

8.1.14 Interrupt Line (INTLN)—Offset 3Ch

Access Method

Type: CFG Register Device: 31 (Size: 8 bits) Function: 4

Default: 0h

74 0

00000000 INTLN

Bit Default & Field Name (ID): Description Range Access

0h Interrupt Line (INTLN): This data is not used by the hardware. It is to 7:0 communicate to software the interrupt line that the interrupt pin is connected to RW PIRQB#.

8.1.15 Interrupt Pin (INTPN)—Offset 3Dh

Access Method

Type: CFG Register Device: 31 (Size: 8 bits) Function: 4

Default: 1h

74 0

00000001 INTPN

Bit Default & Field Name (ID): Description Range Access

1h Interrupt Pin (INTPN): This defines the interrupt pin to be used by the SMBus 7:0 controller. Bits : Pins 0h : No Interrupt 1h : INTA# 2h : INTB# 3h : INTC# 4h : RW/O INTD# 5h-Fh : Reserved

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8.1.16 Host Configuration (HCFG)—Offset 40h

Access Method

Type: CFG Register Device: 31 (Size: 8 bits) Function: 4

Default: 0h

74 0

00000000 SSEN RSVD I2CEN HSTEN SPDWD SSRESET

Bit Default & Field Name (ID): Description Range Access

0h 7:5 Reserved. RO

SPD Write Disable (SPDWD): When this bit is set to 1, writes to SMBus addresses 0h 50h – 57h are disabled. Note: This bit is R/WO and will be reset on PLTRST# 4 assertion. This bit should be set by BIOS to ‘1’. Software can only program this bit RW/O when both the START bit and Host Busy bit are ‘0’; otherwise, the write may result in undefined behavior.

0h SSRESET (SSRESET): Soft SMBUS Reset: When this bit is 1, the SMbus state 3 machine and logic in PCH is reset. The HW will reset this bit to 0 when reset operation RW is completed.

0h I2C_EN (I2CEN): When this bit is 1, the Intel PCH is enabled to communicate with 2 I2C devices. This will change the formatting of some commands. When this bit is 0, RW behavior is for SMBus.

0h SMB_SMI_EN (SSEN): When this bit is set, any source of an SMB interrupt will 1 RW instead be routed to generate an SMI#.

HST_EN (HSTEN): When set, the SMB Host Controller interface is enabled to 0h execute commands. The HST_INT_EN bit needs to be enabled in order for the SMB 0 RW Host Controller to interrupt or SMI#. Additionally, the SMB Host Controller will not respond to any new requests until all interrupt requests have been cleared.

8.1.17 TCO Base Address (TCOBASE)—Offset 50h

Access Method

Type: CFG Register Device: 31 (Size: 32 bits) Function: 4

Default: 1h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000001 IOS RSVD RSVD TCOBA

332219-002 693 SMBus Interface

Bit Default & Field Name (ID): Description Range Access

0h 31:16 Reserved. RO

0h TCO Base Address (TCOBA): Provides the 32 bytes of I/O space for TCO logic, 15:5 RW mappable anywhere in the 64k I/O space on 32-byte boundaries.

0h 4:1 Reserved. RO

1h I/O Space (IOS): Indicates an I/O Space 0 RO

8.1.18 TCO Control (TCOCTL)—Offset 54h

Access Method

Type: CFG Register Device: 31 (Size: 32 bits) Function: 4

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD TCO_BASE_EN TCO_BASE_LOCK

Bit Default & Field Name (ID): Description Range Access

0h 31:9 Reserved. RO

0h TCO Base Enable (TCO_BASE_EN): When set, decode of the I/O range pointed to 8 RW by the TCO base register is enabled.

0h 7:1 Reserved. RO

TCO Base Lock (TCO_BASE_LOCK): When set to 1, this bit locks down the TCO 0h Base Address Register (TCOBASE) at offset 50h. The Base Address Field becomes 0 read-only. This bit becomes locked when a value of 1b is written to it. Writes of 0 to RW/O this bit are always ignored. Once locked by writing 1, the only way to clear this bit is to perform a platform reset.

8.1.19 SMBus Power Gating (SMBSM)—Offset 80h

Access Method

Type: CFG Register Device: 31 (Size: 32 bits) Function: 4

Default: 40000h

694 332219-002

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3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000001000000000000000000 RSVD RSVD PGCBDCGDis

Bit Default & Field Name (ID): Description Range Access

0h 31:19 Reserved. RO

1h PGCB DCG Disable (PGCBDCGDis): Setting this bit will disable the SMBus dynamic 18 RW clock gating.

0h 17:0 Reserved. RO

8.2 SMBus I/O and Memory Mapped I/O Registers Summary

The SMBus registers can be accessed through I/O BAR or Memory BAR registers in PCI configuration space. The offsets are the same for both I/O and Memory Mapped I/O registers.

Table 8-2. Summary of SMBus I/O and Memory Mapped I/O Registers

Offset Offset Default Register Name (ID)—Offset Start End Value

0h 0h Host Status Register Address (HSTS)—Offset 0h 0h

2h 2h Host Control Register (HCTL)—Offset 2h 0h

3h 3h Host Command Register (HCMD)—Offset 3h 0h

4h 4h Transmit Slave Address Register (TSA)—Offset 4h 0h

5h 5h Data 0 Register (HD0)—Offset 5h 0h

6h 6h Data 1 Register (HD1)—Offset 6h 0h

7h 7h Host Block Data (HBD)—Offset 7h 0h

8h 8h Packet Error Check Data Register (PEC)—Offset 8h 0h

9h 9h Receive Slave Address Register (RSA)—Offset 9h 44h

Ah Bh Slave Data Register (SD)—Offset Ah 0h

Ch Ch Auxiliary Status (AUXS)—Offset Ch 0h

Dh Dh Auxiliary Control (AUXC)—Offset Dh 0h

Eh Eh SMLINK_PIN_CTL Register (SMLC)—Offset Eh 4h

Fh Fh SMBUS_PIN_CTL Register (SMBC)—Offset Fh 4h

10h 10h Slave Status Register (SSTS)—Offset 10h 0h

11h 11h Slave Command Register (SCMD)—Offset 11h 0h

14h 14h Notify Device Address Register (NDA)—Offset 14h 0h

16h 16h Notify Data Low Byte Register (NDLB)—Offset 16h 0h

17h 17h Notify Data High Byte Register (NDHB)—Offset 17h 0h

332219-002 695 SMBus Interface

8.2.1 Host Status Register Address (HSTS)—Offset 0h

All status bits are set by hardware and cleared by the software writing a one to the particular bit position. Writing a zero to any bit position has no affect.

Access Method

Type: IO Register Device: 31 (Size: 8 bits) Function: 4

Default: 0h

74 0

00000000 IUS BDS FAIL INTR BERR HBSY DERR SMSTS

Bit Default & Field Name (ID): Description Range Access

BYTE_DONE_STS (BDS): This bit will be set to 1 when the host controller has received a byte (for Block Read commands) or if it has completed transmission of a byte (for Block Write commands) when the 32-byte buffer is not being used. Note that this bit will be set, even on the last byte of the transfer. Software clears the bit by writing a 1 to the bit position. This bit has no meaning for block transfers when 0h 7 the 32- byte buffer is enabled. Note: When the last byte of a block message is RW/1C received, the host controller will set this bit. However, it will not immediately set the INTR bit (bit 1 in this register). When the interrupt handler clears the BYTE_DONE_STS bit, the message is considered complete, and the host controller will then set the INTR bit (and generate another interrupt). Thus, for a block message of n bytes, the Intel PCH will generate n+1 interrupts. The interrupt handler needs to be implemented to handle these cases.

In Use Status (IUS): After a full PCI reset, a read to this bit returns a 0. After the first read, subsequent reads will return a 1. A write of a 1 to this bit will reset the 0h next read value to 0. Writing a 0 to this bit has no effect. Software can poll this bit 6 RW until it reads a 0, and will then own the usage of the host controller. This bit has no other effect on the hardware, and is only used as semaphore among various independent software threads that may need to use the Intel PCHs SMBus logic.

0h SMBALERT_STS (SMSTS): Intel PCH sets this bit to a 1 to indicates source of the 5 interrupt or SMI# was the SMBAlert# signal. Software resets this bit by writing a 1 to RW/1C this location. This bit should also be cleared by RSMRST# (but not PLTRST#).

0h Failed (FAIL): When set, this indicates that the source of the interrupt or SMI# was 4 a failed bus transaction. This is set in response to the KILL bit being set to terminate RW/1C the host transaction.

0h Bus Error (BERR): When set, this indicates the source of the interrupt or SMI# was 3 RW/1C a transaction collision.

0h Device Error (DERR): When set, this indicates that the source of the interrupt or 2 SMI# was due one of the following: Illegal Command Field Unclaimed Cycle (host RW/1C initiated) Host Device Time-out Error. CRC Error

0h Interrupt (INTR): When set, this indicates that the source of the interrupt or SMI# 1 RW/1C was the successful completion of its last command.

Host Busy (HBSY): A 1 indicates that the Intel PCH is running a command from the 0h host interface. No SMB registers should be accessed while this bit is set. Exception: 0 The BLOCK DATA REGISTER can be accessed when this bit is set ONLY when the RW/1C SMB_CMD bits (in Host control register) are programmed for Block command or I2C Read command. This is necessary in order to check the DONE_STS bit.

8.2.2 Host Control Register (HCTL)—Offset 2h

Note: A read to this register will clear the pointer in the 32-byte buffer.

696 332219-002

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Access Method

Type: IO Register Device: 31 (Size: 8 bits) Function: 4

Default: 0h

74 0

00000000 KILL START INTREN PEC_EN SMB_CMD LAST_BYTE

Bit Default & Field Name (ID): Description Range Access

PEC_EN (PEC_EN): When set to 1, this bit causes the host controller to perform the SMBus transaction with the Packet Error Checking phase appended. For writes, the 0h value of the PEC byte is transferred from the PEC Register. For reads, the PEC byte is 7 RW loaded in to the PEC Register. When this bit is cleared to 0, the SMBus host controller does not perform the transaction with the PEC phase appended. This bit must be written prior to the write in which the START bit is set.

START (START): This write-only bit is used to initiate the command described in the 0h SMB_CMD field. All registers should be setup prior to writing a 1 to this bit position. 6 RW This bit always reads zero. The HOST_BUSY bit in the Host Status register (offset 00h) can be used to identify when the Intel PCH has finished the command.

LAST_BYTE (LAST_BYTE): This bit is used for I2C Read commands. Software sets this bit to indicate that the next byte will be the last byte to be received for the block. 0h This causes the PCH to send a NACK (instead of an ACK) after receiving the last byte. 5 Note: This bit may be set when the TCO timer causes the SECOND_TO_STS bit to be RW set. SW should clear the LAST_BYTE bit (if it is set) before starting any new command. Note: In addition to I2C Read Commands, the LAST_BYTE bit will also cause Block Read/Write cycles to stop prematurely (at the end of the next byte).

332219-002 697 SMBus Interface

Bit Default & Field Name (ID): Description Range Access

SMB_CMD (SMB_CMD): As shown by the bit encoding below, indicates which command the Intel PCH is to perform. If enabled, the Intel PCH will generate an interrupt or SMI# when the command has completed If the value is for a non- supported or reserved command, the Intel PCH will set the device error (DEV_ERR) status bit and generate an interrupt when the START bit is set. The Intel PCH will perform no command, and will not operate until DEV_ERR is cleared. Val - Command Description: 000 - Quick: The slave address and read/write value (bit 0) are stored in the tx slave address register. 001 - Byte: This command uses the transmit slave address and command registers. Bit 0 of the slave address register determines if this is a read or write command. 010 - Byte Data: This command uses the transmit slave address, command, and DATA0 registers. Bit 0 of the slave address register determines if this is a read or write command. If it is a read, the DATA0 register will contain the read data. 011 - Word Data: This command uses the transmit slave address, command, DATA0 and DATA1 registers. Bit 0 of the slave address register determines if this is a read or write command. If it is a read, after the command completes the DATA0 and DATA1 registers will contain the read data. 100 - Process Call: This command uses the transmit slave address, command, DATA0 and DATA1 0h registers. Bit 0 of the slave address register determines if this is a read or write 4:2 command. After the command completes, the DATA0 and DATA1 registers will RW contain the read data. 101 - Block: This command uses the transmit slave address,command, and DATA0 registers, and the Block Data Byte register. For block write, the count is stored in the DATA0 register and indicates how many bytes of data will be transferred. For block reads, the count is received and stored in the DATA0 register. Bit 0 of the slave address register selects if this is a read or write command. For writes, data is retrieved from the first n (where n is equal to the specified count) addresses of the SRAM array. For reads, the data is stored in the Block Data Byte register. 110 - I2C Read: This command uses the transmit slave address, command, DATA0, DATA1 registers, and the Block Data Byte register. The read data is stored in the Block Data Byte register. The Intel PCH will continue reading data until the NAK is received. 111 - Block-Process: This command uses the transmit slave address, command, DATA0 and the Block Data Byte register. For block write, the count is stored in the DATA0 register and indicates how many bytes of data will be transferred. For block read, the count is received and stored in the DATA0 register. Bit 0 of the slave address register always indicate a write command. For writes, data is retrieved from the first m (where m is equal to the specified count) addresses of the SRAM array. For reads, the data is stored in the Block Data Byte register. Note: E32B bit in the Auxiliary Control Register must be set for this command to work.

KILL (KILL): When set, kills the current host transaction taking place, sets the 0h 1 FAILED status bit, and asserts the interrupt (or SMI#) selected by the SMB_INTRSEL RW field. This bit, once set, must be cleared to allow the SMB Host Controller to function normally.

0h INTREN (INTREN): Enable the generation of an interrupt or SMI# upon the 0 RW completion of the command.

8.2.3 Host Command Register (HCMD)—Offset 3h

Access Method

Type: IO Register Device: 31 (Size: 8 bits) Function: 4

Default: 0h

74 0

00000000 HCMD

Bit Default & Field Name (ID): Description Range Access

0h Host Command Register (HCMD): This eight bit field is transmitted by the host 7:0 controller in the command field of the SMB protocol during the execution of any RW command.

698 332219-002

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8.2.4 Transmit Slave Address Register (TSA)—Offset 4h

This register is transmitted by the host controller in the slave address field of the SMB protocol. This is the address of the target.

Access Method

Type: IO Register Device: 31 (Size: 8 bits) Function: 4

Default: 0h

74 0

00000000 RW ADDR

Bit Default & Field Name (ID): Description Range Access

0h ADDRESS (ADDR): 7-bit address of the targeted slave. Note: Writes to TSA values 7:1 of A0h - AEh are blocked depending on the setting of the SPD write disable bit in RW HCFG - HostConfiguration.

0h RW (RW): Direction of the host transfer. 1 = read, 0 = write 0 RW

8.2.5 Data 0 Register (HD0)—Offset 5h

Access Method

Type: IO Register Device: 31 (Size: 8 bits) Function: 4

Default: 0h

74 0

00000000 DATA0_COUNT

Bit Default & Field Name (ID): Description Range Access

DATA0/COUNT (DATA0_COUNT): This field contains the eight bit data sent in the 0h DATA0 field of the SMB protocol. For block write commands, this register reflects the 7:0 number of bytes to transfer. This register should be programmed to a value between RW 1 and 32 for block counts. A count of 0 or a count above 32 will result in unpredictable behavior. The host controller does not check or log illegal block counts.

8.2.6 Data 1 Register (HD1)—Offset 6h

Access Method

332219-002 699 SMBus Interface

Type: IO Register Device: 31 (Size: 8 bits) Function: 4

Default: 0h

74 0

00000000 DATA1

Bit Default & Field Name (ID): Description Range Access

0h DATA1 (DATA1): This eight bit register is transmitted in the DATA1 field of the SMB 7:0 RW protocol during the execution of any command.

8.2.7 Host Block Data (HBD)—Offset 7h

Access Method

Type: IO Register Device: 31 (Size: 8 bits) Function: 4

Default: 0h

74 0

00000000 BDTA

Bit Default & Field Name (ID): Description Range Access

Block Data (BDTA): This is either a register, or a pointer into a 32- byte block array, depending upon whether the E32B bit is set in the Auxiliary Control register. When the E32B bit is cleared, this is a register containing a byte of data to be sent on a block write or read from on a block read, just as it behaved on the INTEL PCH. When the E32B bit is set, reads and writes to this register are used to access the 32-byte block data storage array. An internal index pointer is used to address the array, which is reset to 0 by reading the HCTL register (offset 02h). The index pointer then increments automatically upon each access to this register. The transfer of block data into (read) or out of (write) this storage array during an SMBus transaction always starts at index address 0. When the E2B bit is set, for writes, software will write up to 32-bytes to this register as part of the setup for the command. After the Host Controller has sent the Address, Command, and Byte Count fields, it will send the 0h bytes in the SRAM pointed to by this register. When the E2B bit is cleared for writes, 7:0 RW software will place a single byte in this register. After the host controller has sent the address, command, and byte count fields, it will send the byte in this register. If there is more data to send, software will write the next series of bytes to the SRAM pointed to by this register and clear the DONE_STS bit. The controller will then send the next byte. During the time between the last byte being transmitted to the next byte being transmitted, the controller will insert wait-states on the interface. When the E2B bit is set for reads, after receiving the byte count into the Data0 register, the first series of data bytes go into the SRAM pointed to by this register. If the byte count has been exhausted or the 32-byte SRAM has been filled, the controller will generate an SMI# or interrupt (depending on configuration) and set the DONE_STS bit. Software will then read the data. During the time between when the last byte is read from the SRAM to when the DONE_STS bit is cleared, the controller will insert waitstates on the interface.

700 332219-002

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8.2.8 Packet Error Check Data Register (PEC)—Offset 8h

Access Method

Type: IO Register Device: 31 (Size: 8 bits) Function: 4

Default: 0h

74 0

00000000 PEC_DATA

Bit Default & Field Name (ID): Description Range Access

PEC_DATA (PEC_DATA): This 8-bit register is written with the SMBus PEC data 0h prior to a write transaction. For read transactions, the PEC data is loaded from the 7:0 SMBus into this register and is then read by software. Software must ensure that the RW INUSE_STS bit is properly maintained to avoid having this field over-written by a write transaction following a read transaction.

8.2.9 Receive Slave Address Register (RSA)—Offset 9h

Access Method

Type: IO Register Device: 31 (Size: 8 bits) Function: 4

Default: 44h

74 0

01000100 RSVD SA_6_0

Bit Default & Field Name (ID): Description Range Access

0h 7 Reserved. RO

SLAVE_ADDR[6:0] (SA_6_0): This field is the slave address that the Intel PCH 44h decodes for read and write cycles. The default is not 0 so that it can respond even 6:0 RW before the CPU comes up (or if the CPU is dead). This register is reset by RSMRST#, but not by PLTRST#.

8.2.10 Slave Data Register (SD)—Offset Ah

Access Method

332219-002 701 SMBus Interface

Type: IO Register Device: 31 (Size: 16 bits) Function: 4

Default: 0h

15 12 8 4 0

0000000000000000 SD_15_0

Bit Default & Field Name (ID): Description Range Access

SLAVE_DATA[15:0] (SD_15_0): This field is the 16-bit data value written by the 0h external SMBus master. The CPU can then read the value from this register. This 15:0 register is reset by RSMRST#, but not by PLTRST#. SLAVE_DATA(7:0) corresponds to RW the Data Message Byte 0 at Slave Write Register 4 in the table. SLAVE_(15:8) corresponds to the Data Message Byte 1 at Slave Write Register 5 in the table.

8.2.11 Auxiliary Status (AUXS)—Offset Ch

All bits in this register are in the core well.

Access Method

Type: IO Register Device: 31 (Size: 8 bits) Function: 4

Default: 0h

74 0

00000000 CRCE RSVD RSVD Reserved Reserved Reserved

Bit Default & Field Name (ID): Description Range Access

0h 7:5 Reserved. RO

0h Reserved 4 RO

0h Reserved 3 RO

702 332219-002

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Bit Default & Field Name (ID): Description Range Access

0h Reserved 2 RO

0h 1 Reserved. RO

CRC Error (CRCE): This bit is set if a received message contained a CRC error. When 0h this bit is set, the DERR bit of the host status register will also be set. This bit will be 0 set by the controller if a software abort occurs in the middle of the CRC portion of the RW/1C cycle or an abort happens after Intel PCH has received the final data bit transmitted by external slave.

8.2.12 Auxiliary Control (AUXC)—Offset Dh

All bits in this register are in the resume well.

Access Method

Type: IO Register Device: 31 (Size: 8 bits) Function: 4

Default: 0h

74 0

00000000 AAC E32B RSVD

Bit Default & Field Name (ID): Description Range Access

0h 7:2 Reserved. RO

Enable 32-byte Buffer (E32B): When set, the Host Block Data register is a pointer 0h into a 32-byte buffer, as opposed to a single register. This enables the block 1 RW commands to transfer or receive up to 32-bytes before the Intel PCH generates an interrupt.

Automatically Append CRC (AAC): When set, the Intel PCH will automatically 0h 0 append the CRC. This bit must not be changed during SM Bus transactions, or RW undetermined behavior will result. It should be programmed only once during the lifetime of the function.

8.2.13 SMLINK_PIN_CTL Register (SMLC)—Offset Eh

Note: This register is in the resume well and is reset by RSMRST#

Access Method

Type: IO Register Device: 31 (Size: 8 bits) Function: 4

Default: 4h

332219-002 703 SMBus Interface

74 0

00000100 RSVD SMLINK_CLK_CTL SMLINK1_CUR_STS SMLINK0_CUR_STS

Bit Default & Field Name (ID): Description Range Access

0h 7:3 Reserved. RO

SMLINK_CLK_CTL (SMLINK_CLK_CTL): 0 = Intel PCH will drive the SMLINK(0) 1h pin low, independent of what the other SMLINK logic would otherwise indicate for the 2 RW SMLINK(0) pin. 1 = The SMLINK(0) pin is Not overdriven low. The other SMLINK logic controls the state of the pin.

SMLINK[1]_CUR_STS (SMLINK1_CUR_STS): This bit has a default value that is 0h dependent on an external signal level. This returns the value on the SMLINK(1) pin. 1 RO It will be 1 to indicate high, 0 to indicate low. This allows software to read the current state of the pin.

SMLINK[0]_CUR_STS (SMLINK0_CUR_STS): This bit has a default value that is 0h 0 dependent on an external signal level. This returns the value on the SMLINK(0) pin. RO It will be 1 to indicate high, 0 to indicate low. This allows software to read the current state of the pin.

8.2.14 SMBUS_PIN_CTL Register (SMBC)—Offset Fh

Note: This register is in the resume well and is reset by RSMRST#

Access Method

Type: IO Register Device: 31 (Size: 8 bits) Function: 4

Default: 4h

74 0

00000100 RSVD SMBCLK_CTL SMBCLK_CUR_STS SMBDATA_CUR_STS

704 332219-002

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Bit Default & Field Name (ID): Description Range Access

0h 7:3 Reserved. RO

SMBCLK_CTL (SMBCLK_CTL): 0 = Intel PCH will drive the SMBCLK pin low, 1h 2 independent of what the other SMB logic would otherwise indicate for the SMBCLK RW pin. 1 = The SMBCLK pin is Not overdriven low. The other SMBus logic controls the state of the pin.

SMBDATA_CUR_STS (SMBDATA_CUR_STS): This bit has a default value that is 0h dependent on an external signal level. This returns the value on the SMBDATA pin. It 1 RO will be 1 to indicate high, 0 to indicate low. This allows software to read the current state of the pin.

SMBCLK_CUR_STS (SMBCLK_CUR_STS): This bit has a default value that is 0h dependent on an external signal level. This returns the value on the SMBCLK pin. It 0 RO will be 1 to indicate high, 0 to indicate low. This allows software to read the current state of the pin.

8.2.15 Slave Status Register (SSTS)—Offset 10h

All bits in this register are implemented in the 64 kHz clock domain. Therefore, software must poll the register until a write takes effect before assuming that a write has completed internally.

Access Method

Type: IO Register Device: 31 (Size: 8 bits) Function: 4

Default: 0h

74 0

00000000 HNS RSVD

Bit Default & Field Name (ID): Description Range Access

0h 7:1 Reserved. RO

HOST_NOTIFY_STS (HNS): The Intel PCH sets this bit to a 1 when it has completely received a successful Host Notify Command on the SMBus pins. Software reads this bit to determine that the source of the interrupt or SMI# was the reception 0h of the Host Notify Command. Software clears this bit after reading any information 0 needed from the Notify address and data registers by writing a 1 to this bit. Note that RW/1C the Intel PCH will allow the Notify Address and Data registers to be over-written once this bit has been cleared. When this bit is 1, the Intel PCH will NACK the first byte (host address) of any new Host Notify commands on the SMBus. Writing a 0 to this bit has no effect.

8.2.16 Slave Command Register (SCMD)—Offset 11h

All bits in this register are implemented in the 64 kHz clock domain. Therefore, software must poll the register until a write takes effect before assuming that a write has completed internally. Also, software must confirm the prior written value before writing to the register again.

Access Method

332219-002 705 SMBus Interface

Type: IO Register Device: 31 (Size: 8 bits) Function: 4

Default: 0h

74 0

00000000 HNI HNW RSVD SMB_D

Bit Default & Field Name (ID): Description Range Access

0h 7:3 Reserved. RO

SMBALERT_DIS (SMB_D): Software sets this bit to 1 to block the generation of the 0h interrupt or SMI# due to the SMBALERT# source. This bit is logically inverted and 2 RW ANDed with the SMBALERT_STS bit. The resulting signal is distributed to the SMI# and/or interrupt generation logic. This bit does not effect the wake logic.

HOST_NOTIFY_WKEN (HNW): Software sets this bit to 1 to enable the reception 0h 1 of a Host Notify command as a wake event. When enabled this event is ORed in with RW the other SMBus wake events and is reflected in the SMB_WAK_STS bit of the General Purpose Event 0 Status register.

HOST_NOTIFY_INTREN (HNI): Software sets this bit to 1 to enable the generation of interrupt or SMI# when HOST_NOTIFY_STS is 1. This enable does not affect the 0h setting of the HOST_NOTIFY_STS bit. When the interrupt is generated, either PIRQB 0 or SMI# is generated, depending on the value of the SMB_SMI_EN bit (D31, F3, RW Off40h, B1). If the HOST_NOTIFY_STS bit is set when this bit is written to a 1, then the interrupt (or SMI#) will be generated. The interrupt (or SMI#) is logically generated by ANDing the STS and INTREN bits.

8.2.17 Notify Device Address Register (NDA)—Offset 14h

Access Method

Type: IO Register Device: 31 (Size: 8 bits) Function: 4

Default: 0h

74 0

00000000 RSVD Dev_Addr

Bit Default & Field Name (ID): Description Range Access

0h DEVICE_ADDRESS (Dev_Addr): This field contains the 7-bit device address 7:1 received during the Host Notify protocol of the SMBus 2.0 specification. Software RW should only consider this field valid when the HOST_NOTIFY_STS bit is set to 1.

0h 0 Reserved. RO

706 332219-002

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8.2.18 Notify Data Low Byte Register (NDLB)—Offset 16h

Access Method

Type: IO Register Device: 31 (Size: 8 bits) Function: 4

Default: 0h

74 0

00000000 DLB

Bit Default & Field Name (ID): Description Range Access

0h DATA_LOW_BYTE (DLB): This field contains the first (low) byte of data received 7:0 during the Host Notify protocol of the SMBus 2.0 specification. Software should only RO consider this field valid when the HOST_NOTIFY_STS bit is set to 1.

8.2.19 Notify Data High Byte Register (NDHB)—Offset 17h

Access Method

Type: IO Register Device: 31 (Size: 8 bits) Function: 4

Default: 0h

74 0

00000000 DHB

Bit Default & Field Name (ID): Description Range Access

0h DATA_HIGH_BYTE (DHB): This field contains the second (high) byte of data 7:0 received during the Host Notify protocol of the SMBus 2.0 specification. Software RO should only consider this field valid when the HOST_NOTIFY_STS bit is set to 1.

8.3 SMBus Additional Registers Summary

Table 8-3. Summary of SMBus Additional Registers

Offset Offset Default Register Name (ID)—Offset Start End Value

0h 3h TCO Configuration (TCOCFG)—Offset 0h 0h

Ch Fh General Control (GC)—Offset Ch 0h

8.3.1 TCO Configuration (TCOCFG)—Offset 0h

Access Method

332219-002 707 SMBus Interface

Type: MSG Register Device: 31 (Size: 32 bits) Function: 4

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 IE IS RSVD RSVD

Bit Default & Field Name (ID): Description Range Access

0h 31:8 Reserved. RO

0h TCO IRQ Enable (IE): When set, TCO IRQ is enabled, as selected by the 7 RW TCO_IRQ_SEL field. When cleared, TCO IRQ is disabled.

0h 6:3 Reserved. RO

TCO IRQ Select (IS): Specifies on which IRQ the TCO will internally appear. If not using the APIC, the TCO interrupt must be routed to IRQ9-11, and that interrupt is not sharable with the SERIRQ stream, but is shareable with other PCI interrupts. If using the APIC, the TCO interrupt can also be mapped to IRQ20-23, and can be shared with other interrupt. Bits TCO Map 000 IRQ9 (maps to 8259 and APIC) 001 IRQ10 maps to 8259 and APIC) 0h 010 IRQ11 (maps to 8259 and APIC) 2:0 RW 011 Reserved 100 IRQ20 (maps to APIC) 101 IRQ21 (maps to APIC) 110 IRQ22 (maps to APIC) 111 IRQ23 (maps to APIC) When setting the these bits, the IE bit should be cleared to prevent glitching. When the interrupt is mapped to APIC interrupts 9, 10 or 11, the APIC should be programmed for active-high reception. When the interrupt is mapped to APIC interrupts 20 through 23, the APIC should be programmed for active-low reception.

8.3.2 General Control (GC)—Offset Ch

Access Method

Type: MSG Register Device: 31 (Size: 32 bits) Function: 4

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 FD NR RSVD

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SMBus Interface

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

No Reboot (NR): This bit is set when the No Reboot strap is sampled high on 0h PWROK. This bit may be set or cleared by software if the strap is sampled low but 1 may not override the strap when it indicates No Reboot.When set, the TCO timer will RW count down and generate the SMI# on the first timeout, but will not reboot on the second timeout.

0h Function Disable (FD): When set to one, this disables the PCI config register space 0 RW for the SMBus device.

332219-002 709 SMBus Interface

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Additional Configuration Registers

9 Additional Configuration Registers

9.1 DMI Configuration Registers Summary

Table 9-1. Summary of DMI Configuration Registers

Offset Offset Default Register Name (ID)—Offset Start End Value

2234h 2337h DMI Power Management Control (DMIPMCTL)—Offset 2334h 0h

9.1.1 DMI Power Management Control (DMIPMCTL)—Offset 2334h

BIOS may need to program this register.

9.2 IO Trap Registers Summary

Table 9-2. Summary of IO Trap Registers

Offset Offset Default Register Name (ID)—Offset Start End Value

1E10h 1E13h Trapped Cycle Register (TRPCYC1)—Offset 1E10h 0h

1E18h 1E1Bh Trapped Write Data Register (TRPWRDATA1)—Offset 1E18h 0h

9.2.1 Trapped Cycle Register (TRPCYC1)—Offset 1E10h

This register saves information about the I/O Cycle that was trapped and generated the SMI# for software to read.

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 RSVD RSVD RSVD TRPBE TRPRWR TRPADDR

332219-002 711 Additional Configuration Registers

Bit Default & Field Name (ID): Description Range Access

0h 31:25 Reserved. RO

0h Read-Write (TRPRWR): 1 = Read, 0 = Write 24 RO/V

0h 23:20 Reserved. RO

0h Active-High Byte Enables (TRPBE): This is the DWord-aligned byte enables 19:16 associated with the trapped cycle. A 1 in any bit location indicates that the RO/V corresponding byte is enabled in the cycle.

0h IO Address (TRPADDR): This is the DWord-aligned address of the trapped cycle. 15:2 RO/V

0h 1:0 Reserved. RO

9.2.2 Trapped Write Data Register (TRPWRDATA1)—Offset 1E18h

This register saves the data from I/O write cycles that are trapped for software to read

Access Method

Type: MSG Register Device: (Size: 32 bits) Function:

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 TRPDATA

Bit Default & Field Name (ID): Description Range Access

0h Data (TRPDATA): DWord of I/O write data. This field is undefined after trapping a 31:0 RO/V read cycle.

9.3 PCH_PCR Registers Summary

Table 9-3. Summary of PCH_PCR Registers

Offset Offset Default Register Name (ID)—Offset Start End Value

3418h 341Bh General Control & Function Disable (GCFD)—Offset 3418h 0h

9.3.1 General Control & Function Disable (GCFD)—Offset 3418h

Access Method

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Additional Configuration Registers

Type: MSG Register Device: 31 (Size: 32 bits) Function: 0

Default: 0h

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 eSPI RSVD LPC_BD

Bit Default & Field Name (ID): Description Range Access

0h 31:2 Reserved. RO

eSPI Enable Pin Strap (eSPI): This field determines the destination of accesses to the D31:F0 and related Fixed and Variable IO and Memory decode ranges, including 0h BIOS memory range. 1 1'b0: LPC is the D31:F0 target. RO 1'b1: eSPI is the D31:F0 target. Note: This field, along with BC.BBS strap setting determines the final Bios Boot Location.

LPC Bridge Disable (LPC_BD): When set, the LPC bridge is disabled. When 0h disabled the following spaces will no longer be decoded by the LPC bridge: 0 1) D31:F0 PCI Configuration space RW 2) Memory cycles below 16MB (1000000h) 3) I/O cycles below 64kB (10000h)

9.4 RTC Configuration Registers Summary

Table 9-4. Summary of RTC Configuration Registers

Offset Offset Default Register Name (ID)—Offset Start End Value

3400h 3403h RTC Configuration (RC)—Offset 3400h 0h

9.4.1 RTC Configuration (RC)—Offset 3400h

All bits in this register are in the Primary Well and cleared by PLTRST# assertion.

Access Method

Type: Register Device: (Size: 32 bits) Function:

Default: 0h

332219-002 713 Additional Configuration Registers

3 2 2 2 1 1 840 1 8 4 0 6 2

00000000000000000000000000000000 LL UL UE BILD RSVD RSVD HPM_SW_DIS HPM_HW_DIS

Bit Default & Field Name (ID): Description Range Access

Bios Interface Lock-Down (BILD): When set, prevents RTC version of TS 0h (BUC.TS) from being changed. This bit can only be written from 0 to 1 once. This 31 BILD bit has a different function compared to LPC, SPI and eSPI version but BIOS RWLO should set all the corresponding bits after reset in order to lock down the BIOS interface correctly.

0h 30:7 Reserved. RO

RTC High Power Mode HW Disable (HPM_HW_DIS): 0 = HW control of the RTC 0h internal VRM is disabled. 6 RW 1 = The internal VRM that generates the rtc well supply voltage in SUS mode is disabled when SLP_S0# is asserted.

RTC High Power Mode SW Disable (HPM_SW_DIS): 0 = The internal VRM 0h powers the rtc well when RSMRST# is '1'. (default) 5 RW 1 = The internal VRM that generates the rtc well supply voltage in SUS mode is disabled.

0h Upper 128 Byte Lock (UL): When set, bytes 38h-3Fh in the upper 128 byte bank of 4 RTC RAM are locked and cannot be accessed. Writes will be dropped and reads will RWLO not return any guaranteed data. Bit reset on system reset.

0h Lower 128 Byte Lock (LL): When set, bytes 38h-3Fh in the lower 128 byte bank of 3 RTC RAM are locked and cannot be accessed. Writes will be dropped and reads will RWLO not return any guaranteed data. Bit reset on system reset.

0h Upper 128 Byte Enable (UE): When set, the upper 128 byte bank of RTC RAM can 2 RW be accessed.

0h 1:0 Reserved. RO

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