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eZ80Acclaim! Flash Microcontrollers eZ80F91 Product Brief

PB010704-0103

Product Block Diagram • Four Counter/Timers with prescalers support- ing event counting, input capture, output com- eZ80F91 MCU pare, and PWM modes • Watch-Dog Timer with internal RC clocking 256KB+ option 8KB SRAM 32-Bit GPIO 512B Flash • Real-time clock with on-chip 32kHz oscillator, selectable 50/60 Hz input, and separate 10/100Mbps Ethernet MAC RTC_VDD pin for battery backup. 8KB Frame Buffer • Glueless external memory interface with 4 Infrared Chip-Selects/Wait-State Generators and external WAIT input pin. Supports Intel and Motorola Encoder/ 2 UART I2C SPI buses. Decoder • JTAG Interface supporting emulation features Real-Time • 4 PRT WDT Low-power PLL and on-chip oscillator Clock • Programmable-priority vectored interrupts, non- maskable interrupts, and interrupt controller 4 CS JTAG ZDI PLL ¨ +WSG • New DMA-like eZ80 CPU instructions • Power management features supporting HALT/ SLEEP modes and selective peripheral power- Features down controls The eZ80F91 microcontroller is a member of • 144-pin LQFP package ZiLOG’s eZ80Acclaim! product family, which • 3.0Ð3.6 V supply voltage with 5 V tolerant offers on-chip Flash versions of ZiLOG’s eZ80¨ inputs processor core. The eZ80F91 offers the following • Operating Temperature Ranges: features: – Standard: 0¼C to +70¼C ¨ • 50MHz High-Performance eZ80 CPU – High: 0¼C to +105¼C • 256KB Flash Program Memory plus extra 512B device configuration Flash memory General Description • 8KB on-chip high-speed SRAM The eZ80F91 device is an industry first, featuring a • 32 bits of General-Purpose I/O high-performance 8-bit microcontroller with an integrated 10/100BaseT Ethernet Media Access • 10/100BaseT Ethernet Media Access Controller controller (EMAC). It is a power-efficient, opti- (EMAC) with 8KB High-Speed Frame Buffer mized pipeline architecture microcontroller with a • IrDAª-compatible Infrared Encoder/Decoder maximum operating speed of 50 MHz. Offering • 2 UARTs with independent baud rate generators on-chip Flash memory, SRAM, Ethernet MAC, and rich peripherals, the eZ80F91 is well-suited for • I2C with independent clock rate generator industrial, communication, automation, security, • SPI with independent clock rate generator and embedded Internet applications.

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eZ80F91 Product Brief

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eZ80¨ CPU Core pendent Interface (MII) for simple connection to The eZ80¨ CPU can operate in Z80-compatible an external Physical Layer interface (PHY) device. (64KB) mode or full 24-bit (16 MB) addressing The eZ80F91 delivers high performance and over- mode. Considering both the increased clock speed all cost effectiveness as an embedded network and processor efficiency, the eZ80¨’s processing microcontroller. power rivals the performance of 16-bit micropro- High performance is achieved by optimizing the cessors. The eZ80¨ improves on the world-famous internal bus design of the eZ80¨ CPU with shared Z80 architecture. Like the Z80, it features dual memories, dedicated Ethernet Tx/Rx DMAs, and bank registers for fast context switching. Tx/Rx FIFOs. This bus design provides the highest data throughput over the Ethernet interface, yet eZ80F91 Peripherals Description requires minimum eZ80¨ CPU intervention and minimizes system loading. On-Chip Memory The eZ80F91 device offers 256KB of Flash pro- Infrared Encoder/Decoder gram memory. A separate page of 512bytes Flash • Supports IrDA SIR format memory is available for general device configura- • Operates seamlessly with on-chip UART tion data. • Interfaces with IrDA-compliant transceivers • Single power supply operation • Supports transmit/receive to 115Kbps • Page erase feature: 1024 bytes/page Universal Asynchronous Receiver/Transmitter • Fast page erase and byte program operation Each of the two Universal Asynchronous Receiver/ • 60 ns maximum access time Transmitter (UART) channels contains a transmit- • Endurance: 20,000 write cycles (typical) ter, a receiver, control logic/registers, and a Baud Rate Generator (BRG). • Data retention: greater than 100 years @ room temperature • The Baud Rate Generator produces a lower-fre- quency bit clock from the system clock. All In addition, 8 KB of high-speed, relocatable standard baud rates up to 115Kbps (and higher) SRAM is available for general application use. are supported. General-Purpose Input/Output • The UART module implements all of the logic There are 32 bits of General-Purpose Input or Out- required to support asynchronous communica- put (GPIO). All GPIO pins are individually pro- tions, hardware flow control, and 9-bit character grammable and support the following I/O modes: format. The module also contains separate 16- input, output, open drain, open source, level-trig- byte-deep transmit and receive FIFOs. gered interrupts (High or Low), edge-triggered interrupts (High or Low), dual edge-triggered Inter-Integrated Circuit 2 interrupts, and alternate function. Eight of the out- The Inter-Integrated Circuit (I C) channel contains put pins can drive 10mA each (Port A), while 16 control registers and its own clock rate generator. 2 other pins feature Schmitt-trigger input buffers The I C interface operates in four modes: Master (Ports B and C). Transmit or Receive, and Slave Transmit or Receive. A standard and fast I2C speed of 100kbps 10/100BaseT Ethernet MAC and 400kbps are supported. The eZ80F91 device features an integrated IEEE 802.3 Ethernet controller with a total of 8KB of Serial Peripheral Interface dynamically-configurable Tx/Rx frame buffer. It The Serial Peripheral Interface (SPI) channel con- supports speeds of 10 and 100Mbps, full duplex tains control registers and its own clock rate gener- operation, and an industry-standard Media Inde- ator. The SPI is a synchronous serial interface

PB010704-0103 eZ80Acclaim! Flash Microcontrollers

eZ80F91 Product Brief

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allowing multiple SPI devices to be intercon- individually programmed on a 64KB boundary. I/ nected. The SPI interface may be configured to O chip selects can choose a 256-byte section of I/O operate as a master or a slave. space. The WAIT input pin allows interface with slow peripherals. Z80, Intel, and Motorola bus Programmable Reload Timers modes are supported. The eZ80F91 provides four independent Program- mable Reloadable Counter Timers (PRT) to handle JTAG Interface complex timing functions. Each timer is a 16-bit An IEEE 1149.1-compatible five-pin test access downcounter and offers a 4-bit clock prescaler with port (TAP) is provided to interface with on-chip four selectable taps for CLK ÷ 4, CLK ÷ 16, test logic defined by that standard. This TAP also CLK÷64 and CLK÷256. The timers can operate in includes Boundary Scan functions. For IEEE basic mode supporting SINGLE-PASS or CON- 1149.1 compliance, a pull-up resistor is required TINUOUS count. Additional features include 4 on pin TDI. Additionally, the TAP is used to con- input captures, 4 output compares, 2 external event trol the on-chip emulation/debugging capabilities. counters, and 4 PWMs that can operate indepen- Some included features are: software break points, dently or in unison. Any one of the input capture a 64-word trace buffer, complex break points using pins can be programmed as master PWM power- address and data masks, and cascadable triggers. trip inputs. PLL and On-Chip Crystal Oscillator Watch-Dog Timer The eZ80F91 features a complete, low-power, pro- The Watch-Dog Timer (WDT) features four pro- grammable PLL that can be selected to generate grammable time-out periods: 218, 222, 225, or 227 the system clock. Taking its input from the on-chip system clock cycles. It can operate from either the crystal oscillator, the PLL can generate system main system clock, the on-chip 32kHz oscillator clock speeds up to 50MHz from low-cost, low-fre- (from the RTC), or the internal RC oscillator. The quency external crystals in the range of 1Ð10MHz.. time-out action of the WDT is user-programmable ZiLOG Debug Interface for either a hardware reset or a nonmaskable inter- The ZiLOG Debug Interface (ZDI) incorporates rupt to the eZ80¨ CPU. The source of action taken most of the functions of an In-Circuit Emulator on- after a WDT time-out is indicated by a WDT status chip. ZDI allows the user to single-step code, bit. change registers, edit programs, and view status of Real-Time Clock internal registers. The real-time clock (RTC) allows counting of sec- Block Transfer Instructions onds, minutes, hours, days-of-the-week, day-of- Block transfer instructions with expanded repeat the-month, month, year, and century. Alarms and capability have been added to the eZ80¨ CPU. interrupts can be set for seconds, minutes, hours, They provide high-performance data transfer simi- and day-of-the-week. The real-time clock input can lar to hardware DMAs. be taken from the on-chip 32kHz oscillator or from a 50/60Hz input. The real-time clock operates Power Management from an isolated RTC_VDD pin to allow constant operation from a battery. Several power management features are supported Chip-Select/Wait State Generator and WAIT Pin on the eZ80F91. Two peripheral power-down reg- isters allow independent clock gating of on-chip Four independent chip selects are available to facil- peripherals under software control while operating itate glueless interface to system memory and under normal conditions. The eZ80¨ CPU can external devices. Each chip select can be config- write to these control registers to disable the clock ured for up to 7 wait states, and supports either memory or I/O space. Memory chip selects can be

PB010704-0103 eZ80Acclaim! Flash Microcontrollers

eZ80F91 Product Brief

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from driving any one of the peripherals when they • High temperature: 0¼C to +105¼C are inactive. • Supply current @ 50MHz: 50mA (typical) In addition, execution of the HALT instruction sus- ¨ • Supply current in HALT mode with peripherals pends eZ80 CPU operation and eliminates clock powered down: <5mA (typical) power associated with the eZ80¨ CPU core. Nor- mal operation can be restored via external and • Supply current in SLEEP mode: <50µA (typical) peripheral interrupts or hardware reset. Support Tools Execution of a sleep (SLP) instruction provides the lowest power consumption. In SLEEP mode, only The following development tools are available to the on-chip RTC 32kHz crystal oscillator remains program and debug the eZ80F91 device: active to drive the RTC and the WDT. All other • Development board with eZ80¨ CPU plug-in peripherals, the system clock, and the primary module oscillator are disabled. An RTC alarm, a WDT • IPWorksª TCP/IP software stack time-out, or hardware reset can reset the device. • Operating System Electrical Features Summary • ANSI C-Compiler • Power supply: 3.3V ± 0.3V • ZiLOG Developer’s Studio Integrated Develop- • Standard temperature: 0¼C to 70¼C ment Environment (ZDS IDE) including assem- bler, linker, debugger, and simulator Related Products Other integrated devices of interest are: eZ80190 50 MHz eZ80¨ CPU, 8KB SRAM, 16x16 Multiply with 40-bit Accumulators, 32 bits GPIO, 6 Counter Timers with Prescalers, WDT, 4 channel CS+WSG, 2-Channel DMA, 2 UZI Channels, ZDI, On-Chip Oscillator. eZ80L92 20MHz and 50MHz eZ80¨ CPU, low-power modes, 24 bits GPIO, IrDA, 2 UART, I2C, SPI, 6 Counter Timers with I/O features, WDT, RTC, 4-channel CS, JTAG, ZDI. eZ80F92 20MHz eZ80¨ CPU, low-power modes, 128KB+256B Flash, 8KB SRAM, 24 bits GPIO, IrDA, 2 UART, I2C, SPI, 6 Counter Timers with I/O features, WDT, RTC, 4 channel CS+WSG, JTAG, ZDI, PLL. eZ80F93 20MHz eZ80¨ CPU, low-power modes, 64KB+256B Flash, 4KB SRAM, 24 bits GPIO, IrDA, 2 UART, I2C, SPI, 6 Counter Timers with I/O features, WDT, RTC, 4 channel CS+WSG, JTAG, ZDI. Z80S180™ Improved Z80 CPU, 1MB MMU, 2 DMA, 2 16-bit PRTs, 2 UARTs, CSIO, up to 33MHz clock speed Z80181 Z8S180 CPU, SCC, CTC, 16-bit GPIO, up to 33MHz clock speed Z80182 Z8S180 CPU, 2 ESCC, 24-bit GPIO, 16550 Mimic interface, up to 33MHz clock speed Z84C00 Z80™ CPU (up to 20MHz) Z84C15 Z80™ CPU, 2 SIO, 4x8 CTC, 2 PIO, WDT, up to 16MHz clock speed

PB010704-0103 eZ80Acclaim! Flash Microcontrollers eZ80F91 Product Brief

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Block Diagram

Ethernet MAC Signals (18)

Ethernet 8K Byte MAC FIFO (SRAM)

RTC_XOUT Real-Time RTC_XIN Clock RTC_VDD Battery BUSACK backup BUSREQ Bus IORQ Controller I2C SCL & MREQ Serial Arbiter Interface INSTRD SDA RD WR 256KB DATA[7:0] Program SCK Flash HALT_SLP SPI Serial + WAIT SS 512Bytes eZ80 Parallel NMI Config CPU MISO Interface Flash RESET MOSI JTAG JTAG Signals (6) Debug Interface

CTS0/1 ADDR[23:0]

DCD0/1 Interrupt CS0 Chip Select DSR0/1 Vector UART [7:0] & CS1 Universal DTR0/1 Asynchronous Wait State Interrupt CS2 Receiver/ Generator Controller RI0/1 Transmitter CS3 (2) RTS0/1 DATA[7:0] RXD0/1

TXD0/1 ADDR[23:0]

WDT GPIO Crystal Programmable Watchdog IrDA General Oscillator, Reload Encoder/ Purpose PLL and Timer Decoder I/O Port System Clock Timer/Counter (4x 8-bit) Generator (4) Internal RC Osc IN X PHI OUT X EC0/1 PA[7:0] PB[7:0] PC[7:0] PD[7:0] IC0/1/2/3 IR_TXD IR_RXD OC0/1/2/3 LOOP_FILT PWM0/1/2/3 Figure 1. eZ80F91 Block Diagram

PB010704-0103 eZ80Acclaim! Flash Microcontrollers eZ80F91 Product Brief

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Pin Diagram /EC1 /TOUT1 /TOUT0 PWM0/OC0 4/PWM0 6/PWM2 A3/PWM3/OC3 A2/PWM2/OC2 A1/PWM1/OC1 A7/PWM3 A5/PWM1 PA P P P PA0/ VSS VDD PHI SCL SDA WP MDIO MDC RXD3 RXD2 RXD1 RXD0 RX_DV RX_CLK RX_ER VSS VDD TX_ER TXD1 TXD2 TXD3 COL CRS VSS VDD P PA P TX_EN TXD0 TX_CLK 108 VSS 110 1 144 140 130 120 A0 PB7/MOSI A1 PB6/MISO A2 PB5/IC3 A3 PB4/IC2 A4 PB3/SCK VDD PB2/SS VSS PB1/IC1 A5 100 PB0/IC0/EC0 A6 VSS A7 10 VDD A8 PC7/RI1 A9 PC6/DCD1 A10 PC5/DSR1 VDD PC4/DTR1 VSS PC3/CTS1 A11 PC2/RTS1 A12 PC1/RxD1 A13 144-Pin LQFP 90 PC0/TxD1 A14 VSS A15 20 VDD A16 PLL_VDD VDD XOUT VSS XIN A17 PLL_VSS A18 LOOP_FILT A19 VSS A20 VDD A21 A22 80 PD7/RI0 A23 30 PD6/DCD0 VDD PD5/DSR0 VSS PD4/DTR0 CS0 PD3/CTS0 CS1 PD2/RTS0 CS2 PD1/RxD0/IR_RXD CS3 36 73 PD0/TxD0/IR_TXD 40 50 60 70 D0 D1 D2 D3 D4 D5 D6 D7 RD AIT WR TDI NMI VSS VSS VSS TCK VSS VSS VDD VDD VDD TMS TDO W IORQ TRST _VDD C_XIN MREQ T_SLP RESET INSTRD BUSACK C_XOUT BUSREQ RT TRIGOUT RTC HAL RT Figure 2. eZ80F91 144-Pin LQFP Pin Configuration

Ordering Information

Part PSI Description eZ80F91AZ050SC 50MHz, Standard Temperature eZ80F91 device eZ80F91AZ050HC 50MHz, High Temperature eZ80F91 device eZ80F910200ZCO Development Kit, standard version Complete eZ80Acclaim! Development Kit

PB010704-0103 eZ80Acclaim! Flash Microcontrollers eZ80F91 Product Brief

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ZiLOG Worldwide Headquarters 532 Race Street San Jose, CA 95126 USA Telephone: 408.558.8500 Fax: 408.558.8300 www.ZiLOG.com

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PB010704-0103 eZ80Acclaim! Flash Microcontrollers