Harmonic Analysis for Quality of Service HAQS: Sponsored by Texas Instruments

Senior Design I

Group 19: Brian Angiel (EE) Nick Hellenbrand (EE) Louis Hofer (CpE) Kevin White (EE)

Submitted December 10, 2015 Fall 2015

Table of Contents 1 Executive Summary ...... 1 2 Project Description ...... 2 2.1 Project Motivation ...... 2 2.2 Project Goals and Objectives ...... 3 2.3 Project Requirements and Specifications ...... 3 2.3.1 Functionality ...... 3 2.3.2 Form Factor ...... 4 2.3.3 Standards ...... 4 2.4 Sponsor Considerations ...... 5 2.5 Project Block Diagram ...... 5 3 Project Background ...... 6 3.1 Related Products ...... 6 3.1.1 AEMC PowerPad® III Model 8333 ...... 6 3.1.2 YOKOGAWA Clamp-On Power Analyzer CW240 ...... 7 3.1.3 Fluke 435 Series II Power Quality & Energy Analyzer ...... 9 3.2 Project Constraints ...... 10 3.2.1 Economic ...... 10 3.2.2 Environmental ...... 10 3.2.3 Social ...... 10 3.2.4 Political ...... 10 3.2.5 Ethical ...... 10 3.2.6 Health and Safety ...... 10 3.2.7 Manufacturability ...... 10 3.2.8 Sustainability ...... 10 3.3 Relevant Standards ...... 11 3.3.1 Total Harmonic Distortion Reporting Standard ...... 11 3.3.2 Metering Standards ...... 11 3.3.3 Electrical Safety Standards ...... 12 3.3.4 Communication Standards ...... 14 3.3.4.1 SPI Communication Standards ...... 14 3.3.4.2 I2C Communication Standards ...... 15 3.3.5 SD Card Common Interface Standard ...... 15 3.3.6 Electromagnetic Interference and Electromagnetic Compatibility Standards 17 3.4 Research ...... 18 3.4.1 Harmonic Analysis ...... 18 3.4.1.1 Discrete Fourier Transform ...... 18 3.4.1.2 Fast Fourier Transform ...... 18 3.4.1.2.1 Windowing ...... 19 3.4.1.2.2 Sample Synchronization ...... 20 3.4.1.3 Fourier Transforms: Discrete vs. Fast ...... 20 3.4.2 Analog-to-Digital Converter ...... 21 3.4.2.1 Types of Analog-to-Digital Converters ...... 21 3.4.2.1.1 Successive Approximation Register ADC ...... 21 3.4.2.1.2 Flash ADC ...... 23

iii 3.4.2.1.3 Sigma-Delta ADC ...... 25 3.4.2.2 Analog-to-Digital Converter Conclusion ...... 26 3.4.3 Quantization Noise ...... 27 3.4.4 Data Input Methods ...... 28 3.4.4.1 Single-Ended Inputs ...... 28 3.4.4.2 Differential Inputs ...... 28 3.4.4.3 Data Input Method Conclusion ...... 29 3.4.5 Microcontroller Unit ...... 29 3.4.5.1 Launchpads ...... 30 3.4.5.2 Available Processors ...... 30 3.4.5.3 Instruction Set Architecture ...... 31 3.4.5.3.1 ARM v6/7 ...... 32 3.4.5.3.2 Thumb-2 ...... 32 3.4.5.3.3 Arm v6/7 vs. Thumb-2 ...... 32 3.4.5.4 Code Language ...... 33 3.4.5.4.1 C Programming Language ...... 33 3.4.5.4.2 Available Assembly Language ...... 33 3.4.6 Power Supply Unit ...... 35 3.4.6.1 Voltage Step Down ...... 35 3.4.6.1.1 Voltage Divider ...... 35 3.4.6.1.2 Voltage Step Down without a Transformer ...... 36 3.4.6.1.3 Voltage Step Down with a Transformer ...... 37 3.4.6.1.4 Voltage Step Down Conclusion ...... 37 3.4.6.2 Rectification and DC Conversion ...... 37 3.4.6.3 Power Factor Correction ...... 38 3.4.6.4 DC Step Down and Regulation ...... 39 3.4.6.4.1 Linear Regulator ...... 40 3.4.6.4.1.1 Standard Linear Voltage Regulator ...... 40 3.4.6.4.1.2 Low-Dropout Linear Regulator ...... 41 3.4.6.4.1.3 Quasi Low-Dropout Regulator ...... 42 3.4.6.4.2 Switching Regulator ...... 42 3.4.6.4.3 DC Step Down and Regulation Conclusion ...... 43 3.4.7 Liquid Crystal Display ...... 44 3.4.7.1 Capacitive Touch ...... 45 3.4.7.2 Electromagnetic Interference ...... 45 3.4.7.3 Resistive Touch ...... 46 3.4.7.4 Non-Touch LCD ...... 47 3.4.7.5 LCD Conclusions and Comparisons ...... 47 3.4.7.6 Communication Schemes ...... 49 3.4.7.6.1 Serial Peripheral Interface Communication ...... 49 3.4.7.6.2 Inter-Integrated Circuit Communication ...... 50 3.4.7.6.3 Universal Asynchronous Receiver / Transmitter Communication ...... 50 3.4.8 User Interface ...... 51 3.4.8.1 Physical Buttons ...... 51 3.4.8.2 Built-in Touch Interface ...... 52 3.4.9 Voltage and Current Sensing ...... 52 3.4.9.1 Voltage Step Down ...... 52 3.4.9.1.1 Single Phase Transformer ...... 52 3.4.9.1.2 Three Phase Transformer ...... 53 3.4.9.1.3 Voltage Divider ...... 54 3.4.9.2 Current Sensing ...... 55 3.4.9.2.1 Shunt Resistor ...... 55 3.4.9.2.2 Hall-Effect Sensor ...... 56

iv 3.4.9.2.3 Current Transformer ...... 56 3.4.9.3 Filtering ...... 57 3.4.9.3.1 Ferrite Beads ...... 57 3.4.9.3.2 Alias Filtering ...... 58 3.4.10 SD Card Reader ...... 58 3.4.10.1 Communication ...... 58 3.4.10.1.1 SPI ...... 59 3.4.10.1.2 UART ...... 59 3.4.10.2 File System ...... 59 3.4.10.2.1 FatFS ...... 60 3.4.10.2.2 Petit FatFS ...... 60 3.4.11 Circuit Protection ...... 60 3.4.11.1 Solid State Relays ...... 60 3.4.11.2 Fuses ...... 61 3.4.11.3 Gas Discharge Tube ...... 61 3.4.11.4 Thyristors ...... 61 3.4.11.5 Varistors ...... 62 3.4.11.6 High-Speed Switching Diode and Zener Diode ...... 62 3.4.11.7 Transient Voltage Suppressive Diode ...... 63 4 Design ...... 64 4.1 Hardware ...... 64 4.1.1 Voltage Sensor ...... 64 4.1.1.1 Transformer vs. Voltage Divider ...... 64 4.1.1.2 Voltage Sensing Circuit ...... 64 4.1.2 Current Sensor ...... 69 4.1.2.1 Current Sensor Comparison ...... 69 4.1.2.2 Current Sensing Circuit ...... 69 4.1.3 Analog-to-Digital Converter ...... 75 4.1.4 Microcontroller Unit ...... 78 4.1.4.1 Liquid Crystal Display ...... 79 4.1.4.2 SD Card Reader ...... 79 4.1.5 Power Supply Unit ...... 79 4.2 Software ...... 92 4.2.1 Data Structures ...... 95 4.2.1.1 Complex ...... 95 4.2.1.2 Fast Fourier Transform ...... 95 4.2.1.3 Analog-to-Digital Converter ...... 96 4.2.1.4 SD Card ...... 96 4.2.1.5 Liquid Crystal Display ...... 97 4.3 Prototype Assembly ...... 98 4.3.1 Microcontroller Unit ...... 100 4.3.2 SD Card ...... 101 4.3.3 LCD and Capacitive Touch Controller ...... 101 4.3.4 Analog-to-Digital Converter ...... 101 4.3.5 Power Supply Unit ...... 102 4.4 Final PCB Design ...... 102 4.4.1 Design ...... 102 4.4.2 Design ...... 102 4.4.3 Software ...... 103 4.4.4 Vendor ...... 103

v 5 Testing ...... 103 5.1 Module Testing ...... 103 5.1.1 Voltage Sensor Testing ...... 103 5.1.2 Current Transformer Testing ...... 104 5.1.3 Current Sensor Testing ...... 105 5.1.4 Touch Screen Testing ...... 107 5.1.5 Analog-to-Digital Converter Testing ...... 109 5.1.6 Power Supply Unit Testing ...... 112 5.1.7 File System Testing ...... 113 5.1.8 Harmonic Analysis of Multiple Waveforms ...... 114 5.1.9 Total Harmonic Distortion Accuracy Verification ...... 115 5.2 Field Testing ...... 116 6 Product Operation ...... 117 7 Administrative Content ...... 117 7.1 Roles and Responsibilities ...... 118 7.2 Facilities and Equipment ...... 118 7.3 Consultants and Advisors ...... 119 7.4 Milestones ...... 119 7.5 Bill of Materials ...... 120 7.6 Funding ...... 132 8 Design Summary ...... 132 9 Appendices ...... i 9.1 Appendix A – Copyright Permissions ...... i 9.2 Appendix B – Fast Fourier Transform Software ...... vi 9.3 Appendix C – Datasheets ...... ix 9.4 Appendix D – Bibliography ...... xi

vi Table of Figures

Figure 1: HAQS Block Diagram ...... 6 Figure 2: Sinusoidal Waveform with Smaller Window ...... 19 Figure 3: FFT of the above Sinusoid as a Result of a Smaller Window ...... 19 Figure 4: SAR ADC Converter Architecture ...... 22 Figure 5: SAR ADC Block Diagram ...... 22 Figure 6: Flash Analog-to-Digital Converter Architecture ...... 24 Figure 7: Sigma-Delta Analog-to-Digital Converter Block Diagram ...... 26 Figure 8: Single-Ended Input ...... 28 Figure 9: Differential Input ...... 29 Figure 10: AC Step Down and Rectification Circuit without Transformer ...... 36 Figure 11: Input & Output Voltage & Current With & Without a PFC Circuit ...... 38 Figure 12: Standard Linear Voltage Regulator ...... 41 Figure 13: Low-Dropout Linear Voltage Regulator ...... 41 Figure 14: Quasi Low-Dropout Circuit ...... 42 Figure 15: Integrated Solution for Switching Voltage Regulator ...... 43 Figure 16: Resistive Touchscreen ...... 46 Figure 17: SPI Communication Interface ...... 49 Figure 18: I2C Communication Interface ...... 50 Figure 19: UART Communication Interface ...... 51 Figure 20: Original Concept Design with Physical UI ...... 51 Figure 21: Example of Transformer Model ...... 53 Figure 22: Three-Phase Transformer ...... 54 Figure 23: Example of a Split Core Current Transformer ...... 57 Figure 24: Voltage Sensing Circuit ...... 65 Figure 25: Voltage Sensing Circuit Under Ideal Operational Conditions ...... 67 Figure 26: Frequency Response After Frequency Scaling ...... 67 Figure 27: Current Sensing Circuit ...... 70 Figure 28: Current Sensing Circuit Under Ideal Operational Conditions ...... 72 Figure 29: Frequency Response after Frequency Scaling ...... 73 Figure 30: System Power Flow Diagram ...... 79 Figure 31: EMI Filtering Circuit ...... 80 Figure 32: PFC Circuit ...... 81 Figure 33: Vishay KBL02 Diode Bridge Rectifier ...... 82 Figure 34: PFC Voltage Sensing Circuit ...... 82 Figure 35: PFC Current Sensing Circuit ...... 83 Figure 36: PFC Self-Bias Configuration ...... 84 Figure 37: External MOSFET Drive Device ...... 84 Figure 38: LM46001 5.0 VDC Regulated Circuit ...... 88 Figure 39: LM46001 3.0 VDC Regulated Circuit ...... 88 Figure 40: LM46001 1.8 VDC Regulated Circuit ...... 88 Figure 41: LM20133 3.0 VDC Regulated Circuit ...... 90

vii Figure 42: LM20133 3.0 VDC Regulated Circuit ...... 90 Figure 43: Process Flow Diagram ...... 94 Figure 44: Complex Data Structure ...... 95 Figure 45: Fast Fourier Transform Data Structure ...... 96 Figure 46: ADC Data Structure ...... 96 Figure 47: SD Card Data Structure ...... 97 Figure 48: LCD Data Structure ...... 97 Figure 49: Capacitive Touchscreen Panel ...... 108 Figure 50: ZIF Connector for GSL Controller ...... 109 Figure 51: ADS131E08EVM-PDK Evaluation Module ...... 109 Figure 52: The Engineering Process ...... 119 Figure 53: Permission from Maxim Integrated ...... i Figure 54: Permission from Texas Instruments ...... i Figure 55: TI Academic Authorization ...... ii Figure 56: Permission from Vishay Intertechnology ...... ii Figure 57: Permission from MCCDAQ ...... ii Figure 58: Permission from Microchip ...... iii Figure 59: Microchip Academic Authorization ...... iii Figure 60: Permission from Creative Commons ...... iii Figure 61: Permission from Dakota Electric ...... iv Figure 62: Permission from Continental Control Systems ...... v

viii Table of Tables

Table 1: SD Card Comparison ...... 16 Table 2: EMI and EMC Standard Information ...... 17 Table 3: Comparison of DFT and FFT ...... 21 Table 4: ADC Comparison Chart ...... 27 Table 5: TI Processors ...... 31 Table 6: Arm v6/7 vs. Thumb-2 ...... 32 Table 7: C vs. Assembly ...... 34 Table 8: PSU Design Parameters for Research ...... 35 Table 9: AC Step Down Methods Comparison ...... 37 Table 10: Linear and Switching Voltage Regulator Comparison ...... 44 Table 11: Touchscreen Feature Comparisons ...... 48 Table 12: LCD Communication Comparisons ...... 48 Table 13: LCD Resolution Comparison ...... 49 Table 14: Transformer vs. Voltage Divider ...... 64 Table 15: Voltage Sensor Design Requirements ...... 66 Table 16: Current Sensor Tradeoffs ...... 69 Table 17: Current Transformer Specifications ...... 70 Table 18: Current Sensor Design Requirements ...... 71 Table 19: TI MCUs with Integrated ADCs ...... 76 Table 20: Discrete ADC Comparison ...... 77 Table 21: Maximum Voltages from PSU Components ...... 85 Table 22: Viable Regulators for Parallel Regulation ...... 87 Table 23: Parallel Regulation Design Statistics ...... 89 Table 24: Viable Regulators for Serial Regulation ...... 89 Table 25: Serial Regulation Design Statistics ...... 91 Table 26: Parallel vs. Serial Comparison ...... 91 Table 27: Final PSU Design Values ...... 92 Table 28: SD Card to MCU Pinout ...... 98 Table 29: LCD to MCU Pinout ...... 98 Table 30: LCD to MCU Pinout (continued) ...... 99 Table 31: AC Input to ADC Pinout ...... 99 Table 32: Power to ADC Pinout ...... 100 Table 33: Power to Current Senor Pinout ...... 100 Table 34: Power Supply to MCU Pinout ...... 100 Table 35: Power Supply to LCD Pinout ...... 100 Table 36: ADC DGND to MCU DGND...... 100 Table 37: Test Points and Respective Voltages ...... 110 Table 38: Configurations for +3.0 V Unipolar Analog Supply ...... 110 Table 39: Configuration for +1.8 V Digital Display ...... 110 Table 40: Configuration for Utilization of 2.5 V Vref ...... 111 Table 41: Analog-to-Digital Converter PCB BoM ...... 121

ix Table 42: Analog-to-Digital Converter PCB BoM (continued) ...... 122 Table 43: LM46001 5.0 VDC Regulator BoM ...... 122 Table 44: LM20133 3.0 VDC Regulator BoM ...... 123 Table 45: LM20133 1.8 VDC Regulator BoM ...... 123 Table 46: LM20133 1.8 VDC Regulator BoM (continued) ...... 124 Table 47: Voltage Sensor BoM ...... 124 Table 48: SD Card BoM ...... 124 Table 49: MCU BoM ...... 125 Table 50: Current Sensor BoM ...... 125 Table 51: 5” LCD with Capacitive Touch Screen ...... 125 Table 52: Power Factor Correction Circuit BoM ...... 126 Table 53: Power Factor Correction Circuit BoM (continued) ...... 127 Table 54: Power Factor Correction Circuit BoM (continued) ...... 128 Table 55: Power Factor Correction Circuit BoM (continued) ...... 129 Table 56: Power Factor Correction Circuit BoM (continued) ...... 130 Table 57: Total Cost of BoM ...... 131 Table 58: Equipment Provided by TI ...... 131

x 1 Executive Summary The Harmonic Analysis for Quality of Service (HAQS) is a device that is used to measure the overall total harmonic distortion of a three-phase power source. The project’s features will be more along the lines of “quality-of-life,” adding options for displaying harmonic content for voltage, current or overall power. Our group chose this project for a few reasons, one being that it encompassed a healthy combination of electrical engineering and computer engineering majors. The knowledge that our project revolved around was harmonic content, power systems, embedded systems, and analog-to-digital conversion. This project will be a perfect building block for future jobs as well as a challenging path to gaining knowledge. To our group, the most important goal was that our project included challenges while remaining fun and overall was in area of interest to each of us.

This project idea came about through our mentor, Professor Chung Yong Chan, who received a sponsored project from Texas Instruments asking students to design a device to measure harmonic distortion of three-phase power sources. These types of devices do already exist but our secondary focal points are to measure more harmonic values than other products and to pay special attention to sub-harmonic content, as well as keep costs low. The goal for this project is for our group to design a system that, upon being connected to a three-phase power supply, allows the user to navigate using a touch display to receive information of harmonic content ranging from sub-harmonics to the 51st harmonic frequency.

The device will also work with single-phase power sources, in the event that a three-phase power supply is not readily available or for the possible use in homes. Although most of this project has been predefined by our sponsor, fine tuning and picking that perfect part for the job is still necessary. Our group will need to make sure the correct power is delivered to each part we pick, that the communication type between parts is the same, and that we hit our goals of more harmonic points as well as sub-harmonics.

Our project will, based on the menus and sub-menus that the user selects, display total harmonic distortion, harmonic and sub-harmonic content, for three-phase power, voltage or current. Navigation of menus will be done through a capacitive touch liquid crystal display. Current and voltage measurements will be taken using analog-to-digital converters. Our projects coding will take care of the Fast Fourier Transforms of the measured digital signal to convert to the frequency domain and check for harmonic distortion.

All of the previously stated pieces of our project will be combined into our device, used to measure the total harmonic distortion of three-phase power supplies. Overall, our group expects this project to be fun, challenging, and a learning process to benefit us all in the future. Armed with the skills and knowledge to work

1 in a diverse group of engineers we will be prepared for our upcoming careers in the industry. 2 Project Description This project aims to evaluate the THD of the waveforms provided by common mains power outlets. THD is a ratio of the square root of the sum of the signal’s harmonic amplitudes squared and the amplitude of the first harmonic. Ideally, only the first harmonic has an amplitude; any harmonic amplitude after that should be zero.

The exact equation is given below:

( ) %& !"# = *+( ∗ 100, %' where Hn is the amplitude of the signal’s harmonics, from the second harmonic to the nth harmonic; and H1 is the amplitude of the first harmonic. For our purposes, n is fifty-one; and the measured value of THD will provide the value by which we quantify the Quality of Service provided by mains power outlets.

The system will calculate the THD by discretizing the output of the power outlet using an analog-to-digital converter and sending the discretized signal to the microcontroller. The microcontroller will use the Fast Fourier Transform to obtain the frequency response and the separate harmonic content of the sampled waveform. The microcontroller will then conduct an analysis of the first fifty-one voltage and current harmonics to calculate the THD. This value will then be displayed on the LCD for the user to view.

The user will be able to use the physical interface to cycle through the harmonic content information to see where the amplitude spikes that cause THD are occurring. The system will also save the information to an SD card to be uploaded to and viewed on a computer at a later time. 2.1 Project Motivation This project was inspired by the need to determine the quality of power provided by power services. An ideal power signal is a perfect 60 Hz sinusoid with no harmonic content to distort it, but these power signals do not occur in real world applications. As nonlinear elements such as diodes and transistors began appearing in modern day electronics, power signals began to contain harmonic distortion as the nonlinear elements draw currents and voltages that are not perfectly sinusoidal.

These distortions cause some of the transferred signal to exist at different harmonic frequencies. The power transferred through these frequencies is unable

2 to be used by most components within electronic devices today, causing some power transferred to be wasted or even damage components in the device. When harmonic distortion is measured, one can determine if the power being paid for is the ideal 60 Hz sinusoid. 2.2 Project Goals and Objectives Our team’s objective with this project is to create an informative and easy-to-use device that analyzes total harmonic distortion found in three-phase power supplies. We aim to make this device reliable and efficient at analyzing three-phase harmonics.

Another object our team hopes to achieve is making the device possible to operate on both three-phase and single-phase power supply inputs. The reason for that is to give accessibility to households and not limit power harmonic analysis to only those who have access to a three-phase hook up.

Ultimately our goal is to design this device that can benefit all of those who care about the overall quality of power being delivered to their homes. 2.3 Project Requirements and Specifications We have formatted our requirements and specifications into three sections to more clearly organize their topic of limitation. The functionality section details what the final device will be capable of and how it is to be operated. Form factor specifications are provided and describe the size of the device as well as environmental factors. Relevant standards the final device conforms to are also listed in the standards section. The word “shall” will be used to denote a requirement that is guaranteed in the final design. 2.3.1 Functionality The device shall faithfully digitize the analog signal provided by the power outlet under test.

The device shall not let its own power consumption interfere with the QoS calculations.

The device shall compute the Fourier Transform of the discrete signal in order to analyze the harmonic content of the output voltage and current up to the 51st harmonic.

The calculated THD value shall be displayed on an LCD as a percentage.

The device shall display the harmonic content of the AC source on the LCD.

3 The device shall reliably produce consistent results after repeated usage.

Older data shall not interfere with the current data.

The device should prevent damage to itself in the event of an electrical surge.

The software shall conform to the signature of the selected Fast Fourier Transform library.

The system shall run independent of an operating system.

The system shall save analysis information to removable storage media.

The system shall be capable of three-phase metering analysis.

The system shall utilize safety measures for operation in adverse weather conditions.

The device shall be tested in a manner outlined later in this document to verify functionality and fidelity. 2.3.2 Form Factor The device shall be light enough to avoid potentially destructive stress while plugged into a wall outlet.

The device shall be sealed to prevent damage caused by sand, dust, and similar particles.

The device shall weigh no more than one pound.

The device shall be no more than 3” deep, 5” wide, and 7” long. 2.3.3 Standards The system shall adhere to IEEE electrical safety standards.

The system shall adhere to ANSI metering standards.

The system shall adhere to SD Card standards.

The system shall adhere to SPI communication standards

The system shall adhere to I2C communication standards.

The system shall adhere EMI/EMC standards.

The system shall adhere to THD reporting standards. 2.4 Sponsor Considerations This project design was requested and sponsored by Texas Instruments, and as such came with two sets of specifications for the devices. The first specification’s problem statement requests a design that implements a system to show harmonic content using a microcontroller. Its motivation is stated as the following: Advanced electricity meters require measuring power quality as a measure of Quality of Service (QoS). Harmonics provide detailed information on quality of energy generated. Several end equipments relevant to the request are listed such as panel meters, advanced utility electricity meters and solar inverters.

The first specification provided by Texas Instruments lists items they feel would accurately measure the success of the design to fit the request. These can be seen as requirements and are as follows. The system should show harmonic content in an AC source. The device should show voltage and current harmonics up to the 51st harmonic. The device should have the ability to showcase SW/HW integration using discrete or integrated ADC with a microcontroller. These specifications have been noted in the functionality section above.

The second specification provided by TI lists relevant information on the LCD interface for the system. The problem stated was to implement a discrete interface using on-chip digital peripherals to drive a segment based LCD. Its motivation is stated as the following: Segment LCDs are the cheapest form of display used in Smart Meters. Many silicon chips do not have integrated LCD controllers to save cost and size. If this can be demonstrated on one such family of devices, it will show bigger integration. End equipment relevant to the request are similarly listed such as smart electricity meters, smart water/gas meters and smart plugs.

Measures of success are also provided for the second specification and are set as follows. The device should provide proper functionality of commonly used LCD devices under various voltage conditions. The device should have the ability to show between 4 to 6 digits (numeric/alphanumeric). The device should have the ability to show the lowest possible current consumption during microcontroller stand-by or LCD always ON conditions.

These two project specifications were combined into the device we have designed and plan to implement. For the sake of clarity and user-friendly interaction, we have chosen to instead use a touch capacitive LCD screen in the final device due to the nature of the amount of data we wish to represent on screen. 2.5 Project Block Diagram The block diagram for the system is included below in Figure 1.

Figure 1: HAQS Block Diagram

3 Project Background 3.1 Related Products A good start in understanding how to approach the design process of our device is to determine if similar devices exist. Several devices already exist that provide most of the functionality we plan to provide. One specification our design will feature not present in other devices is the ability to display harmonic content up to the 51st harmonic while most others only display up to the 50th. Several devices exist which are designed to measure both single and three-phase source power harmonics, similar to our planned device. 3.1.1 AEMC PowerPad® III Model 8333 The AEMC PowerPad® III Model 8333 is an exceptional meter that can be used to take measurements of both three-phase and single-phase power sources as well as many other power source wiring configurations which include split phase sources, delta connected three-phase sources, and three-phase Wye connected sources where the neutral is not grounded [1]. This particular meter series was found to be in the range of $4,000 and up, putting this meter in a high price range. The physical product includes a color VGA TFT (thin-film transistor) screen that is diagonally 148 mm wide (approximately 5.8 inches), has physical user interface buttons, and weighs 4.3 lbs. The meter can be powered by an included external

6 AC power supply or an internal 9.6 Volt NiMH rechargeable battery with a claimed battery life of greater than 13 hours or 25 hours if the meter is in record mode.

The meter is specified to work for systems with an ideal fundamental frequency of 40 to 70 Hz, will record power measurements and report the values in accordance with IEEE 1459 standards, and measures up to the 50th harmonic of the system being metered [1]. There are more power parameters that are available for measurement on the AEMC meter that were not mentioned. In addition to the vast amount of parameters that can be recorded, this particular meter is able to display the harmonic data recorded using a rendered bar graph, able to display the voltage or current waveforms on a graph with respect to time, output the data to a memory device through its USB interface, and display other power measurements in useful and easy to understand graphs on the meter’s screen. This meter also comes with AEMC’s DataView® software which allows the user to interface and use the meter in real time using a computer through the meter’s USB port.

AEMC’s meter follows IEC 61000-4-30 Class B standards which states that the metering instrument records and reports useful information but the accuracy of the information is not a priority of the metering instrument [2]. The accuracy of the current measured by the AEMC meter is dependent on which sensor made by AEMC the consumer receives with the meter or buys separately. The specifications of this meter state that the THD of the measured voltages and currents are accurate to with an accuracy tolerance of ±2.5% + 5cts excluding two particular AEMC current sensor models [1]. The accuracy of the individual harmonic levels with respect to the fundamental for this meter is ±2.5% + 5cts for the voltage harmonics and for the current harmonics the accuracy is ±2% + 5 ∗ 0.2% + 10cts for harmonics 25 and below and is ±2% + 5 ∗ 0.6% + 5cts for harmonics 26 and above using AEMC’s current sensors excluding the same two particular models that can be found in this meter’s user manual [1].

This meter is a great example of what a high-end power meter should be capable of. Despite the meter’s low priority towards the accuracy of the power measurements, this meter it is quite capable and seems like an exceptional all-in- one meter that can measure just about any power measurement the end user would want to view with an easy to use interface that can graphically display the data in a way that makes interpreting the data easy and AEMC also includes free software to interface and use the meter with a computer. 3.1.2 YOKOGAWA Clamp-On Power Analyzer CW240 The YOKOGAWA Clamp-On Power Analyzer CW240 is another exceptional meter that can also be used to take measurements of both three-phase and single-phase power source networks. This meter can be found in the price range of around $3,000, giving us an example of another power meter that is still in a high price

7 range but is cheaper than the meter by AEMC. This meter has a segmented monochrome LCD screen that is 5.7 inches wide, has physical user interface buttons, and weighs a measly 600 grams which is about 1.32 lbs. This meter can be powered by an included external AC power supply, it can be powered by its optional NiMH rechargeable battery, or by six AA batteries.

Just like the meter by AEMC, YOKOGAWA’s meter has many features that a power meter user would want. The meter is specified to work for systems with an ideal fundamental frequency of 45 to 65 Hz, can simultaneously take measurements of four single phase two wire system loads, can take simultaneous measurements of two single phase (or three phase) three wire system loads, is designed to prevent wiring errors when setting up the meter, measures up to the 50th harmonic of the system being metered, and can also measure more unmentioned power parameters [3]. In addition to the extensive amount of power parameters that can be measured, the software loaded onto this particular meter allows it to record harmonic data and display the harmonic data recorded using a rendered bar graph or a generated list, display the measured waveform shapes with in-depth information on a generated graph, and display the other power measurements it is capable of in simple and easy to understand graphs on the meter’s segmented LCD.

Unlike the AEMC meter, YOKOGAWA’s meter uses RS-232 to interface with other electronics devices such as a computer or a printer. YOKOGAWA’s meter has 1 MB of internal memory and also uses compact flash memory if the user wants to save the data to later view on the meter or a computer. The use of RS-232 for communication and the not so common compact flash memory make interfacing with the meter or saving data from the meter slightly more complicated if the user does not have access to computers with RS-232 communication ports or a compact flash card reader. If the user is able to find a computer with a RS-232 communication port they can utilize the free EasyChart software by YOKOGAWA to easily view the data recorded on the meter.

Similar to AEMC, YOKOGAWA does produce multiple current sensors for the CW240 meter, thus the accuracy and range of current measurements is dependent on what current sensor the end user decides is sufficient enough for their metering purposes. Given in the specifications of YOKOGAWA’s CW240 meter, the accuracy of the 1st to 20th harmonics is ±1.5% due to reading errors and ±1.5% due to the range of the input, the accuracy of the 21st to 30th harmonics is ±2.0% due to reading errors and ±1.5% due to the range of the input, and the accuracy of the 31st to 50th harmonics is ±1.5% due to reading errors and ±1.5% due to the range of the input [3]. Despite the increasing harmonic accuracy range, this meter is another great example of what a high-end power meter should be capable of.

8 3.1.3 Fluke 435 Series II Power Quality & Energy Analyzer The Fluke 435 Series II Power Quality and Energy Analyzer is yet another exceptional power meter that can also be used to take measurements of both three-phase and single-phase as well as many other power source wiring configurations that include split phase sources, delta connected three-phase sources, and single- or three-phase sources without a common neutral connection [4]. This meter can be found in the range of around $8,000, making this the most expensive power meter that was found during our research of existing power meters that can measure the harmonics of a power system. This meter has a color LCD screen that is six inches wide, has physical user interface buttons, and weighs about 2 kilograms (about 4.41 lbs.) with the rechargeable battery. This meter can be powered by an included external AC power supply and it can be powered by its removable Li-ion rechargeable battery which is claimed to have a seven-hour battery life per full charge.

Just like the previously mentioned meters, Fluke put a lot of features into this power meter. The meter is specified to work for systems with an ideal fundamental frequency of 50 or 60 Hz, can record where energy losses occur within a system and estimate how much the consumer is spending on this wasted energy, can measure the phase relationships in a three-phase power source where ideally the phase shift between phases should be 120 degrees, and can measure up to the 50th harmonic of a system and records the THD in accordance with IEC61000-4-7 standards [4]. As with the AEMC and YOKOGAWA power meters, the Fluke power meter is able to measure other important power parameters that the user of a power meter might also want to investigate.

Like the two other previously mentioned meters, the software loaded onto Fluke’s meter allows it to record and display the harmonic data recorded using a rendered bar graph, display the voltages or currents as a waveform similar to an oscilloscope, display the phase relationships between the three-phase sources on an easy to understand graph, and display the other power measurements it is capable of in easy to understand graphs or charts on the meter’s LCD. This meter also comes with Fluke’s Powerlog software to allow the user to interface and use the meter on a computer through the meter’s USB port. Similar to YOKOWAGA’s power meter Fluke’s product supports saving data to removable media, but Fluke’s meter supports SD cards up to 32GB and not the less commonly used compact flash cards.

Similar to AEMC and YOKOGAWA, Fluke produces multiple current sensors that are compatible with the 435 Series II meter. The accuracy of Fluke’s current sensors is either ±1% or ±2% with slight current readings offsets that are specific to each current sensor. As was seen with the other two meters, other

9 measurements that can be made with Fluke can be highly accurate with accuracy tolerances as low as ±0.1%, but the harmonic accuracy tolerance is similar to both AEMC’s meter and YOKOGAWA’s meter with Fluke stating a THD accuracy of ±2.5% for both the measured voltage and current harmonics [4]. Where this meter does lead the pack is the accuracy of the individual harmonic levels with respect to the fundamental with a stated accuracy of ±0.1% ± 5 ∗ 0.1% where n is the harmonic number for both the voltage and current measurements [4]. 3.2 Project Constraints 3.2.1 Economic The final product must be economically feasible and affordable for the team. It must consider the cost of similar, existing solutions so as to not create a product that accomplishes the same goal but with a higher price attached to it. 3.2.2 Environmental The system is not meant to be used in environments that are otherwise unsafe for the operation of electrical equipment. This includes, but is not limited to: rain, snow, and thunderstorms. 3.2.3 Social Social constraints do not impose upon the design or operation of HAQS. 3.2.4 Political Political constraints do not impose upon the design or operation of HAQS. 3.2.5 Ethical Ethical constraints do not impose upon the design or operation of HAQS. 3.2.6 Health and Safety The product will pose no threat to the health and safety of the user. The high- voltage associated with this project will be controlled, processed, and utilized in isolation from the user. 3.2.7 Manufacturability Manufacturability constraints do not impose upon the design or operation of HAQS. 3.2.8 Sustainability Sustainability constraints do not impose upon the design or operation of HAQS.

10 3.3 Relevant Standards 3.3.1 Total Harmonic Distortion Reporting Standard There are two relevant interpretations when it determining how to correctly measure and display harmonic content in the form of total harmonic distortion. The first measurement interpretation is known as THDF. This measurement interpretation involves comparing the harmonic content of a waveform with its fundamental frequency [5]. The second measurement standard, referred to as THDR, involves comparing a waveform’s harmonic content to its RMS value [5]. These two recognized approaches to determining and reporting total harmonic distortion do not differ much in value at low values. As the waveform’s harmonic content increases, however, the two definitions begin to report significantly different total values.

There actual standard interpretation for defining total harmonic distortion, at least with respect to power measurements, involves the interpretation comparing against the waveform’s fundamental [5]. The second interpretation tends to be used for audio amplification applications, and as such is not applicable to this design. We will be making use of the interpretation comparing harmonic content of a given waveform to its fundamental due to the analyzed waveform being a power signal. 3.3.2 Metering Standards Below is a list containing a few relevant International Electrotechnical Commission (IEC) standards of metering for smart grids:

Power Systems Management and Communication – This standard refers to a uniform framework and architecture for the development and application of exchange in power system information. It also offers general principles and guidelines for systems using electric utility operations. This standard also takes into consideration the evolution of technologies and new concepts, in order to develop technological trends in the industry.

Energy Management System Application Program Interface (EMS-API) – This standard provides a general infrastructure as well as a set of guidelines that are required for applications of EMS-API. This standard defines typical scenarios where it’ll be used and the types of applications that it’d be integrated with, as well as providing a framework for the application of other parts.

Data and Communications Security – This standard refers to security of information for power system control operations. It focuses on providing all information in regards to securely communicating information.

Data Exchange for Meter Reading, Tariff and Load Control – This standard describes protocol specifications and hardware design for local meter data exchange. This standard pertains mostly to hand-held units (HHU) or at least units with similar functionality that are connected to a group of devices or tariff device.

Functional Safety of Electrical/Electronic/Programmable Related Systems – This standard covers the issues of safety around (E/E/PE) systems, with a major focus on facilitating the development of applications’ and products’ international standards. This will allow all the relevant factors, associated with the product or application, to be fully taken into account and thereby meet the specific needs of users of the product and the application sector. A second objective of this standard is to enable the development of E/E/PE safety-related systems where product or application sector international standards do not exist [6]. 3.3.3 Electrical Safety Standards Below is a list containing a few relevant Occupational Safety & Health Administration (OSHA) standards of safety for electrical related subsystems and interactions with them:

Electrical Protective Devices - This standard regulates Design requirements for specific types of electrical protective equipment. Rubber insulating blankets, rubber insulating matting, rubber insulating covers, rubber insulating line hose, rubber insulating gloves, and rubber insulating sleeves shall meet certain requirements listed further in the documented standard.

Electrical Power Generation, Transmission, and Distribution – This standard regulates the operation and maintenance of electric power generation, control, transformation, transmission, and distribution lines and equipment.

Electric Utilization Systems – This standard regulates electrical installations and utilization equipment installed or used within or on buildings, structures, and other premises.

General Requirements – This standard regulates basic requirements of electrical subsystems and allowing examination to ensure standards are met.

Wiring Design and Protection – This standard regulates the labeling of device wiring and protection in product design. It also ensure proper grounding terminal connections are labeled.

Wiring Methods, Components, and Equipment for General Use – This standard regulates conductors that are not an integral part of factory assembled equipment, such as: Metal raceways, cable trays, cable armor, cable sheath, enclosures,

12 frames, fittings, and other metal noncurrent-carrying parts that are to serve as grounding conductors, with or without the use of supplementary equipment grounding conductors. It also states the necessity of their bounding to ensure electrical continuity.

Specific Purpose Equipment and Installation – This standard pertains to electric signs and outline lighting. For example, each sign and outline lighting system, or feeder circuit or branch circuit supplying a sign or outline lighting system, shall be controlled by an externally operable switch or circuit breaker that will open all ungrounded conductors. However, a disconnecting means is not required for an exit directional sign located within a building or for cord-connected signs with an attachment plug.

Hazardous (Classified) Locations – This standard regulates requirements for electric equipment and wiring in locations that are classified depending on the properties of the flammable vapors, liquids or gases, or combustible dusts or fibers that may be present therein and the likelihood that a flammable or combustible concentration or quantity is present. Hazardous (classified) locations may be found in occupancies such as, but not limited to, the following: aircraft hangars, gasoline dispensing and service stations, bulk storage plants for gasoline or other volatile flammable liquids, paint-finishing process plants, health care facilities, agricultural or other facilities where excessive combustible dusts may be present, marinas, boat yards, and petroleum and chemical processing plants. Each room, section or area shall be considered individually in determining its classification.

Special Systems – This standard regulates all of the general requirements for any circuit and equipment that operates at over 600 volts.

Scope – This standard regulates electrical safety-related work practices for both qualified persons (those who have training in avoiding the electrical hazards of working on or near exposed energized parts) and unqualified persons (those with little or no such training) working on, near.

Training – This standard regulates rules applied to employees who face a risk of electrical shock that is not reduced to a safe level by the electrical installation requirements. It also lists employee occupations that require the employees to be trained and must understand the expected risk associated with electrical hazards present.

Selection and Use of Work Practices – This standard regulates that Safety-related work practices shall be employed to prevent electric shock or other injuries resulting from either direct or indirect electrical contacts, when work is performed near or on equipment or circuits which are or may be energized. The specific

13 safety-related work practices shall be consistent with the nature and extent of the associated electrical hazards.

Use of Equipment – This standard regulates the use of plug and cord connected equipment, including flexible cord sets, such as extension cords.

Safeguards for Personal Protection - This standard regulates the use of personal protective equipment. It also states that Employees working in areas where there are potential electrical hazards shall be provided with, and shall use, electrical protective equipment that is appropriate for the specific parts of the body to be protected and for the work to be performed [7]. 3.3.4 Communication Standards At the low end of the inter circuit communication spectrum are the two most common forms of communication between peripherals: I2C and SPI. Together these forms of communication complimentarily coexist with each other quite nicely, even for being some of the slower forms of on-board communication [8]. 3.3.4.1 SPI Communication Standards The Serial Peripheral Interface (SPI) bus is the paragon of standards for pin communication. The main problem with this is that is lacks any kind of formal standard that can reflect all of the possible protocol options it has. Word sizes change between devices, that’s a common fact. The problem is that every device defines its own protocols differently, along with whether or not they even support commands at all. Certain devices can be only receivers, whereas other devices can be just transmitters, and other devices can be combinations of both. Sometimes chip selects for certain devices will differ as well, some will be active high while the others may be active low. Some devices have protocols that send most significant bits first but other devices are the opposite.

Some devices even have minor variances from the CPOL/CPHA modes described above. Sending data from slave to master may use the opposite clock edge as master to slave. Devices often require extra clock idle time before the first clock or after the last one, or between a command and its response. Some devices have two clocks, one to read data, and another to transmit it into the device. Many of the read clocks run from the chip select line.

Some devices require an additional flow control signal from slave to master, indicating when data are ready. This leads to a 5-wire protocol instead of the usual 4. Such a ready or enable signal is often active-low, and needs to be enabled at key points such as after commands or between words. Without such a signal, data transfer rates may need to be slowed down significantly, or protocols may need to have dummy bytes inserted, to accommodate the worst case for the slave response time. Examples include initiating an ADC conversion, addressing the

14 right page of flash memory, and processing enough of a command that device firmware can load the first word of the response [9]. (Many SPI masters do not support that signal directly, and instead rely on fixed delays.)

SPI isn’t perfect, some flaws that it does have are associated with its protocols. It can only support messages that are sent in multiples of 8 bits. Because of this, protocols involving SGPIO or even JTAG cannot operate together.

There are also hardware-level differences. Some chips combine MOSI and MISO into a single data line (SI/SO); this is sometimes called 'three-wire' signaling (in contrast to normal 'four-wire' SPI). Another variation of SPI removes the chip select line, managing protocol state machine entry/exit using other methods. Anyone needing an external connector for SPI defines their own: UEXT, JTAG connector, Secure Digital card socket, etc. Signal levels depend entirely on the chips involved. Even the automotive industry, with its ever growing use for electronics in vehicles. The known industry standard is called SafeSPI and mainly focuses on the sensors located in vehicles and their ability to transmit data between different devices [10]. 3.3.4.2 I2C Communication Standards The I2C was redesigned to incorporate three levels: the interface level, the protocol level and the signal level. The interface level can tend to get more complex when it comes to reusability, because each unique new device will have its own number of operation modes. It can also change the number and duration of the operation mode to sort of shift to a more reusable mode. The protocol level is great because it’s not limited by the need for modification in order for it to be reusable. The signal level creates its reusability by setting the number of transferred bytes according to whatever current operation is running [11].

Currently not all of the I2C operations are designed due to reasons dealing with low power. This design method was design in VHDL, implementation in FPGA and applied in bio-logging design for RTC and light sensor which are based on I2C protocol. The data acquired by light sensor were transferred through RS-232 to PC and stored into text file. The file was shown into graph by using Matlab. The data acquired by RTC were shown by RS-232 tool. The correctness efficiency can be confirmed by simulation results [12]. 3.3.5 SD Card Common Interface Standard The Secure Digital (SD) Card is an industry standard format is used in digital devices around the world. There are three formats SD Cards are available in: SDSC (Standard Capacity), SDHC (High Capacity) and SDXC (Xtended Capacity) which allow for different maximum capacities. There are also three form factors each card can come in the form of: SD, miniSD and microSD from largest to smallest. Table 1 contains information about the different types of SD cards. The standard states the following features [13]:

15 • Capacity of Memory: o SDSC: Up to and including 2GB o SDHC: More than 2GB and up to and including 32GB o SDXC: More than 32GB and up to and including 2TB • Voltage Range: 2.7V – 3.6V • Read-Only and Read/Write designations • Bus Speed Mode with 4 parallel data lines

Table 1: SD Card Comparison Bus Speed Signaling Frequency Data Rate Mode Voltage Default Speed 3.3V 25 MHz 12.5 MB/sec Mode High Speed 3.3V 50 MHz 25 MB/sec Mode SDR12 1.8V 25 MHz 12.5 MB/sec SDR25 1.8V 50 MHz 25 MB/sec SDR50 1.8V 100 MHz 50 MB/sec SDR104 1.8V 208 MHz 104 MB/sec DDR50 1.8V 50 MHz 50 MB/sec on both clock edges

• Switch function command that supports Bus Speed Mode, Command System, Drive Strength and future functions • Correction of memory field errors • Content shall not be harmed from card removal during read operation • A Content Protection Mechanism shall be present which complies with highest security of SDMI standard • Password Protection of cards (CMD42 – LOCK_UNLOCK) • Write Protect feature using mechanical switch • Built-in write protection features • Detection of insertion or removal of card • Comfortable erase mechanism • Must follow one of the three form factors: Standard Size SD, miniSD, or microSD • Standard Size SD Memory Card thicknesses: 2.1 mm (normal) or 1.4 mm (Thin SD) • Communication channel protocol attributes: o Six-wire communication channel (clock, command, 4 data lines) o Error-protected data transfer o Single or Multiple block oriented data transfer

16 3.3.6 Electromagnetic Interference and Electromagnetic Compatibility Standards Regulations and standards have been coming out of the woodworks for Electromagnetic Interference (EMI) and Electromagnetic Compatibility (EMC). This is bound to happen due to the ever increasing number of electronic devices, all giving off their own electric fields. Standards will vary from country to country and where you plan to sell or operate, your product will be governed by said regulations [14]. More details about EMI and EMC standards can be found in Table 2.

There are three requirements that a country will apply, one or more, to products to ensure the keep to the compatibility of electromagnetic standards.

Verification – this ensures that the product has been tested to comply with the electromagnetic compatibility standards

Declaration of Conformity – this ensures that the vendor of the product has conformed said product to EMC standards

Certification – this ensures that the test results of the product from a trusted laboratory have been examined by a third party to ensure it meets EMC standards In the United States authoritative jurisdiction varies by administration depending on the product, and their steps for approval vary accordingly [14].

Table 2: EMI and EMC Standard Information Product Type ITE Medical Appliance Radio Authority FCC FDA FCC FCC exempt Approval Procedures EMI: Certification N/A Certification verification DoC: accredited Cert: accredited In-Country No No N/A No Testing Required? MRA with US N/A N/A N/A N/A Marks DoC: FCC N/A N/A None logo

Some of the standards revolving around EMI deal with the antenna factors and antennas used for radiated emission measurements of electromagnetic

17 interference (EMI) from 9 kHz to 40 GHz are provided. Antennas included are linearly polarized antennas such as loops, rods (monopoles), tuned dipoles, biconical dipoles, log-periodic dipole arrays, hybrid linearly polarized arrays, broadband horns, to name a few [15]. 3.4 Research 3.4.1 Harmonic Analysis The main objective of the device specified in this document is to provide a description of the harmonic content in three-phase power sources. This will be accomplished by sampling the three-phase power signal and performing a Fourier Transform on the sample. There are several techniques and algorithms to consider with respect to this frequency domain transformation. 3.4.1.1 Discrete Fourier Transform A naïve Discrete Fourier Transform (DFT) can be used to approximate the frequency response of a sampling. This technique will allow for easier software implementation, requiring less complex functionality to accurately transform the samples taken. This implementation will require only an iterative algorithm that passes through the sample set for computation. This technique will, however, run more slowly when compared to more complex implementations. The naïve Discrete Fourier Transform approach is known to have a time complexity of O(n2), scaling in runtime quickly with respect to the size of the transformed sample. Depending upon how many samples are taken, this second order time complexity will become a non-trivial issue to consider. 3.4.1.2 Fast Fourier Transform Contrary to the naïve Discrete Fourier Transform, a Fast Fourier Transform (FFT) algorithm tends to be implemented recursively. This leads to a time complexity more along the lines of O(n*log(n)) as the stack tends to build a calling tree of logarithmic height. This implementation will solve the major issue introduced in the naïve Discrete Fourier Transform approach: runtime. A Fast Fourier Transform, however, will require more complex implementation characteristics depending on how it is approached. This technique makes use of recursion as opposed to nested iterative loops, making its conception and understanding a bit harder to follow. Additionally, there is higher memory consumption during execution as the stack populates with recursive calls to the function.

A twiddle factor calculation is also needed within each recursion in the popular Cooley-Tukey approach that requires complex numbers to be multiplied, further adding to the complexity of implementation. Finally, as a restriction, non-adjusted Fast Fourier Transform algorithms require input sample sizes to be a power of two in count. While this is not hard to account for, it does prevent an optimally small

18 sample size from being used potentially adding unnecessary redundancy to the sample sets taken in. These tradeoffs may be worth the investment given the requirements of the device. The device must perform six Fourier Transforms in one sample and respond to the user in a timely manner. Given enough samples to provide an accurate analysis, time will by far be the largest concern when deciding on an implementation. 3.4.1.2.1 Windowing Performing a Fast Fourier Transform, while efficient, has limitations due to the fact that the sample used is finite in size. A Fast Fourier Transform assumes that the sample to be transformed can be repeatable as it exists whether or not it is a non- whole number multiple of the period of the actual signal. Consider the below sine wave sampled for two whole periods of the signal. Its Fourier transform, if taken as an FFT, will generally produce the expected spike at the frequency of the signal.

If the sample below is used instead, a less optimal FFT result will be given. This phenomenon is called spectral leakage and causes nearly every frequency in the resulting discrete frequency domain to yield large amplitudes. Below the sample in Figure 2 is its expected FFT result graph in Figure 3.

Figure 2: Sinusoidal Waveform with Smaller Window

Figure 3: FFT of the above Sinusoid as a Result of a Smaller Window

Windowing can be used to minimize this phenomenon through multiplying the sample with what is known as a windowing function. This function is of a finite length and follows the local minimums and maximums of the sample to create a similar but more stretched out version of the sample with a whole number of periods. There are several window functions to choose from when implementing a windowing approach. For our purposes, we are looking at all harmonics from the 1st to the 51st, so it will be optimal to make use of a windowing function that smoothly covers a large bandwidth. If we do choose to make use of a windowing function, the Hanning window can be used to smooth the results of a Fast Fourier Transform.

We can avoid needing to make use of a windowing function by attempting to take samples over a duration that we predict is a multiple of the period of the signal. As power signals generally should operate at 60Hz, it should be relatively easy to define an amount of time through which samples can be taken to approximate whole number multiples of the signal’s period. There is expected to be harmonic content in the signal, so the actual signal will not consist solely of a 60Hz component and therefore its period will not exactly align with this approximated value. Depending on how close to the signals actual period this approximated value can be, we will not need to perform the more complex operation of multiplying the sampled signal with a defined fixed-length windowing function. This approach can save time, energy consumption and software design time. 3.4.1.2.2 Sample Synchronization The device is required to provide harmonic analysis on a three-phase power source. Given this, it is known that six samples will need to be taken for accurate power analysis: three voltage signals and three current signals. Accurate power calculations will require that at least two samples be taken simultaneously during the process: one corresponding pair of voltage and current signals. The three pairs from the sources can be sampled separately if necessary to ensure synchronization. This synchronization issue will rely on the ability of the ADC unit to sample multiple sources simultaneously. 3.4.1.3 Fourier Transforms: Discrete vs. Fast Table 3 provides a short glimpse of what characteristics were considered between the algorithmic approaches to transforming samples into the frequency domain.

20 Table 3: Comparison of DFT and FFT Algorithm Time Ease of Sample Size Space Twiddle Complexity Implementation Restrictions? Complexity factor?

Naïve O(n2) Iterative No O(n) No DFT implementation

FFT O(n*log(n)) Recursive Dependent on O(n*log(n)) Yes (Cooley- implementation complexity of Tukey) implementation

3.4.2 Analog-to-Digital Converter In order to be able to analyze the harmonic content of a power outlet’s output, the analog waveform must first be digitized. The goal is to find an accurate analog-to- digital converter (ADC) that prioritizes speed and resolution. The input frequency bandwidth is of less concern due to the fact that mains power outlets operate at a relatively low frequency. Even at the fifty-first harmonic, the frequency is 3120 Hz, while many ADCs available on the market can digitize input signals in the megahertz range. Finally, cost must be considered. The final solution must meet the specified requirements, but it must also be financially feasible. 3.4.2.1 Types of Analog-to-Digital Converters 3.4.2.1.1 Successive Approximation Register ADC As the name suggests, a Successive Approximation Register (SAR) ADC executes successive approximations based on the redistribution of charges in a series of parallel capacitors. The capacitors used in an n-bit SAR ADC are of specific, binary values relative to the leading capacitor, C. After C, the following capacitors, are chosen such that their capacitances are equal to C/21, C/22, C/23, etc., concluding with two capacitors of the value C/2n+1. This creates an equivalent capacitance of 2C. Additionally, a SAR ADC requires several switches and a voltage reference in order to complete the conversion. Figure 4 illustrates the basic structure of a SAR ADC [16].

The SAR ADC converts analog signals into digital signals in three stages. First is the Sample stage, in which the capacitors are charged by the input voltage and grounded. During the Hold stage, the capacitors are discharged into a comparator by grounding the terminal that was previously being charged in the Sample stage and connecting the terminals that were previously grounded to the inverting input of the comparator [16].

Figure 4: SAR ADC Converter Architecture Reprinted with permission from Texas Instruments

The Redistribution stage is broken into n steps. The first step connects the capacitor to the voltage reference and to the inverting input of the comparator. This generates the most signification bit. If the voltage across C < 0, then the comparator goes high. Conversely, if the voltage across C > 0, the comparator goes low. The newly generated bit is sent to a register and released as an output in response to a clock signal. Depending on the value of the most significant bit, C will either be discharged (if high) or will remain connected to the reference voltage (if low). In either case, the process continues across the capacitor array until all bits have been determined for the given sample [16]. The system described is shown in Figure 5.

Figure 5: SAR ADC Block Diagram Copyright Maxim Integrated Products (http://www.maximintegrated.com). Used by permission.

SAR ADCs make up the majority of mid-to-high resolution ADCs, with resolutions ranging from 8 to 18 bits and a sampling rate of up to 5 mega-samples per second

22 (MSPS). Special calibration protocol is required to ensure the accuracy of SAR ADCs and to reduce the effect of noise in the system, but the calibration pays off in the form of a compact, accurate, fast, power-efficient ADC [17].

However, one of the obvious drawbacks of the SAR ADC is its dependence on the capacitor array. Component values vary, and it is not uncommon for capacitors to have tolerances of 5%, 10% or even 20%. The problem is that higher-resolution conversions require more accurate components. Furthermore, the comparator also needs to exhibit a high level of accuracy in order for the system to be considered fully reliable. Another issue is that of timing. SAR ADCs require precise timing responses in order for the system to work correctly. Although there are practices in place to ensure the accuracy of a SAR ADC, such as trimming and calibration, there exist other ADCs that do not require such precautions [17]. 3.4.2.1.2 Flash ADC Flash Analog-to-Digital, as shown below in Figure 6, converters utilize a network of resistors and comparators to produce a digitized signal. For an n-bit converter, a Flash ADC requires 2n-1 comparators and 2n resistors of equal value. The series of resistors acts as voltage dividers for the reference voltage, which is applied at the most significant resistor (which generates the most significant bit). This provides a baseline voltage, to which the input signal will be compared, to the inverting input of each comparator. The analog input, then, is connected to the non-inverting input of each comparator. The input voltage will ultimately be of a value that is between two of the divided reference voltages. From that point, the more significant comparators will output low, while the less significant comparators will output high [18].

Flash ADCs require several basic adjustments to optimize their performance. Typically, a Flash ADC will output a code such as 00111111. This is expected, as the output for Flash ADCs will always be a series of 1’s, followed by a series of 0’s, barring any errors. Occasionally, the decoder will produce an output such as 00111101, for the same input level. This is known as a sparkle code, which is often caused by mismatched comparator timing. The errors caused by sparkle codes can be significant, but track-and-hold techniques, similar to those utilized in SAR ADCs, can reduce them [18].

Another issue can arise when the comparator output is indecipherable between high and low. This issue, known as metastability, can be assuaged by slowing the ADC down and preventing the n bits from all changing at once. Metastability can also be problematic when the ADC is controlling multiple circuits. Though it is easier and more cost efficient to use one ADC for multiple circuits, it is better from a reliability standpoint to simply use one ADC per circuit. Such practices can reduce metastability issues [18].

Figure 6: Flash Analog-to-Digital Converter Architecture Copyright Maxim Integrated Products (http://www.maximintegrated.com). Used by permission.

Finally, Flash ADCs are dependent upon accurate and reliable timing. As such, any jittering or stuttering with the sampling clock will produce undesirable results. The issue becomes more apparent at high input frequencies. The simple fix for this issue is to utilize sampling clocks that exhibit low levels of jitter [18].

Due to the parallel bit-generation of Flash analog-to-digital conversion, Flash ADCs are the fastest option available, with sampling rates exceeding Giga- samples per second (GSPS). Additionally, conversion speeds to not decrease with increased resolution, unlike other ADC options. However, these ADCs are also limited to a typical maximum of 8-bit resolution. Thus, they are not preferred in situations requiring high resolution [18].

Despite the speed attainable with Flash ADCs, the limitations regarding resolution are what keep these from being a viable option for our purposes. Even at a

24 maximum, the resolution that Flash ADCs offer is insufficient for our purposes. Couple this with the fact that the highest-resolution Flash ADC exhibits drastic increases in die size, cost, and power consumption, and the viability of Flash ADCs diminishes [18]. 3.4.2.1.3 Sigma-Delta ADC Sigma-Delta ADCs leverage analog and digital circuity to produce high-resolution conversions, while keeping cost and power consumption low. The addition of digital circuity, which accounts for roughly 75% of the Sigma-Delta ADC makeup, increases the complexity of Sigma-Delta ADCs [19].

Sigma-Delta ADCs maintain their signal integrity and keep noise low through a process known as oversampling. Sigma-Delta ADCs sample analog inputs at a frequency significantly higher than the frequency of the input signal. The Nyquist Sampling Theorem states that proper sampling requires a sampling frequency of twice the input frequency of the input signal, but these overclocked samplers are often working at sampling frequencies twenty times the frequency of the input signal. This spreads the quantization noise across a broader range of frequencies. A digital filter removes the noise beyond the frequency of the input signal, allowing the Sigma-Delta ADC to provide high resolution analog-to-digital conversion with a low resolution ADC [20].

Oversampling works in tandem with a process known as noise shaping. Oversampling distributes the quantization noise, but noise shaping shifts the noise to higher frequencies by summing the error voltage via an integrator; this is what makes Sigma-Delta ADCs useful for low frequency applications that require high levels of accuracy. The utilization of the same digital filter mentioned before now has an increased effect and removes an overall higher amount of noise from the system. It is important to note that these methods do not alter the total noise power. It does however redistribute it in a way that makes noise more easily removable via digital filters [20].

Sigma-Delta ADCs work in two steps. The first step, called delta modulation, encodes the change (delta) in the input signal, as opposed to the absolute value of the signal, into a stream of bits. The ADC will output a 1 if the comparator’s output is positive and a 0 if the comparator’s output is negative. That is to say, the output will be a one if the input signal is increasing and a 0 if the input signal is decreasing. In the second step, the output is fed into a digital-to-analog converter (DAC), then into a summing (sigma) junction, where the DAC output is averaged. The average of the DAC output is equal to the input value, with the inclusion of some noise, and is then fed through the filter mentioned above to produce the final output. Figure 7 below shows a Sigma-Delta ADC block diagram [21].

Figure 7: Sigma-Delta Analog-to-Digital Converter Block Diagram Copyright Maxim Integrated Products (http://www.maximintegrated.com). Used by permission.

Averaging the stream of bits approximates and quantizes the the input signal at the same time. The 1’s and 0’s in the bit stream are added together at the summing junction into discrete levels. The step that averages the total sum is crucial to enabling the quantized summation to increase or decrease with the input signal. A stream of 1’s will cause the output levels to increase, while a stream of 0’s will cause the output levels to decrease as the average is calculated. A stream with a relatively stable number of 1’s and 0’s produces a flat output [21].

Sigma-Delta ADCs suffer from being a comparatively slow method of analog-to- digital conversion, due to the use of oversampling and filtering. The filtering process also causes latency, further slowing the system. Oversampling consequently limits the maximum frequency of the input signal. If the goal is for the sampling frequency to be roughly 20x that of the input, the input’s frequency must remain within a reasonable boundary. The maximum input frequency for a Sigma- Delta ADC is generally less than 1 MHz, which ideally requires a sampling frequency of 20 MHz [20].

What Sigma-Delta ADCs lack in speed, though, they make up for in resolution. These devices typically offer 12- to 24-bit resolution—the highest resolution available in any ADC. Furthermore, they do not require the same calibration and trimming techniques required in SAR ADCs; instead they sometimes feature a simple anti-aliasing filter, though these are not necessary. Sigma-Delta ADCs also boast the advantages of low cost, low power consumption, and high stability, which is achieved in the process of shaping and filtering out noise [20]. 3.4.2.2 Analog-to-Digital Converter Conclusion Following the research on the different types of ADCs and their respective advantages and disadvantages, the conclusion is to use a Sigma-Delta ADC for HAQS, though SAR ADCs come with their own merits that needed to be considered and evaluated. The limited bandwidth will not be an issue, as the

26 highest frequency of interest is 3120 Hz. Sigma-Delta ADCs offer a high resolution that will be necessary in faithfully and reliably digitizing the mains power outlet output, which will allow a more accurate measure of the output’s Total Harmonic Distortion. A higher resolution also reduces quantization noise (discussed in the following section). Low power consumption and cost are also of high importance for the purposes of HAQS. Finally, the issue of speed is dismissible, as speed is less important than the advantages listed above. HAQS will utilize a Sigma-Delta ADC. A summary of the advantages and disadvantages of each type of ADC is compiled in Table 4.

Table 4: ADC Comparison Chart SAR Flash Sigma-Delta Advantages +Mid-to-High +Fasted ADC +Highest resolution Resolution +Small and cost +Fast sample rate effective +Low noise +Low noise +Cost effective +User friendly +High maximum +High stability frequency Disadvantages -Specialized -Low resolution -Higher power calibration -Specialized consumption techniques calibration -Slow conversion -High dependence techniques -Lower maximum on component -Timing frequency accuracy difficulties -Timing difficulties

3.4.3 Quantization Noise Quantization Noise occurs during the digitization process when a sampled value from the analog signal falls between two discrete values of the digitized signal; that is to say quantization noise is a discrepancy between the analog input and the digital output. Quantization noise is often measured as a ratio of signal strength to noise level in a measurement called Signal-to-Quantization-Noise Ratio (SQNR) [22].

There are several methods that can be used to reduce quantization noise and increase SQNR. First is the inclusion of analog compressors and expanders. In a process called “companding,” the signal is compressed before entering the ADC, meaning the the levels are scaled up or down in order to obtain a relatively stable maximum and minimum waveform value. After digitization, the expander undoes the work of the compressor by decreasing the levels that were increased and increasing the levels that were decreased by the compressor [22].

27 Another method of increasing SQNR is to use a higher resolution ADC. As previously discussed, Sigma-Delta ADCs boast the highest available resolution of any type of ADC. The purpose of HAQS is to measure Total Harmonic Distortion. In order to maintain the integrity of that measurement and not artificially inflate the THD during the analog-to-digital conversion phase, it is of utmost importance to keep quantization noise as low as possible. As such, a high-resolution Sigma-Delta ADC is the most appropriate choice for the needs and requirements of HAQS [22]. 3.4.4 Data Input Methods 3.4.4.1 Single-Ended Inputs A single-ended input measures an input voltage against a single reference point, usually an analog ground, as shown in Figure 8. This method is cost efficient and effective for maintaining a smaller form factor: for N signals, there are N+1 input [23].

Figure 8: Single-Ended Input Reprinted with permission from MCCDAQ

This can be a problem though. Consider a system with multiple input lines. When each input is measured according to the same reference plane, the measurement’s accuracy is potentially compromised by noise. With single-ended inputs, there is no way to differentiate between the signal and the noise that the input lines pick up. In practice, single-ended inputs are preferred only when form factor is a crucial issue [24]. 3.4.4.2 Differential Inputs The differential input method provides each input line with its own reference, as illustrated below in Figure 9. Thus, for N signals, there are 2N inputs. Behind the differential inputs are three amplifiers: two to monitor the incoming voltage and one difference amplifier that compares the input to the reference voltage, which again

28 is usually an analog ground. This configuration is commonly known as an instrumentation amplifier [23].

Figure 9: Differential Input Reprinted with permission from MCCDAQ

Because each differential input is fed into an instrumentation amplifier, any electromagnetic interference that the transmission lines pick up will be subtracted out due to the fact that the EMI would be common to both lines. Twisting the differential inputs together furthers common noise cancellation, keeping the signals much cleaner than a single-ended input would. This is advantageous when the signals are of a low voltage. Since the 120 VRMS output of the three-phase outlet is being reduced to ±1 V, the effect of noise would be even more apparent; and noise, therefore, must be minimized [24].

The obvious disadvantage with differential-inputs is form factor and, consequently, cost. However, the advantages of differential inputs far outweigh these issues. Furthermore, size is of small concern for HAQS. HAQS must be portable by one person, but achieving absolute minimum form factor is not a requirement [24]. 3.4.4.3 Data Input Method Conclusion The same motivation for choosing a 24-bit Sigma-Delta ADC is present in this decision. In order to keep noise low and maintain the fidelity of the THD measurement, differential inputs will be used to interface the three-phase voltage and current lines with the ADC. The utilization of twisted pairs will also aid in noise reduction. The disadvantage of a larger form factor is not enough of a drawback for HAQS to utilize single-ended inputs instead. 3.4.5 Microcontroller Unit The microcontroller unit can be considered the heart of many electrical designs that make use of one. This is due to the fact that the microcontroller generally interfaces with every other component in a design. Because of this, microcontroller design must take into account the specifications of all other designed devices

29 within the whole project. Considerations for interfacing include issues like general purpose input/output (GPIO) pin count, number of available communication channels of each communication standard, amount of onboard ADC channels and width of onboard ADC channels. Additionally, features specific to microcontroller performance should be taken into account such as their frequency of instructions per second, available internal memory, power usage, inclusion of a hardware multiplier, instruction set architecture implemented and the extent of the microcontroller units floating point hardware support. 3.4.5.1 Launchpads Given that our project was requested and sponsored by Texas Instruments, it follows that our microcontroller unit can be supplied by them. In designing and testing our prototype device, the LaunchPads TI makes available can ease the process. LaunchPad units are designed to integrate with community created BoosterPacks which allows more hardware to be easily integrated into the testing unit without designing a new printed circuit board. LaunchPad units may also provide additional breakout pins for easy prototyping and breadboarding external circuits. Given this information, whether a microcontroller unit exists in an available launch pad is a factor to consider when deciding which microcontroller to use within design. 3.4.5.2 Available Processors TI has hundreds of microcontroller units available, so in order to determine which ones to consider a general specification can be applied to limit the possibilities. Our design specifies that our microcontroller unit will be communicating with at least two devices: the SD card reader and the touch capacitive LCD screen. Given this information, we should be looking for microcontroller units with a high number of communication channels. Additionally, as we plan to make use of a Fourier Transform algorithm in our computations, we will potentially be calling a floating point multiplication operation hundreds of times in one sample. Having a 32x32 hardware multiplier will be advantageous for efficiently completing the digital signal processing. Finally, as we want the device to use as little power as possible we will look at the MSP430 and MSP432 series of low-power microcontrollers.

Table 5 below details the options available from Texas Instruments when a large number of communication channels, 32x32 multiplier support and low-power usage considerations are taken into account. TI communication channels tend to always support SPI standards, so an SPI channel count of eight was used to determine the options below.

30 Table 5: TI Processors MCU Freque Non- RAM GPIO ADC Active Special ncy Volatile Pins Power I/O Memory

MSP430 25 128KB 16KB 53 Slope 404µA N/A F5252 MHz MSP430 25 128KB 16KB 53 10- 404µA 1.8V F5253 MHz 10ch I/O MSP430 25 128KB 32KB 53 Slope 404µA 1.8V F5254 MHz I/O MSP430 25 128KB 32KB 53 10- 404µA 1.8V F5255 MHz 10ch I/O MSP430 25 128KB 16KB 53 Slope 404µA 1.8V F5256 MHz I/O MSP430 25 128KB 16KB 53 10- 404µA 1.8V F5257 MHz 10ch I/O MSP430 25 128KB 32KB 53 Slope 404µA 1.8V F5258 MHz I/O MSP430 25 128KB 32KB 53 10- 404µA 1.8V F5259 MHz 10ch I/O MSP430 25 128KB 16KB 87 12- 356µA N/A F5419A MHz 14ch MSP430 25 192KB 16KB 87 12- 356µA N/A F5436A MHz 14ch MSP430 25 256KB 16KB 87 12- 356µA N/A F5438A MHz 14ch MSP432 48 128KB 32KB 84 14- 90µA Capacit P401M MHz 24ch ive Touch I/O MSP432 48 256KB 64KB 84 14- 90µA Capacit P401R MHz 24ch ive Touch I/O

3.4.5.3 Instruction Set Architecture Given that our project was requested and sponsored by Texas Instruments, it follows that our microcontroller unit can be supplied by them. In designing and testing our prototype device, the LaunchPads TI makes available can ease the process. LaunchPad units are designed to integrate with community created BoosterPacks which allows more hardware to be easily integrated into the testing

31 unit without designing a new printed circuit board. LaunchPad units may also provide additional breakout pins for easy prototyping and breadboarding external circuits. Given this information, whether a microcontroller unit exists in an available launch pad is a factor to consider when deciding which microcontroller to use within design. 3.4.5.3.1 ARM v6/7 The ARM architecture is a standard architecture supported in many TI microcontrollers. The ARM architecture boasts smaller, simpler instructions that can run quickly. ARM code is generally faster but longer when compiled or optimized. Compiled code length impacts performance in two ways: ease of writing assembly code and internal memory usage tied to storing source code. If a different language is used to write the source code to be executed, the ease of writing assembly will not be a factor as an available optimizing compiler will perform this work for the writer. These smaller ARM instructions allow the architecture to waste fewer microinstructions in its pipeline. This leads to faster execution times and less power consumption as the hardware is computing less unnecessary microinstructions. 3.4.5.3.2 Thumb-2 Several TI microcontrollers also support the Thumb-2 architecture in addition to ARM. The Thumb-2 architecture, when compared to ARM, provides more complex and convenient instructions for an easier time writing assembly code. Thumb-2 is generally available when the device has more hardware support to avoid inefficiencies in running complex instructions with multiple cycles. These larger instructions contribute to a smaller compiled code size, minimizing usage of internal microcontroller memory. As there are large instructions available, it follows that the size of the pipeline in an implementation will also be longer. This will mean smaller instructions may waste time and energy idling the different stages in hardware. 3.4.5.3.3 Arm v6/7 vs. Thumb-2 Table 6 below shows considerations made when deciding which instruction set architecture support would be preferred in the microcontroller unit of our design.

Table 6: Arm v6/7 vs. Thumb-2 Feature ARM (v6/7) Thumb-2 Smaller Code Size More Energy Efficient Faster General Execution Times Ease of Writing Assembly Available Optimizing Compiler in CCS for TI Microcontrollers

3.4.5.4 Code Language As our device is sponsored by Texas Instruments, we will be writing code to run on a TI microcontroller. This limits our available coding languages to what compilers are available for each of the available chipsets to pick from. TI provides free development environment software in the form of their Code Composer Studio. This development environment provides simulation and debugging support as well as plenty of C compliers for the architectures TI implements in their microcontrollers. Given this development environment, we will be able to write in either C or the compatible ARM or Thumb-2 assembly languages for any microcontroller available to us. Considerations to explore between writing in assembly and writing in C include ease of writing, energy efficiency, optimization capabilities, instruction count, availability of software libraries and time spent developing. 3.4.5.4.1 C Programming Language Writing software in C will all provide the major benefit of more clearly understood code. Writing C code will also allow us to create more complex and useful data structures like the Complex number structure addressed in this document. Additionally, optimizing compilers are available through Code Composer Studio for the C language. This will ensure that our finalized code is optimally small and wastes as little instructions as possible once loaded onto the microcontroller unit. The C language also makes more available the creation of data structures that quicken the process of designing and implementing. Memory usage, such as defining arrays, tends to be much easier in C than lower level languages though not as much as higher level languages with built in garbage collectors. Because of this ability to define data structures, there is a larger chance a library of software exists to aid in the development of C source code. This can ease the process of interfacing with devices like LCD screens and storage units like SD card readers.

There are plenty of tradeoffs that come with the benefits of writing in a high level language like C. The optimized code size of a C translated file will be larger than that of an assembly file due to the number of jumps associated with function calls, so this is less advantageous. Easily written and followed C source code will make use of many potentially unnecessary call stacking as the execution hops from function to function. This will use a bit more energy and time during execution as the code will contain unnecessary jumps and returns to be run. Memory usage will also increase as more of the stack will be used in calling functions. 3.4.5.4.2 Available Assembly Language Writing our software in an assembly language will provide many benefits to the general efficiency of our design. Assembly language programs are provided

33 instructions based on their instruction set architecture, ensuring all non- macroinstruction calls are directly supported by the hardware they are to run on. Every line written will tend to run optimally on whatever microcontroller implements the instruction set adhered to in the software. This means higher energy efficiency as there are less wasted cycles or microinstructions in the pipeline. Additionally, Code Composer Studio provides an assembly optimizer to ensure that once your functional code is written, it will run with as little wasted instructions as possible. This means that the instruction count, and therefore memory usage for storing source code, will be minimized.

The downside of writing software in assembly is obviously the difficulty of following the program flow of a larger source file. Firstly, it is much less likely that a relevant assembly library will be available to you when dealing with tasks like interfacing with external devices. Assembly code is also generally much less clear to the writer than a higher level language like C unless the implemented instruction set is relatively complex. More complex instruction sets lend themselves to energy and time inefficiency due to differing instruction sizes sent through a pipeline. If the benefits of assembly are to be made use of, less clear source code will be the main downfall of the approach. Additionally, it will be much harder to implement data structures and make use of memory when developing assembly. With more inconvenient access to resources and data structure management, developing and following a process flow will take more time. Programming Languages: C vs. Assembly

Table 7 details the considerations made when choosing whether to write our microcontrollers source code in C or an available Assembly language.

Table 7: C vs. Assembly Feature C Assembly Easier to Write More Energy Efficient Smaller Optimized Instruction Count Available Optimizer Higher Potential for Library Support Ability to Define Data Structures Easier to Manage Memory Smaller Memory Usage Faster Development Time

34 3.4.6 Power Supply Unit Powering HAQS will be accomplished by tapping one of the voltage lines from the three-phase power outlet. The Power Supply Unit (PSU) must efficiently and accurately step the voltage down from 120 VRMS to the voltages needed by each component. The steps to accomplishing the PSU design are as follows: stepping the output down, rectifying the waveform, performing a rough AC to DC conversion, and finally regulating each of the voltage lines. Furthermore, each voltage line must supply a sufficient amount of current to each component to ensure operability.

The following sections will discuss the research that went into the options considered for each step with the design specifications detailed in Table 8.

Table 8: PSU Design Parameters for Research Parameter Value Input Voltage 170 VAC (120 VRMS) Output Voltage 1 5.0 VDC Output Voltage 2 3.0 VDC Output Voltage 3 1.8 VDC

3.4.6.1 Voltage Step Down 3.4.6.1.1 Voltage Divider The voltage divider is a simple circuit consisting of one voltage source and two resistors in series. To achieve an output of 12 VRMS, the voltage divider would consist of a voltage source of 170 VAC, fed into a 1.35 kΩ resistor and a 150 Ω load resistor in series. This provides a load voltage of 17 VAC and a load current of 100 mA, which is sufficient for the system considerations above.

In theory, this design would be sufficient for the purposes of powering HAQS. In practice, however, the flaw with this design is power inefficiency. The voltage source in this circuit provides 17 W of power. The 1.35 kΩ resistor disperses 13.5 W of the total power, meaning this design wastes 80% of the power provided by the source in the process of stepping down the voltage. Although the design of the PSU will ultimately require dissipating a large amount of the total power in reducing the 170 VAC input to a range of 3-5 VDC, other designs would dissipate that power over a larger amount of components and steps.

The secondary issue with dissipating such a large amount of power is how that power is dissipated—in the form of heat. The components would have to be able to safely withstand the voltage, current, and power loads, as well as the heat that would be generated through power dissipation.

While the voltage divider is a feasible option for stepping down smaller voltages, the high-voltage provided by the three-phase power outlet cannot be stepped down in such a simple manner without wasting a significant amount of power and taking precautions to handle the generated heat. 3.4.6.1.2 Voltage Step Down without a Transformer The circuit below in Figure 10 depicts a AC step down to DC solution that omits the use of a transformer [25].

Figure 10: AC Step Down and Rectification Circuit without Transformer

The parallel resistor and capacitor connected to the AC voltage source act to reduce the voltage to a manageable level before passing it on to the rectification and regulation stages. The capacitor serves to drop the voltage, but the resistor is set in parallel to allow the capacitor to discharge when the switch is open. The capacitance positively related to and determines the current flowing into the bridge rectifier. The remainder of the circuit handle the rectification and regulation stages, which are outside of the scope of this section [25].

The advantage of this circuit is the removal of the traditional transformer and the undesirable qualities that transformers sometimes bring, such as large size, noise, heat, vibration, and the production of a magnetic field. The omission of the transformer also reduces the cost of the AC step down phase [25].

Though this is theoretically an option for the AC step down. The use of a transformer is safer and more conventional. The capacitor in this circuit would be subject to a high level of AC voltage. Calculation errors, voltage surges, design flaws all contribute to risk associated with this design [25].

36 3.4.6.1.3 Voltage Step Down with a Transformer Traditional transformers utilize the concepts of mutual inductance and deliberate winding ratios in order to increase or decrease the AC voltage input. For the purposes of HAQS, the transformer will need to be a step down transformer. Each inductor in a transformer has a number of turns along the coil. The ratio of turns between the two inductors dictates the input and output voltages. For a step down transformer, the primary winding has more turns than the secondary winding.

Though three-phase transformers are available, HAQS will only employ the use of a single phase transformer, as it is only tapping one phase of the three-phase output. In addition, there exist several other specific types of transformers. However, a simple power transformer with a 10:1 coil ration will suffice and meet the specified requirements at the beginning of this section. 3.4.6.1.4 Voltage Step Down Conclusion Though the three designs considered are ultimately viable solutions for stepping AC voltage down, the use of a transformer is the best option for HAQS. The issues associated with the Voltage Divider and Transformer-less circuit are too many for them to be considered for this project. The advantages and disadvantages of each method of AC Voltage Step down are detailed below in Table 9.

Table 9: AC Step Down Methods Comparison Voltage Divider Transformer-less Transformer Advantages +Ease of use +Small circuit +Conventional, +Simplify design +Low noise therefore there efforts +Less vibration, are many +Use of linear heat, magnetic resources components field documenting their +Low cost use +Safety Disadvantages -Power -High charge on -Size, cost Inefficient capacitor can be -Heat, noise -Feasible current dangerous would be too -More susceptible small to being damaged by a power surge

3.4.6.2 Rectification and DC Conversion In order to convert the AC input signal to a DC voltage, the waveform will be rectified via full wave rectification. Because typical PSUs employs the use of a secondary inductor with only one coil (as opposed to some models that have two

37 output windings), the bridge rectifier scheme will be utilized. Typically, these applications require the use of power diodes to handle the voltage delivered by power outlets. However, since the transformer discussed in the previous section is reducing the voltage to a level that standard diodes can handle, this is not a design concern for HAQS.

Though the use of a transformer with two output windings would only require two diodes and, thus, simplify the design and layout of the final circuit board, the implementation of this type of transformer would complicate other elements of the final design. Another design concern is the voltage drop across each diode. In a transformer with two output windings, the voltage drop is VD per wave (half of a period), where VD is the voltage across the forward biased diode. While the voltage drop across a full wave bridge rectifier is 2*VD per wave. The design of the PSU will simply have to account for this to ensure that dropout voltage required for regulation is maintained after rectification and the DC conversion.

The rectified AC signal will be converted to a DC signal by sending the output through a series of parallel capacitors connected to ground and finally a load resistor. The use of redundant capacitors helps to smooth the DC output and reduce noise. The value of the load resistance is chosen based on the desired output current. 3.4.6.3 Power Factor Correction The challenge with the method of rectification described above is the worsening of the power factor. Typically, designers aim for a power factor of one, but the circuit above, which indicates that the voltage and current waveforms are in phase. Figure 11, below, shows what happens to the voltage and current signals when using the above configuration [26].

Figure 11: Input & Output Voltage & Current With & Without a PFC Circuit Reprinted with permission from Microchip

Notice how the voltage is clearly a rectified sinusoid and how the current waveform’s shape is drastically altered from what is ideal. This happens because of how the current flows during the charging and discharging cycles of the capacitor. The current will spike along with the peaks of the voltage waveform, but this is indicative of a wasteful system. That is, the power is not being utilized to its fullest extent. The circuit above has a power factor of roughly 40-50% [26].

To correct this issue, designers employ the use of a power factor correction circuit. The goal is to make the current waveform look as much like the voltage waveform as possible (in shape, not necessarily in value). The current’s conformity to the shape of the voltage signal dictates the power factor, and, therefore, the real power supplied to the system. The real power is carried by the primary harmonic; thus it is the presence of the non-primary harmonics that reduce the power factor [26].

The power factor correction (PFC) circuit aims to eliminate or, at least, reduce the higher harmonic content. To accomplish this, a PFC circuit must keep its output voltage higher than the input voltage at any given time. Hence, these are referred to as boosting PFC circuits. Between the input and output, the PFC circuit utilizes pulse wave modulation to adjust the current to shape more suited to the voltage’s. When the modulated current signal is averaged and filtered and the shape is tailored, the power factor approaches 1.0, the non-primary harmonics are reduced, the power supplied to the system is cleaner, and the system becomes more efficient [26]. 3.4.6.4 DC Step Down and Regulation After the AC input has been rectified and smoothed out to an approximate DC output, the voltage will need to be stepped down even further in order to interface with and power the individual components, including the ADC, Microprocessor, and LCD. After stepping the voltage down, it will need to be regulated.

This operation can be completed simultaneously by the same device. Modern voltage regulators can handle input voltages at levels much higher than the output voltage. For example, consider an incoming approximated DC voltage of 13 V. A typical voltage regulator will be able to accept the 13 V input and still output a regulated 3.3 V or 5 V, depending on the component. The only requirement for the input voltage is that it is lower than the maximum allowable input and higher than the dropout voltage.

In order to achieve this, there are two options for voltage regulation: linear and switching voltage regulators.

39 3.4.6.4.1 Linear Regulator Linear regulators can only act in a step down operational mode, which is acceptable for the purposes of HAQS, as the input to the regulators will be higher than the required end result and will need to be reduced before interfacing with the individual components [27].

Linear regulators tend to have the following advantages: • Low complexity • Small form factor, with many integrated options • Low cost • No ripple • Low Noise and high noise rejection

A linear voltage regulator is constructed out several BJTs, a difference amplifier that measures the error voltage, and several resistors. This makes for a relatively simple design that is small, inexpensive and easy to implement [27].

Conversely, linear voltage regulators suffer from the following weaknesses: • Only operable in a step-down configuration • Low efficiency • High heat diffusion

The efficiency of a linear voltage regulator is by no means fixed or constant. It can be improved by decreasing the differential between the input and output voltages. However, this would require additional circuitry and design efforts, thus somewhat defeating the simplicity advantage [27].

Under the blanket term, linear regulators, there are several subtypes to consider, and the differences typically revolve around the BJT configuration employed. 3.4.6.4.1.1 Standard Linear Voltage Regulator Standard Linear Voltage Regulators (SLVRs) make use of the Darlington BJT configuration in order to maintain a steady output voltage. When considering a SVLR, it is important to note that these types of regulators have a minimum voltage requirement of 2.5 V to 3 V across the passing transistor. In addition, the SLVR has the highest dropout voltage of the three types of linear voltage regulators to be discussed in this section, which is typically 1.5 V to 2.2 V. Figure 12 illustrates the SLVR [28].

Figure 12: Standard Linear Voltage Regulator

SVLR are particularly advantageous when the DC source is derived from a rectified AC source and when a higher load current is required. SLVRs suffer, though, in the realm of output precision, which is higher than the other types of linear regulators at roughly 5% of the nominal output voltage [28]. 3.4.6.4.1.2 Low-Dropout Linear Regulator Low-Dropout (LDO) linear regulators, shown below in Figure 13, use a simpler BJT configuration than the SLVR, with only one passing BJT. The main advantage of an LDO is the low drop-out voltage, as the name would suggest. The drop-out voltage of an LDO is related to the load current. If the load current is small, the drop-out voltage may be as low as 50 mV. Even still, if the load-current is maximized, the drop-out voltage will still hover between 0.6 V and 0.8 V [28].

Figure 13: Low-Dropout Linear Voltage Regulator

41 Because of this, the LDO regulator is often utilized in battery-powered applications. A low-drop out voltage means that the battery’s resources are more efficiently used by the system being powered, which is not a concern when the device is constantly powered by an outlet. This also reduces cost in the form of requiring fewer battery cells. The efficiency of n LDO is at its best with the difference between the input and output is small (such as 1 V to 2 V) [28]. 3.4.6.4.1.3 Quasi Low-Dropout Regulator Quasi Low-Dropout Linear Regulators (QLDOs) lie between LDOs and SLVRs in several aspects. First, the BJT configuration is more complex than the LDO, but less complex than the SLVR. Second, the dropout voltage for the QLDO is higher than that of the LDO, but lower than the dropout voltage of the SLVR. QLDOs do not offer any outstanding advantages, nor do they have any crippling disadvantages. The use of the QLDO over the other available options would simply depend on the application. Figure 14 illustrates the QLDO circuit [28].

Figure 14: Quasi Low-Dropout Circuit

3.4.6.4.2 Switching Regulator Switching regulators, shown in Figure 15, attempt to fix the issues associated with linear voltage regulators. Unlike a linear regulator, a switching regulator can act to boost (step up) or buck (step down), as well as invert, an input voltage. However, the most common utilization of switching regulators is the buck converter [27]. An integrated switching regulator solution is shown below in a simplified schematic:

Figure 15: Integrated Solution for Switching Voltage Regulator Reprinted with permission from Texas Instruments

In short, switching voltage regulators have the following advantages: • Functional flexibility • High efficiency • Low heat dissipation

The high levels of efficiency associated with switching regulators come from the fact that switching regulators turn off when inactive and back on when needed again, likening the switching regulator to an ideal switch. This especially important in high current applications [27].

Switching regulators are constructed out of an electric switching (usually a MOSFET), an inductor, several capacitors and resistors, and diodes for both voltage referencing and protection. These designs are more complex than the linear alternative [27]. Other disadvantages include: • Large size • High cost • Medium to high noise, due to the ripple at the switching rate

For HAQS, the elimination, reduction, and mitigation of noise is of utmost importance. Therefore, the noise generated by a switching regulator is particularly disadvantageous. Size is also important to consider. HAQS is to be a handheld, easily transported device. The transformer needed to reduce the mains output is large but necessary. The addition of a larger voltage regulator further detracts from the goal of portability [27]. 3.4.6.4.3 DC Step Down and Regulation Conclusion A summary of the advantages and disadvantages of switching and linear voltage regulators is included below in Table 10.

Table 10: Linear and Switching Voltage Regulator Comparison Linear Regulator Switching Regulator Advantages +Low cost +Flexibility in usage +Ease of use +Low heat generation +Low/no noise +Efficient Disadvantages -Heat generation -More expensive -Inefficiencies -More complex circuity

The HAQS PSU will use a transformer to reduce the main voltage to approximately 14 VRMS. The following rectification stage will reduce the voltage even further, to approximately 12 VDC. Several rails with a final outputs of 3.0 V and 1.8 V are desired from the PSU are required to power the system. Reducing the voltage from 12.0 VDC to 3.0 VDC would be a cumbersome task with a linear regulator and has the potential to generate a concerning amount of heat that the system would have to properly handle and dissipate.

The issue of noise can be assuaged with the use of filtering capacitors at the input and output of the switching regulator. This will allow us to enjoy the benefits of the flexibility and efficiency provided by the switching regulator, while also mitigating the harmful effects of noise.

Concerning simplicity, to effectively step a 12 VDC voltage down to 3.0 VDC would require the use of two or more linear regulators in order to keep heat dissipation low; this complicated the circuitry and lessens the validity of using a linear voltage regulator in order to take advantage of their simplicity.

Using a switching regulator increases flexibility in other ways as well. A switching regulator allows a different approach with design efforts. For example, instead of reducing an AC voltage to 14 VRMS, then 12 VDC, then 9 VDC, then 3 VDC (which would be required with a linear voltage regulator), we can perform fewer operations to condition the signal. Some switching regulars can handle input voltages in the range of 40 VDC to 60 VDC and still output 3.0 VDC. The efficiency will drop with such a disparity between the input and output voltages, but the reduction in design efforts and cost associated with a larger design with more components offsets that loss.

Using a switching regulator offers flexibility with design, reduction of component count, efficiency, and accuracy. Therefore, HAQS will incorporate a switching voltage regulator in the final design. 3.4.7 Liquid Crystal Display A Liquid Crystal Display (LCD) was needed in this project due to the desire for feedback to the user in displaying our projects findings on Total Harmonic

44 Distortion. These next few sections will discuss the different types of LCDs and the consideration we put into choosing the LCD that we did. We will also explore any problems we encountered when picking our LCD, such as the probability of Electromagnetic Interference (EMI), and also the types of communication lines that LCDs use. 3.4.7.1 Capacitive Touch The capacitive touch LCD was where we settled for our final screen design. These screens use very small changes in capacitance to detect finger location, and our biggest concern when we considered the capacitive touch LCD was the potential for EMI. With our limited knowledge on the electric fields that are around power supply stations we made the assumption there would be EMI that we would have to deal with. Just about every cell phone out there today uses a capacitive touch LCD and upon researching, we found out that something as simple as the phone charger contributes to EMI in the phone’s screen.

The next hurdle was communication between the MCU and the LCD. The capacitive touch LCD and controller that came with it, makes use of two I2C pins while the remaining pins are just general purpose input output (GPIO). This works nicely for our MCU so we don’t have to fight for communication pins with the other project components. We acquired an MCU with added integration specifically for capacitive touch LCDs, so that was another contributing factor for going with type of screen that we did. The capacitive touch LCD that our group decided to go with is the, 5 inch Capacitive Multi Touch Screen Panel with Controller GSL1680.

The LCD with controller that we have chosen is unique one of the areas that it allows for the measurement of 192 nodes in just under 1 millisecond. The GSL1680 controller is even equipped with EMI signal processing technology that will protect the system from EMI, from LCD, power supplies, radio frequencies, and other outside environmental sources. Although our group’s project will not require this function, the LCD with controller that we have selected is capable of incorporating up to ten finger contact points simultaneously. Keeping our LCD in line with the majority of our other systems, it requires a power supply maximum voltage of 3.3 volts, giving our group the ability to create a simplified uniform power supply system. 3.4.7.2 Electromagnetic Interference Electromagnetic interference can affect any device, caused from the charger it’s plugged into, to outside high electric fields in air. As mentioned previously that capacitive touch LCDs are affected by EMI, our main concern was preventing it if we decided to go with this type of LCD. One of the methods that are currently being used in some chargers are Y-capacitors that are neutral to ground in order to suppress some of the EMI that is conducted [29].

45 3.4.7.3 Resistive Touch Here we start the first half of the touch LCDs, Resistive Touch. We jumped back and forth a few times to this style of LCD for a few reasons. The first being electromagnetic interference (EMI), due to the nature of resistive touch screens using position location by physical pressure to “complete the circuit”, we considered this option [30]. Figure 16 shows the basic construction of a resistive touchscreen.

Figure 16: Resistive Touchscreen

Since our project is focusing more on three-phase power supplies, which are found at power stations and not in homes, this type of LCD wouldn’t be affected by the nearby electric fields. Any user interacting with the device would also be able to wear gloves or use a stylus whereas the capacitive touch LCD falters in that regards. The second factor we considered was price, in terms of large scale or small scale production, at the same screen size, the resistive touch LCD was cheaper than the capacitive touch LCD. The third factor in our LCD consideration was pin communication, but upon researching the two types we found that both use either UART or I2C, so ultimately this did not affect our choice too much. Another obstacle we had to overcome for the two types of touch screens was the analog to digital conversion (ADC) that both kinds would need.

Due to the nature of our project we would need a lot of ADCs just for measuring the differentials of the three-phases. So our problem was either finding a Microcontroller (MCU) that had enough ADCs built in to it or by splitting up the ADCs and grabbing a separate one for the touch LCD. The reason we would have needed separate ADCs for this particular LCD is reasoned behind the way resistive touch senses resistance. These LCDs are typically made of two major layers, one being a plastic film and the other a glass. When the user presses down on the film it completes the circuit with the glass, and because the two layers are covered in a mesh of thin metal wires that run at right angles, we use this for positioning.

At the point of contact, voltage is sensed throughout the circuit and based on the level of resistance a position of the user’s finger can be found. The ADCs come into play because the analog signal of voltage and resistance sensing needs to be converted to digital signals so the MCU can determine coordinates and display accordingly. 3.4.7.4 Non-Touch LCD There are two main categories of LCDs, the first being non-touch screens, and the second being touch screens. The latter will be broken down more later on. Our first iteration of researching possible LCD designs for our project yielded a version with a non-touch LCD and some buttons for user interface. Upon learning of great prices that can be found for capacitive and resistive touch LCDs, and the slight challenge they could bring to designing our project our group decided to forgo the use of a non-touch LCD.

However, there is nothing wrong with a normal LCD, as they tend have lower power consumption and over thinner size compared to the touch screens, it was just personal preference for our group to choose touch capabilities. Other key features are as follows: • Long life and high reliability • High contrast ratio • Wide viewing angle • Fast response • Inexpensive • Simple I/O interface • Low power consumption

3.4.7.5 LCD Conclusions and Comparisons The LCD with controller that we have chosen is unique one of the areas that it allows for the measurement of 192 nodes in just under 1 millisecond. The GSL1680 controller is even equipped with EMI signal processing technology that will protect the system from EMI, from LCD, power supplies, radio frequencies, and other outside environmental sources. Although our group’s project will not require this function, the LCD with controller that we have selected is capable of incorporating up to ten finger contact points simultaneously. Keeping our LCD in line with the majority of our other systems, it requires a power supply maximum voltage of 3.3 volts, giving our group the ability to create a simplified uniform power supply system. Table 11 summarizes the features each type of LCD offers.

47 Table 11: Touchscreen Feature Comparisons LCD Segmented Resistive Capacitive

Low Power • • • Built-In UI • • Multi Touch • Not Affected by EMI • • Useable with Gloves • • RGB Display • •

Table 12 and Table 13 offer further insight into the offerings of the different types of LCDs.

Table 12: LCD Communication Comparisons LCD I2C 4- 8-bit 9-bit 16-bit 24-bit V (Interface) Serial Wire Parallel Parallel Parallel Parallel G A ER- • • • • TFTM050-2 ER- • • • • TFTM050-3 ER- • • • • TFTM050-4 ER- • • • • TFTM050-5 ER- • TFTV050-1 ER- • TFTV050-2 ER- • TFTV050-3 ER- • TFTV050-4

48 Table 13: LCD Resolution Comparison LCD (Resolution) 800 x 480 Dots 480 x 270 Dots ER-TFTM050-2 • ER-TFTM050-3 • ER-TFTM050-4 • ER-TFTM050-5 • ER-TFTV050-1 • ER-TFTV050-2 • ER-TFTV050-3 • ER-TFTV050-4 •

3.4.7.6 Communication Schemes 3.4.7.6.1 Serial Peripheral Interface Communication Serial Peripheral Interface (SPI), typically found in secure digital cards and liquid crystal displays, is a type of communication consisting of four wires between two devices, master out slave in (MOSI), master in slave out (MISO), the serial clock (SCLK), and a chip select (CS) or sometimes called slave select (SS). The MOSI line allows the device that is determined “master” to transmit from itself to whichever slave it is trying to communicate to.

The MISO line allows the device labeled “slave” to transmit from itself to the master device. Keeping the MISO and MOSI lines separate allows for less confusion between devices. The SCLK line keeps all devices synchronized to further avoid any communication errors in which devices is “talking” or “listening.” The CS or SS is used when there are multiple devices for the master to communicate to, allowing the master to select which device it wants to communicate to [31]. The system described above is shown in Figure 17.

Figure 17: SPI Communication Interface

49 3.4.7.6.2 Inter-Integrated Circuit Communication The inter-integrated circuit (I2C) is the follow up to SPI with increased performance and efficiency. The main problem with SPI is the fact that for another slave to be incorporated, another master has to be added as well, you can’t have one master for multiple slaves. The I2C, shown in Figure 18, is the solution because it allows for one master and multiple slaves by adding separate clocks for each slave. The I2C communication lines in our capacitive touch LCD are unique in that they will only provide data packets when internal changes in capacitance is measured [32].

Figure 18: I2C Communication Interface

3.4.7.6.3 Universal Asynchronous Receiver / Transmitter Communication Universal Asynchronous Receiver/Transmitter (UART) is an individual integrated circuit used in device communication. Shown in Figure 19, UART can operate in serial or parallel. Serial uses two lines, one for transmitting and the other for receiving. On the parallel side the UART has the option for making it synchronous by using the clock in Control I/O line. That line also controls the read-write ability, while the Data Bus line controls the data transfer. [33]

Figure 19: UART Communication Interface

3.4.8 User Interface Our first iteration of research bounced around the use of physical buttons as opposed to touch user interface. Every type of UI for this project will be situational, and assessing each option to find a compromise is the overall UI goal. 3.4.8.1 Physical Buttons Everyone can appreciate a solid button system interface and thus the reason for a go-to when we first drew up our possible project design, shown in Figure 20. A compromise between the physical UI and Touch UI that we almost decided upon was a capacitive touch LCD that had haptic feedback.

Figure 20: Original Concept Design with Physical UI

3.4.8.2 Built-in Touch Interface Upon finding an MCU with increased integration specifically for capacitive touch LCDs, our group focused more on making sure that the capacitive touch LCD would be feasible for our group to incorporate as well as an enjoyable and streamlined experience for the user. Even though the possibilities of EMI arose, and our group considered using resistive touch, we determined that the necessary steps to lessen EMI were already taken in the capacitive touch LCD that we wanted to use. One advantage that our LCD has is adjacent touch compensation, which helps our LCD with inter finger interference. Inter finger interference occurs when an LCD detects multiple fingers that are too close to each other and can’t determine if they are one finger or multiples. 3.4.9 Voltage and Current Sensing 3.4.9.1 Voltage Step Down 3.4.9.1.1 Single Phase Transformer When beginning research on methods to step down high voltage from the three- phase power source there were two obvious methods, either using a transformer or a voltage divider. Knowing that the voltage divider would definitely not be an efficient method, research into the challenges that arise due to non-ideal transformer characteristics was paramount. When researching transformers, we found that the datasheets for most transformers did not contain the right information to determine whether the transformer could be used for this portion of the project. Most datasheets provided information on the primary voltages, the specification for the frequency of the input voltage, the output voltage at particular current load, the maximum power the transformer can handle, sometimes the voltage regulation, and the dimensions of the transformer.

The information commonly found is sufficient enough for power supply use but not for stepping down the voltage from a power source to accurately measure the harmonics present in the system. For the purposes of measuring harmonics it is very important to ascertain the frequency response of the transformer. This can be accomplished by either the manufacturer giving a frequency response specification or giving measured magnetizing inductance, leakage inductance, various resistance values, and any other inductances and resistances of a transformer in the datasheet so that the frequency response can be determined using a transformer model. An example of a model that can be used for a transformer is as shown in Figure 21. If we do not know the inductances and resistances present in the practical model of a transformer, we would have to

52 purchase multiple transformers and test them to determine the frequency response of the transformers that may be potentially used for the voltage sensor.

Figure 21: Example of Transformer Model Reprinted with Permission from Cblambert Under the Creative Commons License

When researching the non-ideal characteristics of a transformer, it appeared to be a method of voltage amplitude attenuation that would create many problems and cause inaccurate readings. It was found that there were many losses in a transformer due to the magnetic hysteresis, due to eddy currents, and due to the existent resistance in the copper wiring used to make the transformer [34]. Other than the multiple areas energy loss can occur it was discovered that the transformer generates odd order harmonics [34]. The generation of harmonics by the transformer is a big problem for this portion of the project because the harmonics that are within a power source are what is being measured, thus relatively no harmonic content can be added to the voltage waveform between the voltage source and the ADC.

3.4.9.1.2 Three Phase Transformer Before discovering all of the complications that a transformer would introduce to harmonic measurements, the idea to use a three-phase transformer was brought up so that a single transformer could be used to step down the voltages from a three-phase power source rather than three single transformers. While researching the feasibility of using a three-phase transformer, the datasheets that were found for three-phase transformers also lacked the pertinent information needed for this part of the project as they did for the single phase transformers. In addition to datasheets lacking pertinent information, none of the found three-phase transformers were small enough to use for this project as they were large industrial size transformers as shown Figure 22.

Figure 22: Three-Phase Transformer Reprinted with Permission from Dakota Electric Association

According to [35], the minimum length and width of a pad that these three-phase transformers must sit upon is 68’’ by 82’’ and the pads must also be a minimum of 6 inches thick. The specific model of the transformer shown below could not be determined, thus we do not have a precise height specification. Without a height specification, the dimensions of a length and width that is approximately 68’’ by 82’’ is already considerably large for this project. 3.4.9.1.3 Voltage Divider Another method that was researched for stepping down the voltage was the simple voltage divider. Upon review of the several three-phase power meter designs that are available from Texas Instruments, it was found that many of the circuits used for voltage sensing involved the voltage divider. After learning of the disadvantages of using a transformer, it became clear that using a voltage divider for the voltage sensor was a more suitable choice for measuring harmonics. Compared to using a transformer, the simple voltage divider circuit does not introduce harmonics to the voltage that is being measured between the source and ADC input. Thus the voltage divider produces a much more faithful representation of the voltage waveform from the power source. Using a voltage divider is also relatively cheaper and surface mount devices can be used to realize the voltage sensing circuit. Due to the ability to use surface mount devices, the final version of the project will be more lightweight than if we used multiple transformers to step down the voltage.

Even though introducing harmonics is not a concern for the voltage divider, there are other challenges to face when using a voltage divider to step down the voltage from the three-phase power source. One major concern is the amount of power that will be dissipated in the divider. When the voltage is stepped down from 120 V RMS (170 V peak) to a safe level for the ADC input pins, a large amount of power

54 will need to be dissipated in the resistors that be used to realize the divider. To address this power dissipation concern, a high resistance of around one mega ohm or higher will be used for the portion of the circuit where power dissipation is of high concern. To make the problem even less of an issue the large resistance can be distributed to multiple series resistors to distribute the dissipated power to be within levels that manufactured resistors can withstand.

Another concern when using the voltage divider is the efficiency of the circuit. This is definitely not an efficient design choice as most of the drawn power is lost in the divider circuit. All that can be really done is to lower the power draw from the power source using the same resistance that will dissipate the most power in the voltage divider. To reduce the concern of power lost in the voltage divider the circuit can be designed to dissipate very little power such that it is relatively insignificant to the power drawn and used by the system’s load when the voltage sensor is not present. 3.4.9.2 Current Sensing 3.4.9.2.1 Shunt Resistor Of the three researched current sensing methods, this is conceptually the easiest sensor as only Ohm’s law is used to determine the current of a particular system. Two configurations of shunt current sensing are typically used, high-side and low- side current sensing. The advantages of low-side sensing is that the common- mode voltage is near ground allowing the use of single-supply, rail-to-rail input/output op amps [36]. When using low-side current sensing a disturbance to the system’s load ground potential is created and the current sensor is not able to detect load shorts [36]. Using high-side sensing eliminates the ground potential disturbance and load shorts can now be detected [36]. The challenge with high- side current sensing is resistor matching to obtain a high common mode rejection ratio using standard op amps [37].

Despite whether low-side or high-side sensing is used the shunt resistor needs to be placed into the system if there is not already a shunt resistor for current sensing installed, creating a potential safety concern for people who are inexperienced with high voltage/current electrical safety.

In addition to safety concerns, there are other complications that arise due to the nature of shunt current sensing. Since a resistor is being placed into a high voltage and/or current system the insertion losses (generated heat and wasted power) and the lack of electrical isolation are the shunt sensors shortcomings [38]. Despite these shortcomings, sensing current through a shunt resistor provides data that may be accurate enough to extract useful information and is the cheapest current sensing method. Given a certain budget, this may be the only option as the other two sensors can become quite expensive for accurate measurements.

55 3.4.9.2.2 Hall-Effect Sensor The Hall-Effect sensor can be a very expensive option but can also be the most accurate option. Unlike the shunt resistor, a Hall-Effect sensor does not need to be in any electrical contact between the sensor and the system whose current is being measured, thus there is no insertion loss for this sensor. This isolation between the input and output makes the Hall-Effect sensors a safer option than the shunt resistor. The downsides to using a Hall-Effect sensor are its frequency range, DC offset, use of magnetic material, and external power needed to operate the sensor [38]. According to [38], the frequency range of the Hall-Effect sensor is more limited than the shunt sensor but is generally greater than 20 kHz and just as the shunt sensor need external power to operate, Hall-Effect sensors also need external power to operate.

There are two types of Hall-Effect sensors that are used, open-loop and closed- loop sensors. The open-loop is generally simpler, cheaper, and less accurate than closed-loop sensors. For the open-loop sensor the drawbacks are their susceptibility to saturation and temperature drift [39]. The non-linear characteristics of the sensor are undesirable and can introduce harmonics into the measurements. The closed-loop sensor in contrast is highly linear, has low temperature drift, and is the sensor of choice when high accuracy is essential according to [39].

When researching available Hall-Effect sensors, two physical implementations of the sensor were found and the sensors are readily available at various accuracy levels down to ±0.1%. The two physical implementations that were found was the common solid core sensors and split core sensors, the difference being that the split core sensors have a latch mechanism available so that you don’t have to temporarily create an open in the system to setup the current sensor. When picking a Hall-Effect sensor the core size seemed to be directly related to the price of the sensor, thus an expensive sensor would be needed for a system with thick wiring. 3.4.9.2.3 Current Transformer The current transformer is yet another current sensor that is commonly used. Unlike the two other current sensors the current transformer needs no external power to operate, making this a slightly more efficient current sensor, and it does not exhibit a DC offset at the zero current level [38]. Just like the Hall-Effect sensor, the current transformer is electrically isolated from the system whose current is being measured and there is no insertion loss associated with current transformers [38]. Where this sensor comes up short is the frequency range and cost of the sensor. This particular current sensor cannot measure DC current as a shunt or Hall-Effect sensor could and the useable bandwidth is generally very narrow compared to the shunt sensor and the Hall-Effect sensor.

56 Just like the datasheets for the voltage transformers, the data sheets for current transformer do not always contain the pertinent information needed for this project. A common trend among current transformers with informative datasheets was an output accuracy range given a certain range of the rated primary current. Many current transformers that were found typically have bandwidth specifications of 50 Hz to 400 Hz or the bandwidth is specified as just 50/60 Hz. Just like the shunt sensor, after the current sensing circuit is designed with a burden resistor for the current transformer in mind, Ohm’s Law is used to determine the current at the primary of the current transformer. As seen with Hall-Effect sensors, two common physical implementations exist for current transformers, solid core and split core sensors. An example of a split core current transformer can be seen in Figure 23. We also found that the core size of the transformer seemed to be directly related to its price.

Figure 23: Example of a Split Core Current Transformer Reprinted with Permission from Continental Control Systems, LLC

3.4.9.3 Filtering 3.4.9.3.1 Ferrite Beads Due to the relatively low bandwidth of this project, ferrite beads will be used to simply help suppress or filter EMI noise in the voltage and current sensing circuits. As shown in [40], a ferrite bead can cause unfavorable over/undershoot and cause more problems than if no ferrite bead were used. Thus, special attention must be given to the ferrite bead during the design process to ensure that the ferrite bead can help with the EMI issues the circuit will face and the bead must be selected as to not introduce undesirable over/undershoots.

57 3.4.9.3.2 Alias Filtering For the purposes of this project, the anti-aliasing filter that will be used is simply a low-pass filter. With the already specified harmonic range to allow measurement up to the 51st harmonic there is an implied bandwidth of approximately 3 kHz. With the advancements made in ADCs, typical sampling rates that are typical greater than 4 times this implied bandwidth exist. Thus the anti-aliasing filter will simply ensure that the high frequency harmonics that may exist at the Nyquist frequency and above are filtered out to satisfy the sampling theorem. 3.4.10 SD Card Reader Due to adherence to Secure Digital (SD) card standards, any SD card reader that we can mount on our final printed circuit board should provide the necessary functionality for the device to perform correctly. Due to this, there are few considerations to make when deciding which SD card reader to purchase and mount on the final design. The only factors that should be considered include cost, card type, special packaging and communication.

A reader can support either the standard SD card size or the smaller micro SD card. Adapter units exist for micro SD cards to be inserted into standard SD card slots, so optimally a standard sized SD card reader will be chosen for its ability to read both types given the correct adapters. Additionally, micro SD cards are quite small, meaning that they can be lost easily if used in a device in which the storage is frequently removed. The benefit of micro SD cards is their small size, making larger storage take up less space within a device. Many devices that make use of micro SD cards install the reader behind a casing, demonstrating that frequent removal is not expected. Because of this, a standard SD card reader is preferred.

All SD card readers tend to perform identically, so the only technical difference aside from their accepted card size is the packaging the reader comes mounted on. For the purposes of prototyping and testing components, having an SD card reader mounted on a Texas Instruments BoosterPack board will be beneficial. 3.4.10.1 Communication Available SD card reader boards tend to support either UART communication or SPI communication. Defining the type of communication our planned SD card reader will make use of is imperative if we want to ensure enough communication channels exist on our microcontroller to support its operation. Microcontrollers available from Texas Instruments support communication with UART, SPI as well as I2C standards. However, each UART channel as well as every I2C channel doubles as an SPI channel as well. This means that the SPI communication scheme may be preferred to another scheme because it can be used on potentially any communication channel available on the microcontroller unit.

58 3.4.10.1.1 SPI Serial Peripheral Interface (SPI) communication uses four of the communication pins available on the microcontroller unit to communicate. If we make use of SPI communication with more than one of our external devices, it will begin to consume less communication lines. This is because devices that communicate with the SPI standard can be selected using their slave select (SS) or chip select (CS) line. Texas Instruments microcontrollers that support SPI communication label this line as CS in their documentation. Generally, devices tend to communicate with SD card readers using SPI standards and as such there are several examples and libraries available that provide software support for communicating with SD card readers in this way. The downside to this communication style is that unless more complex methods are used, four communication pins need to be used to communicate with the microcontroller. This may end up posing a problem when taking into account the additional external devices that require communication pins on the microcontroller to provide our expected functionality like the specified LCD screen. 3.4.10.1.2 UART The key benefit of using a Universal Asynchronous Receiver/Transmitter (UART) controller is that it can allow non-serial devices to communicate in serial to our microcontroller and vice-versa. UART communication implies that the sent bits are not synchronously transmitted. This is not necessarily a problem when writing to a file on our SD card but may become an issue if introduced to communication with our sampling circuit. The benefit of asynchronous communication is the omission of a clock signal sent to the receiver. This will reduce the number of pins required to communicate using UART, instead using special bits in the transmitted data used to separate the data into its synchronized unit equivalent groupings. Making use of UART communication when transmitting to the SD card reader may free up crucial communication pins necessary to connect to other external devices. 3.4.10.2 File System If we are to write to a file on the SD card then it needs to be formatted in such a way that blocks of bytes within the storage space can be recognized as separate files. This will require that we implement a file system module with the bytes we stream to the SD card reader. Additionally, the file system we implement has to be recognizable by other devices like PC’s and Mac devices in order for the user to review stored sampling results at their convenience. Due to the overwhelming amount of support and usage of the File Allocation Table (FAT) file system with respect to SD card information storage, a module that implements this would be preferred. There are plenty of software libraries dedicated to implementing these FAT file systems. Along with the generic FAT file system there are variations such as the Petit FAT file system that is specialized for usage with smaller microcontrollers.

59 3.4.10.2.1 FatFS This is the generic FAT file system that many devices use to organize data on storage like SD cards. Windows machines use this format on SD card readers connected to their systems, so files can be easily viewed on a Windows machine. The generic version allows for multiple volumes to be mapped, though this is not necessary as there will only be one SD card within our system at one time. It can also support multiple sector sizes, which is similarly not necessary as we are not writing to or reading from disk mediums. Just because there are several unnecessary features does not completely rule out its usage as a potential file system implemented in our source code. It is known to have good performance even when used in small devices like microcontrollers although it cannot scale as well as modern file systems [41]. This is because each version of the FAT file system has a limited amount of memory that it can actually address due to its simplicity. This should not be an issue as we are planning on using it to store one file which contains around 2KB of information per sample taken. The FAT32 implementation allows for SD cards of sizes up to 4GB to be written to efficiently. This means over 2,000,000 sample results can be stored on a given SD card. 3.4.10.2.2 Petit FatFS The Petit FAT file system is a variant of the generic FAT file system which specializes in support for very small microcontrollers [42]. It can even run on 8-bit devices and has the capacity to write to drives with sectors larger than the microcontroller’s RAM size. It makes use of much less RAM on the microcontroller and, because it implements far fewer features, requires a much smaller code size to implement all of its functionality. The Petit FAT file system requires that the storage written to be of a single volume and a single file. This is not a problem, as it is how we intent to store the devices recorded sample results. The Petit FAT file system can implement the FAT12, FAT16 and FAT32 variants. This means that it also has the capacity to write to an SD cards up to a size of 4GB. 3.4.11 Circuit Protection 3.4.11.1 Solid State Relays For circuit protection, the use of relays to redirect the possible electrical surges was an idea that was explored. At first relays seemed to be enough for circuit protection because they are able to respond quickly and are now advanced enough to communicate with a microcontroller [43]. After further research was done on solid state relays, it seemed that this was not a device that would provide adequate protection. According to [44] and [45], even solid state relays need protection from other overvoltage and overcurrent devices to prevent damage to the elements inside the relay and the load connected to the output of the relay. Seeing as the relay itself would need protection and the load connected to it may

60 also be damaged without other protective devices, the use of relays was quickly dismissed for the voltage and current sensing circuits. 3.4.11.2 Fuses One of most simple circuit protection devices that could be used are fuses. Although they can provide adequate circuit protection, there are significant problems with fuses when determining the feasibility of using them for this project. In terms of response time, fuses can be designed to be ‘slow blow’ to allow large inrush currents and can be alternatively designed to act fast for more sensitive overvoltage and overcurrent systems [46]. Where the fuse falls short is after an event where protection is needed. After the fuse blows, there is no reconnection as with the other protection devices, thus component replacement will be necessary once the fuse protects the circuit from a single surge event. Another problem that may occur with a fuse is that if the current during the surge event is higher than the Rated Breaking Capacity, then the high current surge may not be interrupted providing no protection to the circuit the fuse was supposed to protect [46]. 3.4.11.3 Gas Discharge Tube Another device that can be used for circuit protection is a gas discharge tube. The advantages of this protection device include the ability to carry large amounts of current, they have low off-state capacitance creating very little signal loading, and have the lowest turn on voltage compared to other crowbar devices [46]. Unlike the fuse, the gas discharge tube is able to protect a circuit from more than one surge event. Even though it can protect a circuit from multiple surge events, this particular device still wears out over multiple surge events and will fail after numerous stress events depending on the severity of the surge events [46]. Other downsides to this protection device is that is has a long turn on time, is larger than other available protection devices, is typically more expensive than other devices, and is mostly useful in conjunction with other faster protection devices [46]. The low turn on voltage and little signal loading make this device very attractive for circuit protection, but because it is a large device with a long turn on time, it is not the best choice if it is desired to have a compact device with fewer components. 3.4.11.4 Thyristors The thyristor is another crowbar device similar to the gas discharge tube, but has slightly different pros and cons. The thyristor can also carry a considerable amount of current without damaging the device with low power dissipation and does not wearout like the gas discharge tube, thus this device will not have to be replaced as frequently as a gas discharge tube or a fuse in an environment susceptible to many power surges.

61 According to [46] and [47], the thyristor produces no noise, have fast response, have low on state voltages, but have a turn-off time delay. Because this is a solid- state semiconductor device, the thyristor is more useable for compact PCB designs than gas discharge tubes and can be used on its own due to its fast reaction time, ability to withstand large currents, and long lifetime. Being a crowbar device, the drawback of a thyristor is the time it takes and the specific conditions needed for the device to turn off. The high voltage excursion involved when transitioning from the circuit’s normal operation state to the protective holding point is also a drawback of the thyristor and other crowbar devices. 3.4.11.5 Varistors Unlike the previously mentioned protective devices, a varistor is a clamping device. The varistor is a cheap bidirectional circuit protection device that is very useful for protection against voltage surges. Like the gas discharge tube, the varistor is susceptible to degradation from multiple stresses but is less prone to failure than the gas discharge tube. This gives us a device that can withstand multiple power surges and a circuit protection device that does not have to undergo specific conditions to return to its off-state as a crowbar device would.

Although returning to its standby state is less problematic, the degradation of the varistor changes its breakdown voltage [47]. Thusly the varistor can become problematic if the specified operational voltage becomes higher than the lower breakdown voltage due to degradation. Another potential problem for the varistor is the length of time that it can withstand a stress event. According to [48] varistors are useful for short duration protection of voltage surges in the order of 1 to 1,000 microseconds, but they are not well suited for sustained surges.

The varistor does not only have drawbacks, according to [46] and [49] the upside to the varistor is its response time which is typically less than 20 ns, its ability to dissipate high amounts of energy, and its low stand-by state current draw. Depending on the protection needs, the fast reaction time, ability to withstand considerable energy dissipation, and ability to easily return to its stand-by state make this device a considerable option for this project. 3.4.11.6 High-Speed Switching Diode and Zener Diode One of the simpler protection devices, diodes can be used as clamping devices. Simple high-speed switching diodes, as the name says, have a fast reaction time that is needed from protection devices and according to [50] the most common reverse recovery time is 4 nanoseconds. The concern when using simple diodes for circuit protection is the amount of current conducted at a specific voltage and the amount of power dissipation the diode can handle.

62 The zener diode behaves much like the high-speed switching diode with the added benefit of reverse-bias clamping. According to [51], zener diodes provide very effective clamping and they come closest to an ideal constant voltage clamp. Just like the high-speed switching diodes, when picking a zener diode the power dissipation is an important factor if it will be used as a device for circuit protection as well as the amount of current conducted at a specific forward bias voltage. The main advantages of the zener are its low clamping factor (peak voltage above the nominal clamping voltage), high repetitive pulse power ratings, sub-nanosecond turn-on response time, and they experience very little wearout [47]. Even though the zener seems to be a perfect protection device, it is more likely to break during surges that will exceed the zener’s power dissipation specification compared some of the other circuit protection devices researched. 3.4.11.7 Transient Voltage Suppressive Diode As the name clearly indicates, these protective devices are diodes designed to specifically use for transient voltage suppression. Like the high-speed switching diode, the zener diode, and the varistor, TVS (transient voltage suppressive) diodes are a clamping device. As these devices are specifically designed for protecting circuits from high level transients, TVS diodes typically have power ratings that are much higher than non-TVS diodes and are based on the functionality of zener diodes.

Two significant advantages of this device is that it does not experience wearout unless the power rating is exceeded during a stress event. According to [52] the typical response times for a unidirectional device is less than 1 picosecond and is less than 5 picoseconds for bidirectional devices from 0 volts to the minimum breakdown voltage. Compared to the high-speed switching diodes and zener diodes, the advantage of picking TVS diodes are the even faster response times and the higher designed power ratings, which were of concern when contemplating the use of non-TVS diodes for circuit protection.

Being a clamping device there is no concern of the device returning to its off-state and no concern of high voltage excursion when transitioning from the devices off- state to on-state, thus making this device very useful for situations where quick response is needed for undesired surges and a quick return to normal operation is desired. The TVS diode is not without its imperfections and are similar to many other diode devices, such as introducing capacitance to the circuit it is protecting in its off-state and a small leakage current in its off-state. Compared to the other protective devices researched, the drawbacks for the TVS diode are comparably less significant when taking into account all of the advantages of TVS diodes.

63 4 Design 4.1 Hardware 4.1.1 Voltage Sensor 4.1.1.1 Transformer vs. Voltage Divider Before beginning to design the voltage sensing circuit, a method for stepping down the voltage from the three-phase power source needed to be chosen. The researched tradeoffs for using a transformer or voltage divider are compiled in Table 14.

Table 14: Transformer vs. Voltage Divider Tradeoff Transformer Voltage Divider More Efficient ü Does Not Introduce Harmonics ü Smaller Component(s) ü Cheaper ü Lightweight ü

Examining the tradeoffs shown in Table 14, using a voltage divider is obviously a better choice considering the research into transformers which revealed that transformers generate harmonics. The most important goal for this project is the meter’s ability to measure harmonics, thus using devices that introduce harmonics when they can be avoided would not be a wise design choice. Therefore, the simple voltage divider will be used to step down the high voltage of 120 V RMS from the three-phase power source to a useable level for the ADC that has been picked for this project. 4.1.1.2 Voltage Sensing Circuit The voltage sensing circuit for this project is designed to measure the voltage of the Wye connected three-phase power source that is available to the group for testing. The voltage sensing circuit that will be used for this project is from another meter which was referenced to this group by TI with this project’s proposal. The meter that was referenced is TI’s High Accuracy Three-Phase Electricity Meter with Tamper Detection. The schematic for sensing the voltage of one phase of a Wye connected three-phase system is shown in Figure 24. The schematic shown is comprised of the step down method of choice (the voltage divider), a varistor for circuit protection, two ferrite beads, and a low-pass filter fulfilling the role of an anti- aliasing filter.

Figure 24: Voltage Sensing Circuit Reprinted with permission from Texas Instruments

Before picking components and designing the circuit, the input limit specifications for the ADC that will be used for this project need to be known. The desired bandwidth needs to be identified and the sampling rate needs to be known to design the anti-aliasing filter to satisfy the Nyquist sampling theorem. The operational voltage amplitude needs to be identified and the power that will be drawn from the power source during the final project’s testing need to be known to make the power dissipated by this circuit relatively irrelevant. The ADC that was decided upon for this project is TI’s ADS131E08 due to its availability of a sufficient amount of differential input channels and it is specified to exceed Class 0.1 performance.

The limits that need to be taken into consideration for the ADC is that the input current to any pin except the supply must not exceed 10 milliamps and the full- scale differential input voltage range is ±789:/<=>5. The ADC chosen can take samples at a maximum rate of 64 kSPS, thus a cutoff frequency around 4 to 6 kHz is more than adequate even if we use the ADC at half its maximum sampling rate of 32 kSPS. The project proposal by TI stated that the meter designed is to show up to at least the 51st harmonic. Since we will be testing this project in power systems with a 60 Hz fundamental frequency, the desired -3 dB bandwidth should be at least the 51st harmonic frequency of 3120 Hz. The power system we will be testing with is a 120 V RMS (170 V peak) per phase system. According to [53], some of the less power hungry appliances can draw anywhere from 0.25 to 7 watts of power. The data found from [53] is slightly misleading as the values are for the most efficient units in their class. In the end, all that matters is we will design for power dissipation that is much less than the power used by the system’s load which will consist of every day appliances that the group will requisition for the purposes of the final project’s testing. A comprehensive list of design parameters are given in Table 15.

65 Table 15: Voltage Sensor Design Requirements Parameter Value ADC input current limit 10mA ADC full-scale differential input voltage ±789:/<=>5 ADC max sample rate 64 kSPS Desired -3 dB Bandwidth At least 3120 Hz Voltage Source Amplitude 120 V RMS (~170 V peak) Power Dissipated << System Load Power Usage

The first step taken when designing the voltage sensor was picking values for the voltage divider to satisfy the ADC differential input range given the voltage source amplitude and the power dissipated by the voltage sensing circuit. By examining the voltage sensing circuit, it is easy to see that the DC gain of the circuit, with low- pass filter characteristics at the differential output, is the ratio of the voltage divider. The Vref used for the ADC will be 2.5 V with a gain of 1, giving us a maximum input swing of ±2.5 V and a varistor will later be picked to prevent the differential output from exceeding this value. The divider ratio will provide an output swing of about ±1 V peak to allow the meter to keep taking samples during surge events that won’t exceed the varistor’s breakdown voltage.

Choosing the resistor, or eventually a series of resistors, that will dissipate the most power to be 1 ?Ω when the voltage divider output swing is ±1 V peak, the average power drawn from a single phase is about 0.014326 W and the average power that will be drawn from all three phases is about 0.042978 W. To achieve a ±1 V peak output swing, the output resistor of the divider must be exactly 5.9275 AΩ, but due to resistor tolerances, a readily available 5.9 AΩ resistor will suffice. With the 5.9 AΩ resistor, the output of the voltage divider would ideally now be a swing of ±0.9954 V peak. The other resistors seen in the sensing circuit will be left as 1 AΩ. The chosen resistor values satisfy our requirements to reduce the voltage signal to safe levels for the chosen ADC. The power dissipated by the three voltage phases will be determined to be relatively insignificant to the power load that will be used for the final project’s testing after determining certain requirements for the current sensor.

When choosing the capacitor values, the desired bandwidth and the highest bandwidth allowed to satisfy the Nyquist sampling theorem are the only design concerns. The desired bandwidth is at least 3120 kHz to measure up to the 51st harmonic of the 60 Hz power system. We decided that a sampling rate of at least 32 kSPS will be used for this project. This leaves a large range of frequencies that can be chosen as the -3dB frequency of our anti-aliasing filter. The frequency 12 kHz will be chosen so that the 51st harmonic at 3120 kHz will be attenuated slightly relative to the lower harmonics that are well within the passband region of the low- pass filter.

66 To choose capacitor values the circuit was simulated under the ideal ~170 V peak voltage signal at 60 Hz with no surges, no non-ideal varistor effects, and the ferrite beads approximated to shorts. The circuit was initially simulated with the differential output capacitor initially set to 100 5E and the other two capacitors set to 10 5E and the initial -3 dB frequency was found to be about 187.67 Hz. Using frequency scaling to achieve the desired cutoff frequency of 12 kHz, the new differential output capacitor value is 1.5639 5E and the other two capacitors are 0.15639 5E. The simulated voltage sensor circuit is shown in Figure 25 under ideal operational conditions and the frequency response is as shown in Figure 26. As was done for the voltage divider resistors, the capacitors will be adjusted to lower readily available capacitor values as choosing the closest higher value will undesirably move the cutoff frequency closer to the frequency of the 51st harmonic.

Figure 25: Voltage Sensing Circuit Under Ideal Operational Conditions

Figure 26: Frequency Response After Frequency Scaling

The final requirement to check for the voltage sensing circuit is to determine if the amount of current that the ADC differential input will see is within the ADC’s specified limits. Using the simulated sensing circuit under ideal operational conditions with a 60 Hz 170 V peak (120 V RMS) input, the maximum amplitude of the current from the voltage source is about 170 HI. This means the current seen at the differential output will be well below the ADC’s limit of 10 JI as the current drawn from the voltage source is about 100 times smaller than the ADC’s current limit. When the input amplitude is increased to a theoretical sustained surge value of 300 V peak, the maximum amplitude of the current drawn from the voltage source is about 300 HI, still well below the ADC’s pin current limit.

The final steps for the voltage sensor circuit design is picking the actual components that will be used. Since variable components will not be used, the resistors with lower tolerances are more appealing for this project. Other than the high dissipation resistor with a peak power dissipation of about 29 mW, the next highest average power dissipation is about 85 HW, and even lower for the rest of the components. To use resistors with working voltages lower than the ideal ~170 V peak for the high dissipation resistor, 3 resistors in series can be used to divvy up the ~170 V to more manageable working voltages of less than 60 V and as a positive side effect the power dissipated will also be divvied evenly between the series resistors. The 1 ?Ω resistor was divided into three 332AΩ resistors, thus changing the voltage divider output to about ±0.994 V peak, the average power dissipation to about 14.418 mW, and the frequency response shifted to about 12.002 kHz. Taking the tolerance, power rating, working voltage, temperature coefficient, and price of the resistors into account, the found Yageo RT series of surface mount resistors seem to have the best balance for all of the mentioned considerations.

As when picking resistors, the capacitors picked shall have tight tolerances. When viewing the power dissipation in the simulation with a constant surge keeping the input to 300 V peak, the highest working voltage is 1.2475 V RMS, the highest current is 73.545 nA RMS, and the highest amount of dissipation to worry about in a capacitor is a peak value of about 92 nW. The capacitors are rounded down to the next readily available values, whilst keep the ratio used during the design process, of 1.5 nF and 0.15 nF. The -3 dB frequency has now shifted to ideally 12.748 kHz according to the simulation. Taking the desired tolerance levels, working voltage, temperature coefficient, and price of the capacitors into account, the general purpose Murata Electronics North America ceramic capacitors appear to have the best specifications for this project.

The final two components to pick are the ferrite beads and the varistor. Due to the low frequency range of this project in comparison with the GHz range where the ferrite bead characteristics become vital, the current limit and DC resistance of the

68 bead are the focused specifications for this project. The ferrite beads used will be from Taiyo Yuden’s FB series of ferrite beads for their high ampere ratings and their relatively lower DC resistance values. The varistor chosen will allow the circuit to operate ideally until the output is about 2 V (a value approaching the Vref chosen), can handle high current surges, and can dissipate high amounts of energy. The circuit reaches about 2 V when the voltage source surges to about 2 times the ideal output of about ±170 V peak, thus the varistor chosen will begin to conduct around ±340 V peak. The varistor used will be from EPCOS(TDK)’s B772 series of varistors. The specific component models picked for the voltage sensing circuit will be stated in the bill of materials later on. 4.1.2 Current Sensor 4.1.2.1 Current Sensor Comparison Before beginning to design the current sensing circuit, a method for measuring the current from the three-phase power source needs to be chosen. The researched tradeoffs for the different current sensing methods are compiled in Table 16.

Table 16: Current Sensor Tradeoffs Tradeoff Shunt Hall Effect Current Resistor Sensor Transformer Electrical Isolation ü ü Wasted power ü Cost Low Medium/High Medium/High Disturbs the system ü Needs external power ü ü Accuracy Lowest Highest Middle Can measure DC current ü ü May exhibit DC offset ü ü

Examining the tradeoffs shown in the table above, using either a current transformer or Hall Effect sensor seem to be the more appropriate choices. The most important goal for this project is the meter’s ability to measure harmonics, thus accuracy is not a significant objective for this project. Although accuracy is not a significant objective, the shunt resistor method is not being seriously considered due to its undesirable ability to create disturbances in the system. Due to the Hall Effect sensor needing external power to function, current transformers will be used for this project as accuracy is not a top priority. 4.1.2.2 Current Sensing Circuit The current sensing circuit for this project will be designed to measure the currents of each individual phase as well as the neutral of the Wye connected three-phase power source that is available to the group for testing. The current sensing circuit

69 that will be used for this project is also from TI’s High Accuracy Three-Phase Electricity Meter with Tamper Detection. The schematic for sensing the current of one phase, or the neutral, of the Wye connected three-phase system is shown in Figure 27 below. The schematic shown is comprised of a burden resistor whose value is chosen based on the used current transformer, a system of high-speed switching diodes and a TVS diode for circuit protection, 0 ohm resistors to make parallel node connections on a PCB, and a low-pass filter fulfilling the role of an anti-aliasing filter.

Figure 27: Current Sensing Circuit Reprinted with permission from Texas Instruments

Before beginning the design of the current sensor circuit, a current transformer needs to be picked. In order to pick a current transformer, we need to know the size of the wiring used for the three-phase source and if the power source has a current limit from either an installed breaker or fuse. The three-phase source that is available for testing has a 60 A breaker of fuse, thus a current transformer that can handle up to 60 A is ideal, and the 10 AWG wire used for the three phase- source was measured to have a diameter of about 5mm. From the current transformers found, the two that seemed useable for this project are compiled and compared in Table 17.

Table 17: Current Transformer Specifications Specification Copal Continental control Systems Electronics Inc. LLC C-CT-10 ACT-0750-100 Opt HF Rated Primary Current AC 0.1 - 60 A 100 A Range Core Dimensions 10mm diameter 20.0mm x 20.0 mm Bandwidth/ Applicable 10 Hz – 5 kHz Up to 10 kHz Frequency Turn Ratio 3000:1 N/A Output Accuracy ±1% at 60 A input ±0.75% from 1% to 120% of from a 50/60 Hz rated primary current system Price $37.92 $47.00

Based on the bandwidth alone, the C-CT-10 current transformer from Copal Electronics Inc. is sufficient for this project. This current transformer is also the cheaper of the two, has a given turns ration in its spec sheet, has comparable accuracy to the other transformer, and its core size is large enough to accommodate the wiring of the three-phase power source that is available. The ACT-0750-100 Opt HF current transformer by Continental Control Systems LLC has a slightly higher primary current rating, has a slightly higher bandwidth, can easily accommodate the wiring of the three-phase source, and has a built in burden resistor.

Although the bandwidth is not as wide as the other transformer and due to its cheaper price, its sufficient bandwidth/applicable frequency for this project, and explicitly specified turns ratio, the C-CT-10 transformer will be the current transformer used for this project. With this transformer picked, a current of at least 0.1 A will needed to achieve reliable measurements. This means the power drawn from a single phase will be at least 17 W. Looking back at the voltage sensor, the power drawn from the circuit is an average of about 14.4 mW. We can now confirm that the power drawn from the voltage sensor will be insignificant compared to the power drawn from the system’s load.

With a current transformer picked, the requirements of the current sensor need to be identified to begin the current sensor circuit design. Unlike the voltage sensor, the current sensor is electrically isolated from the three-phase source and the power dissipation relative to the system’s load is not a design concern. Like the voltage sensor, the same ADC limits apply and the same desired bandwidth also applies. Due to the changing current draw depending on the system’s load, we do not have a specific source current value to design to. Without a specific current value to base the sensor around, we will use the limit of the power source and the current transformer, 60 A, as the maximum operational condition and design around this value. The compiled current sensor design requirements are given in Table 18.

Table 18: Current Sensor Design Requirements Parameter Value ADC input current limit 10mA ADC full-scale differential input voltage ±789:/<=>5 ADC max sample rate 64 kSPS Desired -3 dB Bandwidth At least 3120 Hz Maximum Current 60 A

Knowing the maximum current that can occur before the three-phase source will shut off due to the pre-installed fuses, the burden resistor is chosen so that we receive a ±1.2 V peak reading at 60 A. The ±1.2 V peak output was chosen

71 because although the reference voltage that will be used for the ADC is 2.5 V, a safety margin is used to prevent any damage from surges that may occur before the protective devices can react. Since we know that the turn ratio of the current transformer is 3000 and the current at the secondary will be 20 mA, a burden resistor of 60 Ω is needed to receive a ±1.2 V peak reading when the primary current is 60 A. As with the voltage sensor, we will leave the 1 AΩ resistors as they are shown in the figure illustrating the circuit and adjust the circuit’s bandwidth using frequency scaling.

As was done with the voltage sensing circuit, we will simulate the circuit under ideal operational conditions and adjust the capacitors to achieve the desired -3 dB bandwidth using frequency scaling. The circuit was simulated under the ideal conditions that the diodes are all off and exhibit no non-ideal effects, such as leakage current, with the differential output capacitor initially set to 100 5E and the other capacitors initially set to 10 5E.

As with the voltage sensor, the bandwidth of the low-pass filter for the current sensor will be 12 kHz so that the 51st harmonic at 3120 kHz will be attenuated only slightly relative to the lower harmonics that are well within the passband of the filter. The initial simulation showed that the -3 dB frequency was 724 Hz. Using frequency scaling, the output capacitor needs to be 6.033 5E and the other capacitors need to be 0.6033 5E to achieve the desired 12 kHz bandwidth. This simulated current sensing circuit is shown in Figure 28. The frequency response after the frequency scaling is as shown in the dB/phase vs. frequency plot in Figure 29.

Figure 28: Current Sensing Circuit Under Ideal Operational Conditions

Figure 29: Frequency Response after Frequency Scaling

Before moving on to picking parts, the ADC pin current limits requirement needs to be checked. Without checking the simulation, it is expected that a vast majority of the current in the sensor circuit passes through the low impedance path through the burden resistor and the current seen at the output will be negligibly small. As expected, the current that flow through the output capacitor is about 2.5 HI, much smaller than the 10 mA limit of the ADC.

Now that the design requirements of the current sensor have been met, the specific components that will be used can be picked. As with the voltage sensor, tight tolerance components are more appealing for this project. The power dissipation for the burden resistor peaks at about 24 mW and the next highest dissipation in the other resistors peaks at about 9 nW. These dissipations are insignificant to the commonly found 1/10 and 1/8 W resistors. As for the working voltage, the burden resistor will have the highest working voltage and is not anywhere near the values seen in the voltage sensing circuit.

The same resistors picked for the voltage sensor’s 1 AΩ resistors from the Yageo RT series of surface mount resistors will also be used for the current sensor circuit. When looking for a 60 Ω burden resistor, the only available surface mount resistor had an undesirably high tolerance of 10%. A 57.6 Ω resistor with a tolerance of 0.1% and a power dissipation of 1/10W was found in the Yageo RT series of surface mount resistors and will be used for the burden resistor. This smaller resistance changes the output voltage to ±1.152 V peak and the power dissipation decreased to a peak value of 23.03 mW. As was discovered when picking components for the voltage sensor, this series of resistors has many desirable specs for this project.

Similar to the capacitors for the voltage sensor, the capacitors for the current sensor shall have tight tolerances. When viewing the power dissipation in the simulation with the input set to the maximum current of 20 mA, the highest working voltage is 1.15 V peak, the highest current through a capacitor is 1.8516 HI RMS,

73 and the highest amount of dissipation to worry about in a capacitor is a peak value of about 1.5 HK. The capacitors are rounded down to the next readily available values, which keep the ratio used during the design process, of 5.6 nF and 0.56 nF. With these new capacitor values the -3 dB frequency has now shifted to ideally 12.33 kHz according to the simulation. For the 5.6 nF capacitor, the general purpose Murata Electronics North America ceramic capacitors were available and have sufficient specifications to be used for the current sensors. For the 0.56 nF capacitors, the C0G (NP0) Dielectric series of surface mount capacitors by AVX Corporation were found to have comparable specs to the Murata capacitors and are found to have sufficient specifications to be used for the current sensors.

For the protective circuit consisting of the high-speed switching diodes and the TVS diode, its purpose is mostly for ESD protection as there is already a safety margin that was taken into account when picking the burden resistor for the current transformer. The diodes will be picked to limit the input current to the ADC pins and clamp the voltage during current surge events. During ESD events the high current surge will be redirected to the power supply or to ground and the voltage will be clamped by both the high-speed switching diodes and the TVS diode. The diode array connected to the power supply seemed confusing at first, but when viewing the ADC’s datasheet we see that in the event of the input signal exceeded the supply rails TI has designed the input terminals to be diode-clamped to the power-supply rails. Along with the integrated input voltage clamping, we must current limit this event so that the current to the ADC’s input pin does not exceed 10 mA.

At the moment, we know that the output of the current transformer is 20 mA at the highest rated primary current of 60 A. Thus a redirection of 100 mA from a current surge may be more than enough protection. For the transformer to output 100 mA, the three-phase source will need to experience a 300 A surge for the secondary current to reach 100 mA. We also know that the three-phase source has a 60 A fuse installed, so this protection may not be needed. Although it may be unneeded, it will act as a second level of protection as the fuses may not react quick enough to protect our devices.

For the high-speed switching diodes the amount of current conducted at its turn on voltage, the leakage current, reverse recovery time, and capacitance introduced during its off state are important specs to take into consideration for the current sensor. For circuit protection, we want the diodes to be able to redirect a significant amount of current to the power supply or ground to prevent the output from exceeding the ADC’s input current limit. We would like to clamp the voltage to a value of about 2 V but the diode array connected to the power supply will clamp to Vcc+2Vd, thus the current limiting mentioned in the ADC spec sheet is very important for possible ESD events or current surges. The PMLL4148L diode by NXP Semiconductors satisfies the projects needs with specifications including a

74 leakage current of 25 nA at 20V, a capacitance of 4 pF at 0V and 1 MHZ, and a reverse recovery time of 4 ns.

For the bidirectional TVS diode we want the device to have a reverse standoff voltage greater than the ideal operating voltage of the sensor circuit, we want it to withstand high power dissipation, introduce little capacitance in its off state, and by its nature have a quick reaction time. The SMAJ5.0CA TVS diode by Bourns Inc. satisfies the needs of the circuit with a reverse standoff to prevent the TVS diode from conducting unless a high ESD event occurs. The picked TVS diode can hand a current pulse of up to 43.5 A, can handle a peak power pulse of 400 W, and is a zener type diode, thus naturally has a very quick reaction time. The specific component models picked for the current sensing circuit will be stated in the bill of materials later on. 4.1.3 Analog-to-Digital Converter As we began to consider the design of the analog-to-digital converter, as well as the other elements in the system, we discovered that many MCUs offer built-in ADCs that we could leverage. TI offers a wide array of MCUs, many of which are equipped with very capable ADCs that proved to be worth our consideration.

Our motivations for considering the use of an integrated MCU are as follows: • Reduced form factor when the ADC and the MCU are on the same chip • Reduced design efforts • Reduced number of communication channels needed

Table 19 below details the MCUs offered by TI with an integrated ADC and a sufficient number of input channels for our purposes.

Table 19 illustrates that there are ample options in the realm MCUs with an integrated ADC. Several MCUs even have more than one ADC built into it. The table includes the MSP432P401R, which TI recommended for this project, as well as several other contenders. The following information needed to be evaluated when considering these MCUs and, consequently, ADCs for HAQS: • Number of input channels—six total o Three for voltage o Three for current • Furthermore, the number of differential versus single-ended inputs • Number for GPIO pins and communication pins • High resolution to accurately and reliably digitize the signals and minimize quantitation noise

75 Table 19: TI MCUs with Integrated ADCs Part Number GPIO I2C SPI UART ADC ADC10 - 6ch, MSP430F6778 90 2 6 4 SigmaDelta24 - 7ch ADC10 - 6ch, MSP430F67781 90 2 6 4 SigmaDelta24 - 7ch ADC10 - 6ch, MSP430F67781A 90 2 6 4 SigmaDelta24 - 7ch ADC10 - 6ch, MSP430F6778A 90 2 6 4 SigmaDelta24 - 7ch ADC10 - 6ch, MSP430F6779 90 2 6 4 SigmaDelta24 - 7ch ADC10 - 6ch, MSP430F67791 90 2 6 4 SigmaDelta24 - 7ch ADC10 - 6ch, MSP430F67791A 90 2 6 4 SigmaDelta24 - 7ch ADC10 - 6ch, MSP430F6779A 90 2 6 4 SigmaDelta24 - 7ch MSP430FG6626 73 4 4 2 SigmaDelta16 - 10ch 84, 4, 8, 4, ADC14 - 24ch, 64, 4, 7, 3, ADC14 - 16ch, MSP432P401M 48 3 6 3 ADC14 - 12ch 84, 4, 8, 4, ADC14 - 24ch, 64, 4, 7, 3, ADC14 - 16ch, MSP432P401R 48 3 6 3 ADC14 - 12ch

The major drawback to using an integrated ADC, however, is the fact that many MCUs have more architecture dedicated to SAR ADCs than Sigma-Delta ADCs. This was a compromise we were willing to make, provided the MCU offered all other criteria. SAR only narrowly edges out Sigma-Delta, with a slight advantage in accuracy being the main winning point of Sigma-Delta conversion.

Based on these needs, the MSP432P401 stands out as an obvious option, as it offers a 14-bit SAR ADC. However, because this project depends heavily on the accuracy of the conversion and the minimization of quantization noise, we agreed upon the fact that a higher resolution was necessary.

Many of the MCUs in the table above have 24-bit Sigma-Delta ADCs built-in, and while they have a sufficient number of input channels, they were lacking in the number communication pins. The MCU must have enough communication pins to interface with and host the LCD and SD Card, which came to a count of six (6) communication channels required. More specifically, we were aiming to find an MCU with six SPI channels. Again, the MCUs in the table above offer six SPI channels.

The problem was finally discovered that none of the MCUs with sufficient integrated ADCs offered enough differential input channels. For example, the MSP430FG6626 has ten (10) input channels into the ADC, but only four (4) of

76 those are differential inputs. The remaining inputs are single-ended, which we decided we wanted to avoid in order to minimize noise and cross-talk contamination between all six inputs. The quality of the project might drop by using a 14-bit ADC over a 24-bit ADC or by choosing a SAR ADC over a Sigma-Delta ADC. But the project becomes impossible if we do not have a sufficient number of inputs for the six voltage and current waveforms that we will be analyzing [54].

This put an end to the idea of using an integrated ADC. For the all the benefits and simplifications that such a solution offers, not having enough differential inputs for the evaluation of the three-phase THD is crippling to the functionality of the project. Thus, we started searching for a discrete ADC. The same search criteria still applied: a sufficient number of differential input channels and high resolution to achieve accuracy and reduce quantization noise.

From there, we had to decide which standalone ADC we would use. Table 20, below, outlines the options available from TI. The criteria for the ADCs in the table are as follows: • Delta-Sigma architecture • Active ADCs • High Precision ADCs • Maximum cost of $50

Table 20: Discrete ADC Comparison Resolution Sample Rate # Part Number Description (Bits) (max) (SPS) Inputs Octal, Simultaneous Sampling, 16-Bit Analog-to-Digital ADS1178 Converter 16 52kSPS 8 High Resolution, Low Noise, 32-bit, 38kSPS ADC with PGA ADS1262 and Internal Reference 32 38kSPS 10 High Resolution, 32-bit, 38- kSPS, ADC with PGA, Int ADS1263 Reference and Auxiliary ADC 32 38kSPS 10 Octal, 144kHz, Simultaneous Sampling 24-Bit Delta Sigma ADS1278 ADC 24 144kSPS 8 8-Channel, 24-Bit Analog-To- Digital Converter With ADS1298 Integrated ECG Front End 24 32KSPS 8 8-Channel, 24-Bit Analog-To- Digital Converter w/Integrated Respiration Impedance and ADS1298R ECG Front End 24 32KSPS 8 Analog Front-End for Power Monitoring, Control and ADS131E08 Protection 24 64kSPS 8

77 At the beginning of this project, TI recommended the ADS131E08; therefore, we researched the ADS131E08 extensively and ultimately opted to incorporate this ADC into our design.

The 24-bit resolution offers quantization steps of 20.2 µV, which is excellent when accuracy is of utmost importance. This also limits quantization noise to 10.1 µV. Being able to sample all eight differential channels simultaneously will also prove to be useful for the overall accuracy of the THD measurement, as the waveform might twitch or jump slightly at different times. Thus, as per TI’s recommendation and our own researching into the available options, HAQS will incorporate the use of the ADS131E08 ADC [55].

Another benefit of using the ADS131E08 is the compatible Evaluation Module that TI offers. The ADS131E08EVM-PDK Evaluation Module shall be used to aide development efforts in designing a PCB that hosts all necessary functions of the ADS131E08 [56]. In addition to the ADC chip, we will also need the following items for the design of the ADC PCB: • Male and Female Pin interconnects and various jumpers for input/output purposes as well as signal routing within the PCB • Terminal blocks to input the analog signal • Ferrite beads for protective purposes • An external voltage reference • An oscillator to control the frequency of conversion • Several types of power modules to service and power the board’s functions • EEPROM module

This list provides a general idea of what will be required for the design of the ADC PCB. More detail shall be provided in the Final PCB Design Section. 4.1.4 Microcontroller Unit Our final design will implement only the necessary features available and used from the prototype during testing. This means our programmed microcontroller unit will need to be removed from the prototype LaunchPad. It may be necessary to program a new microcontroller for the sake of being mounted on the final printed circuit board given the LaunchPad microcontroller is not recoverable.

There will be several components directly connected to the mounted microcontroller on the final printed circuit board. Components like the SD card reader and LCD screen controller unit will be implemented on the final board, requiring connection lines on the final board that can be used to connect the actual device or chip.

78 4.1.4.1 Liquid Crystal Display The printed circuit board that our team uses in the end will implement most of the connections present on the board LCD and Capacitive Touch screen’s controller. Due to the added integration of the MCU to a capacitive touch LCD this allow for most of the MCU’s general purpose input output pins to be used with the majority of the LCD and Capacitive Touch Controller pins. The LCD will be powered by a 5.0 V rail, and the controller will be powered with a 3.3 V rail. 4.1.4.2 SD Card Reader Our final printed circuit board will implement most of the connections present on the board of the CardReader SDCard BoosterPack used within our prototype design. There will be no need for the breakout pins or the 40-pin LaunchPad adapter pin set on the BoosterPack board, but everything else should be implemented on our final design in such a way that the SD card reader can be correctly interfaced with. Additionally, the LED connected to the Card Detection pin on the card reader will not be necessary, reducing the number of additional components to mount on the final circuit board. 4.1.5 Power Supply Unit The Power Supply Unit must be capable of fulfilling the power requirements listed in Figure 30, which contains a detailed Power Flow for the system. Above the PSU block and the individual regulator blocks are the voltage, current, and power requirements of the components that will be supplied by the regulators. To the side of each component is the individual voltage, current, and power needs. The block above the PSU contains the requirements for the overall system.

Figure 30: System Power Flow Diagram

The above figure was generated using worst-case-scenario values, such as inrush currents and maximum momentary currents. Thus designing a PSU capable of delivering 2.507 W would suffice for the power needs of the system. However, in order to guarantee that there is enough power to be distributed to the entire system under all circumstances, we must look at the maximum voltage provided by the PFC circuit and the individual regulators. Since we have already factored in the maximum current draw of the system, by finding the percent overshoot of the voltage, we can find the optimum value for the PFC output power. This design decision will be detailed in a later section.

For the sake of generating this Power Flow diagram, the assumption was made that the voltage regulators would run in series. The advantages and disadvantages of this approach will be evaluated later in this section in order to make a final design decision.

The PSU input will directly interface with the three-phase power outlet. Designing a PSU that functions with three-phase power would complicate design efforts, so instead, HAQS will only take one phase of power from the outlet. The design conceived during the research phase shall be modified in this section to best fit the components available. The parameters of the design and the components shall be discussed throughout this section.

In order to ensure that the input signal is clean and relatively free of preventable noise, the input will be filtered using an Electromagnetic Compatibility (EMC) filter. EMC is described as a device’s ability to function as intended in an electromagnetic environment without, in turn, producing or emitting an electromagnetic field that would be harmful to other devices in the system. The EMC filter serves to reduce the amount of electromagnetic noise transferred between the mains power supply and the load. Applying the EMC filter serves to protect and improve the quality of the power system [57]. Figure 31, below, shows a basic EMI filter:

Figure 31: EMI Filtering Circuit

The next step in conditioning and processing the 120 VRMS input voltage signal to something that is efficient and usable by the system is to address the power factor issue that would be otherwise present. To do this, a TI UCC29950 PFC IC will be worked into the traditional step-down and rectification. The resulting circuit will resemble the circuit in Figure 32.

Figure 32: PFC Circuit Reprinted with permission from Texas Instruments

The first block, the EMC Filter has already been discussed. Note that following the PFC circuit incorporates a diode bridge rectifier. Because the voltage will be rather large, it is important to find a diode bridge that can operate under such conditions. The Vishay KBL02, shown below in Figure 33, allows an input voltage of up to 200 VRMS and can survive an average forward current of 4.0 A, which is safely beyond the scope of our needs. The datasheet provided by Vishay notes that this particular diode bridge is typically used for AC/DC full wave rectification and Switched-Mode Power Supplies, which is appropriate for our uses. The transformers incorporated in the the PFC circuit will also need to be large enough to handle the voltages that will be present [58].

Figure 33: Vishay KBL02 Diode Bridge Rectifier Reprinted with permission from Vishay Image courtesy of Vishay Intertechnology

With some of the preliminary pieces of information regarding the PFC circuit covered, we will not discuss the design of the PFC itself.

The first element to design is the voltage sensing portion of the PFC circuit, shown in Figure 34. TI specifies the following • RL1 = RL2 = 9.3 MΩ • RTOP = 30 MΩ • RBOT = 73.33 kΩ

These parameters meet another requirement for the PFC: that the RTOP:RBOT ratio must not be greater than 425. The specified resistors provide an ideal ratio of 410. VBULK should be as close to a nominal regulation point of 385 V as possible. This is an ideal parameter for the UCC29950 [57].

Figure 34: PFC Voltage Sensing Circuit Reprinted with permission from Texas Instruments

Following the voltage sensing circuit is the current sensing circuit, shown in Figure 35. TI specifies the following: • RF(pfc) = 1 kΩ

Based on the 7 W need of the system, RCS(pfc) = 1400 mΩ (below the MOSFET) [57].

Figure 35: PFC Current Sensing Circuit Reprinted with permission from Texas Instruments

The UCC29950 offers flexibility in the design process in that for certain steps, there are several configurations worth considering. The first design decision that we must consider is how to bias the PFC circuit. The UCC29950 can be biased in one of two ways: it can operate under a self-biasing mode, or it can be biased by an external source in auxiliary bias mode. The auxiliary bias mode provides flexibility with the operational modes of the PFC circuit, but such functionality is not necessary for the HAQS PSU. Additionally, it requires an external component that would otherwise require incorporation into the system, which complicates the PCB layout and design efforts in general [57]. The setup for the UCC29950 self bias mode is shown in Figure 36. The zener diode is an 18 V diode, as per TI’s specifications.

Figure 36: PFC Self-Bias Configuration Reprinted with permission from Texas Instruments

Following the bias operational mode, another decision must be made regarding how to drive the MOSFET. Once again there are two options: drive the MOSFET Gate with a transformer, or drive the MOSFET Gate with an external driver device. The first method requires no extra components but does incorporate the use of a one-input-two-output transformer, which adds size and noise to the PSU environment. In this instance, the inclusion of an external device simplifies design efforts by eliminating the need for such a transformer. The MOSFET Gate driver device is shown in Figure 37.

Figure 37: External MOSFET Drive Device Reprinted with permission from Texas Instruments

After these design decisions have been made, the values for the individual components must be computed. TI has provided the values for several components that do not change from design to design, as listed above, but the other component values must still be calculated in order to complete the design. For the sake of brevity, the design calculations and processes will be omitted. Instead, the values for the components required can be found in the Bill of Materials section.

The voltage coming out of the PFC will be a DC voltage that can be determined based on the components used. TI offers several design tools that accompany the UCC29950. An output voltage of 24 VDC has been selected. The design tools also recommend this output voltage for various reasons, including the ease of sourcing parts that are required to achieve this output. The components required for this process will be listed in the Bill of Materials section.

Table 21 below shows the projected maximum voltages provided by the PFC circuit and the regulators. The maximum percent overshoot will guide the design of the PFC output power parameter.

Table 21: Maximum Voltages from PSU Components Component Nominal Output Maximum Output Percent Overshoot UCC29950 24.000 V 24.300 V 1.250% LM46001 5.000 V 5.080 V 1.600% LM23001 3.000 V 3.030 V 1.000% LM23001 1.800 V 1.809 V 0.500%

Based on the information in the preceding table, the PSU will be designed to deliver of 2.6 W power, providing a roughly 2% overshoot of the nominal power needed.

Now that the initial 120 VRMS has been processed and converted to a lower DC voltage, the voltage needs to be stepped down and regulated to the appropriate voltage levels in order to power the remaining components in the system. Based on the research conducted prior to the design phase, HAQS will utilize a switching voltage regulator. The use of a switching voltage regulator prevents us from having to reduce the DC voltage signal any further prior to regulation, which would not be the case for a linear regulator.

The step down and regulation can ideally be done with one component. The goal is to find a switching regulator that can accept the designed DC voltage as an input and output 5.0 VDC, 3.0 VDC, and 1.8 VDC.

Two major design methods need to be evaluated when looking through the available voltage regulators. 1. Feed the higher DC voltage into three voltage regulators in parallel that will output their respective regulated voltages. 2. Cascade the three regulators: have the first take in the higher DC voltage and output 5.0 VDC, which will feed into the next regulator and output 3.0 VDC, which will feed into the final regulator and output 1.8 VDC.

The first method simplifies design efforts. It will only require one type of regulator, configured in three different ways. The tools and software at our disposal while

85 working on this project make generating three designs a simple task. It also reduces the variety of components needed, since, for many regulators, the output is designated by the resistors chosen. Using the same voltage regulator three time means having the same capacitors and configuration for each regulator and only needing to change the resistor values—which is both simple and cost effective.

The second method increases efficiency. For the sake of discussion, we assume that the initial DC voltage is 25 VDC. Stepping 25 VDC down to 5.0 VDC, 3.0 VDC, and 1.8 VDC is multiplied inefficiency; that is to say that all three regulations cause a loss in power during the step down and regulation processes. If, instead, we opt to cascade the regulators, then the first regulator might suffer in the realm of efficiency, but stepping down 5.0 VDC to 3.0 VDC and 3.0 VDC to 1.8 VDC is significantly more efficient than the method outlined in the previous paragraph and at the beginning of this paragraph.

Both methods have advantages and disadvantages. To effectively evaluate both options, we looked at components that would work for method one and components that could work for method two separately. Then we selected the best component in each instance and ran WEBENCH simulations in order to compare the reference designs generated for their individual purposes. The results of the comparison directed us to the best regulator for HAQS.

Table 22, below, lists the regulators that would suffice in a design that organizes the regulators in parallel. The minimum input voltage is of no concern in this design because the voltage will be rather high, but the regulators listed below can accept input voltages of 35 VDC and higher, as well as output voltages as low as 0.8 VDC. These parameters fit safely into the designs considered for the PSU.

86 Table 22: Viable Regulators for Parallel Regulation Part Vin Vin Vout Vout Number Description (Min)(V) (Max)(V) (Min)(V) (Max)(V) 4.5-36V, 3A Current Mode Synchronous Buck Regulator with Frequency LM20333 Synchronization 4.5 36 0.8 32 4.5-36V, 3A Current Mode Synchronous Buck Regulator LM20343 with Adjustable Frequency 4.5 36 0.8 32 3A Switching Regulator with LM26003 High Efficiency Sleep Mode 3 38 1.25 35 SIMPLE SWITCHER® 3.5V to 36V, 1A Synchronous Step-Down Voltage LM43601 Converter 3.5 36 1 28 SIMPLE SWITCHER® 3.5V to 36V, 3A Synchronous Step-Down Voltage LM43603 Converter 3.5 36 1 28 SIMPLE SWITCHER® 3.5 to 60V, 1A Synchronous Step- LM46001 Down Voltage Converter 3.5 60 1 28

The TI LM46001 was chosen for regulatory purposes because of its compatibility with a wide range of input and output voltages. The LM46001 can accept an input voltage of 3.5 V to 60.0 V with an output range of 1.0 V to 28.0 V. This is particularly beneficial to HAQS design efforts because it allows for the same regulator to be used across the board for all required voltage supply values in a parallel configuration. Furthermore, the LM46001 can output up to 1 A of current, which, again, is safely beyond the scope of the system’s needs [59].

The LM46001 is current-mode controlled. This provides the advantage of a faster response than the voltage-mode controlled counterpart, as well as improved compensation when the input voltage changes, due to the addition of an inductor. Current-mode controlled regulators are, however, more difficult to analyze. The use of an integrated solution will ease design efforts, as the LM46001 has several functions built in that would be difficult to capture, had we elected to design the regulators ourselves [59].

Some of these functions include: • High efficiency, which is achieved using Discontinuous Conduction Mode and Pulse Frequency Modulation, • Internal compensation to decrease design efforts and the number of external parts needed, • Soft-Start to prevent any damaging inrush current,

87 The datasheet for the LM46001 provides a detailed design example, but Texas Instruments’ WEBENCH tool proved to be useful in generating a design that fits the PSU’s needs. The simulation schematics generated by WEBENCH are shown in Figure 38, Figure 39, and Figure 40. Notice how the layouts and capacitor values are consistent across the three designs. This is a major advantage for parallel regulation.

Figure 38: LM46001 5.0 VDC Regulated Circuit Reprinted with permission from Texas Instruments

Figure 39: LM46001 3.0 VDC Regulated Circuit Reprinted with permission from Texas Instruments

Figure 40: LM46001 1.8 VDC Regulated Circuit Reprinted with permission from Texas Instruments

Table 23, below, lists information regarding the designs above. This information will also be used later to directly compare to the results gathered from analyzing the serialized method of regulation.

88 Table 23: Parallel Regulation Design Statistics Design BoM BoM Efficiency Footprint Power Cost Count Dissipated 5.0 VDC $2.54 11 79% 187 1.34 W Regulator 3.0 VDC $2.51 10 70% 175 1.30 W Regulator 1.8 VDC $2.68 11 67% 237 0.88 W Regulator Average $2.57 10.67 72% 199.67 1.17 W

Table 24 below, lists the regulators that would suffice in a design that organizes the regulators in parallel. The minimum input voltage was of significant concern for this design method, as the input voltage decreases across the three regulators. The 5.0 VDC regulator has to be able to accept the highest input voltage of the three. Though it is not on the table, the LM46001 can be used again in the same form as the previous design. Following this, the second and third regulators only need to be able to accept an input of 5.0 VDC and 3.0 VDC. The LM20133 is chosen for the second and third regulators. The benefits and features of the LM20133 are similar to what the LM46001 offers, thus they will not be discussed in this section to avoid redundancy [60].

Table 24: Viable Regulators for Serial Regulation Part Vin Vin Vout Vout Number Description (Min)(V) (Max)(V) (Min)(V) (Max)(V) 2.95-5.5V, 5A, Current Mode Synchronous Buck Regulator LM20125 with Optional Automotive Grade 2.95 5.5 0.8 5 2.95-5.5V, 3A, Current Mode Synchronous Buck Regulator with Input Sync and Optional LM20133 Automotive Grade 2.95 5.5 0.8 5 2.95-5.5V, 4A, Current Mode Synchronous Buck Regulator with Input Sync and Optional LM20134 Automotive Grade 2.95 5.5 0.8 5 2.95-5.5V, 6A, Current Mode Synchronous Buck Regulator LM20136 with Input Synchronization 2.95 5.5 0.8 5 2.95-5.5V, 5A, Current Mode Synchronous Buck Regulator LM20145 with Adjustable Frequency 2.95 5.5 0.8 5 1.5A Switching Regulator with LM26001 High Efficiency Sleep Mode 3 38 1.25 35 3A Switching Regulator with LM26003 High Efficiency Sleep Mode 3 38 1.25 35

89 The simulation schematics generated by WEBENCH are shown Figure 41 and Figure 42.

Figure 41: LM20133 3.0 VDC Regulated Circuit Reprinted with permission from Texas Instruments

Figure 42: LM20133 3.0 VDC Regulated Circuit Reprinted with permission from Texas Instruments

Table 25, below, lists information regarding the designs above. This information will also be used later to directly compare to the results gathered from analyzing the serialized method of regulation.

90 Table 25: Serial Regulation Design Statistics Design BoM BoM Efficiency Footprint Power Cost Count Dissipated 5.0 VDC $2.54 11 79% 187 1.34 W Regulator 3.0 VDC $2.54 14 96% 157 0.12 W Regulator 1.8 VDC $2.49 13 95% 145 0.10 W Regulator Average $2.52 12.67 90% 164 0.52 W

Table 26, below, compares the averages of the selected parameters from the parallel and serial methods of regulation.

Table 26: Parallel vs. Serial Comparison Design BoM BoM Efficiency Footprint Power Cost Count Dissipated Parallel $2.57 10.67 72% 199.67 1.17 W

Serial $2.52 12.67 90% 164 0.52 W

Advantage Serial Parallel Serial Serial Serial

Based on the WEBENCH simulation results, using serial regulation is the better of the two options. The design lacks uniformity (which adds to design complexity) and has a slightly higher part count, but the efficiency, footprint, and power dissipation tend toward more advantageous values. Thus, HAQS will use the LM46001 in conjunction with the LM20133 in order to achieve the regulated voltages needed to power the system’s components.

With the regulated outputs achieved, all that is left is to ensure that the currents into each component are within the acceptable range. This will require measurements made during the design and testing phases and will, therefore, remain ambiguous until then.

Table 27 contains the updated design parameters as a summary of the design choices made during the process of choosing components to achieve the requirements of the PSU:

91 Table 27: Final PSU Design Values Parameter Value Input Voltage 170 V (120 VRMS) Approximated DC Voltage 24 VDC Regulated Output Voltage 5.0 VDC 3.0 VDC 1.8 VDC

4.2 Software The following information details the expected procedures our microcontroller unit will follow in order to carry out the desired task of harmonic analysis. From the perspective of the microcontroller, the process begins by initializing all necessary input and output pins for communication. This ensures that the components within our system can be put to use when that stage of the process arrives. This step includes setting up communication with the onboard SD card reader, the separate ADC unit and the touch capacitive LCD screen. The step also ensures that the ADC is properly initialized and waiting for the ready signal to begin sampling input data from the three-phase source.

The next stage is where the device will spend most of its time from the perspective of the user. At the idle stage, the LCD will display a ready screen providing interactive onscreen buttons for input. The idle stage will display the information from the last sample taken by reading the most recent results from the SD card reader. This is the only stage where the user is able to interact with the system to either give input or observe output. During idle the device will wait for user input, prioritizing the initiate sample input button. Other functionality will be available to the user at this stage, such as adjusting the displayed graph with the left and right onscreen buttons.

Pressing the initiate sample input button in the idle state will allow the process to proceed to the sampling stage. This will tell the microcontroller to read in data from the device’s ADC unit. The ADC will begin sampling all six sources and stream the information to be stored in the microcontroller’s memory. Once appropriate samples have been taken for all sources, the sample information will need to be formatted into arrays of complex numbers. Specifications on the complex number data structure are provided within this documentation. Once the sample arrays have been correctly formatted, the microcontroller will be able to perform a Fast Fourier Transform on the data. Results then can undergo additional computation to be filtered and formatted to be more user-friendly and readable.

Filtered results are written to the removable SD card to keep a log of sampled data for later analysis by the user as well as reviewing at a later time on the device. The results are also displayed on the LCD in the form of a bar graph and percentage

92 values. Additionally, the total harmonic distortion percentage will be displayed for easy qualitative analysis of the sampled power. The microcontroller then returns to its idle state to accept additional user input if necessary. Once one sample has been taken, the displayed graph in the idle state can also be scrolled to the left or right through user input on the LCD. This will not sample the inputs again, but simply display different harmonic content that previously would not fit on the display screen. Once the updated information is correctly and completely displayed on the LCD screen, the device will return to its idle state. The process flow described above is illustrated in Figure 43.

Figure 43: Process Flow Diagram

94 4.2.1 Data Structures 4.2.1.1 Complex The complex data structure, seen in Figure 44, is used to represent one complex number pair. This pair consists of a floating point real value as well as a floating point imaginary number. It is useful to define this structure due to the imaginary information resulting from a Fourier transform on real valued data. With the complex data structure defined, arrays of these value pairs can be declared and used in storing sample and resultant data.

The following implementation of the complex data structure additionally defines a function for multiplying two complex numbers. This is necessary for taking into account the twiddle factor when computing an input array’s Fourier transformation using a Fast Fourier Transform algorithm. The function takes in two complex numbers and returns a new complex number which is the product of the two inputs. Other complex functions, such as addition and subtraction, are not defined separately due to their simplicity. This is done to prevent unnecessary jump instructions in the compiled results.

Figure 44: Complex Data Structure

4.2.1.2 Fast Fourier Transform The FourierTransform data structure, seen in Figure 45, is used to abstract the transformation of a signal in the time domain to its representation in the frequency domain. It is a static structure that holds onto two constant values: two pi and negative two pi. These are stored so they do not need to be unnecessarily computed hundreds of times during the transformation. It has a method fft that computes the transformation of a given signal in the form of an array of complex numbers.

Figure 45: Fast Fourier Transform Data Structure

4.2.1.3 Analog-to-Digital Converter The ADC data structure, seen in Figure 46, is in charge of abstracting the process of sampling data from the power source. It has a pin set that gets initialized and made use of to tell the necessary devices to sample. ADC also holds two constant values: SAMPLESIZE and SAMPLERATE. These values determine how quickly the ADC unit is told to sample information and for how long. ADC also has a sample method that will read information from its communication pins and build up an array of complex numbers to be returned to the caller.

Figure 46: ADC Data Structure

4.2.1.4 SD Card The SDCard structure, seen in Figure 47, abstracts the functionality of the external SD card reader that is used to store and load information about previous power source samplings. The SDCard structure has a pin set variable used to track the pin values necessary for communication with the device and the microcontroller. It also stores the number of lines written to the SD card’s only file: a .csv containing result data from each previous sampling. The SDCard structure has the methods writeLine and readCurrentLine which are used to store the currently displayed sample and display the most recently saved sample respectively. SDCard can

96 similarly read a line of the specified row. SDCard can also open and close the file stream available to the SD card reader.

Figure 47: SD Card Data Structure

4.2.1.5 Liquid Crystal Display The LCD data structure, seen in Figure 48, holds onto its own pin set for communication with the external capacitive touch screen. LCD knows the current waveform it is displaying as both the array of double precision floating point values for each frequency as well as the line the information is stored on in the SD card. As the main output of the device, the LCD structure provides a method that will draw a given waveform signal to the screen as a bar graph of harmonic content. The LCD can scroll the displayed output left and right without requiring any information outside of its own members due to the displayed data being stored within it. The LCD structure provides an idle method that can be called to spend time polling for inputs to the capacitive touch screen. The method will adjust the pins member and return true or false depending on whether a button was pressed. This will allow the main function to determine what action to perform based on the pin state found within the LCD data structure.

Figure 48: LCD Data Structure

4.3 Prototype Assembly Our prototype device, unlike the final design, will not be one complete and unified unit on one printed circuit board. The prototype device will be composed of several boards integrated together for communication between each component of our design. The prototype will be used to test functionality, both as unit tests for each component as well as integration tests for interactions between components. Given that we need to ensure our design and components operate as expected, it will be essential to detail how our prototype will be prepared for testing. This will allow us to follow through with our final design once all tests pass and requirement specifications are met.

The first step to prototyping the system is mapping out how each of the components communication. To that end, our team created an I/O Pinout table to aid prototyping efforts. The pin designations are named in relation to the prototype boards called out below.

Table 28, and Table 29 below outline the pins used for the communication of data among the components.

Table 28: SD Card to MCU Pinout Part A Part B Connection from A Connection to B SD Card MCU Data In Pin 2 SIMO P1.6 SD Card MCU Data Out Pin 7 SOMI P1.7 SD Card MCU GP (Ground) GND SD Card MCU VCC Pin 4 +3.3V SD Card MCU Clock Pin 5 Clock P1.5 SD Card MCU CS Pin1 GPIO P4.6

Table 29: LCD to MCU Pinout Part A Part B Connection from A Connection to B LCD MCU Pin 19 Enable P3.0 LCD MCU Pin 13 Clock P3.1 LCD MCU Pin 12 SOMI/SIMO P3.2 LCD MCU Pin 2 Pin 7.1 LCD MCU Pin 3 Pin 7.2 LCD MCU Pin 4 Pin 7.3 LCD MCU Pin 5 Pin 7.4 LCD MCU Pin 6 Pin 7.5 LCD MCU Pin 7 Pin 7.6

98 Table 30: LCD to MCU Pinout (continued) Part A Part B Connection from A Connection to B LCD MCU Pin 8 Pin 7.7 LCD MCU Pin 9 Pin 7.8 LCD MCU Pin 22 Pin 6.1 LCD MCU Pin 23 Pin 6.2 LCD MCU Pin 24 Pin 6.3 LCD MCU Pin 25 Pin 6.4 LCD MCU Pin 26 Pin 6.5 LCD MCU Pin 27 Pin 6.6 LCD MCU Pin 28 Pin 6.7 LCD MCU Pin 29 Pin 6.8 LCD MCU Pin 31 Pin 5.1 LCD MCU Pin 32 Pin 5.2 LCD MCU Pin 33 Pin 5.3 LCD MCU Pin 34 Pin 5.4 LCD MCU Pin 35 Pin 5.5 LCD MCU Pin 36 Pin 5.6 LCD MCU Pin 37 Pin 5.7 LCD MCU Pin 38 Pin 5.8 LCD MCU Pin 39 Pin 5.9 LCD MCU Pin 40 Pin 5.10

Table 31: AC Input to ADC Pinout Part A Part B Connection from A Connection to B Voltage Phase A ADC VA + Pin 16 ADC VA - Pin 15 Voltage Phase B ADC VB + Pin 14 ADC VB - Pin 13 Voltage Phase C ADC VC + Pin 12 ADC VC - Pin 11 Current Phase A ADC IA + Pin 10 ADC IA - Pin 9 Current Phase B ADC IB + Pin 8 ADC IB - Pin 7 Current Phase C ADC IC + Pin 6 ADC IC - Pin 5

Table 32, Table 33, Table 34, Table 35, and Table 36 below outline the pins used for powering the components. Note that the analog and digital grounds should be tied together in order to keep the applied potentials equal across the components.

99 Table 32: Power to ADC Pinout Part A Part B Connection from A Connection to B 3.0 V regulator ADC 3.0 V output AVDD Pins 19,21,22,56,59 3.0 V regulator ADC 3.0 V output AVDD1 Pin 54 AGND ADC PSU ground AVSS Pins 20,23,32,57,58 AGND ADC PSU ground AVSS1 Pin 53 1.8 V regulator ADC 1V8 output DVDD Pins 48,50

Table 33: Power to Current Senor Pinout Part A Part B Connection from A Connection to B 3.0 V regulator Current Phase A 3.0 V output ESD Diode Circuit VCCs 3.0 V regulator Current Phase B 3.0 V output ESD Diode Circuit VCCs 3.0 V regulator Current Phase C 3.0 V output ESD Diode Circuit VCCs

Table 34: Power Supply to MCU Pinout Part A Part B Connection from A Connection to B 3.0 V regulator MCU 3.0V DVCC Pins 13, 73 3.0 V regulator MCU 3.0V AVCC Pins 45, 87 GND MCU GND AVSS Pins 43, 84, 40 GND MCU GND DVSS Pins 15, 72, 82

Table 35: Power Supply to LCD Pinout Part A Part B Connection from A Connection to B 3.0 Regulator LCD 3.0 V output AVDD Pin 1, 21 3.0 Regulator LCD 3.0 V output VDDIO pin 19 3.0 Regulator LCD PSU ground GND pins 10, 18, 30,

Table 36: ADC DGND to MCU DGND Part A Part B Connection from A Connection to B MCU ADC DGND Pin 15 DGND Pin 33,49,51

4.3.1 Microcontroller Unit Our prototype will make use of the MSP432P401R LaunchPad and its large amount of breakout pins for communicating with the necessary external devices. We will use the LaunchPad and its USB adapter to load our software onto the chip for testing as well as for the final printed circuit board design. The LaunchPad can be used to easily load software onto the chip which can then be removed to be mounted on the final circuit board. Several breakout pins from the LaunchPad will be used when assembling our prototype as described in the pin connections section. Several devices will be using SPI communication which requires at least four pins to for the standard and sometimes more general purpose input/output

100 pins for additional control. Once the necessary components have their communication channels and power connected the prototype will be complete and can be tested. 4.3.2 SD Card Our prototype will be assembled using an SD Card BoosterPack called The CardReader. This BoosterPack is made available through 43oh, a store and forum for organizing the design of TI LaunchPad BoosterPacks. The CardReader is designed for use with a 40-pin MSP430 LaunchPad but is compatible with 20-pin variants as well as our chosen MSP432 LaunchPad in its 40-pin configuration. The reader device within the BoosterPack is compatible with the standard SD Card form factor and not a micro or mini SD Card form. This is not relevant to our design as we plan to employ a standard SD Card form factor. Additionally, the user guide of The CardReader BoosterPack provides relevant code samples based on the Petite FatFS library we plan to implement as our file system.

The SD Card section will be assembled similarly to how any BoosterPack is interfaced with. Its two pin sets will be mounted on our MSP432P401R LaunchPad to connect the major control pins and digital power lines. The BoosterPack will then need to make use of its available breakout pins to connect to an available communication port on the microcontroller through the LaunchPad. The BoosterPack is designed to ease implementation within a prototype device, so this should be the only steps needed to start making use of the SD card reader. 4.3.3 LCD and Capacitive Touch Controller Our prototype will make use of many general purpose input output pins that the MSP432P401R has available along with the capacitive touch supportive features. The LCD we have chosen requires very few I2C pins and can free up any of the MCU’s serial pins that may have been originally thought to be reserved for the LCD. The most that the LCD and Controller need for the prototype to be complete is making sure the communication pins are connected and that it is being supplied the correct power. 4.3.4 Analog-to-Digital Converter For the purposes of prototyping, the ADC IC shall be mounted to the same ADS131E08EVM-PDK module used in the testing phase. This will allow us to prototype the system early enough in the process to make any necessary adjustments, reductions, or additions before designing and fabricating the final PCB for the ADC. The ADS131E08EVM-PDK was acquired from TI.

The board itself shall be prototyped using a breadboard before the final design can be considered verified and ready for fabrication. The schematics that will be tested

101 and ultimately incorporated into the PCB can being found in the TI ADS131E08EVM-PDK User’s Manual. 4.3.5 Power Supply Unit The PSU as it will exist in the final design will not be included in the prototype. Instead, we shall opt to focus our design efforts on the other components of the system and save the PSU for later in the development process. For the time being, the system will be powered using Three-Channel Power Supply.

The PSU itself, however, will undergo prototype testing in parallel with overall system prototype testing. The PSU will be constructed and tested on a breadboard until it is verified and ready for manufacturing. At that point, the PSU will be implemented into the system. 4.4 Final PCB Design 4.4.1 Design The system shall incorporate the use of a PCB for the following systems: • ADC • MCU o SD Card Reader o LCD Controller • PSU • Voltage Sensor • Current Sensor

The goal is to capture all of these schematics on the same circuit board. Size constraints may prevent this goal, however. The PCBs need to be small enough to fit inside the enclosure, which we are trying to minimize for the sake of transportability. Of course, the PCB can host multiple layers, which will shrink the overall size of the card, but multilayer PCBs are also associated with higher cost and more difficulty to maintain or fix if something is damaged.

These design decisions shall be made after the PCBs are constructed and our options are evaluated. 4.4.2 Design Design is currently underway with a projected completion of December 22, 2015, after which point the team will choose a vendor (options listed below) and have multiple copies of the board constructed for prototyping, testing, and construction.

102 4.4.3 Software The PCBs will be design using CadSoft’s Eagle PCB Design software. 4.4.4 Vendor The options we are currently considering for our PCB vendor are: • Avanti Circuit, Inc. • Advanced Circuits • Sunstone Printed Circuit Boards

The final vendor will be chosen upon designing the PCBs and sending out the gerber files for a quote from each company. Turnaround time, price, and quality all need to be taken into consideration. 5 Testing Our group will perform the next group of tests either separately or cooperatively, and simultaneously in locations we deem necessary in order to bring the project ready for full sub-system integration. Most of the testing will be conducted in the Senior Design Lab due to the readily available parts and lab equipment. 5.1 Module Testing This section will specify unit tests and small integration tests that will be carried out to ensure the operability and functionality of each separate block in our design. The smaller integration tests will require the use of multiple components to ensure the correct functionality of one of the components. This is due to the nature of several blocks within our design, such as the ADC, which cannot be properly tested by itself without another block to provide output results to us correctly. 5.1.1 Voltage Sensor Testing The voltage sensor shall be tested to verify that all of the requirements in the design section were met. This means that we are simply testing to ensure the voltage divider ratio is correct and we will also verify the frequency response of the circuit. Although we won’t be using a high voltage source we will also check the ratio of current that is delivered from the voltage source and seen at the output is comparable to the same ratio seen in the simulation. The equipment used for this test will consist of a function generator available in the senior design lab, a DC power supply available in the senior design lab, a digital multimeter, an oscilloscope available in the senior design lab, a bread board to prototype the circuit upon, and the necessary components needed to realize the circuit. The components used will be through-hole components with comparable specifications to the surface mount components that were picked for the voltage sensor. Using the input impedance specification of the ADC, we will simulate the ADC load that the sensor will see and take measurements accordingly.

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The testing procedure will be carried out as follows after the circuit has been built: 1. The DC power supply will be connected to the input of the sensor and set to the highest available voltage of 30 V. 2. Using the digital multimeter the input and output of the circuit will be measured. 3. Using the measured input and output voltages, the voltage divider ratio will be verified to be the expected design ratio of 0.0059 within expected tolerances. 4. The function generator will replace the DC power supply as the input to the sensor and will be set to a sinusoidal wave at 20 V peak to peak at an initial frequency of 60 Hz. 5. At 60 Hz we will use the digital multimeter to measure the current drawn from the function generator and the current that flows through the simulated load. Using the measured values, we will find a ratio of input to output current. This calculated ratio will be compared to the ratio from the simulated circuit with the added ADC simulated load. 6. The oscilloscope will then be hooked up to the sensor circuit to allow measurements of the input and output waveforms. 7. While measuring the voltage gain and phase difference between the input and output waveforms on the oscilloscope, the function generator will be swept through various frequencies from 10 Hz to 15 kHz. This data will be used to determine the frequency response of the circuit. 8. After the frequency response has been determined from the circuit, it will be verified to be the expected frequency response as seen in the simulation within an acceptable range due to component tolerances.

Given that the measured parameters of the sensing circuit are the expected design values with expected tolerances, the breadboard with the circuit will be put aside until it needs to be used for testing with other modules of the project. If the measured parameters heavily deviate from the design parameters, then the circuit will be reanalyzed and adjusted to the desired specifications. 5.1.2 Current Transformer Testing Before moving onto testing the design of the current sensor circuit, we need to verify the specifications of the current transformer. At the moment this paper is being written, we are still looking into any available equipment that will allow us to properly test the current transformer. What is needed is ideally a sinusoidal current source or a sinusoidal voltage source that can deliver at least 100 mA of current and allows us to sweep the frequency of the source from about 10 Hz to at least 5 kHz. If we try to use a voltage source we will also need a low resistance power resistor that will need to withstand the high power dissipation needed when creating a circuit with a current of at least 100 mA from a voltage source. Once we are able to obtain a variable frequency current source of at least 100 mA, we can

104 begin testing the current transformer. Other than the current signal needed we will most likely use a digital multimeter that can safely measure high current and an oscilloscope to measure the voltage across the burden resistor.

As previously stated, we are testing the current transformer to verify certain specifications that are significant to the functionality of the project. During this test we are going to verify the turn ratio of the current transformer and we are going to verify what the applicable frequency means in the datasheet. In the datasheet the applicable frequency specification is given as just the numbers 10 Hz to 5 kHz. What we need to determine is the magnitude and phase response within that bandwidth because the information in the datasheet does not give much more information than the values of 10 Hz to 5 kHz.

The following test procedures are subject to slight changes when the equipment needed to perform this test are found, but the general objective of the steps will essentially be the same. Once we find the equipment that allows us to perform this test, the testing procedure will be carried out as follows: 1. Set the source signal to 60 Hz and verify that the AC current flowing is at least 100 mA using a digital multimeter. 2. Before placing the wire with the AC current in the core of the current transformer, place the burden resistor across the output terminals of the current transformer. Make sure to measure the resistance of the resistor for accurate calculations when calculating the current across the resistor from the measured voltage across the resistor. 3. Now place the wire with the current of at least 100 mA in the current transformer. 4. Verify that the turn ratio is 3000:1 given the measured AC current at the primary and the calculated current at the secondary of the current transformer. 5. Sweep the frequency of the source signal from 10 Hz to 5 kHz and record the frequency response of the current transformer.

This test will be done on each of the current transformers that will be used for the project to determine if a current transformer is uncharacteristically deviating from the specifications or if the specifications are not consistently accurate. Once this test is done, we will be able to adjust the rest of the project given that the current transformers do not perform terribly. The project modifications that will result from this test are any gain or phase compensations needed for certain frequency components to achieve more accurate results or a complete current sensor redesign if they are too unreliable. 5.1.3 Current Sensor Testing After testing the current transformer, we can test the current sensor circuit and verify that the design requirements of the sensor are all met. Since we verified the

105 turn ratio of the current transformer in the transformer’s separate series of tests, we are going to verify the magnitude and possibly the phase response of the circuit. We will also determine the ratio of current across the burden resistor and across the simulated ADC load. We will also perform some test to try to better understand the functionality of the ESD system consisting of high-speed switching diodes and a TVS diode.

The equipment that will be used for the testing of the current sensor consist of the current source used for the current transformer’s test, an oscilloscope, a digital multimeter, a DC power supply, a breadboard to prototype the circuit upon, and the necessary components needed to realize the circuit. The components used will be through-hole components with comparable specs.

The testing procedure will be carried out as follows after the circuit has been built, given we are able to find a current source sufficient to supply the current needed at the primary of the current transformer: 1. The DC power supply will be connected to the array of diodes used for ESD with a supply of 3 V. 2. The current signal used will be set to 10 Hz and a minimum of 100 mA. If a voltage source is used, the resistor used to obtain the specific current will be measured to accurately calculate the current from the measured voltage source waveform. 3. Before placing the wire carrying the current signal in the current transformer, the burden resistor needs to be measured to accurately calculate the current from the measured voltage across the simulated ADC load. 4. Using the oscilloscope, the voltage across the simulated load will be measured and if a voltage source is used to generate our current signal, we will also measure the voltage source on the oscilloscope. 5. While sweeping the frequency from 10 Hz to 15 kHz, a record of the current signal and output voltage will be kept and the phase difference between the source and output if possible. 6. Once the frequency sweep is finished, the output will be related to the input via current or voltage and the magnitude response will be determined. 7. Now the current signal will be set to 60 Hz and the current through the simulated load and burden resistor will be measured. The ratio of current through the burden resistor and simulated load will be compared to the ratio seen in the simulation. 8. The DC power supply will now replace the current signal and will initially be set to 0 V. 9. Using the digital multimeter, the current through the simulated load, the diode array, and voltage source will be monitored.

106 10. The DC voltage source will be swept through the voltages -30 V to 30 V and the currents at the specified nodes will be measured. After collecting all of the data for the DC sweep, it needs to be verified that the current through the simulated load will not exceed 10 mA. 11. Steps 9 and 10 will be repeated with the current signal. The current signal will be kept at 60 Hz and its amplitude will slowly be increased. The currents and voltages across the burden resistor, diode array, and the simulated load will be monitored during the current amplitude changes.

Given that the frequency response of the current sensing circuit is as expected compared to the design values, the current ratio between the input and output are as expected, and the diode array limits the current through the simulated ADC load to less than 10 mA, the breadboard with the circuit will be put aside until it needs to be used for testing with other modules of the project. If the measured parameters heavily deviate from the design parameters, then the circuit will be reanalyzed and adjusted to meet the desired specifications. 5.1.4 Touch Screen Testing Objective: The objective for this test is to ensure LCD is set up properly in order to receive information and display it on screen.

Supplies: • MCU • LCD with Controller • Circuit Board • Power Supply

Preparation: Connect the MCU to the LCD and the Controller on the circuit board and add the power supply.

Procedure: After uploading a test code to the MCU, the code should run and send information, of our choice, to the LCD to be displayed.

Expected Results: Whatever test code we create should command the LCD to print on screen.

Test Name: Capacitive Touch LCD Touch Sensing

Objective: The objective for this test is to ensure LCD is set up properly in order to respond and act accordingly to the response of a finger’s touch.

Supplies: • MCU • LCD with Controller

107 • Circuit Board • Power Supply

Preparation: Connect the MCU to the LCD and the Controller on the circuit board and add the power supply.

Procedure: Continuing after the last LCD test for display, another test code should be uploaded that is focused more towards sensing an individual’s touch and reacting to it. Expected Results: Whatever test code we create should command the LCD to react to the user’s touch, by moving forward or back in a system of sub-menus.

For the purposes of testing, the HAQS shall employ the use of the Capacitive touch Panel with Controller GSL 1680, which is shown below in Figure 49.

Figure 49: Capacitive Touchscreen Panel

This will allow the team to analyze the performance of the Capacitive Touch Panel and Controller, particularly for the purposes of HAQS. The Capacitive Touch Panel and Controller used in testing will not be used in the final product, however, the LCD that our team does purchase will come with a fresh version of the same Capacitive Touch Panel and Controller.

The controller will first be supplied a power voltage ranging from 1.8 to 3.3 volts. The controller then needs to drop the VDD below 1.6 volts to initiate the Power On Reset to get the capacitive sensor ready. The Shutdown mode will be tested by pulling the Shutdown pin low, which will put the controller into a “deep sleep” mode and consume the least amount of power. The four modes of operation will each be

108 tested based on their respected current draw as well. Shutdown mode will use less than 30 uA, Green Mode will use less than 3mA, Low Scan Speed will use less than 6 mA, and Active Mode will use less than 9 mA.

The GSL 1680 controller, seen in Figure 50, below, will make use of the ZIF connector that comes with it to better connect the LCD’s capacitive screen to the MCU.

Figure 50: ZIF Connector for GSL Controller

5.1.5 Analog-to-Digital Converter Testing For the purposes of testing, the HAQS shall employ the use of the Texas Instruments ADS131E08EVM-PDK Evaluation Module, which is shown in Figure 51 below.

Figure 51: ADS131E08EVM-PDK Evaluation Module Reprinted with permission from Texas Instruments

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This will allow the team to analyze the performance of the ADC, particularly for the purposes of HAQS. The Evaluation Module will not be used in the final product, however, as that board will be designed by the team’s own efforts.

Testing the ADC shall begin with verifying the voltage signals in accordance with Table 37 below [56].

Table 37: Test Points and Respective Voltages Test Point Voltage TP4 -4.96 V TP5 +3.0 V TP6 -2.5 V TP7 +5.0 V TP8 GND (0 V) TP9 +1.8 V TP10 +3.3 V TP13 +2.5 V

Note that the pins designated are relative to the Evaluation Module and will, therefore, need to be transposed to the board designed by the team.

Furthermore, the hardware on the Evaluation Module requires slight modification before testing can begin. Since the Module is stock configured for a bipolar AVDD of ±2.5 V, the jumpers must be configured in the manner depicted in Table 38, Table 39, and Table 40 for the power scheme discussed in the Analog-to-Digital Converter Design section [56].

Table 38: Configurations for +3.0 V Unipolar Analog Supply Jumper Configuration JP1 2-3 JP7 1-2 U6 3.0 V

Table 39: Configuration for +1.8 V Digital Display Jumper Configuration JP1 2-3 JP7 1-2 U6 1.8 V

Finally, using the internal voltage reference requires the following jumper configuration:

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Table 40: Configuration for Utilization of 2.5 V Vref Jumper Configuration JP2 Remove JP12 N/A

Once the above voltages and hardware configurations have been tested and verified, a function generator shall be used to interface with the input blocks J5 – J12. The software provided by TI and outlined in the Performance Demonstration Kit for the ADS131E08 [56] shall be used to test the digitization of the various input signals. This will also allow the team to test communication and data retrieval.

The Test and Analysis software will allow us to examine the following: • Scope • Histogram • Fast-Fourier Transformer

The Scope tool allows the user to view the input data in the time domain and examine a detailed report of the data conversion to verify that the digitization meets expectations and requirements. The use of the Waveform Examination tool allows the user to view one or all of the channels. This will be important for HAQS, as the ADC will be interfacing with six different input waveforms (three voltages, three currents). We must verify that the channels do not interfere with each other, and having the ability to individually examine each input will be valuable in verifying signal integrity [56].

The Histogram tool creates a histogram of the data generated by each channel. The valuable aspect of this tool is the details provided by the Histogram Analysis, which allows the user to view the RMS and peak voltages of the input, among other things. The RMS and peak voltages will be beneficial checks to ensure that the values provided are what is expected based on the input. For example, if the goal is to reduce the mains output to ±1 V, the RMS voltage is expected to be 0.707 V. Comparing the expected values for the peak and RMS voltages is simply another level of verification that can be utilized to ensure system functionality [56].

The Fast-Fourier Transformer (FFT) tool allows the user to view the input in the frequency domain. Digging deeper in the FFT Analysis tool will provide the user with information regarding the SNR, THD, and the harmonic information of the input. The whole purpose of HAQS is to provide this information to the end user; therefore, having it available as early in the system chain as the ADC is valuable as a reference to the end output. If the FFT information generated by the ADC is similar (ideally, identical) to what the MCU provides, we know that signal integrity has been maintained and that the analysis of the signal was successful [56].

111 The ADC shall be tested with the following input waveforms: • 2 Vpp, 60 Hz Sine wave • 2 Vpp, 60 Hz Square wave • 2 Vpp, 60 Hz Ramp wave

Output data shall be collected and saved into a Test Report and compared to the expected results.

ADC testing shall conclude with verifying the ability to communicate with the MCU. The digitized output shall be sent to the MCU for processing, where we will verify that the data was sent and processed without compromising the integrity of the signal. 5.1.6 Power Supply Unit Testing The PSU shall be tested in accordance with the voltage and current needs of the system in a systematic, step-by-step method that confirms each step is working as expected before connecting the next component. The expected values are provided between steps to check the results throughout the process.

Before manufacturing a PCB for the PSU, the design will be tested on a breadboard in the UCF Senior Design laboratory. The circuit will be set up as described in the PSU Design section and critical measurements will be made at the outputs of each of the three regulators. After concluding that the design is operable and correct, the PCB will be generated and sent to a manufacturer.

The testing procedure shall proceed as follows: 1. The PFC circuit, which include rectification and AC to DC conversion, will be assembled and tested. The output is expected to be 24 VDC. 2. The output of the PFC shall be measured with a DMM and Oscilloscope to verify the output voltage and current. a. Current must be measured to evaluate the effectiveness of the PFC. The whole purpose of including the PFC is to condition the current to behave similarly to the voltage waveform. This will be verified during prototype testing and after manufacturing and board population. b. If a DMM or Oscilloscope that can handle the transformer’s output cannot be found, then a simple resistive voltage divider circuit will be to reduce the voltage to a level that the equipment can handle. c. Special care will be taken to measure the component values to enhance the precision of calculations of expected results. Component values will be measured and recorded. Only components that comply to the expected tolerances and values will be used. 3. The smoothing capacitors and appropriate load resistor shall be added to test the AC to DC conversion, pre-regulator. The concern at this stage is

112 ensuring that the ripple is minimized and that the approximated DC signal is close to the projected value in the design phase. This is important in ensuring proper operation of the voltage regulator, as the design was created with specific input ranges in mind. 4. The expected output is 24 VDC with 0.3 Vripple and a load current of 150 mA. 5. Excess ripple can be smoothed by adding capacitance. 6. A series of filtering capacitors shall be added along with the voltage regulators. The circuits depicted in the PSU Design section shall be constructed and implemented into the system at this stage. 7. The expected outputs from the regulators are the following: a. 5.0 V b. 3.0 V c. 1.8 V

To reiterate and concentrate the important details for PSU testing, refer back to Figure 30. 5.1.7 File System Testing The process for testing the file system will be simple, but will require the use of a personal computer multiple times. To begin, we will make a new file following the comma-separated value format. This will allow us to easily store results of the harmonic analysis in a table structure that can then be viewed in practically any piece of software that reads spreadsheets such as Microsoft Excel. The personal computer used must have its own SD card reader drive for saving the created file to the SD card that will be used in the device.

Once the file is saved to the SD card, it can be removed and inserted into the SD card reader BoosterPack mounted on the prototype LaunchPad. The BoosterPack should flash its LED on the card detection signal when the card is inserted, a signal that is required by SD card standards. This will ensure that the SD card reader is sending the correct signals and is powered from the LaunchPad adequately. The next step of testing is to either perform a fake sample so data can be produced or simply write some data to the SD card programmatically. If a fake sample is taken, a bit more of the system will be exercised that is not directly under testing so this will more closely resemble an integration test as opposed to the planned file system unit test. Simply writing data to the SD card reader will require writing software that will not be present in the final design, although it will not be long nor will it stray further from the desired unit test.

Once some data is written to the SD card in the CSV format, it can be tested and confirmed. The SD card should be removed and then reinserted into the SD card reader drive on the personal computer used previously. The file can be opened in any compatible software such as Microsoft Excel or Notepad. The file should contain data that was not previously on it from when it was first created. This will

113 confirm that the SD card reader is communicating to the microcontroller correctly and its software appropriately formats the data written to the SD card.

The file system should now be tested to confirm that it reads data correctly. This will require that the LCD is properly configured on the prototype so it will resemble an integration test with the software controlling displays on the LCD. Once the SD card is inserted into a personal computer’s SD card reader drive, the file contained within the SD card should be edited to contain at least one line of data. This data should be 52 numbers separated by commas on one line, the 51 values for harmonic content and a final percentage of total harmonic distortion.

The SD card should be removed from the personal computer’s drive and inserted into the SD card reader BoosterPack on the prototype. The final design’s software should provide the functionality to view the results of the last sample taken by reading it from the SD card. This functionality should be tested by powering on the device and then determining if data resembling the values written to the file from the PC is displayed before another sample is taken and displayed in its place. This should finalize the testing necessary to ensure the file system correctly reads and formats data to be stored on the SD card through the reader BoosterPack. 5.1.8 Harmonic Analysis of Multiple Waveforms The primary functionality of our final design will be to perform a harmonic analysis of a three-phase source by calculating the total harmonic content of the signals. This can be boiled down to a more relaxed model for testing by performing an analysis on one source. For an accurate test, the source should be modeled after an example of which we know its harmonic content and Fourier transformation. A function generator can be set to send a sinusoid and connected to the necessary inputs to be sampled by the ADC unit. The purpose of this test will be to exercise the software written in the microcontroller for performing the necessary transforms and statistical calculations. This test will be a large integration test, as it requires the use of many components within the system like the LCD screen, the ADC unit and the microcontroller itself along with the necessary software for communication.

The microcontroller should be signaled to perform a sampling operation through the LCD screen’s touch interface. This should make the ADC perform a sample from the function generator’s sinusoid output. If the software is written correctly and communication between the microcontroller unit and the ADC unit is performed properly, the microcontroller should produce a result. The result should appear on the LCD in the form of a bar graph representing harmonic content at the different harmonics and a percentage of total harmonic distortion. The results displayed should be compared to the known and expected results for the sinusoid. This is practically all needed to test this high level integration process.

114 Additional waveforms should be tested in a similar manner. Standard waveforms such as a square or triangle waveform should be generated from the function generator hooked up to the inputs of the ADC unit. The results of these waveforms should be similarly compared to their expected harmonic distribution. Waveforms with induced harmonics, potentially from non-linear components, should be produced for testing as well. These induced harmonics should be simulated accurately in software that can provide a Fourier transform of the signal so the microcontroller’s results can be compared. 5.1.9 Total Harmonic Distortion Accuracy Verification After the project is complete and the meter is able take harmonic measurements, we will verify the accuracy of the THD that the meter reports. To verify the accuracy of the reported THD, a couple methods are being looked into and will be discussed. Other methods of verification are still being researched and we will most likely use multiple researched verification methods to record consistent results that show our meter’s accuracy.

The first method that may be used will require equipment available in the senior design lab and whatever setup was discovered to give us as an AC current source. The first mentioned method to verify the THD accuracy of the meter is quite simple. For the voltage harmonic measurements, we would setup the input to the sensors to be a signal whose spectral content is known. Two waveforms that would be used are the square wave and the triangular wave. Given we have the same waveform options for our AC current source, we would also setup the input to the current sensors to be the same waveforms used for the voltage sensors.

After the harmonic data is collected with the square, triangular, and any other input waveforms we decided to test with, we will simply compare the measured harmonic content and THD to the already known ideal values for the simple waveforms. If we find that the meter is highly inaccurate, we would not continue to verify its accuracy with subsequent tests. In the event that the meter is highly inaccurate, we will determine what is causing the incorrect measurements and redesign, or simply adjust, the meter to record more accurate data.

The second method that may be used to verify the accuracy of the THD that the meter reports, is to use another meter that can take harmonic measurements of the three-phase power source. According to the application report of TI’s High Accuracy Three-Phase Electricity Meter with Tamper Detection, the software library used for the meter supports harmonic analysis [61]. Although this meter exceeds Class 0.2 accuracy requirements from both ANSI and IEC, there are no specifications given for the accuracy of the harmonics that will be measured by this meter [62]. Thus if we decided to use this meter to compare the THD measured by our project, we would have to first determine the accuracy of TI’s reference meter.

115 If we find a meter that UCF owns that can measure the THD of the three-phase source with given harmonic accuracy specifications, it may be used instead of the TI meter to eliminate the need to determine the accuracy of two meters. 5.2 Field Testing Once smaller unit tests are performed on specific components and integration tests between these components are passed, we can move on to field testing the completed prototype device. This testing will exercise all components and their connections to ensure that the expected functionality is provided: that being a harmonic analysis of a three-phase source using a statistic of total harmonic distortion.

Before we begin the testing of the completed project, we need to select appliances that will be used to create loads for individual phases of the three-phase source. The source available for testing is in a somewhat isolated room where the source is used specifically for the robotics division of UCF. When selecting the appliances that will be used for the system loads we knew that the load must draw at least 100 mA to be within the specified primary rating of the current transformer. We also decided to pick appliances that would constantly draw power so we do not have to worry about the appliance going into a low-power or sleep state thus causing current dropping below the rated primary current of the current transformer. Assuming an ideal voltage source of 120 VRMS, we searched for appliances that drew at least 17 W of power.

The appliances picked for the system load were a vacuum cleaner, a hair dryer, and a crockpot. The vacuum cleaner that will be used is made by Eureka, is specified to work with a 60 Hz 120 V AC source, and is not given a power specification but a 12.0 A current draw specification which is more than sufficient for our test. The hair dryer that will be used is made by Conair and is specified to have a power draw of 1900 W, which is more than the minimum desired power use of 17 W. The slow cooker that will be used for the third system load is made by Rival and is specified to have a power draw of 190 W, which is also more than the minimum desired power use of 17 W

The first step in testing the final prototype device will be to determine whether the power drawn is accurate enough and the current of each phase will be sufficient for our project’s current transformers. To determine whether the power drawn is sufficient we will use TI’s High Accuracy Three-Phase Electricity Meter with Tamper Detection to measure the power drawn from each phase of the three- phase power source. Given the meter verifies the power usage of the appliances, we will continue onto testing our device.

Once we have determined that the loads are sufficient, the testing of the final project will occur as follows:

116 1. The meter will be setup, powered on, and will be prepared for taking measurements. 2. The appliances will be turned on after the meter is prepared. 3. Once the loads to the three phases are drawing power, we will begin to take samples of voltages or currents. 4. Once the meter is finished taking samples the meter will analyze the samples and determine the harmonic levels. The user can then save the data to the SD card and keep taking measurements or view the harmonic data that was just analyzed 6 Product Operation To operate the device, the following steps should be adhered to for expected operation: • Locate the power source to be analyzed • Ensure that the meter is plugged into a source to power itself • Connect the attached current sensor clamps to the source to be analyzed • Feed the source to be analyzed into the voltage sensing input

At this stage, the last analysis performed will be displayed on the LCD screen if a removable SD card is present in the SD card reader on the device. Several options are available for the user here: • Press the sample button displayed on the touch capacitive LCD screen to perform a new analysis • This will display new harmonic content and save it to any available SD card • Press the left or right buttons to scroll between harmonic content from the last analysis

Once data is stored on the removable SD card, it can be reviewed using any device with its own SD card reader and compatibility with .csv file formats. Applications like Microsoft Excel can open the file saved on the SD card used by the device 7 Administrative Content The topics falling under the Administrative Content section will be used to fully define, assign, and explain everything related to our group that also doesn’t apply directly to design, research, or prototyping of the project.

The Roles and Responsibilities section will clearly state what each group member worked on and how they overall contributed to the project and the paper that accompanied it.

The Consultants and Advisors section of the paper will clearly state who assisted in this project. It will state who our sponsors were, if any, and it will give credit to everyone our group has ever contacted for assistance on this project.

117

The Milestones section of the paper will clearly state our groups overall timeline and goals we had set at the beginning of the semester for the project.

The Bill of Materials section of the paper will be dedicated to listing every individual part that was purchased and the cost of each piece. This section will give the reader a general understanding of how much it would cost to fully construct this device, and will be listed in a neat tabular format. 7.1 Roles and Responsibilities Brian’s primary role for our project was anything related to the ADC and supplying power to the many different sub systems. He is also in charge of writing about everything related to those topics for this paper. Brian also operated as back up for anything involving the LCD. He also served as documentarian.

Kevin’s primary role for our project was anything related to the three-phase step down from the mains power supply to the ADC. He is also in charge of writing about everything related to those topics for this paper as well as some of the odds and ends that don’t directly apply to a specific group member. Kevin also operated as back up for anything involving the MCU, the DC step down for the power supply, as well as the LCD’s user interface.

Louis’ primary role for our project was anything related to the MCU and the SD card reader, as well as, any software or coding related sections. He is also in charge of writing about everything related to those topics for this paper. Louis also operated as back up for the LCD’s user interface.

Nick’s primary role for our project was anything related the LCD and the user’s interface. He is also in charge of writing about everything related to those topics as well as most of the odds and ends that don’t directly apply to a specific group member. Nick also operated as back up for anything involving the ADC and the AC step down from the mains power supply to the ADC. 7.2 Facilities and Equipment In order to properly test and eventually demonstrate the operation of HAQS, the team will require access to a three-phase outlet, which can be found at the University of Central Florida in Engineering I, room 364 (ENG1 364).

During the prototyping, construction, and testing phases, the team will require the oscilloscopes, power supplies, multimeters, and function generators provided by the University of Central Florida in the Senior Design Lab, which can be found in Engineering I, room 456 (ENG1 456).

118 7.3 Consultants and Advisors This project was made possible thanks to our advisors, mentors, sponsors, and consultants:

Sponsor: Texas instruments

Advisor: Dr. Samuel Richie Dr. Chung Yung Chan

Mentor: Dr. Chung Yung Chan

Consultants: Dr. Samuel Richie Dr. Chung Yung Chan Robert M Reedy, P.E. 7.4 Milestones Our group set out some milestones for this project to be completed in the coming semesters of Senior Design 1 and Senior Design 2. We were taught that the basic outline of a project’s life cycle was Definition, Research, Design, Prototype, and Testing. Each section connects with all the others because the project is continually being redefined as the group continues to learn. The basic steps of the engineer process are outlined in Figure 52.

Figure 52: The Engineering Process

119 [Senior Design 1]

Week 1-2 – Group Formation

[Definition]

Week 2 -- Finalize Block Diagram, and complete the Divide and Conquer section Week 3 -- Complete the Initial Document

[Research]

Week 2-6 -- Complete individual research

[Design]

Week 9-12 – Design process

[Write Up]

Week 9-12 – Finish Senior Design 1 Paper

[Senior Design 2]

Week 1 -- Acquire hardware

[Prototype]

Week 2 -- Design and purchase PCBs Week 3-6 -- Complete prototype

[Testing]

Prototype Revisions -- Depends on the revision 7.5 Bill of Materials Below are several Bill of Materials tables. The items chosen and placed into this list are temporary, as they are based on the design ideas as they currently stand. These design ideas themselves are also subject to change. The tables will relate to specific components of the system, rather having one table with the components needed for the whole system.

Note that the numbers in the Quantity column indicate the number required. The number purchased will be 2 to 3 times the number required in order to compensate

120 for broken, misplaced, or malfunctioning equipment, as well as for prototyping efforts. Table 41: Analog-to-Digital Converter PCB BoM Part Number Manufacturer Description Qty CAP CER 1UF 25V 10% GRM188R61E105KA12D Murata X5R 0603 15 CAP CER 22UF 6.3V 10% JMK212BJ226KG-T Taiyo Yuden X5R 0805 1 CAP CER 10UF 10V 10% GRM219R61A106KE44D Murata X5R 0805 11 CAP CER 0.1UF 50V 10% GRM188R71H104KA93D Murata X7R 0603 10 CAP CER 2.2UF 6.3V 10% GRM185R60J225KE26D Murata X5R 0603 4 CAP CER 100UF 10V 20% LMK325BJ107MM-T Taiyo Yuden X5R 1210 2 10 Pin, Dual Row, SM TSM-110-01-T-DV-P Samtec Header (20 Pos.) 1 10 Pin, Dual Row, SM SSW-110-22-F-D-VS-K Samtec Header (20 Pos.) 1 5 Pin, Dual Row, SM Header SSW-105-22-F-D-VS-K Samtec (10 Pos.) 1 TERMINAL BLOCK 3.5MM ED555/2DS On Shore 2POS PCB 8 3 Position Jumper _ .1" TSW-103-07-T-S Samtec spacing 8 2 Position Jumper _ .1" TSW-102-07-T-S Samtec spacing 2 FERRITE BEAD 470 OHM BK2125HM471-T Taiyo Yuden 0805 5 RES 0.0 OHM 1/10W 5% RC0603JR-070RL Yageo 0603 SMD 5 RES 10.0K OHM 1/10W 1% RC0603FR-0710KL Yageo 0603 SMD 20 RES 49.9K OHM 1/10W 1% RC0603FR-0749K9L Yageo 0603 SMD 1 RES 46.4K OHM 1/10W 1% RC0603FR-0746K4L Yageo 0603 SMD 1 RES 47.5K OHM 1/10W 1% RC0603FR-0747K5L Yageo 0603 SMD 1 RES 43.2K OHM 1/10W 1% RC0603FR-0743K2L Yageo 0603 SMD 1 TEST POINT PC MINI 5001 Keystone .040"D BLACK 5 TEST POINT PC MINI 5000 Keystone .040"D RED 11

121 Table 42: Analog-to-Digital Converter PCB BoM (continued) Part Number Manufacturer Description Qty 8-channel, 16bit Analog Front End for Power ADS131E08IPAG TI Control 1 IC UNREG CHRG PUMP TPS60403DBVT TI V INV SOT23-5 1 IC LDO REG 250MA 3.0V TPS73230DBVT TI SOT23-5 1 C LDO REG NEG 200MA TPS72301DBVT TI ADJ SOT23-5 1 IC LDO REG 250MA ADJ- TPS73201DBVT TI V SOT23-5 1 IC EEPROM 256KBIT 24AA256-I/ST Microchip 400KHZ 8TSSOP 1 OSC 2.0480 MHZ 3.3V FXO-HC735-2.048 Fox HCMOS SMT 1 0.100 Shunt - Black 969102-0000-DA 3M Shunts 9

Table 43: LM46001 5.0 VDC Regulator BoM Part Number Manufacturer Description Qty CAP CER 27PF 50V C0805C270J5GACTU Kemet NP0 0805 1 CAP CER 4.7UF 10V GRM21BR71A475KA73L MuRata X7R 0805 1 CAP CER 0.47UF 6.3V GRM155C80J474KE19D MuRata X6S 0402 1 CAP CER 4.7UF 50V GRM32ER71H475KA88L MuRata X7R 1210 1 CAP CER 1UF 50V GRM31MR71H105KA88L MuRata X7R 1206 1 CAP CER 47UF 10V GRM31CR61A476KE15L MuRata X5R 1206 1 CAP CER 2.2UF 6.3V GRM188R60J225KE19D MuRata X5R 0603 1 FIXED IND 33UH 1.4A SRN6045-330M Bourns 188 MOHM SMD 1 RES SMD 255K OHM CRCW0402255KFKED Vishay-Dale 1% 1/16W 0402 1 RES SMD 1M OHM 1% CRCW04021M00FKED Vishay-Dale 1/16W 0402 1 Texas IC REG BUCK ADJ 1A LM46001PWPR Instruments SYNC 16HTSSOP 1

122 Table 44: LM20133 3.0 VDC Regulator BoM Part Number Manufacturer Description Qty CAP CER 0.1UF 25V GRM21BR71E104KA01L MuRata X7R 0805 1 CAP CER 10000PF GRM216R71H103KA01D MuRata 50V X7R 0805 1 CAP CER 1UF 25V C2012X7R1E105K TDK X7R 0805 1 CAP CER 22UF 16V GRM32ER61C226KE20L MuRata X5R 1210 1 CAP CER 10UF 6.3V GRM219R60J106KE19D MuRata X5R 0805 2 CAP CER 6800PF 50V CC0805KRX7R9BB682 Yageo America X7R 0805 1 Fixed Inductors XAL4030 High Current XAL4030-332MEB Coilcraft 3.3 uH 20 % 6.6 A 1 RES SMD 1 OHM 1% CRCW04021R00FKED Vishay-Dale 1/16W 0402 1 RES SMD 1.74K OHM CRCW04021K74FKED Vishay-Dale 1% 1/16W 0402 1 RES SMD 12K OHM RC0603FR-0712KL Yageo America 1% 1/10W 0603 1 RES SMD 33K OHM RC0603FR-0733KL Yageo America 1% 1/10W 0603 1 RES SMD 48.7K OHM CRCW040248K7FKED Vishay-Dale 1% 1/16W 0402 1 Texas IC REG BUCK ADJ 3A LM20133MH/NOPB Instruments SYNC 16TSSOP 1

Table 45: LM20133 1.8 VDC Regulator BoM Part Number Manufacturer Description Qty CAP CER 0.1UF 25V GRM21BR71E104KA01L MuRata X7R 0805 1 CAP CER 10000PF 50V GRM216R71H103KA01D MuRata X7R 0805 1 CAP CER 1UF 25V X7R C2012X7R1E105K TDK 0805 1 CAP CER 22UF 6.3V C3216X5R0J226K TDK X5R 1206 1 CAP CER 22UF 4V X6S GRM21BC80G226ME39L MuRata 0805 1 CAP CER 6800PF 50V CC0805KRX7R9BB682 Yageo America X7R 0805 1

123 Table 46: LM20133 1.8 VDC Regulator BoM (continued) Part Number Manufacturer Description Qty Fixed Inductors XAL4030 High Current XAL4030-332MEB Coilcraft 3.3 uH 20 % 6.6 A 1 RES SMD 1 OHM 1% CRCW04021R00FKED Vishay-Dale 1/16W 0402 1 RES SMD 1.27K OHM CRCW04021K27FKED Vishay-Dale 1% 1/16W 0402 1 RES SMD 12K OHM 1% RC0603FR-0712KL Yageo America 1/10W 0603 1 RES SMD 15K OHM 1% CRCW040215K0FKED Vishay-Dale 1/16W 0402 1 CRCW040248K7FKED Vishay-Dale CRCW040248K7FKED 1 Texas IC REG BUCK ADJ 3A LM20133MH/NOPB Instruments SYNC 16TSSOP 1

Table 47: Voltage Sensor BoM Part Number Manufacturer Description Qty RT0603BRD075K9L Yageo RES SMD 5.9K OHM 3 0.1% 1/10W 0603 RT0805BRD07332KL Yageo RES SMD 332K OHM 9 0.1% 1/8W 0805 RT0805BRD071KL Yageo RES SMD 1K OHM 0.1% 6 1/8W 0805 GRM1885C1H152FA01D Murata CAP CER 1500PF 50V 3 NP0 0603 GRM1555C1H151FA01D Murata CAP CER 150PF 50V 6 NP0 0402 FBMJ3216HS480NT Taiyo Yuden FERRITE BEAD 48 OHM 6 1206 S20K230 EPCOS (TDK) VARISTOR 324V 8KA 3 DISC 20MM

Table 48: SD Card BoM Part Number Manufacturer Description Qty DEV-MSP-SDCARD- 43oh SD Card BoosterPack 1 BOOST COMP-SDCARD-CONN 43oh SD Card Push Pull 1 Socket

124 Table 49: MCU BoM Part Number Manufacturer Description Qty MSP-EXP432P401R TI MSP432 LaunchPad 1 MSP432P401R TI MSP432 microcontroller 1

Table 50: Current Sensor BoM Part Number Manufacturer Description Qty C-CT-10 Copal AC CURRENT SENSOR, 4 Electronics 10MM HOLE RT0603BRD0757R6L Yageo RES SMD 57.6 OHM 4 0.1% 1/10W 0603 RT0805BRD071KL Yageo RES SMD 1K OHM 0.1% 8 1/8W 0805 GRM2195C1H562FA01D Murata CAP CER 5600PF 50V 4 NP0 0805 08055A561FAT2A AVX CAP CER 560PF 50V 8 NP0 0805 PMLL4148L,115 NXP DIODE GEN PURP 75V 32 Semiconductors 200MA LLDS SMAJ5.0CA Bourns TVS DIODE 5VWM 4 9.2VC DO214AC RC0603JR-070RL Yageo RES SMD 0.0OHM 8 JUMPER 1/10W 0603

Table 51: 5” LCD with Capacitive Touch Screen

Part Number Manufacturer Description Qty

ER-TFTM050-2 BuyDisplay 5” LCD 1 Controller with the Capacitive Touch GSL1680 BuyDisplay panel 1

125 Table 52: Power Factor Correction Circuit BoM Part Number Manufacturer Description Qty ECQ-U2A474ML Panasonic CAP FILM 0.47UF 20% 2 275VAC RAD ECQ-U2A334ML Panasonic CAP FILM 0.33UF 20% 1 275VAC RAD GRM43DR72J104KW01L MuRata CAP CER 0.1UF 630V X7R 2 1812 380LQ271M450K022 Cornerll Dubilier CAP ALUM 270UF 20% 1 450V SNAP GRM32ER70J476KE20L MuRata CAP CER 47UF 6.3V X7R 1 1210 08055C104JAT2A AVX CAP CER 0.1UF 50V X7R 3 0805 GRM21BR71H105KA12L MuRata CAP CER 1UF 50V X7R 2 0805 DE1E3KX102MA5BA01 MuRata CAP CER 1000PF 250V 1 RADIAL ECW-F6163JL Panasonic CAP FILM 0.016UF 5% 2 630VDC RAD ECW-H8123HA Panasonic CAP FILM 0.012UF 3% 2 800VDC RAD C0603C104K4RACTU Kemet CAP CER 0.1UF 16V X7R 2 0603 BFC233820473 Vishay- CAP FILM 0.047UF 20% 1 BcComponents 630VDC RAD UMK107AB7105KA-T Taiyo Yuden CAP CER 1UF 50V X7R 1 0603 APS-160ELL331MJC5S Nippon Chemi- CAP POLYMER 330UF 20% 2 Con 16V T/H EEU-FR1C102L Panasonic CAP ALUM 1000UF 20% 4 16V RADIAL GMK212B7105KG-T Taiyo Yuden CAP CER 1UF 35V X7R 1 0805 EKY-350ELL221MH15D Nippon Chemi- CAP ALUM 220UF 20% 35V 1 Con RADIAL 08055C473KAT2A AVX CAP CER 0.047UF 50V X7R 1 0805 06035C104KAT2A AVX CAP CER 0.1UF 50V X7R 2 0603 GMK316AB7106KL Taiyo Yuden CAP CER 10UF 35V X7R 2 1206 C0603C471K5RACTU Kemet CAP CER 470PF 50V X7R 3 0603 06033C104KAT2A TDK CAP CER 0.1UF 25V X7R 1 0603 C0603C102K5RACTU AVX CAP CER 1000PF 50V X7R 1 0603 CGA5L3X5R1H106K160AB AVX CAP CER 10UF 50V X5R 2 1206

126 Table 53: Power Factor Correction Circuit BoM (continued) Part Number Manufacturer Description Qty 06035A101FAT2A Kemet CAP CER 100PF 50V NP0 2 0603 06035A101FAT2A MuRata CAP CER 100PF 50V NP0 1 0603 C0603C103K5RACTU AVX CAP CER 10000PF 50V 1 X7R 0603 GRM1885C1E102JA01D Nichicon CAP CER 1000PF 25V NP0 0 0603 06035A470JAT2A Vishay- CAP CER 47PF 50V NP0 0 Semiconuctor 0603 UVR1V100MDD1TA Micro Commercial CAP ALUM 10UF 20% 35V 0 Components RADIAL 1N5406 Vishay- DIODE GEN PURP 600V 3A 1 Semiconuctor DO201AD GBU8J-BP Micro Commercial RECT BRIDGE GPP 8A 1 Components 600V GBU C3D04060A Cree DIODE SCHOTTKY 600V 1 4A TO220-2 IN4007 Fairchild DIODE GEN PURP 1KV 1A 1 Semiconductor DO41 ZLLS350TA Diodes Inc. DIODE SCHOTTKY 40V 1 380MA SOD523 BYG20J-E3/TR Vishay- DIODE AVALANCHE 600V 1 Semiconuctor 1.5A STPS40L45CT ST DIODE ARRAY SCHOTTKY 2 Microelectronics 45V TO220AB MMSZ5248B-7-F Diodes Inc. DIODE ZENER 18V 500MW 1 SOD123 BAV99,215 NXP DIODE ARRAY GP 100V 2 Semiconductors 215MA SOT23 BZX384-C12,115 NXP DIODE ZENER 12V 300MW 1 Semiconductors SOD323 DA2JF8100L Panasonic DIODE GEN PURP 800V 2 200MA SMINI2 BAS16-7-F Diodes Inc. DIODE GEN PURP 75V 1 200MA SOT23-3 BAS316,115 NXP DIODE GEN PURP 100V 2 Semiconductors 250MA SOD323 0216008.MXESPP Littelfuse FUSE CERAMIC 8A 1 250VAC 5X20MM 29311 Keystone MACHINE SCREW PAN 9 SLOTTED M3 4824 Keystone HEX STANDOFF 6-32 8 NYLON 1-1/2" 1903C Keystone HEX STANDOFF 6-32 8 NYLON 1/2"

127

Table 54: Power Factor Correction Circuit BoM (continued) Part Number Manufacturer Description Qty MAX01NG Aavid Technology MAX01NG 7

782653B04250G Aavid Technology HEAT SINK, CLIP, 3 ALUMINUM, ANODIZED ED120/3DS On-Shore TERMINAL BLOCK 5.08MM 2 Technology VERT 3POS ED120/4DS On-Shore TERMINAL BLOCK 5.08MM 1 Technology VERT 4POS PBC03SAAN Sullins Connector CONN HEADER .100 1 Solutions SINGL STR 3POS ED120/2DS On-Shore TERMINAL BLOCK 5.08MM 1 Technology VERT 2POS 5103308-1 TE Connectivity CONN HEADER LOPRO 1 STR 10POS GOLD 7448258022 Wurth Elektronik CHOKE TOROID 2.2MH 8A 1 eiSos VERTICA RLTI-1108 Renco Electronics Inductor, ?, , A, TH 1

75PR8106 Vitec Corporation Inductor, shielded, ?, 55 μH, 11 A, 0.065 Ω, TH IHLP6767GZER1R5M11 Vishay-Dale FIXED IND 1.5UH 48A 1.62 1 MOHM THT-14-423-10 Brady Thermal transfer printable 1 labels, 0.65 inch wide x 0.20 " HLMP1523 Everlight LED CBI 3MM 1POS 1 GREEN TH AOW25S65 AOS MOSFET N-CH 650V 25A 3 TO262 BSS126 H6906 Infineon MOSFET N-CH 600V 1 Technologies 0.021A SOT23 CRCW120610R0FKEA Vishay-Dale RES SMD 10 OHM 1% 1 1/4W 1206 CRCW20103R30JNEF Vishay-Dale RES SMD 3.3 OHM 5% 2 3/4W 2010 CRCW20101R00JNEF Vishay-Dale RES SMD 1 OHM 5% 3/4W 2 2010 CSRN2512FTR100 Stackpole RES SMD 0.1 OHM 1% 2W 3 Electronics Inc 2512 ERJ-1TRQF1R0U Panasonic RES SMD 1 OHM 1% 1W 3 2512 ERJ-8RQF3R3V Panasonic RES SMD 3.3 OHM 1% 2 1/4W 1206 CRCW120651R1FKEA Vishay-Dale RES SMD 51.1 OHM 1% 2 1/4W 1206 CRCW060310K0FKEA Vishay-Dale RES SMD 10K OHM 1% 5 1/10W 0603

128

Table 55: Power Factor Correction Circuit BoM (continued) Part Number Manufacturer Description Qty RC0603FR-0710ML Yageo America RES SMD 10M OHM 1% 1 1/10W 0603 CRCW06031M10FKEA Vishay-Dale RES SMD 1.1M OHM 1% 1 1/10W 0603 RR1220P-512-D Susumu Co Ltd RES SMD 5.1K OHM 0.5% 1 1/10W 0805 ERJ-8ENF49R9V Panasonic RES SMD 49.9 OHM 1% 1 1/4W 1206 RC0603FR-0718KL Yageo America RES SMD 18K OHM 1% 1 1/10W 0603 CRCW08050000Z0EA Vishay-Dale RES SMD 0.0 OHM 1 JUMPER 1/8W 0805 3006P-1-103LF Bourns TRIMMER 10K OHM 0.75W 14 PC PIN CRCW12060000Z0EA Vishay-Dale RES SMD 0.0 OHM 6 JUMPER 1/4W 1206 CRCW12063M09FKEA Vishay-Dale RES SMD 3.09M OHM 1% 3 1/4W 1206 CRCW120610M0FKEA Vishay-Dale RES SMD 10M OHM 1% 1 1/4W 1206 CRCW060375K0FKEA Vishay-Dale RES SMD 75K OHM 1% 1 1/10W 0603 CRCW06033M30JNEA Vishay-Dale RES SMD 3.3M OHM 5% 3 1/10W 0603 CRCW0603100KFKEA Vishay-Dale RES SMD 100K OHM 1% 2 1/10W 0603 RC0603FR-07470RL Yageo America RES SMD 470 OHM 1% 1 1/10W 0603 CRCW06032K21FKEA Vishay-Dale RES SMD 2.21K OHM 1% 1 1/10W 0603 CRCW06033K32FKEA Vishay-Dale RES SMD 3.32K OHM 1% 1 1/10W 0603 ERJ-6RQF1R0V Panasonic RES SMD 1 OHM 1% 1/8W 1 0805 CRCW08052R20JNEA Vishay-Dale RES SMD 2.2 OHM 5% 1 1/8W 0805 CRCW12060000Z0EA Vishay-Dale RES SMD 0.0 OHM 1 JUMPER 1/4W 1206 RC0603FR-075K1L Yageo America RES SMD 5.1K OHM 1% 0 1/10W 0603 CRCW0603100RFKEA Vishay-Dale RES SMD 100 OHM 1% 0 1/10W 0603 CRCW060339K2FKEA Vishay-Dale RES SMD 39.2K OHM 1% 0 1/10W 0603 CRCW12061K00FKEA Vishay-Dale RES SMD 1K OHM 1% 1 1/4W 1206

129

Table 56: Power Factor Correction Circuit BoM (continued) Part Number Manufacturer Description Qty CRCW06030000Z0EA Vishay-Dale RES SMD 0.0OHM 2 JUMPER 1/10W 0603 RC0603FR-071K2L Yageo America RES SMD 1.2K OHM 1% 1 1/10W 0603 CL-40 GE Sensing ICL 5 OHM 25% 6A 1 19.56MM SPC02SYAN Sullins Connector CONN JUMPER 2 Solutions SHORTING GOLD FLASH SP900S-0.009-00-114 Bergquist THERMAL PAD TO-220 8 Company .009" SP900 200USP9T1A1M2RE E-Switch SWITCH TOGGLE SPST 2 0.4VA 20V RLTI-1115 Renco Electronics LLC transformer, 280 μH, 1 TH 5014 Keystone TEST POINT PC MULTI 2 PURPOSE YEL 5012 Keystone TEST POINT PC MULTI 25 PURPOSE WHT 5006 Keystone TEST POINT PC COMPACT 3 .063"D BLK 5005 Keystone TEST POINT PC COMPACT 1 .063"D RED 5010 Keystone TEST POINT PC MULTI 1 PURPOSE RED 5011 Keystone TEST POINT PC MULTI 1 PURPOSE BLK ACPL-217-56AE Avago OPTOISOLATOR 3KV 1 TRANS 4SOIC UCC29950EVM-631 Texas Instruments UCC29950 Evaluation 1 Module UCC27511DBV Texas Instruments IC GATE DVR LOW SIDE 1 1CH SOT23-6 UCC27714D14 Texas Instruments High-Speed Low-Side Gate 1 Driver Device TL431AIDBZ Texas Instruments IC VREF SHUNT ADJ 1 SOT23-3 UCC29950D Texas Instruments IC PFC CTRLR BUCK 1 16SOIC TPS7A1601DGNT Texas Instruments IC REG LDO ADJ 0.1A 1 8MSOP B72207S2301K101 EPCOS Inc VARISTOR 423V 1.75KA 1 DISC 7MM

130 The estimated total cost of the system and its components is detailed in Table 57.

Table 57: Total Cost of BoM ADC $63 PFC + PSU $106 SD Card Interface $8 MCU $52 Voltage Sensor $12 Current Sensor $170 LCD Touchscreen $35 Total $445

The equipment listed in Table 58 was provided by TI for the purposes of prototyping, testing, and ultimately constructing the HAQS system.

Table 58: Equipment Provided by TI Part Number Description ADS131E08IPAG 8-channel, 16bit Analog Front End for Power Control IC UNREG CHRG PUMP V INV TPS60403DBVT SOT23-5 IC LDO REG 250MA 3.0V SOT23- TPS73230DBVT 5 C LDO REG NEG 200MA ADJ TPS72301DBVT SOT23-5 IC LDO REG 250MA ADJ-V TPS73201DBVT SOT23-5 LM46001PWPR IC REG BUCK ADJ 1A SYNC 16HTSSOP LM20133MH/NOPB IC REG BUCK ADJ 3A SYNC 16TSSOP MSP-EXP432P401R MSP432 LaunchPad MSP432P401R MSP432 Microcontroller UCC29950EVM-631 UCC29950 Evaluation Module UCC27511DBV IC GATE DVR LOW SIDE 1CH SOT23-6 UCC27714D14 High-Speed Low-Side Gate Driver Device TL431AIDBZ IC VREF SHUNT ADJ SOT23-3 UCC29950D IC PFC CTRLR BUCK 16SOIC TPS7A1601DGNT IC REG LDO ADJ 0.1A 8MSOP EVM430-F6779 THREE-PHASE METER EVALUATION MODULE

131

7.6 Funding This project is sponsored by Texas Instruments, which generously provided our team with any Texas Instruments components needed for the completion of this project. Any additional equipment or components needed were purchased using the team’s own money. 8 Design Summary The final design of the Harmonic Analysis for Quality of Service (HAQS) prototype is based on the research, calculations and simulations performed and explained in this report. The prototype of the total harmonic distortion analyzer will consist of components including the circuits for the AC step down, the DC step down, the power supply units, the analog-to-digital converter, microcontroller, the capacitive touch liquid crystal display, and the SD card reader.

The ADC that our group decided to go with is the ADS131E08 because it offers a sufficient number of differential inputs (8), and it makes use of Sigma-Delta analog- to-digital conversion. It has 24-bits for digitization, which will keep accuracy high and quantization noise low, as well as matching a supplied voltage to that of the other subsystems.

The MCU that our group decided to go with is the MSP432P401R because it is a low-power microcontroller with a sufficient number of communication and general I/O ports. It also offers special connectivity for the capacitive touchscreen, as well as matching a supplied voltage to that of the other subsystems.

The LCD that our group decided to go with is the five inch TFT LCD Module 800 x 480 Display and Capacitive Touch Panel with Controller GSL1680. The reason for this selection was that it required very few I2C pin connections and that it had increased compatibility with our previously selected MCU, as well as matching a supplied voltage to that of the other subsystems.

We went with an SD card booster pack, part number: DEV-MSP-SDCARD- BOOST, for ease of use to help us with testing and exporting data from the MCU to a removable media storage device.

132 9 Appendices 9.1 Appendix A – Copyright Permissions

Figure 53: Permission from Maxim Integrated

Figure 54: Permission from Texas Instruments

The relevant section is as follows in Figure 55

Figure 55: TI Academic Authorization

Figure 56: Permission from Vishay Intertechnology

Figure 57: Permission from MCCDAQ

Figure 58: Permission from Microchip

The relevant section is as follows in Figure 59.

Figure 59: Microchip Academic Authorization

Figure 60: Permission from Creative Commons

iii

Figure 61: Permission from Dakota Electric

Figure 62: Permission from Continental Control Systems

v 9.2 Appendix B – Fast Fourier Transform Software #include #include #include

/** * Good constant combinations: * 65536, 16384, 2048 * 16384, 8192, 1024 * 1024, 512, 60 **/ #define SAMPLESIZE 65536 // a power of 2 that is a whole number multiple of the sample rate #define SAMPLERATE 16384 // a value at least twice that of the sampled frequency (10x or more is good) #define FREQUENCY 1024 // frequency of the simulated signal for producing fake samples

#define SPIKE (SAMPLERATE / 3) // the magnitude at which we consider a value a spike #define NEGATIVESPIKE (SPIKE * -1)

#define TWOPI 6.283185307179586 #define NEGATIVETWOPI -6.283185307179586 typedef struct complex_struct { double real; double imaginary; } complex; complex cmult(complex a, complex b) { complex out; out.real = a.real * b.real - a.imaginary * b.imaginary; out.imaginary = a.real * b.imaginary + a.imaginary * b.real; return out; } complex *sample() { complex *signal = malloc(sizeof(struct complex_struct) * SAMPLESIZE); int i, amplitude = 1; // Determines the amplitude of the known wave

for(i = 0; i < SAMPLESIZE; i++) { signal[i].real = (double) amplitude * sin((TWOPI * i * FREQUENCY) / SAMPLERATE); signal[i].imaginary = 0.0; }

return signal; }

/** * Requires that size of complex array input be a power of 2 */ complex *fft(complex *in, int n) { complex *out = (complex*) malloc(sizeof(complex) * n); complex *evens, *odds, *evensOut, *oddsOut;

vi int i, half = n / 2;

if(n == 1) { out[0] = in[0]; return out; }

evens = (complex*) malloc(sizeof(struct complex_struct) * half); odds = (complex*) malloc(sizeof(struct complex_struct) * half);

for(i = 0; i < half; i++) { evens[i] = in[2 * i]; odds[i] = in[2 * i + 1]; }

evensOut = fft(evens, half); oddsOut = fft(odds, half);

/** twiddle factor */ for(i = 0; i < half; i++) { complex twiddle; double angle = (double) (NEGATIVETWOPI * i )/ n; twiddle.real = cos(angle); twiddle.imaginary = sin(angle);

oddsOut[i] = cmult(twiddle, oddsOut[i]); }

for(i = 0; i < half; i++) { out[i].real = evensOut[i].real + oddsOut[i].real; out[i].imaginary = evensOut[i].imaginary + oddsOut[i].imaginary;

out[i + half].real = evensOut[i].real - oddsOut[i].real; out[i + half].imaginary = evensOut[i].imaginary - oddsOut[i].imaginary; }

free(evensOut); free(oddsOut); return out; } void outputResults(complex *in, complex *out) { int i;

for(i = 0; i < SAMPLESIZE; i++) if((out[i].real > SPIKE || out[i].real < NEGATIVESPIKE) || (out[i].imaginary > SPIKE || out[i].imaginary < NEGATIVESPIKE)) printf("%d: Real: %20.13f\t\tImaginary: %20.13f\n", i, out[i].real, out[i].imaginary);

/** Maintenance and user friendly pause */ free(in); free(out); system("PAUSE"); }

vii int main(int argc, char *argv[]) { complex *in; complex *out;

/** FFT test */ in = sample(); out = fft(in, SAMPLESIZE); outputResults(in, out); system("PAUSE");

return 0; }

viii 9.3 Appendix C – Datasheets Resistors: Yageo RT Series Resistors: http://www.yageo.com/documents/recent/PYu-RT_1-to-0.05_RoHS_L_6.pdf

Yageo Thick Film Chip Resistors: http://www.yageo.com.tw/exep/pages/download/literatures/PYu-R_INT- thick_7.pdf

Capacitors: Murata Electronics North America Capacitors: http://search.murata.co.jp/Ceramy/image/img/A01X/partnumbering_e_01.pdf

AVX Corporation C0G (NP0) Dielectric Capacitors: http://datasheets.avx.com/C0GNP0-Dielectric.pdf

Ferrite Beads: Taiyo Yuden FB Series M Type Ferrite Beads: http://www.yuden.co.jp/productdata/catalog/en/chipbeads01_e.pdf

Protection Devices: EPCOS (TDK) B722 StandarD Series Varistors: http://en.tdk.eu/inf/70/db/var_11/SIOV_Leaded_StandarD.pdf

Bourns Inc. SMAJ Series TVS Diodes: http://www.bourns.com/docs/Product-Datasheets/SMAJ.pdf

NXP Semiconductors PMLL4148L; PMLL4448 High-Speed Switching Diodes: http://www.nxp.com/documents/data_sheet/PMLL4148L_PMLL4448.pdf

Analog-to-Digital Converter: Texas Instruments ADS131E08 ADC: http://www.ti.com/lit/ds/symlink/ads131e08.pdf

Microcontroller Unit: Texas Instruments MSP432P401R http://www.ti.com/lit/ds/symlink/msp432p401r.pdf

Liquid Crystal Display EastRising ER-TFTM050-2 LCD Module http://www.tato.ind.br/files/ER-TFTM050-2_Datasheet.pdf

Silead GSL 1680 http://dl.linux-sunxi.org/touchscreen/GSL1680.pdf

Current Transformers: Copal Electronics Inc. C-CT Series Current Transformers: http://www.nidec-copal-electronics.com/e/catalog/current-sensor/c-ct.pdf

Continental Control Systems LLC Accu-CT Current Transformers: http://www.ccontrolsys.com/w/ACT_Series_Split-Core_Current_Transformers http://www.ccontrolsys.com/w/ACT-0750_Advanced_Options

Diode Bridge Rectifier: Vishay KBL02 http://www.vishay.com/docs/88655/kbl005.pdf

Power Factor Correction Circuit: Texas Instruments UCC29950 http://www.ti.com/lit/ds/symlink/ucc29950.pdf

Voltage Regulators: Texas Instruments LM46001 http://www.ti.com/lit/ds/symlink/lm46001.pdf

Texas Instrument LM23011 http://www.ti.com/lit/ds/symlink/lm20133.pdf

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xiv