On Impacts Of ESD Protection Structure On Circuit Performance In Aluminum And Copper Interconnects

Ke Gong, Haigang Feng and Albert Z. Wang Integrated Electronics Laboratory Department of Electrical & Computer Engineering Illinois Institute of Technology 3301 S. Dearborn St., Chicago, IL 60616 Tel: (312) 567-6912, Fax: (312) 567-8976 Email: [email protected]

ABSTRACT ESD structures, therefore even more ESD parasitic effects. On the other hand, This paper presents a comparison study it is reported that new copper on influences of on-chip electro-static interconnect technology delivers many discharge (ESD) protection structures on benefits to IC designs as compared to its performance of the circuits protected, aluminum counterpart, e.g., higher using 1.5V, 0.18mm aluminum and speed, better reliability in terms of both copper interconnect technologies, harness and ESD respectively. A low-power, high-speed robustness [1]. However, little has been Op Amp was designed. Simulation reported regarding how seriously ESD results show that while ESD parasitics structures may affect the circuits may degrade the circuit performance protected and how well the copper inevitably, the use of Cu interconnects technology may alleviate this problem. can substantially recover such corruption Such problem was studied in this work. compared to using Al, while maintains better ESD protection. DESIGN

INTRODUCTION In this work, a low-power, high- performance Op Amp circuit with Parasitic effects of on-chip ESD CMOS-type ESD protection was protection structures become significant designed in 0.18mm aluminum and issues in high-speed and RF IC design, copper interconnect technologies. as chip sizes continuously shrink. Comprehensive studies were then Similar to the well-known global conducted to estimate how much interconnect timing issues, the parasitic parasitic CESD exists, to investigate how capacitance, CESD, of ESD protection seriously CESD may deteriorate the Op structures may corrupt circuit Amp performance, such as speed, performance as well, such as, clock driving capability and stability, etc. as signals, band width, stability, etc. The well as to demonstrate how well the Cu problem becomes even more challenging ESD design may recover such these days as the marketing strategies degradation. The design uses the drive ESD specification level higher and commercial 1.5V, 0.18mm one-poly, six- higher, leading to ever-larger size for metal Cu and Al high-speed CMOS primary ESD metal and metal 2 (M2) technologies from the UMC foundry. was used for interconnect bridges. Study of the layout shows that the main source A. ESD Protection of ESD parasitic capacitance, CESD, In order to illustrate the interactions comes from the ESD metal line between ESD structures and the core IC associated inter-layer capacitance, circuits, this design chose to use the including metal-to-substrate, inter- conventional ground-gate CMOS metals, as well as metal-to-poly-gate. [2] (GGMOS) ESD protection structure Therefore, the total CESD consists of the because of its ubiquitousness and large following capacitances: M1-to-substrate, size. The target ESD protection level is M1-to-Diffusion, M1-to-Poly 1, and M1- 4kV to reflect current market trend. The to-M2. Material data for inter-layer schematic of a GGMOS ESD structure dielectric thickness and permitivity (e) and a complete ESD protection scheme that were used to calculate the CESD is are shown in Fig 1. In principle, the listed in Table I. In calculating CESD, normally off ESD units are triggered on parasitic capacitance from both NMOS during an ESD event to form a low- and PMOS ESD units are included based impedamce discharging path to shunt the upon the complete ESD protection huge transient ESD pulses, therefore topology shown in Fig. 1. The estimated protect the core circuit against ESD data for CESD are summarized in Table damages. For comparison purpose, two II, which shows substantial parasitic versions of ESD structures and circuits capacitance from the ESD structures and were designed using Cu and Al roughly 30% of CESD reduction for the interconnects, respectively. To ensure Cu ESD circuit as compared to the Al meaningful comparison between Cu and version. Al designs, the same ESD compliance level (4KV) were used for both ESD chips. ESD simulation[3, 4] was Table I Inter-layer dielectric thickness and performance to predict the ESD permittivity data for CESD estimation performance as well as to guide the size From To Thickness selection of the ESD devices for (KÅ) Metal 1 Diffusion 10 adequate ESD performance. The Metal 1 Sub-strate 14 simulation shows that to achieve the Metal 1 Poly-1 8 same ESD protection level, over 30% of Metal 1 Metal 2 5.7 metal width reduction can be obtained in ILD-layers ILD-films e using Cu interconnects as compare to STI SiO2 3.6 using the conventional Al interconnects. ILD Si3N4 7 This substantial size reduction translates MD1 SiO2 3.6 into significant decrease of the parasitic ESD capacitance CESD, to be discussed in the following sections. Table II Estimated CESD for 4KV GGMOS GGMOS Cu Al

Full-ESD CESD (pF) 0.300 0.429 B. Estimation of Parasitic CESD According to the design rules, metal layers 1 and 2 were used in ESD design where metal 1 layer (M1) was used for C. Op Amp Circuit for the purpose of comparison. The To illustrate the whole-scale influences typical circuit performance are shown in of the ESD parasitic CESD on the circuits, Figs.3-6 for the gain Bode plot, phase a low-power, high-performance Op Amp Bode plot, large-signal step response for is designed and used as a test vehicle in slew-rate test and small-signal step this work. The Op Amp design targets response for settling time extraction. The include low power, high slew rate, short typical circuit specification data are settling time, wide output swing and extracted and summarized in Tables IV large bandwidth. The circuit schematics & V for comparison study. The results are shown in Fig. 2, which has the clearly show that parasitic ESD following features: A differential pair capacitance may substantially corrupt input stage for better noise rejection; a the circuit performance, for example, source-follower gain stage for high gain over 20% reduction in bandwidth, 15% as well as level shift; A class AB decrease in slew rate and 57% increase complementary push-pull output stage in settling time. The data also with low quiescent current for high- demonstrate that, while maintaining the swing, low power consumption, as well same ESD protection level, the use of Cu as crossover distortion elimination; and a interconnects can significantly alleviate compensation capacitor CC with active such circuit performance deterioration, nulling resistor for wide band width and e.g., ~20% recovery over a broad range. adequate stability. It is therefore beneficiary to use Cu interconnect technology in high-speed SIMULATION AND DISCUSSION IC designs.

A. Op Amp Performance The Op Amp circuit operates at Table III. The Op Amp circuit specifications Technology 0.18um, 1.5V, Cu, VDD=1.5V. SPICE simulation was performed for both stand-alone Op Amp 1P6M Power supply (V) 1.5 circuits and the circuits with CESD Gain (dB) 74.21 included to represent the parasitic ESD Phase margin 62.2 ° capacitive effects. The simulation data fT (MHz) 156.5 for the stand-alone Op Amp circuit are f-3dB (kHz) 33.9 summarized in Table III, which shows V-swing (V, @80%) 0.96 very low power consumption of 0.47 Settling time (ns, @1%) 5.01 mw; gain of 74dB, phase margin of 62°; SR (mV/ns) 215.6 Power cons. (mw) 0.469 unity-gain band-width of 156 MHz; wide output swing of 0.96V (measured at 80% small-signal gain), very high Table IV. Influences of CESD loads on the Op slew-rate of 215 mV/ns; and very short Amp circuit: Cu ~ Al, (CL = 1pF). settling time of 5 ns measured at 1% of ESD CESD fT Phase SR tset (pF) (MHz) marg. (mV/ns) (ns) the output. External load (CL) of 1 pF is ° used for data extraction. None 0 156.5 62.2 215.6 5.01 Al 0.3 118.8 59.9 ° 181.8 7.88 Cu 0.43 127.4 ° 190.7 7.28 B. Performance Comparison 60.8 Simulation with different CESD for both Cu and Al interconnects was conducted CONCLUSION ACCKNOWLEDGEMENT

In summary, a comparison study was The authors wish to thank SRC and conducted to investigate the influences UMC foundry service for making this of on-chip ESD protection structures on work possible. performance of the circuits protected, using aluminum and copper interconnect REFERENCES technologies, respectively. Simulation results show that parasitic ESD effects 1. S. Voldman, et al., "High-current may degrade the circuit performance TLP characterization of Al and Cu substantially and inevitably. It also interconnects for advanced CMOS demonstrates that the use of Cu technologies", in interconnects can substantially alleviate Proc. of Int'l Rel. Physi. Symp., such corruption problem as compared to pp.293-301, 1998. using Al interconnects, while 2. A. Amerasekera and C. Duvvury, maintaining the same or better ESD ESD in Integrated Circuits, performance. John Wiley, New York, 1995. 3. A. Wang and C. Tsay, "A Novel Design Methodology Using Table V. Op Amp performance degradation due Simulation For On-Chip ESD to CESD loads: Cu ~ Al. Protection For ICs", In Proc. of IEEE Parameters No C Al Cu ESD 5th Int'l Conf. Solid-State IC 156.5 -24.1% -18.6% Technology, pp.509-512, 1998. fT (MHz) Reduction in Degradation ® +22.8% ® 4. A. Wang, H.G. Feng and K. Gong, A Phase 62.2 ° -3.7% -2.3% SRC Cu Design Contest Report, Margin Reduction in Degradation 1999. ® +39.2% ® Slew rate 215.6 -15.7% -11.5% (V/us) Reduction in Degradation ® +26.8% ®

tset 5.01 -57.3% -45.3% (ns, 1%) Reduction in Degradation ® +20.9% ® B VDD S G D VDD

+ P N+ N+ N-well N-well P-well

(a)

VDD

ESD CESD

I/O ESD

CESD ESD GND (b)

Fig. 1 GGMOS ESD protection structure: a) cross-section for a GGNMOS, b) a complete ESD protection scheme.

ESD load + external load

Fig. 2 Schematic of a high-performance Op Amp circuit. Parasitic capacitive side effects from ESD protection units are simulated by CESD connected to the I/O pins. Gain (dB)

No ESD

Al ESD Cu ESD

f in log

Fig. 3 Gain plot of the Op Amp circuit with CESD load.

Phase

Cu ESD

No ESD

Al ESD

f in log

Fig. 4 Phase plot of the Op Amp circuit with CESD load. V(V) No ESD Al ESD

Cu ESD

Time

Fig. 5 Large-signal step response plot of the Op Amp circuit with CESD load for slew-rate test.

V Al ESD

No ESD

Cu ESD

Time

Fig. 6 Small-signal step response plot of the Op Amp circuit with CESD load for settling-time test.