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Theory and Applications of the MC34063 and mA78S40 Switching Regulator Control Circuits http://onsemi.com

APPLICATION NOTE

This paper describes in detail the principle of operation of the MC34063 and μA78S40 switching regulator subsystems. Several converter design examples and numerous applications circuits with test data are included.

INTRODUCTION control signal will go low and turn off the gate, terminating The MC34063 and μA78S40 are monolithic switching any further switching of the series−pass element. The output regulator subsystems intended for use as dc to dc converters. voltage will eventually decrease to below nominal due to the These devices represent a significant advancement in the presence of an external load, and will initiate the switching ease of implementing highly efficient and yet simple process again. The increase in conversion efficiency is switching power supplies. The use of switching regulators primarily due to the operation of the series−pass element is becoming more pronounced over that of linear regulators only in the saturated or cutoff state. The voltage drop across because the size reductions in new equipment designs the element, when saturated, is small as is the dissipation. require greater conversion efficiency. Another major When in cutoff, the current through the element and likewise advantage of the switching regulator is that it has increased the power dissipation are also small. There are other application flexibility of output voltage. The output can be variations of switching control. The most common are the less than, greater than, or of opposite polarity to that of the fixed frequency pulse width modulator and the fixed input voltage. on−time variable off−time types, where the on−off switching is uninterrupted and regulation is achieved by PRINCIPLE OF OPERATION duty cycle control. Generally speaking, the example given In order to understand the difference in operation between in Figure 1b does apply to MC34063 and μA78S40. linear and switching regulators we must compare the block diagrams of the two step−down regulators shown in Figure Vin Vout 1. The linear regulator consists of a stable reference, a high Ref gain error amplifier, and a variable resistance series−pass Linear Control + Voltage element. The error amplifier monitors the output voltage Signal − level, compares it to the reference and generates a linear Error Amp control signal that varies between two extremes, saturation and cutoff. This signal is used to vary the resistance of the a. Linear Regulator series−pass element in a corrective fashion in order to maintain a constant output voltage under varying input Vin Vout voltage and output load conditions. The switching regulator consists of a stable reference and Error a high gain error amplifier identical to that of the linear Amp Ref regulator. This system differs in that a free running oscillator Gated + Voltage and a gated latch have been added. The error amplifier again Latch − monitors the output voltage, compares it to the reference Digital level and generates a control signal. If the output voltage is Control Signal below nominal, the control signal will go to a high state and OSC turn on the gate, thus allowing the oscillator clock pulses to drive the series−pass element alternately from cutoff to b. Switching Regulator saturation. This will continue until the output voltage is Figure 1. Step−Down Regulators pumped up slightly above its nominal value. At this time, the

© Semiconductor Components Industries, LLC, 2013 1 Publication Order Number: December, 2013 − Rev. 6 AN920/D AN920/D

GENERAL DESCRIPTION these conditions, the comparator’s output can inhibit a The MC34063 series is a monolithic control circuit portion of the output switch on−cycle, a complete cycle, a containing all the active functions required for dc to dc complete cycle plus a portion of one cycle, multiple cycles, converters. This device contains an internal temperature or multiple cycles plus a portion of one cycle. compensated reference, comparator, controlled duty cycle oscillator with an active peak current limit circuit, driver, Drive Switch 8 1 and a high current output switch. This series was specifically Collector B Latch Collector designed to be incorporated in step−up, step−down and S Q Q2 voltage−inverting converter applications. These functions A Q1 are contained in an 8−pin dual in−line package shown in R Figure 2a. I 170 Switch μ pk 7 2 The A78S40 is identical to the MC34063 with the Sense Emitter addition of an on−board power catch diode, and an Ipk uncommitted operational amplifier. This device is in a CT OSC 16−pin dual in−line package which allows the reference and Timing the noninverting input of the comparator to be pinned out. VCC 6 3 These additional features greatly enhance the flexibility of Capacitor + 1.25 V this part and allow the implementation of more sophisticated Reference applications. These may include series−pass regulation of − Regulator Comparator Comp the main output or of a derived second output voltage, a Inverting 5 4 Ground tracking regulator configuration or even a second switching Input regulator. a. MC34063 FUNCTIONAL DESCRIPTION The oscillator is composed of a current source and sink which charges and discharges the external timing capacitor Sense CC pk V CT between an upper and lower preset threshold. The typical Noninverting Input Inverting Input GND Timing Capacitor I Driver Collector Switch Collector charge and discharge currents are 35 μA and 200 μA 9 10 11 12 13 14 15 16 respectively, yielding about a one to six ratio. Thus the GND ramp−up period is six times longer than that of the A Latch ramp−down as shown in Figure 3. The upper threshold is CT Ipk S Q equal to the internal reference voltage of 1.25 V and the OSC

B lower is approximately equal to 0.75 V. The oscillator runs − Comp R

continuously at a rate controlled by the selected value of C . T + 170

During the ramp−up portion of the cycle, a Logic “1” is Op

present at the “A” input of the AND gate. If the output 1.25 V − Amp voltage of the switching regulator is below nominal, a Logic Ref + D1 “1” will also be present at the “B” input. This condition will set the latch and cause the “Q” output to go to a Logic “1”, 8 7 6 5 4 3 2 1

enabling the driver and output switch to conduct. When the CC Ref V Input Input oscillator reaches its upper threshold, C will start to Diode Diode Anode

T Switch Output Output Emitter Op Amp Cathode discharge and Logic “0” will be present at the “A” input of Inverting

the AND gate. This logic level is also connected to an Noninverting inverter whose output presents a Logic “1” to the reset input b. mA78S40 of the latch. This condition will cause “Q” to go low, Figure 2. Functional Block Diagrams disabling the driver and output switch. A logic truth table of these functional blocks is shown in Figure 4. V The output of the comparator can set the latch only during Upper Threshold 1.25 V Typical the ramp−up of CT and can initiate a partial or full on−cycle of output switch conduction. Once the comparator has set the latch, it cannot reset it. The latch will remain set until CT Lower Threshold 0.75 V Typical begins ramping down. Thus the comparator can initiate t output switch conduction, but cannot terminate it and the latch is always reset when CT begins ramping down. The 6t Charge t comparator’s output will be at a Logic “0” when the output Discharge voltage of the switching regulator is above nominal. Under Figure 3. CT Voltage Waveform

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AND Gate Inputs Latch Inputs Active Condition of Output Timing Capacitor, CT A B S R Switch Comments on State of Output Switch Begins Ramp−Up 0 0 0 Switching regulator’s output is ≥ nominal (‘B’ = 0).

Begins Ramp−Down 0 0 0 No change since ‘B’ was 0 before CT Ramp− Down. Ramping Down 0 0 1 0 No change even though switching regulator’s output < nominal. Output switch cannot be initiated during RT Ramp−Down. Ramping Down 0 0 1 0 No change since output switch conduction was terminated when ‘A’ went to 0. Ramping Up 1 0 Switching regulator’s output went < nominal → during CT Ramp−Up (‘B’ 1). Partial on− cycle for output switch. Ramping Up 1 0 1 Switching regulator’s output went ≥ nominal → (‘B’ 0) during CT Ramp−Up. No change since ‘B’ cannot reset latch.

Begins Ramp−Up 1 Complete on−cycle since ‘B’ was 1 before CT started Ramp−Up. Begins Ramp−Down 1 Output switch conduction is always termi- nated whenever CT is Ramping Down. Figure 4. Logic Truth Table of Functional Blocks Current limiting is accomplished by monitoring the waveform as shown in Figure 5. Operation of the switching voltage drop across an external sense resistor placed in series regulator in an overload or shorted condition will cause a with VCC and the output switch. The voltage drop developed very short but finite time of output conduction followed by across this resistor is monitored by the Ipk Sense pin. When either a normal or extended off−time internal provided by this voltage becomes greater than 330 mV, the current limit the oscillator ramp−down time of CT. The extended interval circuitry provides an additional current path to charge the is the result of charging CT beyond the upper oscillator timing capacitor CT. This causes it to rapidly reach the upper threshold by overdriving the current limit sense input. This oscillator threshold, thereby shortening the time of output can be caused by operating the switching regulator with a switch conduction and thus reducing the amount of energy severely overloaded or shorted output or having the input stored in the inductor. This can be observed as an increase voltage grossly above the nominal design value. in the slope of the charging portion of the CT voltage

1 Comparator Output 0

Timing Capacitor, CT

On Output Switch Off

Nominal Output Voltage Level

Output Voltage Startup Quiescent Operation

Figure 5. Typical Operating Waveforms

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30 L ° Q1 TA = 25 C +Vin +Vout 10 VCC = 40 V MC34063 + VCC = 5 V D1 C R 3.0 μA78S40 o L

1.0 a. Step−Down Vout Vin 0.3

, Charging Current (mA) L

chg Ichg = Idischg I 0.1 +Vin +Vout D1 MC34063 + 0.03 Q1 C R 0 0.2 0.4 0.6 0.8 1.0 μA78S40 o L VCLS, Current−Limit Sense Voltage (V) Figure 6. Timing Capacitor Charge Current versus Current−Limit Sense Voltage b. Step−Up Vout Vin

Under extreme conditions, the voltage across CT will +Vin Q1 −Vout approach VCC and can cause a relatively long off−time. This D1 action may be considered a feature since it will reduce the L + Co RL power dissipation of the output switch considerably. This μA78S40 feature may be disabled on the μA78S40 only, by connecting a small signal PNP transistor as a clamp. The emitter is connected to CT, the base to the reference output, and the c. Voltage−Inverting |Vout| Vin collector to ground. This will limit the maximum charge Figure 7. Basic Switching Regulator Configurations voltage across CT to less than 2.0 V. With the use of current limiting, saturation of the storage inductor may be prevented Because the integrated circuit substrate is common with the as well as achieving a soft startup. internal and external circuitry ground, the cathode of the diode In practice the current limit circuit will somewhat modify the cannot be operated much below ground or forward biasing of charging slope and peak amplitude of CT each time the output the substrate will result. This totally eliminates the diode from switch is required to conduct. This is because the threshold being used in the basic voltage inverting configuration as in voltage of the current limit sense circuit exhibits a “soft” Figure 15, since the substrate, pin 11, is common to ground. voltage turn−on characteristic and has a turn−off time delay The diode can be considered for use only in low power that causes some overshoot. The 330 mV threshold is defined converter applications where the total system component where the charge and discharge currents are of equal value with count must be held to a minimum. The substrate current will VCC = 5.0 V, as shown in Figure 6. The current limit sense be about 10 percent of the catch diode current in the step−up circuit can be disabled by connecting the Ipk Sense pin to VCC. configuration and about 20 percent in the step−down and To aid in system design flexibility, the driver collector, voltage−inverting in which pin 11 is common to the negative output switch collector and emitter are pinned out output. System efficiency will suffer when using this diode separately. This allows the designer the option of driving the and the package dissipation limits must be observed. output switch transistor into saturation with a selected STEP−DOWN SWITCHING forced gain or driving it near saturation when connected as REGULATOR OPERATION a Darlington. The output switch has a typical current gain of Shown in Figure 7a is the basic step−down switching 70 at 1.0 A and is designed to switch a maximum of 40 V regulator. Transistor Q1 interrupts the input voltage and collector−to−emitter, with up to 1.5 A peak collector current. provides a variable duty cycle squarewave to a simple LC The μA78S40 has the additional features of an on−chip filter. The filter averages the squarewaves producing a dc uncommitted operational amplifier and catch diode. The op output voltage that can be set to any level less than the input amp is a high gain single supply type with an input by controlling the percent conduction time of Q1 to that of common−mode voltage range that includes ground. The output the total switching cycle time. Thus, is capable of sourcing up to 150 mA and sinking 35 mA. A t separate VCC pin is provided in order to reduce the + ǒ Ǔ + ǒ on Ǔ Vout Vin %ton or Vout Vin ) integrated circuit standby current and is useful in low power ton toff applications if the operational amplifier is not incorporated The MC34063/μA78S40 achieves regulation by varying into the main switching system. The catch diode is the on−time and the total switching cycle time. An constructed from a lateral PNP transistor and is capable of explanation of the step−down converter operation is as blocking up to 40 V and will conduct current up to 1.5 A. follows: Assume that the transistor Q1 is off, the inductor There is, however, a “catch” when using it. current IL is zero, and the output voltage Vout is at its nominal

http://onsemi.com 4 AN920/D value. The output voltage across capacitor Co will The off−time, toff, is the time that diode D1 is in eventually decay below nominal because it is the only conduction and it is determined by the time required for the component supply current into the external load RL. This inductor current to return to zero. The off−time is not related voltage deficiency is monitored by the switching control to the ramp−down time of CT. The cycle time of the LC circuit and causes it to drive Q1 into saturation. The inductor network is equal to ton(max) + toff and the minimum operating current will start to flow from Vin through Q1 and, Co in frequency is: parallel with RL, and rise at a rate of ΔI/ΔT = V/L. The + 1 fmin ) voltage across the inductor is equal to Vin − Vsat − Vout and ton(max) toff the peak current at any instant is: A minimum value of inductance can now be calculated for V * V * V L. The known quantities are the voltage across the inductor I + ǒ in sat outǓ t L L and the required peak current for the selected switch At the end of the on−time, Q1 is turned off. As the magnetic conduction time. Vin * Vsat * Vout field in the inductor starts to collapse, it generates a reverse Lmin + ton voltage that forward biases D1, and the peak current will Ipk(switch) decay at a rate of ΔI/ΔT = V/L as energy is supplied to Co and This minimum value of inductance was calculated by RL. The voltage across the inductor during this period is equal assuming the onset of continuous conduction operation with to Vout + VF of D1, and the current at any instant is: a fixed input voltage, maximum output current, and a V ) V minimum charge−current oscillator. I + I * ǒ out FǓ t L L(pk) L The net charge per cycle delivered to the output filter capacitor C , must be zero, Q+ = Q−, if the output voltage Assume that during quiescent operation the average o is to remain constant. The ripple voltage can be calculated output voltage is constant and that the system is operating in from the known values of on−time, off−time, peak inductor the discontinuous mode. Then I attained during t L(peak) on current, and output capacitor value. must decay to zero during t and a ratio of t to t can be off on off t1 t2 determined. ǒ 1 Ǔ ǒ 1 Ǔ Vripple(p−p) + ŕ itdt) ŕ iȀ tdt * * ) Co Co ǒVin Vsat VoutǓ ǒVout VFǓ 0 t1 ton + toff L L 1 1 Ipkt Ipkt whereit+ 2 and iȀ t + 2 ) t ń2 t ń2 N ton + Vout VF on off * * toff Vin Vsat Vout I t I t + 1 Ť pk t2 Ť 1 ) 1 Ť pk t2 Ť 2 Note that the volt−time product of ton must be equal to that Co ton 2 0 Co toff 2 t1 of t and the inductance value is not of concern when off t t Andt + on and t * t + off determining their ratio. If the output voltage is to remain 1 2 2 1 2 constant, the average current into the inductor must be equal Substituting for t and t − t yields: to the output current for a complete cycle. The peak inductor 1 2 1 I (t ń2)2 I (t ń2)2 current with respect to output current is: + 1 pk on ) 1 pk off C ton 2 C t 2 I I o o off ǒ L(pk)Ǔ ) ǒ L(pk)Ǔ + ǒ Ǔ ) ǒ Ǔ ton toff Iout ton Iout toff I (t ) t ) 2 2 + pk on off 8Co IL(pk)(ton ) toff) + I (t ) t ) 2 out on off A graphical derivation of the peak−to−peak ripple voltage N + can be obtained from the capacitor current and voltage IL(pk) 2Iout waveforms in Figure 8. The peak inductor current is also equal to the peak switch The calculations shown account for the ripple voltage current Ipk(switch) since the two are in series. The on−time, ton, contributed by the ripple current into an ideal capacitor. In is the maximum possible switch conduction time. It is equal practice, the calculated value will need to be increased due to to the time required for CT to ramp up from its lower to upper the internal equivalent series resistance ESR of the capacitor. threshold. The required value for CT can be determined by The additional ripple voltage will be equal to Ipk(ESR). using the minimum oscillator charging current and the Increasing the value of the filter capacitor will reduce the typical value for the oscillator voltage swing both taken output ripple voltage. However, a point of diminishing return from the data sheet electrical characteristics table. will be reached because the comparator requires a finite D voltage difference across its inputs to control the latch. This C + I ǒ t Ǔ T chg(min) DV voltage difference to completely change the latch states is t about 1.5 mV and the minimum achievable ripple at the output + 20 10− 6 ǒ onǓ 0.5 will be the feedback divider ratio multiplied by 1.5 mV or: + Vout 4.0 10− 5 ton Vripple(p−p)min + (1.5 10− 3) Vref

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V + V Voltage Across in F V Switch Q1 in VCE Vsat 0 V Voltage Across in V − V Diode D1 in sat V KA 0 VF Switch Q1 Ipk Current

Iin = IC(AVG) 0

Diode D1 Ipk Current ID(AVG) 0

Inductor Ipk Current Iout = Ipk/2 = IC(AVG) + ID(AVG)

0

+Ipk/2

Capacitor Co

ÌÌÌÌ ÌÌ 1/2 I ÏÏ Current Q+ pk/2

0

ÌÌÌÌ ÏÏÌÌ ÌÌÌQ− off/2 on/2 t −I t pk/2 ÌÌÌ

Vout + Vpk Capacitor Co Ripple Voltage Vout Vripple(p−p) Vout − Vpk t0 t1 t2

Figure 8. Step−Down Switching Regulator Waveforms

This problem becomes more apparent in a step−up 1. Determine the ratio of switch conduction ton versus converter with a high output voltage. Figures 12 and 13 show diode conduction toff time. two different ripple reduction techniques. The first uses the t V ) V μ on + out F A78S40 operational amplifier to drive the comparator in the toff Vin(min) * Vsat * Vout feedback loop. The second technique uses a Zener diode to ) level shift the output down to the reference voltage. + 5.0 0.8 21.6 * 0.8 * 5.0 + 0.37 Step−Down Switching Regulator Design Example 2. The cycle time of the LC network is equal to t A schematic of the basic step−down regulator is shown on(max) + t . in Figure 9. The μA78S40 was chosen in order to off 1 implement a minimum component system, however, the ton(max) ) toff + MC34063 with an external catch diode can also be used. fmin The frequency chosen is a compromise between switching + 1 losses and inductor size. There will be a further discussion 50 103 of this and other design considerations later. Given are the + 20 ms per cycle following: 3. Next calculate t and t from the ratio of t /t in V = 5.0 V on off on off out #1 and the sum of t + t in #2. By using I = 50 mA on off out substitution and some algebraic gymnastics, an fmin = 50 kHz equation can be written for toff in terms of ton/toff and Vin(min) = 24 V − 10% or 21.6 V ton + toff. Vripple(p−p) = 0.5% Vout or 25 mVp−p

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The equation is: Note that the ratio of ton/(ton + toff) does not exceed the maximum of 6/7 or 0.857. This maximum is ton(max) ) toff toff + defined by the 6:1 ratio of charge−to−discharge ton ) 1 toff current of timing capacitor CT (refer to Figure 3). − 6 4. The maximum on−time, t , is set by selecting + 20 10 on(max) 0.37 ) 1 a value for CT. + 14.6 ms CT + 4.0 10− 5 ton Since ton(max) ) toff + 20 ms + 4.0 10− 5 (5.4 10− 6) ton(max) + 20 ms * 14.6 ms + 216 pF + 5.4 ms Use a standard 220 pF capacitor.

Vin = 24 V

+ 47

R2 R1 Rsc

36 k 12 k 2.7

CT 220 pF

9 10 11 12 13 14 15 16 GND VCC

CT Ipk

OSC S Q − Comp R

+ 170

Op

1.25 V − Amp Ref + D1

8 7 6 5 4 3 2 1

1N5819 853 μH

* Vout L 5 V/50 mA

Co + 27

Test Conditions Results Δ ± Line Regulation Vin = 18 to 30 V, Iout = 50 mA = 16 mV or 0.16% Δ ± Load Regulation Vin = 24 V, Iout = 25 to 50 mA = 28 mV or 0.28%

Output Ripple Vin = 21.6 V, Iout = 50 mA 24 mVp−p Ω Short Circuit Current Vin = 24 V, RL = 0.1 105 mA

Efficiency, Internal Diode Vin = 24 V, Iout = 50 mA 45.3%

Efficiency, External Diode* Vin = 24 V, Iout = 50 mA 72.6%

Figure 9. Step−Down Design Example

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5. The peak switch current is: 9. The nominal output voltage is programmed by the R1, R2 resistor divider. The output voltage is: Ipk(switch) + 2Iout + − 3 V + 1.25 ǒR2 ) 1Ǔ 2(50 10 ) out R1 + 100 mA The divider current can go as low as 100 μA without 6. With knowledge of the peak switch current and affecting system performance. In selecting a maximum on time, a minimum value of inductance minimum current divider R1 is equal to: can be calculated. R1 + 1.25 − 6 ǒVin(min) * Vsat * VoutǓ 100 10 Lmin + ton(max) Ipk(switch) + 12, 500 W Rearranging the above equation so that R2 can be * * + ǒ21.6 0.8 5.0Ǔ 5.4 10− 6 solved yields: 100 10− 3 V R2 + R1 ǒ out * 1Ǔ + 853 mH 1.25 7. A value for the current limit resistor, Rsc, can be If a standard 5% tolerance 12 k resistor is chosen for determined by using the current level of Ipk(switch) R1, R2 will also be a standard value. when Vin = 24 V. R2 + 12 103 ǒ 5.0 * 1Ǔ ǒVin * Vsat * VoutǓ 1.25 IȀpk(switch) + ton(max) + Lmin 36 k Using the above derivation, the design is optimized to 24 * 0.8 * 5.0 + ǒ Ǔ 5.4 10− 6 meet the assumed conditions. At Vin(min), operation is at the

853 10− 6 onset of continuous mode and the output current capability + 115 mA will be greater than 50 mA. At Vin(nom) i.e., 24 V, the current limit will activate slightly above the rated Iout of 50 mA. + 0.33 Rsc Ȁ I pk(switch) STEP−UP SWITCHING REGULATOR OPERATION The basic step−up switching regulator is shown in Figure + 0.33 7b and the waveform is in Figure 10. Energy is stored in the − 3 115 10 inductor during the time that transistor Q1 is in the “on” + 2.86 W,use2.7W state. Upon turn−off, the energy is transferred in series with This value may have to be adjusted downward to Vin to the output filter capacitor and load. This configuration compensate for conversion losses and any increase allows the output voltage to be set to any value greater than that of the input by the following relationship: in Ipk(switch) current if Vin varies upward. Do not set R to exceed the maximum I limit of 1.5 A ǒtonǓ ǒton Ǔ sc pk(switch) Vout + Vin ) Vin or Vout + Vin ) 1 when using the internal switch transistor. toff toff 8. A minimum value for an ideal output filter capacitor An explanation of the step−up converter’s operation is as can now be obtained. follows. Initially, assume that transistor Q1 is off, the Ipk(switch) (ton ) toff) inductor current is zero, and the output voltage is at its Co + nominal value. At this time, load current is being supplied 8Vripple(p−p) only by Co and it will eventually fall below nominal. This − 6 + 0.1 (20 10 ) deficiency will be sensed by the control circuit and it will 8(25 10− 3) initiate an on−cycle, driving Q1 into saturation. Current will start to flow from Vin through the inductor and Q1 and rise + 10 mF at a rate of ΔI/ΔT = V/L. The voltage across the inductor is Ideally this would satisfy the design goal, however, equal to Vin − Vsat and the peak current is: even a solid tantalum capacitor of this value will V * V I + ǒ in satǓ t have a typical ESR (equivalent series resistance) of L L 0.3 Ω which will contribute 30 mV of ripple. The When the on−time is completed, Q1 will turn off and the ripple components are not in phase, but can be magnetic field in the inductor will start to collapse assumed to be for a conservative design. In generating a reverse voltage that forward biases D1, satisfying the example shown, a 27 μF tantalum with supplying energy to C and R . The inductor current will an ESR of 0.1 Ω was selected. The ripple voltage o L decay at a rate of ΔI/ΔT = V/L and the voltage across it is should be kept to a low value since it will directly equal to V + V − V . The current at any instant is: affect the system line and load regulation. out F in

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V + V Voltage Across out F Switch Q1 Vin VCE Vsat 0 V − V Diode D1 Voltage out sat VKA 0 VF Switch Q1 Ipk Current

0

Diode D1 Ipk Current Iout 0

Inductor Ipk Current Iin = IL(AVG)

0

Ipk − Iout

Capacitor Co ÌÌ

Current 1/2(Ipk − Iout) ÌÌ ÑÑ Q+

0 Q−

ÌÌ ÑÑ ÏÏÏÏÏ −Iout ÌÌÌÌ toff ton t1 Vout + Vpk Capacitor Co Ripple Voltage Vout Vripple(p−p)

Vout − Vpk

Figure 10. Step−Up Switching Regulator Waveforms

V ) V * V Figure 10 shows the step−up switching regulator I + I * ǒ out F inǓ t L L(pk) L waveforms. By observing the capacitor current and making Assuming that the system is operating in the some substitutions in the above statement, a formula for discontinuous mode, the current through the inductor will peak inductor current can be obtained. reach zero after the toff period is completed. Then IL(pk) IL(pk) ǒ Ǔ t + I (t ) t ) attained during ton must decay to zero during toff and a ratio 2 off out on off of t to t can be written. on off ǒton Ǔ IL(pk) + 2Iout ) 1 ǒVin * VsatǓ ǒVout ) VF * VinǓ toff ton + toff L L The peak inductor current is also equal to the peak switch ) * current, since the two are in series. N ton + Vout VF Vin toff Vin * Vsat With knowledge of the voltage across the inductor during t and the required peak current for the selected switch Note again, that the volt−time product of t must be equal on on conduction time, a minimum inductance value can be to that of t and the inductance value does not affect this off determined. relationship. The inductor current charges the output filter capacitor ǒVin * VsatǓ Lmin + ton(max) through diode D1 only during toff. If the output voltage is to Ipk(switch) remain constant, the net charge per cycle delivered to the The ripple voltage can be calculated from the known output filter capacitor must be zero, Q+ = Q−. values of on−time, off−time, peak inductor current, output Ichg toff + Idischg ton current and output capacitor value. Referring to the

http://onsemi.com 9 AN920/D capacitor current waveforms in Figure 10, t is defined as the V ) V * V 1 ton + out F in(min) capacitor charging interval. Solving for t1 in known terms toff Vin(min) * Vsat yields: 28 ) 0.8 * 6.75 Ipk * Iout Ipk + + 6.75 * 0.3 t1 toff + 3.42 * ǒIpk IoutǓ 2. The cycle time of the LC network is equal to t Nt1 + toff on(max) Ipk + toff. And the current during t can be written: 1 t ) t + 1 on(max) off f Ipk * Iout min I + ǒ Ǔ t t1 + 1 3 The ripple voltage is: 50 10 + 20 ms per cycle t1 * ǒ 1 Ǔŕ Ipk Iout Vripple(p−p) + tdt 3. Next calculate ton and toff from the ratio of ton/toff in Co t1 0 #1 and the sum of ton + toff in #2. * 1 Ť Ipk Iout t2 Ť t1 20 10− 6 + toff + Co t1 2 0 3.42 ) 1 + 4.5 ms (Ipk * Iout) + 1 t C 2 1 o ton + 20 ms * 4.5 ms Substituting for t1 yields: + 15.5 ms * * 1 (Ipk Iout) (Ipk Iout) + toff Note that the ratio of ton/(ton + toff) does not exceed Co 2 Ipk the maximum of 0.857. (I * I )2 t + pk out off 4. The maximum on−time, ton(max), is set by selecting 2Ipk Co a value for CT. A simplified formula that will give an error of less than 5% CT + 4.0 10− 5 ton for a voltage step−up greater than 3 with an ideal capacitor + is shown: 4.0 10− 5 (15.5 10− 6) ǒIoutǓ + 620 pF Vripple(p−p) [ ton Co 5. The peak switch current is: This neglects a small portion of the total Q− area. The area ǒton Ǔ neglected is equal to: Ipk(switch) + 2Iout ) 1 toff I A + (t * t ) out + − 3 ) off 1 2 2(50 10 ) (3.42 1) + 442 mA Step−Up Switching Regulator Design Example 6. A minimum value of inductance can be calculated The basic step−up regulator schematic is shown in Figure since the maximum on−time and peak switch current 11. The μA78S40 again was chosen in order to implement are known. a minimum component system. The following conditions Vin(min) * Vsat are given: L + ǒ Ǔ t min I on Vout = 28 V pk(switch) Iout = 50 mA 6.75 * 0.3 f = 50 kHz + ǒ Ǔ 15.5 10− 6 min 442 10− 3 Vin(min) = 9.0 V − 25% or 6.75 V Vripple(p−p) = 0.5% Vout or 140 mVp−p + 226 mH 1. Determine the ratio of switch conduction ton versus diode conduction toff time.

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7. A value for the current limit resistor, Rsc, can now be 9 Iout Co [ ton determined by using the current level of Ipk(switch) Vripple(p−p) when Vin = 9.0 V. 9 50 10− 3 ǒVin * VsatǓ [ 15.5 10− 6 IȀpk(switch) + ton(max) 140 10− 3 Lmin [ 50 mF * + ǒ 9.0 0.3 Ǔ 15.5 10− 6 226 10− 6 The ripple contribution due to the gain of the comparator: + 597 mA V V + out 1.5 10− 3 0.33 ripple(p−p) V Rsc + ref IȀpk(switch) + 28 1.5 10− 3 + 0.33 1.25 597 10− 3 + 33.6 mV + 0.55 W,use0.5W A 27 μF tantalum capacitor with an ESR of 0.10 Ω Note that current limiting in this basic step−up was again chosen. The ripple voltage due to the configuration will only protect the switch transistor capacitance value is 28.7 mV and 44.2 mV due to from overcurrent due to inductor saturation. If the ESR. This yields a total ripple voltage of: output is severely overloaded or shorted, D1, L, or Vout Iout Eripple(p−p) + 1.5 10− 3 ) ton ) Ipk ESR Rsc may be destroyed since they form a direct path Vref Co from Vin to Vout. Protection may be achieved by + ) ) current limiting Vin or replacing the inductor with 33.6 mV 28.7 mV 44.2 mV 1:1 turns ratio transformer. + 107 mV 8. An approximate value for an ideal output filter capacitor is:

http://onsemi.com 11 AN920/D

Vin = 9 V

+ 47 226 μH R2 R1 Rsc

47 k 2.2 k 0.5 C T 240 620 pF

9 10 11 12 13 14 15 16 GND VCC

CT Ipk

OSC S Q − Comp R

+ 170

Op

1.25 V − Amp Ref + D1

8 7 6 5 4 3 2 1

1N5819

* Vout 5 V/50 mA Co + 27

Test Conditions Results Δ ± Line Regulation Vin = 6.0 to 12 V, Iout = 50 mA = 120 mV or 0.21% Δ ± Load Regulation Vin = 9.0 V, Iout = 25 to 50 mA = 50 mV or 0.09%

Output Ripple Vin = 6.75 V, Iout = 50 mA 90 mVp−p

Efficiency, Internal Diode Vin = 9.0 V, Iout = 50 mA 62.2%

Efficiency, External Diode* Vin = 9.0 V, Iout = 50 mA 74.2%

Figure 11. Step−Up Design Example

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Vin

L Rsc

CT

9 10 11 12 13 14 15 16 GND VCC

CT Ipk

OSC S Q − Comp R

+ 170

Op

1.25 V − Amp Ref + D1

8 7 6 5 4 3 2 1

R2 Vout + R1 Co

Figure 12. mA78S40 Ripple Reduction Technique

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L The current required to drive the internal 170 Ω base−emitter resistor is: VBE(switch) I W + 170 170 8 1 + 0.7 170 S Q Q2 + 4.1 mA Q1 R The driver collector current is equal to sum of 22.1 mA + 4.1 mA = 26.2 mA. Allow 0.3 V for driver 7 2 saturation and 0.2 V for the drop across Rsc (0.5 × Ipk D1 442 mA Ipk). Rsc CT OSC Then the driver collector resistor is equal to: V in Vin * Vsat(driver) * VRSC 6 VCC 3 R + driver I ) I W 1.25 V B 170 + C Reference T 7.0 * 0.3 * 0.2 − + Regulator ) − 3 Comp (22.1 4.1) 10 5 4 + 248 W, use 240 W GND

Vout VOLTAGE−INVERTING SWITCHING REGULATOR OPERATION R1 VZ = Vout − 1.25 V + Co The basic voltage−inverting switching regulator is shown in Figure 7c and the operating waveforms are in Figure 14. Energy is stored in the inductor during the conduction time Figure 13. MC34063 Ripple Reduction Technique of Q1. Upon turn−off, the energy is transferred to the output filter capacitor and load. Notice that in this configuration the output voltage is derived only from the inductor. This allows 9. The nominal output voltage is programmed by the the magnitude of the output to be set to any value. It may be R1, R2 divider. less than, equal to, or greater than that of the input and is set by the following relationship: V + 1.25 ǒ1 ) R2Ǔ out R1 ǒtonǓ Vout + Vin A standard 5% tolerance, 2.2 k resistor was selected toff for R1 so that the divider current is about 500 μA. The voltage−inverting converter operates almost identically to that of the step−up previously discussed. The R1 + 1.25 500 10− 6 voltage across the inductor during ton is Vin − Vsat but during toff the voltage is equal to the negative magnitude of Vout + + 2500 W,use2.2k VF. Remember that the volt−time product of ton must be V equal to that of toff, a ratio of ton to toff can be determined. Then R2 + R1 ǒ out * 1Ǔ 1.25 (Vin * Vsat)ton + (|Vout| ) VF)toff

+ 2200 ǒ 28 * 1Ǔ t |Vout| ) VF 1.25 N on + toff Vin * Vsat + 47, 080 W,use47k The derivations and the formulas for Ipk(switch), Lmin, and 10. In this design example, the output switch transistor Co are the same as that of the step−up converter. is driven into saturation with a forced gain of 20 at an input voltage of 7.0 V. The required base drive is: Ipk(switch) IB + Bf − 3 + 442 10 20 + 22.1 mA

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V Voltage Across in V Switch Q1 sat 0 VCE Vin − (−Vout + VF)

(Vin − Vsat) + Vout Diode D1 Voltage VKA 0 VF Switch Q1 Ipk Current Iin = IC(AVG) 0

Diode D1 Ipk Current Iout 0

Inductor Ipk Current

0

Ipk − Iout

Capacitor Co ÌÌÌ

Current 1/2(Ipk − Iout) ÌÌÌ ÑÑÑ Q+

0 Q−

ÌÌÌ ÑÑÑ ÏÏÏÏ −Iout ÌÌÌÌ toff ton t1 −Vout + Vpk Capacitor Co Vripple(p−p) Ripple Voltage Vout

−Vout − Vpk

Figure 14. Voltage−Inverting Switching Regulator Waveforms

Voltage−Inverting Switching Regulator Design Example 2. The cycle time of the LC network is equal to ton(max) A circuit diagram of the basic voltage−inverting regulator + toff. is shown in Figure 15. 1 ton(max) ) toff + The μA78S40 was selected for this design since it has the fmin reference and both comparator inputs pinned out. The + 1 following operating conditions are given: 50 10− 3 V = −15 V out + 20 ms Iout = 500 mA 3. Calculate t and t from the ratio of t /t in #1 fmin = 50 kHz on off on off and the sum of t + t in #2. Vin(min) = 15 V − 10% or 13.5 V on off Vripple(p−p) = 0.4% Vout or 60 mVp−p 20 10− 6 t + 1. Determine the ratio of switch conduction ton versus off 1.24 ) 1 diode conductions t time. off + 8.9 ms |V | ) V ton + out F ton + 20 ms * 8.9 ms t V * V off in sat + 11.1 ms + 15 ) 0.8 13.5 * 0.8 + 1.24

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Note again that the ratio of ton/(ton + toff) does not exceed the maximum of 0.857.

Vin = 15 V

+ Q2 100 R2 MPS 36 k Rsc U51A * 0.12 RBE C T 160 R 430 pF B R1 160 3.0 k 9 10 11 12 13 14 15 16 GND VCC

CT Ipk

OSC S Q − Comp R

+ 170

Op

1.25 V − Amp Ref + D1 1N5822 V 8 7 6 5 4 3 2 1 out −15 V/0.5 A

L Co Co +

66.5 μH 470 + 470

* Heatsink, IERC PSC2−3CB

Test Conditions Results Δ ± Line Regulation Vin = 12 to 16 V, Iout = 0.5 A = 3.0 mV or 0.01% Δ ± Load Regulation Vin = 15 V, Iout = 0.1 to 0.5 A = 27 mV or 0.09%

Output Ripple Vin = 13.5 V, Iout = 0.5 A 35 mVp−p Ω Short Circuit Current Vin = 15 V, RL = 0.1 2.5 A

Efficiency Vin = 15 V, Iout = 0.5 A 80.6%

Figure 15. Voltage−Inverting Design Example 4. A value of CT must be selected in order to set ǒton Ǔ Ipk(switch) + 2Iout ) 1 ton(max). toff + − 5 CT 4.0 10 ton + 2 (500 10− 3) (1.24 ) 1) + 4.0 10− 5 (11.1 10− 6) + 2.24 A + 444 pF, use 430 pF 6. The minimum required inductance value is: 5. The peak switch current is:

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* ǒVin(min) VsatǓ also be at ground potential when Vout is in regulation. Lmin + ton Ipk(switch) The magnitude of Vout is: * |V | + 1.25 R2 + ǒ13.5 0.8Ǔ 11.1 10− 6 out R1 2.24 A divider current of about 400 μA was desired for + m 66.5 H this example. 7. The current−limit resistor value was selected by R1 + 1.25 determining the level of Ipk(switch) for Vin = 16.5 V. 400 10− 6 * ǒVin VsatǓ + W IȀpk(switch) + ton 3,125 ,use3.0k Lmin |Vout| * Then R2 + R1 + ǒ 16.5 0.8 Ǔ 11.1 10− 6 1.25 66.5 10− 6 + 15 3.0 10− 3 + 2.62 A 1.25 + 36 k 0.33 Rsc + IȀpk(switch) 10. Output switch transistor Q2 is driven into a soft saturation with a forced gain of 35 at an input voltage + 0.33 of 13.5 V in order to enhance the turn−off switching 2.62 time. The required base drive is: + W W 0.13 , use 0.12 Ipk(switch) IB + 8. An approximate value for an ideal output filter Bf capacitor is: + 2.24 35 [ ǒ Iout Ǔ Co ton + Vripple(p−p) 64 mA The value for the base−emitter turn−off resistor R 0.5 BE [ 11.1 10− 6 is determined by: 60 10− 3 10 Bf [ m RBE + 92.5 F Ipk(switch) The ripple contribution due to the gain of the comparator is: + 10 (35) 2.24 |Vout| + W W Vripple(p−p) + 1.5 10− 3 156.3 , use 160 Vref The additional base current required due to RBE is: 15 + 1.5 10− 3 VBE (Q2) 1.25 IR + BE RBE + 18 mV + 0.8 For a given level of ripple, the ESR of the output filter 160 capacitor becomes the dominant factor in choosing + 5.0 mA a value for capacitance. Therefore two 470 μF capacitors with an ESR of 0.020 Ω each was chosen. Then IB (Q2) is equal to the sum of 64 mA + 5.0 mA The ripple voltage due to the capacitance value is = 69 mA. Allow 0.8 V for the IC driver saturation × 5.9 mV and 22.4 mV due to ESR. This yields a total and 0.3 V for the drop across Rsc (0.12 2.24 A Ipk). ripple voltage of: Then the base driver resistor is equal to: Vin(min) * Vsat(IC) * VRSC * VBE(Q2) |Vout| Iout R + Eripple(p−p) + 1.5 10− 3 ) ton ) Ipk ESR B I ) I W Vref Co B 160 + 18 mV ) 5.9 mV ) 22.4 mV + 13.5 * 0.8 * 0.3 * 1.0 (64 ) 5) 10− 3 + 46.3 mV + 165.2 W, use 160 W 9. The nominal output voltage is programmed by the R1, R2 divider. Note that with a negative output voltage, the inverting input of the comparator is referenced to ground. Therefore, the voltage at the junction of R1, R2 and the noninverting input must

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STEP UP/DOWN SWITCHING Q1 +V +V REGULATOR OPERATION in L out When designing at the board level it sometimes becomes necessary to generate a constant output voltage that is less + D1 C than that of the battery. The step−down circuit shown in o Figure 16a will perform this function efficiently. However, as the battery discharges, its terminal voltage will eventually a. Step−Down Vout Vin fall below the desired output, and in order to utilize the remaining battery energy the step−up circuit shown in +V +V Figure 16b will be required. in L out D2

General Applications Q2 + By combining circuits a and b, a unique step−up/down Co configuration can be created (Figure 17) which still employs a simple inductor for the voltage transformation. Energy is b. Step−Up V V stored in the inductor during the time that transistors Q1 and out in Q2 are in the “on” state. Upon turn−off, the energy is Figure 16. Basic Switching Regulator Configurations transferred to the output filter capacitor and load forward biasing diodes D1 and D2. Note that during ton this circuit is identical to the basic step−up, but during toff the output +V Q1 +V voltage is derived only from the inductor and is with respect in L out D2 to ground instead of Vin. This allows the output voltage to be set to any value, thus it may be less than, equal to, or greater + D1 Q2 than that of the input. Current limit protection cannot be Co employed in the basic step−up circuit. If the output is severely overloaded or shorted, L or D2 may be destroyed b. Step−Up/Down Vout Vin since they form a direct path from Vin to Vout. The step−up/down configuration allows the control circuit to Figure 17. Combined Configuration implement current limiting because Q1 is now in series with Vout, as is in the step−down circuit. 1. Determine the ratio of switch conduction ton versus diode conduction toff time. Step−Up/Down Switching Regulator Design Example t V ) V ) V A complete step−up/down switching regulator design on + out FD1 FD2 toff Vin(min) * VsatQ1 * VsatQ2 example is shown in Figure 18. This regulator was designed to operate from a standard 12 V battery pack with the + 10 ) 0.6 ) 0.6 * * following conditions: 7.5 0.8 0.8 + Vin = 7.5 to 14.5 V 1.9 Vout = 10 V 2. The cycle time of the LC network is equal to ton(max) fmin = 50 kHz + toff. Iout = 120 mA 1 ton(max) ) toff + Vripple(p−p) = 1% Vout or 100 mVp−p fmin The following design procedure is provided so that the 1 user can select proper component values for his specific + 50 103 converter application. + 20 ms per cycle

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3. Next calculate ton and toff from the ratio of ton/toff in 6. A minimum value of inductance can now be #1 and the sum of ton(max) + toff in #2. calculated since the maximum on−time and peak switch current are known. ton(max) ) toff toff + * * ton ) 1 ǒVin(min) VsatQ1 VsatQ2Ǔ toff Lmin + ton Ipk(switch) − 6 + 20 10 ) * * 1.9 1 + ǒ7.5 0.8 0.8Ǔ 13.1 10− 6 − 3 + 6.9 ms 696 10 + 111 mH t + 20 ms * 6.9 ms on A 120 μH inductor was selected for Lmin. + 13.1 ms 7. A value for the current limit resistor, Rsc, can be determined by using the current limit level of 4. The maximum on−time is set by selecting a value for Ipk(switch) when Vin = 14.5 V. CT. ǒVin * VsatQ1 * VsatQ2Ǔ C + 4.0 10− 5 t IȀpk(switch) + ton(max) T on(max) Lmin + 4.0 10− 5 (13.1 10− 6) * * + ǒ14.5 0.8 0.8Ǔ 13.1 10− 6 + 524 pF 120 10− 6 Use a standard 510 pF capacitor. + 5. The peak switch current is: 1.41 A ǒton Ǔ Ipk(switch) + 2Iout ) 1 toff

+ 2 (120 10− 3)(1.9) 1)

+ 696 mA

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D2 Q1 120 μH 1N5818 MPSU51A Vout 10 V/120 mA D1 RBE + 1N5818 Co 330 300 RB 150 8 1

S Q Q2 R

170 7 2

R Ipk sc CT 0.22 OSC

Vin 6 VCC 3 7.5 to 14.5 V + 1.25 V C 100 + T Reference 510 pF − Regulator Comp 5 4 MC34063 GND

R2

R1 9.1 k 1.3 k

Test Conditions Results Δ ± Line Regulation Vin = 7.5 to 14.5 V, Iout = 120 mA = 22 mV or 0.11% Δ ± Load Regulation Vin = 12.6 V, Iout = 10 to 120 mA = 3.0 mV or 0.015%

Output Ripple Vin = 12.6 V, Iout = 120 mA 95 mVp−p Ω Short Circuit Current Vin = 12.6 V, RL = 0.1 1.54 A

Efficiency Vin = 7.5 to 14.5 V, Iout = 120 mA 74%

Figure 18. Step−Up/Down Switching Regulator Design Example

0.33 Ideally this would satisfy the design goal, however, Rsc + IȀpk(switch) even a solid tantalum capacitor of this value will have a typical ESR (equivalent series resistance) of + 0.33 Ω 1.41 0.3 which will contribute an additional 209 mV of ripple. Also there is a ripple component due to the + W 0.23 gain of the comparator equal to: Use a standard 0.22 Ω resistor. ǒVoutǓ 8. A minimum value for an ideal output filter capacitor Vripple(p−p) + 1.5 10− 3 Vref is: + ǒ 10 Ǔ − 3 ǒ Iout Ǔ 1.5 10 Co [ ton 1.25 Vripple(p−p) + 12 mV 120 10− 3 [ ǒ Ǔ 13.1 10− 6 The ripple components are not in phase, but can be − 3 100 10 assumed to be for a conservative design. From the [ 15.7 mF above it becomes apparent that ESR is the dominant

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factor in the selection of an output filter capacitor. A DESIGN CONSIDERATIONS 330 μF with an ESR of 0.12 Ω was selected to satisfy As previously stated, the design equations for Lmin were this design example by the following: based upon the assumption that the switching regulator is * ǒIoutǓ * ǒVoutǓ − 3 operating on the onset of continuous conduction with a fixed Vripple(p−p) C ton V 1.5 10 ESR [ o Ref input voltage, maximum output load current, and a Ipk(switch) minimum charge−current oscillator. Typically the oscillator 9. The nominal output voltage is programmed by the charge−current will be greater than the specific minimum of R1, R2 resistor divider. 20 microamps, thus ton will be somewhat shorter and the actual LC operating frequency will be greater than predicted. Vout R2 + R1 ǒ * 1Ǔ Also note that the voltage drop developed across the VRef current−limit resistor Rsc was not accounted for in the ton/toff + R1 ǒ 10 * 1Ǔ and Lmin design formulas. This voltage drop must be 1.25 considered when designing high current converters that + 7R1 operate with an input voltage of less than 5.0 V. If 1.3 k is chosen for R1, then R2 would be 9.1 k, both When checking the initial switcher operation with an being standard resistor values. oscilloscope, there will be some concern of circuit instability 10. Transistor Q1 is driven into saturation with a forced due to the apparent random switching of the output. The gain of approximately 20 at an input voltage of 7.5 V. oscilloscope will be difficult to synchronize. This is not a The required base drive is: problem. It is a normal operating characteristic of this type of switching regulator and is caused by the asynchronous Ipk(switch) IB + operation of the comparator to that of the oscillator. The Bf oscilloscope may be synchronized by varying the input − 3 + 696 10 voltage or load current slightly from the design nominals. 20 High frequency circuit layout techniques are imperative + 35 mA with switching regulators. To minimize EMI, all high The value for the base−emitter turn−off resistor RBE current loops should be kept as short as possible using heavy is determined by: copper runs. The low current signal and high current switch and output grounds should return on separate paths back to 10 Bf RBE + the input filter capacitor. The R1, R2 output voltage divider Ipk(switch) should be located as close to the IC as possible to eliminate any noise pick−up into the feedback loop. The circuit + 10 (20) 696 10− 3 diagrams were purposely drawn in a manner to depict this. + 287 W All circuits used molypermalloy power toroid cores for Ω the magnetics where only the inductance value is given. The A standard 300 resistor was selected. number of turns, wire and core size information is not given The additional base current required due to RBE is: since no attempt was made to optimize their design. Inductor VBEQ1 and transformer design information may be obtained from IR + BE RBE the magnetic core and assembly companies listed on the switching regulator component source table. + 0.8 300 In some circuit designs, mainly step−up and + 3.0 mA voltage−inverting, a ratio of ton/(ton + toff) greater than 0.857 may be required. This can be obtained by the addition The base drive resistor for Q1 is equal to: of the ratio extender circuit shown in Figure 19. This circuit V * V * V * V + in(min) sat(driver) RSC BEQ1 uses germanium components and is temperature sensitive. RB ) IB IRBE A negative temperature coefficient timing capacitor will help reduce this sensitivity. Figure 20 shows the output + 7.5 * 0.8 * 0.15 * 0.8 (35 ) 3) 10− 3 switch on and off time versus CT with and without the ratio + 151 W extender circuit. Notice that without the circuit, the ratio of t /(t + t ) is limited to 0.857 only for values of C greater Ω on on off T A standard 150 resistor was used. than 2.0 nF. With the circuit, the ratio is variable depending The circuit performance data shows excellent line and upon the value chosen for CT since toff is now nearly a load regulation. There is some loss in conversion efficiency constant. Current limiting must be used on all step−up and over the basic step−up or step−down circuits due to the voltage−inverting designs using the ratio extender circuit. added switch transistor and diode “on” losses. However, this This will allow the inductor time to reset between cycles of unique converter demonstrates that with a simple inductor, overcurrent during initial power up of the switcher. When a step−up/down converter with current limiting can be constructed.

http://onsemi.com 21 AN920/D the output filter capacitor reaches its nominal voltage, the 1000 s) Comparator Noninverting Input = V μ ref voltage feedback loop will control regulation. Comparator Inverting Input = GND VCC = 5 V; Ipk(sense) = VCC ° Vin = 5 V TA = 25 C

Off Time ( Time Off 100

− ton

t 8 1 ton off ton 10 S Q toff

R , Output Switch On toff Without Ratio Extender Circuit off To Scope t 170 − With Ratio Extender Circuit

7 2 on 0 t 0 1.0 10 100 100 C , Oscillator Timing Capacitor (nF) Ipk T CT OSC 1N270 Figure 20. Output Switch On−Off Time versus Oscillator Timing Capacitor 6 VCC 3 1.25 V + CT + Reference 10 2N524 − Regulator Comp 5 4 ton Ratio toff Extender Circuit Figure 19. Output Switch On−Off Time Test Circuit

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APPLICATIONS SECTION major groups based upon the main output configuration. Listed below is an index of all the converter circuits shown Each of these circuits was constructed and tested, and a in this application note. They are categorized into three performance table is included.

INDEX OF CONVERTER CIRCUITS Output 1 Output 2 Output 3 Figure Main Output Configuration Input V V/mA V/mA V/mA No. Step−Down μA78S40 Low Power with Minimum Components 24 5/50 − − 9 MC34063 Medium Power 36 12/750 − − 21 MC34063 Buffered Switch and Second Output 28 5.0/5000 12/300 − 22 μA78S40 Linear Pass from Main Output 33 24/500 15/50 − 23 μA78S40 Buffered Switch and Buffered Linear Pass from Main Output 28 15/3000 12/1000 − 24 μA78S40 Negative Input and Negative Output −28 −12/500 − − 25 Step−Up μA78S40 Low Power with Minimum Components 9.0 28/50 − − 11 MC34063 Medium Power 12 36/225 − − 26 MC34063 High Voltage, Low Power 4.5 190/5.0 − − 27 μA78S40 High Voltage, Medium Power Photoflash 4.5 334/45 − − 28 μA78S40 Linear Pass from Main Output 2.5 9.0/100 6/30 − 29 μA78S40 Buffered Linear Pass from Main Output EE PROM Programmer 4.5 See − − 30 Circuit

μA78S40 Buffered Switch and Buffered Linear Pass from Main Output 4.5 15/1000 12/500 −12/50 31 μA78S40 Dual Switcher, Step−Up and Step−Down with Buffered Switch 12 28/250 5.0/250 − 32 Step−Up/Down MC34063 Medium Power Step−Up/Down 7.5 to 14.5 10/120 − − 18 Voltage−Inverting MC34063 Low Power 5.0 −12/100 − − 33 μA78S40 Medium Power with Buffered Switch 15 −15/500 − − 15 μA78S40 High Voltage, High Power with Buffered Switch 28 −120/850 − − 34 μA78S40 42 Watt Off−Line Flyback Switcher 115 Vac 5.0/4000 12/700 −12/700 35 μA78S40 Tracking Regulator with Buffered Switch and Buffered Linear 15 −12/500 12/500 − 37 Pass from Input

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8 1

S Q

R

170 7 2 1N5819 Ipk 0.2 CT OSC

Vin 6 VCC 3 190 μH 36 V 1.25 V + + 470 pF 47 Reference − Regulator Comp 5 4 GND

Vout 15 k + 12 V/750 mA 1.74 k 270

Test Conditions Results Δ ± Line Regulation Vin = 20 to 40 V, Iout = 750 mA = 15 mV or 0.063% Δ ± Load Regulation Vin = 36 V, Iout = 100 to 750 mA = 40 mV or 0.17%

Output Ripple Vin = 36 V, Iout = 750 mA 60 mVp−p Ω Short Circuit Current Vin = 36 V, RL = 0.1 1.6 A

Efficiency Vin = 36 V, Iout = 750 mA 89.5%

A maximum power transfer of 9.0 watts is possible from an 8−pin dual−in−line package with Vin = 36 V and Vout = 12 V. Figure 21. Step−Down

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D45VH4 (1)

MBR2540 (2)

22 51 8 1

S Q T R 1.4T 170 μ 0.036 7 2 23.1 H 100 Ipk + CT 1N5819 OSC 22,000

Vin 6 VCC 3 28 V 1.25 V + + 330 pF 2200 Reference − Regulator Comp 5 4 GND

3.6 k + 1.2 k 470

Vout1 Vout2 5 V/5 A 12 V/300 m A (1) Heatsink, IERC HP3−T0127−CB (2) Heatsink, IERC UP−000−CB

Test Conditions Results Δ ± Line Regulation Vout1 Vin = 20 to 30 V, Iout1 = 5.0 A, Iout2 = 300 mA = 9.0 mV or 0.09% Δ ± Load Regulation Vout1 Vin = 28 V, Iout1 = 1.0 to 5.0 A, Iout2 = 300 mA = 20 mV or 0.2%

Output Ripple Vout1 Vin = 28 V, Iout1 = 5.0 A, Iout2 = 300 mA 60 mVp−p Ω Short Circuit Current Vout1 Vin = 28 V, RL = 0.1 11.4 A Δ ± Line Regulation Vout2 Vin = 20 to 30 V, Iout1 = 5.0 A, Iout2 = 300 mA = 72 mV or 0.3% Δ ± Load Regulation Vout2 Vin = 20 V, Iout2 = 100 to 300 mA, Iout1 = 5.0 A = 12 mV or 0.05%

Output Ripple Vout2 Vin = 28 V, Iout1 = 5.0 A, Iout2 = 300 mA 25 mVp−p Ω Short Circuit Current Vout2 Vin = 28 V, RL = 0.1 11.25 A

Efficiency Vin = 28 V, Iout1 = 5.0 A, Iout2 = 300 mA 80% A second output can be easily derived by winding a secondary on the main output inductor and phasing it so that energy is delivered to Ω Vout2 during toff. The second output power should not exceed 25% of the main output. The 100 potentiometer is used to divide down the voltage across the 0.036 Ω resistor and thus fine tune the current limit. Figure 22. Step−Down with Buffered Switch and Second Output

http://onsemi.com 25 AN920/D

Vin = 33 V

+ 33

18.2 k 1.0 k 0.22

750 pF

9 10 11 12 13 14 15 16 GND VCC

CT Ipk

OSC S Q − Comp R

+ 170

Op

1.25 V − Amp Ref + D1

8 7 6 5 4 3 2 1

Vout2 15 V/50 mA 1.8 k 22 k 0.1 130 μH

Vout1 24 V/500 mA 1N5819 + 100 2.0 k

Test Conditions Results Δ ± Line Regulation Vout1 Vin = 30 to 36 V, Iout1 = 500 mA, Iout2 = 50 mA = 30 mV or 0.63% Δ ± Load Regulation Vout1 Vin = 33 V, Iout1 = 100 to 500 mA, Iout2 = 50 mA = 70 mV or 0.15%

Output Ripple Vout1 Vin = 33 V, Iout1 = 500 mA, Iout2 = 50 mA 80 mVp−p Ω Short Circuit Current Vout1 Vin = 33 V, RL = 0.1 2.5 A Δ ± Line Regulation Vout2 Vin = 30 to 36 V, Iout1 = 500 mA, Iout2 = 50 mA = 20 mV or 0.067% Δ ± Load Regulation Vout2 Vin = 33 V, Iout2 = 0 to 50 mA, Iout1 = 500 mA = 60 mV or 0.2%

Output Ripple Vout2 Vin = 33 V, Iout1 = 500 mA, Iout2 = 50 mA 70 mVp−p Ω Short Circuit Current Vout2 Vin = 33 V, RL = 0.1 90 mA

Efficiency Vin = 33 V, Iout1 = 500 mA, Iout2 = 50 mA 88.2%

Figure 23. Step−Down with Linear Pass from Main Output

http://onsemi.com 26 AN920/D

Vin = 28 to 36 V

35 μH 0.022 D45VH10 * Vout1 15 V/3.0 mA + 470 MBR1540 100 * + 2200

22 k 2.0 k 51

910 pF 9 10 11 12 13 14 15 16 GND VCC

CT Ipk

OSC S Q − Comp R

+ 170

Op

1.25 V − Amp Ref + D1

8 7 6 5 4 3 2 1

820

TIP31 *

Vout2 12 V/1.0 mA 0.1 8.2 k

963 *All devices mounted on one heatsink, extra #10 hole required for MBR2540, IERC HP3−T0127−4CB

Test Conditions Results Δ ± Line Regulation Vout1 Vin = 28 to 36 V, Iout1 = 3.0 A, Iout2 = 1.0 A = 13 mV or 0.043% Δ ± Load Regulation Vout1 Vin = 36 V, Iout1 = 1.0 to 4.0 A, Iout2 = 1.0 A = 21 mV or 0.07%

Output Ripple Vout1 Vin = 36 V, Iout1 = 3.0 mA, Iout2 = 1.0 A 120 mVp−p Ω Short Circuit Current Vout1 Vin = 36 V, RL = 0.1 12.6 A Δ ± Line Regulation Vout2 Vin = 28 to 36 V, Iout1 = 3.0 A, Iout2 = 1.0 A = 2.0 mV or 0.008% Δ ± Load Regulation Vout2 Vin = 36 V, Iout2 = 0 to 1.5 A = 2.0 mV or 0.08%

Output Ripple Vout2 Vin = 36 V, Iout1 = 3.0 A, Iout2 = 1.0 A 25 mVp−p Ω Short Circuit Current Vout2 Vin = 36 V, RL = 0.1 3.6 A

Efficiency Vin = 36 V, Iout1 = 3.0 A, Iout2 = 1.0 A 78.5%

Figure 24. Step−Down with Buffered Switch and Buffered Linear Pass from Main Output

http://onsemi.com 27 AN920/D

Vin = −28 V 11.8 k 3.09 k + 100 275 μH

Vout

−12 V/500 mA + 470 470 1N5819 820 pF

9 10 11 12 13 14 15 16 GND VCC

CT Ipk

OSC S Q − Comp R

+ 170

Op

1.25 V − Amp Ref + D1

8 7 6 5 4 3 2 1

10 k 20 k

470 20 k 10 k −2.5 V

Test Conditions Results Δ ± Line Regulation Vin = −22 to −28 V, Iout = 500 mA = 25 mV or 0.104% Δ ± Load Regulation Vin = −28 V, Iout = 100 to 500 mA = 10 mV or 0.042%

Output Ripple Vin = −28 V, Iout = 500 mA 130 mVp−p

Efficiency Vin = −28 V, Iout = 500 mA 85.5% In this step−down circuit, the output switch must be connected in series with the negative input, causing the internal 1.25 V reference to be with respect to −Vin. A second reference of −2.5 V with respect to ground is generated by the Op Amp. Note that the 10 k and 20 k resistors must be matched pairs for good line regulation and that no provision is made for output short−circuit protection. Figure 25. Step−Down with Negative Input and Negative Output

http://onsemi.com 28 AN920/D

180 μH

T 7.75T 1.25 V 1N5819 8 1 Vout + 36 V/225 mA S Q 100

R

170 7 2

Ipk 0.22 CT OSC

Vin 6 VCC 3 12 V 1.25 V + 910 pF Reference 470 − Regulator Comp 5 4 GND

75 k 2.7 k

Test Conditions Results Δ ± Line Regulation Vin = 11 to 15 V, Iout = 225 mA = 20 mV or 0.028% Δ ± Load Regulation Vin = 12 V, Iout = 50 to 225 mA = 30 mV or 0.042%

Output Ripple Vin = 12 V, Iout = 225 mA 100 mVp−p

Efficiency Vin = 12 V, Iout = 225 mA 90.4%

A maximum power transfer of 8.1 watts is possible with Vin = 12 V and Vout = 36 V. The high efficiency is partially due to the use of the tapped inductor. The tap point is set for a voltage differential of 1.25 V. The range of Vin is somewhat limited when using this method. Figure 26. Step−Up

http://onsemi.com 29 AN920/D

T1 1N4936 Vout + L = 140 μH 190 V/5.0 mA p 1.0 To SCD 504 Display

8 1

S Q

R

170 7 2

Ipk 0.24 CT OSC

Vin 6 VCC 3 4.5 to12 V 1.25 V + + 680 pF 100 Reference − Regulator Comp 5 4 GND

4.7 M T1: Primary = 25 Turns #28 AWG 27 k Secondary = 260 Turns #40 AWG Core = Ferroxcube 1408P−L00−3CB Bobbin = Ferroxcube 1408PCB1 10 k Gap = 0.003″ Spacer for a primary inductance of 140 μH.

Test Conditions Results Δ ± Line Regulation Vin = 4.5 to 12 V, Iout = 5.0 mA = 2.3 V or 0.61% Δ ± Load Regulation Vin = 5.0 V, Iout = 1.0 to 6.0 mA = 1.4 V or 0.37%

Output Ripple Vin = 5.0 V, Iout = 5.0 mA 250 mVp−p Ω Short Circuit Current Vin = 5.0 V, RL = 0.1 113 mA

Efficiency Vin = 5.0 V, Iout = 5.0 mA 68%

This circuit was designed to power the ON Semiconductor Solid Ceramic Displays from a Vin of 4.5 to 12 V. The design calculations are based on a step−up converter with an input of 4.5 V and a 24 V output rated at 45 mA. The 24 V level is the maximum step−up allowed by the oscillator ratio of ton/(ton + toff). The 45 mA current level was chosen so that the transformer primary power level is about 10% greater than that required by the load. The maximum Vin of 12 V is determined by the sum of the flyback and leakage inductance voltages present at the collector of the output switch during turn−off must not exceed 40 V. Figure 27. High−Voltage, Low Power Step−Up for Solid Ceramic Display

http://onsemi.com 30 AN920/D

Vin = 4.5 to 6.0 V

0.022 D45VH10 * + T1 2200 Lp = 27 16.5 μH 5.1

1600 pF MR817 + 9 10 11 12 13 14 15 16 C1 22 M 500 GND VCC

CT Ipk OSC

S Q 10 − Comp R 0.033

+ 170 G.E.

Op − FT−118

1.25 V Amp Ref + D1 TRAID

8 7 6 5 4 3 2 1 Shutter PL−10

18 k 1.8 M * Heatsink, IERC PB1−36CB

120

4.7 M

Charging T1: Primary = 10 Turns #17 AWG 18 k Indicator Secondary = 130 Turns #30 AWG LED Core = Ferroxcube 2616P−L00−3C8 Bobbin = Ferroxcube 2616PCB1 Gap = 0.018″ Spacer for a Primary Inductance of 16.5 μH.

With Vin of 6.0 V, this step−up converter will charge capacitor C1 from 0 to 334 V in 4.7 seconds. The switching operation will cease until C1 bleeds down to 323 V. The charging time between flashes is 4.0 seconds. The output current at 334 V is 45 mA. Figure 28. High−Voltage Step−Up with Buffered Switch for Photoflash Applications

http://onsemi.com 31 AN920/D

Vin = 2.5 V

+ 470 40 μH 62 k 10 k 0.22 1N5819 Vout1 9.0 V/100 mA

+ 330 910 pF 27

9 10 11 12 13 14 15 16 GND VCC

CT Ipk

OSC S Q − Comp R

+ 170

Op

1.25 V − Amp Ref + D1

8 7 6 5 4 3 2 1

8.2 k

Vout2 6.0 V/30 mA 38.3 k 0.1

10 k

Test Conditions Results Δ ± Line Regulation Vout1 Vin = 2.5 to 3.5 V, Iout1 = 100 mA, Iout2 = 30 mA = 20 mV or 0.11% Δ ± Load Regulation Vout1 Vin = 2.5 V, Iout1 = 25 to 100 mA, Iout2 = 30 mA = 20 mV or 0.11%

Output Ripple Vout1 Vin = 2.5 V, Iout1 = 100 mA, Iout2 = 30 mA 60 mVp−p Δ ± Line Regulation Vout2 Vin = 2.5 to 3.5 V, Iout1 = 100 mA, Iout2 = 30 mA = 1.0 mV or 0.0083% Δ ± Load Regulation Vout2 Vin = 2.5 V, Iout2 = 0 to 50 mA, Iout1 = 100 mA = 1.0 mV or 0.0083%

Output Ripple Vout2 Vin = 2.5 V, Iout1 = 100 mA, Iout2 = 30 mA 5.0 mVp−p Ω Short Circuit Current Vout2 Vin = 2.5 V, RL = 0.1 150 mA

Efficiency Vin = 3.0 V, Iout1 = 100 mA, Iout2 = 30 mA 68.3%

Figure 29. Step−Up with Linear Pass from Main Output

http://onsemi.com 32 AN920/D

Vin = 4.5 to 5.5 V 16.5 k ‘A’ + 47 70 μH 0.22 ‘B’ 294 k 13.7 k

68 820 pF

9 10 11 12 13 14 15 16 GND VCC

CT Ipk

OSC S Q − Comp R

+ 170

Op

1.25 V − Amp Ref + D1

8 7 6 5 4 3 2 1

1.0 k

+ 2N5089 470 + 57.6 k 4.7 k 1.0 ‘X’ TIP29 470 16.5 k VPP Output 0.058 10.2 k WRITE TTL Input 47 k

3.4 k

Voltage @

Switch Position WRITE Pins 1 & 5 X VPP A < 1.5 23.52 5.24 20.95 A > 2.25 23.52 1.28 5.12 B < 1.5 28.07 6.25 25.01 B > 2.25 28.07 1.28 5.12

NOTE: All values are in volts. Vref = 1.245 V. Contributed by Steve Hageman of Calex Mfg. Co. Inc. μ Used in conjunction with two transistors, the A78S40 can generate the required VPP voltage of 21 V or 25 V needed to program and erase EEPROMs from a single 5.0 V supply. A step−up converter provides a selectable regulated voltage at Pins 1 and 5. This voltage is used to generate a second reference at point ‘X’ and to power the linear regulator consisting of the internal op amp and a TIP29 transistor. When the WRITE input is less than 1.5 V, the 2N5089 transistor is OFF, allowing the voltage at ‘X’ to rise exponentially with an approximate time μ constant of 600 s as required by some EEPROMs. The linear regulator amplifies the voltage at ‘X’ by four, generating the required VPP output voltage for the byte−erase write cycle. When the WRITE input is greater than 2.25 V, the 2N5089 turns ON clamping point ‘X’ to the μ internal reference level of 1.245 V. The VPP output will not be at approximately 5.1 V or 4.0 (1.245 + Vsat 2N5089). The A78AS40 Ω reference can only source current, therefore a reference pre bias of 470 is used. The VPP output is short−circuit protected and can supply a current of 100 mA at 21 V or 75 mA at 25 V over an input range of 4.5 to 5.5 V. Figure 30. Step−Up with Buffered Linear Pass from Main Output for Programming EEPROMs

http://onsemi.com 33 AN920/D

Vin = 4.5 to 5.5 V

+ 6800 22 k 2.0 k 0.022

μ 5.1 8.8 H 1200 pF

9 10 11 12 13 14 15 16 Vout1 2N5824 15 V/1.0 mA GND VCC + 2200

CT Ipk

OSC S Q − Comp R

+ 170

Op

1.25 V − Amp Ref + D1 47 1N5818

+ MC79L12 V 8 7 6 5 4 3 2 1 ACP out3

−12 V/50 mA 1N5818 + 47 0.1 820 D44 VH1 27 (1)

TIP29 (2)

Vout2 −12 V/50 mA 0.1 8.2 k + 47

953 (1) Heatsink, IERC LAT0127B5CB (2) Heatsink, IERC PB1−36CB

Test Conditions Results Δ ± Line Regulation Vout1 Vin = 4.5 to 5.5 V = 18 mV or 0.06% Δ ± Load Regulation Vout1 Vin = 5.0 V, Iout1 = 0.25 to 1.0 A = 25 mV or 0.083%

Output Ripple Vout1 Vin = 5.0 V 75 mVp−p Δ ± Line Regulation Vout2 Vin = 4.5 to 5.5 V = 3.0 mV or 0.013% Δ ± Load Regulation Vout2 Vin = 5.0 V, Iout2 = 100 to 500 mA = 5.0 mV or 0.021%

Output Ripple Vout2 Vin = 5.0 V 20 mVp−p Ω Short Circuit Current Vout2 Vin = 5.0 V, RL = 0.1 2.7 A Δ ± Line Regulation Vout3 Vin = 4.5 to 5.5 V = 2.0 mV or 0.008% Δ ± Load Regulation Vout3 Vin = 5.0 V, Iout3 = 0 to 50 mA = 29 mV or 0.12%

Output Ripple Vout3 Vin = 5.0 V 15 mVp−p Ω Short Circuit Current Vout3 Vin = 5.0 V, RL = 0.1 130 mA

Efficiency Vin = 5.0 V 71.8% NOTE: All outputs are at nominal load current unless otherwise noted. Figure 31. Step−Up with Buffered Switch and Buffered Linear Pass from Main Output

http://onsemi.com 34 AN920/D

Vin = 12 V

+ 47

47 k 108 μH 0.24 Vout1 2.2 k 1N5819 + 28 V/250 mA 470 180 470 pF

9 10 11 12 13 14 15 16 GND VCC

CT Ipk

OSC S Q − Comp R

+ 170 Op

1.25 V − Amp 10 k Ref + D1

8 7 6 5 4 3 2 1

100 MPSU51A

0.1 1.0 M 4.4 mH 470 Vout2 + 5.0 V/250 mA 1N5819 2200

3.6 k

1.2 k

Test Conditions Results Δ ± Line Regulation Vout1 Vin = 9.0 to 15 V, Iout1 = 250 mA, Iout2 = 250 mA = 30 mV or 0.054% Δ ± Load Regulation Vout1 Vin = 12 V, Iout1 = 100 to 300 mA, Iout2 = 250 mA = 20 mV or 0.036%

Output Ripple Vout1 Vin = 12 V, Iout1 = 250 mA, Iout2 = 250 mA 35 mVp−p Ω Short Circuit Current Vout1 Vin = 12 V, RL = 0.1 1.7 A Δ ± Line Regulation Vout2 Vin = 9.0 to 15 V, Iout1 = 250 mA, Iout2 = 250 mA = 4.0 mV or 0.04% Δ ± Load Regulation Vout2 Vin = 12 V, Iout2 = 100 to 300 mA, Iout1 = 250 A = 18 mV or 0.18%

Output Ripple Vout2 Vin = 12 V, Iout1 = 250 mA, Iout2 = 250 mA 70 mVp−p

Efficiency Vin = 12 V, Iout1 = 250 mA, Iout2 = 250 mA 81.8% This circuit shows a method of using the μA78S40 to construct two independent converters. Output 1 uses the typical step−up circuit configuration while Output 2 makes the use of the op amp connected with positive feedback to create a free running step−down converter. The op amp slew rate limits the maximum switching frequency at rated load to less than 2.0 kHz. Figure 32. Dual Switcher, Step−Up and Step−Down with Buffered Switch

http://onsemi.com 35 AN920/D

8 1

S Q

R

170 7 2

μ Ipk 88 H 0.24 CT OSC

Vin 6 VCC 3 4.5 to 6.0 V + + 1.25 V + 100 Reference 1300 pF − Regulator Comp 5 4 1N5819 GND

Vout R2 R1 + −12 V/100 mA 8.2 k 953 1000 |V | + 1.25 ǒ1 ) R2Ǔ out R1

Test Conditions Results Δ ± Line Regulation Vin = 4.5 to 5.0 V, Iout = 100 mA = 2.0 mV or 0.008% Δ ± Load Regulation Vin = 5.0 V, Iout = 10 to 100 mA = 10 mV or 0.042%

Output Ripple Vin = 5.0 V, Iout = 100 mA 35 mVp−p Ω Short Circuit Current Vin = 5.0 V, RL = 0.1 1.4 A

Efficiency Vin = 5.0 V, Iout = 100 mA 60% The above circuit shows a method of using the MC34063 to construct a low power voltage−inverting converter. Note that the integrated circuit ground, pin 4, is connected directly to the negative output, thus allowing the internally connected comparator and reference to function properly for output voltage control. With this configuration, the sum of Vin + Vout + VF must not exceed 40 V. The conversion efficiency is modest since the output switch is connected as a Darlington and its on−voltage is a large portion of the minimum operating input voltage. A 12% improvement can be realized with the addition of an external PNP saturated switch when connected in a similar manner to that shown in Figure 15. Figure 33. Low Power Voltage−Inverting

http://onsemi.com 36 AN920/D

Vin = 28 V

Rsc 0.022 2N6438 * + 4700 100 100 k 10

51 1050 1200 pF 1000 pF 9 10 11 12 13 14 15 16 GND VCC

CT Ipk

OSC S Q − Comp R

+ 170

Op

1.25 V − Amp MR822 Ref + D1 Vout

−120 V/850 mA 8 7 6 5 4 3 2 1 + 560

200 μH Center Tapped

*Heatsink IERC Nested Pair HP1−T03−CB HP3−T03−CB

Test Conditions Results Δ ± Line Regulation Vin = 24 to 28 V, Iout = 850 mA = 100 mV or 0.042% Δ ± Load Regulation Vin = 28 V, Iout = 100 to 850 mA = 70 mV or 0.029%

Output Ripple Vin = 28 V, Iout = 850 mA 450 mVp−p Ω Short Circuit Current Vin = 28 V, RL = 0.1 6.4 A

Efficiency Vin = 28 V, Iout = 850 mA 81.8% This high power voltage−inverting circuit makes use of a center tapped inductor to step−up the magnitude of the output. Without the tap, the output switch transistor would need a VCE breakdown greater than 148 V at the start of toff; the maximum rating of this device is 120 V. All calculations are done for the typical voltage−inverting converter with an input of 28 V and an output of −120 V. The inductor value will be μ μ 50 H or 200 H center tapped for the value of CT used. The 1000 pF capacitor is used to filter the spikes generated by the high switching current flowing through the wiring and Rsc inductance. Figure 34. High Power Voltage−Inverting with Buffered Switch

An economical 42 watt off−line flyback switcher is shown used. Output regulation and isolation is achieved by the use in Figure 35. In this circuit the μA78S40 is connected to of the TL431 as an output reference and comparator, and a operate as a fixed frequency pulse width modulator. The 4N35 optocoupler. As the 5.0 V output reaches its nominal oscillator sawtooth waveform is connected to the level, the TL431 will start to conduct current through the noninverting input of the comparator and a preset voltage of LED in the 4N35. This in turn will cause the optoreceiver 685 mV, derived from the reference is connected to the transistor to turn on, raising the voltage at Pin 10 which will inverting input. The preset voltage reduces the maximum cause a reduction in percent on−time of the output switch. percent on−time of the output switch from a nominal of The peak drain current at 42 W output is 2.0 A. As the 85.7% to about 45%. The maximum must be less than 50% output loading is increased, the MPS6515 will activate the when an equal turns ratio of primary to clamp winding is Ipk(sense) pin and shorten ton on a cycle−by−cycle basis. If an

http://onsemi.com 37 AN920/D output is shorted, the Ipk(sense) circuit will cause CT to charge output filter capacitor must have separate ground returns to beyond the upper oscillator trip point and the oscillator the transformer as shown on the circuit diagram. A complete frequency will decrease. This action will result in a lower printed circuit board with component layout is shown in average power dissipation for the output switching Figure 36. transistor. The μA78S40 may be used in any of the previously shown Each output has a series inductor and a second shunt filter circuit designs as a fixed frequency pulse width modulator, capacitor forming a Pi filter. This is used to reduce the level however consideration must be given to the proper selection of high frequency ripple and spikes. Care must be taken with of the feedback loop elements in order to insure circuit the layout of grounds in the Pi filter network. Each input and stability.

L1 Vout1 MBR1635 T1 5.0 V/4.5 A

12 680 100 3.3 k 6 6 1 1/2 4N35 + 1N4303 1.0 k 2200 2 +

20 Ω 15 k 0.1 1000 + 2.0 W 470 10 11 11 3.3 k TL431 20 A + Fusible Resistor 22 1N965A 5.0 V Return 1000 pF

0.1 1.0 k L2 Vout2 MUR110 12 V/0.8 A

20% 9 10 11 12 13 14 15 16

± 8 GND VCC + 1000 + CT Ipk 10 115 VAC VAC 115 OSC S Q 9

Comp 9 ±12 V − R + 1000 + Return

+ 170 4 10 Op 5

1.25 V − Amp 7 Ref + D1 Vout3 L3 −12 V/0.8 A 8 7 6 5 4 3 2 1 MTP 470 pF 4N50 *

5 0.0047 6 1.0 k 560 MPSA55 MPS6515 1N4937 UL/CSA 4 0.24

680 1.8 k 3.9 k *Heatsink 1000 pF Thermalloy 6072B−MT

T1 − Primary: T1 − Core and Bobbin: Coilcraft PT3995 Pins 4 and 6 = 72 Turns #24 AWG, Bifilar Wound Gap: 0.030″ Spacer in each leg for a primary inductance of 550 μH. Pins 5 and 6 = 72 Turns #26 AWG, Bifilar Wound Primary to primary leakage inductance must be less than 30 μH. Secondary 5.0 V: L1 − Coilcraft Z7156: 6 Turns (two strands) #18 AWG Bifilar Wound Remove one layer for final inductance of 4.5 mH. Secondary 12 V: L2, L3 − Coilcraft Z7157: 14 Turns #23 AWG Bifilar Wound 25 μH at 1.0 A

Figure 35. 42 Watt Off−Line Flyback Switcher with Primary Power Limiting

http://onsemi.com 38 AN920/D

Test Conditions Results Δ ± Line Regulation Vout1 Vin = 92 to 138 Vac = 1.0 mV or 0.01% Δ ± Load Regulation Vout1 Vin = 115 Vac, Iout1 = 1.0 to 4.5 A = 3.0 mV or 0.03%

Output Ripple Vout1 Vin = 115 Vac 40 mVp−p Ω Short Circuit Current Vout1 Vin = 115 Vac, RL = 0.1 19.2 A Δ ± Line Regulation Vout2 or Vout3 Vin = 92 to 138 Vac = 10 mV or 0.04% Δ ± Load Regulation Vout2 or Vout3 Vin = 115 Vac, Iout2 or Iout3 = 0.25 to 0.8 A = 384 mV or 1.6%

Output Ripple Vout2 or Vout3 Vin = 115 Vac 80 mVp−p Ω Short Circuit Current Vout2 or Vout3 Vin = 115 Vac, RL = 0.1 10.8 A

Efficiency Vin = 115 Vac 75.7% NOTE: All outputs are at nominal load current unless otherwise noted.

Figure 35. (continued) 42 Watt Off−Line Flyback Switcher with Primary Power Limiting

http://onsemi.com 39 AN920/D

Component Layout − Bottom View

Printed Circuit Board Negative − Bottom View

Figure 36. 42 Watt Off−Line

http://onsemi.com 40 AN920/D

Vin = 15 V

0.15 MPSU51A 1N5822 * Vout1 + −12 V/500 mA 100 100

Vout2 36.1 μH Voltage Adj + 100

2.0 k 12 k 1.5 k 270

180 pF 9 10 11 12 13 14 15 16 GND VCC

CT Ipk

OSC S Q − Comp R

+ 170

Op

1.25 V − Amp Ref + D1

8 7 6 5 4 3 2 1

6.2 k *Heatsink IERC PSC2−3

MPSU01A *

Vout2 12 V/500 mA 0.1 12 k

Tracking Adj 200

12 k

Test Conditions Results Δ ± Line Regulation Vout1 Vin = 14.5 to 18 V, Iout1 = 500 mA, Iout2 = 500 mA = 10 mV or 0.042% Δ ± Load Regulation Vout1 Vin = 15 V, Iout1 = 100 to 500 mA, Iout2 = 500 mA = 2.0 mV or 0.008%

Output Ripple Vout1 Vin = 15 V, Iout1 = 500 mA, Iout2 = 500 mA 125 mVp−p Δ ± Line Regulation Vout2 Vin = 14.5 to 18 V, Iout1 = 500 mA, Iout2 = 500 mA = 10 mV or 0.042% Δ ± Load Regulation Vout2 Vin = 15 V, Iout2 = 100 to 500 mA, Iout1 = 500 A = 5.0 mV or 0.021%

Output Ripple Vout2 Vin = 15 V, Iout1 = 500 mA, Iout2 = 500 mA 140 mVp−p

Efficiency Vin = 15 V, Iout1 = 500 mA, Iout2 = 500 mA 77.2% This tracking regulator provides a ±12 V output from a single 15 V input. The negative output is generated by a voltage−inverting converter while the positive is a linear pass regulator taken from the input. The ±12 V outputs are monitored by the op amp in a corrective fashion so ± that the voltage at the center of the divider is zero VIO. The op amp is connected as a unity gain inverter when |Vout1| = |Vout2|. Figure 37. Tracking Regulator, Voltage−Inverting with Buffered Switch and Buffered Linear Pass from Input

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SUMMARY SWITCHING REGULATOR The goal of this application note is to convey the theory of COMPONENT SOURCES operation of the MC34063 and μA78S40, and to show the derivation of the basic first order design equations. The Capacitor circuits were chosen to explore a variety of cost effective and Erie Technical Products practical solutions in designing switching converters. P.O. Box 961 Another major objective is to show the ease and simplicity Erie, PA 16512 in designing switching converters and to remove any (814) 452−5611 mystical “black magic” fears. ON Semiconductor maintains Mallory Capacitor Co. a Linear and Discrete products applications staff that is P.O. Box 1284 dedicated to assisting customers with any design problems Indianapolis, IN 46206 or questions. (317) 856−3731

BIBLIOGRAPHY United Chemi−Con 9801 W. Higgins Road Steve Hageman, DC/dc Converter Powers EEPROMs, Rosemont, IL 60018 EDN, January 20, 1983. (312) 696−2000 Design Manual for SMPS Power Transformers, Copyright 1982 by Pulse Engineering. Heatsinks IERC HeatSink/Dissipator Products and Thermal Management 135 W. Magnolia Blvd. Guide, Copyright 1980 by International Electronic Burbank, CA Research Corporation. (213) 849−2481 Linear and Interface Integrated Circuits Data Manual, Thermalloy, Inc. Copyright 1988 by Motorola Inc. 2021 W. Valley View Lane Linear Ferrite Materials and Components Sixth Edition, by Dallas, Texas 75234 Ferroxcube Corporation. (214) 243−4321 Linear/Switchmode Voltage Regulator Hanbook Theory and Magnetic Assemblies Practice, Copyright 1989 by Motorola Inc. Coilcraft, Inc. Molypermalloy Powder Cores, Catalog MPP−303U, 1102 Silver Lake Rd. Copyright 1981 by Magnetics Inc. Cary, IL 60013 Motorola Power Data Book, Copyright 1989 by Motorola (312) 639−2361 Inc. Pulse Engineering Motorola Rectifiers and Zener Diodes Data Book, P.O. Box 12235 Copyright 1988 by Motorola Inc. San Diego, CA 92112 Structured Design of Switching Power Magnetics, (714) 279−5900 AN−P100, by Coilcraft Inc. Magnetic Cores Switching and Linear Power Supply, Power Converter Ferroxcube Design, by Abraham I. Pressman, Copyright 1977 by 5083 Kings Highway Hayden Book Company Inc. Saugerties, NY 12477 mA78S40 Switching Voltage Regulator, Application Note (914) 246−2811 370, Copyright 1982 by Fairchild Camera and Magnetics, Inc. Instruments Corporation. P.O. Box 391 Switchmode Transformer Ferrite E−Core Packages, Butler, PA 16001 DS−P200, by Coilcraft Inc. (412) 282−8282 Jim Lange, Tapped Inductor Improves Efficiency for TDK Corporation of America Switching Regulator, ED 16, August 2, 1979. 4709 Golf Rd., Suite 300 Voltage Regulator Handbook, Copyright 1978 by Fairchild Skokie, IL 60076 Camera and Instruments Corporation. (312) 679−8200 ON Semiconductor does not endorse or warrant the suppliers referenced.

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