EDITED BY BRAD THOMPSON designideasAND FRAN GRANVILLE READERS SOLVE DESIGN PROBLEMS

JFET-based dc/dc converter DIs Inside

operates from 300-mV supply 94 Configurable logic gates’ Jim Williams, Linear Technology Corp, Milpitas, CA Schmitt inputs make versatile monostables  You use a JFET’s self- as large as 2 mA—enough to serve characteristics to build a dc/dc many micropowered applications or to 98 Stealth-mode LED converter that operates from power provide auxiliary bias for a higher power controls itself sources such as solar cells, thermopiles, switched-mode regulator. At 100 Data-acquisition system cap- and single-stage fuel cells, all of which 300-mV input, the circuit starts up at tures 16-bit voltage measurements deliver less than 600 mV and some- load currents of 300 A. A load current using the USB times as little as 300 mV. Figure 1 of 2 mA requires an input of 475 mV. What are your design problems shows the drain-to-source characteris- In Figure 2, Q1, a parallel-connect- tics of an N-channel JFET under zero- ed pair of Philips Semiconductor’s and solutions? Publish them here bias conditions, which you can produce (www.semiconductors.philips.com) and receive $150! Send your by connecting its gate and source BF862 , and Coiltronics’ (www. Design Ideas to edndesignideas@ together. Applying 100 mV causes a coiltronics.com) Versa-Pac trans- reedbusiness.com.

current of 10 mA to flow through the former, T1, form an oscillator in which device, increasing to 30 mA at 350 mV. T1’s secondary winding provides feed- ative voltage to Q1’s gate, which turns Exploiting the JFET’s ability to conduct back to Q1’s gate. When you first apply off Q1 and interrupts current flow significant current at zero bias makes it power, Q1’s gate rests at 0V, and drain through T1’s primary winding. In turn, possible to design a self-starting, low- current flows through T1’s primary T1’s secondary voltage collapses, and input-voltage converter. winding. T1’s phase-inverted secondary sustained oscillations begin. Although The circuit can supply 5V at currents winding responds by delivering a neg- the BF862’s published specifications do not cover the device’s internal geome- try, the device has a low on-resistance and maintains a low gate-turn-on threshold voltage. Using a pair of par-

allel-connected JFETs for Q1 ensures the low saturation voltage for operation at low power-supply . Rectifying and filtering the positive-

going flyback-voltage impulses on Q1’s drain produce a dc voltage across capac-

itor C1. To assist the circuit’s start-up, a P-channel MOSFET, Q2, which requires a gate-to-source voltage of approximately 2V for conduction, ini- tially isolates the output load from the

. When Q2 conducts, the out- put voltage increases toward 5V. Com-

parator IC1, a Linear Technology (www. linear.com) LTC-1440, draws power

from Q2’s source and imposes output- Figure 1 At 100 mV between drain and source (horizontal axis), the drain by comparing its current reaches 10 mA (vertical axis) and increases to 30 mA at 300 mV. internal voltage reference with a sam- ple of the output voltage. The output

MAY 25, 2006 | EDN 91 designideas

from IC1 varies Q1’s on-time through Q3 to close the control loop and main- tain output-voltage regulation. Figure 3 shows the voltage present at the ’s output. When the

output voltage decays, comparator IC1 (Trace B, middle) and allows

Q1 to oscillate. The resulting flyback events at Q1’s drain (Trace C, bottom) restore the output voltage.

Using Q3 as a simple but effective shunt control for Q1’s gate voltage results in a 25-mA quiescent-current drain from the power source. A modi- fication reduces the quiescent drain to

1 mA (Figure 4). Inserting Q4 in series with T1’s secondary winding more efficiently controls Q1’s gate. Bootstrapping the voltage across T1’s secondary winding produces negative- Figure 3 The dc output (Trace A), comparator IC ’s output, and the voltage turn-off-bias voltage for Q4. Figure 5 1 at Q ’s drain (Trace C) have a horizontal-deflection factor of 5 msec. illustrates how to connect T1’s wind- 1

7 + 3 8 IC1 LTC1440 _ 4 C3 5 1.18V 6 0.01 F REFERENCE OUT

R3 100 0.3 TO R2 1.6VIN 1.21M

5 T1 3 PRIMARY R1 D1 SECONDARY 3.83M 1N5817 D 7 6 S Q2 D 5 V , C + OUT C + 2 2 mA MAXIMUM Q 1 100 F 1 6.8 F TP0610L G G C D 4 2 S 0.001 BAT-85 D

Q VN2222L G 3 S

NOTES: 1. USE 1%-TOLERANCE METAL-FILM FOR R1 AND R2. 2. CONNECT T1 AS SHOWN IN FIGURE 5. 3. Q1 COMPRISES PHILIPS BF862 JFETs CONNECTED IN PARALLEL.

Figure 2 A pair of parallel-connected JFETs allows this dc/dc converter to operate from power sources that supply as little as 300 mV.

92 EDN | MAY 25, 2006 designideas

ings. When Q4 switches off, it inter- peak voltage would approach 15V and 0.8V appear at Pin 5, necessitating the rupts the current flowing in T1’s sec- reverse-bias Q4, an undesirable condi- use of two series-connected to ondary winding and drives T1’s Pin 5 tion. Under normal operating condi- clamp the voltage at a safe level. Zener positive. Without diodes D4 and D5, the tions, excursions of approximately D3 holds off bias-supply loading to aid start-up during initial power S R4 Q4 1M BF862 application.EDN G D 0.3 TO 1.6VIN R3 D 5 6 D 51 + TO R 1N4148 4 C5 3 1N4148 T1 10 F 5 3 5VOUT, 2 mA D MAXIMUM 2 5 Q 1N4148 D1 2 7 6 1N5817 TP0610L 4

S D D D + + 2 C C 1 D 1N751 G 1 2 3 6.8 F G 100 F 3 12 1N4148 5.1V TO VIN D S R1 PRIMARY SECONDARY G 3.83M C4 6 9 Q 1% METAL TO Q +1 F 1 1 11 BF862 S FILM DRAINS

8 12V 10 3 Q 7 3 8 IC1 C TP0610L 3 LTC1440 0.01 F 7 1 TO Q1 4 T 5 R2 1 GATES 6 1.21M R 5 1% METAL 470k 1.18V REFERENCE FILM OUTPUT Figure 5 Comprising six independ- ent windings that offer more than NOTES: 500 configurations, Coiltronics’ 1. USE 1%-TOLERANCE METAL-FILM RESISTORS FOR R1 AND R2. 2. CONNECT T AS SHOWN IN FIGURE 5. 1 VP1-1400 serves as a combination 3. Q1 COMPRISES PHILIPS BF862 JFETs CONNECTED IN PARALLEL. 4. T1 = COILTRONICS VP1-1400. feedback and flyback in this application. Connect the wind- Figure 4 Adding Q3, Q4, and the bootstrapped negative-bias generator compris- ings as shown. ing D2, D3, and C4 reduces the circuit’s quiescent current from 25 mA to 1 mA.

inversion of one input. These devices Configurable logic gates’ Schmitt feature inverted outputs, overvoltage- input tolerance, and high current drive. inputs make versatile monostables Every input has hysteresis, making Glenn Chenier, Allen, TX these devices ideal for timed pulse gen- eration. A design that combines digi-  You can assemble a pulse-gener- input logic gates and found only “old tal logic with analog interfaces often ation circuit from a simple faithfuls”—familiar Schmitt-input requires timed pulses and delays, along Schmitt-input AND gate plus a resis- AND gates and Schmitt buffers. with pulse shorteners and stretchers. tor- timing network. Howev- Disappointed, I investigated other For applications in which exact pulse er, if you need a logic function that’s not logic offerings from Fairchild and stum- times are not critical, the added feature a standard catalog item, you need a bled across a section of the Web site of Schmitt inputs allows the delay of Schmitt-input gate or inverter and an that describes “configurable logic one input using an RC (resistance- additional logic gate. Drawing from an gates.” Lo and behold, I suddenly real- capacitance) timing network. When earlier Design Idea (Reference 1) and ized I was looking at the solution to my the slowly changing RC circuit’s output a recent design requirement for adding problem. The NC7SZ57 and NC7SZ- crosses the analog-level upper- or lower- pulse-generation functions to a crowd- 58 (Reference 2) comprise tiny, six-pin trip-point thresholds, the Schmitt fea- ed pc board, I searched Fairchild Semi- surface-mount packages that you can ture converts the slowly rising and conductor’s Web site (www.fairchild configure as inverters or as AND, OR, falling voltages to fast digital edges. semi.com) for small-footprint Schmitt- or XOR gates, all of which allow the Texas Instruments (www.ti.com)

94 EDN | MAY 25, 2006 designideas

offers functional equivalents—the SN- gered by both the rising and the REFERENCES 74LVC1G57 and SN74LVC1G58 falling edges, enabling it to function 1 Roche, Stephan, “Add a Schmitt- (Reference 3). Both companies’ de- as a frequency doubler for generating trigger function to CPLDs, FPGAs, vices offer upper- and lower-trip-point- strobe pulses on rising and falling and applications,” EDN, Oct 13, voltage thresholds averaging 37 and clock edges. You can make any invert- 2005, pg 104, www.edn.com/

63%, respectively, of VCC, or approxi- ing-gate configuration into an oscil- article/CA6262539. mately one RC time constant on the lator by feeding back its inverted out- 2 “NC7SZ57/NC7SZ58, TinyLogic rising or the falling edges. According to put to an RC-delayed Schmitt input UHS Universal Configurable 2-Input the published data sheets from the and enabling the gate’s remaining Logic Gates,” Fairchild Semiconduc- manufacturers’ Web sites, Texas In- input. However, once the XOR oscil- tor, April 2000, www.fairchildsemi struments’ versions impose somewhat lator’s remaining gate switches off the conductor.com/ds/NC/NC7SZ57 tighter tolerances on the analog oscillation, the gate’s output state pdf. threshold levels and thus deliver hangs at either a one or a zero to pro- 3 “SN74LVC1G57 Configurable tighter timing tolerances than do the duce a truly random state derived Multiple-Function Gate,” Texas Instru- Fairchild parts. from the oscillation’s nonsynchronous ments, November 2002, http:// For digital-analysis purposes, any relationship to the timing of the dis- focus.ti.com/lit/ds/symlink/ voltage below the upper trip point for abling input.EDN sn74lvc1g57.pdf. a rising edge effectively represents a logic zero, and any voltage above the lower trip point for a falling edge rep- DEVICE CONNECTIONS INPUT PIN 5 V resents a logic one. These conditions CC PIN 2 GND are true only after the input crosses a UPPER PIN 3 VARIES AS SHOWN TRIP POINT RC CIRCUIT'S OUTPUT respective trip point, such as a rising LOWER edge that approaches but never crosses TRIP POINTS the upper trip point. This voltage

remains a logic zero, even if the volt- INPUT 1 OUTPUTS' OUTPUT age then drops back to ground poten- 4 DELAYED RISING tial on its falling edge. R 6 EDGE

Figure 1a shows some typical circuit C PIN 3 VCC implementations. Note that these cir- INPUT cuits lack some of the niceties of gen- 3 4 OUTPUT uine monostables. For example, a cir- R DELAYED FALLING 6 EDGE cuit doesn’t retrigger until after its RC PIN 1 GND network has stabilized or about five C time constants have elapsed. The RC INPUT 1 time constant must be five times short- 4 OUTPUT R FALLING-EDGE er than the time between triggering 6 PULSE events. Devices from the SN74LVC- C PIN 3 GND 1G57 family produce the waveforms in INPUT Figure 1b, and circuits using the SN- 6 4 OUTPUT RISING-EDGE 74LVC1G58-family devices produce R 1 PULSE the inverse of these waveforms. The C PIN 3 GND circuits’ operation is straightforward. INPUT The RC circuits delay one input, so 1, 3 4 OUTPUT that the inputs momentarily rest at FREQUENCY R 6 opposite states. When one RC time DOUBLER constant elapses, the delayed voltage C GATED crosses the Schmitt upper- or lower- INPUT 1, 3 OSCILLATOR trip-point thresholds, and the delayed 4 OUTPUT RANDOM- input catches up to the straight- R 6 STATE GENERATOR through input. C Of unusual interest and unlike the usual variety of monostable that trig- (a) (b) gers only from a voltage transition in one direction, the XOR implementa- Figure 1 One gate plus an RC network (a) can deliver a range of useful tion functions as a monostable trig- timed outputs (b).

96 EDN | MAY 25, 2006 designideas

Stealth-mode LED controls itself and triggers one-shot IC . The one- Howard Myers, Greensboro, NC 2A shot turns on Q1 for an inter-  Since the LED’s invention more it turns off. The circuit’s main compo- val, lighting the LED for approximate- than 30 years ago, its emission nents comprise LED D1, micropower ly 3 msec until the one-shot’s output efficiency has steadily increased, and, operational IC1, one-shot goes low. In a darkened room, the cycle although it may surprise you, the IC2A, and transistor switch Q1 to con- repeats at a 200-Hz rate, and the LED increased conversion efficiency works trol current through the LED. blinks repeatedly with short off periods. in two directions. Certain bright, effi- When dark, the LED produces no At high flash rates, the LED appears to cient LEDs, such as Hewlett-Packard’s photovoltaic current. When moderate be continuously on. (www.hp.com) HLMP-EG30-NR000, lighting, such as that in an office or a The circuit’s current drain in the day- a red emitter molded in clear encapsu- lab, illuminates it, it generates 50 to light state mainly comprises the current lation, also exhibit significant photo- 100 mV into a 4.7-M load . driving the reference-bias network: voltaic action. The circuit in Figure 1 Comparator op amp IC1 compares the 3.6V/162 k 22 A. In both day and shows how you can put an LED’s pho- voltage that the LED produces with a night modes, with the LED drawing a tovoltaic characteristics to work. threshold reference voltage of approx- few milliamperes when illuminated, a Using the same components, older, red imately 50 mV. You can vary the cir- battery that can deliver 1 Ahr would LEDs also function but with lower light cuit’s sensitivity threshold by altering power the circuit for a couple of

output in this circuit. This Design Idea the values of resistors R1 and R2 in the months. You can reduce the current by circuit describes an LED that controls that connects to IC1’s increasing the values of R1 and R2. itself by determining whether it’s on or Pin 2. Given the circuit’s low and intermit- off without the assistance of any light When ambient light decreases, the tent current drain in a well-lighted sensor other than its own characteris- LED produces less voltage, and, when environment, a 1-Ahr lithium cell’s tics. When you darken the LED, it the voltage falls below the 50-mV service life should approach its shelf turns on, and, when you illuminate it, threshold, the op amp’s output goes low life.EDN

REPEATED ONE-SHOT 3.6V PERIODS WHEN LED WHEN LED SEES DARKNESS SEES LIGHT ONE- SHOT 0V

R5 Q 10k R 1 1 2N2907 LED SEES 160k LIGHT DETECTION R 16 3 3.6V 4 THRESHOLD LED SEES R6 470 LITHIUM VCC RESET 100k VOLTAGE 2 7 DARKNESS 7 CELL IC Q 1 6 5 IC OP-90 2A 3 4 ½MC14528 4 2 CXRX R R 2 3 D1 C1 2.2k 4.7M RED LED VSS GND 0.22 F 1 8

NC NOTE: CONNECT IC2B'S UNUSED INPUTS TO GROUND. 14 11 10 NC

IC2B 12 NC 9 15 13

Figure 1 An efficient LED forms the heart of a light-sensitive “mystery lamp” that contains no apparent .

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Data-acquisition system captures 16-bit Based on a Cypress (www.cypress. voltage measurements using the USB com) CY7C63743 controller, USBmi- Terry Millward, Maxim Integrated Products Inc, Blonay, Switzerland cro’s (www.usbmicro.com) U421 USB- interface module provides as many as 16  The USB has become the inter- make a simple, eight-channel, 16-bit I/O lines and an option to use some of face of choice for connecting to measurement system. The MAX1168 those lines as an SPI port at selectable PCs. Available on all relatively modern includes eight input channels, an SPI clock rates of 62.5 kHz, 500 kHz, 1 MHz, PCs, the USB offers a standard con- (serial-peripheral-interface) port, a or 2 MHz. Firmware on the U421 allows nector and can supply power to periph- 4.096V reference, and a clock oscillator. generic access to SPI read-and-write erals at 5V and as much as 100 mA of The MAX1168 operates from a 5V sup- devices, and the device’s general-purpose current. The circuit in Figure 1 com- ply and can convert individual channels, I/O lines can serve as slave-select lines bines Maxim’s (www.maxim-ic.com) execute multiple conversions on one for addressing multiple SPI devices. One MAX1168, a low-power, 16-bit ADC, channel, or scan the channels sequen- I/O line controls the MAX1168’s chip- with a small USB-interface module to tially and store measured data on-chip. select input. When you use it with an

10 51 AVCC AVCC

0.1 F10 F 0.1 F FB1 0.1 F150 F 0.1 F _

MAX CH0 +4230 AVCC DVCC

AVCC DSEL

0.22 F _ 5V MAX AIN0

CH1 DSPR USB +4230 100 pF AVCC DSPX 0.22 F AIN1

J1 _ 100 pF USB

MAX CONNECTOR CH2 +4230 AIN2 IC101 USB AVCC USBMICRO 100 pF U421 5V 1

0.22 F _

MAX CH3 +4230 2 USB D AIN3 AV CC IC

100 pF 100 3

0.22 F MAX1168 USB D _ MAX

AIN4 USB CH4 + 4230 DGND 4

AVCC 100 pF EOC PA.0

0.22 F _ AIN5 DOUT PA.6/SPI MISO

MAX CH5 +4230 DIN PA.5/SPI MOSI 100 pF

AVCC AIN6 SCLK PA.7/SPI SCK 0.22 F

CS PB.0 _ MAX

AIN7 NC CH6 +4230

AVCC 100 pF

0.22 F _ MAX

CH7 +4230 REF REFCAP AGND AGND DGND DGND

100 pF 1 F 0.1 F 0.22 F

FB2 NOTE: RESISTOR-DIVIDER PAIRS ARE PRECISION-MATCHED, 100-k MAX5490s. Figure 1 This simple data-acquisition system provides eight channels of 16-bit data to a host computer through a USB interface.

100 EDN | MAY 25, 2006 designideas

1 HID (human-interface de- of /11, to allow maximum read- vice), the U421 USB con- able inputs of 45V at resolu- troller can transfer data at rates tions of 687.5 V. as high as 800 bytes/sec. With Written in Microsoft’s Visu- additional filtering to reduce al Basic.Net, Standard Edition, noise, the USB port provides the evaluation software pro- 5V power to the circuit. vides commands to the U421 The MAX1168’s sample- through the USBm.dll DLL and-hold circuit must acquire (dynamic-linking-library) file. the input voltage and charge The demo program sets the its 45-pF holding capacitor in MAX1168 to scan all eight 3 sec and thus requires a fast channels and display the amplifier to minimize acquisi- results. When you run the pro- tion errors. Available in dual gram, the Visual Basic form and quad versions, the MAX- allows you to set the reference 4230 provides a 10-MHz voltage to allow for the input bandwidth, 2V/sec slew rate, Figure 2 User-interface software for the data-acquisi- divider, select the scan time, rail-to-rail inputs and outputs, tion system allows selection of operating parameters. and enable any of the eight and the ability to operate from In this image, the lower three channels are unselected input channels for screen dis- a 5V rail or from voltages as and hence are not visible in the display. play (Figure 2). You can down- low as 2.7V. The MAX4230’s load the evaluation software at bias current—typically, 50 pA—allows ing, each buffer amplifier’s input in- www.maxim-ic.com/MAX=1168DI.EDN significant input impedance without cludes a 100-k precision-matched affecting accuracy. resistive divider. This application uses ACKNOWLEDGMENT To provide protection from over- Maxim’s MAX5490VA10000 10-to-1 Thanks to Robert Severson of USBmicro voltages and apply input-voltage scal- dividers, which provide a scaling factor for his help with the interface.

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