Development of Wafer-Level Chip Size Package (WL-CSP)

by Toshiaki Asada *, Toshiaki Amano *, Kazuhito Hikasa *, Ken’ichi Sugahara *, Hirofumi Oshima * and Yoshimi Ono *2

Recently electronic equipment have remarkably improved becoming more com- ABSTRACT pact and lighter and having upgraded function, requiring semiconductor pack- ages mounted thereon to be more compact, thin-bodied and lightweight as well as to enable high-density mounting on substrates. Thus a new semiconductor package called wafer-level chip size package (hereafter called WL-CSP) technology is drawing attention. In response to such situations, the authors have developed a new WL-CSP, in which a tape sub- strate is bonded with wafers in a continuous roll-to-roll manufacturing process enabling cost reduction and quick delivery, and a resin post structure is adopted for the terminal pads to ensure high reliability. This paper reports on the structure, manufacturing process and results of prototype manufacturing of Furukawa Electric’s original WL-CSP, together with its features and reliability test results.

1. INTRODUCTION semiconductor packages mounted on these electronics Recently electronics products represented by mobile products are keenly required to be more compact, thin- phones, mobile computers, personal digital assistance bodied and lightweight as well as to enable high-density (PDA) and digital still cameras (DSC) have been remark- mounting on substrates. See Figure 1. ably improved becoming more compact and lighter and Against this background, a new semiconductor packag- having upgraded function. Along with such market trends, ing technology called WL-CSP is drawing attention, where

１９８７ １９９３ ２００１ ２００４ ２０１０ １９８７１９８７ １９９３ ２００１ ２００４ ２０１０２０１０ Trend in アナログ デジタル ＦＯＭＡ i-mode 第４世代 アナログAnalog デジタルDigital ＦＯＭＡFOMA i-mode Fourth第４世代 generation mobile phone カラー液晶 カメラ付き Ｆｅｌｉｃａ モバイルマルチメディア Colorカラー液晶 LCD, Built-inカメラ付き camera ＦｅｌｉｃａFelica Mobile multi-media

WL-CSP: Real chip-size (Stack→Si-penetrating electrode) package, where chips are Chip stacking redistributed, electrode formed → ＳＩＰ and resin sealed in a wafer

process to make individual Package stacking pieces.

ＷL-CSP ＳＯＢ CSP BGA function upgrading QFP SOP DIP Miniaturization, weight reduction, SIP Peripheral Area pad To 3D- pad adptive new technology

Insertion mounting Surface To 3D- mounting adptive new technology

Figure 1 Trend in semiconductor packaging technology.

* Ecology and Energy Laboratory, R&D Division *2 Production Technology Development Center, Production Technology and Engineering Division

Furukawa Review, No. 31 2007 13 Development of Wafer-Level Chip Size Package (WL-CSP) chips are packaged plainly as in the wafer state. In the semiconductor chips. The FBTI which may be called a WL-CSP process, all the steps including redistribution, tape substrate with soldered bumps is manufactured by a electrode formation, resin sealing and dicing are carried continuous method named roll-to-roll method, aiming at out in a series of wafer processes, and the size of a semi- cost reduction. conductor chip finally cut from the wafer corresponds to The FBTI has been applied to semiconductor packages its package size. Thus the WL-CSP process can be said called TQON (Thin Quad Outline Non-Leaded) and SBM ideal from the standpoint of miniaturization and weight (System Block Module) at Toshiba Semiconductor reduction, so that the process has already been employed Company. The structure of these products is such that Au in mobile phones and so forth. We have developed a new stud bumps formed on semiconductor chips are flip-chip WL-CSP manufacturing technology, in which a soldered bonded to SnAg solder bumps on the FBTI, and high reli- tape substrate is bonded to wafers enabling quick deliv- ability has been confirmed in these applications. In view ery and cost reduction. And we have adopted a resin post of these achievements, and based on the idea of combin- structure for the terminal pads on the mounting substrate, ing the two technologies, i.e., the tape substrate manufac- and confirmed its high reliability. In this paper, the turing technology for FBTI aiming at cost reduction and achievements of this high-bonding reliability WL-CSP the flip-chip bonding technology having proven reliability manufactured by the new process will be reported. through applications, we considered it was highly feasible to realize Furukawa’s original WL-CSP, and embarked on 2. DEVELOPMENTAL BACKGROUND OF the development accordingly. FURUKAWA’S WL-CSP 3. CONCEPT OF FURUKAWA’S WL-CPS Furukawa Electric has developed FBTI (Flexible Bumped Tape Interposer) 1) as an interposer for semiconductor Figures 4 and 5 show the structures of copper post-type devices to cope with weight reduction, height lessening WL-CSP with an established track record in the market and speed upgrading, and began marketing the product and Furukawa’s WL-CSP, respectively. The copper post- in 2001. The FBTI is an interposer designed on the pre- type WL-CSP commercially available has a characteristic sumption of using flip-chip bonding that is more suited for structure in which copper posts 100 µm in height are space saving and high-frequency operation than the con- formed on the wafer redistribution to ensure the reliability ventional wire bonding. As shown in Figures 2 and 3, the of mounting with the substrate. The manufacturing pro- interposer comprises SnAg solder bumps formed on a cess of the copper post-type WL-CSP includes forming of tape substrate to be used for electrical connection with redistribution to build routing circuitry on the wafer, forma- tion of copper posts and resin sealing, necessitating spe- cial manufacturing equipment required by the wafer pro- Flip-chip mounting surface Conductor SnAg SolderSolderololderder 基 導体 Bump Substrate材 cess. Moreover, the plating process for formation of cop- per posts constituting the characteristic structure takes much time, and the delivery time allegedly takes a rather Pitch:150Pitch : 150µmpµm Bumpバンプ部 Bump diameterDiameter：75 µm long time because the manufacturing starts at the time of Bump Height:10height:10～25 µm wafer reception. Product appearance Mounting pad surface ViaVia SnAgSnAg Substrate基 SolderSolder-plated めっき Via ViaVia部 材 Al pad PI layer Cu re-distribution

UBM Pitch:500Pitch : 500µmpµm Via diameterDiameter ：: 150150 µm IC Via Height:2.0height : 2.0～～16.0 µm

Figure 2 Appearance of FBTI.

Top view Epoxy seal Cu post

Figure 4 Schematic structure of commercially available WL-CSP. BGA pad

Al pad Adhesion Au stud bump

DCA pad with SnAg solder bump IC Polyimide film Passivation (Glass epoxy) Bottom view Solder plated

Cu pattern Cross-section Figure 3 Schematic structure of FBTI. Figure 5 Schematic structure of Furukawa’s WL-CSP.

Furukawa Review, No. 31 2007 14 Development of Wafer-Level Chip Size Package (WL-CSP)

On the other hand, the manufacturing process of the named DDR3-DRAM which will come on the market in the Furukawa’s WL-CSP can be broadly divided into three: future. manufacturing of the tape substrate with resin posts, for- mation of Au stud bumps on the wafer and bonding of the 4. TECHNOLOGICAL PROBLEMS WITH wafer and the tape substrate. See Figure 6. With regard to the manufacturing process of the tape substrate with resin FURUKAWA’S WL-CSP posts, application of the roll-to-roll manufacturing process In the manufacturing process of commercially available for tape substrates with an established track record for WL-CSP, routing circuitry is formed on the wafer, so that FBTI is expected to result in cost reductions. Moreover, the wafer processes including direct application of photo- because manufacturing of the tape substrate can be start- definable elastomer on the wafer, exposure, development, ed upon receipt of design information on the wafer, only metal plating, and etching are carried out directly on the the later manufacturing processes of Au stud bump for- wafer. Wafer processes for semiconductors are typically mation and bonding of the wafer and the tape substrate employed to deal with the crucial points of manufacturing are to be carried out after receipt of the wafer, thus such as precise alignment of the exposure mask on to the enabling quick delivery. wafer. On the other hand, manufacturing of Furukawa’s The structure of Furukawa’s WL-CSP is characterized WL-CSP comprises, differing completely from that of com- by its terminal pad --called resin post, containing resin. mercially available WL-CSP, the process of flip-chip bond- WL-CSPs are generally used with their terminal pads ing the Au stud bumps formed on the wafer to the solder loaded with solder balls, and they are mounted on the bumps formed on the tape substrate, and this presented mounting substrate. The mounting reliability of electronic two major technological problems. One is the high level components such as semiconductor packages is usually of dimensional accuracy required for the tape substrate, evaluated by means of thermal shock test. In the case of and the other is high-precision bonding of the tape sub- WL-CSP which is mounted on substrates using solder strate and the wafer. balls, its reliability is influenced by a cracking mechanism The dimensional accuracy required for the tape sub- such that a mechanical stress is applied to the solder strate depends on the design parameters such as I/O pad balls due to the difference in the coefficients of thermal pitch of the semiconductor chip, and can be derived as expansion between a semiconductor chip made of silicon shown in Figure 9, which was calculated on the following and a mounting substrate called FR-4 printed circuit assumptions; formation accuracy of Au stud bumps: board, generating cracks either between the WL-CSP and ±3.5 µm; mounting accuracy between tape substrate and the solder balls or between the mounting substrate and the solder balls. These cracks can grow to cause fatigue failures, and this constitutes a main cause of malfunction. Silicon wafer Condition

That is to say, in terms of reliability test conditions, the Copper Resin layer Copper post height: 100 µm lower the stress on the solder balls, the longer the lifetime Joint height: 90 µm Solder layer until failure. Stress analysis based on simulation of the -40℃⇔+125℃ thermal shock test Glass-epoxy Maximum stress: 914 MPa terminal pad structure shows, as illustrated in Figures 7 substrate and 8, that the resin post structure results in a reduced maximum stress at the solder joints than the copper post structure, and thus it is expected that the joint lifetime is improved. In the Furukawa’s WL-CSP, moreover, the Au stud bumps on the wafer (i.e., semiconductor chip) are flip- chip bonded to the solder bumps on the tape substrate. Figure 7 Calculated stress distribution of commercially avail- Since this flip-chip bonding of Au to SnAg has a track able WL-CSP. record in semiconductor packages as mentioned before, and this structure is advantageous in terms of high-fre- Condition quency operation, the Furukawa’s WL-CSP is thought to Protrusion height: 50 µm be promising to cope with a high-speed memory device Joint height: 50 µm -40℃⇔+125℃ thermal shock test Maximum stress: 284 MPa

Inversion Au bumps formed on wafer

Roll-to-roll process, where Wafer bonding by Back-grinding/dicing Pick & place into tray tape substrate with SnAg Au/SnAg flip-chip solder bumps are formed bonding

Figure 6 Concept of Furukawa’s WL-CSP manufacturing pro- cess. Figure 8 Calculated stress distribution of Furukawa’s WL-CSP.

Furukawa Review, No. 31 2007 15 Development of Wafer-Level Chip Size Package (WL-CSP) wafer: ±5 µm; tip diameter of Au stud bump: 15 µmφ; the market to acquire some equipment with a mounting and minimum gap: 25 µm. It can be seen that, assuming accuracy specification of ±5 µm, but due to its unique an I/O pad pitch of 80 µm for a semiconductor chip using process behaviors we were unable to find out any. 8-in wafer, the position accuracy of the solder bumps on Accordingly, we at the Production Technology Development the tape substrate is required to be not greater than about Center developed an alignment press machine in-house, 19 µm over 100 mm (i.e., the center to periphery distance and the machine is currently used to manufacture proto- of 8-in wafer). In the future, if the I/O pad pitch of semi- type products for performance evaluation. See Figure 11. conductor chips becomes narrower, or larger wafers (say At present, when a tape substrate and wafer are bonded 12-in) are used, it would be necessary to take appropriate together, the position accuracy of Au stud bumps in rela- measures to cope with such changes, including: 1) to tion to solder bumps has been confirmed to be satisfacto- reduce the tip diameter of Au stud bump, 2) to adopt nar- ry. See Figure 12. rower minimum gaps, and 3) to improve the accuracy of tape substrate. In manufacturing the tape substrate for 5. RELIABILITY EVALUATION the Furukawa’s WL-CSP, material handling of substrate and suppression of its deformation constitute important Reliability evaluation procedures can be divided into reli- technical points because the continuous manufacturing ability evaluation of the WL-CSP itself (hereafter called pri- scheme of roll-to-roll method is employed together with mary mounting reliability evaluation) and that of the sub- the use of tape substrates susceptible to deformation. By strate-mounted WL-CSP using solder balls (hereafter combining appropriate measures such as selection of fix- ing carrier material for the substrate, ingenious fixation Setting of work → Up-down alignment through image processing method and circuit formation method, we have succeed- ed in achieving a position accuracy of ±5 µm. See Figure 10. To improve the position accuracy further, it would be necessary to control the tape manufacturing environment including temperature and humidity. Bonding process of the tape substrate and wafer after → Temporary press → Transfer → Vacuum press alignment, constituting the second problem, is also spe- About 0.1 atm 3 ton max cific to the Furukawa’s WL-CSP. Mounting accuracy at this process obviously influences the position accuracy of the substrate, so that bonding equipment is required to be as good as possible in mounting accuracy. We investigated

30 Assumptions (position accuracy) 25 Accuracy of Au stud bump: ±3.5 µm Tip diameter of Au stud bump: φ15 µm

） Bonding accuracy: ±5.0 µm Minimum gap: 25 µm ｍ

µ 20 （

15

10 tape substrate 5 Figure 11 Appearance of alignment press machine. Position accuracy required for 0 40 50 60 70 80 90 100 Semiconductor I/O pad pitch（µm） Au stud diameter: 60 µm Figure 9 Position accuracy required for the tape substrate. SnAg bump diameter: 150 µm

Tape substrate accuracy for 8-in wafer 100 mm

テープ基板のはんだバンプ位置精度 テープ基板のはんだバンプ位置精度 0.0200 0.02000.0200 内 0.0150 以 m ｍ

0.01500.0150 µ 差 差

0.0100 μ ５ 公 公 0.01000.001500 ± ±5 の の ） ） 0.00500.0050 ら ら

ｍ ｍ 0.0000 か か

ｍ ｍ 0.00000.0000

-0.0050 １ １ ２ ２ ３ ３ ４ ４ ５ ５ 心 心 り り （ （ 程 程 程 程 程 程 程 程 程 程 --0.00500.0050 が が （mm） 中 中 工 工 工 工 工 工 工 工 工 工 -0.0100 上 上 Finish 仕 仕 ト ト --0.01000.01500 ー ー

--0.01500.0150 Process 4 Process 5 Process 1 シ シ

-0.0200 Process 3 --0.02000.0200 Process 2 プロセス Processプロセス Tolerance from sheet center

Figure 10 Position accuracy of solder bumps on the tape sub- Figure 12 Confirmation of position accuracy of WL-CSP using strate. soft X-ray image.

Furukawa Review, No. 31 2007 16 Development of Wafer-Level Chip Size Package (WL-CSP) called secondary mounting reliability evaluation). of this semiconductor package. Thus reliability of Au/ The sample chip used for reliability evaluation is an SnAg flip-chip bonding was confirmed. evaluation TEG chip 6.3-mm square having pads of 48 pins around the chip periphery, as shown in Figure 13. 5.2 Reliability of Secondary Mounting The most commonly used printed circuit board of FR-4 5.1 Reliability of Primary Mounting was adopted as a substrate for evaluating the mounting The tape substrate was designed in such a way that, reliability. The mounting pad pitch was 0.5 mm, and when a WL-CSP consisting of a TEG chip and tape sub- SnAgCu solder balls 0.3 mm in diameter were used. Two strate is mounted on a substrate for secondary mounting types of samples were evaluated paying attention to the reliability evaluation, a daisy chain is formed. Bonding chip thickness and solder ball layout, and the results are conditions of the tape substrate to the wafer was opti- shown in Figure 14. One was in peripheral pad layout mized in terms of deformation of Au stud bumps, flow of having 48 mounting solder balls on the periphery ---the SnAg solder around Au stud bumps, and thickness of the minimum number necessary for creating a daisy chain, insulation layer. and its chip thickness was 530 µm, while the other was in With respect to the contents of evaluation, after each an area array pad layout having solder balls at a 0.5-mm test item shown in Table 1 was performed, the terminal pitch, and its chip thickness was 200 µm. pads were confirmed for presence or absence of conduc- Figure 15 is the Weibull distribution of the failure rates tion by the four-terminal method, along with abnormalities obtained by the reliability evaluation, where the conduc- confirmation by observation of the appearance and the tion of the daisy chain created by the mounting substrate cross-section. In the cross-section observation especially, and WL-CSP was monitored during thermal shock test close attention was paid to crack generation at the Au/ (-40℃ to 125℃, held 7 min at each temperature). The SnAg bonding portions as well as to layer peeling at the blue line shows the results for peripheral pad layout using semiconductor chip/adhesive layer and at the tape sub- solder balls with a chip thickness of 530 µm, whereby it is strate/adhesive layer. demonstrated that the initial development target of 400 The results of reliability evaluation for the current proto- cycles at a failure rate of 1% has been achieved. The red typing show that all samples passed the tests satisfactori- line in turn shows the results for area array pad layout ly as shown in Table 1, demonstrating excellent reliability using solder balls with a chip thickness of 200 µm, corre- sponding to a total package thickness of 280 µm exclud- ing solder balls. It can be seen that better results are obtained here, rendering not only small area packages but also thin packages sufficiently promising. With com- ～～～～～～mercially available WL-CSPs, it is allegedly difficult to

Reliability evaluation of WL-CSP itself

～～～～～～

Reliability evaluation of substrate-mounted WL-CSP

6.30 Perspective view of the chip from the top Blue: Wiring pattern on tape substrate 5.00 Black: Mounting pad Red: Wiring pattern on chip Green: Flip-chip bonding portion Peripheral pad layout Area array pad layout Thickness of mounting substrate: 0.8 mm (FR-4, pattern on both sides) Figure 14 Comparison of surface mounting methods. Pad diameter: φ230 µm Solder ball: φ300 µm SnAgCu

6.30 5.00 Chip thickness: 530 µm，200 µm Y-PLOT Mounting pad diameter: φ230 µm 3 99.999 Mounting pad pitch: 0.5 mm 99.99 99.9 Chipﾁ thickness:ｯﾌﾟ厚530μ 530ｍｔ µmt 2 99 Peripheralﾍﾟﾘﾌ ｪpadﾗﾙ実 layout装 Number of mounting pad 95 90 6.30 1 80 5.00 Area array pad layout: 121 70 60 0 50 Peripheral pad layout: 48 40 30 -1 20 6.30 5.00 15 Figure 13 Sample for reliability evaluation. 10 -2 7 5 4 -3 3 2 1.5 Chipﾁ thickness:ｯﾌﾟ厚200μ 200ｍ µmt -4 Table 1 Conditions and results of PKG reliability test. 1 Area arrayﾌﾙｱﾚ padｲ実 装layoutｔ 0.7 0.5 6.306.30 -5 0.4 -40℃⇔+125℃ 5.00 0.3 held 7 min at each temperature 0.2 各７分保持 -6 0.15 Test Condition Failure rate 0.1 0.07 -7 0.05 6.30 5.00 0.04 Thermal shock -65 ⇔ 150℃ 1,000 cycles 0/22 0.03 -8 0.02 Accumulated failure rate F(t) (%) 0.015 0.01 -9 High temp. storage 150℃ 1,000 hrs 0/10 Accumulated failure rate lnln(1-/(1-F(t))) -10 10 100 1000 10000 Autoclave ℃ 0/10 121 85%RH 500 hrs Number of cycles (times) Pre-conditioning 85℃ 85%RH 168 hrs 0/22 （JEDEC） 250℃ reflow 3 pass Figure 15 Solder joint reliability test results.

Furukawa Review, No. 31 2007 17 Development of Wafer-Level Chip Size Package (WL-CSP) reduce the chip thickness due to rather large stresses between the hard metal compound layer and the soft sol- resulting from the fact that the copper post is 100 µm in der layer, and they grow to cause fatigue fracture. Given height and that a thick resin layer is used to embed the the fact that the Furukawa’s original WL-CSP having a copper posts. In contrast with this, Furukawa’s WL-CSP proprietary structure of resin post fractures in the same has great possibilities of reducing the chip thickness mode as for the common BGA components mounted on lower than that evaluated at this time, because it under- substrates using solder balls, it can be said that they goes back grinding process after bonding the wafer and share the same concept of reliability for mounting sub- the tape substrate. strates. From this standpoint, we are making efforts to Now let us consider the failure mechanism of WL-CSP. promote study to ensure reduced height and improved Failure analysis of cross-sections observed after thermal reliability. shock tests suggests that failures occur between the sol- der ball and the mounting substrate or the WL-CSP, and 6. CONCLUSION more precise observation reveals that cracks are created at the interface between CuSn compound ---a hard sub- We have recently developed WL-CSP, an ideal package in stance made by diffusion of copper into solder, and sol- terms of miniaturization and weight reduction, using a der which is rather soft. With respect to the location of manufacturing process completely different from conven- fracture occurrence, a major influence is exerted on the tional wafer process, whereby the tape substrate is bond- solder balls on the four corners, because these are where ed to the wafer. It has been confirmed that the new pro- the stress due to the difference in the coefficients of ther- cess makes quick delivery and reduced cost compatible, mal expansion between the semiconductor chip and the and bonding reliability for mounting substrates is ensured substrate tends to concentrate on. In accordance with through the adoption of a new structure in which the ter- this, in actual evaluation, it has been confirmed that con- minal pads comprise resin posts. We have confirmed the ductivity NGs occur at the solder balls on the four corners possibility of thin-bodied packages using the WL-CSP, very often. since good reliability has been confirmed for a thin pack- Observation of peeled surfaces on the solder balls age 200 µm in chip thickness, corresponding to a total reveals a continuous striped pattern which runs perpen- package thickness of 280 µm excluding solder balls. dicularly from the WL-CSP’s corners to the center. See While commercially available WL-CSPs are only applied Figure 16. From these analyses, it can be seen that the to high-yield wafers since they are manufactured by wafer failure mechanism is such that due to repeated strains processes, Furukawa’s WL-CSP enables individual mount- generated by the difference in the coefficients of thermal ing of selected KGDs using a flip-chip bonder. Moreover, expansion between the semiconductor chip and the when it comes to semiconductor chips having multitudes mounting substrate, cracks are generated at the interface of I/O pads, all the mounting pads can not be placed on the bottom face of the chip to configure the fan-in, but in case of individual mounting of chips the fan-out layout by placing mounting pads on the outside of the chip is per- mitted. Thus, this WL-CSP is expected to develop as a high-reliability semiconductor package with resin posts for terminal pads.

反射電子像 Traveling direction of fracture 破壊進行方向

Ｃu6Sn5

Enlargement

CuSＣnu3Slayern 銅箔 REFERENCE Peeled surface on solder ball 1) Hikasa et al., “Development of Flexible Bumped Tape Interposer”, Figure 16 Analysis of failure. Furukawa Review, No.24, pp.59-64 (2003)

Furukawa Review, No. 31 2007 18