/ Single-chip encoder-decoder converts NRZ into Manchester code

LSI chip works with multiprotocol controllers to transmit synchronous data and clock signals in one bit stream

by Le ster Sanders, Horris Corp .. Melbourne. Rs.

O Multiprotocol controll crs are data-link control chips establish a much more accurate data lin k as well. that perform many of the communicatin g fun ctions Encoding and dccoding data in Manchester code also between digital systems. As intell igent circuits, they cl im inatcs a number af limitati ons inhcrent in NRZ cod­ assume many tasks that would otherwise require the ing. Tf the data paltern transmitted is alllogical Os or 15. altention of a central processing uni!. When used with NRZ reprcsents this as a static voitage levei in a dc synch ronous protocols, for example, they handle such wavcform. The disadvantage, however, is that it is more functions as [rame synchroniza tion, control information, difficult to couple an amplifier in de than in ac, which address gcneration and recognition, and errar checking. using Manchester coding permits. Tn additio n, there can In synchronous communication, multiprotocol control­ be considerable low-frequency noise in the data-commu­ lers usuall y represe"t data in nonreturn-to-zcro code. nica ti on link. Since the Manchester code has no dc or But now, with the Harri s HD6409 Manchester encoder­ low-frequency camponents, a li the noise can be rejected decoder-the first based on a large-scale integrated with a bandpass receivcr. chip- a network ca n reap the benefits of both transmit­ Fina ll y, using Manchester code provides a measure of ting Manches ter-encoded data and using multiprotocol error dctcction for every bi t transmittcd. Of cou rsc, controllers by encodin g NRZ into Manchester 11 code where dc coupling is available. at slower data rates in and decoding Manchester 11 back into NRZ (see "When cnvironmcnlS th at are nol clcctrica ll y noisy, ar wherc a to prefer Manchester coding," p. 106). very low error rate is not required, NRZ may be perfectly A s thcir na me indicatcs, using multiprolocol control­ adequate. But where these conditions do not cx ist, the lers makes it possible to handle most of the common one-chip LS t approach of the 6409-as opposed to the data-communication protocols. :fhese in clude byte-con­ prcvious more cxpcnsive implemcntations with 15 to 20 trolled protocols, such as IBM'S Binary Synchronous small-scale integrated chips-may prove cost-elrective. Communications Protocol (Bisync), and bit-oriented The 6409 (Fig. I) is designed for private-wire, limited­ ones, such as IBM'S Synchronous Data Link Control distance (Iess than a mile) seri al data Iinks. It may (SDLC). They also take care of the Tntern ational Stan­ opcrate as cither a converter ar a repcater. dards Organization's High-Level Data-Link Control As a repeatcr, lhe devicc serves to rccovcr lhe am pli­ (HDLC) and the American ational Standards Insti­ tude or phase to ensure data integrity a nd mai ntain a tute's Advanced Data Com- spccific systcrn bit-errar munica tions ContraI Proce­ 1. Unique. l he HD6409 Manchester encoder-decoder chip has no ra te on long or noisy da ta dure (ADCCP), as well as LSI counterparts on lhe markel. l he complemenlary-MOS chip is bul links. As a converter, one byte-count protocols, such 11 4 by 75 mils and conlains aboul 2.500 transislors. 6409 operates at the as Digital Equipment tr ansmittcr cnd af a seri­ Corp.'s Digit al Data Com­ a l data link encodin g munica ti on: Control Proce­ NRZ code into M anches­ dure (DDCM·P). ter li, while another at Usin g Manchester code the receiving end decodes ca n rcdu ce transrni ss ion line the Manchester II code costs by eliminating the cus­ into NRZ. Because the tomary c1 0ck wire as it 6409 operates at a data includes both the c10ck and rate of up to I megabit data in a single se ri al data per secand, it is compati­ slream. Also, beca use Man­ ble with mos t DLCS that chester code has belter syn­ generate NRZ code. chronization prope rti cs lh an The use of a 6409, or NRZ, the chip may not only any synchronous dcvicc further ofn oad processing 5uch as a mu ltiprotocol tasks from the CPU, but also controll cr, in a nct wo rk

Eteclronics / July 28. 1982 105 fo-' ~ When to preter Manchester coding " . ~ , ~,.~: ~ For th~, overwheiming majority of data-communicatlon determine~ whether the data is a O or a 1. This transition I, networks,' nonreturn-to-zero (NRZ) codlng satlsfies ali' occurs in the middle of each data pell. If i~ is a low to hlgh r. data-transmission requirements. In fact, NAZ is the stan- transition, the binary value ofthe data is'a O, whiJe if it is a : dard by which ali olher codes are measured, since It high to low transition. it is a 1. ,',:' "" , requlres no éncoding or decoding and makes efficlent use The trequency response of. an NAZ.sig'nal is trom ,dc to of a communlcation channel's bandwidth. Almost ali exist- half the clock rate, while thatofManchester,is trom half I ing digital integrated circuits' for data communications 'the clock rate· to the full' clock rate. Since·a· code's !: employ some form of it., : " ,', ' " ' bandspread ratio (the ratio otihê maximum' to minimum • However" NAZdoes have some inherentdeficiencies' frequency) is an important parámeter'in the design of a'- that makealternative codes such as NAZ-inverted (NAZI) . receiver for serial data-Iink applications, the',advantages of and Manc~ester 11 codlng' necessary, as 'shown in (a) 'of: Manchester éoding, are obvious. The frequency response ~. 'the, figure at theright For example, data-lilÍk controllers of Manchester co de extends' one' octàve,while for NRZ, i.' use N~Z ~coc;te when tra~srnitting asynchronous data. B~t half the clock. rate divided by.. dê (or zero) is undefined and t for synchronous' dat::. transfer, or for operàtlon' Ina loop extends in practice somewhere In the range of 5 to 10 ~ configuration, NAZI with ,automatlc zerolnsertion and octaves .. This bandwid,th advantage, issignificant because f,: deletion is better because it achleves a lower error rate. ~ Jt is considerably easier to design a narrowband than a ~', NRZ, NAZr, and Manchester coding define' multioctave' receiver~"Further, lhe commonly used single­ (" , signal~ For ~xampie, the serial data stream at the top of sldeba~d~or pf1as~-baseéJ çfata-communica• f.~ part [a)of thefiguré is '100110. NAZ represents súch a tioo netWorkswóufdrequir~·additiolÍàl éircuitry in order to ~ " data' streáin' a'S':8: series.of voftage leveis that' ,rema,in, l1andledcsignal('" ':." ',' -':,:~'~':~"'"',- . ":.~: " " f: constantfor lhe duratlon 'of each bit period. ,'", ,,', ,,;;':"~ In additiori to' thé advantáges mentioned, the mld-bit ~ 'In NAZI, alsoknown' as NRZ~mark, a foglcal 1 isrepre- 'transitlori ,'of Ma-ricnester cade mà,y tie used to detect ~ ::: .. sented by .no çh~lnge in the "state ~f ~he preceding da~a "" déta:-transmissiC?n ,errors. ,For~~xan1ple, suppose that dur­ ~: cell and a logical,O bya changeln.thatcell's state. Tl1us,lng abi1cell a1.~a~ represe~ted in the upper row of (b), is L assee'n in the figure. It Is', possibletor, a, f, or'a.b to be: ,transmitted~ IfÍloise 'oh ttie. tran'smisslon..line producesa [: .repre~'nted ,by, a 'Iow 'or' hlg~ J~gic: leyel.)\', !óng, s'trlng ;~f ',: !ÔQ.i# :,i,nye~io,~':'Jf tn~""s~c~~~:.~~!f..' ~f the data, cell, the ~' consecutive 1s will produce' a statio fevel,. whlle ,contiguous: slgn,ál'wlll; be,'~çfete9ted: a~)r.ansrnittecl as in the second ~; Os willproçtuce án altemating slgnai waveform: .,:':.:.~:,' ';'~~,"> row;: Si~é~ ,_th~: .~ási~ ó~,: tr~}Aa~~h~ster sqheme Is that ' ~. ' By çontrast. Manchester,code represents bln,ary'values' 'each' dat~:éell niust':'con~âin:,a:'rriid:cell transition, the ~. ; with. a levei transltlon.' The directlon of the levei frahsltión absencê of a rrild-ceIrtralÍsitiOn 1$ detected as an Invalld ~.. ~ ,." ~! ". : ., ..... ~ . ; •. ". . , '~ •. ,' .~',~ ;.',.:,. ~.,'~ ".:.~'~:J"~" ... ' - ,.,

depends on the communications tasks at hand. OLCs such sequence of eight Manchester Os and a synchronization as universal asynchronous receiver-transmitters are pattern (Fig. 2b), but otherwise appears transparent to effective for interfacing slow, asynchronous peripherals the frame. like keyboards or other man-machine interfaces. How­ Although data is usually transmitted in byte-wide ever, machine-machine interfaces benefit from the trans­ packets, receivers of bit-oriented protocols must be able mission of synchronous data. to recognize the closing ftag at any time. It is noi Synchronous data.. transfer frames blocks of data rath­ sufficient to recognize the boundary of such a packet. To er than characters, allowing greater throughput for do their job, most OLCs have residual character-handling block-type data structures that are communicated techniques that, when confronted with an information between computers. For example, downloading large field that is not an integral number of bytes wide, add programs or sharing common data bases in a multipro­ extra bits to the final character. cessing environment often requires large blocks of data Further, since synchronization is the process whereby to be transferred. The throughput gained using synchro­ individual data cells or groups of data cells are delin­ nous rather than asynchronous data transfer can be eated by a clock or a frame, a receiver must be able to considerable. With this increased rate of data transfer, detect the location of individual data cells that represent the probability of error also increases, warranting the Os and 1s on a bit basis. This is true whether increased error-detection capabilities as well. synchronization takes place on frames or characters. One problem with synchronization in the bit-oriented Timely timing SOLC frame is that the data in the information field can Ali synchronization to incoming data ultimately takes reproduce the bit pattern of the opening and closing place on the basis of bits and either characters or frames. ftags. If this happens, then a closing ftag is detected For example, asynchronous devices such as UARTs syn­ prematurely. To prevent this, multiprotocol controllers chronize on individual characters with start and stop bits rely on a function known as automatic zero insertion and enclosing the data word. In bit-oriented protocols such as deletion. Since the bit pattern of the closing ftag is SOLC, the opening and closing ftag bits of the frame are Olll1110, when tive consecutive Is appear in the data used by the receiver to synchronize to frames. stream following the opening ftag, the transmitter auto­ A typical synchronous bit-oriented protocol frame matically inserts a O after the tifth 1. At the receiver, consists of an opening ftag; address, control, and infor­ this is deleted prior to error checking. mation fields; a frame-checking sequence (FCS); and a In addition to frame synchronization in bit-oriented c10sing ftag (Fig. 2a). The 6409 generates an initial protocols, ftags may also serve as time-tilling interframe

106 Electronics/July 28, 1982

", characters. To understand how this is done, it is neces­ waveform alternates before or after each data cell. sary to go into some details of the frame structure. Thus, with this scheme, a transition will occur at least The address and control fields are referenced by the once every five data cells and at the beginning of the opening ftag, while the ~CS is referenced by the c10sing data eell. For protocol controllers, NRZI supports syn­ ftag. The closing ftag terminates the frame, but also chronous operation, which requires that the c10ck be provides a reference point to identify the 16 bits that recovered from the received serial data stream. NRZI is constitute the FCS. Thus, ali bits between the control commonly used to eliminate the c10ck wire for short-haul field and the FCS are part of the information field. data Iinks. With it, some reeeiver designs also use an As a result, interframe fill characters are either ftags analog phase-Iocked loop in the c10cik recovery. or abort characters or else a combination of the two. If Keeping in sync data is not avaiJable at the transmitter, itmay send an abort character, which indicates to the receiver that it In the 6409, bit synchronization depends on a digital should invalidate the frame. phase-Iocked loop (DPLL) to determine the time the Automatic zero insertion' plays a major role in auto­ receiver needs to sample or logically determine the value matic c10ck recovery in an NRZ-encoded data transmis­ of the transmitted binary data. Optimally, this takes· . sion. Data transitions in such a serial data stream nomi- plaee midway between ali data transitions. Given the '-, nally occur at predetermined positions. For exa.mple, typical nonzero rise and fali times of signals on transmis­ with NRZ and the related NRz-inverted, transitions can sion lines, this approach allows the time to occur at the beginning or end of a data cell. In contrast, reaeh its true value. for Manchester coding, there is always a transition in the A DPLL was chosen for the 6409 because its adjust­ middle of each data ceU. These transitions provide a ments for a time-varying data stream are bidireetional, a reference that enables a receiver to recover its c1ock. necessity when the data network is in the commonly used Since NRZ can not guarantee transitions in the loop eonfiguration. The Intel 8273 DLC employs a some­ encoded waveform, it is not a self-clocking. code. Cou­ what . similar OPLL algorithm, and Western Digital's pled with automatic zero insertion and deletion, how­ 1933 also uses one. However, many DLCs do not depend ever, NRZI does provide transitions for the receiver to on a DPLL, sinee of the bit-oriented protocols, only SLDC recover the clock from the serial data stream. For exam­ supports this loop configuration. pIe, if ali 1s are transmitted, automatic zero insertion A c10ck oscil1ator operating at either 16 or 32 times and deletion inserts a transition once every five data the data rate, a transition detector, a sample counter, cells. If ali Os are to be transmitted, the NRZI signal and auxiliary logic comprise the DPLL. Its operation is

Electronics/ July 28. 1982 107 OPENING AODRESS .CONTROl FRAME·CHECKING CL()SING ., ,-'-FLAG·. INFORMATION SEQUENCE . FLAG 0111111 (ANV NUMBER OF BITS) ., ' (80R . (8 OR : . (8 BITS) 16 BITS) 16 BITS) (16 BITS) (8 BITS)

(a)

2. Bit picking. In the HD6409 encoder­ decoder chip. the information in the bit­ oriented protocol frame (a) is preceded by 8 MANCHESTER lOGICAl Os COMMAND I DATA eight Manchester Os, a command synchro- SVNCHRO' nizatlon pulse. and two valid Manchester bits "i NIZATlON (b) (b). The length of the data block following is user-defined. straightforward. Upon initialization, depending on the izes at least once every data cell during its transition. speed of the oscillator selected, two data points are FunctionalIy, the 6409 consists of c1ock, control, set-mid count (MC) and end count (EC). MC is the encoder, and decoder sections. The clock rate is common count on the· sample counter at which the receiver to both the encoder and decoder, and a multi pie of either expects a data tiansition to occur; EC is the count at 16 or 32 times the input frequency can be selected. For a which the counter expects to sample. If the 16 X mode is given input c1ock, such as 16 megahertz, the data rate is used, MC is 4 and EC is 8, while if the 32 X speed is therefore twice as fast in the 16 X mode as in the 32 X selected, MC and EC are 8 and 16, respectively. mode. Thus, if data rates in the I-Mb/s range are In terms of the data-bit cell length, EC occurs one desired, the 16 X mode should be. selected. quarter of a data cell after MC (Fig. 3). ~ince in Moreover, for lower data rates, the 32 X mode permits Manchester code, transitions sometimes occur in the greater timing margin since the internai operation beginning as well as in the center of the data cell, this of the decoder has increased resolution. The clock pulse end-count occurrence plac'es the sample at one quarter of may be supplied externally through the c1pck input pin, a data cell after or midway between transitions. or the on-chip oscillator may be used. If the latter alternative is chosen, a crystal, a resistor, and two capac­ Period adjustment 01 itors are added. Whether the externai c10ck or on-chip The DPLL adjusts the 6409 to any speed variations in oscillator is selected, a buffered clock output may be the received data stream. Speed ftuct~ations are detected used for other system clocking. when the receiver registers a transition earlier or later The encoder in the 6409 acts as a transmitter on a than the expected mid count-a condition determined by serial data link in that it accepts NRZ data at its input whether the samplc"counter has a lower or higher count and encodes this into Manchester 11, which is transmit­ than MC when the transition occurs. The sample coun~er ted out on the logically cómplementary pins, bipolar-O counts the oscillator and is reset to zero when a sample is out and bipolar-l out. This arrangement is convenient madeat EC. beca use some line drivers require data input in this If the data transition is detected earlier than formato In addition, the data sent is inverted for use with expected-that is, the data rate exceeds what is inverting line drivers. expected - the DPLL takes a sample one clock cycle Preliminary pulse earlier than scheduled, at EC - 1. If the data transition takes place Iater than expected (the date rate is slower Prior to accepting data for encoding, the 6409's encod­ than expected), the sample is taken one c10ckcycle later er generates a synchronization pulse 3 bits wide that than scheduled, or at EC + I. precedes a data frame with 11/2 data bits in one logic In operation, the receiver looks at every transition and state and follows it with 1112 bits in the opposite state. resynchronizes on the basis of where that transition This data is shifted serially into the 6409 internai shift occurs. Because it is known where transitions are register. For synchronization to occur, the synchroniza­ expected, receivers can recover the clock by Iooking at tion pulse, followed by 2 valid Manchester bits, must where they actually occur with respect to where they be received by the decoder. nominally should occur. Since MancheSter code has so As noted, the 6409 can encode la~ge blocks of data many transitions on which to synchronize, errors do not with only the synchronization sequence as overhead. . accumulate over successive adjacent data cells. This sequence is sent to the decoder as a serial data The difference in synchronization using the NRZI with stream consisting of eight Manchester Os followed the automatic zero insertion and deletion and using Man­ synchronization pulse, which is an invalid Manchester chester code is determined by the number of transitions pattern initiated by an externally generated high to low in the·data cell. The first method can go five data cells transition and the 2 valid Manchester bits. During the without resynchronization, while the latter resynchron- first 10 bits of the synchronization sequence, the encod-

108 Electronics/ July 28. 1982 CLOCK

UNIPOLAR DATA IN

UDI SAMPLE CDUNTER FC 1112131MCISl61FCll 1213IMCI~fl~fl~1IECI~~11 121~~I~CI~lCI~fl~~IECI~~11 121~nMCI~fl~fl!~IECI FC ' FC DATA TRANSITION t t t er- SC <; MC lit- COMPUTED SC> MC SC < EC FINAL COUNT FC c EC-1 FC li EC + 1 FC .. EC+ 1 by 'O- SAMPLE ,t Us t t t

I is EC · END COUNT FC .. FINAL COUNT MC .. MIO COUNT SC lO SAMPLE COUNT

3. Locked loop. A digital phase-Iocked loop generated in the HD6409 samples the data rate of a multiprotocol controller. lhe sampling algorithm is shown for early, late, or no transitions. Here the clock rate Is 16 times the data rate, but 1i can be twice that. ' >1, >n er-c1ock signal remains low so that it does not strobe sary to reset the decoder between frames, as the synchro­ er data into the send-data input. Near the end of the nization pulse will perform this chore. ' a sequence, it becomes an active clock at the data rate. Manchester' data received is decoded into NRZ and is is ExternaI circuits supplying NRZ data into the send-data output on the serial-data-out pin. The decoder-c1ock X input must be synchronized' such that the data meets the signal synchronizes this NRZ data output with the multi­ re minimum setup and hold times around the fa11ing edge protocol'controll~r receiving the data. AIso required to of this clock signal.' . receive' data from the decoder is the nonvalid Man­ ts For i~s part in the 6409's operation, the decoder chester signal (NVM), which serves two functions. It is an )fi receives data in either the unipolar data-in input or indicator to externai circuits as to whether or not NRZ se b~polar l-in and O-in inputs. If the bipolar l-in and O-in data out of serial-data-out is properly decoded data, and n, are used, unipolar data-in must be held low. If unipolar it is also an error detector. er data-in is used, bipolar l-in is tied high and bipolar O-in Since incoming Manchester data is decoded randomly c­ is tied low. While some standards such as RS-232-C even before and during the synchronization pulse, the ip define an unbalanced line, the differential data described externai circuits know that the data intended to be )e is required by other types of line drivers and receivers. decoded is valid only when' NVM is high. Thus, NVM is monitored along with the decoder-c1ock. signal to deter­ Taking delivery a mine when to accept the NRZ data. There is a 2-bit delay lt The decoder synchronizes to the pre-frame synchro­ between the incoming data, whether bipolar or unipolar, t­ nization sequence generated by the encoder. The eight beca use the 2 valid Manchester bits in the synchroniza­ ·0 Manchester Os are supplied the DPLL of the decoder with tion pattern must be detected prior to synchronization. lt a sufficient number of transitions for it to synchronize The second function' of the NVM output, error detec­ is upon start-up. Furthermore, the decoder's internai cir­ tion, verifies that a transition has occurred at mid-cell. If :h cuitry resets its internai counters and synchronization the decoder receives invalid Manchester-encoded data, circuits upon detection of the 5-bit-wide pattern consist­ synchronization must be reestablished, with the encoder ing of the 3-bit-wide synchronization pulse followed by regenerating its synchronization sequence. the 2 valid Manchester bits. Since the 6409 can encode and decode indefinitely 1- Decoding circuitry in the 6409 will recognize the after the initial synchronizati~n sequence, its data frame lt synchronization pulse, and initial synchronization to will not interfere with the controller's protocol, whatever ic data will take place only when this occurs. The impor­ it may be, Simply put, the 6409 appears to the controller e. tant point here is that the decoder must detect 10 logic as a synchronous modem. Not only is the data format rt 'states in the incoming data to establish synchronization. transparent, but ali interface signals between the 6409 l­ The probability of 10 logic states simultaneously being and the controller are direct, eliminating the need for ;t induced by noise on the transmission line and an initiat­ processor intervention. In addition, as with most DLCs, ing false synchronization is low. The criterion for syn­ the 6409 operates on a 5-volt power supply. a chronization is purposely made as complex as this Control signals from the controller to the 6409 are 1.' because if the, initial synchronization is not established also no problem. DLCs generally have modem control a properly, then it cannot be expected la ter. signals for interfacing data terminal equipment with .e Tnternally, a 2 X c10ck shifts the incoming serial data data-circuit-terminating equipment. These standard sig­ :r into a shift register. Logic-decoding circuitry in the nals, most often used in modems that communicate data N register will detect the 5-bit-wide synchronization pat­ over phone lines, make the connections straightforward. e tern and reset the internaI counters. Although the input For its part, the 6409 provides the timing signals to c10ck 1-. reset wil1 also reset the decoder outputs, it is not neces- the transmitter and receiver of the controller. O

Electronics / July 28, 1982 109