RMo1B-2 Scalable Analytical Model of 1.7 THz Cut-off Frequency Schottky Integrated in 55nm BiCMOS Technology

Vincent Gidel123, Fréderic Gianesello1, Pascal Chevalier1, Grégory Avenier1, Nicolas Guitard1, Victor Milon1, Michel Buczko1, Charles-Alex Legrand1, Cyril Luxey2 and Guillaume Ducournau3 1STMicroelectronics, France 2Polytech’Lab, Univ. Nice Sophia A., France 3IEMN, UMR CNRS 8520, France [email protected]

Abstract—In this paper, an innovative Schottky II. INNOVATIVE ARCHITECTURE IN 55 NM architecture is proposed and implemented in 55 nm BiCMOS BICMOS TECHNOLOGY technology. A State-of-the-art 1.7 THz cut-off frequency is measured and an analytical scalable model is proposed and A. Schottky diodes state-of-the-art experimentally validated paving the way for further performance The first ever integrated Schottky diode has been developed improvement. In addition, this analytical model can be integrated in III-V technology using whiskered architecture [5]. The in a Design Kit library in order to enable sub-THz Schottky diode- evolution of the fabrication processes allowed the development based circuit designs in advanced BiCMOS. of planar architecture in order to facilitate integration inside a Keywords— Schottky diode, modeling, THz. chip. The progress of silicon technologies to address high I. INTRODUCTION frequency applications enables to support planar Schottky diode architecture. In CMOS technologies, lateral architecture Our connected society asks a never ending consumption for with Shallow Trench Insulation (STI) has been proposed first more data, which requests a continuously growing demand for [6], [7], [8] and then polysilicon spacer architecture has higher data rates therefore driving the carrier frequencies to be emerged in order to reduce achievable series resistance of the extended up-to the millimeter wave (mmW) [1] and even diode [9], [10]. The major limitation of CMOS structure is terahertz (THz) range. Recently, a new standard (802.15.3d- linked to parasitic substrate capacitance which reduces 2017) has been established around 300 GHz by the IEEE, and achievable performances in antiparallel configuration [11]. In data rates up-to 100 Gb/s has already been demonstrated in [2]. BiCMOS technology, leveraging the buried collector module From the transmitter side, such high data rates have been dedicated to bipolar has enabled to develop an achieved with III-V technologies using photonics-based improved resistive Schottky diode [7]. However, in advanced techniques leveraging their intrinsic broadband and linear BiCMOS technology, the collector is not buried deeply enough performances. But as it was the case some years ago for the and a deeper layer, requiring a specific implantation, is needed previous developments at mmW frequencies, silicon is today to avoid an increase of the parasitic capacitance [12]. starting to seriously compete with those photonics-based transmitters leveraging Silicon Photonics developments [3]. B. Proposed Innovative Schottky Diode Architecture Consequently, the question is now to determine the Taking advantage of those state-of-the-art results, we feasibility of high performance sub-THz receivers in silicon propose here a new Schottky diode architecture (Fig. 1) technology. At such high frequencies, mixer first receiver is the leveraging both the advantages of CMOS architecture and architecture of choice. Available Local Oscillator (LO) power specific bipolar process steps available in BiCMOS technology. being a constraint, subharmonic mixer is a natural choice and state-of-the-art Sub-Harmonics Mixer (SHM) are today implemented in III-V using Schottky diodes [4]. The availability of high-performance Schottky diodes in advanced CMOS or BiCMOS technology could then make feasible the development of a full silicon-based chipset solution enabling higher integration and low-cost solution. In this paper, we present in section II an innovative Schottky diode architecture implemented in 55 nm BiCMOS process. In section III, we propose an analytical model for this Schottky diode which is validated by experimental characterizations in section IV. (a) (b) Fig. 1. Innovative BiCMOS 55nm Schottky Diode: (a) Side-cut view; (b) Top view The proposed architecture of the diode takes advantage of the polysilicon spacer developed in CMOS technology combined with the Nsinker implantation (in order to reduce

978-1-7281-1701-0/19/$31.00 © 2019 IEEE 23 2019 IEEE Radio Frequency Integrated Circuits Symposium series resistance) and deep trenches module [13] of bipolar linked to metallic access CBE (Back-End capacitance) from the transistor (in order to reduce the substrate parasitics). junction capacitance Cj0. An extracted cut-off frequency of 1.7 THz is obtained which represents a state-of-the-art value (Fig. 3). 2 [13] SiGe BiCMOS 90nm 1.8 BiCMOS 55 nm (this work) 1.6 1.4 CMOS 130 nm [6] 1.2 (a) (b) [9] [8] 1 Fig. 2. Schottky diode layout with: (a) 1 Anode fingers; (b) 4 Anode fingers SiGe BiCMOS 130nm

Fc (THz) 0.8 As depicted in Fig. 1, the metal- junction has 0.6 [10] been integrated at the surface on the Nwell with NiSi silicide 0.4 [10] [7] [7] deposit (inside the polysilicon ring). The diffusion current 0.2 [10] [7] CMOS 65 nm flows inside the Nwell between the anode and the cathode. [7] 0 Moreover, the anode-to-cathode isolation is achieved with a 012345678910 polysilicon spacer in order to reduce the current resistive path. 2 Anode area (µm ) Nsinker implant enables to further reduce the series resistance Fig. 3. Schottky diodes cut-off frequency achieved with 55 nm BiCMOS value. Then, the cathode-substrate insulation is improved using process (this work) presented with state-of-the-art other diodes. deep trenches BiCMOS Deep Trenches Insulation (BDTI) module. III. SCALABLE ANALYTICAL MODEL DEVELOPMENT C. Measured 55 nm BiCMOS Schottky diode performances A. Proposed equivalent lumped model The main parameters which sets the performance of the In the aim to enable future circuit designs and identify Schottky diode are the series resistance Rs and the zero-bias possible improvements for the proposed Schottky diodes, it junction capacitance Cj0. For some applications, it could be seems meaningful to elaborate an analytical model describing useful to consider the barrier height Φb and the ideality factor η key electrical figure in function of device key technological and as well. The cut-off frequency of the diode is given by Eq. 1: layout parameters. We propose to use the circuit model presented Fig. 4 an assuming the three following hypotheses: 1 • The current circulation between the anode and the = (1) cathode fingers will be modelled by an average path 2 × × due to the distributed nature of the conductive path. Table 1. Comparison of Schottky Diode performances • The inductive contribution of the anode and the cathode A fingers will be neglected due to their small lengths and Ref. Rs (Ω) Cj0 (fF) Φb (V) η (µm²) their interdigitated configuration. • The doping value Nd inside the Nwell layer given by [7] 3.68 57 0.43 N.R. N.R. the TCAD report simulation is reliable and accurate. [6] 1.63 10 7 0.52 1.3

[9] 2.3 15 8.2 0.38 1.34 [10] 0.42 210 3 N.R. N.R.

[8] 4 13 14.3 N.R. N.R.

[13] 4 5.4 21 N.R. N.R (a) (b) This Fig. 4. (a) Schottky diode circuit model related to (b) side cut-view of the diode 2 39.9 2.34 0.65 1.16 work B. Series resistance modelling strategy

The series resistance Rs was estimated thanks to the Table 1 summarizes extracted parameters from the measured existing Design Rules Manual (DRM) of the BiCMOS 55 nm I-V curve of one of our typical achieved diode in ST 55 nm technology and the Schottky diodes layout drawing parameters. BiCMOS technology (This work). The junction capacitance Cj0 The Rs model is given by the following equations: has been de-embedded thanks to Technology Computer-Aided Design (TCAD) simulation (to assess doping) coupled with S ij = // + + + (2) parameter measurements in order to dissociate the capacitance

24 × × ×_ + Canode_N+ = × (13) = 2 ℎ 1 4 (3) __ ( + )×_ × The total parasitic capacitance Ctot (equation (8)) has two □_ □_ major contributors which are the junction capacitance Cj0 □_ × = (4) (equation (10)) and the back-end capacitance CBE (equation (9)). 2× □_ ×( +) Cj0 induces Schottky area, doping values, Schottky barrier and = (5) silicon material dependency. CBE can be split in three different × capacitances. The anode and the cathode fingers are very close □_ × = (6) and induce two capacitances given by the equations (11) and 2× 1 (12). The last equation (13) is due to the charges flowing under = × the anode finger in the N+ ring implanted for the cathode layer. _ + (7) Fig. 6 shows some width and thickness used to determine the □_ ×( + ) 2 total parasitic capacitance Ctot and highlight the fact that the anode-to-cathode capacitance is due to the metal (only first Rs equation (2) models the resistive path seen by the current metal layer) finger stack anode and cathode accesses. Moreover, in working configuration. This equation includes the weight of this cross section underlines that junction capacitance Cj is the back-end stack metallization of the anode (equation (3)) and defined by the anode area NiSi/Nwell doping interface cathode (equation (7)). Moreover, the resistive weight of the dimensions. current in the doping layers have been splintered in equations for Nwell (equation (5)) and N+ (equation (6)). Finally, we have chosen to include the silicide resistive value for the Schottky anode contact (equation (4)) and to neglect the contribution of the contacts and vias. Fig. 5 shows the equivalent current path of the series resistance inside the cross-section of the diode with some width and length used to determine each resistive contribution due to the series resistance Rs.

Fig. 6. Total capacitance circuit model

IV. SCALABLE MODEL EXPERIMENTAL VALIDATION

In this part, we will bring to highlight the agreement reached between the proposed model and experimental data for the series resistance (Fig. 7) and the parasitic capacitance (Fig. 8)

25 Area = 4 µm² ) ● Rs max. Ω 20 ● Rs typ. Fig. 5. Series resistance circuit model Rs ( 15 ● Rs min. X Rs meas. C. Parasitic capacitance modelling strategy 10 The total parasitic capacitance Ctot is composed of the sum 5 of the junction capacitance Cj and the back-end capacitance CBE estimated using the DRM of the 55 nm BiCMOS technology 0 and the Schottky diodes layout drawing parameters. The C 0246810 tot Nfing model is given by the following equations: Fig. 7. Series resistance analytical model versus extracted measurement = + (8) parameters. = + +_ (9) _ Concerning the measured series resistance, as illustrated in × × = × × × , (10) Fig. 7 , a good agreement with the predicted value from the 2 ×1− analytical model is obtained using worst-case process × ×( +2× +)×ℎ parameters. This worst case is induced by the variation of the Cacces = × (11) +2× +2× +__ square resistance of the Nell which is established in the DRM × × ×ℎ ×2× CA_K = (12) for several Nwell geometries (more or less aggressive). + + − − − 2 __ __ 2 __ Consequently, it is reasonable to assume that an acceptable

25 model accuracy can be achieved using some calibration on V. CONCLUSION corners lot which take account of process dispersion as it is State-of-the-art Schottky diodes with cut-off frequency of done for all other models integrated in ST Process Desing Kit ~1.7 THz have been achieved using an innovative BiCMOS (PDK). diode architecture combining aggressive 55 nm poly-gate 20 spacer and bipolar dedicated implantation to reduce parasitic Model Area = 4 µm² resistance. In addition, we proposed an analytical model Meas. demonstrating a reasonable agreement with experimental 15 Cbackend measurements validating its future integration in a design kit Ctot library. Those results pave the way for the design of high 10 Cj performance subharmonic mixers in BiCMOS technology in

Capacitance (fF) Capacitance order to develop highly integrated and low-cost receivers 5 targeting communication links at 300 GHz leveraging IEEE standard 802.15.3d-2017. 0

4.0Nfing 8.0 REFERENCES Fig. 8. Parasitic capacitance analytical model versus extracted measurement parameters [1] Cisco, “Mobile VNI Forecast,” 09 February 2017. [Online]. Available: https://www.cisco.com/c/en/us/solutions/service-provider/visual- Dealing with parasitic capacitance, the total capacitance Ctot networking-index-vni/vni-infographic.html. has been extracted from Sij parameters and the junction [2] VK Chinni and al., “Single-channel 100 Gbit/s transmission using III–V capacitance has been extracted using III.A hypothesis. While UTC-PDs for future IEEE 802.15. 3d wireless links in the 300 GHz band,” IET Electronics Letters, vol. 55, no. 10, pp. 638-640, 17 May using previous hypothesis, the extracted and modeled Cj0 values 2018. are by definition equivalent, we can see in Fig. 8 that predicted [3] E. Lacombe and al., “300 GHz OOK Transmitter Integrated in Advanced and extracted parasitic related to back-end-of-line are Silicon Photonics Technology and Achieving 20 Gb/s,” in IEEE Radio a good agreement. This confirms the validity of the chosen Frequency Integrated Circuits Symposium (RFIC), Philadelphia, hypothesis and the accuracy of the proposed methodology. PA,USA, 10-12 June 2018. Finally, the development of the analytical model of the [4] Paul Richard Wilkinson, “Development of 664GHz Sub-harmonic proposed Schottky diodes has enabled to identify which part of Mixers,” Thesis Report, April 2014. [Online]. Available: http://etheses.whiterose.ac.uk/8079/1/Thesis%201.31.pdf. the device is limiting the achievable performances. Fig. 9 [5] T. Crowe et al, “GaAs Schottky Barrier Diodes for Space Based shows that the major resistive contributor is the path in the Applications at Submillimeter Wavelengths,” in International Nwell layer and consequently this is where we have to put some Symposium on Space Terahertz Technology (ISSTT), Oxford and Didcot, efforts at the process or the layout level for further improvement UK, 23-25 March 2010. of the performances. [6] S. Sankaran and al., “Schottky Barrier Diodes for Millimeter Wave Detection in a Foundry CMOS Process,” IEEE Electron Device Letters, 24 Rnwell vol. 26, no. 7, pp. 492-492, July 2005. ) 88 % Ω 20 [7] M. K. Matters-Kammerer and al., “RF Characterization of Schottky 16 Diodes in 65-nm CMOS,” IEEE Transactions on Electron Device, vol. 12 Ranode // 57, no. 5, pp. 1063-1068, May 2010. Rn+ 8 Rsalicide Rcathode [8] U. R. Pferiffer and al, “Schottky barrier diode circuits in silicon for future 4 3% 5% 4 % millimeter-wave and terahertz applications,” IEEE Transactions on Resistance ( 0 Theory and Techniques (TMTT), vol. 56, no. 2, pp. 364-371, 4.0 Area (µm²) february 2008. Fig. 9. Impact of each resistive Rs contributors [9] Junyu Shi and al., “A CMOS Schottky Barrier Diode with the Four-Sided Cathode,” in International Conference on Integrated Circuits and The total capacitance Ctot is mainly dominated by the back- Microsystems (ICICM) , Chengdu, China, 23-25 November 2016. end-of-line capacitance CA_K. Some improvement could be [10] Suna Kim and al., “A New Resistance Model for a Schottky Barrier performed on the metal access spacing to reduce this anode-to- Diode in CMOS Including N-well Thickness Effect,” Journal of cathode parasitic capacitance. It is though more complicated to Semiconductor Technology and Science, vol. 13, no. 4, pp. 381-386, August 2013. optimize the junction capacitance Cj without having to introduce any specific implantation steps and so adding costs. [11] E. Seok and al, “Progress and Challenges Towards Terahertz CMOS Integrated Circuits,” IEEE Journal of Solid-State Circuits, vol. 45, no. 8, 10 % pp. 1554-1564, August 2010. [12] F. Stein and al, “Advanced Extraction Procedure for Parasitic Collector 8 CA_K Series Resistance Contributions in High-Speed BiCMOS Technologies,” Cj 6 in BiCMOS Circuits and Technology Meeting (BCTM), Bordeaux, % France, September 30 to October 3. 4 [13] V. Jain and al., “Schottky Barrier Diodes in 90nm SiGe BiCMOS,” in Caccess 2 Canode_N+ IEEE BiCMOS Circuits and Technology Meeting (BCTM), Bordeaux, France, September 30 to October 3.

Capacitance (fF) Capacitance % 0 %

4.0 Area (µm²) Fig. 10. Impact on the total capacitance Ctot of each parasitic capacitance

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